Communication control device

Abstract: Disclosed is a communication control device in which a clock frequency for processing communication data is the same as or lower than the transfer speed of the communication data without requiring specially complicated construction of the input-output portion (11) to the network so as to make it possible to realize low power consumption and easy design and manufacture of the device.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a network control device for receiving input data in the form of a train of serial bits from a communication network through a media interface in order to convert the input data into n-bit parallel signals by partitioning the serial bit train into respective successive n-bit signals in accordance with the order of reception and to generate clock signals in synchronism with the parallel signals, said network control device comprising: n shift registers for receiving the n parallel signals n being an integer greater than or equal to 2; n detection circuits connected to said n shift registers for detecting whether a bit pattern composed of parallel outputs from each of n shift registers agrees with a start delimiter which indicates a start point of a data item contained in said input data. A device of this kind is known from EP-A-0 249 935. Description of the Prior Art Recently, high-speed data transmission in a LAN (Local Area Network) has been studied. Particularly, the high-speed data transmisstion in the LAN by the so-called token ring method which is standardized in IEEE 802.5 is now noted. As communication data used in the token ring method, the so-called differential Manchester codes (DM codes) are used. In the system of the codes, a time interval which is required for transferring data as a unit of information is divided into two parts as shown in Fig.1. The signal level of the former half part of the time interval is compared with that of the latter half part of the previous time interval thereof, and the signal level of the latter half part of the time interval is compared with that of the former half part thereof. In Fig.1, four states of combination of inversion and non-inversion of the former half part and the latter half part of the time interval are shown with respect to each state (H level or L level) of the latter half part of the previous time interval. These states are called "J", "K", "1", "0" respectively as shown in Fig.1. In this case, when inversion is denoted by "1" and non-inversion is denoted by "0", the DM codes "J", "K", "1", "0" are expressed as "11", "01", "10", "00" respectively. These new codes respectively comprising combination of the two binary bits are called ER codes. Herein, the lower bit of each of the ER codes is called code violation bit, and the higher bit thereof is called data bit. In communication data in which each unit of information is serial as shown in Fig.1, no discriminating factor for showing a boundary between serial two units of information is included in each of the units. Therefore, it is very likely that two bits comprising the latter half part of the previous unit of information and the former half part of a unit of information are recognized to be one unit of information. To prevent this problem, a start code of data or a discrimination code of boundary expressed by "JKOJKOOO" comprising the DM codes is used as a start delimiter (SD), and the units of information starts from this code by two bits. For example, as shown in Fig.2, there is a terminal of a conventional LAN system based on the token ring method in which such DM codes are used. In Fig.2, a media interface 1 is mainly composed of an analog circuit, and regenerates reception data having some logic level from a weak input signal given by a network, and also extracts a reception clock signal overlapping in the input signal. The reception data regenerated by the media interface 1 are converted into reception information by a network control device 2 in synchronism with the reception clock signal extracted, then the reception information is given to a data processing device 3. Moreover, the data processing device 3 generates transmission information. Then, the transmission information is given to the network control device 2, and converted into transmission data thereby. The transmission data are further converted into an analog output signal by the media interface 1, thereafter the output signal is outputted to the network, and transmitted therefrom. In such construction, the communication data are transferred on the network as bits arranged in series, and transmitted or received through the media interface 1. Therefore, between the media interface 1 and the network control device 2, the transmission data or the reception data are serially transferred by one bit thro,ugh a transmission data line 4 or a reception data line 5. Moreover, through another reception clock line 6, the reception clock signal is given to the network control device 2 from the media interface 1. Accordingly, one unit of information of transmission data expressed by the DM code as described above is processed as the ER code comprising two bits, and the ER code is serially transferred by one bit through the transmission data line 4 or the reception data line 5 so as to be processed by one bit. Namely, the transmission data or the reception data must be recognized and processed by the media interface 1 and the network control device 2 not by one DM code but by one bit. However, the reception signal must have a frequency which is synchronous to one bit and is twice as high as the transfer speed of one unit of information. As mentioned above, in the conventional LAN system based on the token ring method in which the DM code is used, it is necessary that the clock signal has a frequency twice as high as the transfer speed of communication data. Therefore, when the transfer speed of the communication data becomes higher, a circuit included in the system for generating the clock signal must generate a clock signal having a higher frequency, so that the circuit must be operated at a higher speed. However, when the operation speed becomes high, the power consumption is inevitably increased. Moreover, by the increase of power consumption, a large-scale power source and system construction capable of heat radiation must be required. Accordingly, it is difficult to realize a small-scale system by the conventional method. Moreover, to realize the high-speed operation, it is necessary to compose the circuit more finely. Moreover, the delay time on transmitting signals must be more reduced. As the result, the circuit design and layout design for the communication control device and the manufacture thereof become very difficult. SUMMARY OF THE INVENTION The present invention was invented in the light of these problems of the prior art, therefore it is an object thereof to provide a communication control device in which a clock frequency for processing communication data is the same as or lower than the transfer speed of the communication data without requiring specially complicated construction of the input-output portion to the network so as to make it possible to realize low power consumption and easy design and manufacture. To achieve the object, the present invention is characterized by n selector circuits each connected between two consecutive stages of said n shift registers) and each for selecting one of said n parallel signals and outputting it to the respective stage of said n shift registers; a mode judgement circuit connected to the outputs of the n detection circuits for determining an operating mode of said selector circuits; a mode information holding circuit for holding a mode information indicative of the operating mode of said selector circuits determined by said mode judgement circuit; and a counter circuit for generating signals partitioning m-bit data by dividing said clock signals, m being an integer greater than or equal to 2; said mode judgement circuit determining anew the operating mode of said selector circuits in accordance with the mode information held in said mode information holding circuit and the output of one of said n detection circuits which detects that the bit pattern of the said shift register matches said start delimiter, said selector circuits performing shift input operation to said shift registers by aligning the parallel bits in accordance with the operating mode determined by said mode judgement circuit. In this construction, the communication data composed of a serial row of bits from the communication network are converted into data composed of parallel rows of a plurality of bits, and the data composed of parallel rows of a plurality of bits are taken in and held in accordance with the reception clock signal which is synchronous to the data composed of parallel rows of a plurality of bits, then the plurality of units of the data composed of parallel rows of a plurality of bits held are compared with the data start discriminating information so as to discriminate start of data, thereafter data to be processed by the network control device 2 are extracted and selected. Accordingly, the frequency of the reception clock signal as a timing for carrying out process of the communication data can be reduced as compared with that of the prior art by converting the serial data into the data composed of parallel rows of a predetermined number of bits. These and other objects, features and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a diagram to show forms of communication data in an LAN system; Fig.2 is a diagram to show construction of a main part in a conventional LAN system; Fig.3 is a diagram to show construction of a communication system in which a communication control device is used; Figs.4, 5, 7 and 9 are diagrams to respectively show fundamental construction of a main part in the device shown in Fig.3; Fig.6 is a diagram to explain operation of an alignment circuit shown in Fig.3; Fig.8 is a diagram to explain operation of circuits shown in Figs.5 and 7; Figs.10 and 11 are diagrams to explain operation of the device shown in Fig.3; Fig.12 is a diagram to show construction of a main part related to another embodiment; Fig.13 is a diagram to show construction of an alignment circuit related to an embodiment of the present invention; Figs.14 and 16 are diagrams to show a main part of the circuit shown in Fig.13; Fig.15 is a diagram to explain operation of the main part shown in Fig.13; Figs.17 through 20 are diagrams to explain operation of the circuit shown in Fig.13. DETAILED DESCRIPTION OF THE EMBODIMENTS Fig.3 is a diagram to show construction of a system in which a communication control device is used. The embodiment shown in the same drawing is a system in which communication data are transmitted and received between a network and a data processing device 3 through a media interface 11 and a network control device 12 in the same manner as shown in the prior art. This embodiment is characterized in that the ER code as one unit of information composing communication data comprises two bits to be transmitted or received parallel to each other between the media interface 11 and the network control device 12, and the start delimiter is detected in the network control device 12. Incidentally, in Fig.3, parts or portions designated by the same reference numerals or characters have the same functions respectively as those shown in Fig.2, thus the explanation on them is omitted. In Fig.3, the media interface 11 is arranged between the network and the network control device 12 (hereinafter, it is called NC device). The media interface 11 has a reception data regeneration circuit 7 for converting a weak network input signal from the network into data comprising DM codes of a logic level, a DM/ER converting circuit 8 for decoding the data comprising DM codes from the reception data regeneration circuit 7 and forming serial data comprising ER codes each of which is composed of two bits, and a parallelizing circuit 9 for parallelizing the serial data comprising ER codes to form parallelized reception data. Accordingly, the DM codes composing the input signal given from the network are decoded and converted into the serial ER codes each of which comprises two bits. Then, the serial ER codes are parallelized by two bits comprising a higher bit X0 and a lower bit X1 to form the parallelized reception data, thereafter the resultant parallelized reception data are transmitted from the media interface 11 to the NC device 12. Moreover, the media interface 11 has a clock extracting circuit 10 which extracts a clock signal overlapping on the network input signal and generates a serial clock (which corresponds to the reception clock signal of the prior art shown in Fig.2) synchronous to the serial data of the ER codes from the DM/ER converting circuit 8, and a reception clock generating circuit 26 for generating a reception clock signal synchronous to the parallelized reception data from the parallelizing circuit 9 in accordance with the serial clock from the clock extracting circuit 10. Accordingly, since it becomes possible to carry out reception of one DM codes every one clock due to the reception data parallelized by two bits, the frequency of the reception clock signal is the same as that of the DM code. Namely, the frequency of the reception clock signal outputted from the media interface 11 of this embodiment is a half of that of the reception clock signal outputted from the media interface 1 to the NC device 2 in the prior art shown in Fig.2. Additionally, the media interface 11 has transmitting means 27 for converting parallelized transmission data comprising the ER codes each of which is composed of two bits given from the NC device 12 into the DM codes, and transmitting the DM codes as a network output signal to the network. For example, the parallelizing circuit 9 and the reception clock generating circuit 26 of the media interface 11 are a two-bit shift register 9 and an 1/2 divider 26 respectively as shown in Fig.4. The NC device 12 controls the input-output of data between the media interface 11 and the data processing device 3, and has an alignment circuit 13, a transmitting circuit 14 and a transmission-reception control circuit 15. The alignment circuit 13 receives the parallelized reception data and the reception clock signal from the media interface 11, and detects start delimiter (SD) from the parallelized reception data in synchronism with the reception clock signal. Moreover, the alignment circuit 13 gives the ER codes aligned after the SD to the transmitting circuit 14, further obtains reception data comprising eight units of information each unit of which is corresponding to one ER code of two bits, and gives the reception data to the transmission-reception control circuit 15. Moreover the alignment circuit 13 generates a detection timing signal of SD and a timing signal for showing boundaries of the reception data, and gives these signals to the transmission-reception control circuit 15. These operations of the alignment circuit 13 are carried out in synchronism with the reception clock signal given from the media interface 11. The transmitting circuit 14 converts the transmission data given from the transmission-reception control circuit 15 into the ER codes, and transmits either of the ER codes converted and the ER codes given from the alignment circuit 13 to the media interface 11 in accordance with a control signal given from the transmission-reception control circuit 15. The transmission-reception control circuit 15 extracts reception information to be given from a reception frame comprising reception data given from the alignment circuit 13 to the data processing device 3, and composes a transmission frame with transmission information given from the data processing device 3, further carries out the so-called protocol procedure to control operations of the alignment circuit 13 and the transmitting circuit 14. Next, concrete construction of the alignment circuit 13 for detecting SD and obtaining the reception data from the parallelized reception data comprising the ER codes in accordance with the reception clock signal which has the same frequency as that of the DM codes will be explained with reference to Fig.5. In Fig.5, the alignment circuit 13 has an eight-bit shift register 16 and a nine-bit shift register 17 respectively comprising cascade connection of D-type flip-flops (F/F). The eight-bit shift register 16 shifts the higher bits X0 of the parallelized reception data given from the media interface 11 successively in synchronism with the reception clock signal. While, the nine-bit shift register 17 shifts the lower bits X1 of the parallelized reception data successively in synchronism with the reception clock signal. In this case, the higher bits X0 are received prior to the lower bits X1. Since the data to be given to the shift registers 16, 17 as the parallelized reception data are the lower bits X1 and the higher bits X0 respectively parallelized by two bits, for example, when the SD pattern of "JKOJKOOO" (which is designated as "1101001101000000" by the ER codes) is given to the shift registers 16, 17, as schematically shown in Fig.6, these two kinds of bits are held in two ways, that is, a first and a second alignment mode. Accordingly, means for discriminating and selecting either of the two alignment mode is required. Then, returning to Fig.5, the discriminating and selecting means is described. Of outputs (Y1, Y3, Y5, Y7, Y9, Y11, Y13, Y15) in respective stages of the shift register 16 and outputs (Y0, Y2, Y4, Y6, Y8, Y10, Y12, Y14, Y16) in the respective stages of the shift register 17, the shift registers 16, 17 give the outputs Y0 through Y15 to an SD detecting circuit 18 and the outputs Y1 through Y16 to an SD detecting circuit 19. The SD detecting circuits 18, 19 detect SD from the parallelized reception data successively given by the media interface 11 by comparing the outputs of 16 bits given from the shift registers 16, 17 with the SD pattern designated as "JKOJKOOO" by the DM codes. When SD is detected from the result of the comparison, the SD detecting circuits 18, 19 output SD detection signals A, B respectively. When the parallelized reception data given from the media interface are in the same cycle as that of the reception clock signal and express correct DM codes, or in case of the first mode shown in Fig.6, the SD detecting circuit 19 detects SD and outputs and SD detection signal B to an OR gate 20. While, when the reception data of ER codes given from the media interface 11 bestride different cycles of the reception clock signal, and correct DM codes can not be given as X0, X1 to the shift registers at the same time, or in case of the second mode shown in Fig.6, the SD detecting circuit 18 detects SD and outputs the SD detection signal A to the OR gate 20. The OR gate 20 detects that either of the SD detecting circuit 18 and 19 detects SD, and gives an SD detection timing (SDDET) signal to an F/F 21, a counter 22 and the transmission-reception control circuit 15. When SD is detected and the SDDET signal of the level "1" is given, the F/F 21 takes in the SD detection signal B and gives it as an alignment mode (MODE) signal to selector circuits 23. The selector circuits 23 select correct ER codes each of which is one unit of information from the parallelized reception data shifted and held in the shift registers 16, 17, and align them. As shown in Figs.5 and 7, the selector circuits 23 are provided correspondingly to bits in the data portions (DT0 to DT7) and the code violation portions (CV0 to CV7) of the ER codes composing the reception data, and generate the reception data comprising eight units of information. The respective selector circuits 23 select the outputs corresponding to the respective stages of the shift registers 16, 17 in accordance with a value of the MODE signal as shown in Fig.8 to obtain an aligned ER code. The selector 23, for example as shown in Fig.9, can be composed by combination of OR gates. The counter 22 is a three-bit binary counter, and carries out counting operation in synchronism with the reception clock signal. In this case, a count value obtained by the counter 22 is cleared by the SDDET signal of the level "1". Namely, the count value of the counter 22 becomes "000" when the SD is detected, and is increased in synchronism with the reception clock signal after then. Accordingly, the count value indicates a timing of a unit of information composing the reception data, which follows SD. Therefore, the count value of "111" indicates the (8 × n)th clock (n = 1, 2, ··· ) from the detection of SD. As the result, the boundaries of the reception data which exist every eight units of information can be indicated. Next, the operation of this embodiment is explained with reference to Figs.10 and 11. First, the case in which the parallelized reception data inputted at the same time to the alignment circuit 13 of the NC device 12 from the media interface 11 show correct ER codes of the reception data, or the first mode is described with reference to Fig.10. The input signal given to the media interface 11 from the network is converted from the DM codes into the ER codes by the media interface 11, then is given to the alignment circuit 13 of the NC device 12 as the parallelized reception data in synchronism with the reception clock signal extracted from the input signal. Then, the higher bits X0 of the parallelized reception data successively given to the alignment circuit 13 are successively shifted and held by the shift register 16, and the lower bits X1 of the parallelized reception data are succcessively shifted and held by the shift register 17. These bits of the parallelized reception data respectively held by the shift registers 16, 17 are given to the SD detecting circuits 18, 19 correspondingly. In this case, since the ER codes obtained by conversion of the SD pattern are given in synchronism with the reception clock signal as shown in Fig.10, the SD pattern given to the input signal is given to the SD detecting circuit 19 as the respective outputs of Y1 to Y16 of the shift registers 16, 17. As the result, the SD given to the input signal is detected by the SD detecting circuit 19, and the level of the SD detection signal B becomes "1". Then, the SD detection signal B is taken in the F/F 21 in synchronism with the reception clock signal and the level of the SDDET becomes "1". As the result, the MODE signal as the output from the F/F 21 becomes the level "1", and is given to the respective selector circuits 23. Thereby, the respective selector circuits 23 select the outputs in the respective stages of the shift registers 16, 17 as shown in Fig.8. While, the SDDET signal is given to the counter 22, and the position of a unit of information of the parallelized reception data following the SD is counted. Then, the count value is outputed as a timing signal as shown in Fig.10. Then, the parallelized reception data following SD are shifted and held in the shaft registers 16, 17 correspondingly in synchronism with the reception clock signal, and when the count value of the counter 22 reaches "111", first reception data comprising eight units of information following the SD are obtained as shown in Fig.10 as the aligned ER codes which are outputs of the respective selector circuits 23. Also after the first reception data, the reception data when the count value is "111" are obtained as outputs of the selector circuits 23. Next, the case in which the parallelized reception data inputted at the same time to the alignment circuit 13 of the NC device 12 from the media interface 11 show incorrect ER codes of the reception data, or the case in which the ER codes shift from the reception clock signal by a half cycle so that the correct ER codes bestride serial different cycles of the reception clock signals, that is, the second mode is described with reference to Fig.11. In this case, since the correct ER codes of reception data can not be given at the same time to the corresponding shift registers 16, 17 as the parallelized reception data, the SD pattern which is given to the input signal and is taken and held in the respective shift registers 16, 17 in synchronism with the reception clock signal is obtained as the outputs Y0 to Y15 of the respective shift registers 16, 17 as shown in Fig.11. As the result, the SD is detected by the SD detecting circuit 18, and the level of the SD detection signal A becomes "1", and also the level of the SDDET signal becomes "1". Accordingly, the SD detection signal B of the level "0" is given to the input of the F/F 21, and the level of the MODE signal becomes "0". When the level of the MODE signal becomes "0", the respective selector circuits 23 select the outputs in the respective stages of the shift registers 16, 17 as shown in Fig.8, and as described above, whenever the count value of the counter 22 is "111", the reception data comprising eight units of information of correct ER codes following the SD can be obtained. As stated above, according to this embodiment, it becomes possible to extract the reception data correctly from the input signal not by the clock signal having a frequency which is twice as high as the transfer speed of the signal transferred on the network but by the clock signal having the same frequency as the transfer speed. For example, in a network having a signal speed of 16Mbits/sec, a reception clock signal of 32MHz is required in the prior art. However, in this embodiment, it is possible to obtain correct reception data even by a reception clock signal of 16MHz. Accordingly, since the frequency of the operational clock of the NC device 12 can be reduced into a half of that in the prior art, it becomes unnecessary to operate the internal circuits at a high speed. Thereby, the power consumption can be cut down and the capacity of the power source can be reduced, so that it becomes possibe to realize a small-scale communication control device. Moreover, it becomes unnecessary to consider the fine processing of circuits and delay of signal transmission so much. As the result, the circuit design and layout design can be easily carried out. Next, another embodiment of the present invention is described. Fig.12 is a diagram to show construction of an alignment circuit related to another embodiment. A feature of this embodiment is in that a media interface does not parallelize ER codes extracted from an input signal given from a network, and an alignment circuit in an NC device carries out it. Therefore, in this embodiment, the media interface does not have a parallelizing circuit 9 as shown in Fig.3, and the NC device includes F/F 33, 34 for the parallelization instead. Namely, in Fig.12, the ER codes which are converted from DM codes as the input signal by the media interface are serially operated in synchronism with a reception clock signal having a frequency which is twice as high as the input signal composing respective first steps of shift registers 31, 32, and successively shifted in the F/F 33, 34 whose outputs are Y16, Y15 respectively. Thereby, the ER codes which are parallelized and held in the F/F 33, 34 are shifted and held in shift registers 31, 32 correspondingly in synchronism with the reception clock signal divided into two halves by a divider 35, so as to detect SD in the same manner as in the previous embodiment. While, the aligned ER codes are serialized by a selector circuit 36 in accordance with a transmission clock, and given to the media interface as transmission data. Incidentally, in Fig.12, parts or portions designated by the same reference numerals or characters have the same functions respectively as in Fig.5, thus the explanation on them is omitted here. In such construction, since the ER codes which are transmitted or received between the media interface and the NC device are serially transferred, it is possible to reduce the number of signal lines. And, it is possible to delete a difficulty of forming a logic circuit into the media interface comprising analog circuits. Next, an embodiment of the present invention is explained. Fig.13 is a diagram to show construction of an alignment circuit 13 related to this embodiment. In Fig.13, shift registers 40, 41 are composed by respectively inserting selector circuits 42, 43 between F/F of the first and the second stages of the shift registers 16, 17 shown in Fig.5. The selector circuit 42 selects output Y15 of an F/F when the level of a SELECT signal is "1", or selects output Y16 of an F/F when the level of the SELECT signal is "0", then gives the output Y15′ to an F/F of the next stage whose output is Y13. While, the selector circuit 43 selects output Y16 of the F/F when the level of the SELECT signal is "1", or selects parallelized reception data X0 when the level of the SELECT signal is "0", then gives the output Y16′ to an F/F of the next stage whose output is Y14. While, SD detecting circuits 44, 45 detect coincidence between the respective outputs of the shift registers 40, 41 and the SD pattern in the same manner as the SD detecting circuits 18, 19, and are respectively constructed as shown in Fig.14. In Fig.14, the SD detecting circuit 44 uses the output Y15 of the F/F selected by the selector circuit 46 as the lowest bit (which judges "0") of the SD pattern when the level of a MODE signal is "1", and uses the output Y16 of the F/F selected by the selector circuit 46 as such when the level of the MODE signal is "0". While, the SD detecting circuit 45 uses the outputs Y15, Y16 of the F/F selected by the selector circuits 47, 48 as the secondly lowest bit of the SD pattern when the level of the MODE signal is "1", and uses the output Y16 of the F/F and the parallelized data X0 selected by the selector circuits 47, 48 as such when the level of the MODE signal is "0". Returning to Fig.13, a MODE judging circuit 49 gives its result of judgement to an F/F 51 and a selector circuit 52 in accordance with an SD detection signal A and an SD detection signal B when the SD is detected, and the MODE signal previous to the SD detection, then gives an initial value of a timing signal to a counter 53. The MODE judging circuit 49, as shown in Fig.15, judges the result of judgement and the initial value of the positional signal. For example, as shown in Fig.15, the MODE judging circuit 49 judges the level of the result of judgement to be "0" when the level of the MODE signal before the SD is detected is "1" and the level of the SD detection signal A is "1" when the SD is detected, and decides the initial value of the timing signal to be "001" in the binary expression. The F/F 51 takes in and holds the result of judgement of the MODE judging circuit 49 when the SD is detected and the SDDET signal is given from the OR gate, then outputs the result of judgement to the MODE judging circuit 49 and the selector circuit 46, 48, 52, 54, 55 as the MODE signal. The selector circuit 52 selects the MODE signal or the result of judgement outputted from the MODE judging circuit 49 in accordance with the SDDET signal, and gives it to the selector circuits 42, 43. The selector circuit 52 selects the result of judgement when the level of the SDDET signal is "1", and selects the MODE signal when the level is "0". The counter 53 functions in the same manner as the counter 22 shown in Fig.5, but differs from the counter 22 in that the initial value of the timing signal outputted from the MODE judging circuit 49 is set when the level of the SDDET signal is "1". From the outputs Y1 to Y16 and the parallelized reception data X0 of the respective shift registers 40, 41 obtained by such construction, as shown in Fig.16, reception data (DT0 to DT7 in the data portion, CV0 to CV7 in the code violation portion) are obtained. In Fig.16, the reception data DT1 to DT7 and CV1 to CV7 are directly corresponding to the outputs Y1 to Y14 of the F/F. While, with respect to the reception data CV0, the output Y16 of the F/F is correspondingly selected by the selector circuit 54 when the level of the MODE signal is "1", and the parallelized reception data X0 is correspondingly selected by the selector circuit 54 when the level is "0". Moreover, with respect to the reception data DT0, the output Y15 of the F/F is correspondingly selected by the selector circuit 55 when the level of the MODE signal is "1", and the output Y16 of the F/F is correspondingly selected by the selector circuit 55 when the level is "0". Next, the alignment circuit shown in Fig.13 is explained with reference to Figs.17 through 20. Fig.17 shows the operation when the MODE signal is "1" and the reception clock signal and the ER codes are matched with each other. Since the MODE signal is "1", the shift registers 40, 41 shift the outputs from Y15, Y16 to Y13, Y14 directly, and output them to the Y0 to Y16. At the time, the SD pattern is detected in the Y1 to Y16, and the level "1" is outputted to the SD detection signal B. The MODE judging circuit 49 outputs a new MODE signal "1" as the result of judgement as shown in Fig.15, and also outputs "000" as the initial value of the timing signal. Since the new MODE signal is also "1", the SELECT signal remains "1". Therefore, the aligned ER codes are outputted correspondingly to the outputs Y1 to Y16, and can be taken out as the first reception data when the timing signal is "111". Fig.18 shows a case in which the reception clock signal and the ER codes shift from each other when the MODE signal is "1". Since the MODE signal is "1", the shift registers 40, 41 shift the outputs from Y15, Y16 to Y13, Y14 directly, and outputs them to Y0 to Y16. At the time, the SD pattern is detected in the outputs Y0 to Y15, and the level "1" is outputted to the SD detection signal A. The MODE judging circuit 49 outputs a new MODE signal "0" as the result of judgement as shown in Fig.15, and also outputs "001" as the initial value of the positional signal. Since the new MODE signal is "0", the SELECT signal changes into "0" immediately, then the selector circuits 42, 43 operate so that the Y13 shifts into the value of the output Y16, and the Y14 shifts into the value of the data X0. Accordingly, the aligned ER codes are outputted correspondingly to the outputs Y1 to Y14, Y16 and the data X0. Since the reception data DT0 and CV0 are selected so that the output Y16 and the data X0 are outputted respectively, they can be taken out as the first reception data when the positional signal is "111". Fig.19 shows a case in which the reception clock signal and the ER codes shift from each other when the MODE signal is "0". Since the MODE signal is "0", the shift registers 40, 41 shift the outputs from Y16, X0 to Y13, Y14 directly, and outputs them to Y0 to Y16. At the time, the SD pattern is detected in the outputs Y1 to Y14, Y16 and the data X0. However, since the SD detecting circuit 45 detects coincidence of the SD pattern when the MODE signal is "0", the level "1" is outputted to the SD detection signal B. Then, the MODE judging circuit 49 outputs a new MODE singal "0" as the result of judgement as shown in Fig.15, and also outputs "000" as the initial value of the timing signal. Since the new MODE signal is also "0", the SELECT signal remains "0", and the selector circuits 42, 43 operate so that the output Y13 shifts into the value of the output Y16 and the output Y14 shifts into the value of the data X0. Accordingly, the aligned ER codes are outputted to the outputs Y1 to Y14, Y16 and the data X0. Therefore, since the reception data DT0 and CV0 are selected so that the output Y16 and the data X0 are outputted respectively, they can be taken out as the first reception data when the positional signal is "111". Fig.20 shows a case in which the reception clock signal and the ER codes are matched with each other when the MODE signal is "0". Since the MODE signal is "0", the shift registers 40, 41 shift the outputs from Y16, X0 to Y13, Y14 directly, and outputs them to Y0 to Y16. At the time, the SD pattern is detected in the outputs Y0, Y14, Y16. However, since the SD detecting circuit 44 detects coincidence of the SD pattern when the MODE signal is "0", the level "1" is outputted to the SD detection signal A. Then, the MODE judging circuit 49 outputs a new MODE singnal "1" as the result of judgement as shown in Fig.15, and also outputs "000" as the initial value of the timing signal. Since the new MODE signal is "1", the SELECT signal changes into "1" immediately, and the shift registers 40, 41 take in the data X0, X1 directly. As the result, the aligned ER codes are outputted to the outputs Y1 to Y16, and they can be taken out as the first reception data when the timing signal is "111". As stated above, in this embodiment, since the selector circuits are provided in the reception data holding portion composed of the shift registers, the number of the selector circuits can be further reduced as compared with the previous embodiment. Moreover, since the MODE signal is outputted to the SELECT signal when the SD is not detected, the selector circuits 54, 55 for preparing the aligned ER codes are equivalent to the selector circuits 42, 43 in the shift registers 40, 41. Namely, if the aligned ER codes are not used just when the SD is detected, the alignment circuits 54, 55 can be replaced by the alignment circuits 40, 41. This replacement can be carried out by outputting Y15 as DT0 and Y16 as CV0. In case of such construction, the number of the selector circuits required at six including those included in the SD detecting circuits 44, 45. Accordingly, as compared with the sixteen selector circuits required for the previous embodiment, this embodiment can be realized by a far small number of hardwares. Incidentally, it should be clearly understood that this invention is not limited to the above embodiments. For example, it is possible that the parallelized reception data are composed of units of N bits. In such a case, it is necessary to prepare shift registers, SD detecting circuits and selector circuits of N inputs for the parallelized reception data composed of the N-bit units, and generate a MODE signal so that the N-input selector circuits can select suitable outputs from respective stages of the shift registers. For example, in case of a signal speed of 100Mbits/sec, if the media interface outputs parallelized reception data of 8 bits and a reception clock signal of 25MHz, it is possible to construct the alignment circuits in the NC device using eight shift registers and SD detecting circuits and sixteen 8-input selector circuits. In summary, according to the present invention, since the communication data given as a serial row of bits are parallelized to form parallelized data, and desired data are selected and extracted from the communication data in synchronism with the parallelized data, it becomes possible to carry out the operational process on or after the parallelization of the communication data in synchronism with a clock signal of a frequency which is the same as or lower than the transfer speed of the communication data. As the result, a communication control device of low power consumption and easy design and manufacture can be provided without making construction of the input-output portion thereof to a network complicated. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope of the appended Claim.

Claims: A network control device (12) for receiving input data in the form of a train of serial bits from a communication network through a media interface (11) in order to convert the input data into n-bit parallel signals, n being an integer greater than or equal to 2, by partitioning the serial bit train into respective successive n-bit signals (X₀, X₁) in accordance with the order of reception and to generate clock signals in synchronism with the parallel signals, said network control device comprising: n shift registers (40, 41) for receiving the n parallel signals (X₀, X₁); n detection circuits (44, 45) connected to said n shift registers (40, 41) for detecting whether a bit pattern composed of parallel outputs from each of said n shift registers (40, 41) agrees with a start delimiter (SD) which indicates a start point of a data item contained in said input data; characterized by n selector circuits (42, 43) each connected between two consecutive stages of said n shift registers (40, 41) and each for selecting one of said n parallel signals (X₀, X₁) and outputting it to the respective stage of said n shift registers (40, 41); a mode judgement circuit (49) connected to the outputs of the n detection circuits for determining an operating mode of said selector circuits (42, 43); a mode information holding circuit (51) for holding a mode information indicative of the operating mode of said selector circuits (42, 43) determined by said mode judgement circuit (49); and a counter circuit (53) for generating signals partitioning m-bit data by dividing said clock signals, m being an integer greater than or equal to 2; said mode judgement circuit (49) determining anew the operating mode of said selector circuits (42, 43) in accordance with the mode information held in said mode information holding circuit (51) and the output of one of said n detection circuits (44, 45) which detects that the bit pattern of the said shift register matches said start delimiter, said selector circuits (42, 43) performing shift input operation to said shift registers (40, 41) by aligning the parallel bits in accordance with the operating mode determined by said mode judgement circuit (49).

Inventors: TANAKA KOICHI, TANAKA, KOICHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H04L25
IPC codes: H04L25