Double-diffused drain CMOS process using a counterdoping technique

Abstract: The present process comprises the use of a blanket phosphorus (n-) implant coupled with a masked boron (p+) implant to permit the elimination of the conventional n+ implant and the LDD masks. The use of the blanket n- implant and the masked p+ implant allows production of an n- drain region which reduces hot-electron-induced degradation and a low concentration S/D region which is subsequently more easily counterdoped by a high concentration implant. A shallow blanket n+ implant is included prior to the P+ mask step to prevent contact resistance problems. Thereafter in the process of this invention, a salicide is formed at the sources and drains to produce a low sheet resistance in the contacts of the n-channel devices, notwithstanding the absence of the conventional thick n+ layer.

Description: The invention herein relates to the production of CMOS devices. More particularly it relates to a method for production of CMOS devices in which certain masks can be eliminated. A significant limiting factor in current n-channel MOSFETs is hot-electron-induced degradation, because of high channel electric fields and electron impact ionization rates in the micron and sub-micron n-channel devices. In hot electron injection, electrons are injected into the gate oxide by the high electric field created by the short channel region adjacent to the drain. As a result, the threshold voltage of the device is altered. In addition, overlap between the gate electrode and the source and drain results in parasitic capacitance between the diffusion region and the gate. This phenomenon, called Miller capacitance, decreases device speed. "Lightly doped drain" (LDD) and "double diffused drain" (DDD) structures have been developed to minimize this degradation. Both of these structures are based on the theory that if there is a lightly doped n-surface layer adjacent to the channel, the peak electric field will be reduced and shifted from under the gate so that hot electron-induced degradation will be lessened. However, both pose other types of problems. Production of LDD structures requires the use of an additional mask to prevent LDD phosphorus from implanting into p-channel regions. In both the LDD and DDD structures one must construct a highly doped n+ region to produce low contact resistance at the n-channel source and drain for high-speed circuits. The production of CMOS (complementary metal-oxide semiconductor) devices requires about eleven masks to produce the sequential layers of oxides, active areas and contacts which form the device. Each step in the device production generally involves a separate mask, except where "blanket" implant and oxidations can be effected. Each mask which must be used adds to the cost and time required to produce the device. Not only is expense incurred in the masking step itself, but the additional handling required for each mask step increases the possibility of defects, resulting in lower yields. The requirement of added mask steps to reduce hot electron effects has provided greater incentive to find other steps for which masks may be eliminated. Prior research has been directed to techniques for eliminating masks whenever possible or to replace complex mask steps with simpler ones. One technique described involves a source/drain (S/D) counterdoping step to eliminate the S/D implant mask, in which a blanket implant of boron (p+) was followed by a masked phosphorus (n+) implant to counterdope the boron existing in the n+ source and drain regions. This, however, has required excessive quantities of phosphorus to be used to insure complete counterdoping of the boron. The document International Electon Devices Meeting, Los Angeles, CA, 7th-10th December 1986, pages 256-259, IEEE, New York, US; M.-L. Chen et al.: "A high performance submicron CMOS process with self-aligned chan-stop and punch-through implants (Twin-Tub V)" discloses a method for manufacturing a double-diffused drain CMOS device. This method comprises in sequence the following steps: N-well patterning, N-well phosphorous and arsenic implantation, N-well oxidation, a first P-well boron implantation, a well drive-in step, a second P-well boron implantation, stripping of the N-well oxide, depositing thin oxide and patterning thereof, high-pressure field oxidation, a blanket threshold adjustment implantation, gate oxidation, definition of N+ poly gates, blanket N phosphorous implantation, selective P (BF₂) implantation, forming sidewall spacers, selective N+ arsenic implantation, selective P+ (BF₂) implantation, dopant activation by a thermal treatment, and self-aligning silicidation. Document EP-A-0 183 032 discloses a high density CMOS integrated circuit manufacturing process. The process comprises the steps of implanting N impurity into a selected area of a face of a P type silicon body to create an N-well area and growing a first oxide over said N-well area, implanting P impurity into said face using said first oxide as a mask to create a P-well area and subjecting said body to heat treatment to drive both said N-well and P-well into said face, forming an oxidation mask over said face and opening a hole in said mask within said P-well area, then etching a recess into the silicon of said face in said hole, oxidizing said silicon in said recess to create a field oxide isolation area extending into said face, the field oxide having a top surface about level with said face, applying a layer of conductive material on said face and patterning said laver to leave gate layers on said N-well and P-well areas, implanting N+ impurity into both the N-well and P-well areas to create N+ source/drain for an N-channel transistor in the P-well area, using said gate layers as a mask, implanting P+ impurity into only the N-well area, using the gate layer and a photoresist coating as a mask, to create P+ source/drain regions in the N-well area, at a concentration which is much higher than that in said N+ regions. Prior to said last-mentioned implanting steps sidewall spacers are formed in said gate layers. On the source/drain regions a silicide is formed and also on the gate layers which comprise polycrystalline silicon. Document EP-A-0 166 167 discloses a process for fabricating a semiconductor device having N-channel and P-channel MISFETS. In this method only one selective P+ implanting step after the forming of sidewall spacers is provided. It would therefore be advantageous to have a method for production of CMOS devices which would allow for elimination of masking steps while still providing a means of reducing hot-electron effects. It would also be advantageous for such method to permit elimination of an n+ layer without increasing the n-channel S/D contact resistance. It is to this end that the present invention is directed as set forth in claim 1. Preferably, the process comprises the use of a blanket phosphorus (n-) implant coupled with a masked boron (p+) implant to permit the elimination of the conventional n+ implant and the LDD masks. The use of the blanket n- implant and the masked p+ implant allows production of an n- drain region which reduces hot-electron-induced degradation and a low concentration S/D region which is subsequently more easily counterdoped by a high concentration implant. A shallow blanket n+ implant is included prior to the p+ mask step to prevent contact resistance problems. Thereafter in the process of this invention, a silicide is formed at the sources and drains to produce a low sheet resistance in the contacts of the n-channel devices, notwithstanding the absence of the conventional thick n+ layer. After completion of a standard CMOS self-aligned gate process through formation of the gate structures, sequential low-energy blanket implants of n-type dopants are performed. A low dosage implant of a first n-type dopant is completed before formation of spacers adjacent to exposed edges of the gate structures. After formation of the spacers, a high dosage implant of a second n-type dopant is performed. A high energy, high dosage implant of p-type dopant is performed into p-channel regions exposed by a p+ mask of photoresist which creates the source/drain regions of the p-channel devices by counterdoping the prior n-type blanket implants. A silicide is formed in the active areas to provide low contact resistance. The single Figure 1 of the drawing is a flow diagram illustrating the sequence of steps 1A trhough 1L in the production process of the present invention. The process of this invention can be best understood by reference to the Figure. The process for fabrication of self-aligned MOS devices is well known to those skilled in the art. Therefore, the process steps prior to the description of the present invention will not be detailed, but are merely included to complete the process flow. The proposed process incorporates several novel steps which markedly improve the ease of production while yielding a CMOS device which has operating characteristics equivalent to or better than devices made by conventional processes. The present process starts with a p-type substrate 2 as illustrated in the Figure 1A. The preferred embodiment uses a twin well process. The n-well 4 is formed by an n- implant into the area exposed by selective removal of a composite layer of thin SiO₂ and Si₃N₄. A thick oxide is grown in the n area, after which the Si₃N₄ is stripped. A p-well 7 is formed by implant into the area where the Si₃N₄ was etched away. The n- area is masked against the p- implant by the thicker oxide. All oxides are then stripped and the two wells are driven in. A first alternate embodiment is the formation of only an n-well in a p-type substrate. The "p-well" in this case would simply be the area which was not exposed during n-implant. A second alternate embodiment would involve starting with a n-type substrate. A p-well would be formed using a similar masking step through which a p-type dopant would be implanted. Both alternate embodiments are widely used in the industry, however, excessive doping effects involved in single-well processes leads to the preference of a twin well process for the present invention. The active regions 6 are subsequently defined by use of a composite-Si₃N₄ mask, and then are followed by p-field implant 8 using a field implant blocking mask. Device isolation is achieved by field oxidation 10 of non-active areas through a mask of oxidation-inhibiting silicon nitride, or a composite thereof. Following removal of the silicon nitride, a gate oxide 12 is grown in the active areas, followed by a V t channel implant 14. Polysilicon 16 is deposited and doped, and is etched as defined by the polysilicon mask 18 to form the gate structures 17. All steps to this point are conventional for CMOS self-aligned gate technology. Slight variations in this procedure may be anticipated and will not limit the scope of the invention. It is at this point that the present process diverges from the conventional CMOS production techniques of the prior art. An LDD layer 20 is formed by a blanket n- implant of phosphorus. A low temperature oxide is deposited followed by anisotropic etching to form oxide spacers 22 over the LDD layer, adjacent to the edges of the gate structures 17, per conventional techniques. The oxide spacer 22 serves the dual purpose of defining the LDD regions and, later, as a mask to prevent silicide formation too near the gate so as to prevent gate to source and/or drain shorts. The next new step in the process is the formation of a shallow blanket n+ implant of arsenic 24. This provides for low contact resistance in the n-channel devices. Photoresist 25 is spun on the substrate and patterned to expose the p+ contact areas. A high dose p+ implant 26 is performed, resulting in counterdoping of the exposed areas which previously received the blanket n- and n+ implants 20 and 24. For the purpose of this process, a "low" dosage is defined as a dosage of <10¹³ atoms/cm², a "medium" dosage as 10¹³-10¹⁵ atoms/cm² and a "high" dosage as >10¹⁵ atoms/cm². Thereafter, the structure is subjected to rapid thermal annealing (RTA) to drive in the implants and activate the dopants. Furnace annealing at 900° C for approximately 80 minutes provides the same degree of dopant activation and counterdoping, however, RTA is preferred in order to minimize diffusion of the junctions. A thin film of titanium 30 is deposited and the source/drain regions are heat treated to form a silicide 32 of TiSi₂. The titanium 30 does not react where it is deposited on oxide, specifically over field oxide 10 and oxide spacers 22. The unreacted titanium is subsequently removed. The silicide 32 produces low sheet resistance in all contacts, however, the low resistance in the n-channel contacts 42 is primarily due to the n+ blanket implant 24 and not the silicide 32 alone. A low temperature dielectric film 33 is deposited and patterned with photoresist through which contact openings 34 are etched. Interconnect 36 is achieved using conventional procedures of metal deposition and patterning. By means of this technique, the need to use n+ and LDD masks is eliminated. The inclusion of the shallow n+ layer also eliminates the high contact resistance problem which would otherwise have been present because of use of an n-phosphorus layer alone. Specific examples derived from experimental results will illustrate process of this invention. The initial n-phosphorus implant has a dose of 1 x 10¹⁴ atoms/cm² and an energy of 30 KeV. This implant dose provides a low peak substrate current and good hot-electron-resistant performance. It is contemplated that doses in the range of 9 x 10¹³ to 4 x 10¹⁴ atoms/cm² will be suitable for use, with the preferred ranges being 1 x 10¹⁴ to 3 x 10¹⁴ atoms/cm². The low implant energy is necessary to form the shallow n-channel S/D junction to be subsequently counterdoped by the p+ implant 26. The implant energies must be kept low for this reason, and will normally be in the range of 30 to 50 KeV, preferably 30 to 40 KeV. The formation of the n- layer 20 was followed by formation of an oxide spacer, which in turn was followed by a shallow blanket n+ implant 24 needed to reduce or prevent contact resistance problems. An arsenic dose of 7.5 x 10¹⁴ atoms/cm² and an energy of 25 KeV was used. This provided a dose high enough to form the ohmic S/D contacts in the n-channels but low enough to be easily counterdoped subsequently by the BF₂ p+ implant. Generally the n+ implantation will be conducted with doses of 5 x 10¹⁴ to 9 x 10¹⁴ atoms/cm² and energies of 25 to 40 KeV. The optimum doses and energies will be determined from the constraints mentioned above. In this experiment the shallow n-channel S/D region was subsequently counterdoped with a BF₂ p+ implant of 5 x 10¹⁵ atoms and with an energy of 50 KeV. In the further silicide step the Ti thickness formed was 700Å. The device characteristics of a CMOS device made by the process of this invention are given in the Table below, derived from tests of 100/1 µm MOSFET's.

Claims: A method of making a double-diffused drain CMOS device, comprising implanting, into a semiconductor substrate (2) of a first impurity type (p), an impurity of opposite polarity (n) through exposed areas of a composite mask to thereby form a plurality of n- and p-wells (47), removing the mask and performing an implant of said first impurity type, defining a plurality of active regions (6) within said n-wells and said p-wells using a mask, growing isolating thermal oxide (10) on the areas exposed by said mask and removing said mask, growing a gate oxide (12) on the active regions, performing a threshold voltage-determining implant (14), forming doped polysilicon gate structures (17) overlying portions of the active regions; the method comprising the steps of: performing a blanket implant of a first type of n-type dopant after formation of said gate structures, using a dosage of 9x10¹³ to 4x10¹⁴ atoms/cm² and an energy of 30 to 50 KeV, forming spacers (22) adjacent to exposed edges of said gate structures, performing a blanket implant of a second type of n-type dopant, using a dosage of 5x10¹⁴ to 9x10¹⁴ atoms/cm² and an energy of 25 to 40 KeV, performing an implant of p-type dopant into p-channel regions exposed by a p+ mask (25), using a dosage of 4x10¹⁵ to 1x10¹⁶ atoms/cm² and an energy of 45 to 60 KeV, heat treating the substrate to drive in the implants and activate the dopants, forming a silicide (32) in the active p-channel and n-channel regions by depositing a metal and exposing said substrate to a siliciding temperature treatment, and forming contacts through a low temperature dielectric film (33) deposited over the substrate by etching areas exposed by a contact-mask; and forming a metal interconnect (36) through which access to the device may be achieved. A method as defined in claim 1 wherein said first n-type dopant is phosphorous. A method as defined in claim 1 wherein said second n-type dopant is arsenic. A method as defined in claim 1 wherein said p-type dopant is BF₂. A method as defined in claim 1 wherein said metal used to form said silicide is titanium, thereby creating TiSi₂. A method as in claim 1 wherein said heat treating is rapid thermal annealing. A method as defined in claim 1 wherein said spacers (22) are formed of oxide and are of sufficient width to prevent gate to source/drain shorts when said silicide is formed. A method as defined in claim 1 wherein said spacers are of appropriate width to minimize hot-electron effects.

Inventors: LIOU TIAN-I, TENG CHIH-SIEH, LIOU, TIAN-I, TENG, CHIH-SIEH
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L27, H01L29, H01L21