MOSFET depletion device

Abstract: A p-channel depletion device (10) in a MOSFET is formed and preferably comprises a silicon substrate (12), an N-well region (14), P+ source (16) and drain (18) regions, and a polysilicon gate (20) which has been appropriately doped to be of a P- conductivity type. The resulting structure performs analogously to a depletion device formed in accordance with conventional methods wherein a depletion mask and implant are utilized, and is characterized by having a threshold voltage of approximately +250 millivolts.

Description: This invention generally relates to integrated circuit fabrication techniques. More particularly, this invention relates to a P-channel depletion mode device created within a metal-oxide-semi-conductor field-effect transistor (MOSFET) as specified in the preamble of claim 1, for example as disclosed in US-A-4,599,789. A further p-channel MOSFET is known from IEEE-ED 36 (1989), June, no.6, pgs. 1087-1093 Background of the Invention In metal-oxide-semi-conductor (MOS) monolithic integrated circuit technology, field-effect transistors (FET's) are the essential components, acting as both active and passive components. MOSFET's are formed with p-type channels or n-type channels. It is desirable at times to operate these devices in a depletion mode. Typically, depletion occurs when the channel is heavily doped with an appropriate species to form, simplistically speaking, an electrical short in the channel between source and drain regions of the FET. This results in the device being "on", even though the applied voltage to a gate thereof is zero. This depletion mode affects the threshold voltage of the transistor. The threshold voltage is that voltage which must be applied to result in mobility of the electronic charge carriers across the channel. The threshold voltage is dependent on many characteristics of the FET including not only the doping density of the channel region or depletion zone, but also the work function difference between the gate and the silicon substrate, the oxide thickness and permittivity, the surface-state charge density and the distributed charge in the oxide. Generally, variations in device threshold voltages, such as that caused by depletion, are preferably achieved through separate dopant implants into the channel of the device. This requires additional process steps and masks. In particular, the depletion zone is typically formed using ion implantation techniques wherein an appropriate species is implanted into the channel region to form the depletion zone. However, a shortcoming associated with this method as stated previously, is that generally additional mask and implant steps are required to form this depletion zone. As widely known throughout the electronics industry, it is desirable to minimize or alleviate the number of processing steps, particularly those that require masking and alignment procedures. Therefore, it would be desirable to provide a method for forming a depletion device within an MOSFET which does not require the additional processing steps associated with the conventional masking and implanting methods for forming these devices. It would be extremely desirable if such methods were compatible with currently utilized processing steps. Summary of the Invention A p-channel depletion PET in a CMOS device according to the present invention is characterised by the features specified in the characterising portion of claim 1. It is an object of the present invention to provide a p-channel depletion device and a method for forming such a device. It is a further object of this invention that such a device be formed using conventional CMOS techniques with polysilicon resistors without additional masking, implanting or processing steps. In accordance with a preferred embodiment of this invention, these and other objects and advantages are accomplished as follows. This invention comprehends a p-channel depletion device in a MOSFET and a method for forming the same. The p-channel depletion device comprises an N-well region within an appropriate substrate such as silicon, P+ source and drain regions within said N-well region and a P- polysilicon gate region. In accordance with a preferred embodiment of this invention, the preferred method for forming the p-channel depletion device comprises the following steps. Using conventional CMOS technology, a resistor mask used for forming the polysilicon resistors masks the P-type gate. Therefore, the P-gate does not receive the normal heavy phosphorus diffusion used to form the low-resistance N-type polysilicon gate and interconnect regions. After this phosphorus doping, the resistor mask is removed, and the N+ source/drain mask is applied. Once the N+ source/drains are implanted and formed, the N+ mask is removed, and the P+ mask is applied. Here, the lightly-doped gate of the P-channel device is counter-doped heavily P+, while the P-gate is counter-doped with boron during the formation of the P+ source and drain regions. It is during this doping step of the P+ source and drain regions that the polysilicon gate, which was not doped previously, is doped so as to be characterized by P- conductivity type. The resulting device performs analogously to a P-channel depletion device and is characterized by a change in threshold voltage of approximately +1 volt or greater, to a threshold voltage of approximately +250 millivolts. The formation of this depletion device is accomplished using normal CMOS processing with polysilicon resistors. During processing, the resistor mask, used for formation of the polysilicon resistor, is also used to block the normal phosphorus doping of the p-channel polysilicon gate. The gate is then subsequently counter-doped during the implanting of the P+ source and drain regions. With this invention, a depletion implant is not utilized, thereby alleviating the additional masking and implant steps associated with the formation of the depletion device. The teachings of this invention may also be utilized with an n-channel device. The resulting n-channel device features small positive threshold voltage shifts, and therefore may be useful as a comparator-type device. Other objects and advantages of this invention will be better appreciated from the following detailed description. Brief Description of the Drawings Figures 1-8 illustrate the preferred processing steps for formation of a p-channel depletion device in accordance with this invention. Detailed Description of the Invention A p-channel depletion device 10 in a MOSFET is formed. As shown in Figure 1, the p-channel depletion device 10 comprises an appropriate substrate 12 such as silicon, an N-well region 14 diffused into the substrate 12, source and drain regions, 16 and 18 respectively, which have been doped to be of a P+ conductivity type, and a polysilicon gate 20 which has been appropriately doped to be of a P- conductivity type. The resulting structure 10 performs analogously to a depletion device formed in accordance with conventional methods wherein a depletion implant is utilized and is characterized by a threshold voltage of approximately 1 volt. Conventional gate oxide 22, field oxide 24 and a complimentary n-channel transistor 26 are also present. Simplistically, a conventional p-channel MOSFET is converted into a depletion mode device by using the resistor mask used for formation of the polysilicon resistors, to block the normally heavy phosphorus doping of the P-type polysilicon gate 20. Then, when the p-channel device receives its normal P+ source/drain implant, the polysilicon gate 20 becomes doped by boron to P- type conductivity. The difference in doping species and relative concentration creates a significant positive offset of approximately 1.0-1.5 Volt (depending on the original gate implant dose) in the p-channel threshold. The resulting device is characterized by a threshold voltage of approximately +250 millivolts. A conventional p-channel device is characterized by a threshold voltage of approximately -750 millivolts. The p-channel polysilicon gate 20 of the device is then electrically connected back to the source 16, creating a V gs = OV situation, resulting in a depletion load. The preferred method for forming this p-channel depletion device is as follows: As shown in Figure 2, first, using conventional techniques an N-well region 14 is formed within an appropriate substrate 12 such as single crystal silicon. Gate oxide 22 and field oxide 24 have also been formed using conventional techniques. As shown in Figure 3, a blanket layer of polysilicon 32 is deposited everywhere. The resistor implants are then applied by doping the blanket layer of polysilicon 32. The polysilicon 32 is doped using conventional dosages of phosphorus to result in the polysilicon layer 32 having a N-- type conductivity characterized by a resistance of approximately 750 ohms per square. As shown in Figure 4, regions 34 of low-temperature oxide are conventionally deposited and patterned. This is accomplished by first depositing a layer of low-temperature oxide and densifying the oxide, then depositing a photoresist resistor mask and patterning the mask using a hydrofluoric acid etch through the unprotected low-temperature oxide layer, followed by a photoresist strip to retain the patterned regions of low-temperature oxide. In those regions not masked by the regions 34 of low-temperature oxide, a phosphorus diffusion is used to convert the N-- type polysilicon layer 32 to a N+ type conductivity region 36 characterized by a resistance of approximately 30 ohms per square. As shown in Figure 5, the patterned regions of low-temperature oxide are then removed using a conventional hydrofluoric acid oxide etch-back process. This results in a resistor structure having adjacent areas of N+ polysilicon 36 and N-- polysilicon 32. The polysilicon gate regions 38 and 40 are formed next as shown in Figure 6. The polysilicon layer 32 is masked with an appropriate photoresist, conventionally etched and then the photoresist is stripped away. This results in an N-- gate 40 over the N-well region 14 and an N+ gate 38 over the corresponding n-channel transistor 26. Source and drain regions 28 and 30 are now formed in the corresponding n-channel transistor 26, as shown in Figure 7. First, a photoresist mask 42 is deposited and patterned so as to mask the N-- gate 40 over the N-well region 14. The N+ source and drain regions 28 and 30 are then formed by implanting phosphorus or other appropriate dopant into the source and drain regions of the unmasked n-channel transistor 26. The N+ source and drain regions 28 and 30 are self-aligned by the N+ gate 38. During this step, the N-- gate 40 over the N-well region 14 in the p-channel device is masked from receiving any dopant. Lastly, the photoresist mask 42 is removed. As shown in Figure 8, the p-channel source and drain 16 and 18 are formed while also appropriately doping the corresponding gate 20. This is accomplished by first masking the n-channel transistor 26 using a conventional photoresist mask 44. The P+ source and drain regions 16 and 18 are then formed by implanting an appropriate dosage of boron so as to result in a resistance of approximately 100 ohms per square. The polysilicon p-channel gate 20 which was previously N-- type conductivity also receives the boron doping and becomes characterized by P- type conductivity having a resistance of approximately 300 ohms per square. The photoresist mask 44 protecting the n-channel transistor 26 is then removed. The resulting structure is shown in Figure 1. The p-channel depletion 10 device performs analogously to a depletion mode device wherein the threshold voltage is approximately +250 millivolts, resulting in a change of approximately 1.0-1.5 Volts. The n-channel transistor 26 is characterized by a conventional threshold voltage of approximately +750 millivolts. With this invention, a depletion implant is not utilized, thereby alleviating the additional masking and implant steps associated with the formation of the depletion device. The teachings of this invention may also be utilized with an n-channel device. The resulting n-channel device features small positive threshold voltage shifts, and therefore it may be useful as a comparator-type device. For the n-channel device, the resistor mask is used to block the normal heavy phosphorus doping of the gate. The gate is then counterdoped with the normal N+ source drain implant. A relatively small but consistent offset is created by the doping level difference from a normal gate. Therefore, it is foreseeable that this device could be useful for comparator applications. With this invention, a depletion mode device may be formed using conventional CMOS technology and processing steps, and without the use of additional masking and implanting steps.

Claims: A p-channel depletion FET (10) in an CMOS device comprising the following: a -well region (14) of N conductivity type within an appropriate substrate (12); source (16) and drain (18) regions of P+ conductivity type within said N-well region (14); and a polysilicon gate region (20) of P- conductivity type; characterised in that the threshold voltage of said device (10) is approximately +250 millivolts. A method for forming a p-channel depletion FET (10) according to claim 1, in an MOSFET, which method comprises the following steps: forming an N-well region (14) of conductivity type within an appropriate substrate (12); forming a polysilicon gate (40) over said N-well region (14) which is characterized by a N-- conductivity type; and implanting boron into said N-well region (14) to form source (16) and drain (18) regions of P+ type conductivity whilst concurrently counter-doping said gate (40), so that said gate (40) is changed into a gate (20) characterized by a P- type conductivity.

Inventors: HENDERSON MARK F, SCHLAIS JOHN R, HENDERSON, MARK F., SCHLAIS, JOHN R.
Applicants: DELCO ELECTRONICS CORP, DELCO ELECTRONICS CORPORATION
Application year: 1990
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27