Digital signal reproducing apparatus

Abstract: There is provided a digital signal reproducing apparatus comprising: a binarization circuit (5) to binarize a signal which was read out of a recording medium or a transmitted signal; first and second pulse generators (15, 16) to generate pulses which are respectively synchronized with leading and trailing edges of a binary signal which was binarized by the binarization circuit (5); and first and second signal generators to generate first and second position signals indicative of the positions of the leading and trailing edges synchronously with the first and second sync pulses which are generated from the first and second pulse generators. The binary signal is a signal of the NRZ coding system. Each pulse generator has a PLL circuit (17, 18). With the apparatus, the signal can be accurately reproduced irrespective of the recording density by compensating the phase difference between the leading and trailing edges of the binary signal.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a digital signal reproducing apparatus for accurately reproducing a transmitted binary signal or a binary signal which was read out of a recording medium. Related Background Art Fig. 4 is a block diagram showing a conventional information decoding and reproducing apparatus for decoding a transmitted binary signal or a binary signal which was reproduced from a recording medium. In Fig. 4, explanation will now be made with respect to the case of reading out data which was recorded in a recording medium such as magnetic disk 1, magnetic tape 2, or the like. The data written in the recording medium is first converted into the electric signal corresponding to the magnetic flux density detected by a detector 3 comprising a magnetic head or the like. The electric signal is amplified by a preamplifier 4 and binarized by a binarization circuit 5. The binary signal which was binarized by the binarization circuit 5 is input to a PLL circuit 6. A sync clock signal which is synchronized with the binary signal is produced from the PLL circuit 6. The binary signal is a signal which has been encoded by, for instance, a 2-7 conversion coding method or the like. The sync clock signal and the binary signal are input to a code decoding circuit 7. The decoded reproduction data and a clock synchronized therewith are output from the code decoding circuit 7. Even in the case of using an optical disk in place of the magnetic disk and magnetic tape, only the detecting method by the detector 3 differs and the subsequent processes are similar to those mentioned above. As a method of writing data into the recording media 1 and 2, there are mainly used an NRZ coding (mark interval storing system) method whereby in the binarized signal, a truth value (code word) "1" is made correspond to one pulse and an NRZI coding (mark length storing system) method whereby a truth value (code word) "1" is made correspond as a change point of the polarity of the signal as shown in Fig. 5. Either one of the above two methods is selected used in accordance with the characteristics of the recording medium, characteristics of the transmitting system, characteristics of the coding system, and the like. The NRZI code and NRZ code in Fig. 5 will now be compared. In the case of the NRZI code, since information is provided for the edges of both polarities of the leading and trailing edges of the signal, when comparing in the same frequency band, information can be transmitted or stored at a double density. However, to use the NRZI code, some conditions are required for the transmitting system. That is, to use the NRZI code, in the transmitting system of the signal, the ratio of the "H" level signal on the transmission side and the ratio of the "H" level signal on the reception side must coincide, while the ratio of the "L" level signal on the transmission side and the ratio of the "L" level signal on the reception side must coincide, respectively. However, for instance, in the case of recording information by forming optical, magnetical, or physical pits onto one recording medium, there is a case where the ratios of "H" and the ratios of "L" mentioned above in the recording information and the reproduced information do not coincide. For instance, if a difference occurs between the recording sensitivity and the reproducing sensitivity due to the characteristics of the recording means of the recording and reproducing apparatus and the characteristics of the reading means thereof, as shown in Fig. 6, the portion of "H" becomes long or the portion of "L" becomes long. In Fig. 6, reference numeral 61 denotes a reproduction signal when the recording sensitivity is good and 62 indicates a reproduction signal when the recording sensitivity is bad. If the recording sensitivity and the reading sensitivity are good, the reproduction signal has a waveform near the recording signal as shown by reference numeral 63 and the relation between the time when the reproduction binary signal is held in the state of "H" and the time when it is held in the state of "L" is held in a manner similar to that in the recording signal. Therefore, in such a case, the NRZI coding method can be used. However, when the recording sensitivity is low, the reproduction signal waveform becomes dull as shown by reference numeral 62 and the phases of the leading edge and trailing edge of the reproduction binary signal are deviated as shown by reference numeral 64. Further, when the recording sensitivity is not constant, a phase deviation amount also becomes unstable and the efficient NRZI coding method cannot be used. US-A-4688205 proposes a data demodulation apparatus in which a binary coding circuit binarises a signal read from an optical disc. A PLL circuit generates a reproduction pulse which is either locked to the phase of the binarised data or alternatively is locked to the phase and frequency of a clock signal from a reference clock generator. The reproduction pulses are supplied to a reproduction code output circuit which synchronises the binary data with the reproduction pulses, and reproduction pulses together with the synchronised data are supplied to a demodulator. SUMMARY OF THE INVENTION According to the present invention there is provided a digital signal reproducing apparatus as set out in claim 1 and a digital signal reproducing method as set out in claim 14. The remaining claims set out optional features. The apparatus and method of the present invention may be applied to a signal which was read out of a recording medium or a signal which was transmitted. An embodiment of the invention provides a digital signal reproducing apparatus for accurately reproducing a signal without being influenced by the recording sensitivity. An embodiment of the invention provides a digital signal reproducing apparatus for reproducing an accurate signal by compensating the phase deviation between the leading edge and the trailing edge of a binary signal. An embodiment of the invention provides a digital signal reproducing apparatus which can use the NRZI coding method. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an embodiment according to the present invention; Fig. 2 is a detailed circuit diagram of a clock sync unit 10 in Fig. 1; Fig. 3 is a timing chart of input/output signals in the embodiment shown in Figs. 1 and 2; Fig. 4 is a block diagram for explaining a general digital information reproducing apparatus; Fig. 5 is a timing charge for explaining a general recording method; and Fig. 6 is a timing charge for explaining the problems in the case of using the conventional NRZI coding method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the invention will be described in detail hereinbelow with reference to the drawings. The invention is applied to the reproduction of a communicated signal and the reproduction of the signal which was read out of a recording medium or which was transmitted. Explanation will now be made with respect to a method of decoding a signal obtained by reproducing and reading out NRZI coding method information which had been encoded in accordance with the NRZI coding method and stored into a memory medium. Fig. 1 is a block diagram of an embodiment according to the invention and is a diagram showing the details of a circuit corresponding to the PLL circuit 6 in Fig. 4. The parts and components similar to those in Fig. 4 (for example the binarization circuit 5 and the code decoding circuit 7) are designated by the same reference numerals and their detailed descriptions are omitted here. Fig. 2 is a detailed circuit diagram of a clock sync unit 10 in Fig. 1. Fig. 3 is a timing chart for signals in Figs. 1 and 2. In the embodiment, attention is paid to a point that phase delays a and a′ of the leading edges in Fig. 6 are equal and, further, phase delays or phase advances b and b′ of the trailing edges are equal. That is, when paying attention only to the leading edges or only to trailing edges, their phases are delayed by a constant phase error amount at any particular degree of recording sensitivity. Therefore, the apparatus is constructed by also comprising: means for producing a first clock synchronized with the phase of the leading edges of a binary signal; means for generating information corresponding to the position of the leading edges by using the first clock as a reference; means for producing a second clock synchronized with the phase of the trailing edges; and means for generating information corresponding to the position of the trailing edges by using the second clock as a reference. Due to this, the phase difference between the leading edges of the binary signal and the phase difference between the trailing edges are set off and the edge position information can be accurately reproduced. Therefore, the NRZI code can be used irrespective of a change in sensitivity or the like. In Figs. 1 and 2, a binary signal "A" from the binarization circuit 5 is a signal which was encoded by the NRZI coding method and has information with respect to both of the positions of the leading and trailing edges. However, as mentioned above, according to the above system, in many cases, there is a phase deviation between the leading edges and the trailing edges due to the instability of the recording sensitivity and the signal is read out in such a phase deviated state. When explaining with respect to an example shown in the timing chart of Fig. 3, the phase of the trailing edges has been advanced than the phase of the leading edges by about "ϑ". Therefore, to also properly cope with such a phase deviation, in the embodiment, pulse signals "B" and "D" having predetermined widths which are respectively synchronized with the leading edges and the trailing edges are first produced by two respective monostable multi-vibrators 15 and 16. The pulse signals "B" and "D" are input to PLL circuits 17 and 18, respectively. The PLL circuits 17 and 18 produce clock signals "C" and "E" having predetermined periods which are synchronized with the pulse signals "B" and "D". These are sent to the clock sync unit 10 together with the above signals "B" and "D". The periods of the clock signals "C" and "E" coincide with the period of the sync clock of the real recording data. In the case of Fig. 3, there is a phase deviation of "ϑ" between the clock signals "C" and "E" as mentioned above. In the clock sync unit 10, the clock synchronization is executed for each clock signal by clock sync circuits 11 and 12 and data signals "F" and "G" are produced. Fig. 2 shows a detailed diagram of the clock sync unit 10. The clock sync circuit 11 uses two flip-flops 11a and 11b. The clock sync circuit 12 uses three flip-flops 12a, 12b, and 12c. In the clock sync circuit 11, since the inverted signal of the signal C is used as a clock signal of the flip-flop 11b, the signal F rises later than the signal B by the time of half clock and is output with a pulse width of one clock period. On the other hand, in the clock sync circuit 12, since the signal E is used as a clock signal of the flip-flop 12c, a signal G rises later than the signal D by the time of one clock and is output with a pulse width of one clock period. After that, the OR of both data signals "F" and "G" is calculated by an OR circuit 13. In a clock sync circuit 14 (using two flip-flops 14a and 14b as shown in Fig. 3), reproduction code data "J" and a synchronous clock signal "I" as an inverted signal of the clock signal "C" are produced from the OR signal "H" and one clock (leading edge clock signal "C" in this case). In the clock sync circuit 12, the leading edge of the signal D is delayed by the time of one period of the clock signal E and is synchronized. In the clock sync circuit 14, the signal G is delayed by the time of half period of the clock signal C and is synchronized. Therefore, if the phase difference of the trailing edges of the binary signal A is equal to or smaller than the half period of the clock signal C, the phase difference can be absorbed. Therefore, as shown in Fig. 3, the reproduction code word data "J" is output as reproduction data which is equal to the real recording data shown in the top portion in Fig. 3 together with the clock signal "I" as a sync signal because the phase difference between the leading and trailing edges which is caused due to the instability of the sensitivity is eliminated and corrected. The reproduction code word data is decoded to the original data by the code decoding circuit 7. As described above, according to the embodiment, in the case of using the NRZI coding method, even in the case where a phase deviation is caused between the leading information of the read signal and the trailing information thereof due to a deterioration of the reading sensitivity or the like, such a phase deviation can be effectively corrected and the stable reproduction code word data can be obtained. Since the PLL circuits 17 and 18 operate by receiving pulses of predetermined widths, they need the monostable multivibrators 15 and 16 shown in Fig. 1 and described above. However, if the phase comparator arranged in the inputting section of the PLL circuits 17 and 18 is of the type so as to operate by, for instance, edge inputs, the monostable multivibrators 15 and 16 can be omitted. In the embodiment, the trailing edge data has been clock synchronized with the leading edge data and handled as a series of serial data. However, the invention is not limited to the above example. The invention also obviously incorporates a construction in which the leading edge data and the trailing edge data are respectively independently reproduced and output as independent reproduction data and used. As described above, according to the embodiment, it is possible to compensate the phase shift error of the trailing edges relative to the leading edges of the binary signal which is caused by a level change of the reception analog signal due to the sensitivity change. Thus, in the recording or signal transmission in which only the mark interval recording method (NRZ code) can be used hitherto, the mark length recording method (NRZI code) can be used and the recording density can be doubled. The present invention is not limited to the foregoing embodiment but many modifications and variations are possible within the scope of the appended claims of the invention.

Claims: A digital signal reproducing apparatus comprising: a binarisation circuit (5) to binarise an input signal read from a recording medium or which was transmitted; and clock generator means (17, 18) for generating a clock signal synchronised with the binarised signal (A) output from the binarisation circuit, characterised in that the clock generator means (17, 18) is for generating first and second clock signals (C, E), the first clock signal (C) being synchronised with the leading edges of the binarised signal (A) output from the binarisation circuit (5) and the second clock signal (E) being synchronised with the trailing edges of the binarised signal (A) output from the binarisation circuit (5), and in that the apparatus comprises a phase compensating means (10) for generating a reproduction output (J) in which the phase difference between the leading edges and the trailing edges of the said binarised signal (A) is compensated by using the first and second clock signals (C, E). A digital signal reproducing apparatus according to claim 1 in which the phase compensating means is also for outputting a clock signal (I) with which the leading edge data and the trailing edge data are synchronised in the reproduction output (J). A digital signal reproducing apparatus according to claim 1 or claim 2 in which the said binarised signal (A) is NRZI coded. A digital signal reproducing apparatus according to any one of the preceding claims in which the reproduction output (J) is NRZ coded. A digital signal reproducing apparatus according to any one of the preceding claims comprising a decoding circuit (7) for receiving and decoding the reproduction output (J) from the phase compensating means (IO). A digital signal reproducing apparatus according to any one of the preceding claims comprising pulse generating means (15, 16) for generating first pulses (B) in response to leading edges in the binarised signal (A) and generating second pulses (D) in response to trailing edges in the binarised signal (A), and outputting the first and second pulses (B, D) to the clock generator means (17, 18), the clock generator means (17, 18) synchronising the first clock signal (C) to the first pulses (B) and synchronising the second clock signal (E) to the second pulses (D). A digital signal reproducing apparatus according to any one of the preceding claims in which the phase compensating means (10) comprises: signal generating means (11, 12) for generating first and second data signals (F, G), the first data signal (F) representing the leading edges of the binarised signal (A) output from the binarisation circuit (5) and being synchronised with the first clock signal (C), and the second data signal (G) representing the trailing edges of the binarised signal (A) output from the binarisation circuit (5) and being synchronised with the second clock signal (E); and further means (13, 14) for generating the reproduction output (J) from the first and second data signals (F, G). A digital signal reproducing apparatus according to 6 in which the phase compensating means (10) comprises: signal generating means (11, 12) for generating first and second data signals (F, G), the first data signal (F) representing the leading edges of the binarised signal (A) output from the binarisation circuit (5) and being generated from the first pulses (B) and synchronised with the first clock signal (C), and the second data signal (G) representing the trailing edges of the binarised signal (A) output from the binarisation circuit (5) and being generated from the second pulses (D) and synchronised with the second clock signal (E); and further means (13, 14) for generating the reproduction output (J) from the first and second data signals (F, G). A digital signal reproducing apparatus according to claim 7 or claim 8 in which the further means comprises data re-timing means (14) for synchronising the leading edge data of the first data signal (F) and the trailing edge data of the second data signal (G) with one of the first and second clock signals (C, E). A digital signal reproducing apparatus according to any one of claims 7 to 9 in which the further means comprises a logical 'OR' circuit (13) for receiving the first and second data signals (F, G) and outputting a combined data signal (H). A digital signal reproducing apparatus according to any one of claims 1 to 9 in which the reproduction output (J) comprises separate leading edge and trailing edge data outputs. A digital signal reproducing apparatus according to any one of claims 1 to 9 in which the reproduction output (J) comprises leading edge data and trailing edge data in a serial output. A digital signal reproducing apparatus according to any one of the preceding claims in which the clock generator means comprises a first PLL circuit (17) for synchronising the first clock signal (C) and a second PLL circuit for synchronising the second clock signal (D). A digital signal reproducing method comprising: binarising an input signal read from a recording medium or which was transmitted, to provide a binarised signal (A); and generating a clock signal synchronised with the binarised signal (A), characterised in that the step of generating a clock signal comprises generating first and second clock signals (C, E), the first clock signal (C) being synchronised with the leading edges of the binarised signal (A) and the second clock signal (E) being synchronised with the trailing edges of the binarised signal (A), and in that the method comprises generating a reproduction output (J) in which the phase difference between the leading edges and the trailing edges of the said binarised signal (A) is compensated by using the first and second clock signals (C, E). A digital signal reproducing method according to claim 14 which comprises outputting a clock signal (I) with which the leading edge data and the trailing edge data are synchronised in the reproduction output (J). A digital signal reproducing method according to claim 14 or claim 15 in which the said binarised signal (A) is NRZI coded. A digital signal reproducing method according to any one of claims 14 to 16 in which the reproduction output (J) is NRZ coded. A digital signal reproducing method according to any one of claims 14 to 17 comprising the step of receiving and decoding the reproduction output (J). A digital signal reproducing method according to any one claims 14 to 18 comprising: generating first pulses (B) in response to leading edges in the binarised signal (A) and generating second pulses (D) in response to trailing edges in the binarised signal (A), and synchronising the first clock signal (C) to the first pulses (B) and synchronising the second clock signal (E) to the second pulses (D). A digital signal reproducing method according to any one of claims 14 to 19 which comprises generating first and second data signals (F, G), the first data signal (F) representing the leading edges of the binarised signal (A) and being synchronised with the first clock signal (C), and the second data signal (G) representing the trailing edges of the binarised signal (A) and being synchronised with the second clock signal (E), and the reproduction output (J) is generated from the first and second data signals (F, G). A digital signal reproducing method according to claim 19 which comprises generating first and second data signals (F, G), the first data signal (F) representing the leading edges of the binarised signal (A) and being generated from the first pulses (B) and synchronised with the first clock signal (C), and the second data signal (G) representing the trailing edges of the binarised signal (A) and being generated from the first pulses (D) and synchronised with the second clock signal (E), and the reproduction output (J) is generated from the first and second data signals (F, G). A digital signal reproducing method according to claim 20 or claim 21 comprising the step of synchronising both the leading edge data of the first data signal (F) and the trailing edge data of the second data signal (G) with the same one of the first and second clock signals (C, E). A digital signal reproducing method according to any one of claims 20 to 22 comprising the step of performing a logical 'OR' operation on the first and second data signals (F, G) and outputting a combined data signal (H). A digital signal reproducing method according to any one of claims 14 to 22 in which the reproduction output (J) comprises separate leading edge and trailing edge data outputs. A digital signal reproducing method according to any one of claims 20 to 22 in which the reproduction output (J) comprises leading edge data and trailing edge data in a serial output.

Inventors: SATOMURA SEIICHIRO C O CANON K, SATOMURA, SEIICHIRO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H04L25
IPC codes: H04L7, G11B20, H03M5