Semiconductor device comprising wiring layers

Abstract: At least one slit (4a, 4b) having a predetermined shape is formed around a contact region of a lower wiring layer (1) formed on a substrate (5), and insulating portions (6a, 6b) formed integrally with an insulating layer (6) is embedded in these slits (4a, 4b). This insulating layer (6) is formed on the lower wiring layer (1) and has a contact hole (3) located at a position corresponding to the contact region. Since the insulating portions (6a, 6b) as a wedge-like portion project into the slits downwardly from the rigid insulating layer (6), positional errors caused by thermal expansion of the lower wiring layer (1) in annealing of the upper wiring layer (2) can be suppressed, and an abnormal geometry such as a projec­ tion on the upper wiring layer (2) can be prevented. In addition, a semiconductor device free from inter­ wiring short-circuiting and excellent in flatness can be obtained.

Description: The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a multilayered wiring structure. A semiconductor device manufactured by conventional techniques will be described with reference to Fig. 1. Fig. 1 is a sectional view showing the semiconductor device manufactured by conventional techniques. The semiconductor device having a multilayered wiring structure formed by conventional techniques comprises an insulating layer 26 formed on a semiconductor substrate 21, a lower wiring layer 22 formed on the insulating layer 26, an insulating layer 23 formed on the lower wiring layer 22 and having a contact hole 25 in a predetermined contact region, and an upper wiring layer 24 formed on the insulating layer 23 and connected to the lower wiring layer 22 through the contact hole 25. In this semiconductor device, after the upper wiring layer 24 is formed, annealing is performed, for example, to form a protective layer on the upper wiring layer 24. When annealing is performed according to the conventional technique, the lower wiring layer 22 connected to the upper wiring layer 24 through the contact hole 25 thermally expands to push out the upper wiring layer 24 through the contact hole 25 and to thus cause an abnormal geometry such as a projection on the upper wiring layer 24. When the projection or the like extends laterally, lines of the upper wiring layer 24 are connected to each other to result in short-circuiting. Even if the lines of the lines wiring layers 24 are not connected to each other, a distance between the lines is decreased to form a void in the insulating layer or the like on the wiring layer. When thermal stress acts on the insulating layer having a void, the projection grows to cause interwiring short-circuiting, thus degrading reliability. When the projection or the like extends vertically, flatness of the upper wiring layer 24 is degraded when a wiring layer is to be further formed on the upper wiring layer 24. In addition, the influences of thermal expansion become conspicuous when the area of the lower wiring layer 22 is larger than that of the upper wiring layer 24. It is known from JP 61-15350 A to prohibit cracks by providing a plurality of slits extending lengthwise to a wiring layer of a semiconductor device. The prohibition of projections is, however, not achieved. It is an oject of the present invention to provide a semiconductor device wherein an abnormal geometry e.g., a projection on an upper wiring layer which is caused by thermal expansion of a lower wiring layer by the conventional technique described above can be prevented, interwiring short-circuiting can also be prevented, and flatness can be improved. In order to achieve the above object of the present invention, there is provided a semiconductor device comprising: a substrate; a lower wiring layer formed above said substrate; an insulating layer formed on said lower wiring layer having a contact hole; an upper wiring layer formed on the insulating layer and being connected to said lower wiring layer through said contact hole ; at least one slit formed in said lower wiring layer in the vicinity of said contact hole and extending along one side of a contact region which is defined as a region which is located near the contact hole and in contact with the upper wiring layer (2); and an insulating portion formed integrally with the insulating layer and being embedded in said slit whereby movement of the lower wiring layer within said contact region due to thermal expansion during annealing is prevented. According to the present invention, since at least one slit is formed around the contact region of the lower wiring layer, and the insulating portion having the same material as that of the upper insulating layer is embedded in the slit is formed integrally with the upper insulating layer, even if the periphery of the contact region of the lower wiring layer thermally expands, the insulating portion in the slit can prevent movement of the lower wiring layer upon its expansion, and thus the influence on the contact hole can be prevented. Therefore, the influence on the upper wiring layer connected to the lower wiring layer through the contact hole formed in the contact region due to the annealing in forming the protect film on the upper wiring layer can be prevented, and an abnormal geometry such as a projection on the upper wiring layer by thermal expansion of the lower wiring layer can be prevented. Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention. Fig. 1 is a sectional view showing a semiconductor device manufactured by conventional techniques; Fig. 2A is a sectional view showing a semiconductor device according to the first embodiment of the present invention cut along the line II - II of Fig. 2B; Fig. 2B is a plan view showing the semiconductor device according to the first embodiment of the present invention cut along the line I-I of Fig. 2A; and Figs. 3 to 9 are plan views of semiconductor devices according to other embodiments of the present invention, respectively. There will now be described an embodiment of this invention with reference to the accompanying drawings. Semiconductor devices according to embodiments of the present invention will be described with reference to Figs. 2A to 9. For illustrative convenience, each of the plan views of Figs. 2B to 9 does not illustrate a substrate 5 and an insulating layer 7 but illustrates a structure cut along the line I - I of Fig. 2A. Figs. 2A and 2B are a sectional view and a plan view, respectively, showing a semiconductor device according to the first embodiment of the present invention. As shown in Fig. 2A, this semiconductor device comprises the insulating layer 7 formed on the semiconductor substrate 5, a lower wiring layer 1 formed on the insulating layer 7, an insulating layer 6 formed on the lower wiring layer 1 and having a contact hole 3 in a predetermined contact region, and made of a silicon oxide film (SiO 2 film) or the like, and an upper wiring layer 2 formed on the insulating layer 6 and connected to the lower wiring layer 1 through the contact hole 3. Slits 4a and 4b are formed around the contact region of the lower wiring layer 1. Insulating portions 6a and 6b are embedded in the slits 4a and 4b and are formed integrally with the insulating layer 6. The insulating layer 6 has rigidity having a predetermined value or more. The "contact region" in the present invention is defined as a region which is located near the contact hole 3 and in contact with the upper wiring layer 2. As shown in Fig. 2B, the length of each of the slits 4a and 4b is larger than the length of one side of the contact hole 3, and the width of each of the slits 4a and 4b is preferably minimized to obtain a minimum wiring pitch due to the following reason. When the width of each of the slits 4a and 4b is large, a current through the contact region is undesirably reduced due to the slits 4a and 4b. In addition, each of the slits 4a and 4b is preferably formed in a region spaced apart from the contact hole 3 by a wiring margin due to the following problem. When the slits 4a and 4b are formed adjacent to the contact hole 3, a problem is posed by mask misalignment at the time of formation of the insulating layer 6. For example, when the width of the contact hole 3 is 1.6 µm, and its length is 2.5 µm, slits 4a and 4b each having a width of 2 µm and a length of 3.7 µm are respectively formed at both sides of the contact hole 3 at positions spaced apart from the contact hole 3 by 2 µm each. In the semiconductor device of Fig. 2B, since the slits 4a and 4b are formed at both sides of the contact region of the lower wiring layer 1, positional errors caused by thermal expansion of the lower wiring layer 1 during annealing for forming the protection film on the upper wiring layer 2 can be prevented by the insulating portions 6a and 6b respectively formed in the slits 4a and 4b. For this reason, the influence of annealing on the upper wiring layer 2 connected to the lower wiring layer 1 through the contact hole 3 formed in the contact region can be prevented. Therefore, an abnormal geometry such as a projection formed on the upper wiring layer according to the conventional problem can be minimized, and flatness of the upper wiring layer 2 can be improved. In particular, since the slits 4a and 4b are not formed immediately under the upper wiring layer 2, flatness of the upper wiring layer 2 can be further improved. In addition, in the semiconductor device described above, an influence of thermal expansion of the lower wiring layer 1 on the contact hole 3 in a direction perpendicular to the upper wiring layer 2 can be prevented. Figs. 3 to 9 are plan views showing semiconductor devices according to the second to ninth embodiments of the present invention, respectively. The reference numerals as in Fig. 1 denote the same parts in Figs. 3 to 10. In the second to ninth embodiments of the present invention, the positions and shapes of the slits of the first embodiments are changed. The conditions for the slit width, the slit length, the distance from a contact hole 3 to the slit are the same as those of the first embodiment. However, these conditions may be arbitrarily changed. An insulating portion is embedded in each slit of the each of the following embodiments and formed integrally with an insulating layer. In the second embodiment shown in Fig. 3, two slits 4a and 4b are formed at both sides of the contact hole 3 in a direction perpendicular to an upper wiring layer 2. In the semiconductor device of this embodiment, the same effect as in the first embodiment can be obtained, and an influence of thermal expansion of a lower wiring layer 1 on the contact hole 3 in a direction parallel to the upper wiring layer 2 can be prevented. In the third embodiment shown in Fig. 4, a contact region is formed at a side edge of a lower wiring layer 1. In this case, two slits need not be formed at both sides of the contact hole 3. More specifically, only one slit 4a is formed in a region opposite to the side edge with respect to the contact hole 3. The same effect as in the second embodiment can be obtained in the semiconductor device of the third embodiment. In the fourth embodiment shown in Fig. 5, four slits 4a to 4d are formed to surround the contact hole 3 along the four sides of the contact hole 3. The slits 4a and 4c extend parallel to each other along an upper wiring layer 2, and the slits 4b and 4d extend parallel to each other in a direction perpendicular to the upper wiring layer 2. In the semiconductor device of this embodiment, influences of thermal expansion of a lower wiring layer 1 on the contact hole 3 in the direction perpendicular to the upper wiring layer and in the direction parallel to the lower wiring layer 1 can be prevented. In the fifth embodiment shown in Fig. 6, a contact region is formed at a side edge of a lower wiring layer 1 in the same manner as in the third embodiment. In this case, the slits need not be formed near the side edge of the contact hole 3. More specifically, slits 4a and 4c are formed at both sides of the contact hole 3 in a direction parallel to an upper wiring layer 2, and one slit 4b is formed in a region opposite to the side edge with respect to the contact hole 3 in a direction perpendicular to the upper wiring layer 2. The same effect as in the fourth embodiment can be obtained in the semiconductor device of the fifth embodiment. In the seventh embodiment shown in Fig. 7, a contact region is formed at a corner of a lower wiring layer 1. In this case, two slits 4a and 4b are formed in a region opposite to one side edge with respect to the contact hole 3 in a direction parallel to the upper wiring layer 2 and in a region opposite to the other side edge with respect to the contact hole 3 in a direction perpendicular to the upper wiring layer 2, respectively. The same effect as in the fourth embodiment can be obtained in the semiconductor device of the seventh embodiment. The eighth embodiment shown in Fig. 8 exemplifies an important structure in practical applications. Four slits 4a to 4d are formed to surround the contact hole 3 along the four sides of the contact hole 3. In addition, four L-shaped slits 4aa to 4dd are formed at four corners of the contact hole 3 so as to surround the four slits 4a to 4d in a staggered manner. The same effect as in the fourth embodiment can be obtained in the semiconductor device of the eighth embodiment. An influence of thermal expansion of a lower wiring layer 1 on the upper wiring layer 2 contacting the lower wiring layer 1 through the contact hole 3 can be completely prevented. In the ninth embodiment shown in Fig. 9, a contact region is formed at a side edge of a lower wiring layer 1 as in the fifth embodiment. In this case, three slits 4a to 4c are formed in three regions, respectively, as in the fifth embodiment. However, in the ninth embodiment, two slits 4a and 4c formed at both sides of the contact hole 3 in a direction parallel to the upper wiring layer 2 are not separated from the side edge of the lower wiring layer 1 but are in contact therewith. The same effect as in the fourth embodiment can be obtained in the semiconductor device of the ninth embodiment. According to the present invention as has been described above, at least one slit is formed around a contact region of a lower wiring layer 1, and an insulating portion having the same material as that of the insulating layer 6 is embedded to form a rectangular projecting portion, thereby preventing the periphery of the contact region of the lower wiring layer 1 from being moved by thermal expansion. Therefore, the influence of thermal expansion of the lower wiring layer 1 on the upper wiring layer 2 connected to the lower wiring layer 1 through the contact hole 3 formed in the contact region can be prevented. There is therefore provided a semiconductor device capable of preventing an abnormal geometry such as a projection on the upper wiring layer 2 and thus improving flatness of the upper wiring layer 2 and further preventing a short-circuit between the wiring layers. Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described. Accordingly, departures may be made from such details without departing from the scope of the general inventive concept as defined by the appended claims. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: Semiconductor device comprising: a substrate (5); a lower wiring layer (1) formed above said substrate (5); an insulating layer (6) formed on said lower wiring layer (1) having a contact hole (3); an upper wiring layer (2) formed on the insulating layer (6) and being connected to said lower wiring layer (1) through said contact hole (3); at least one slit (4a; 4a, 4b; 4a, 4b, 4c; 4a, 4b, 4c, 4d; 4aa, 4bb, 4cc, 4dd) formed in said lower wiring layer (1) in the vicinity of said contact hole and extending along one side of a contact region which is defined as a region which is located near the contact hole (3) and in contact with the upper wiring layer (2); and an insulating portion (6a; 6a, 6b; 6a, 6b, 6c; 6a, 6b, 6c, 6d; 6aa, 6bb, 6cc, 6dd) formed integrally with the insulating layer (6) and being embedded in said slit (4a; 4a, 4b; 4a, 4b, 4c; 4a, 4b, 4c, 4d; 4aa, 4bb, 4cc, 4dd) whereby movement of the lower wiring layer within said contact region due to thermal expansion during annealing is prevented. A device according to claim 1, characterized in that the length of said at least one slit is not less than a length of one side of said contact hole (3). A device according to any one of claim 1, characterized in that said at least one slit comprises a slit extending in a direction parallel to said upper wiring layer (2). A device according to any one of claim 1, characterized in that said at least one slit comprises a slit extending in a direction perpendicular to said upper wiring layer (2). A device according to any one of claim 1, characterized in that said at least one slit comprises slits extending in a direction parallel to said upper wiring layer (2) and in a direction perpendicular to said upper wiring layer (2). A device according to any one of claim 1, characterized by comprising four slits (4a, 4b, 4c, 4d) along the four sides of a rectangular contact hole (3) and by comprising further outer slits (4aa, 4bb, 4cc, 4dd) which are formed in a staggered manner with respect to said four slits. A device according to claim 6, characterized in that said outer slits comprise L-shaped slits, respectively.

Inventors: KIDA MUNENOBU, KINUGASA MASANORI, SHOJI SHUICHI, TAKAYAMA KOHICHI, KIDA, MUNENOBU, KINUGASA, MASANORI, SHOJI, SHUICHI, TAKAYAMA, KOHICHI, KIDA, MUNENOBU, C/O INTELLECTUAL PROPERTY DIV., KINUGASA, MASANORI, C/O INTELLECTUAL PROPERTY DIV., SHOJI, SHUICHI, C/O INTELLECTUAL PROPERTY DIV., TAKAYAMA, KOHICHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L23
IPC codes: H01L21, H01L23