Pipeline microprocessor having instruction decoder unit performing precedent decoding operation

Abstract: A microprocesseur comprises a decoder for decoding an instruction supplied thereto and producing a decoded instruction, storage means for temporarily storing said decoded instruction, means for producing an execution ready signal when said decoded instruction stored in said storage means is brought into a ready state for execution, means responsive to said execution ready signal for reading out said decoded instruction from said storage means, an execution unit for receiving and executing the read-out decoded instruction, means responsive to information representing that a conditional branch instruction is decoded by said decoder for masking the execution ready signal for at least one instruction which is decoded by said decoder and stored in said storage means during an unsettled period of branch condition of said conditional branch instruction, and means responsive to branch success or branch failure determined under the settled branch condition of said conditional branch instruction for removing said masking of the execution ready signal or changing the execution ready signal to an invalid state.

Description: BACKGROUND OF THE INVENTION The present invention relates to a pipeline microprocessor and, more particularly, to an improvement in an instruction decoder unit in a pipeline microprocessor. In a pipeline microprocessor, respective units, such as an instruction prefetch unit for prefetching an instruction, an instruction decoder unit (IDU) for decoding the prefetched instruction, a memory management unit for calculating an effective address of operand data in response to operand access information from IDU and an execution unit (EXU) for executing the instruction in accordance with decoded instruction information from IDU, perform an individually allocated operation in accordance with a predetermine pipeline flow. IDU is thus decoding an instruction which is a few steps late with respect to an instruction being currently executed by EXU, in general. A conditional branch instruction is often written in a string of instructions to be executed and is employed to control an instruction stream to be executed by whether or not the branch condition designated by the conditional branch instruction is satisfied under the content of a program status word controlled by the result and/or state of the instruction executed by EXU. When IDU decodes the conditional branch instruction, it detects the branch condition designated by that instruction. However, if the instruction being currently executed by EXU and/or a non-executed instruction or instructions between the currently executed instruction and the conditional branch instruction may change the content of the program status word, the branch condition is not settled until EXU completes the execution of such instruction(s). Therefore, such a construction is generally adopted that when IDU decodes the conditional branch instruction it stops to decode subsequent instructions until the branch condition is settled. This means, however, that the pipeline processing flow is suspended to cause the processing-speed neck of the microprocessor. Thus, the conditional branch instruction disturbs the pipeline processing flow of the microprocessor. US-A-3,771,138 discloses a pipelined processing unit of a Digital computer, wherein an apparatus for sharing the processing capability of the computer between two independent instruction streams is provided. The apparatus includes a buffer for instructions of each of the independent instruction streams. These buffers are connected to a selection means which samples various machine resources and determines which instruction of the two independent instruction streams is to be executed next. The selection means performs a control so as to determine in which one of registers 50, 54 and 56 respective instructions contained in one instruction stream are to be stored in accordance with the full or empty state of each register, the operant access condition and the instruction condition. US-A-3,490,005 discloses a microprocessor comprising a decoder for decoding an instruction supplied thereto and producing a decoded instruction code, storage means for temporarily storing said decoded instruction code, and an execution unit for receiving and executing a decoded instruction code. In none of these documents is provided any facility allowing the decoder to continue to decode instructions while the unsettled period of a conditional branch instruction is detected. SUMMARY OF THE INVENTION Therefore, an object of the present invention as defined in the appended claims is to provide an improved microprocessor in which the disturbance of a pipeline processing flow caused by a conditional branch instruction is suppressed. Another object of the present invention is to provide a microprocessor including an instruction decoder unit having a precedent-decoding function in which at least one instruction subsequent to a conditional branch instruction or an instruction at a branch destination address is decoded, in advance, during a branch condition unsettled period. A microprocessor according to the present invention is disclosed in claim 1. Claims 2 and 3 disclose particular embodiments thereof. Thus, the decoder continues to decode an instruction even after the conditional branch instruction is decoded. However, the ready state for execution of the instruction, which is decoded during the unsettled period of the branch condition, is masked until the branch condition is settled. In response to the branch success or branch failure determined under the settled branch condition, the ready state for execution is finally controlled. The pipeline processing flow is thereby stopped or disturbed even after the conditional branch instruction is decoded. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram representative of an embodiment of the present invention; Fig. 2 is a block diagram representative of an instruction decoder unit (IDU) shown in Fig. 1; Figs. 3A and 3B are circuit diagrams representative of blocks shown in Fig. 2; Figs. 4 and 5 are timing charts representative of operations of IDU shown in Figs. 2 and 3 for explaining a precedent decoding function; Fig. 6 is a block diagram representative of another embodiment of the present invention; Fig. 7 is a circuit diagram representative of an output circuit 408' shown in Fig. 6; and Fig. 8 is a block diagram representative of a main part of a bus interface unit (BIU) shown in Fig. 1 or 6. DETAILED DESCRIPTION OF THE EMBODIMENTS Referring to Fig. 1, a microprocessor 10 according to an embodiment of the present invention includes a bus interface unit (BIU) 20 which performs operand data read/write operations via a system bus 21 with respect to a memory and peripheral I/O devices (not shown). A prefetch/predecode control unit (PDU) 30 communicates with BIU 20 via a bus 22 to perform an instruction prefetch operation. PDU 30 temporarily stores the prefetched instruction stream and predecodes it to make a decoding operation easy by an instruction decoder unit (IDU) 40. Namely, PDU 30 divides the instruction stream into an operation code, addressing mode information, data and so forth and transfers them to IDU 40 via a bus 31 as an instruction code. IDU 40 decodes the instruction code thus transferred and supplies via a bus 42 a memory management unit (MMU) 50 with address information necessary for calculating an effective operand address. IDU 40 further supplies via a bus 41 an execution unit (EXU) 60 with a decoded instruction processing code having arithmetic/logic operation designation information, an operand location (general register, memory or other I/O device) information and so forth. MMU 50 calculates the effective address of operand data in response to the address information from IDU 40, translates it into a real address and issues an operand access request to BIU 20. When MMU 50 receives branch address information from IDU 40, it supplies a branch address to PDU 30 via a bus 52. MMU 50 supplies a TLENDI signal to IDU 40 to inform that the address calculation and translation is completed. EXU 60 communicates with BIU 20 via a bus 61 in response to the decoded instruction processing code from IDU 40 and starts to execute the instruction at a time when operand data are ready. IDU 40 includes a plurality of queue registers (Fig. 2) each for temporarily storing the decoded instruction processing code and supplies an IDQFULL signal to PDU 30 when all the queue registers stores non-executed decoded instruction code. PDU 30 thereby suspends to transfer the instruction code to IDU 40. When all the queue registers are brought into an empty state, IDU 40 supplies an IDQEMP signal to EXU 60 to suspend the instruction execution by EXU 60. When EXU 60 fetches the decoded instruction code, it returns an IDQACK signal to IDU 40. EXU 60 includes a program status word register (PSW) 65, the content of which is controlled and changed by the result and/or state of the executed instruction, and judges whether or not the branch condition designated by a conditional branch instruction supplied from IDU 40 is satisfied with reference to the content of PSW 65. The judging resultant is transferred to IDU 40 as a TAKEN signal. In response to this signal, IDU 40 generates a VCAN signal in case of branch success (i.e., the branch condition being satisfied) and a UCAN signal in case of branch failure (i.e., the branch condition being not satisfied). These signals VCAN and UCAN are supplied to PDU 30 and BIU 20 to inform the branch success or failure. BIU 20, PDU 30, IDU 40, MMU 50 and EXU 60 operate in a pipeline manner and thus perform an individually allocated operation in parallel to one another. Referring to Fig. 2, IDU 40 includes a decoder 400 decoding an instruction code supplied via the bus 31 from PDU 30 in accordance with a decoding sequence controlled by sequencer 401. The address information of the coded information is transferred to MMU 50 via the bus 42 and the decoded instruction code is supplied via a bus 413 in common to three queue registers (IDQ0, IDQ1, IDQ2) 402 - 404. Each of IDQ0 - 2 (402 - 404) temporarily stores the decoded instruction code on the bus 413 in response to a corresponding one of write-strobe signals QSLSTB0 - 2 applied to a write-enable terminal WE thereof and reads out the stored decoded code therefrom in response to a corresponding one of read-strobe signals EXQSL0 - 2 applied to a read-enable terminal RE thereof. These signals QSLSTB0 - 2 and EXQSL0 - 2 are controlled by a queue register read/write control circuit 405. Specifically, this control circuit 405 generates sequentially the signals QSLSTB0 - 2 one by one in response to an IDQSTB signal, which is generated by the sequencer 401 each time the decoding of one instruction is completed, and thus causes IDQ0 - 2 (402 - 404) to sequentially store the coded instruction code from the decoder 400. The circuit 405 further generates sequentially the signals EXQSL0 - 2 one by one in response to IDQACK signal from EXU 60 and a corresponding one of queue ready signals IDQRDY0 - 2 from a queue ready control circuit 407 and thus causes IDQ(0 - 2) to sequentially transfer the stored code onto the bus 41 coupled to EXU 60. The queue ready control circuit 407 generates one of IDQRDY0 - 2 signals in response to TLENDI signal representing that the address calculation and translation of operand data necessary to the decoded instruction stored in the corresponding one of IDQ0 - 2 (402 -404) is completed. Therefore, each of IDQRDY0 - 2 signals represents the ready state for execution of the decoded instruction stored in the corresponding one of IDQ0 - 2 (402 - 404). IDQRDY0 - 2 signals are cleared by clear signals VQCLR0 - 2 from a queue ready clear control circuit 411, respectively. The decoder 400 further produces a CBRA signal representing that a conditional branch instruction is decoded. In response to this CBRA signal, a branch queue register pointer 406 temporarily stores the location number BRPT0 - 2 of the queue register (IDQ) that stores the decoded code of the conditional branch instruction. The decoder 400 further produces a FLAGM signal representing that an instruction now decoded may change the content of PSW 65 of EXU 60. A branch condition unsettled period detector 409 temporarily latches FLAGM signal and thus informs a period, during which the branch condition designated by the conditional branch instruction is not settled, by changing an FHZR signal to an active level. In response to CBRA signal, a branch control signal output circuit 408 is activated. However, this circuit 408 holds both of VCAN and UCAN signals at an invalid level during the active level of FHZR signal. When FHZR signal changes to an inactive level, the circuit 408 outputs valid VCAN (branch success) and UCAN (branch failure) signals in response to TAKEN signal from EXU 60. Since IDU 40 continues to decode an instruction subsequent to the conditional branch instruction or an instruction at a branch address during the unsettled period of the designated branch condition, a queue ready mask control circuit 410 is provided. This circuit 410 masks each of IDQRDY0 - 2 signals by the corresponding one of mask control signals INV0 - 2 and removes INV0 - 2 signals in response to BREN signal from the circuit 408. BREN signal represents that the output circuit 408 outputs valid VCAN and UCAN signals. During the mask state of IDQRDY signal, the control circuit 405 does not generate the corresponding EXQSL signal, so that the corresponding decoded instruction is not transferred to EXU 60. If the instruction or instructions, which were decoded during the unsettled period of the branch condition, are changed to an instruction or instructions not to be executed due to the branch success or branch failure, the clear circuit 411 detects such instruction(s) by inverted mask control signal INV 0 - 2 and clears the corresponding one or ones of IDQRDY0 - 2 signals. When the valid VCAN signal is outputted, the queue read/write control circuit 405 fetches the pointer data BRPT0 - 2 from the pointer 406, which data represents the queue register IDR0, 1 or 2 storing the decoded conditional branch instruction, and thus causes the queue register next to the queue register represented by the pointer data BRPT0 - 2 to store a new decoded instruction. The decoded instruction, which was decoded during the unsettled period of the branch condition, is thereby deleted from the queue register. The above-described operations of the respective circuits 405 to 411 are realized by circuit constructions shown in Figs. 3A and 3B. Fig. 3A shows the circuits 405, 406, 408 and 409 and Fig. 3B shows the circuits 407, 410 and 411 related to the queue ready control. A detailed operation will be described below with reference to Figs. 1 to 3 and further to timing charts shown in Figs. 4 and 5. In this embodiment, instructions subsequent to a conditional branch instruction are decoded precedently to the branch condition settlement. Further, Fig. 4 shows the case where the branch condition is not satisfied, i.e. the precedently decoded instructions become valid. In contrast, Fig. 5 shows the case where the branch condition is satisfied so that the instruction to be executed next to the conditional branch condition is an instruction stored at a branch address. The precedently decoded instructions thereby become invalid. In the timing chart shown in Fig. 4 first, it is assumed that D-type flip-flops (D-F/Fs) 307, 317 and 360 store "1" at the time the decoder 400 starts to decode an instruction before a conditional branch instruction . At this time, moreover, it is assumed that EXU 60 is executing an instruction 8 ○ whose decoded code was stored in IDQ2(404) and IDQ0(402) stored the decode code of an instruction 9 ○ between the instructions 8 ○ and . When the decoder 400 completes to decode the instruction , the sequencer 401 produces IDQSTB signal, so that an AND gate 312 produces QSLSTB1 signal. The decoded code of the instruction is thereby stored into IDQ1(403). An S-R type flip-flop (SR-F/F) 303 is set. The operand address information is transferred to MMU 50. In response to delayed IDQSTB signal via a delay circuit 314, each of D-F/Fs 316 to 318 fetches an input at D-terminal thereof. Although not shown, multiplexers (MPXs) 319 to 321 are controlled by VCAN signal and selects respectively the Q-outputs of F/Fs 316 to 318 when VCAN signal assumes the inactive level (low level). Accordingly, the Q-output "1" of F/F 317 is transferred to F/F 318 and F/Fs 316 and 317 fetches "0". Since the instruction is an arithmetic/logic operation instruction which may change the content of PSW65, the decoder 400 further produces FLAGM signal, so that SR-F/F 506 is set. When MMU 50 completes the operand address calculation and translation, it produces TLENDI signal, so that SR-F/F 353 is set. Since SR-F/Fs 366 to 368 are in a reset state initially, they produce high-level INVO -2 signals at the respective Q -outputs. Therefore, IDQRDY1 signal is changed to the active high level to indicate that the instruction is read for execution. The active high level IDQRDY1 signal opens an AND gate 507 to change FHZR signal to the high level. If the instruction 8 ○ or 9 ○ may also change the content of PSW 65, the corresponding F/F 502 or 510 was in the set state, so that FHZR signal has already assumed the high level. By the delayed TLENDI signal via a delay circuit 362, D-F/Fs 359 to 361 fetches an input at D-terminal thereof. Since MPXs 363 to 364 are also controlled by VCAN signal, the Q-output "1" of F/F 360 is fetched by F/F 361 and F/Fs 359 and 360 fetches "0". IDQRDY1 signal holds the active high level by F/F 354. The decoder 400 then starts to decode the conditional branch instruction . During this decoding, EXU 60 completes the execution of the instruction 8 ○ and then produces an instruction execution end signal EXQEND to reset SR-F/F 518. Thus, each of SR-F/Fs 502, 506 and 510 stores the data representing whether or not the decoded instruction stored in the corresponding one of IDQ0 - 2 (402-404) may change the content of PSW 65 and SR-F/F 518 stores the data representing whether or not the instruction being currently executed by EXU 60 may change the content of PSW 65. EXU 60 thereafter fetches the decoded instruction transferred onto the bus 41. In the present description, since EXQSLO assumes the active high level, the decoded code of the instruction 9 ○ stored in IDQ0 (402) is fetched into EXU 60. EXU 60 produces IDQACK signal to inform the decoded code being fetched. In response to this signal, the data of F/F 502 representing whether or not the instruction 9 ○ may change the content of PSW 65 is transferred to F/F 518. In response further to IDQACK signal, Q-output "1" of F/F 307 is fetched into F/F 308 and F/F 307 fetched data "0", so that IDQRDY0 signal is inverted from the high level to the low level. In response to this inversion, a one-shot pulse generator (OS) 504 generates a one-shot pulse EXQEO to reset F/F 502. By the EXQEO pulse, an OR gate 373 of the queue ready clear control circuit 411 produces the clear signal VQCLRO to reset F/Fs 301 and 353. IDQRDY signal is thereby changed to the inactive low level. Since F/F 308 fetches data "1" and IDQRDY1 signal has already assumes the active high level, EXQSL1 signal takes the active high level to cause IDQ1(403) to read out the decoded code of the instruction onto the bus 41. EXU 60 is executing the instruction 9 ○. In response to IDQSTB signal representing the decoding completion of the conditional branch instruction, QSLSTB2 signal is generated, so that the decoded code of the instruction is stored into IDQ2(404). F/F 303 is set and the data "1" is shifted from F/F 318 to F/F 316. The branch condition of the conditional branch instruction is delivered via a bus 412 to EXU 60 precedently. FLAGM signal is not produced (i.e., being held at the low level), so that F/F 510 maintained the reset state. The decoder 400 further produces CBRA signal due to the decoding the conditional branch instruction . In response to CBRA and QSLSTB2 signals, an AND gate 341 supplies a latch-enable signal to a latch circuit 322. Thus, the location number of IDQ2 storing the decoded code of the instruction , i.e. IDQ2 = "001", is latched into the latch circuit 322. The AND gate 341 further sets SR-F/F 343. Since the output CBRAQL of F/F 343 is delayed by a delay circuit 372 and then supplied to AND gates 369 to 371, SR-F/F 368 is free from the set state. INV 2 is thereby held at the high level. While an AND gate 327 is made open by CBRAQL signal, at least F/F 506 is in the set state and IDQRDY 1 signal assumes the active high level, so that FHZR signal from the OR gate 519.is at the high level. The output of AND gate 327 is thereby held at the low level. In response to TLENDI signal representing the completion of the branch address calculation and translation, SR-F/F 355 is set to change IDQRDY2 signal to the high level. The data "1" is shifted from F/F 361 to F/F 359. Since IDU 40 decodes instructions subsequent to the conditional branch instruction precedently to the branch condition settlement, the decoder 400 starts to decode the instruction . During this decoding, EXU 60 completes the execution of the instruction 9 ○ and resets F/F 518 by EXQEND signal. EXU 60 further judges whether or not the branch condition precedently delivered from the decoder 400 is satisfied with reference to the content of PSW 65 each time the current instruction execution is completed, and then outputs the judging resultant as TAKEN signal. However, FHZR signals takes at this time the high level to indicate the branch condition unsettled period, and therefore AND gates 324 and 325 have the closed state. Valid VCAN and UCAN signals are thereby outputted. Since EXQSL1 signal assumes the signal level, EXU 60 fetches the instruction and then produces IDQACK signal. By this signal, the stored data "1" of F/F 506, representing that the instruction may change the content of the PSW 65, is transferred to F/F 518 to maintain FHZR signal at the high level. Further by IDQACK signal, EXQSL1 signal is changed to the low level, so that F/Fs 506, 354 and 302 are reset. F/F 309 fetches the data "1". In response to the decoding completion of the instruction , QSLSTBO signal is produced to cause IDQ0(402) to store the decoded code of the instruction . If this instruction may change the content of PSW 65, FLAGM signal is further produced and thus F/F 502 is set. Since IDQRDY0 signal is not yet produced at this time, the AND gate 503 is closed. F/F 302 is set and the data "1" is shifted from F/F 316 to F/F 317. The AND gate 369 is opened by QSLSTBO signal and the delayed CBRAQL signal to set F/F 366. The queue mask signal INVO is thereby changed to the active low level to indicate that the instruction was decoded precedently to the branch condition settlement. Accordingly, even when F/F 353 is set in response to TLENDI signal representing the completion of the operand address calculation and translation for the instruction , IDQRDYO signal is masked to the low level by INV0 signal and the AND gate 350. Since IDQRDYO signal is masked, the content of F/F 502 is also masked by the AND gate 503. That is, FHZR signal is not influenced by the instruction which was decoded precedently to the branch condition settlement. The decoder 400 advances the decoding operation to decode an instruction , so that the decoded code thereof is stored into IDQ1(403). Similarly to the case of the instruction , the ready signal IDQRDY1 for the instruction and the data of F/F 506 are masked. Since all IDQO-2 (402-404) stores the decoded codes of the instructions to which are yet not executed, an AND gate 300 produce IDQFULL signal of the active high level. In response thereto, the sequencer 401 suspends the decoding operation of the decoder 400 and PDU 30 also suspends the transfer of an instruction. When EXU 60 completes the execution of the instruction , F/F 518 is reset and thus FHZR signal is inverted to the low level. Namely, the circuit 409 informs the output circuit 408 of the elapse of the branch condition unsettled period by the low level of FHZR signal. As a result, AND gates 324 and 325 are opened. At this time, EXU 60 already produces TAKEN signal representing whether or not the branch condition of the conditional branch instruction was satisfied with reference to the content of PSW 65 controlled by the execution of the instruction . In the present description, since the branch condition is not satisfied, TAKEN signal assumes the low level. Accordingly, the output circuit 408 changes UCAN signal to the high level with holding VCAN signal at the low level to inform the branch failure. The output BREN of an OR gate 323 receiving VCAN and UCAN signals resets F/F 343, so that both of VCAN and UCAN signals are changed to invalid (inactive) level. Further by BREN signal, F/Fs 366 to 368 are reset to change the mask signals INVO and 1 to the inactive high level. Thus, IDQRDY0 and 1 signals are released from the masked state and changed to the active high level, respectively. The mask state of F/F 502 and 506 are also removed. If at least one of the instructions and may change the content of PSW 65, FHZR signal is again changed to the high level. Thus, the instructions and are brought into a valid state andhave a ready state for execution. Since EXQSL2 signal is produced at the time point of the execution completion of the instruction , EXU 60 fetches the instruction and then returns IDQACK signal. EXQSL2 is thereby inverted to the low level and thus F/F 355 is reset to change IDQRDY2 signal to the low level. Moreover, F/F 303 is reset to change IDQFULL signal to the low level, so that IDU 40 resumes the decoding operation to decode an instruction . Furthermore, since the data "1" is shifted from F/F 309 to F/F 307, EXQSLO signal changes to the high level to cause IDQ0 (402) to transfer the decoded code of the instruction onto the bus 41. Although EXU 60 fetches the conditional branch instruction , since this instruction has already substantially been executed, EXU 60 executes the instruction as a No-operation instruction. That is, any states and conditions of EXU 60 do not change. EXU 60 thereafter fetches the instruction and starts to execute it. As apparent from the above description, even if the conditional branch instruction is decoded, PDU30, IDU40 and MMU50 continue to perform the respective subsequent operations in the pipeline flow. Moreover, the respective operations precedent to the branch condition settlement become valid in response to the branch failure, so that the pipeline processing flow of the respective. units are not stopped substantially. On the other hand, in case where the branch condition of the conditional branch instruction is satisfied, VCAN (branch success) signal is changed to the active high level, as shown in Fig. 5, so that AND gates 374 and 376 of the clear control circuit 411 produces the clear signals VQLCR0 and 1 to reset F/Fs 354 and 355. Accordingly, even when INV0 and 1 signals changes to the high level to release the masked state, IDQRDY0 and 1 signals are maintain at the low level. The decoded instructions and thus become invalid and is not executed. F/Fs 301 and 302 are also reset to change IDQFULL signal to the low level. By VCAN signal, BIU 20 and PDU 30 are commanded to fetch an instruction at the branch address. Further, VCAN signal supplies a clock signal via OR gates 315 and 560 to F/Fs 316 to 318 and 359 to 360 and commands MPXs 319 to 321 and 364 to 366 to select the pointer data "001" from the latch circuit 322. As a result, the data "1" is fetched into F/Fs 316 and 359, whereas F/Fs 317, 318, 360 and 361 fetches data "0". Thus, IDQ0(402), which is next to IDQ2(404) storing the conditional branch instruction , is designated as a queue register to store the decoded code of the instruction at the branch address. The instruction stream to be transferred to EXU 60 is thereby not disturbed. In response to IDQACK signal representing that EXU 60 fetched the instruction , F/F 355 is reset to change IDQRDY2 to the low level. For this reason, all the IDQRDY0 - 2 signals assume the low level to cause a NOR gate 310 to produce IDQEMP signal of the active high level. That is, EXU 60 is informed of the information representing that no one of IDQ0-2 (402 -404) stores the decode code of an instruction having an execution ready state. In response thereto, EXU 60 stops to fetch the decoded code from IDU 40 and thus suspends the program execution. An error in operation of EXU 60 is thereby prevented. An instruction at the branch address is thereafter transferred to IDU 40 from PDU 30 and decoded by IDU 40. The decoded code of the instruction is stored into IDQ0(402). When the operand address calculation and translation for the instruction is completed, IDQRDY0 signal changes to the active high level and IDQEMP signal is inverted to the low level. EXU 60 thereby resumes the operation and then fetches and executes the decoded code of the instruction . Thus, in the case of branch success, although the decoding operation and address calculation and translation operation for the instructions and becomes invalid, the pipeline processing flow is not stopped until the branch condition is settled. Since the address calculation and translation of the branch address has already been completed, PDU 30 can be constructed so as to prefetch not only instructions to but also the instructions and . In this case, PDU 30 can transfer the instructions and to IDU 40 in response immediately to VCAN, branch success, signal. The stop of the pipeline flow after the production of VCAN signal is suppressed at a minimum. In Figs. 4 and 5, when the instruction does not change the content of PSW 65 and the instruction 9 ○ may change the content of PSW 65, the level of TAKEN signal is settled at the time of completion of the instruction 9 ○ and thus valid VCAN and UCAN signals are produced. It is apparent that the detailed circuit construction shown in Figs. 3A and 3B for the circuits 405 to 411 can be modified and changed for realizing the substantially similar functions and operations thereof. Turning to Fig. 6, there is shown a microprocessor according to another embodiment of the present invention, wherein the same constituents as those shown in Fig. 1 are denoted by the same reference numerals. In this embodiment, a prefetch/predecode/branch-predict unit (BPPDU) 600 is employed in place of PDU 30 of Fig. 1. This unit 600 performs a branch-predict operation in addition to the instruction prefetch and predecoding operations. For the branch-predict operation, BPPDU 600 includes a register (CPFIAR) 601 for storing an address of an instruction being currently prefetched, a register (BRAIAR) 602 for storing an address of a conditional branch address (called hereinafter "branch source address), a register (BRDTAR) 603 for storing a branch destination address designated by the conditional branch instruction and a comparator (COMP) 604. The content of CPFIAR 601 is ordinarly updated by byte numbers of the prefetched instruction. BRAIAR 602 stores the branch source address into which the conditional branch instruction which was prefetched and executed in the past is stored. Accordingly, when that conditional branch instruction is prefetch again, COMP 604 produces a branch-predict hit signal HITBRA. BPPDU 600 thus prefetches the instruction at the branch destination address by use of BRDTAR 603, not instructions subsequent to the conditional branch instruction. HITBRA signal is supplied to an output circuit 408' of IDU 40, this circuit 408' being slightly different from the circuit 408 of Fig. 3A, as shown in Fig. 7. More specifically, HITBRA signal sets SR-F/F 701. The Q-output thereof control a multiplexer (MPX) 702. When the Q-output of F/F 701 assumes the high level, MPX 702 outputs the outputs of AND gates 324 and 325 as UCAN and VCAN signals, respectively. On the other hand, in case of the low level output of F/F 701, the outputs of AND gates 324 and 325 are derived as VCAN and UCAN signals, respectively. The operation of the microprocessor shown in Figs. 6 and 7 is basically the same as that shown in Figs. 4 and 5 except that the instructions transferred after the prefetch of the conditional branch instruction may be different from those shown in Figs. 4 and 5. More specifically, when HITBRA signal is produced by prefetching the conditional branch instruction , F/F 701 is set and BPPDU 600 prefetches the instructions 50 at the branch address and instructions , and so forth subsequent to . Accordingly, the instruction stream to be decoded indicated as "Decoding Operation" in Figs. 4 and 5 is → → → ···. The branch condition of the instruction is settled at the end of the execution of the instruction . If the branch condition is satisfied, the outputs of AND gates 324 and 325 are changed to the high level and the low level, respectively. Since F/F 701 is set to output the high level at Q-output thereof, the output of AND gate 324 is transferred as UCAN signal. Therefore, the decoded code of the instructions and stored in IDQ0 and 1 (402 and 403) becomes valid and then executed by EXU 60. On the other hand, in case where the branch condition is not satisfied, since VCAN signal assumes the active high level, the instructions and becomes in valid. The prefetch and predecode operations for instructions , and so forth are thereby performed. When BPPDU 600 prefetches the conditional branch instruction with the miss-hit of the branch predict, the operations shown in Figs. 4 and 5 are performed. In the above embodiments, the operand data access for instructions which was decoded precedently to the branch condition settlement is required to be made after the branch condition settlement. For this purpose, BIU 20 includes an access information storage 800, as shown in Fig. 8. This storage 800 includes three buffer registers ADR0(801), ADR1(803), ADR2(805) of a queue structure, each of which temporarily store an operand address. Further, ADR0 - 2 (801, 803 and 805) are accompanied by tag flag BT0(802), BT1(804), BT2(805), respectively, supplied with CBRAQL signal (Fig. 3). Accordingly, the addresses of operands for the instruction which are decoded during the branch condition unsettled period are temporarily stored in the storage 800 together with the tag information representing that unsettled period. An access controller 810 receives the contents of BT0 - 2 (802, 804 and 805) and suspends the operand access if the tag information is stored therein. When VCAN signal is produced, the controller 810 invalidates the contents of the storage 800. On the other hand, in the case of UCAN signal, the operand access is made by use of the storage 800. Each of ADR0 - 2 (801, 803 and 805) can be further added with access priority data, respectively. In this case, the operand access is started from the register ADR having the highest priority in response to UCAN signal. The present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention.

Claims: A microprocessor comprising a decoder (400) for decoding an instruction supplied thereto and producing a decoded instruction code, storage means (402-404) for temporarily storing said decoded instruction code, and an execution unit (60) for receiving and executing a decoded instruction code, characterized in that said microprocessor further comprises: ready control means (407) for producing an execution ready signal (IDQRDY) when said decoded instruction code stored in said storage means is brought into a ready state for execution, reading means (405) responsive to said execution ready signal for reading out said decoded instruction code from said storage means and supplying the read-out decoded instruction code to said execution unit, masking means (410) responsive to information representing that a conditional branch instruction is decoded by said decoder for masking the execution ready signal for at least one instruction which is decoded by said decoder and stored in said storage means during an unsettled period of a branch condition designated by said conditional branch instruction, and branch control means (408, 409, 411) responsive to branch success or branch failure determined under a settled state of said branch condition designated by said conditional branch instruction for removing said masking of said execution ready signal or changing the execution ready signal to an inactive level to invalidate the decoded instruction code. The microprocessor as claimed in claim 1, characterized in that said storage means includes a plurality of registers (402-404) each temporarily storing the decoded instruction code supplied from said decoder, and that said ready control means (407) produces said execution ready signal for each of said registers when the decoded instruction code stored in the respective ones of said registers is brought into a ready state for execution. The microprocessor as claimed in claim 2, characterized in that said microprocessor further comprises a pointer (406) temporarily storing a location number designating one of said registers (402-404) which stores the decoded instruction code of said conditional branch instruction, and that said location number stored in said pointer is used to cause another one of said registers next to said one of said registers to store a new decoded instruction code when said branch failure occurs.

Inventors: SUZUKI NARIKO, SUZUKI, NARIKO, SUZUKI, NARIKO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G06F9
IPC codes: G06F9