Interunit communication system and resetting method

Abstract: The invention provides an interunit communication system which comprises a main unit and a plurality of subunits and executes a communication between the units by a microcomputer of each unit. The system comprises: power producing means, provided for each subunit, for producing a driving power for the microcomputer of the subunit by a power which is supplied from the main unit through a power line; resetting means, provided for each subunit, for resetting the microcomputer of the subunit in the case where the power supply was restarted after the power supply from the main unit had been shut off; detecting means, provided for the main unit, for detecting a runaway of the microcomputer of the subunit on the basis of a reception state from a signal line for communication; power shut-off means, provided for the main unit, for shutting off the power supply to the subunit when the detecting means detects the runaway of the microcomputer; and power restarting means for restarting the power supply to the subunit.

Description: The present invention relates to an interunit communication system for executing a communication between a main unit and one or a plurality of subunits which are controlled by the main unit and also relates to a method of resetting the subunits by the main unit. Related Background Art Hitherto, in such a kind of system for executing the interunit communication, power source lines, communication lines, resetting lines, and other signal lines are individually provided and a plurality of lines are combined and the units are connected. On the other hand, there also exists a system in which in order to omit the resetting lines among the above lines, each subunit has therein a circuit to individually reset the self microcomputer. However, in the system in which in order to reset the microcomputer in the subunit, a plurality of lines including the resetting line are combined to connect the units, in addition to a drawback such that the combining cost is necessary, there is a large drawback such that in the case where noises were mixed onto the resetting lines the microcomputer in the subunit is reset by the noises. On the other hand, in the system in which the resetting line is omitted by providing the resetting circuit into the subunit, if the microcomputer in the subunit ran away, there is no means for detecting such a runaway of the microcomputer and for automatically resetting the microcomputer. Therefore, each device in the subunit runs away, resulting in that a serious damage is given to the apparatus. To stop the runaway, a runaway detecting circuit must be provided for each subunit. There is a drawback such that when the number of subunits increases, the costs of the runaway detecting circuits also remarkably increase. It is a concern of the invention to eliminate the above-mentioned drawbacks. An aspect of the invention provides a resetting method in which one unit can reset other units without providing any resetting line among the units. Another aspect of the invention provides an interunit communication system in which resetting lines among units can be omitted and in the case where a microcomputer ran away, the microcomputer can be reset without providing any runaway detecting means for each subunit. Patent Specification No. WO 8805 569 discloses a microcomputing system in which a dedicated driving circuit common to all the computers is capable of resetting a failed computer. U.S. Patent Specification No. 4,593,349 discloses a CPU connected to a peripheral power control sequencer which is capable of carrying out emergency power off. Both of these prior documents disclose the use of a dedicated reset circuit. In accordance with a first aspect of the present invention there is provided a system for resetting one subunit by a main unit as set out in claim 1. In accordance with a second aspect of the present invention there is provided a method for resetting one subunit by a main unit as set out in claim 7. In order that the present invention may be more readily understood, embodiments thereof will now be described by way of example and with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram showing the connection of a main unit and subunits according to an embodiment of the invention; Fig. 2 is a circuit diagram showing an arrangement of the main unit in the embodiment; Fig. 3 is a circuit diagram showing an arrangement of the subunit in the embodiment; Fig. 4 is a timing chart showing a resetting sequence of a subCPU in the embodiment; Fig. 5 is a circuit diagram showing the second embodiment of the invention; and Fig. 6 is a circuit diatram showing the third embodiment of the invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS An embodiment regarding the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 1 is a circuit diagram showing the connection of a main unit and subunits according to an embodiment of the invention. In the embodiment, three subunits 4 to 6 are connected to a main unit 3. A power source unit 7 is also connected to the main unit 3. A power source of +5V, a power source of +24V, and a resetting signal are supplied from the power source unit 7 to the main unit 3. Fig. 2 is a circuit diagram showing an arrangement of the main unit 3. The main unit 3 has: a one-chip microcomputer (hereinafter, referred to as a CPU) 1 having therein an ROM and an RAM; and a power source circuit 8 to supply power sources to the subunits 4 to 6. The power source circuit 8 has: transistors Q₁ to Q₃; resistors R₁ to R₆; a Zener diode ZD₁; and an inverter IC₁. Particularly, the resistor R₃ is a posistor whose resistance value increases with an increase in temperature of the device. In addition, other loads 18, 19, and 20 of 24V are connected to the CPU 1. Fig. 3 is a circuit diagram showing an arrangement of the subunits 4 to 6. Although three subunits exist, since they have the same construction, only the first unit 4 is shown in Fig. 3. Each of the subunits 4 to 6 has: a CPU having therein an ROM and an RAM; and a resetting and subpower source circuit 9. The resetting and subpower source circuit 9 has: resistors R₁₀ and R₁₁; a diode D₁₀; a Zener diode ZD₁₀; and a capacitor C₁₀. On the other hand, transistors Q₁₀ to Q₁₃ and diodes D₁₁ to D₁₄ are connected to the CPU 2. In the above construction, the CPU 1 in the main unit 3 is made operative by the power source of +5V which is supplied from the power source unit 7 and a resetting signal RESET. A power source of +24V is also supplied. When the CPU 1 is reset, the input/output port is set to a high impedance. An output of the inverter IC1 is set to the low level. The transistors Q₁ and Q₃ are turned off. No power source is supplied from power source output terminals J₁₋₁, J₂₋₁, and J₃₋₁ to the subunits. A voltage which is obtained by dividing a power source voltage V D to the subunits 4 to 6 by the resistors R₄ and R₅ is input to an analog-digital conversion port AN (hereinafter, referred to as an A/D port AN) of the CPU 1 and is monitored. After the CPU 1 confirmed that the power sources to the subunits 4 to 6 had completely been shut off on the basis of an input of the A/D port AN, an output port O₁ is set to the low level to thereby turn on the transistors Q₁ and Q₃ and the power sources are supplied to the subunits 4 to 6. When the power source is supplied to an input terminal J₁₀₁₋₁ of the subunit 4, a power source V cc of the CPU 2 of the subunit is formed by the resistor R₁₀ and Zener diode ZD₁₀. At this time, as shown in Fig. 4, although the power source V cc of the CPU 2 rises at time t ri , the rising timing of the resetting input RESET of the CPU 2 is delayed by the resistor R₁₁ and a time constant of the capacitor C₁₀. The CPU 2 is reset for the time interval of t re when the voltage level is a predetermined voltage level or less. It is now assumed that when the CPUs 1 and 2 are controlling the system by starting the operations, the CPU 2 erroneously operated and ran away due to, for instance, electrostatic noises or the like. In this case, the CPUs 1 and 2 periodically transmit and receive information by a three-line type serial communication which is connected by a serial input SI, a serial output SO, and serial clocks SCK₁. However, when the CPU 2 runs away, the communication is interrupted. Therefore, the CPU 1 can detect that the CPU 2 has run away. Fig. 4 is a timing chart showing a sequence to reset the CPU 2 in the above case. First, the output port O₁ of the CPU 1 is set to the high level and the transistors Q₁ to Q₃ are turned off, thereby shutting off the power sources to the subunits 4 to 6. Since the subunits 4 to 6 have not only resistive loads but also capacitive loads and the like, the power source voltage is not soon set to 0V but gradually approaches to 0V with a certain time constant. When the power source voltage decreases to a level lower than a Zener voltage V z of the Zener diode ZD₁₀, the power source V cc of the CPU 2 also gradually drops. As mentioned above, in the main unit 3, the subunit power source is also input to the CPU 1 by the resistors R₄ and R₅ and monitored. As in the resetting process upon activation of the system mentioned above, when the CPU 1 confirms that the subunit power source dropped until a voltage enough to reset the CPU 2, the CPU 1 sets the output port O₁ to the low level and turns on the transistors Q₁ and Q₃, and can reset the CPU 2. As shown in Fig. 1, stepping motors M₁, M₂, and M₃ are connected to the subunits 4 to 6. When the CPU 1 intends to drive the stepping motor M₂, the CPU 1 first outputs a stepping motor drive command to the CPU 2 by using the communication line. The CPU 2 receives the command and executes a stepping motor exciting signal output program written in the ROM provided in the CPU 2. Then, the CPU 2 outputs exciting signals of the double-phase exciting type from output ports O₂ to O₅ of the CPU 2 and can drive the stepping motor M₂ by the transistors Q₁₀, Q₁₁, Q₁₂, and Q₁₃. The diodes D₁₁, D₁₂, D₁₃, and D₁₄ are used to absorb the counter electromotive voltage of the stepping motor M₂. The resistor R₂ in Fig. 2 functions in a manner such that when a collector current I C3 of the transistor Q₃ exceeded a predetermined current, the transistor Q₂ is turned on and the collector current I C3 is limited. On the other hand, the posistor R₃ functions in a manner such that in the case where, for instances a coil of the stepping motor M₂ in the subunit 5 was short-circuited or the like, large currents flowing through the transistor Q₃ and the stepping motor driving transistors Q₁₀ to Q₁₃ in the subunits are suppressed. There is also a possibility such that when a large current flows due to a short-circuit of a load or the like, a temperature suddenly increases and the transistor Q₃ is burned and damaged. However, by arranging the posistor R₃ in contact with the transistor Q₃, a resistance value of the posistor R₃ rises in accordance with an increase in temperature of the transistor Q₃ and a base current I B3 of the transistor Q₃ is limited and the collector current I C3 can be reduced. Thus, it is possible to prevent that the transistor Q₃ and the transistors Q₁₀ to Q₁₃ in the subunits are burned and damaged. Since the CPU 1 monitors the power source voltage supplied to the subunit by the resistors R₄ and R₅ by the A/D port AN, if the transistor Q₃ failed and the power source voltage dropped due to some causes, such a voltage drop is detected and the fact that the power source could not be supplied to the subunit can be displayed. If the relation between the Zener voltage V z of the Zener diode ZD₁ to protect an overvoltage input of the A/D port AN of the CPU 1 and the input voltage V Di of the A/D port AN of the CPU 1 when the power source voltage V D to the subunit is correct is set to V z > V Di and the potential difference of (V z - V Di ) can be sufficiently detected at the A/D port AN of the CPU 1, when an overvoltage exceeding the normal input voltage V Di was generated and the input voltage V Di increased, such a voltage increase can be detected and the transistor Q₃ can be immediately turned off. Further, since the transistor Q₃ exists between the power source line to the subunit and the 24V line, the other 24V loads and the power source unit can be protected from the overvoltage. Fig. 5 is a block diagram showing the second embodiment of the invention. In the first embodiment, the 3-line type serial communication method has been used for the communication between the CPUs. However, the similar operation can be also obtained by using the parallel communication method using 8-bit communication buses. At this time, CS₁, CS₂, and CS₃ of the CPU 1 denote chip selection signals to select the CPU to be communicated. On the other hand, Fig. 6 is a block diagram showing the third embodiment of the invention. In the embodiment, a communication line is commonly used for each units while power source lines to the subunits are classified into two systems and the power sources to the subunits are controlled by the power source circuits 8 and 10, respectively. The CPU 1 can interrupt the power supply to the subunit 4 by changing an output level of the output port O₁ to the power source circuit 8. On the other hands the CPU 1 can interrupt the power supply to the subunits 5 and 6 by changing an level of an output port O₉ to the power source circuit 10. On the other hand, as shown in the first embodiment, the power source voltages are monitored by the A/D ports AN and AN₁ of the CPU 1, respectively. When the subunit ran away, in the case where the subunit which exerts an influence on the whole system exists and in the case where only the relevant unit is influenced, by controlling the power supply by using two systems or by individually supplying a power source to every unit as in the embodiment, the influence on the system can be minimized. On the other hand, if a reset command is included in the commands which are transmitted from the main CPU to the subCPU and at the leading time of the power-on of the system or the like, a soft resetting is executed from the main CPU to the subCPU in addition to the hard resetting, the subCPU can be further certainly reset.

Claims: A main processor unit (3) for connection to one or more subunits (4,5,6) via a power line (VD) and a communication line (SI,SO,SCK₁), said main unit comprising a central processor (CPU 1), and a power source (8) for supplying power to the or each subunit, and characterised in that said main processor unit is adapted to detect abnormal functioning of the or each subunit connected thereto, to control the voltage from said power source to be supplied to the or each said subunit, and to monitor the voltage supplied by said power source, and wherein, when said main unit detects abnormal functioning of a subunit, the main unit cuts off the power supply to that subunit, and restarts the power supply to that subunit thereby to reset the subunit after detecting that said voltage supplied by said power source has reached a predetermined level. A main unit according to claim 1, wherein said CPU during reset of a subunit shuts off the power supply to the subunit for a predetermined period. A main unit according to claim 1 or claim 2, wherein said CPU is adapted to shut off the power supply to an abnormally functioning subunit by controlling the voltage which is supplied to the subunit from the power source. A main unit according to any one of claims 1 to 3, wherein said power source includes means for detecting supply of an overcurrent to the or each subunit and/or for detecting an increase in temperature of a circuit device due to the supply of overcurrent, and means for limiting current to an abnormally functioning subunit on the basis of at least the detection of the supply of overcurrent to the subunit and/or of an increase in temperature of said circuit device due to the supply of the overcurrent. A main unit according to any one of claims 1 to 4, and including an A/D converter and an analog input terminal (AN), and a signal corresponding to the supply voltage to the or each subunit is input to said analog input terminal. An interunit communication system comprising a main unit according to any one of claims 1 to 5 and at least one subunit connected thereto, each subunit including a microprocessor. A method for resetting at least one subunit (4,5,6) by a main unit (3) connected via a power line (VD) to the subunit, the main unit having a CPU (1) and a power source (8) for supplying power to the or each subunit, characterised in that said CPU detects abnormal functioning of a subunit through communication with the subunit via a communication line (SI,SO,SCK₁), gives a control signal to the power source so as to shut off power supply to the abnormally functioning subunit, receives a signal relating to the voltage supplied to the abnormally functioning subunit, monitors the received signal to determine whether or not the voltage supplied to the abnormally functioning subunit has reached a predetermined level; and restarts the power supply to said subunit thereby to reset the subunit when the received signal reaches said predetermined level. A method according to claim 7, and wherein the main unit is connected to a plurality of subunits, and wherein when abnormal functioning of a single subunit is detected the CPU resets only said one subunit by shutting off and restarting power supply to said subunit. A main unit according to any one of claims 1 to 5, wherein said main unit has a plurality of power sources each of which corresponds to at least one subunit or to a group containing more than one subunit.

Inventors: ABE MAKOTO C O CANON KABUSHIKI, INUYAMA TOSHIHIKO C O CANON KA, ITOH TOSHIYUKI C O CANON KABUS, KIMIZUKA JUNICHI C O CANON KAB, KUSANO AKIHISA C O CANON KABUS, OKAZAWA KAZUHIKO C O CANON KAB, SATO KAORU C O CANON KABUSHIKI, ABE, MAKOTO, C/O CANON KABUSHIKI KAISHA, INUYAMA, TOSHIHIKO, C/O CANON KABUSHIKI KAISHA, ITOH, TOSHIYUKI, C/O CANON KABUSHIKI KAISHA, KIMIZUKA, JUNICHI, C/O CANON KABUSHIKI KAISHA, KUSANO, AKIHISA, C/O CANON KABUSHIKI KAISHA, OKAZAWA, KAZUHIKO, C/O CANON KABUSHIKI KAISHA, SATO, KAORU, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: G06F1
IPC codes: G06F15, G06F11, G06F1