Semiconductor device with a fusible link and method of making a fusible link on a semiconductor substrate

Abstract: A fusible link (13) is fabricated using sidewall spacer technology. The fusible link (13) of the present requires low fusing power because a fusible link (13) having a small cross-sectional area is obtainable. A conductive or semiconductive, fusible sidewall spacer is formed around a platform (12) or in a well of a dielectric layer (11). Each fusible link (13) may have two fusible portions per site, resulting in a built-in redundancy. Alternatively, the packing density of the fusible links (13) may be increased by using each side of the fusible sidewall spacer as a fusible link (13). This process is compatible with bipolar and BICMOS processes used in fabricating high performance memory devices.

Description: Background of the Invention This invention relates, in general, to semiconductor devices with fusible links, and to a method of making fusible links on a semiconductor substrate. Memory elements are used in integrated circuit memory devices, such as Programmable Array Logic devices (PAL's), Programmable Logic Array devices (PLA's), or Programmable Read Only Memories (PROM's) to produce field programmable products. Memory elements can be horizontal, metallic, fusible links; transistors which are shorted when sufficient reverse current is supplied; or floating gate transistors which can be turned on and off by introducing and releasing charge on the gate. Metallic fusible links are typically employed in high performance applications using bipolar/BICMOS technologies. In a memory array, a transistor supplies sufficient current to blow the fusible link to create an open circuit between a selected pair of bit and word lines. Fusible links remain intact to represent one logic state, and are fused open to represent the opposite logic state. The amount of energy required for fusing open a fusible link is determined primarily by the fusible link cross-sectional area in the fusing portion. Other parameters which affect the amount of energy required for fusing are the resistivity, thermal conductivity, and melting temperature of the fusible link material. In the past, fusible links have been fabricated by using a thin, horizontal, conductive or semiconductive film of either polysilicon, nickel chrome, platinum silicide, or titanium tungsten. A disadvantage of fabricating the fusible links in this manner is that a high fusing power is required for fusing. This means that larger transistors and diodes must be provided to handle the larger currents. The fusing power required can not be significantly reduced because a reduction of the fusible link cross-sectional area is limited. The thickness of the fusible link material is typically on the order of 100nm (1000 Angstrom). The width of the link is on the order of 2 microns and can not be reduced due to photolithography constraints. Thus, there is a need to provide a means of fabricating a fusible link having a smaller cross-sectional area than can be defined by the method described above. A fusible link having a smaller cross-sectional area will require a lower fusing power. Smaller transistors and diodes can be used, thereby reducing the die size of the integrated circuit memory device. An article entitled "Programmable Fuse Utilizing Deposited Conformal Metal Stringers as the Fuse Element" in Research Disclosure, no. 264, April 1986, pages 202-203, Emsworth, Hampshire, GB describes a technique for making in-chip fuses in wafers. The technique utilises etching and masking steps to form undercut sidewalls. The undercut regions are then filled with conformal metal to form a fuse. Summary of the Invention According to a first aspect of the present invention , there is provided a method of making a fusible link on a semiconductor substrate, comprising the steps of: providing a dielectric layer on the semiconductor substrate; patterning a platform or a well from the dielectric layer having substantially vertical sidewalls; forming a layer of a fusible material over and around the platform or well, the fusible material consisting of a conductive or semiconductive material; etching the layer of fusible material to leave a fusible sidewall spacer along a sidewall of the platform or well; and forming first and second electrodes contacting the fusible sidewall spacer at opposite ends thereof, whereby the fusible sidewall spacer forms a fusible link therebetween which is fusible by an electric current. In accordance with a second aspect of the present invention there is provided a semiconductor device comprising: a semiconductor substrate, a dielectric layer located on the substrate a well or a platform formed in the surface of the dielectric layer providing a substantially vertical sidewall, a fusible sidewall spacer formed along the sidewall, said fusible sidewall spacer being formed from a conductive material or a semiconductive material, and a first electrode and a second electrode, the first and second electrodes contacting the fusible sidewall spacer at opposite ends thereof, whereby the fusible sidewall spacer forms a fusible link therebetween which is fusible by an electric current. Another disadvantage of the fusible links made in the past is that a defect in the fusible link may cause the link to be open. Thus, there is also a need to provide a fusible link having a built-in redundancy. Built-in redundancy could provide two separate fusible portions in one fusible link element, so that if there is a defective portion on the fusible link, an intact fuse state is still formed. It is preferred that the well or platform has a quadrilateral shape and has sidewalls extending around the well or the platform and wherein the fusible sidewall spacer extends round all the sidewalls of the well or platform and wherein the first electrode is in electrical contact with first ends of two opposing sides of the sidewall spacer and wherein the second electrode is in electrical contact with second ends of the two opposing sides of the sidewall spacer, such that the two opposing sides of the sidewall spacer form two fusible links between the electrodes. Thus, an improved fusible link is provided requiring lower fusing power and a built-in redundancy. The method of fabricating has the advantage of providing a fusible link having a small cross-sectional area, thus requiring low fusing power. The method is compatible with modern bipolar and BICMOS processes. The fusible link preferably has built-in redundancy by fabricating the fusible link with two fusible portions per site. The invention allows for increased packing density of fusible links on an integrated circuit area. Brief Description of the Drawings Figs 1-2 illustrate enlarged cross-sectional views of a structure embodying the present invention in various stages of development; Fig 3 illustrates an enlarged top view of a structure embodying the present invention; and Fig 4 illustrates an enlarged cross-sectional view of a second embodiment of the present invention. Figs 1-3 illustrate one embodiment of the present invention in various stages of development. Fig 1 illustrates a semiconductor substrate 10 with a dielectric layer 11 deposited thereon. Substrate 10 will have semiconductor devices built therein, however, they are not illustrated here. A second dielectric layer 12 is deposited on layer 11 and then patterned to leave a transition or platform 12. Dielectric layer 11 and 12 can be comprised of two different dielectrics having an interface at dotted line 16. Dielectric layers 11 and 12 can also be comprised of a single dielectric layer which is patterned to form a platform 12. In a preferred embodiment, dielectric layers 11 and 12 would be a single layer of oxide, however, dielectric layers 11 and 12 can be any combination of oxide, nitride, or the like. A fusible layer 13 is then formed on dielectric layers 11 and 12. A fusible layer 13 is made of a conductive or semiconductive material such as doped polysilicon, silicided polysilicon, or a metal. Dielectric layers 11 and 12, and fusible layer 13 are deposited by any standard processes known in the art. Fig 2 illustrates the structure of Fig 1 with fusible layer 13 partially etched to form a fusible sidewall spacer 13. Layer 13 is etched in the same manner that is used to form a dielectric sidewall spacer. In a preferred embodiment, fusible sidewall spacer 13 is formed by employing a directional etch, such as a Reactive Ion Etch (RIE), that only etches in the vertical direction. In addition, a combination of a vertical and a horizontal etch may be used as long as fusible sidewall spacer 13 is not completely removed. Sidewall spacer technology is common in bipolar and BICMOS integrated circuit processes. Typically, sidewall spacers are dielectric spacers used to isolate two electrodes by a submicron distance. In the present invention, layer 13 is not a dielectric layer, but a conductive or semiconductive layer which is fusible. Since sidewall spacer technology is commonly used in bipolar and BICMOS processes, the process illustrated here can be easily integrated into the structure shown. As one can note from Fig 2, the cross-sectional area of fusible sidewall spacer 13 is very small. Photolithography does not limit the width of fusible sidewall spacer 13 as in the prior art. In the present invention, the thickness and the width can both be on the order of approximately 100 nm (1000 Angstrom). The small cross-sectional area results in low power required to fuse open a fusible link made with a fusible sidewall spacer 13 and can still facilitate low fuse resistances by virtue of proper choice of materials. The present invention allows for more flexibility in choosing a conductive or semiconductive layer 13 having a higher melting temperature, because the cross-sectional area can be greatly reduced. Fig 3 illustrates the structure of Fig 2 from a top view. The structure is also illustrated having two electrodes 14 and 15 making electrical contact to fusible sidewall spacer 13. As one can note from Fig 3, a fusible link is formed having two fusible portions per site, thereby providing for a built-in redundancy. If one portion of fusible sidewall spacer 13 is defective, the other portion can still be fused open or left intact. If there are no defects, both portions will fuse. A fusible link may also be fabricated without having a built-in redundancy, if desired, by providing four electrodes (not illustrated), instead of only two electrodes 14 and 15, making contact to fusible sidewall spacer 13. In this manner, up to four fusible links can be provided by using each side of fusible sidewall spacer 13 as a fusible link. Thus, the packing density of fusible links on a given semiconductor device area can be increased substantially. Fig 4 illustrates a second embodiment of the present invention. Dielectric layers 11 and 12 are deposited on substrate 10 and a fusible sidewall spacer 13 is fabricated thereon as in Figs 1 and 2. Fig 4 is very similar to Fig 2 except that fusible sidewall spacer 13 is formed inside a transition that is a well in dielectric layers 11 and 12 rather than on a platform as in Fig 1. Furthermore, dielectric layers 11 and 12 can be comprised of two different dielectric layers having an interface at dotted line 16, or a single dielectric layer as described in Fig 1. By now it should be appreciated that there has been provided a new and improved method of fabricating a fusible link element which is compatible with modern bipolar and BICMOS processes.

Claims: A method of making a fusible link on a semiconductor substrate (10), comprising the steps of: providing a dielectric layer (11) on the semiconductor substrate (10); patterning a platform or a well (12) from the dielectric layer (11) having substantially vertical sidewalls; forming a layer of a fusible material over and around the platform or well (12), the fusible material consisting of a conductive or semiconductive material; etching the layer of fusible material (13) to leave a fusible sidewall spacer along a sidewall of the platform or well (12); and forming first (14) and second (15) electrodes contacting the fusible sidewall spacer at opposite ends thereof, whereby the fusible sidewall spacer forms a fusible link therebetween which is fusible by an electric current. The method of claim 1 wherein the material from which the fusible sidewall spacer (13) is formed is selected from the group of polysilicon, doped polysilicon or silicided polysilicon. The method according to any preceding claim wherein the patterning step comprises patterning a well or platform having a quadrilateral shape and sidewalls extending around the well or platform, wherein the etching a fusible sidewall spacer step comprises forming a fusible sidewall spacer extending round all the sidewalls of the well or platform, and wherein the step of forming first and second electrodes comprises: forming the first electrode (14) in electrical contact with first ends of two opposing sides of the sidewall spacer; and forming the second electrode (15) in electrical contact with second ends of the two opposing sides of the sidewall spacer, whereby the two opposing sides of the sidewall spacer form two fusible links between the electrodes. A semiconductor device comprising: a semiconductor substrate (10), a dielectric layer (11) located on the substrate, a well (12) or a platform (12) formed in the surface of the dielectric layer providing a substantially vertical sidewall, a fusible sidewall spacer (13) formed along the sidewall, said fusible sidewall spacer being formed from a conductive material or a semiconductive material, and a first electrode (14) and a second electrode (15), the first (14) and second (15) electrodes contacting the fusible sidewall spacer at opposite ends thereof, whereby the fusible sidewall spacer forms a fusible link therebetween which is fusible by an electric current. A device according to claim 4, wherein the well or platform has a quadrilateral shape and has sidewalls extending around the well or the platform and wherein the fusible sidewall spacer extends round all the sidewalls of the well or platform and wherein the first electrode (14) is in electrical contact with first ends of two opposing sides of the sidewall spacer and wherein the second electrode (15) is in electrical contact with second ends of the two opposing sides of the sidewall spacer, such that the two opposing sides of the sidewall spacer form two fusible links between the electrodes.

Inventors: MASTROIANNI SAL THOMAS, MASTROIANNI, SAL THOMAS
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1990
Main classification: H01L23
IPC codes: H01L23, H01L21, H01L27