FULLY DIFFERENTIAL CMOS POWER AMPLIFIER

Abstract: Fully differential power amplifier comprising one high gain input stage (A1) and one AB class output stage (A2) realized in CMOS technology. Each of the two stages (A1, A2) is provided with a common mode feedback circuit (CMF1, CMF2) to set the working point thus optimizing the amplifier overall dynamic range. Besides a power dissipation reduction circuit (PWD) is provided to limit the power dissipated during the idle state of the power amplifier. In particular, the topology of the amplifier is fully symmetrical. In this way, a wide range output signal on a low resistive load, a very small harmonic distortion, as well as a low power consumption are achieved.

Description: FULLY DIFFERENTIAL CMOS POWER AMPLIFIER The present invention concerns a fully differential power amplifier implemented as an integrated circuit in CMOS technology operating with one single power supply voltage, e.g. 5 V; The chip on wich the circuit is integrated contains also a digital part. The amplifier according to the invention is able to drive a low impedance load in order of a few hundreds ohms with a low harmonic distortion and a wide output dynamic range, e.g. 4 Vpp (peak to peak voltage) if a 5 V power supply is used. The amplifier according to the invention is useful in those cases where it is necessary to drive low impedance loads with a wide dynamic range in relationship to the power supply voltage, low distortion and high common mode rejection ratio as well as a low power consumption. The circuit in his preferred application drive a mixer, for RF carrier modulation in a telecommunication system. The US-A-4 794 349 patent describes a differential power amplifier with three cascaded stages, one input stage, one gain stage and one output stage, respectively. This well known circuit has some drawbacks and limitations that make the circuit unsuitable for the above mentioned tasks. More precisely, the gain stage layout is not perfectly symmetric and may give rise to output distortions in case of mismatch between the gains of the two differential input stages. Besides the high complexity of this stage considerably limits the circuit bandwith. The output stage configuration according to the USA patent needs a control circuit to limit the rest current variations of the transistors in the two extreme branches, associated to possible technological inaccuracies in the integrating process. Finally, the circuit according to the USA patent has a high power consumption even in idle state, which makes it improper to be used with battery power supply. The purpose of this invention is to obtain a fully differential power amplifier overcoming the limitations of the former technique and in particular a power amplifier having wide dynamic range as well as a good Power Supply Rejection Ratio (PSRR) and low power consumption. The structure is featured by high noise rejection so that it is possible to integrate the circuit in a chip that also contains a digital part. The circuitry layout is fully symmetrical with respect to the two differential paths and permits to obtain a symmetrical layout from a geometrical point of view. This turns to be very important for what concern the high rejection of the noise coming from the substrate and by the power supply lines, mainly caused by switching of the digital part. Said noise affect in an identical modo the two differential paths and is translated into common modo noise only, while the differential signal is not affected of any noise. These purposes are obtained by means of the invention that consists in a fully differential CMOS power amplifier characterized by the fact that it comprises the following: - one folded-cascode input stage with two input terminals; - one AB class output stage, the inputs of which are connected to the outputs of said input stage; - one first common modo feedback circuit associated to the input stage; - one second common mode feedback circuit associated to the mentioned output stage; - one power dissipation reduction circuit able to inhibit the amplifier outputs in order to switch off the amplifier circuit when it is in idle state. Further characteristics and advantages of the invention will be evidenced by the following description related to a preferred bat not limitative form of the invention, which is illustrated in the attached figures, viz.: Figure 1 shows the power amplifier according to the invention evidencing the completely differential structure; Figure 2 shows a detailed block diagram of the amplifier according to the invention; Figure 3 is a schematic diagram of the input stage of the amplifier circuit; Figure 4 is a schematic diagram of the output stage of the amplifier circuit; Figure 5 shows the common modo feedback- circuit of the input stage; Figure 6 shows the time diagrams of the two control phases of the power dissipation (PWD) reduction circuit. As can be seen in Figure 1, the amplifier A according to the invention has a fully differential structure, i.e. both the input and the output are of differential type. More precisely, as can be seen in Figure 2, it comprises a differential input stage designated by Al having two inputs (IN+ and IN-) receiving two counterphase signals and one output stage designated by A2, also of differential type, at the outputs of which OUT+ and OUT- is present the amplified signal. In particular, AB class amplifier A2 is able to generate output currents suitable to drive a low impedance load with very low signal distortion. The amplifier ■ circuit also comprises two common mode feedback circuits CMFl and CMF2 for stabilizing the common mode voltage and a power down (PWD) circuit to reduce the power dissipation, the control of which is schematically indicated by the signal PWDCON. The input stage is illustrated in detail in Figure 3. It is a balanced stage in the folded-cascode configuration consisting of two MOS transistors QI and Q2 connected ' to the common source (node Jl), the gates of which are two differential inputs, whereas the differential output signal is available on the drains of said transistors. Current generator G2 injects a constant current into nodo Jl, while current generators G4 and G5 constitute a high impedance load for the signal. The differential pair consisting of QI and Q2 is followed by two transistors Q7 and Q6, the gates of which are tied to a reference voltage VR1. The differential signal entering the terminals IN+ and IN- is amplified when reaching the drains of the transistors Q6 and Q7; then it is buffered and translated, by Q25 and Q26, to a voltage (Vo +, Vo -) suitable to drive the following output stage. The voltage present on the drains of the transistors Q6 and Q7 is reproduced on the drains of the transistors * Q36 and Q39 (VC2, VC1) and then used by the common mode feedback circuit CMFl to optimize the input stage dynamic. In this way, the common feedback circuit CMFl can read the instantaneous output voltage variation of the first stage without altering the load on the drains of Q6 and Q7. Correction takes place by injecting an Ic f, current proportional to the detected common mode voltage, into node Jl common to the sources of QI and Q2. Said current, which, together with the bias component 2Io produced by the current generator G2, forms an algebric sum, is able to feed back the voltage on the drains of Q6 and Q7 at half of the power supply voltage. Figure 3 also shows some current generators from Gl to G7 producing currents Io or 2Io illustrated in the figure. The two transistor pairs Q34-Q35 reflect the drain currents of Q25 and Q26, respectively. In this way, if neglecting the current component drained by circuit CMFl in presence of the differential signal, the transistor Q39 conducts the same drain current of Q26 and also the transistor Q36 conducts the same current of Q25. Consequently, voltages VC1 and VC2 are a true reflection of the voltages present on the drains of Q7 and Q6, respectively. Besides, the presence of power dissipation reduction (PWD) circuit has been drawn with switches W1-W9 controlled by signals Fl and F2, which will be illustrated in detail in the following text. As regards the input stage operation under regular conditions, i.e. not in idle state, said switches are supposed to be positioned as shown in the Figure 3. Finally, figure 3 shows voltages VREF, VSS and VDD being the 2.5 V reference voltage, ground and the +5 V power supply voltage, respectively. For the sake of completeness, Figure 3 shows compensating capacitors CM1, CM2, CF1, CF2, CF3, CF4. More precisely and with reference to Figure 4 as well, CM1 is connected between the gate of Q25 and output OUT- of the power amplifier. CM2 is connected between the gate of Q26 and output 0UT+ qf the power amplifier. Said capacitors CM1 and CM2 constitute a dominating pole compensation. CF1 is connected between the gate of Q25 " and node J2 common to the gates M6 and M8. CF3 is connected between the gate of Q26 and node J3 common to the gates M5 and M7. CF2 and CF4 are connected between the gate and source of Q25 and 26, respectively. Capacitors CF1, CF2, CF3 and CF4 constitute a feedforward compensation permitting to optimize the phase margin of the amplifier. Figure 4 shows the output stage A2, the core of which consists of a transconductance amplifier made up of transistors Ml, M2, M3, M4, M5, M6, M7 and M8. Signals Vo+, Vo- coming from the input stage Al are applied to the gates of Ml and M2 and after voltage translation they are fed back to the gates of M6 and M5 by means of transistor pairs M4-M7 and M3-M8. The transconductance stage currents present on the branches identified by Ml and M5, and by M2 and M6, respectively are mirrored in a ratio of 1 to 10, then they are recombined thus generating the two counterphase output voltages 0UT+ and OUT-. There are four current mirror consisting of the pairs Mil and M15, M12 and M16, M9 and M13, M10 and M14. A current ten times the current flowing through the drains of M15, M16, M9 and M10, respectively, is mirrored in the drains of the transistors Mil, M12, M13 and M14. In this case common mode feedback circuit CMF2 directly reads the output voltages and, depending on the detected common modo signal, it injects two equal currents Icmf 2 in correspondence with the drains of M9 and M10. In this way, a voltage, the average value of which equals half the power supply voltage, is restored in output nodes 0UT+ and OUT-. Figure 4 also shows the current generators G8 and G9 that force a constant current I 2 to the transistor pairs M7 and M4, M8 and M3, respectively. Also in the output stage shown in Figure 4, the PWD circuit effect is drawn by several switches W10-W17 controlled by signals Fl and F2, as can be seen in the figure. As already stated, in the input stage Al as well as in output stage A2 of the power amplifier circuit according to the invention, a common mode feedback circuit is provided to optimize the whole amplifier dynamic range. The common mode feedback circuit CMFl of the input stage Al is shown in detail in Figure 5. The detection of the common mode signal; i.e. of the average voltage (Vo+ and Vo-) shift from the reference voltage VREF (where VREF equals half the power supply voltage) is obtained by means of a resistive partition consisting of two equal resistors RM1 and RM2, to the ends of which are applied the stage output voltages Vo+ and Vo- to be stabilized. Two capacitors Cl and C2 with equal value are connected in parallel to the resistors RM1 and RM2; they are designed to stabilize the common mode feedback loop. The voltage Vp present in the center of the voltage divider, proportional to the common mode signal, is compared with the reference voltage VREF by means of the differential stage constituted of Q29 and Q30. If the center of the voltage divider shifts from VREF, the transistors Q29, Q30, Q31 and Q32 generate a current signal Icmf-; as already mentioned, this signal forms an algebraic sum with the current 2Io, injected into the transistors QI and Q2 of the differential input stage, thus restoring an quiescent voltage equal to the VREF on the drains of transistors Q7 and Q6. The current generator G10 generates current I, biasing the stage consisting of Q29, Q30, Q31 and Q32 so that the current Ic f, is enough to feed back the average value of Vo+ and Vo- to the reference voltage VREF. W18 is a part of the circuit PWD previously described. Said circuit "reads" the common mode voltages (i.e. the average value of voltages Vo+ and Vo-) and produces an internal signal attenuating the noise without altering the differential signal. In this way, the circuit * CMFl returns the average value of the two voltages Vo+ and Vo- to a reference value VREF applied to the correcting circuit, value that allow to obtain the maximum output dynamic range. This type of circuit permits to achieve a high gain of the common mode feedback loop and a bandwidth comparable to that of the whole amplifier. In this way, a small common mode error over the whole bandwidth is obtained. As common mode feedback circuit CMF2 of the output stage has a similar configuration, but with a common mode feedback circuit which is twice that of the input stage, i.e. the part of the circuit between the center node of the resistive partition and VREF, and therefore no further description will be given. As already stated, Figures 3 and 4 show the power dissipation reduction circuit PWD with controlled switches W1-W18, which during regular operation of the amplifier circuit, are in the state indicated in the figures. The PWD circuit operation results to be particularly useful when the circuit according to the invention is a built-in part of portable devices with battery power supply, wherein part of the circuit remains in idle state for a certain period, such as e.g. half duplex transceivers where, during reception the transmit section is in idle state and vice versa. Another typical case is that of data transmission systems operating according to the TDMA (Time Division Multiple Access) technique, in which the turn-on of the single equipment is accomplished according to time slots. In particular, the PWD circuit according to the invention may be actvated or disactivated in very short time of the order of a few hundreds of microseconds. The switch on and switch off transitions of the amplifier circuit must be very short and no spurious signals caused by them should be present at the differential outputs. The power dissipation reduction circuit has two control signals or phases designated by Fl and F2 on the command electrodes of the controlled switches W1-W8. The time diagram of the two phases is shown in Figure 6. On the falling edge of phase F2 the drains of transistors Q6 and Q7 of Figure 3 and the drains of transistors Mil, M.12,. M13, M14 of Figure 4 are connected across at the 2.5 V reference voltage by means of switches W14 and W15 controlled by phase F2. Hence the amplifier outputs are inhibited for the whole period F2 is at a low level . The following falling edge of the control signal Fl causes switching off of the remaining analog part of the amplifier according to the invention as well as of any other circuit which is part of the chip. The acuteness of inhibiting the amplifier outputs before turning off the chip permits to isolate the outputs from all spurious transitions caused by turning off and on the amplifier itself and of all circuits connected before the power amplifier. Turning off the input stage of the amplifier Al is accomplished by switching off the current generators G1-G7 shown in Figure 3 and forcing to zero the reference voltate VR1. Turning off the output stage of the amplifier A2 is accomplished by switching off the current generators G8 and G9 and short circuiting the gates of the transistors Mil, M15, M16 and M12 to VDD and the gates of M13, M9, M10 and M14 to VSS by means of switches W10, W13, W16 and W17 shown in figure 4. In these conditions the power dissipation is reduced to the value of a few nW. As regards re-switching on, the rising edge of Fl (see Figure 6) causes the whole chip to turn on again. Being the drains of Q6, Q7, Mil, M12, M13 and M14 still shortcircuited towards reference voltage VREF, the transition switch-on signal cannot propagate to the amplifier outputs. The drains of these transistors are released only later on the rising edge of F2 and at this time the circuit is fully reactivated. Besides, another advantage of the invention consists in the elimination of the conversion circuit from differential to single-end present.in the devices with non differential outputs, a circuit which introduces further time constants that limit the bandwidth. This means an increased amplifier signal bandwidth.

Claims: AMENDED CLAIMS [received by the International Bureau on 8 May 1991 (08.05.91); original claims 1 and 2 amended; other claims unchanged (2 pages)] 1. Fully differential CMOS power amplifier comprising: one input stage (Al) of the folded-cascode type having two input terminals (IN+, IN-) ; - one AB class output voltage stage (A2) , the inputs of which are connected to outputs (Vo+, Vo-) of said input stage, respectively; a first common mode feedback circuit (CMFl) associated to said input stage (Al) ; - a second common mode feedback circuit (CMF2) associated to said output stage (A2) ; characterized by the fact that said second common mode feedback circuit (CMF2) is connected between the output of said output stage (A2) and an internal low impedance junction thereof; and by the fact that said power amplifier (A) comprises a power dissipation reduction circuit (PWD) which during the idle periods of the amplifier (A) is able to connect both said outputs (Vo+, Vo-) of the output stage (A2) to a voltage reference (VREF) through a pair of controlled switches (SW14, SW15) and thereafter, after a predetermined delay, to turn off the whole amplifier through a plurality of controlled switches (SW10, SW13, SW16, SW17) . 2. Amplifier circuit according to claim 1, characterized by the fact that said power dissipation reduction circuit (PWD) comprises a first set of command switches (W1-W3, W6- W13, W16-W18) controlled by a first control signal (Fl) and a second set of command switches (W4, W4A, W14, W15) controlled by a second control signal (F2) , the active edge of said first control signal (Fl) being delayed with respect of the active edge of said second control signal (F2) when switching off said amplifier circuit (A) , and viceversa when switching on said amplifier circuit (A) . 3. Amplifier circuit according to claims 1 or 2, characterized by the fact that said input stage (Al) comprises a first transistor pair (QI, Q2) having the source electrodes connected in a common node (Jl) and the gate electrodes of which constitute two differential inputs (IN+, IN-) , being said common node (Jl) also connected to a constant current generator (G2) and to the output of said first common mode feedback circuit (CMFl) which injects a correction current (Icmf-^) into said node. 4. Amplifier circuit according to claim 3, characterized by the fact that the drain electrodes of the transistors of said first pair (QI, Q2) are connected to the source electrodes of a second transistor pair (Q7, Q6) , respectively, the gate electrodes of which are tied to a first reference voltage (VRl) .

Inventors: GAZZOLI GIUSEPPE, MALOBERTI FRANCO, PALMISANO GIUSEPPE, SFORZINI LUIGI, GAZZOLI, GIUSEPPE, MALOBERTI, FRANCO, PALMISANO, GIUSEPPE, SFORZINI, LUIGI
Applicants: ITALTEL SPA, ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI S.P.A.
Application year: 1990
Main classification: H03F3
IPC codes: H03F3