Inductive structures for semiconductor integrated circuits

Abstract: An inductive structure integrable with a semiconductor integrated circuit comprises an electrically insulating substrate (1) having opposed fist and second surfaces; an electrical conductor disposed in a spiral (2) spaced from the first surface of the substrate (1), the spiral (2) including an external end (3) disposed outside the spiral (2) as a first lead and an internal end (4) disposed within the spiral (2), said first spiral (2) including at least two windings adjacent each other; and a plurality of electrically conducting, spaced apart posts (25) disposed on the first surface of the substrate (1) contacting and supporting the first spiral (2), wherein each post (25) supporting one winding is disposed intermediate two adjacent posts (25) supporting an adjacent winding.

Description: The present invention relates to inductive structures, as claimed in the preamble of claim 1, integrable with semiconductor integrated circuits, particularly for use at high frequencies. Of all passive electrical elements (resistors, capacitors, and inductors), inductors are the most difficult to form in integrated circuits. Inductors present difficulties because they require relatively large areas and/or volumes to achieve useful values of inductance. In addition, the traditional three-dimension character of inductors is difficult to realize within integrated circuits that are essentially two-dimensional in character. The difficulties of making satisfactory inductors of useful values that are integrable with integrated circuits are aggravated at higher frequencies. Because of the limited volumes available for components, i.e., active and passive elements in essentially two-dimensional integrated circuits, the conventional inductive structures suffer from increasing parasitic capacitances at increasing frequencies. These undesirable capacitances are produced by conductor cross overs, closely spaced wiring paths, and the like. The parasitic capacitances adversely affect and limit the frequency at which the circuits perform properly. At high enough frequencies, the effects of the parasitic capacitances can be so strong that they overwhelm the inductive characteristic of an inductance element. In more complex structures employing several windings, the difficulties associated with controlling the area and volume of an element while achieving desired performance and limiting parasitic capacitances are even greater. It is an object of the present invention to provide inductive structures integrable with semiconductor integrated circuits that have reduced parasitic capacitances. According to the invention, directed to a spiral like conductor supported above a substrate by a plurality of posts, the posts of adjacent conductors in the spiral are offset so that a post of one winding is disposed intermediate two adjacent posts of an adjacent winding. This spacing reduces the capacitive coupling and the parasitic capacitance between windings and posts that arises in the prior art structures. Figure 1 is a perspective view of a prior art spiral inductor; Figures 2(a) and 2(b) are plan and sectional views, respectively, of a prior art spiral inductor; Figures 3(a), 3(b), and 3(c) are perspective, plan, and sectional views, respectively, of a prior art inductor employing two electrically interconnected spirals; Figures 4(a) and 4(b) are plan and sectional views, respectively, of a further prior art spiral inductor; and Figures 5(a) and 5(b) are plan and sectional views, respectively, of a spiral inductor according to an embodiment of the invention. Figure 1 is a perspective view of a prior art inductor disposed on a semiconductor substrate 1 that may be gallium arsenide. In this inductor, an electrical conductor 2 arranged in a spiral pattern is disposed on a first surface of the substrate 1. As used here, the term "spiral" means a winding that increases in diameter with reference to a central point as the conductor becomes longer. The spiral may be smooth, gradually increasing in diameter like the shell of a nautilus, or have corners with angular turns like the ninety degree turns shown in Figure 1. The spiral is formed of a metal that is deposited by evaporation or by plating and includes an external end 3 lying outside the spiral and an internal end 4 disposed at the inside of the spiral. In Figure 1, external end 3 is connected to a terminal 5 for ease of connection by wire bonding or other techniques to other circuit components. Internal end 4 is connected through a lead 6 to a terminal 7 for making external connections. Lead 6 must cross over and, therefore, be electrically insulated from windings of the conductor 2. An electrically conducting ground plane 8 is disposed on the opposite side of substrate 1 from the conductor 2. In Figures 2(a) and 2(b), a plan view and a sectional view of a prior art Inductor similar in structure to the inductor of Figure 1 is shown. An electrically insulating air bridge 9 including an air space 10 is part of lead 6, providing the electrical insulation from the turns of the conductor 2. The air bridge is formed by conventional technology employing a temporary support, such as a polyimide or photoresist film, covering the windings 2 while the metal comprising air bridge 9 is deposited. After that metal is deposited, the temporary support is removed, for example, with a solvent, leaving a free standing air bridge. In conventional technology, the spacing between the metal of the air bridge and the conductors 2 is, at most, a few microns. Because of this close spacing, even though the dielectric constant of the air between lead 6 and windings 2 is relatively low, a significant parasitic capacitance exists between the windings 2 and the lead 6 at air bridge 9. In Figures 3(a), 3(b), and 3(c), an inductive structure disclosed in Japanese Published Utility Model Application 60-136156 is shown in perspective, plan, and sectional views, respectively. A substrate 1, that may be a semiconductor material, employed with the structure is not shown in Figure 3(a) for clarity. The inductive structure of Figures 3(a)-3(c) includes two spiral electrical conductors 2 and 12 that are disposed opposite each other. The internal end 4 of spiral 2 is electrically connected to an external end 13 of spiral 12 through an electrical conductor 15. The inductive structure has a first terminal 5 electrically connected to the external end 3 of spiral 2 and a second terminal 7 connected to the internal end 14 of spiral 12. Realization of the inductive structure shown schematically in Figure 3(a) is indicated in the cross-sectional view of Figure 3(c). The structure is produced by depositing patterns of metal in conjunction with insulating layers 20, 30, 40, and 50 successively disposed on substrate 1. Initially, after the deposition of insulating layer 20, a window is opened for establishing contact with a highly conductive region la in substrate 1. Then, spiral 2 is formed by depositing and patterning a metal. Thereafter, insulating layer 30 is deposited and a window is opened for making a connection to the internal end 4 of spiral 2. After a subsequent metal deposition and patterning to form an interconnection with conductor 15, insulating layer 40 is deposited and a window opened. After still another metal deposition and patterning to form spiral 12, making an electrical connection in the window at the external end 13 of spiral 12, a final, electrically insulating layer 50 is deposited. The inductance of the structure shown in Figures 3(a)-3(c) is the inductance of the individual spirals plus a mutual inductance between the two spirals. Since the mutual inductance between the two spirals is greater than if they were side-by-side, the total inductance is increased over that of two side-by-side spirals and a smaller volume is occupied. However, the fabrication process for the structure of Figures 3(a)-3(c) is extremely complex and, as in the prior art device described with respect to Figures 2(a) and 2(b), the spacing between the two spirals is limited by the thickness of the insulating layers 20, 30, 40, and 50. Therefore, a significantly increased parasitic capacitance is produced by the structure of Figures 3(a)-3(c), limiting its useful frequency range. Another known method of reducing the parasitic capacitance of a planar spiral inductive structure which is considered to represent the closest prior art is illustrated in Figures 4(a) and 4(b). There, in plan and cross-sectional views, an electrically conducting spiral 2 is supported above the surface of a substrate 1 by a plurality of electrically conductive posts 25. The metal posts 25 are spaced apart from each other by air spaces 26. The dielectric constant of air is about one and is smaller than that of the underlying substrate, for example, twelve, when the substrate is gallium arsenide. The supporting structure of Figures 4(a) and 4(b) reduces the capacitance between adjacent windings of spiral 2, effectively changing the dielectric constant between the windings from twelve to one. However, some parasitic capacitance is added by the posts 25. Figures 5(a) and 5(b) show in plan and sectional views a modification according to the invention of the supporting structure of Figures 4(a) and 4(b) that results in still further reduced parasitic capacitance. In Figures 4(a) and 5(a), the supporting posts 25 are electrically conducting and support the spiral 2 at a distance from the surface of substrate 1. In Figure 4(a), each post 25 has at least one neighbor directly opposite it in an adjacent winding. In other words, in Figure 4(a), each pair of adjacent posts 25 supporting one winding has a corresponding pair of adjacent posts in an adjacent winding with the respective posts in each winding aligned with each other. However, in the embodiment of the invention shown in Figure 5(a), for each pair of adjacent posts supporting one winding, there is, in an adjacent winding, a supporting post intermediate those two adjacent posts. That arrangement, as shown in Figure 5(a), results in a zig-zag pattern of posts in adjacent windings. Assuming the posts have the same spacing interval for each winding in Figure 4(a) and 5(a), the spacing arrangement of Figure 5(a) increases the distance between posts of adjacent windings by the square root of two. Thus, the parasitic capacitance between adjacent windings is reduced. As illustrated in Figures 5(a) and 5(b), the vias 21 and 23 and an electrical conductor 22 can be employed with the novel supporting post structure. The reduced capacitance of the novel supporting structure permits an inductive structure according to the invention to be employed at higher frequencies from prior art structures without being degraded by parasitic capacitance.

Claims: An inductive structure integrable with a semiconductor integrated circuit, comprising: an electrically insulating substrate (1) having opposed first and second surfaces; an electrical conductor disposed in a spiral (2) spaced from the first surface of the substrate (1), the spiral (2) including an external end (3) disposed outside the spiral (2) as a first lead and an internal end (4) disposed within the spiral (2), said spiral (2) including at least two windings adjacent each other; and a plurality of electrically conducting, spaced apart posts (25) disposed on the first surface of the substrate (1) contacting and supporting said spiral (2), characterized in that each post (25) supporting one winding is disposed intermediate two adjacent posts (25) supporting an adjacent winding. The inductive structure of claim 1, further characterized by first and second electrically conducting vias (21,23) passing through the substrate (1) from the first to the second surface, the first via (21) intersecting and establishing an electrical connection to the internal end (4) of the spiral (2); the second via (23) lying outside the spiral (2); an electrically conducting connector (22) disposed on the second surface of the substrate (1) electrically connecting the first and second vias (21,23); and a second lead (6) disposed on the first surface of the substrate (1) outside the spiral (2) electrically connected to the second via (23) whereby electrical connections to the inductive structure can be made on the first surface of the substrate (1). The inductive structure of claim 1 or 2, characterized in that the substrate (1) is an electrically insulating semiconductor. The inductive structure of claim 3, characterized in that the substrate (1) is chosen from the group consisting of gallium arsenide and indium phosphide.

Inventors: ANDOH NAOTO, INOUE AKIRA, NAKAHARA KAZUHITO, NAKAJIMA YASUHARU, ANDOH, NAOTO, INOUE, AKIRA, NAKAHARA, KAZUHITO, ANDOH, NAOTO, MITSUBISHI DENKI K.K. ELEC., INOUE, AKIRA, MITSUBISHI DENKI K.K. ELEC., NAKAHARA, KAZUHITO, MITSUBISHI DENKI K.K. ELEC., NAKAJIMA YASUHARU, MITSUBISHI DENKI K.K. ELEC.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H01F17
IPC codes: H01F17, H01F21, H01L21, H01L23