Low impedance buffer circuitry

Abstract: A low impedance class AB buffer stage in complementary transistor technology has its quiescent current stabilized and its operation thereby made more reliable by means of suitable error op-amps (A1, A2) that are supplied with transistor feedback loops (M1, M2) which are connected to the stage's output terminal (21) through resistors (R1, R2). In addition, for full rail-to-rail output voltage capability, transistor switching devices (M5, M6) are added to turn off current through either of the resistors (R1, R2) when the output voltage (V OUT ) of the stage approaches the voltage of either power rail, and also a pair of serially rail-to-rail connected transistors (M3, M4) is connected in parallel with the feedback loops.

Description: Amplifier circuitry having relatively low output impedance is necessary for driving large capacitive or resistive loads, such as the relatively low impedance of a telephone line, typically an impedance of about 600 ohms or less. In prior art, such amplifier circuitry typically is composed of a low impedance unity-gain buffer output stage fed by one or more voltage-gain stages. This amplifier circuitry typically is integrated in a semiconductor chip; whereas the load is situated off-chip. For example, as shown in the textbook by P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (John Wiley & Sons, second edition, 1984) at page 759, Figure 12.43, a buffer stage for class B (push-pull) operation can be formed by a pair of error operational amplifiers (error op-amps) which are connected to receive feedback from a pair of serially connected output transistors in such a manner as to assure unity voltage gain. The operation is class AB (push-pull) in cases where in the quiescent (no signal) state both output transistors conduct current, but one of them does not conduct any current whenever the input voltage goes outside a narrow range, typically the range of about ± 0.5 volt around ground potential. As known in the art, class AB operation in general is desirable from the standpoints of low standby power consumption and of no missing output signals for small input signals (no "dead zone") which would distort the output. However, the circuit design of the aforementioned buffer stage is undesirably sensitive to semiconductor processing variations, so that either excessive power dissipation or circuit instability (oscillations) caused by poor feedback control over the quiescent current, or both, may result: Too high a quiescent current is wasteful of power, whereas too low a quiescent current can result in the above-mentioned circuit instability. GB 2180710 discloses a CMOS output stage comprising complementary push-pull connected MOS transistors each fed by a respective differential amplifier whose negative input is fed by the input signal and whose positive input is fed by the output signal appearing at the node between the MOS transistors. Such an arrangement suffers from the disadvantage that the output quiescent current level is greatly affected by offsets in the differential amplifiers. According to this invention there is provided amplifier circuitry as claimed in claim 1. The buffer stage can be operated class AB and advantageously be fed by a high voltage gain stage of amplifier circuitry. Also, a pair of serially connected third and fourth transistors, having much higher channel width-to-length ratios than the first and second transistors, can be connected in parallel with the first and second transistors, in order to make the output voltage swing more nearly approximate the rail-to-rail power supply voltage. Furthermore, for full rail-to-rail output capability, a separate switching transistor is inserted between the first and second rails, respectively, and the first and second transistors; and each such switching transistor has its control terminal respectively connected to the first and second nodes. The invention will now be described with reference to the accompanying drawing which is a circuit schematic including a buffer stage in amplifier circuitry. Detailed Description The FIGURE shows a low impedance buffer stage 20 embodying the invention. Advantageously this buffer stage 20 is supplied with voltages V1 and V2 by a high voltage gain stage 10. The circuitry of both the stages 10 and 20 can be integrated into a single silicon semiconductor chip, as known in the art and as further discussed below. In the FIGURE, power lines ("rails") V DD and V SS are set at typically +5 volt dc and -5 volt dc, respectively, as known in the art. A fixed electrical current source of current I S is connected serially with a resistor R S and an n-channel MOS transistor M7 between the power rails, in order to form the high gain stage 10. During operation, this high gain stage 10 receives an input voltage V IN at its input terminal 11 and delivers voltages V1 and V2 to the buffer stage 20. Each of a pair of standard op-amps A1 and A2 (each of which can be formed by a simple differential pair of transistors) is connected in the stage 20, and each of these op-amps has its respective negative input terminal connected to receive the voltages V1 and V2. Serially connected from rail to rail are n-channel MOS transistors M5 and M1, a resistor R1, a resistor R2, and p-channel transistors M2 and M6. A node between the resistors R1 and R2 develops an output voltage V OUT at an output terminal 21 of the stage 20. Optionally, for reasons discussed below, another n-channel MOS transistor M3 and another p-channel MOS transistor M4 are added to the buffer stage 20 in parallel with the branch formed by the serially connected M5, M1, R1, R2, M2 and M6. The transistors M3 and M4 are serially connected from rail to rail. A node between these transistors M3 and M4 is connected to the output terminal 21. Advantageously, the parameters of the transistors M3 and M4 are selected so as to equalize their transconductances. The channel width to length ratio (W/L) of each of M3 and M4 advantageously is at least about five times as large as that of M1 and M2, respectively. Likewise, advantageously the transistors M1 and M2 are formed with equal transconductances. The resistors R1 and R2 advantageously are a matched pair (R1=R2). The requirements of matched pairs for R1 and R2, as well as for equal transconductances of M1 and M2, M3 and M4, need not be satisfied, at some penalty of signal distortion. Indeed, one of the resistances R1 and R2 could be zero (short circuit). The purpose of M5 and M6 is to enable full rail-to-rail output voltage swing at the output terminal 21, for such full rail-to-rail operation tends to be prevented by the voltage drop(s) across R1 and R2. For example, because of the voltage drop across R2, the output voltage V OUT cannot attain V DD regardless of how high V2 rises, so long as current can flow through R2. In the presence of M6, however, when V2 rises and causes the potential at the node N2 to rise to a threshold below V DD , the transistor M6 turns off, whereby the voltage drop across R2 vanishes sand hence the transistor M4 can then bring the output voltage V OUT fully to V DD . If, on the other hand, such full rail-to-rail output is not required, then the transistors M5 and M6 can be omitted, with the source terminals of M1 and M2, respectively, being connected directly to V SS and V DD . Each of the op-amps A1 and A2, respectively, has its output terminal coupled (connected) to a low current carrying control terminal (gate terminal) of the pair M1, M3 and the pair M2, M4. In practice, the op-amps A1 and A2 are biased (not shown) so that there is an adequate safety margin of non-zero quiescent current in a neighborhood of the quiescent state (no signal region), in order to avoid the signal distortion problem otherwise caused by a "dead zone" in which a change in the input signal would not produce any change in the output. The buffer stage 20 operates as follows. Because the op-amp A1 and A2, being operational amplifiers, cannot support any significant differences in the voltages applied to their positive vs. negative input terminals, the feedback to their positive input terminals supplied by node N1 located between R1 and M1 (to A1) and by node N2 located between R2 and M2 (to A2) makes the quiescent current i Q well-defined and controlled, i.e., adjustable to the desired value by proper selection of parameters. More specifically, assuming that the source-drain voltage drop across M5 and M6 are both much less than a threshold of n-channel and p-channel transistors, the quiescent current i Q is given by: i Q = I S R S (1+a)/(R1+R2) where the R's are the resistances of the respective designated resistors, and where a is equal to the ratio of the width-to-length ratio (W/L)₃ of M3 to that (W/L)₁ of M1, and equally of M4 to M2 (assuming matched pairs of transistors): a=(W/L)₃/(W/L)₁=(W/L)₄/(W/L)₂ Note that from eq. (1) it follows the quiescent current i Q is thus well-controllable and insensitive to semiconductor processing variations: the resistances of the resistors track one another, as do the W/L ratios. Although the current I S supplied by the current source varies with semiconductor processing conditions, it does so in a well-defined non-critical way, so that the quiescent current is relatively stable with respect to variation in semiconductor processing conditions: the feedback in the operational amplifiers does not introduce any significant circuit instability. By selecting R1=R2=R, then, in the quiescent state: V OUT = (V₁+V₂)/2; i.e., the output voltage of the buffer stage 20 then is conveniently equal to the common mode voltage of the inputs V1 and V2 to this buffer stage. As noted above, the transistors M3 and M4, as well as M6 and M5, can be omitted, but then during class AB operation (push-pull) the output voltage V OUT could not swing as closely from V DD to V SS as it can when these transistors are present. Note that the larger the value of a , as given by eq. (2), the closer the output voltage swing becomes equal to rail to rail. In order to assure stable operation with sufficient quiescent current, and hence to assure class AB operation, I S and R S should be selected to be large enough to make I S R S greater than the sum of the maximum expected absolute values of the operational amplifier offset voltages of A1 and A2 by a factor of about 5 to about 10 or more, lest chip-to-chip variations of the offset in A1 or A2 or both should cause undesirably large chip-to-chip variations in the quiescent current i Q . The resistors R₁, R₂, R₅ can be formed, for example, by standard diffused regions in semiconductor or by standard deposited polysilicon resistors. The current source I S can be formed by an MOS transistor biased in its saturation region, as known in the art. Note that in the presence of signal applied to the gate terminal of M7, the voltage drop (V2-V1) across R S remains fixed (I S R S ). That is, the difference mode (V2-V1)/2 is fixed; whereas the common mode (V2 + V1)/2 varies with signal. In a typical case, only by way of illustration, approximate values for the various parameters are: R1 = R2 = 2000 ohm; R S = 1000 ohm; I S = 50 microamp; a = 30. With signal, the output current at the output terminal 21 can go as high as 10 milliamp. The gate terminal of M7, to which V IN is applied, can be connected, for example, to the output terminal of a differential gain stage (not shown); and the output terminal 21 of the stage 20 can then be connected, for the purpose of feedback, to the negative input terminal of the differential gain stage. In that way, overall unity gain of V OUT relative to the input voltage applied to a positive input terminal of the differential gain stage can be achieved, in combination with overall high input impedance and low output impedance, as is desired in amplifier circuitry for driving large currents into large loads (line drivers). Although the invention has been described in detail in terms of a specific embodiment, various modifications can be made within the scope of the claims. For example, instead of n-channel and p-channel MOS transistors, npn and pnp bipolar transistors can be used.

Claims: Amplifier circuitry comprising a buffer stage (20) which comprises first and second amplifiers (A1,A2) each having an output terminal and a first and a second input terminal, first and second connection means (R1,R2), first and second transistor devices (M1,M2) respectively having first and second relatively high current carrying controlled paths and respectively having first and second relatively low current carrying control terminals, first and second power rails (V SS , V DD ), the first high current path of the first transistor device (M1), the first connection means (R1), the second connection means (R2), and the second high current path of the second transistor device (M2) being serially connected, in the order stated, in a path between the first power rail and the second power rail, means for connecting the output terminal of the first amplifier to the control terminal of the first transistor device (M1), and means for connecting the output terminal of the second amplifier to the control terminal of the second transistor device (M2), CHARACTERIZED IN THAT the first and second amplifiers (A1,A2) are operational amplifiers, at least one of the first and second connection means comprises resistance means (R1,R2), there is provided means for connecting a first node (N1) located between the first transistor device (M1) and the first connection means (R1) to the second input terminal of the first amplifier, and means for connecting a second node (N2) located between the second transistor device (M2) and the second connection means (R2) to the second input terminal of the second amplifier (A2), and there is provided a voltage gain stage (10) comprising current source means (I S ) for supplying a constant current, further resistance means (R S ) having first and second terminals (V1, V2), a third transistor device (M7) having a control terminal that is connected to a circuitry input terminal (11) for receiving an input signal voltage, the third transistor device having a third relatively high current path suitable for carrying the constant current, means for connecting, from the first rail to the second rail, serially, in the order stated, the current source means, the further resistance means, and the third relatively high current path, and means for connecting the first and second terminals of the further resistance means to the first input terminal of the first and second operational amplifiers, respectively. Circuitry as claimed in claim 1, wherein each of said first and second connection means comprises resistance means (R1, R2), and there is provided means for connecting a node located between the first and second connection means to an output terminal (21) of the buffer stage. Circuitry as claimed in claim 1 or 2 comprising fourth and fifth transistor devices (M3, M4) having respectively third and fourth relatively low current carrying control terminals that are coupled respectively to the first and second control terminals of the first and second transistor devices, respectively, the fourth and fifth transistor devices having respectively fourth and fifth relatively high current paths that are connected serially from the first power rail to the second power rail. Circuitry as claimed in claim 3 wherein the channel width to length ratio of the fourth transistor device and of the fifth transistor device is at least five times greater than that of the first transistor device and of the second transistor device, respectively. Circuitry as claimed in claim 3 or 4 comprising sixth and seventh transistor devices (M5,M6) whose high current paths are respectively connected in series with that of the first and second transistor devices, and whose control terminals are respectively connected to the first and second nodes (N1,N2). Circuitry as claimed in any preceding claim wherein the constant current multiplied by the resistance of the further resistance means is at least about 5 times the input offset voltage of the first and second amplifiers. A semiconductor integrated circuit comprising circuitry as claimed in any preceding claim.

Inventors: KHOURY JOHN M, KHOURY, JOHN M.
Applicants: AT & T CORP, AT&T CORP.
Application year: 1990
Main classification: H03F3
IPC codes: H03F3