Video signal processing circuit

Abstract: A video signal processing circuit is disclosed in which error correction, error concealment and weighted mean processing (in this order) are performed on input playback video signals from a video tape recorder, wherein, for performing error concealment on erroneous sample data on which error correction has not been feasible a plurality of error concealment methods or algorithms are provided. One of the available error concealment methods is selected in dependence upon the state of error flags of sample data in the neighboring and/or temporal direction of the erroneous sample data to perform a concealment in accordance with the error pattern to provide satisfactory error concealment for a broad range of error rates.

Description: This invention relates to a video signal processing circuit. More particularly, it relates to such video signal processing circuit in which playback video signals are input from a video tape recorder, for example, error correction and error concealment are performed in this order on the input video signals, and error-corrected and error-concealed signals are output after weighted mean processing. In recording and/or reproducing digital sample data of video signals by a digital video tape recorder (VTR), so-called code errors are produced due to noise or defects on the medium. The erroneous data produced by the code errors are subjected to error correction using error correction codes and the erroneous sample data which have been unable to be corrected by such error correction are subjected to error concealment by interpolation or replacement using other error-free sample data. On the other hand, for generating a sequence of the odd and even numbered fields, once disrupted such as during different speed reproduction, that is, reproduction at a speed different from that during recording, into order, a weighted mean processing is frequently performed, which consists in forming at least signals of another field from signals of a given field. Meanwhile, in a so-called D-1 format (4:2:2 format of CCIR recommendations No. 601), which is one of the formats of a component digital VTR, two-dimensional error correction by the product code is performed, using so-called outer and inner codes. Thus, during recording, 360-byte-per-line sample data, which have been subjected to in-line shuffling, are sent to a two-dimensional error correction coding circuit employing product codes. First, a 2-bit outer code, i.e. outer correction code or outer parity, is annexed at intervals of 30 bytes or samples. The resulting code block is subjected to sector array shuffling and then a 4-byte inner code, i.e. inner correction code or inner party, is annexed at an interval of a 60-bytes-per-row sample data in the perpendicular direction of the shuffled code block to form an inner code block. A sync block structure generated from two such inner code blocks is recorded as a recording unit on the magnetic tape. During playback, an operation which is the reverse of the above mentioned operation is performed. Thus, two of the inner code blocks are taken out from the sync block and subjected to an error correction by the inner code, followed by a deshuffling which is the reverse operation of the sector array shuffling. Finally, a so-called erasure correction is performed, using 2-byte outer codes at an interval of a 32bytes-per-row outer code block. The erroneous sample data, which have been unable to be corrected for errors by the product code, are subjected to error concealment by interpolation or replacement. Among the methods for error concealment are a method of interpolation in th= horizontal or H direction, using sample data on both sides of and on the same as the erroneous sample data, a method of interpolation in the vertical or V direction, using sample data at the same position as and on lines above and below the line of the erroneous sample data, a method of interpolation in the D+ direction, using near-by sample data on a positive diagonal line, that is a diagonal line with a rightward positive gradient, of the erroneous sample data, a method of interpolation in the D₋ interpolation, using near-by sample data on the negative diagonal, that is, on the diagonal with leftward negative gradient, of the erroneous sample data, a method of replacement by error-free samples of the preceding frame or field exhibiting high temporal correlation, and a method of replacement by near-by sample data of the erroneous sample data. Meanwhile, it is desirable for actual error concealment to function over a wide range of error rates, for example, over a range from substantially 0 % during normal reproduction to substantially 100 % during high speed tape shuttling. However, an error concealment method with a high concealment accuracy may operate properly for a low error rate but fail to operate properly for a high error rate, while the error concealment method that may be operated even with a high error rate suffers from low concealment accuracy, such that there lacks an effective single concealment method whereby errors may be concealed at a suitable or acceptable concealment accuracy over the above mentioned wide range of the error rates. Although it may be contemplated to use a plurality of error concealment methods in combination and to make switching from one to another of the error concealment methods, such switching operation by manual operation is cumbersome and undesirable in view of operational reliability. On the other hand, in case of high error rate of the sample data reproduced from the VTR, sample data used in interpolation or replacement are mostly in the erroneous state and thus cannot be subjected to the above mentioned usual interpolation or replacement. It is however desirable that some sort error concealment can be made even on these occasions. Additionally, it occurs frequently that correct sample data are contained in sample data which have been determined to be in error in the course of the error correction process preceding error concealment. For example, in the course of the above-mentioned outer error correction, when the number of erasure pointers generated by the inner error correction product code exceeds the number of parities of the outer code, it may be envisaged to compute the syndrome of the outer code block, using the outer code, and not to perform error correction on the outer code block, when all of these syndromes are determined to be "0", under the assumption that all of the sample data of the outer code block are free of errors. However, in error correction/detection employing the inner code or inner parity, there is a risk that erroneous data will be deemed correct data since it is not certain if the error correction capability in the error correction/detection employing the inner code or parity has a sufficient detection capability to generate correct the erasure pointers, or if error detection by the outer code or parity exhibits a sufficient reliability. It is undesirable from the viewpoint of reliability to treat these sample data as being error free, while it is wasteful to treat them as being in error. When a weighted mean processing is to be performed in order to synthesize signals of at least another field from signals of a given field after error concealment, several horizontal delay devices are necessitated for error concealment, above all, two-dimensional error concealment, while several other horizontal delay elements are necessitated for weighted mean processing. However, use of the horizontal delay devices, dedicated to the error concealment and weighted mean processing, separately in the respective processing circuits, would be uneconomical. Finally, when weighted mean processing operations are performed at the upper and lower ends of the picture surface the image quality may be deteriorated and the picture may suffer from flickers or vertical movements. It is an object of the present invention to provide a video signal processing circuit in which the effect of the above mentioned drawbacks is reduced. The two part form of claim 1 is based on the article by Heitmann on pages 15-22 of the Jan/Feb 1987 issue of "Fernseh und Kino-Technik". This article is a general review of digital video recording technology which discloses, inter alia, the adoption of measures to conceal errors which are uncorrectable by the other error-correction techniques. GB-A-2,073,534 discloses a method of concealing errors in a digital television signal comprising selecting an algorithm from a plurality of algorithms for error-concealment. By operating each of the plurality of algorithms to predict known sample values, the algorithm producing the most accurate prediction for that known sample value is selected. According to the present invention, there is provided a video signal processing circuit for processing video signal sample data which is input thereto, comprising error correcting means for performing error correction on the input video signal sample data and outputting both error-corrected sample data and error flags indicating the error states of the various error-corrected data, and error concealment means supplied with the error-corrected data for performing error concealment on particular error-corrected data which are indicated by the error flags as still being in error, characterised in that the error concealment means uses, for the performing of error concealment, error-corrected data which, relative to the particular error-corrected data, are peripheral and/or temporally adjacent, the error concealment means having a plurality of different error concealment algorithms according to one of which the error concealment is performed on the particular error-corrected data, wherein the particular error concealment algorithm for the particular error-corrected data is selected on the basis of the error flags of the error-corrected data which, relative to the particular error-corrected data, are peripheral and/or temporally adjacent. The present invention can provide a video signal processing circuit in which effective error concealment may be performed over a wider range of error rates. The present invention may provide a video signal processing circuit whereby optimum error concealment may be performed within the feasible range even with a high error rate. The present invention may provide a video image processing circuit wherein the modeless concealment strategy is adopted in which the entire concealment algorithm is made to be independent of the current playback mode and the best possible concealment algorithm for the current error situation will always be selected. The present invention may provide a video image processing circuit wherein variable-length horizontal interpolation is adopted in which the number of the samples used in the horizontal concealment calculation can be automatically varied from two to six samples. The present invention may provide a signal processing circuit wherein ideal direction ranking may be adopted in which, instead of picking a simple ideal concealment direction, the concealment directions may be ranked from best to worst. The present invention may provide a video signal processing circuit wherein the luminance data are used to determine the ideal direction ranking, which direction ranking may be used for both luminance and chrominance concealment. The present invention may provide a video signal processing circuit wherein the error threshold puts a limit on the estimated concealment error value. The present invention may provide a video signal processing circuit wherein adaptive temporal replacement is adopted in which video data and error flags surrounding the point being concealed are examined to see if the data in the current frame is substantially the same as the video data in the preceding frame and, when the data are almost the same, video data from the preceding frame are used to conceal errors in the current frame. The present invention may provide a video signal processing circuit wherein the concealment circuitry has its own frame memory. The present invention may provide a video signal processing circuit wherein the maximum number of recursion levels allowed for recursive concealment is variable to allow the maximum concealment area covered by one error-free point to be changed. The present invention may provide a video signal processing circuit wherein, for points that may not actually be in error, the concealing value calculated by the concealment algorithm is compared with the value of the point being concealed and, if the difference is less than the pass-through threshold, the point being concealed is output as the concealed point. The present invention may provide a video signal processing circuit wherein, when performing the weighted mean processing for synthesize signals of at least another field from signals of a given field, for fixing the disrupted odd and even sequence of the fields, horizontal delay devices are used in common for the respective processing operations to reduce the number of the horizontal delay devices. The present invention may provide a video signal processing circuit wherein, when performing the weighted mean processing, the formulae at the upper and the lower edges of the picture surface, above all, the multiplication coefficients, are made to be different from those in the inner portions to prevent the picture from being affected at these upper and lower edges. In order that the present invention may be better understood, the following description is given, merely by way of example, with reference to the drawings, in which:- Fig. 1 is a block diagram showing the general organization of a video signal processing circuit according to an embodiment of the present invention and its peripheral circuitry. Fig. 2 is a block diagram showing a typical construction of a one-dimensional error concealment circuit. Fig. 3 shows the error state of sample data for illustrating the operating principle of the one-dimensional error concealment circuit. Fig. 4 is a block circuit diagram showing one embodiment of a variable-length interpolation circuit. Fig. 5 shows an array of sample data used at the time of two-dimensional error concealment. Fig. 6 shows an array of error flags used at the time of two-dimensional error concealment. Fig. 7 is a block circuit diagram of a ranking control circuit for two-dimensional error concealment. Fig. 8 is a block circuit diagram showing a more detailed construction of the ranking control circuit. Fig. 9 is a block circuit diagram showing a main part of the two-dimensional error concealment circuit and a gray flag processing circuit. Fig. 10 is a block circuit diagram for illustrating a typical construction for temporal replacement. Fig. 11 is a block circuit diagram for illustrating embodiments of high and low accuracy temporal interpolation circuits. Fig. 12 is a block circuit diagram for illustrating an embodiment of a low accuracy temporal replacement decision logic circuit. Figs. 13 and 14 illustrate the number of generations of repetitive replacement. Figs. 15 and 16 illustrate the range of repetitive replacement. Fig. 17 is a block circuit diagram of the repetitive replacement circuit. Fig. 18 is a block circuit diagram of a gray flag processing circuit. Fig. 19 is a block circuit diagram showing a weighted mean processing circuit and its peripheral circuit. Fig. 20 illustrates the weighted mean processing near the upper and lower edges of the picture. Fig. 21 is a block diagram for illustrating the principle of constituting a variable coefficient multiplication circuit by the bit shifting and summation. Fig. 22 is a chart for illustrating gain and delay characteristics of the line signals of the formed field at other than the upper and lower ends of the picture. Fig. 23 is a chart for illustrating gain and delay characteristics of the line signals of the formed field in the vicinity of the upper end of the picture, with the value of the weighting coefficient being fixed. Fig. 24 shows gain and delay characteristics of line signals of the formed image with the value of the weighting coefficient being varied from Fig. 22. Fig. 25 is a block diagram showing the organization of the variable coefficient multiplication circuit with the use of a read only memory. Fig. 1 shows, in a block diagram, a video signal processing circuit according to an embodiment of the present invention, and its peripheral circuit. In the present illustrative embodiment, signal processing is assumed to be performed on reproduction signals of a digital VTR of the so-called D-1 format. The digital VTR in this case is so constructed that digital video (and audio) signals are allocated to e.g. four channels and the digital signals of these four channels are recorded and/or reproduced in parallel by four rotary magnetic heads. Thus the four-channel reproduction signals ( a to d channel signals) from the four magnetic heads of the digital VTR are subjected to clock regeneration, demodulation and error correction by a so-called inner code, i.e. inner correction code or inner parity. The four-channel data thus subjected to inner code error correction are transmitted to field memories 101a, 101b, 101c and 101d shown in fig. 1. Each of these field memories 101a to 101d has a memory capacity of e.g. three fields. The video data of the respective channels sequentially read out from these field memories 101a to 101d are transmitted to deshuffle circuits 102a, 102b, 102c, 102d for deshuffling and then transmitted to outer code error correction circuits 103a, 103b, 103c, 103d for error correction by a so-called outer code, i.e. outer correction code or outer parity. At this time, the gray flags as later described are annexed to the data, in addition to the usual error flags. These four-channel video data, error flags and gray flags are transmitted to a deinterleaving circuit for deinterleaving and are grouped together, while being separated into a luminance component and a chrominance component, which are transmitted to a luminance component error concealment section 105Y and a chrominance component error concealment section 105C. The luminance component data and the chrominance component data, concealed of errors by the error concealment sections 105Y, 105C, respectively, are output by way of output circuits 106Y, 106C, respectively. The gray flag is briefly explained hearinafter. In the D-1 format digital VTR, a two-dimensional error correction is performed by a product code using so-called outer and inner codes. Thus, during recording, 360-byte-per-line sampling data in one channel are subjected to the product code error correction coding. First, at an interval of 30 bytes or 30 samples, each two byte outer code, that is outer correction code or outer parity, is generated and annexed and subjected to a sector array shuffling to form a 32 sample x 60 row product block array. Then, at an interval of 60 samples per row, each 4-byte inner code, that is, inner correction code or inner parity, is generated and annexed to form 32 rows of the inner code blocks, with each row consisting of 64 samples. Two of the 64-sample inner code blocks are connected together and a sync pattern (2 bytes) and an identification pattern (4 bytes) are annexed to a loading position to form a sync block. Recording on a magnetic tape is performed with a such sync block as one recording unit. For reproduction, an operation which is the reverse of the above described sequence is performed. Thus, two inner code blocks are taken out from the sync block and subjected to error correction by the inner code to produce data of the above mentioned product block array organization which are then input to the field memories 101a to 101d of Fig. 1 as the input data. In deshuffling circuits 102a to 102d, a deshuffling operation, which is the reverse of the above mentioned sector array shuffling operation, is performed. In the outer code correction circuits 103a to 103d, a so-called erasure correction is performed, at an interval of the 32-sample-per-column outer code block, using the two-byte outer code. The erasure pointer used at this time has been output at the time of the above mentioned inner code error correction. Meanwhile, when there is a large number of error samples in the inner code block such that error correction becomes impossible because the error correction ability of the inner code is overloaded, the inner code block in its entirety is deemed to be in error and erasure pointers are set. The inner code block is passed to erasure correction by the outer code. The outer code acts perpendicularly to the inner code. It is capable of detecting if any errors exist, and can correct one or two errors (erasures). Normally, when the number of erasure pointers is three or move (ie, the inner code is overloaded for three or move inner code blocks), the error correction capability of the outer code block is also overloaded and the entive block is marked as being in error for purposes of error concealment. However, when the error is a so-called random error, it occurs frequently that, even when a small number of sample data in the inner code block is in an error state, the remaining sample data are correct data, i.e. error-free data. Thus, in consideration that most data of the inner code block deemed to be in error in its entirety are correct data, all data in the outer code block may be assumed to be correct if the result of error detection by the outer code is determined to be free of errors. However, in view of the possibility of mistaken error detection, it is not desirable that the block be handled as completely correct data on the basis only of the results of error detection by the outer code. Thus, to indicate meaning of seemingly correct data gray flags are introduced. Thus, with sample data, deemed to be in error as a whole by inner code error detection but deemed to be free of error by the results of error detection by the outer code, the error flag is reset, while the gray flag is set. When the difference upon comparison of the original sample date with the result of error concealment is within a predetermined threshold, the probability is extremely high that the data are the correct data, so that the original sample data are handled as the correct data. The sample data which have been corrected for errors, inclusive of sample data which are in error and which have not been corrected for errors, are transmitted, along with the error flags and the gray flags, so as to be supplied to the error concealment units 105Y, 105C for error concealment. The arrangement of the luminance component error concealment unit 105Y and the chrominance component error concealment unit 105C, shown in Fig. 1, is hereinafter explained. Since the concealment units 105Y, 105C are of substantially the same construction, only one of the units, herein the luminance component error concealment unit 105Y, is explained, while the other nit is not explained for simplicity. To the luminance component error concealment unit 105Y, there are supplied, in association with the luminance component of the component digital video signals, sample data which have been corrected for errors as described above, error flags and the gray flags. Of these, the sample data and the error flags are first transmitted to a one-dimensional concealment circuit 111 for error concealment in the horizontal direction, that is in the direction of the horizontal scanning lines, and then transmitted to a two-dimensional concealment circuit 112 and a line delay circuit 113 having a delay time of 1H, i.e. one horizontal scanning period. The outputs (the sample data and the delayed error flags) from the two-dimensional concealment circuit 112 are transmitted to a line delay circuit 114 and a frame delay circuit 115 having a delay time of one frame (1F=2V=2 vertical scanning periods). The outputs from these line delay circuits 113, 114 and from the frame delay circuit 115 (sample data and error flags) are transmitted to the two-dimensional concealment circuit 112. The output signal from the line delay circuit 113 is the reference signal for 0H, whereas the output from the one-dimensional concealment circuit 111 corresponds to the sample data and error flags for -1H, that is, one line below the current line, the output from the line delay circuit 114 corresponds to the sample data and error flags for +1H, that is, one line above the current line and the output from the frame delay circuit 115 corresponds to the sample data and error flags for +1F, that is, the current line of the previous frame. In other words, sample data for the current line, the lines directly above and below the current line and the current line of the previous frame, are supplied to the two-dimensional error concealment circuit 112. If a delay T D caused by processing in the two-dimensional error concealment circuit 112 is to be taken into account, it is sufficient if the delay time in the line delay circuit 114 and the frame delay circuit 115 are set so as to be H-T D and F-T D , respectively. In the two-dimensional error concealment circuit 112, an optimum error concealment is performed, using the sample data on the above mentioned four lines. This two-dimensional error concealment circuit 112 has a plurality of error concealing functions, including interpolation in a plurality of directions, replacement of the sample data at the same position of the previous frame for the erroneous sample data or replacement of vicinal or neighboring sample data for the erroneous sample data, and execution of error concealment in an ideal direction which will minimize changes in the sample data. For finding this optimum direction, a ranking control circuit 117 is provided within the two-dimensional error concealment circuit 112. It is in this ranking control circuit 117 that the optimum direction of two-dimensional error concealment is found on the basis of the sample data and the error flags and, based on the results, an optimum two-dimensional error concealment is executed. In the above described manner, error concealment is performed on the erroneous sample data which have not been corrected for errors in the course of the error correction of the preceding stage. An weighted mean processing circuit is hereinafter explained. The sample data from the two-dimensional concealment circuit 112 are transmitted to an weighted mean processing circuit 120 by way of a gray flag processing circuit 118. To this weighted mean processing circuit 120, there are simultaneously suplied sample data at the relative position of +1H, that is, one line above the current line, from the line delay circuit 114, sample data at the relative position of +2H, that is two lines above the current line, after a delay introduced in a line delay circuit 121, and sample data at the relative position of -1H, that is one line below the current line, from the one-dimensional concealment circuit 111. In the weighted mean processing circuit 120, video sample data from a plurality of lines are summed together with a predetermined mixing ratio to constitute at least signals for another field from the signals of a given field. This processing is performed to compensate for disorders in the sequence of even- and odd-numberd fields brought about by different speed reproduction of VTR video signals. Meanwhile, if the processing time T D in the two-dimensional concealment circuit 112 or the processing time T G in the gray flag processing circuit 118 is to be taken into consideration, it is only sufficient to set the delay time in the line delay circuit 121 to 1H + T D + T G , while introducing each one delay circuit having a delay time equal to T D + T G between the line delay circuit 114 and the weighted mean processing circuit 120 and between the one-dimensional concealment circuit 111 and the weighted mean processing circuit 120. In the circuitry of Fig. 1, a signal delayed by 1H in the line delay circuit 113 is transmitted by way of the two-dimensional concealment circuit 112 and a gray flag processing circuit 118 to the weighted mean processing circuit 120 to provide a 0H or reference position signal. On the other hand, a line delayed by 1H in the line delay circuit 114 and the 1H delay signal further delayed through a line delay circuit 121 are transmitted to the weighted mean processing circuit 120 to provide a +1H signal, that is, the signal one line above the reference position signal and a +2H signal, that is, the signal two lines above the reference signal. The signal from the one-dimensional concealment circuit 111 proves to be the -1H signal, that is the signal one line below the reference signal. In this manner, line delay brought about by these line delay circuits 113, 114 simultaneously realizes line delay necessary for producing plural line signals at the weighted mean circuit. In other words, the line delay circuits 113, 114 are used simultaneously in the two-dimensional error concealment and in weghted mean processing. In this manner, only one delay circuit may be used in lieu of three line delay circuits dedicated to weighted mean processing in the conventional system, so that a significant saving may be realized in the memory capacity. In the circuitry of Fig. 1, of the four video signals transmitted to the weighted mean processing circuit 120, the -1H signal is directly supplied from the one-dimensional concealment circuit 111 and thus remains in the state prevailing before the two-dimensional concealment is executed. However, in view of the low weighting factor for the -1H sample data at the time of the weighted mean processing operation, it is not crucial to perform high precision concealment and hence no practical problem is raised. It is however possible to add a line delay circuit in the weighted mean processing circuit to delay the signal from the line delay circuit 121 further by 1H and to supply the thus delayed signal to the circuit 120 without using the video signal from the one-dimensional concealment circuit 111. In this case, the delay of the output signal from the delay circuit 114 is the reference 0H and that of the output signal from the two-dimensional concealment circuit 112 is -1H such that the totality of the four input video signal is replaced by signals which have undergone the two-dimensional concealment. In this case, although two line delay circuits each in the two-dimensional error concealment processing section and in the weighted mean processing circuit, thus totalling four line delay circuits, are necessitated, one line delay circuit may be saved as compared with the conventional system. The basic setup of the error concealment in the embodiments of the present invention is hereinafter explained. An error concealment algorithm acts on luminance video sample data and multiplexed chrominance video sample data to inspect the associated error flags. It is assumed with the concealment algorithm that both of a pair of chrominance data exist in association with one of two luminance sample data. Even when the video sample data supplied to the error concealment section assume the values in the range from 01H to FEH of the hexadecimal number system, the concealment algorithm is able to produce output sample data in the range from 00H to FFH of the hexadecimal number system. In other words, the concealment algorithm accepts sample data in the range from 00H to FFH of the hexadecimal number system. The error flag "1" indicates that the preceding error correction circuit has marked a given sample datum as being in error. The concealment algorithm requires that all of the of the error flags in the horizontal and vertical image blanking areas be of the value "1". The relation between the luminance data concealment and the chrominance data concealment is hereinafter explained. The error concealment algorithm is able to use the luminance date to generate the ranking of the concealment direction from the best to the worst. In regular video data, luminance data provide a satisfactory prediction of the concealment direction for both the luminance data and the chrominance data, so that this ranking of the concealment direction may be used for both the luminance and chrominance concealments. It may however occur that a calculation for concealment in the direction of the best ranking cannot be executed because of the error flags. Hence, for each of the luminance and the chrominance, the optimum direction is found within the possible range of the calculation operation for concealment. It is because if the error pattern for luminance differs from that for chrominance, the practical concealment direction for luminance differs from that for chrominance. Meanwhile, with the present illustrative embodiment, a one-dimensional error concealment and a two-dimensional error concealment are performed in this sequence. Two different classes of the concealment strategies, that is the true and the temporary strategies, are employed for the one-dimensional error concealment. The true concealment strategies are variable-length-interpolation, neighbor replacement and distant replacement, as later described, whereas temporary concealment strategy means long distance replacement and last good sample replacement, similarly as later described. The true strateies are a subset of the two-dimensional concealment strategies in the broad sense. If one of the true strategies is possible, and if the two-dimensional concealment section cannot find better method, then the two-dimensional concealment section simply passes through the one-dimensional results. However, if a better two-dimensional strategy is found then the two-dimensional section overwrites the one-dimensional result with a two-dimensional result. Temporary one-dimensional concealment results are always overwritten by a two-dimensional concealment strategy. These temporary concealment strategies are provided so that one-dimensional concealment can conceal all erroneous points. The two-dimensional error concealment is actually a superset of one-dimensional error concealment. In the present embodiment, since the sample data after passing through one-dimensional error concealment is passed to the two-dimensional error concealment, the calculation in the horizontal direction is omitted in the two-dimensional concealment circuit. That is, the two-dimensional circuit simply determines if the appropriate concealment was already performed by the one-dimensional concealment circuit. The one-dimensional error concealment means an error concealment in the horizontal direction (H-direction) employing data of samples which are in the vicinity of the reference sample point to be concealed and which are on the same line as that on which the reference sample point is located. It is classified into an interpolation employing interpolated values obtained by taking a weighted mean of the neighboring sample data and a replacement directly employing any one of the neighboring sample data. In the interpolation in the horizontal direction, 2 to 6 neighboring samples are used by way of a variable-length interpolation, as will be explained subsequently. The number of samples is determined by inspecting the error flags and finding the longest possible error-free concealment length. Fig. 2 shows a practical example of the aforementioned one-dimensional error concealment circuit 111, and Fig. 3 shows, for illustrating the operation of the one-dimensional error concealment, the error state of neighboring sample data on the same line as that on which the erroneous sample data is located. The practical one-dimensional error concealment circuit shown in fig. 2 is roughly made up of an interpolating section and a replacement section. The interpolation section performs error concealment using interpolated values, for example, weighted mean values, based on a plurality of sample data on both sides of the erroneous sample data and, above all, performs variable-length interpolation using a variable number of sample data on both sides of the erroneous sample data. The replacement section operates to substitute one of the sample data in the vicinity of and on the same line as the erroneous sample data for the erroneous sample data. With a sample data P0, shown in Fig. 3, as the reference sample data to be concealed by the one-dimensional error concealment, the variable length interpolation section includes a variable length interpolation circuit 11 for calculating a weighted mean value using a plurality of sample data, such as P1 to P3 and M1 to M3, on both lateral sides of the reference sample data P0, and a sample number control circuit 13 for discriminating error flags FP1 to FP3 and FM1 to FM3 associated with these sample data P1 to P3 and M1 to M3 and controlling the number of the sample data used for calculating the weighted mean value and the weighting coefficients on the basis of the results of discrimination. The replacement section includes a replacement circuit 12 for substituting one error-free sample data from the sample data P1 to P3 and M1 to M3 for the reference sample data P0 and a replacement mode control circuit 14 for discriminating the error flags FP1 to FP3 and FM1 to FM3 and identifying the sample data employed for replacement based on the results of discrimination. The error-concealed sample data from the circuit 11 and 12 supplied to a selector 16 where the sample data from the interpolating operation is taken out at a terminal 18, or the sample data from the replacement operation is taken out at the terminal 18, in dependence upon whether the interpolation was performed or interpolation was not feasible and hence replacement was performed. Needless to say, when the reference sample data P0 is error-free, with the error flag being "0", the sample data P0 is directly output at the terminal. The output sample data from the terminal 18 is transmitted to the two-dimensional error concealment circuit 112 shown in Fig. 1. It is noted that, since the sample data along a given line of the image are distributed on the four channels, as described hereinabove, for recording or reproduction, sample data of the same channel are separated with the interposition of the other three channels therebetween. In other words, with the above mentioned 6-sample interpolation for restoration of sample data of a given channel, samples of the three other channels are employed. Thus, when the number of samples for an arithmetic operation for interpolation , is increased beyond six samples, the samples of the same channels as that of the reference sample to be concealed would be used, so that an advantage corresponding to the increase in hardware cannot be expected. The reason is that, when an error flag of a sample is set, the risk is high that an error flag is also set for the sample from the same channel in the vicinity of the erroneous sample. Thus it may be said that the length of interpolation in excess of 6 samples would be useless in view of the increased hardware volume. The operation of the one-dimensional error concealment circuit is hereinafter explained. As shown in Fig. 3, this one-dimensional error concealment circuit are supplied with, for example, seven sample data P3, P2, P1 P0, M1, M2, M3 on the same line of the video signals, and error flags FP3, FP2, FP1, FP0, FM1, FM3, associated respectively with these sample data. The sample data P0 is the reference sample data to be error concealed, the sample data P1, P2, P3 are the three sample data on the left side of and closer in this order to the sample data P0 and the sample data M1, M2, M3 are the three sample data on the right side of and closer in this order to the sample data P0. The sample data P3, P2, P1, M1, M2, M3 on both sides of the reference sample data P0 are supplied to the variable length interpolating circuit 11 and the replacement circuit 12. The error flags FP3, FP2, FP1, FM1, FM2 and FM3 are supplied to the sample number control circuit 13 and the replacement mode control circuit 14. The reference sample data P0 and the error flags FP0 are supplied to a latch 15 and a selector 16. In the sample number control circuit 13, the state of the error flags of the plural sample data on both sides of the erroneous sample data P0 to be error concealed is discriminated, and a control signal for weighted mean processing is supplied to the variable-length interpolation circuit 11. In the specific embodiment, shown in Figs. 2 and 3, the above six error flags FP3, FP2, FP1, FM1, FM2 and FM3 are discriminated, and a control signal for weighted mean processing with the exclusion of the erroneous simple data (with error flag "1") is supplied to the variable length interpolation circuit 11. In the variable length interpolating circuit 11, a weighted mean processing operation is performed with the exclusion of those of the six sample data P3, P2, P1, M1, M2, M3 for which the error flags are "1" indicating an error. In Fig.3, the mark ○ indicates an error-free sample data, the mark x indicates the relerence sample data being concealed, the mark Δ indicates at least one of the left and right sample data being in error and the mark □ indicates the sample data for which there is no necessity to consider the error state. Fig. 3 a shows the state in which the reference sample data P0 is in error while the six sample data on both sides of the sample data P0 are error-free, that is, the error flags FP3, FP2, FP1, FM1, FM2 and FM3 are "0" indicating no error. A weighted mean is found using the six samples P3 to M3. More specifically, with the weighting coefficients K1, K2 and K3, the weighted mean P is given by P = K1 x (P1+M1) + K2 x (P2+M2) + K3 x (P3+M3). Fig. 3b shows the state in which four sample data P2, P1, M1 and M2 on both sides of the reference sample data P0 are error-free, while at least one of the sample data P3 and M3 is in error, that is, the state in which the error flags FP2, FP1, FM1 and FM2 are "0" and at least one of the error flags FP3 or FM3 is "1" indicating an error. At this time, a weighted mean is found using from samples P2 to M2 to find the weighted mean P P = K1 x (P1+M1) + K2 x (P2+M2). Fig. 3c shows the state in which two sample data P1 and M1 on both sides of the sample data in error P0 are error-free and at least one of sample data P2 or M2 is in error, that is the state in which the error flags FP1 and FM1 are "0" and at least one of the error flags FP2 or FM2 is "1". The two samples P1, M1 are used to find the weighted mean P, P = K1 x (P1+M1) The weighted mean P thus obtained at the variable-length interpolating circuit 11 is supplied to the selector 16 shown in Fig. 2. Fig. 4 shows a specific example of the variable length interpolation circuit 11 organized for specific values of the coefficients K1, K2 and K3. Thus, in consideration of the easiness of circuit constitution and reduction in the number of the component parts, the following values are used for the coefficients K1, K2 and K3. (a) For 2 samples K1 = 1/2 = 0.5, K2 = K3 = 0 (b) For 4 samples K1 = 1/2 + 1/8 + 1/16 = 0.6875 K2 = -(1/2 + 1/4)/4 = -0.1875, K3 = 0 (c) For 6 samples K1 = 1/2 + 1/4 = 0.75, K2 = -(1/2 + 1/8)/2 = -0.3125, K3 = 1/16 = 0.0625 These values of the coefficients are expressed as the sum of powers of 2 and the results of multiplication may be obtained easily by bit shifting and summation at the time of actual digital signal processing. Referring to Fig. 4, if the sample data of the video signal is an 8-bit word, each bit of each sample data in the drawing is indicated by a suffix from the MSB to the LSB. Thus, with a sample data P1, these bits are indicated as P1₇, P1₆, P1₅, P1₄, P1₃, P1₂, P1₁ and P1₀. Of the six 8-bit sample data, sample data P1 and M1 are supplied to a summation circuit 21, sample data P2, M2 are supplied to a summation circuit 26 and sample data P3, M3 are supplied to a summation circuit 31. As described hereinabove, the sample number control circuit 13 determines the number of samples used for interpolation, in dependence upon the error flags FP1 to FP3 and FM1 to FM3, and outputs a 2-sample control signal XS2, a 4-sample control signal XS4 and a 6-sample control signal XS6, by way of a decoder or the like. In the following, it is assumed that the 6-sample control signal XS6 is output, and the weighted mean value P = (1/2+1/4) x (P1+M1) - (1/2+1/8)/2 x (P2+M2) + 1/16 x (P3+M3) for 6 samples is to be found. Sample data P1 and M1 are summed together at the summation circuit 21. The upper five bits of the sum (P1+M1) are supplied to five bits of the zeroer 22, the upper sight bits of the sum (P1+M1) are supplied to eight bits of a B input of the summation circuit 23, the seven upper order bits of the sum (P1+M1) are supplied to the lower seven bits of an A input of the selector 24 and the upper six bits of the sum (P1+M1) are supplied to the lower six bits of the B input of the selector 24. By such coupling of the summation circuit 21 and the selector 22, the output of the summation circuit 21 is shifted by four bits towards the side LSB to be multiplied by 2⁻⁴ or 1/16 to produce a result (P1+M1)/16. Similarly, by coupling the summation circuit 21 with the input B of the summation circuit 23, the output (P1+M1) of the circuit 21 is shifted by one bit towards the side LSB (x2⁻¹) to produce the result (P1+M1)/2 and, by coupling the circuit 21 to the input A of the selector 24, the sum (P1+M1) is shifted by two bits towards the side LSB to produce the result (P1+M1)/4. Finally, by coupling the circuit 21 to the input B of the selector 24, the sum (P1+M1) is shifted by three bits towards the side LSB (x2⁻³) to produce the result (P1+M1)/8. The zeroer 22 allows date to pass through when selected by the above mentioned 4-sample control signal XS4. For 6-sample operation, the zerore 22 is not selected, that is, its output is zero, which value is supplied to the input A of the summation circuit 25. The selector 24 becomes valid when selected by the 6-sample control signal XS6 so that the output (P1+M1)/4 of the selector 24 is supplied to the input A of the summation circuit 23. Thus the output of the circuit 23 is (P1+M1)/2 + (P1+M1)/4 which output is transmitted to the input B of the summation circuit 25. The result (P1+M1)/2 + (P1+M1)/4 is output from the summation circuit 25 and transmitted to the input B of the summation circuit 33. On the other hand, sample data P2, M2 are summed together at the summation circuit 26. The upper eight bits of the sum (P2+M2) are supplied to the eight bits of the input B of the summation circuit 27, the upper seven bits of the sum (P2+M2) are supplied to the lower seven bits of the input A of the selector 28 and the upper six bits of the sum (P2+M2) are supplied to the lower six bits of the input B of the selector 28. In this manner, with the summation circuit 26 connected to the input B of the summation circuit 27, the sum (P2+M2) is shifted by one bit towards the side LSB to find the result (P2+M2)/2 and, with the summation circuit 26 connected to the input A of the selector 28, the sum (P2+M2) is shifted by two bits towards the side LSB to find the result (P2+M2)/4. Similarly, with the summation circuit 26 connected to the input B of the selector 28, the sum (P2+M2) is shifted by three bits towards the side LSB to find the result (P2+M2)/8. During the 6-sample operation, the input B (P2+M2)/8 of the selector 28 is selected and supplied to the input A of the summation circuit 27. Thus the output of the summation circuit 27 is (P2+M2)/2 + (P2+M2)/8. The upper seven bits of the output of the summation circuit 27 are supplied to the lower seven bits of the input A of the selector 29, while the upper eight bits of the output of the summation circuit 27 are supplied to the eight bits of the input B of the selector 29. In this manner, with the summation circuit 27 connected to the input A of the selector 29, the output of the summation circuit 27 is shifted by two bits towards the LSB to find the result of the arithmetic operation ((P2+M2)/2 + (P2+M2)/8)/4 and, with the summation circuit 27 connected to the input B of the selector 29, the output of the summation circuit 27 is shifted one bit towards the side LSB to find the result of the arithmetic operation ((P2+M2)/2 + (P2+M2)/8)/2. During the 6-sample operation, the input B of the selector 29 is selected and the output ((P2+M2)/2 + (P2+M2)/8)/2 is supplied to the decrementing input M of the subtractor 30. The sample data P3 and M3 are summed together at the summation circuit 31 and the upper five bits of the sum (P3+M3) is supplied to the five bits of the zeroer 32. With the summation circuit 31 connected to the zeroer 32, the output of the summation circuit 31 is shifted by four bits towards the side LSB to find the result of the arithmetic operation (P3+M3)/16. During the 6-sample operation, the output (P3+M3) of the zeroer 32 is supplied to the five bits of the input A of the summation circuit 33, so that the result of the arithmetic operation (P1+M1)/2 + (P1+M1)/4 + (P3+M3)/16 is obtained at the summation circuit 33. The output (P1+M1)/2 + (P1+M1)/4 + (P1+M1)/16 of the summation circuit 33 is supplied to a incrementing input P of the subtractor 30, so that the above mentioned weighted mean P P = (1/2+1/4) x (P1+M1) - (1/2+1/8)/2 x (P2+M2) + 1/16 x (P3+M3) This interpolation data 1(these bits are indicated as I0 to I7) are supplied to the selector 16 shown in Fig. 2. For 4-sample and 2-sample operations, the weighted mean values P P = (1/2+1/8+1/16) x (P1+M1) -(1/2+1/4)/4 x (P2+M2) (for 4 samples) P = 1/2 x (P1+M1) (for 2 samples) are found, respectively, at the variable-length interpolating circuit 11, under control of the sample number control circuit 13. The operation of replacement in the replacement section of Fig. 2, including the replacement circuit 12 and the replacement control circuit 14, is hereinafter explained. The replacement operation is performed mainly at the replacement circuit 12 for other than the three error modes shown in Figs. 3a, 3b and 3c as described above. The state of the error flags FP1, FM1 is determined in the replacement mode control circuit 14 and, when one of the error flags FP1 or FM1 is "1" indicating an error, the replacement of the erroneous sample data P0 is performed with the use of the error free one of the sample data P1 and M1. This replacement is referred to as neighbor replacement. When both the error flags FP1 and FM1 are "1" (indicating an error) and at least one of the error flags FP2 or FM2 is "0" (indicating no error), replacement of the erroneous sample data P0 is performed using an error-free one of the sample data P2 and M2. This replacement is referred to as distant or indirect replacement. When both the error flags FP2 and FM2 are "0" (indicating no error), the sample data P2 is used preferentially. When the error flags FP2, FP1, FM1 and FM2 are all "1" (indicating an error) and at least one of the error flags FP3 or FM3 is "0" (indicating no error), replacement of the erroneous sample data P0 is performed using error-free one of the sample data P3 or M3. This is termed as very distant or long-distance replacement. Meanwhile, when both the error flags FP3 and FM3 are "0" indicating no error, the sample data P3 is used preferentially. When the error flags FP3, FP2, FP1, FM1, FM2 and FM3 are all "1" indicating an error, the last error-free sample data is used for replacement of the erroneous sample data P0. The last error-free sample data means the stored sample data obtained after sequentially updating one-sample data stored in a latch by the error-free sample data on the same line. This replacement is termed a last good sample replacement. The sample data after such replacement is supplied to the selector 16. More specifically, three sample data, that is the sample data (weighted mean values) obtained at the variable length interpolation circuit 11, sample data obtained at the replacement circuit 12 and the sample data P0, are supplied to the selector 16 where one sample data is selected on the basis of the state of the error flag FP0 and the control signal from the interpolation/replacement control circuit 17 and taken out at the terminal 18. Thus, when the error flag FP0 is "0" (indicating no error) at the selector 16, the sample data P0 is taken out. When the error flag FP0 is "1" (indicating an error) and the interpolation is feasible, the above mentioned weighted mean value P (interpolated sample data) is taken out from the variable length interpolating circuit 11. If interpolation is not feasible, sample data obtained by replacement from the replacement circuit 12 is taken out. The output sample data is supplied to a two-dimensional error concealment circuit 112 shown in Fig. 1. The basic principle of the two-dimensional error concealment is explained by referring to Figs. 5 and 6. The two-dimensional error concealment circuit 112 shown in Fig. 1 makes use of video data from the current line, the previous line, the next line, and the corresponding line in the previous frame. By examining this two-dimensional video data, the concealment algorithm tries to find the direction in which the video data is changing most slowly. This ideal direction is the best direction for performing concealment calculations. Possible directions in this algorithm are horizontal, vertical, diagonal minus (negative slope) and diagonal plus (positive slope). The concealment algorithm attempts to rank these possible directions from best to worst. Other two-dimensional concealment operations are performed when an ideal direction cannot be determined, or if the ideal direction concealment calculation is not possible. These concealment operations are various kinds of interpolation and replacement. Fig. 5 shows sample data supplied from the one-dimensional error concealment circuit 111, line delay circuits 113, 114, and the frame delay circuit 115 of Fig. 1 to the two-dimensional concealment circuit 112. Fig. 6 shows error flags associated with these sample data. Referring to Fig. 5, with the reference sample data P0 to be concealed for error, three sample data each on the left and right sides of the reference sample data P0 on the same line, that is, the current line, are P3, P2, P1, M1, M2, M3. In association with these seven sample data, sample data on the previous line or upper line are PP3, PP2, PP1, PP0, PM1, PM2 and PM3, while sample data on the next line on the lower line are NP3, NP2, NP1, NP0, NM1, NM2 and NM3 and sample data on a line of a previous frame corresponding to the current line are LP3, LP2, LP1, LP0, LM1, LM2 and LM3. The range shown in Fig. 5 is termed a concealment window, which includes all of the sample points handled during the arithmetic operation for concealment. Referring to Fig. 6, the error flag associated with the sample data P0 isFP0, while the error flags associated with the sample data P3 to P1, M1 to M3, PP3 to PM3, NP3 to NM3 and LP3 to LM3 are FP3 to FP1, FM1 to FM3, FPP3 to FPM3, FNP3 to FNM3 and FLP3 to FLM3, respectively. For error concealment of the reference sample data P0, if the error concealment direction is the horizontal or H direction, the sample data in use are at least P1 and M1 and, with the variable-length interpolation, the sample data in use are P3, P2, P1, M1 M2 and M3. If the error concealment direction is the vertical or V direction, sample data in use are PP0 and NP0. Similarly, if the concealment direction is diagonal minus (D₋) or diagonal plus (D+), sample data in use are PP1 and NM1 or PM1 and NP1, respectively. The above applies for both interpolation and replacement. Other methods of replacement include replacement with an error-free sample data of the preceding frame or field showing high temporal correlation or replacement with previously error concealed sample data. For determining the direction for the above described interpolation or replacement, concealment errors (conversely, concealment accuracy) in plural different directions are found using sample data in the vicinity of the reference sample data to be concealed and the concealment errors in the respective directions are compared to find the best concealment direction which will minimize the concealment error. The ranking control circuit is provided for finding the concealment error or accuracy in each of the error concealment directions and ranking the error concealment directions in the order of preference. Thus the two-dimensional error concealment circuit 112 shown in Fig. 1 includes the ranking control circuit 117 for selecting the ideal concealment direction error concealment circuit actual interpolation and replacement. Fig. 7 is a block circuit diagram showing on example of the ranking control circuit 117. In Fig. 7, an H concealment accuracy output circuit 41 functions to predict the accuracy of error concealment in the H or horizontal direction on the basis of the concealment error in the H direction in the vicinity of the reference sample data P0 to be concealed for error. Thus the circuit 41 includes a horizontal up or H(U) error calculating circuit 41a for calculating one-side concealment error using sample data on the line above the reference sample data, a horizonal down or H(D) error calculating circuit 41b for calculating one-side concealment error using sample data on the line below the reference sample data, and an averager/selector circuit 41c for calculating an average value of the output of the H(U) error calculating circuit 41a and the output of the H(D) error calculating circuit 41b. The H(U) error calculating circuit 41a is supplied with sample data PP5, PP2, PP1, PP0 and PM1, PM2, PM3 on the line above the reference data sample P0 and the corresponding error flags FPP3, FPP2, FPP1, FPP0 FPM1, FPM2, FPM3 and a first one-side concealment error in the H direction (for the case where the error flags allow six-sample interpolation) |PP0-(0.75(PP1+PM1)-0.3125(PP2+PM2)+0.0625(PP3+PM3))| is found. Other interpolation equations are used if the error flags permit only two-sample or four-sample interpolation (as described above in the section titled "EXANPLE OF VARIABLE LENGTH INTERPOLATION"). On the other hand, the H(D) error calculating circuit 41b is supplied with sample data NP3, NP2, NP1, NP0, NM1, NM2, NM3 on the line below the reference sample data P0 and the corresponding error flags FNP, FNP2, FNP1, FNP0, FNM1, FNM2, FNM3 and a second one-side concealment error in the H direction (for the six-sample interpolation case) |NPO-(0.75(NP1+NM1)-0.3125(NP2+NM2)+0.0625(NP3+NM3))| are supplied to the averager/selector circuit 41c where an average value of the first and second one-side concealment errors in the H direction is computed. That is, the concealment error E(H) in the H direction (for the six-sample interpolation case) E(H)=(|PP0-(0.75(PP1+PM1)-0.3125(PP2+PM2)+0.0625(PP3+PM3))| + |NP0-(0.75(NP1+NM1)-0.3125(NP2+NM2)+0.0625(NP3+NM3))|)/2 is found. The concealment error E(H) in the H direction thus found is transmitted to a ranking decision circuit 45. Meanwhile, if variable length interpolation is not possible due to the error flags of the first one-side concealment error in the H direction, such as the error flag FPP1 for sample data PP1, is "1", indicating an error, the concealment error E(H) in the H direction may be determined solely by the second one-side concealment error, such that E(H)=|NP0-(0.75(NP1+NM1)-0.3125(NP2+NM2)+0.0625(NP3+NM3))|. For the concealment error E(H) in the H direction, a concealment error for variable-length interpolation using a weighted mean value for up to 6 samples at the maximum may be found, as in the aforementioned specific example of finding the one-dimensional error concealment. An invalied signal (NG signal) is employed, which shows that the arithmetic operation for finding the concealment error cannot be performed due to the state of the error flag of the sample data for calculating the concealment error in the H direction. That is, when the error flag of one of sample data employed for calculating the first one-side concealment error in the H direction, such as error flag FPP1 for PP1, and the error flag for one of sample data employed for calculating the second one-side concealment error in the H direction, such as error flag FNP1 for NP1, are both "1" indicating an error, it becomes impossible to compute the concealment error E(H) in the H-direction. At this time, the invalid signal HNG for the H direction is output and transmitted via output terminal 46 to the main part of the two-dimensional error concealment circuit, as later described, so that the H direction is no longer taken into account as the ideal direction for two-dimensional error concealment. That is, this "H" direction is excluded from the consideration of the error concealment direction. In the present illustrative embodiment, the first and second one-Bide concealment errorS in the H direction are compared with a predetermined threshold value T. When at least one of the concealment errors is above the threshold value T, as a result of this comparison, the invalid signal HNG in the H direction is output, so that the H direction is not deemed to be an ideal direction. Since the concealment error at the vicinal position predicts the concealment error at the concealed point, the threshold value T enforces a maximum value of the predicted concealment error. The threshold T may be variable and adapted to be set from outside. When the value of the threshold T is reduced, the ideal direction for two-dimensional error concealment may be determined with a higher accuracy, however, the error concealment direction may not be determinable for some date sample. Conversely, when the value of the threshold T is increased, the error concealment direction in many positions can be determined with poor accuracy. A V concealment accuracy output circuit 42 function to predict the accuracy in error concealment in the vertical or V direction on the basis of the concealment error in the V direction in the vicinity of the reference sample data P0. Thus the circuit 42 is constituted by a vertical left or V(L) error calculating circuit 42a for calculating the one-side concealment error using a sample data P1 on the left side of the reference sample data P0 and sample data PP1 and NP1 above and below the sample data P1, a vertical right or V(R) error calculating circuit 42b for calculating the one-side concealment error using a sample data M1 on the right side of the reference sample data P0 and sample data PM1 and NM1 above and below the sample data M1, and an averager/selector circuit 42c for calculating an average value of the outputs of the circuits 42a and 42b. Thus, in the V(L) error calculating circuit 42a, V(R) error calculating circuit 42b and the averager/selector circuit 42c, the concealment error E(V) E(V)=(|P1-(PP1+NP1)/2|+|M1-(PM1+NM1)/2|)/2 is found on the basis of the first one-side concealment error is the V direction |P1-(PP1+NP1)/2| and the second one-side concealment error in the V direction. |M1-(PM1+NM1)/2| If one of the one-side concealment errors cannot be calculated, then the concealment error is the calculable one-side concealment error. This concealment error E(V) in the V direction is supplied to the ranking decision circuit 45. When the concealment error cannot be computed, the invalid signal VNG for the V direction is output via output terminal 47, as in the case of finding the concealment error in the H direction. It is also determined if the first and the second one-side concealment errors are larger than the predetermined threshold T. If the errors are larger than the threshold value, the invalid signal VNG is output, so that the V direction is discarded from consideration of the ideal direction for two-dimensional error concealment. The D₋ concealment accuracy output circuit 43 functions to predict the accuracy of error concealment in the D₋ direction, that is, the diagonal minus or negative slope on the basis of the concealment error in the D₋ direction in the vicinity of the erroneous sample data. Thus the circuit 43 is constituted by a diagonal minus left or D₋(L) error calculating circuit 43a for calculating the one-side concealment error using sample data P1 on the left side of the reference sample data P0 and sample data PP2, NP0 on both ends of the negative diagonal line passing through the sample data P1, a diagonal minus right or D₋(R) error calculating circuit 43b for calculating the one-side concealment error using a sample data M1 on the right side of the sample data P0 and sample data PP0, NM2 on both ends of a negative diagonal line passing through the sample data M1, and an averager/selector circuit 43c for calculating the average value of the output of the D₋(L) error calculating circuit 43a and the D₋(R) error calculating circuit 43b. That is, in the D₋(L) error calculating circuit 43a, D₋(R) error calculating circuit 43b and the average value/selector circuit 43c, a first one-side concealment error in the D₋ direction |P1-(PP2+NP0)/2| a second one-side concealment error in the D₋ direction |M1-(PP0+NM2)/2| and a concealment error E(D₋) in the D₋ direction E(D₋)=(|P1-(PP2+NP0)/2|+|M1-(PP0+NM2)/2|)/2 are found. The concealment error E(D₋) in the D₋ direction is supplied to the ranking decision circuit 45. If one of the one-side concealment errors cannot be calculated, then the concealment error is the calculable one side concealment error. Meanwhile, if the concealment error E(D₋) in the D₋ direction cannot be computed or the first and second one-side concealment errors are larger than the predetermined threshold T an invalid signal MMG in the D₋ direction, wherein M stands for diagonal "minus", is output via output terminal 48, so that the D₋ direction is discarded from consideration of the ideal direction for two-dimensional error concealment. The D+ concealment accuracy output circuit 44 functions to predict error concealment accuracy in the D+ direction, that is diagonal plus or positive direction on the basis of the concealment direction in the D+ direction in the vicinity of the reference sample data P0. Thus the circuit 44 includes a diagonal plus left or D+(L) error calculating circuit 44 for calculating a one-side concealment error using a sample data P1 on the left side of the reference sample data P0 and sample data PP0, NP2 on both ends of a diagonal pulus passing through the sample data P1, a diagonal plus right or D+(R) error calculating circuit 44b for calculating a one-side concealment error using a sample data M1 or the right side of the sample data P0 and sample data on both ends of a diagonal minus passing through the sample data M1, and an averager/ selector circuit 44c calculating an average value of the outputs of the D+(L) error calculating circuit 44a and the D(R) error calculating circuit 44b. That is, in the D+(L) error calculating circuit 44a, D+(R) error calculating circuit 44b and the averager/selector circuit 44c, a first one-side concealment error in the D+ direction |P1-(PP0+NP2)/2| a second one-side concealment error in the D+ direction |M1-(PM2+NP0)/2| and a concealment error E(D+) in the D+ direction E(D+)=(|P1-(PP0+NP2)/2|+|M1-(PM2+NP0)/2|)/2 are found. The concealment error E(D+) in the D+ direction is supplied to the ranking decision circuit 45. If one of the one-side concealment errors cannot be calculated, then the concealment error is the calculable one-side concealment error. Meanwhile, if the concealment error E(D+) in the D+ direction cannot be computed or the first and second one-side concealment errors are larger than the predetermined threshold T, an invalid signal PNG in the D+ direction, wherein P stands for diagonal "plus", is output via output terminal 49, so that the D+ direction is discarded from consideration of the ideal direction for two-dimensional error concealment. Then, in the ranking decision circuit 45, the remaining concealment errors E(H), E(V), E(D₋) and E(D+), which have not been excluded, are compared to each other and the concealment direction ranking (sequence of preference) is determined in the order of the increasing magnitude (ie, the direction with the smallest error has the highest preperence.). If the concealment error values in the respective directions are equal, preference is in the order of H direction, V direction, D₋ direction and D+ direction. The ranking flags (plural bits) from the ranking decision circuit 45 are supplied to the main part of the two-dimensional error concealment circuit as later described. Meanwhile the arithmetic operation for concealment can nnot always be executed in any desired direction, as a function of the status of the error flags. The direction effectively selected as the ideal direction means the direction in which the error flags permit an actual arithmetic operation for concealment and which has the highest ranking. The ranking of the ideal direction is computed using luminance sample data. This is because the luminance data has broader bandwidth and thus more detail than the chrominance data. The error flag states for luminance and chrominance are examined separately. Because of the error flags, the selection of the highest ranking direction in which the calculation for actual concealment may be executed is completely independent so that the direction of actual luminance concealment may differ from the direction of actual chrominance concealment. Although the processing operation for determining the ideal direction of interpolation has been mainly explained in the foregoing, the ideal direction may be determined in case of the replacement by ranking the directions to be replanced. Interpolation in the horizontal direction may be variable length interpolation using up to six samples as explained in the foregoing. A more specific example of ranking control with the above taken into account will be explained by referring to Fig. 8. In this figure, the H concealment accuracy generation circuit 41 is adapted to find the concealment error on the occasion of performing the variable-length interpolation of up to a maxiimum of the 6 samples. The H(U) error computing circuit 41a in this H concealment accuracy output circuit 41 computes one-side concealment error using sample data on a line above the line of the reference sample data P0. Within this H(U) error calculating circuit 41a, there is provided a variable length interpolation circuit 241 for executing the above mentioned variable-length interpolation on the basis of the six sample data PP3, PP2, PP1, PM1, PM2 and PM3. When six samples are available, the variable-length interpolation circuit 241 finds an interpolated value PP0 INT PP0 INT =K1 x (PP1+PM1)+K2 x (PP2+PM2)+K3 x (PP3+PM3) using the above mentioned formula for finding a weighted mean value of six samples. With four or two available samples, the interpolated value PP0 INT may naturally be found using the respective formulae. The interpolated values thus found by the variable length interpolating circuit 241 is transmitted to an interpolation/replacement selector 242. Substitution data in the H direction from a replacement circuit 243 are supplied to the interpolation/replacement selector 242. Vicinal sample data PP1 and PM1 on the upper line are supplied to the replacement circuit 243. One of these sample data is selected and transmitted to the selector 242. The selector 242 is switched to one of the replacement data or the variable-length interpolation data, in dependence upon whether the error flags prohibit or allow interpolation of one-side data. as will be described. The output data from this interpolation/replacement selector 242 are transmitted via a timing latch 245 to a subtractor/comparator 246. The subtractor/comparator 246 takes the difference between the output from the latch 245 and the reference sample data PP0 on the upper line and outputs the difference as the one-side concealment error, while effecting comparative discrimination of whether the one-side concealment error exceeds the threshold T and outputting the result of discrimination. The H(U) error calculating circuit 41a outputs a signal indicating infeasibility of the interpolation or replacement making use of the neighboring sample data on the upper line and transmits the signal to the averager/selector circuit 41c simultaneously with the one-side concealment error and the result of discrimination. The sample data supplied to the H concealment accuracy output circuit 41 are shown in Fig. 5 for simplifying the description. In consideration that a one-sample delay is caused by the latch 245, it is necessary for the actually input sample data to be delayed one sample with respect to the sample data PP0 or NP0 The H(D) error calculating circuit 41b in the H concealment accuracy output circuit 41 computes the one-side concealment error using sample data on the line below line of the reference sample data P0 and the associated error flag and has the construction similar to that of the H(U) error calculating circuit 41a. The variable length interpolation circuit 241 within the H(D) error calculating circuit 41b executes a variable length interpolating operation on the basis of the six sample data NP3, NP2, NP1, NM1, NM2 and NM3 on the line below of the reference data sample P0. Within the H(D) error calculating circuit 41b, there are also provided an interpolation/replacement selector 242, replacement circuit 243, latch 245 and the subtractor/comparator 246, which operate in the same manner as the corresponding circuits in the H(U) error calculating circuit 41a except processing different data from those processed in the latter circuit. The one-side concealment error and the result of discrimination (result of comparison with the threshold T) as well as the above mentioned infeasibility signal from the subtractor/comparator 246 of the H(D) error calculating circuit 41b are transmitted to the averager/selector circuit 41c. The averager/selector circuit 41c takes the average value of the one-side concealment error from the H(U) error calculating circuit 41a and the one-side concealment error from the H(D) error calculating circuit 41b to output the above mentioned H direction concealment error, while outputting an H direction invalid signal HNG for excluding the H direction from ideal direction ranking in dependence upon the result of discrimination and each infeasibility signal. Since the 2-sample interpolation or so-called mean value interpolation is performed in the concealment accuracy output circuits 42 to 44, in place of the variable length interpolation, a summation circuit 244 for calculating the average value is provided in each of the error calculating circuits 42a, 42b, 43a, 43b, 44a and 44b. The V(L) error calculating circuit 42a of the V concealment accuracy output circuit 42 computes one-side concealment error, using the sample data P1 on the left side of the reference sample data P0 and sample data PP1, NP1 above and below the sample data P1. Thus the sample data PP1, NP1 are supplied to the summation circuit 144 in the V(L) error calculating circuit 42a so as to be summed together and the resulting sum is supplied to the interpolation/replacement selector 242 after shifting one bit. The error calculating circuit 42a is otherwise similar in construction and operation to the above mentioned H(U) error calculating circuit 41a or the H(D) error calculating circuit 41b. Thus, replacement data from the replacement circuit 243 (V-direction reference sample, left side sample data PP1 or NP1) are transmitted to the interpolation/replacement selector 242 and one of the interpolation data or the replacement data is selected and output in dependence upon whether the error flags allow or prohibit interpolation of the one-side date. The output data from the selector 242 are supplied via timing latch 245 to the subtractor/comparator 246, where the difference thereof from the left side sample data P1 is taken and output as the one-side concealment error. The subtractor/comparator 246 also outputs the result of comparative discrimination of whether the one-side concealment error exceeds the threshold value T. The V(L) error calculating circuit 42a also outputs the above mentioned infeasibility signal and these signals are supplied to the averager/selector circuit 42c. In the remaining error calculating circuits 42b, 43a, 43b, 44a, 44b, there are provided a summation circuit 244, an interpolation/replacement selector 242, a replacement circuit 243, a latch 245 and a subtractor/comparator 246, which function similarly to the corresponding circuits in the V(L) error calculating circuit 42a except processing different data from those processed in the latter circuits. Similarly to the averager/selector circuit 41c, the averager/selector circuit 42c takes the mean value of the one-side concealment error from the V(L) error calculating circuit 42a and the one-side concealment error from the V(R) error calculating circuit 42b and outputs the above mentioned V-direction concealment error E(V), while outputting the V-direction invalid signal VNG for excluding the V direction from the ideal direction ranking. Similarly, the averager/selector circuit 43c outputs a D₋ direction concealment error E(D₋) and a D₋ direction invalid signal MNG, while the averager/selector circuit 43 outputs a D+ direction concealment error E(D+) and the D+ direction invalid signal PNG. The ranking decision circuit 45 is constituted by six comparators 251 to 256 for comparing the magnitudes of the concealment errors E(H), E(V), E(D₋) and E(D+) in the above four directions. By these comparators 251 to 256, the relative magnitudes E(H) > E(V), E(H) > E(D₋), E(H) > E(D+), E(V) > E(D₋), E(V) > E(V+), E(D₋) > E(D+), are examined to check the relative magnitude of the concealment errors in the above four directions. The comparison outputs E(H)>E(V) to E(D₋)>E(D+) are expressed as HGV, HGM, HGP, VGM, VGP and MGP, respectively, wherein M and P denote the diagonal "minus" (D₋) and the diagonal "plus" (D+), respectively. The outputs HGV to MGP from the ranking decision circuit 45 are output via latch 259 and correspond to the ranking flags output from the output terminal 50 shown in Fig. 7. The invalid signals HNG, VNG, MNG and PNG in the above four directions are taken out via latch 249 at the output terminals 46, 47, 48 and 49, respectively. It is noted that the error concealment need be performed in the ulterior stage in consideration that the output data are delayed each by one sample by these latches 259, 249. In the circuitry of Fig. 9, error flags in the vicinity of the reference sample points, such as FPP1, FPP0, FPM1, FP1, FM1, FNP1, FNP0 or FNM1, are supplied to the input terminal 70, while the ranking flags obtained by the above mentioned ideal direction ranking and feasibility signals for the various directions are supplied to the input terminals 71 and 72. All of these error flags, ranking flags and feasibility signals are supplied to the ideal direction interpolation decision circuit 51 and the ideal direction replacement decision circuit 53 which discriminate the error state in the vicinity of the reference erroneous sample data P0 with the aid of these data to determine the method for error concealment in the ideal concealment direction. The interpolation data at the error-concealed reference sample point from the one-dimensional concealment circuit 111, that is the variable-length interpolation data in the horizontal direction, are transmitted to the input terminal 73, while the sample data PP0, NP0, PP1, NM1, PM1 and NP1 for interpolation in the V, D₋ and D+ directions are transmitted to the input terminals 74 to 79. Eight sample data PP1, PP0, PM1, P1, M1, NP1, NP0 and NM1 in the vicinity of the reference sample for replacement in the H, V, D₋ and D+ directions, are transmitted to the input terminals 80 to 87, respectively. Sample data LP0 of a point of a preceding frame corresponding to the reference sample point is supplied to the input terminal 88, while the reference sample data P0 to be concealed for error is supplied to the input terminal 89. The circuitry of Fig. 9 may be roughly divided into some sections. These are a section performing an interpolation using error-free sample data in the vicinity of the reference sample point, input via terminals 73 to 79, constituted by ideal direction interpolation decision circuit 51, optional interpolating direction (any direction interpolation) decision circuit 54, error concealment method selector 58, interpolation circuits 61 to 63 and selectors 64, 66; a section performing a replacement using error-free sample data in the vicinity of the reference sample point, input via terminals 80 to 87, constituted by ideal direction replacement decision circuit 53, nearest neighbor vicinal replacement decision circuit 56, error concealment method selector 58 and selectors 65, 66; a section performing temporal replacement using error-free sample data of the previous frame, input via terminal 88, constituted by high accuracy temporal replacement decision circuit 52, low accuracy temporal replacement desision circuit 55, error concealment method selector 58 and selector 66, and a section performing a replacement using error-concealed sample data, constituted by recursive replacement decision circuit 57, recursive count generator 59, recursive count memory 60, error concealment method selector 58 and selectors 65, 66. With the main part of the two-dimensional concealment circuit, that one of the concealment strategies or algorithms shown in Table 1 is selected which (is can be calculated) and which is highest in the ranking or sequence of preference, In the above Table 1, the concealment strategies and the instantaneous error rates are tabulated in the order of the decreasing position in the ranking of preference. The error rates indicate the range of applicability of therespective error concealment method, showing that plural error concealment methods may be applied to one and the same error rate. Fig. 9 shows, in the order of the above Table 1, the ideal direction decision interpolation circuit 51, high accuracy temporal replacement decision circuit 52, ideal direction replacement decision circuit 53, anydirection interpolation direction circuit 54, low accuracy temporal replacement decision circuit 55, nearest neighbor replacement decision circuit 56 and the recursive replacement decision circuit 57. The error rates shown in Table 1 are not used in determining the error concealment method, and it is the state of error flags (error patterns) in the vicinity of the reference sample data P0 and the video data contents that determine the particular error concealment method. However, the accurate strategy is mostly used for low error rates. This preference system enables so-called modeless concealment. That is, the best error concealment method is always selected for the current error pattern without dependence upon the current reproduction mode. The instantaneous error rate of Table 1 shows the minimum and maximum values of the error rate that enables each of the concealment strategies. The actual error rate at which each strategy is used depends appreciably on the error flag pattern at each point to be concealed. Selection of the concealment strategy depends on the computation feasibility of a variety of strategies. If an interpolating operation in a given direction is possible, that direction can be interpolated. Similarly, if a replacement sample in a given direction is valid, that direction can be substituted. The above mentioned error concealment methods, namely the concealment strategy and the concealment algorithim, are hereinafter explained. First, the construction and the operation for ideal direction interpolation is explained. The ideal interpolating direction decision circuit 51 of Fig. 9 is supplied with error flags FPP1, FPP0, FPM1, FP1, FM1, FNP1, FNP0 and FNM1, associated with sample data in the vicinity of the reference erroneous sample data P0, ranking flags from the ranking control circuit, such as the above mentioned comparison output signals HGV, HGM, HGP, VGM, VGP and MGP, and with the above mentioned invalid signals HNG, VNG, MNG and PNG, indicating computation feasibility in the various directions. The ideal interpolating direction decision circuit 51 examines the state of these error flags, ranking flags and invalid signals to determine the ideal interpolating direction and transmits, a control signal to the error concealment method selector 58. More specifically, the ideal direction interpolation becomes feasible when, for a given direction, the invalid signal is set (meaning that the computed concealment error is not more than tha threshold T) and the error flags allow the actual interpolation. The direction with the ranking (smollest calculated concealment error) is selected. Thus inappropriate directions, are excluded by the above invalid signals and error flags, and the direction of the highest preference is determined on the basis of the ranking flags. A control signal indicating this direction of the highest preference is supplied to the error concealment method selector 58. From the error concealment method selector 58, the selection control signal for selective of the ideal direction interpolation data is transmitted to the selectors 64, 66. At this time, one of the interpolated sample data for the above mentioned four directions is selected at the selector 64. That is, the weighted mean value in the H direction, or the variable-length interpolated data, already computed at the above mentioned one-dimensional error concealment circuit via terminal 73, is supplied to the selector 64. On the other hand, sample data PP0, NP0 above and below the sample data to be interpolated are supplied via terminals 74, 75 to a V interpolation circuit 61 where the above mentioned interpolated value in the V direction ((PP0+NP0)/2) is formed and transmitted to the selector 64. Sample data PP1, NM1 on a diagonal minus of the sample data P0 to be interpolated are supplied via terminals 76, 77 to a D₋ interpolation circuit 62 where an interpolated value in the D₋ direction ((PP1+NM1)/2) is found and transmitted to the selector 64. Sample data PM1, NP1 on the diagonal plus of the sample data P0 to be interpolated are supplied via terminals 78, 79 to a D+ interpolating circuit 63 where the interpolated value in the D+ direction ((PM1+NP1)/2) is found and transmitted to the selector 64. The above mentioned interpolated values in the various directions are supplied to the selector 64 where the interpolated value of the direction determined by the ideal interpolating direction decision circuit 58, i.e. the minimum concealment error direction, is selected by the control signal from the error concealment method selector 58 and transmitted to the selector 66. If the above mentioned ideal direction interpolation is feasible, the selector 66 selects output data from the selector 64 and transmits the data to the terminal 68. If this ideal direction interpolation is not feasible, the ideal interpolation method is not selected and the high accuracy temporal replacement method with the next high ranking of preference is selected ifitis possible. The ideal direction replacement is explained. The ideal replacement direction decision circuit 53 is supplied with error flags FPP1, FPP0, FPM1, FP1, FM1, FNP1, FNP0 and FNM1, ranking flags from the ranking circuit and calculable feasibility signals for the various directions and discriminates these error flags, ranking flags and the invalid states to determine the ideal replacement direction. More specifically, any of the above mentioned H direction, V direction, D₋ direction or D+ direction, considered to be inappropriate on the basis of the invalid signals and the error flags, are eliminated, and the direction of the highest preference is determined on the basis of the ranking flags for the remaining directions. The control signal indicating this highest preference direction is supplied to the error concealment method selector 58. When the replacement at the ideal replacement direction is selected at the error concealment direction 58, the selectors 65, 66 are controlled so that sample data having the direction determined by the ideal replacement direction decision circuit 53, from the sample data PP1, PP0, PM1, P1, M1, NP1, NP0 and NM1 input via terminals 80 to 87, that is, the minimum concealment error direction, is transmitted via selectors 65, 66 to the terminal 68. The any direction interpolation is now explained. Error flags FPP1, FPP0, FPM1, FP1, FM1, FNP1, FNP0 and FNM1 are supplied to the any direction interpolation decision circuit 54 where the state of these error flags is discriminated. Thus the direction in whitch interpolation is possible (ie, with the error flag "0" on both side) indicating no error is selected and a control signal indicating that interpolation in such direction is feasible is transmitted to the error concealment method selector 58. When plural directions are possible, the ranking of preference is set in the order of H direction, V direction, D+ direction and D₋ direction. When the any direction interpolation is selected at the error concealment method selector 58, the selectors 64, 66 are controlled, so that, from the interpolating values P of the various directions input to the selector 64, that value P which has the direction determined at the any direction interporation decision circuit 54 is selected and transmitted via selector 66 to the terminal 58. The nearest neighbor replacement is now explained. The nearest neighbor replacement decision circuit 56 is supplied with four error flags FP2, FP1, FM1 and FM2 or both sides of the erroenous sample data P0 to be concealed for errorc, three error flags FPP1, FPP0 and FPM1 on the line above the line of the cample data P0 and three error flags FNP1, FNP0 and FNM1 on the line below the line of the sample data P0 to determine the state of these error flags. That is, the nearest neighbor one of the sample data with the error flags "0" indicating no error is used in replacement for the erroneous sample data P0. The control signal used to replace the nearest neighbor vicinal sample data for the erroneous sample data P0 is supplied to the error concealment method selector 58. When plural sample data are usable, the ranking of preference of sampole data is set in the order of P1, M1, P2, M2, PP0, NP0, PP1, PM1, NP1 and NM1. When the nearest neighbor replacement is selected at the error concealment method selector 58, the selectors 65, 66 are controlled so that, from sample data PP1, PP0, PM1, P1, M1, NP1, NP0 and NM1 input via terminals 80 to 87, that sample data determined by the nearest neighbor replacement decision circuit 56 is selected and transmitted via selector 66 to terminal 68. The general construction and operation for high accuracy temporal replacement is now explained. The high accuracy temporal replacement decision circuit 52 is supplied with six sample data P3, P2, P1, M1, M2 and M3 on both sides of the reference erroneous sample data P0, seven sample data LP3, LP2, LP1, LP0, LM1, LM2 and LM3 on the corresponding line of the previous frame, and associated error flags FP3, FP2, FP1, FM1, FM2, FM3, FLP3, FLP2, FLP1, FLP0, FLM1, FLM2 and FLM3 to discriminate the error flags to decide if the temporal replacement, that is, replacement on the time axis, is feasible. When the above error flags are all "0" indicating no error, and the difference between corresponding sample data is not more than a predetermined threshold HT, a control signal for substituting the sample data LP0 of the previous frame for the erroneous sample data P0 is transmitted to the error concealment method selector 58. In other words, when all of the conditions FP3=FP2=FP1=FM1=FM2=FM3=FLP3=FLP2=FLP1 =FLP0=FLM1=FLM2=FLM3=0, | LP3-P3 | ≦ HT, |LM1-M1 | ≦ HT, | LP2-P2 | ≦ HT, | LM2-M2 | ≦ HT, | LP1-P1 | ≦ HT, | LM3-M3 | ≦ HT are satisfied, the erroneous sample data P0 is replaced by sample data LP0. That is, when the six sample data on both sides of the sample data P0 in error are whithin a difference threshold HT of the corresponding date in the previous frame, temporal replacement is performed on the assumption that the erroneous sample data P0 is also not changed temporally. Meanwhile, a small value is used for the threshold HT, and this value can be varied. When high accuracy temporal replacement is selected at the error concealment method selector 58, the selector 66 is controlled so that the sample data LP0 of the previous frame, input via terminal 88, is transmitted to terminal 68. The low accuracy temporal replacement is now explained. The low accuracy temporal replacement decision circuit 55 is supplied with six sample data P3, P2, P1, M1, M2 and M3 on both sides of the erroneous sample data P0, seven sample data LP3, LP2, LP1, LP0, LM1, LM2 and LM3 on the corresponding line of the preceding frame, and associated error flags of these sample data FP3, FP2, FP1, FM1, FM2, FM3, FLP3, FLP2, FLP1, FLP0, FLM1, FLM2 and FLM3. With the accuracy temporal replacement decision circuit 55, if, as a result of discrimination of the error flags, the error flag FLP0 is "0" indicating no error, and at least one of the corresponding three sets of pairs of error flags on each side of the erroneous sample data P0 is "0" indicating no error, with the difference between the two sets of the sample data being not more than a predetermined value, a control signal to enable substituting the sample data LP0 of the previous frame for the erroneous sample data P0 is transmitted to the error concealment method selector 58. That is, when the condition FLP0=0, and (FP3=FLP3=0 or FP2=FLP2=0 or FP1=FLP1=0), and (FM1=FLM1=0 or FM2=FLM2=0 or FM3=FLM3=0), and (| LPn-Pn | ≦ LT, | LMm-Mm | ≦ LT for all error-free n and m) where n, m indicate the numbers 1,2 3 of the error-free sample data pairs, is satisfied, the sample data LP0 is substituted for the erroneous sample data P0. In other words, in the above mentioned high accuracy temporal replacement circuit 52, the six sample data on both sides of the erroneous sample data P0 and the corresponding sample data of the previous frame must all be error-free. The high accuracy temporal replacement is effective for a low error rate, while the low accuracy temporal replacement is effective for a high error rate. The threshold LT is to be of a small value and can be varied. With the error concealment method selector 58, when low accuracy temporal replacement is selected, the selector 66 is controlled, so that the sample data LP0 of the previous frame, input via terminal 88, is transmitted to the terminal 68. Fig. 10 shows a practical hardware construction for implementing the above mentioned high-accuracy temporal replacement. In this figure, an input video signal to be subjected to temporal replacement is supplied to the input terminal 121. This input video signal is delayed by one frame by a one-frame delay circuit 122, and transmitted to a comparison discriminating circuit 124 along with one-frame delay video signal. A multiplexer 123 substitutes, only when the near-by samples of the reference sample shows a high frame correlation, the sample data of the previous frame for the erroneous sample data and outputs the sample data of the previous frame at an output terminal 125. The comparison discriminating circuit 124 is constituted of a shift register circuit comprised of 7-stage registers flip-flops(FF) supplied with the input video signal, another shift register circuit comprised of 7-stage register FF supplied with the frame delay video signal, six comparator circuits CP for comparing corresponding near-by sample data of the current and the previous frames, and an AND gate taking an AND of the outputs from the circuit CP for discriminating if frame correlation is high. The registers FF are operated responsive to data clocks from a clock input terminal 127. The outputs from the registers FF constituting the two 7-stage shift registers in the comparison discriminating circuit 124 correspond to sample data P3, P2, P1, P0, M1, M2, M3; LP3, LP2, LP1, LP0, LM1, LM2, LM3. The comparator circuit CP compares, with respect to three samples each on the left and right sides of the reference sample point, sample data P3 to LP3, P2 to LP2 and so forth, corresponding to each other with one frame in-between. When the comparison error, that is, |P3-LP3|, |P2-LP2| etc. is within the above-mentioned threshold HT, the output of the comparator circuit CP is set to the high level or "1". The "co-valued" relation holds when comparison outputs HTP3, HTP2, HTP1, HTM1, HTM2, HTM3 from the six comparator circuits CP are at the high level. When the three near-by samples each on both sides of the reference sample data P0 are "co-valued" with the corresponding data of the previous frame, that is when the comparison outputs HTP3 to HTM3 are all at the high level, the output of the AND gate 126 goes high. The output of the AND gate 126 going high means that a discrimination has been made that the near-by frame correlation is high. The output from AND gate is supplied to an AND gate 128, the output of which performes a switching control of the multiplexer 123. The function of the multiplexer 123 is to make a switching selection between the reference sample data P0 and the sample data LP0 of the previous frame to transmit the selected sample data to the output terminal 125. In order for such high accuracy temporal replacement to be performed correctly, it is essential that the reference sample data P0 be in error, and that the near-by sample data compared between the frames, sample data P3, P2, P1, M1, M2, M3 and corresponding sample data of the previous frame LP3, LP2, LP1, LP0, LM1, LM2 and LM3 be free of errors. These conditions are discriminated using respective error flags. Referring to Fig. 10, error flags are supplied to an input terminal 131. By using two 7-stage shift registers and a frame delay circuit 132, the error flags FP3 to FM3 and FLP3 to FLM3 shown in Fig. 6 are generated. The error flags of all of the neighboring points in both the circuit frame and the previous frame are input to NOR gate 129. It all of these error flags are "0" (ie, none of the points are erroeous), the output of NOR gate 129 is "1" . This output is input to AND gate 128, together with the error flag of the sample date point, FP0. Thus the output from the AND gate 128 goes high only when the output from the AND gate 126, the output from the NOR gate 129 and the error flag FP0 are at the high level. At this time, the multiplexer 123 is so controlled as to select the sample data LP0 by switching selection to transmit the sample data to the output terminal 125. By using the temporal replacement, shown in Fig. 10, when the sample data in the vicinity of the sample data are error-free and exhibit high interframe correlation, that is, when the image is stationary with only small movement or variation, temporal concealment is performed with the use of the error-free sample data of the preceding frame so that optimum temporal error concealment with extremely small concealment error may be realized in response to the contents of the video image. The circuitry of Fig. 10 is somewhat complex because the register flip flops in the comparator discriminating circuit 124 are adapted for affording a one-sample delay to video data, such as 8-bit-per-sample data, while six comparator circuits CP are necessitated. In the circuitry shown in Fig. 11, video sample data are first compared, and the results of comparison are discriminated after having been delayed by one sample, for realizing an operation which is equivalent to that of Fig. 10. Fig. 11 also shows the hardware for performing the above mentioned low accuracy temporal replacement. Referring to Fig. 11, video sample data of the current frame are supplied to an input terminal 141, while video sample data of the previous frame, that is, video sample data delayed by one frame, are supplied to an input terminal 142. The current frame data is subtracted at a subtractor 143 from the previous frame data and an absolute value is taken at an absolute value circuit 144 to produce the above mentioned comparison errors |LP3-P3|, |LP2-P2| etc. These comparison error outputs are transmitted to a comparator 145 for comparison with a threshold HT for high accuracy temporal replacement and a comparison output which goes high when the comparison error output is not more than the threshold HT is transmitted to a 7-stage shift register 146. The outputs from the six registers excluding the central reference position shift register of the registers of the 7-stage shift register circuit 146 correspond to HTP3, HTP2, HTP1, HTM1, HTM2 and HTM3. These outputs HTP3 to HTM3 are trasmitted to an AND gate 151 of a high accuracy temporal replacement decision logic circuit 150. To the high accuracy temporal replacement decision logic circuit 150, error flags FP3, FP2, FP1, FM1, FM2 and FM3, associated with six nearby samples of the reference sample point of the current frame, and error flags FLP3, FLP2, FLP1, FLM1, FLM2 and FLM3 of the corresponding sample points of the preceding frame, are supplied, and transmitted to a NOR gate 152. The error flag FLP0 of a corresponding sample point of the preceding frame of the reference sample point is transmitted via inverter 153 to an AND gate 154, to which the output of the AND gate 151 and the output of the NOR gate 152 are also supplied. A high accuracy temporal replacement enable signal HTEN, indicating that the high precision temporal replacement is enable, is transmitted to the AND gate 154. Thus the AND gates 154 outputs a high accuracy temporal replacement decision signal HTOK, which goes high when the conditions for high accuracy temporal replacement are satisfied and high accuracy temporal replacement is feasible. The signal is output to error concealment method selector 58 in Fig. 9. Responsive to this decision signal HTOK, sample data LP0 of the preceding frame is substituted for the reference sample data P0 by way of high accuracy temporal replacement. For performing low accuracy temporal replacement in Fig. 11, an absolute value output if the comparison error from the absolute value circuit 144 is supplied to a comparator circuit 147 where it is compared to a threshold for low accuracy temporal replacement LT. A comparison output which goes high when the absolute value output is not more than the threshold LT is transmitted to a 7-stage shift register 148. The outputs LTP3, LTP2, LTP1, LTP0, LTM1, LTM2 and LTM3 from these shift registers 148 represent logical values indicating the result of comparison, such that, with the output of the register of the central register as the reference, the output LTP3 represents the result of comparison |LTP3-P3|<LT. Of these outputs, the six outputs LTP3 to LTP1 and LTM1 to LTM3, with the exclusion of the result of comparison for the reference position, are transmitted to a low accuracy temporal replacement decision logical circuit 160. This low accuracy temporal replacement decision logic circuit 160 is organized as shown for example in Fig. 12. It is this logic circuit 160 which decides if the above mentioned conditions for low accuracy temporal replacement are satisfied. Thus the error flags FP3, FP2, FP1, FM1, FM2 and FM3 of the near-by six sample points and the error flags FLP3, FLP2, FLP1, FLM1, FLM2 and FLM3 of the corresponding sample points of the preceding frame are supplied respectively to six NOR gates of the NOR gate set 161, such that the output of the NOR gate for which both input samples are free of errors goes high. The six outputs from the NOR gate set 161 are transmitted to six NAND gates of a NAND gate set 162 and six AND gates of an AND gate set 163. The above six outputs of comparison results LTP3 to LTP1 and LTM1 to LTM3 are transmitted to six AND gates constituting the AND gate set 163. Thus the outputs of the AND gates of the AND gate set 163 are at "H" when the input sample pair is error free and not higher than the above threshold LT. The three outputs on each side of the AND gate set 163 are sent to two OR gates of the OR gate set. The output of each of the OR gates goes high when one of the three one-side inputs is at "H" level. The outputs of the OR gates of the OR gate set are sent to an AND gate 165, the output of which goes high when at least one sample pair on each side of the reference sample is error-free and not higher than the threshold LT. The output of the AND gate 165 is transmitted to an AND gate 166. The six NAND gates of the NAND gate set 162 are supplied with the above mentioned six comparison result outputs LTP3 to LTP1 and LTM1 to LTM3 which are supplied after inversion by six inverters of an inverter set 167. Thus the output of each of the NAND gates of the NAND gate set 162 goes high when the input sample pair is free of errors and the result of comparison is not unfavorable. The outputs of the NAND gates of the NAND gate set 162 are sent to a NOR gate 168, the output of which is sent to an AND gate 166. The output of NOR gate 168 is "1" if the difference between no corresponding error-free points is above threshold LT. The error flag FLP0 of the sample data LP0 to be substituted, after inversion at an inverter 169, and a low accuracy temporal enable signal LTEN, indicating that of the low accuracy temporal replacement is enabled, are also supplied to the AND gate 166. Thus the AND gate 166 outputs a low accuracy temporal replacement decision signal LTOK which goes high when the conditions for low accuracy temporal replacement are satisfied and low accuracy temporal replacement is feasible. This signal is output to concealment method selector 58 in Fig. 9. Responsive to this decision signal LTOK, the sample data LP0 of the preceding frame is substituted for the reference sample data P0 to perform the low accuracy temporal replacement. Recursive replacement in now explained by referring to Figs. 9 and 13 to 17. A recursive replacement decision circuit 57 shown in Fig. 9 is supplied with error flags, above all, an error flag FP0 of the point to be concealed, and recursive count from a recursive count memory 60. Recursive replacement means recurrent repetition of replacement of previously concealed sample data for the erroneous sample data P0. This is performed in cases wherein the error rate of supplied sample data is so high that the above mentioned usual interpolation or replacement cannot be performed. For example, sample data obtained after replacement using error-concealed sample data are the first generation sample data, and the sample data obtained by second replacement using these first generation sample data are the second generation sample data. The state of these generations is represented by the recursion counts. Assuming that, as shown in Fig. 13, sample data P5 is error free, as indicated by a mark ○, and that sample data P4, P3, P2, P1 and P0 are all in error, as indicated by a mark ×. The sample data P4 is replaced by sample data P5 and the sample data P3 is replaced by sample data P4 (recursive replacement of P5) to prove to be first generation sample data. The sample data P2 is replaced by sample data P3 to turn out to be the second generation data of recursive replacement. The sample data P1 is replaced by sample data P2 to turn out to be the third generation data. The sample data P0 is replaced by the sample data P1 to turn out to be the fourth generation data of recursive replacement. Fig. 14 shows a specific example in which the above mentioned recursive replacement is performed up to the eighth generation. As specific values of the recursive count, an initial value is set for each sample date depending on the error concealment method, that is, a concealment strategy or algorithm, that was used and this initial value is added to by 2 each time the above mentioned recursive replacement is performed. Default temporal replacement means substituting a sample data LP0 of the previous frame for the erroneous sample data P0 in cases wherein none of the above mentioned error concealment methods can be utilized. This replacement is performed on erroneous samples when the error rate is so high that the above mentioned recursive replacement cannot be executed. If this default temporal replacement is performed repeatedly, the image is seen to be stationary. With the present embodiment, the upper values of the recursive counts are varied to change the upper limit on the generations of recursive repetitive replacement. Supposing that the erroneous samples that cannot be concealed by the recursive replacement are to be concealed by the default temporal replacement, changing the upper limit of the generation in the above described manner is tantamount to changing the ratio between concealment by default temporal concealment and concealment by recursive replacement of erroneous sample points in an image that cannot be concealed by the usual concealment methods. More specifically, the upper limit of the recursive counts may be changed responsive to the image types or contents. For example, in case of an image having high temporal correlation, that is, high frame-to-frame or field-to-field correlation, such as a still image, the upper value of the number of times of repetition of the recursive replacement is reduced to reduce the concealment area by recursive replacement 171 while widening the concealment area by default temporal replacement 172, that is, the area for which the temporally preceding image is displayed (Fig. 15). conversely, with an image showing a lower temporal correlation, such as in case of an animation or during shuttle playback mode, the above upper value is increased to increase the concealment area by recursive replacement 171 while narrowing the concealment area by default temporal replacement 172 (Fig. 16). In Figs. 15 and 16, since the same sample data are used in the area 171 concealed by recursive replacement, the area 171 is displayed by a sole color and sole intenisty, as if it were composed of a sole pixel. On the other hand, in the area 172 concealed by the default temporal replacement, temporally preceding error-free sample data which are closest to sample positions are used. When the errors are consecutive, old sample data are used directly, so that the image is seen to remain stationary. Hence, with an image with small movements, the area 172 in which the preceding image data may be directly used is widened, as shown in Fig. 15, to improve the resolution, while, with an image with vigorous movements, real time data are increased at the costs of the resolution, as shown in Fig. 16, to eliminate the adverse effects otherwise caused by the residual preceding image. Discrimination of the image types or contents, above all, the magnitude of movements, may be made with, for example, the VTR playback mode. This is in consideration that the image with lesser movements is likely to be produced during the still or slow playback mode of the VTR while an image with vigorous movements is likely to be produced with high tape running speeds, such as in the case of a so-called shuttle mode. That is, during the shuttle, cue or review playback mode, the upper limit of the number of times of repetition of recursive replacement is increased to widen the area of recursive replacement, while, during still or slow playback mode, the upper limit is reduced to narrow the area of recursive replacement. As specific values of the upper limit, the state in which the maximum number of the recursive count is set to 7 and the generations of recursive replacement is limited to 4 and the state in which the maximum number of the recursive count is set to 15 and the generations of recursive replacement is limited to 8, may be set alternately. The upper limit of the number of times of repetition of recursive replacement may also be changed as a function of the error rate. Also, in a shuttle playback mode, for example, the area of recursive replacement, that is the upper limit of the number of times of recursive replacement, may be increased for high speed operation with a high error rate. Meanwhile, the recursive counts are stored in a recursion count memory 60 shown in Fig. 9 and are set in association with all of the sample data. In a recursive replacement decision circuit 57, the recursive counts of the positions of sample data P1 preceding the sample data to be concealed and sample data PP1, PP0 and PM1 on the line above the line of the sample data to be concealed, are compared to the maximum value of the recursive count input via terminal 67, such as 7, and the position of the smallest recursive count less than 7 is selected. A control signal employed for recursive replacement is supplied to an error concealment method selector 58. The recursive count of the selected position is sent from the recursive replacement decision circuit 57 to a recursive count generator 59. A signal indicating the error concealment method has been selected at the selector 58 is supplied to the recursive count generator 59. When the recursive replacement method is selected, the recursive count of the selected position is added to by 2 and the thus incremented recursive count is newly stored in the recursive count memory 60 as the recursive count of the substituted position. When other concealment methods are selected, the recursion count is set as shown in Table 2. When the recursive counts of the positions of the sample data P1, PP1, PP0 and PM1 are of the same value, the ranking of preference is set in the order of sample data P1, PP0, PP1 and PM1. Fig. 17 shows a specific circuit construction of the recursive replacement decision circuit 57. In this figure, H direction recursive counts, V direction recursive counts, D₋ direction recursive counts and D+ direction recursive counts of sample data P1, PP0, PP1, PM1 in the vicinity of sample data P0 to be concealed for errors, are supplied to comparators 190 to 193 via terminals 180 to 183, respectively. These recursive counts are compared in the comparators 190 to 193 with the upper value of the recursive count, such as 7 supplied via terminal 67. When at least one of the recursive counts is lesser than 7, a signal indicating recursive replacement feasibility is taken out via NAND gate 194 at a terminal 185. The upper limit of the recursive count is supplied from a recursive count upper limit switching circuit 174, which may be switchingly controlled by a switching control signal supplied via terminal 175. As the switching control signal from terminal 175, a signal indicating if the playback mode of the VTR is the shuttle mode, for example, may be employed. The switching circuit 174 outputs 15, for example, in case of the shuttle mode and 7 otherwise, to the terminal 67, as the upper limit of the recursive count. The recursive counts in the various directions are supplied to a replacement direction selection circuit 195 where the position of the smallest recursive count is selected and a signal indicating such position is taken out at a terminal 186. The signals indicating recursive replacement feasibility and the position are supplied as the recursive replacement control signal to the error concealment method selector 58 shown in Fig. 9. When the recursive replacement is selected at the error concealment method selector 58, the selectors 65, 66 are controlled so that the sample data determined by the recursive replacement control decision circuit 57 from sample data PP1, PP0, MP1 and P1 input via terminals 80 to 83 are selected and output via selector 66 at the terminal 68. As described above, the error concealment method selector 58 selects one of a variety of interpolating or substituting processes which is feasible and has a higher ranking of preference. If none of the above mentioned error correcting methods can be applied, the selector 66 is controlled to perform the default replacement so that the sample data LP0 of the previous frame supplied via terminal 88 is selected. Thus the sample data concealed by the concealment method selected by the error concealment method selector 58 or the original sample data P0 are output via selector 66 at the terminal 68. The sample points may be displayed by different colors in dependence upon the ideal directions at the respective sample points ranked at the time of the ideal direction ranking. Thus, color signals indicating the ideal directions, such as red for the sample point with the H selected direction, blue for the sample points with the V selected direction, green for the sample points with the D₋ direction or yellow for the sample points with the D+ selected direction, may be output and displayed for monitoring on a CRT, as a function of the ranking flags from the ranking decision circuit 45 already explained with reference to Fig. 7. Different color display may also be used as a function of the selection of the concealment methods shown in Table 1. The gray flag is hereinafter explained. Concealed video sample data are supplied from a terminal 68 of Fig. 9 to a gray flag processing circuit 118 of Fig. 18, to which are also supplied the gray flag explained in connection with Fig. 1 via terminal 91 and the reference sample data P0 from the terminal 89 via terminal 69. The gray flag processing circuit 118 selects and outputs one of the original sample data or the error-concealed sample data on the basis of error-concealed sample data from various interpolation and replacement operations, and is constituted by a selector 92, a comparator 93 and an AND gate 94. With seening correct sample data on which the gray flag is set, the following operation is performed. The error-concealed sample data and the original sample data before error concealment are compared to each other. When the difference is lesser than a predetermined threshold value Vth, the original sample data is output as the correct data and, when the difference is larger than the above threshold Vth, the error concealed sample data is output. More specifically, referring to Fig.18, the above gray flag is supplied via terminal 91 to an AND gate 94, to the other input of which an output of the comparator 93 is supplied. The value Vs of the original sample P0 input from terminal 89 via terminal 69 is compared to the value Ve of the error-concealed output sample data from the terminal 68 at the comparator 93. When the result of the comparison is lesser than the above predetermined threshold Vth, that is, when it is determined that the condition |Vs-Ve|<Vth is satisfied, a signal "1" is transmitted from the comparator 93 to the AND gate 94. Therefore, when the gray flag supplied to the AND gate 94 via terminal 91 is in the set state, or "1", the output of the AND gate 94 is "1", so that the original sample data P0 is selected at the selector 92. When it is determined at the comparator 93 that the above condition is not satisfied, the error-concealed sample data is selected at the selector 92 and output at a terminal 95. When the gray flag is in the reset state, or "0", the AND gate 94 is turned off to interrupt the output from comparator 93 so that the selector 92 selects the error-concealed output from the terminal 68 to issue the error-concealed output at the terminal 95. In this manner, the sample data whose gray flags are set, that is, seeningly correct sample data, are treated for the time being as error-free sample data, and compared with error-concealed data obtained by interpolation by near-by sample data. When the result of comparison is markedly different from the error-concealed data, the error-concealed sample data are used. However, when the result of comparison is within the above mentioned threshold Vth, the seeningly correct sample data are deemed to be correct sample data. This avoids the situation in which all the sample data of the inner code block are deemed to be in error in outer erasure correction and prevents an unnecessary error concealment operation from being performed for all of these sample data while avoiding the situation in which the error sample data mistakely deemed to be free of error are output directly. By eliminating the unnecessary error concealment in this manner, the error rate may be improved by 3.4 x 10⁻² (=2/(60-2)). In sum, when the number of the erroneous sample data which have not been corrected at the time of the error correction at the first code series of the product code exceeds the error correction capability of the second code series, gray flags are set for the erroneous sample data in the series deemed to be error-free at the time of the second code series. For error concealment, with the sample data with the gray flag set, the original sample data are compared to the error-concealed data, and the original sample data are used as the correct sample data when the difference is less than a predetermined value, thereby improving the error rate and preventing the erroneous data from being output as the correct data through error detection mistakes. The concealed video sample data output at terminal 95 is transmitted to the weighted mean calculating circuit 120. The arithmetic mean calculating circuit 120 function to generate line signals for a second field on the basis of plural line signals of a first field to suppress flickers or objectionable vertical image movements and includes a weighted mean calculating circuit for summing the line signals of the first field after multiplication by variable coefficients. The circuit 120 senses that the line signals processed by the weighted mean calculating circuit are outside the effective video signal area to change the coefficients of the weighted mean calculating operation to improve image properties in the vicinity of the upper and lower edges of the picture and to suppress image flickers or vertical movements. In other words, when the line signals are outside the effective video signal area, gain characteristics of the line signals of the two fields can be made analogous to each other even at the upper and lower picture edges. In addition, delay characteristics of the line signals can be improved to suppress image flickers and vertical movements for the whole picture. An example of the weighted mean calculating circuit 120 is explained by referring to Figs. 19 to 25. In Fig. 19, the weighted mean calculating circuit 210 represents the main portion of the weighted mean calculating circuit 120. Four sample data, distributed on four lines in the vertical direction of the picture, are supplied to the weighted mean calculating circuit 120. These sample data are produced in general by delaying the video signals input via input terminal 201 by means of three series connected 1H delay circuit 211, 212, 213. However, in the embodiment described in connection with Fig. 1, line delay circuits used for two-dimensional error concealment are used in conjunction with the weighted mean operation to reduce the number of line delay circuits. The weighted mean signal thus obtained at the weighted mean calculating circuit 210 is output at an output terminal 205 as an arithmetic mean output video signal. The weighted mean calculating circuit 210 is constituted by variable coefficient multiplication circuits 214, 215, 216, 217 and a summation circuit 218. Two sets of coefficients A(A1, A2, A3, A4) and B(B1, B2, B3, B4) are associated with the variable coefficient multiplication circuits 214 to 217, and are adapted to be switched selectively as a function of the correlation between input and output fields. More specifically, such selective switching is performed by inputting odd and even field data for each of the input and output fields to an A/B control circuit 219 via input terminals 203, 204. Thus the A/B control circuit 218 discriminates the correlation between the input and output fields on the basis of the above two data lines to control the variable multiplication circuits 214 to 217 by an A/B control signal which is the result of the discrimination. A field position signal indicating the currently input video line signal in the field is input to the terminal 202 and thence to a control circuit 220, the output signal of which is transmitted to the variable coefficient multiplication circuits 214 to 217. The field formed by the weighted mean calculating operation with the coefficient set A is termed F A , whereas the field formed by the weighted mean calculating operation with the coefficient set B is termed F B . The coefficient sets A, B need be set so that the gain G A of the line signal of the field F A and the gain G B of the field F B are equal to each other to the extent that the flicker on the picture surface raises no problem. It is also necessary that the difference between the delay D A of the line signal of the field F A and the delay D B of the line signal of the field F B are as close to 1/2 line as possible. By referring to Fig. 20, the operation of the weighted mean calculating circuit 210 is explained. Fig. 20 shows the relative position of the line signals of the input video signals on the picture surface, wherein the longitudinal direction indicates the vertical direction on the picture surface and the line signals with line numbers n=1 to L indicate that the line signals are within the effective video signal area. The following explanation is given for the case of performing a weighted mean operation using plural line signals, such as four line signals, of the original field of the input video signals. It is assumed that the coefficient sets A, B consists of each four sets of coefficients A1m, A2m, A3m, A4m; B1m, B2m, B3m, B4m, m being 1, 2, 3 or 4. With the value of the line signal at a predetermined position t(position from the left end of horizontal scanning) on the n'th line of the original field set to v(n, t), the value of the line signal at a predetermined position on the n'th line of the field F A set to x(n, t) and with the value of the line signal at the predetermined position on the n'th line of the field F B set to y(n, t), the values x(n, t), y(n, t) of the line signal are given by x(n, t)=A1m·v(n+1, t)+A2m·v(n, t) +A3m·v(n-1, t)+A4m·v(n-2, t) y(n, t)=B1m·v(n+1, t)+B2m·v(n, t) +B3m·v(n-1, t)+B4m·v(n-2, t) where when n≦2, m=n, when 3≦n≦L-1, m=3 and when n=L, m=4. Thus the coefficient sets A, B are changed in dependence upon the line position of the line signal of the original field subjected to weighted mean calculating operation. This operation is controlled by the control circuit 220 discriminating the field position signal input via input terminal 202 in Fig. 19. Meanwhile, if the variable coefficient multiplication units are designed as the usual multiplication units, circuit construction becomes complex and the operational speed is lowered. If the circuit is organized by using ROMs, that is if all weighted line signal values or data are provided in advance and read out to produce the results comparable to those of the multiplication, the processing speed is increased, however, since the coefficients are variable, output data for the coefficient need be recorded with resulting increase in memory capacity and circuit scale. For providing a simplified circuit capable of providing a high speed operation, it is preferred to combine data bit shift and summation by adjusting the values of the coefficients appropriately. A circuit organization for implementing the above variable coefficient multiplication unit by the combination of the bit shifting and summation is explained by referring to Fig. 21. The principle of the circuit it that the values of the input line signal are shifted towards the lower order bits, so that the line signal data is multiplied by 1/2 for each shift bit, and that the thus shifted bits are summed to produce weighted line signals. Fig. 21 illustrates the principle of the variable coefficient multiplication circuits 214, 215, 216, 217 of Fig. 19. For example, with the variable coefficient multiplication circuit 214, the input line signal is input to an input terminal 231 corresponding to the input terminal 201 shown in Fig. 19. The field position signal is input to an input terminal 232 corresponding to the input terminal 202 of Fig. 1. The input terminal 233 is connected to an output of the A/B control circuit in Fig. 19 and is fed with the A/B control signal. The output terminal 238 is connected to the summation circuit 18 of Fig. 19. In Fig. 21, there is shown a case in which, for simplifying the explanation, two coefficients are used for each of the coefficient sets A, B. For these coefficients, the values shown in Table 3 are used. The numerals, such as 8, entered near the signal lines in Fig. 21, indicate the number of bits of the data. D₇ to D₀ stand for the values of 8 bits of the 8-bit data. The value v(n, t) of the line signal input via input terminal 231 is the 8-bit data (D₇ to D₀), the upper 5-bit data (D₇ to D₃) of which are sent to summation circuit 234 as its lower 5-bit data. This is equivalent to shifting the 8-bit input data at the input terminal 231 by 3 bits towards the lower bits to render only the upper 5 bits (D₇ to D₃) valid (multiplication by 2⁻³), these bits proving to be the lower 5 bits of the input data of the summation circuit 234. The upper four bits (D₇ to D₄) and upper three bits (D₇ to D₅) of the input 8 bits are also sent to multiplexer 235 as its lower 4 bit data and lower 3 bit data, respectively. This is equivalent in shifting by four bits (multiplication by 2⁻⁴) and five bits (multiplication by 2⁻⁵) towards the lower bit side, respectively. On the other hand, the field position signal and the A/B control signal are input to a coefficient control circuit 237 via input terminal 232, 233, respectively. In the coefficient control circuit 237, the multiplexers 235, 236 are controlled. More specifically, when an arithmetic operation is performed using the value of the coefficient A at the position X of the line signal in the field, data shifted by 5 bits (or multiplied by 2⁻⁵) are selected at the multiplexer 235 and summed at the summation circuit 234 to the data shifted by three bits (or multiplied by 2⁻³), so that a multiplication by (2⁻³+2⁻⁵), is made, and the summed data is selected at the multiplexer 236. Similarly, when an arithmetic operation is performed using the value of the coefficient B at the position X of the line position in the field, data shifted by 4 bits (or multiplied by 2⁻⁴) are selected at the multiplexer 235 and summed at the summation circuit 234 to data shifted 3 bits (or multiplied by 2⁻³), so that multiplication by (2⁻³+2⁻⁴) is made and the thus sumed signal is selected at the multiplexer 236. In the case of performing an arithmetic operation employing the coefficent A at the position A at the positive Y of the line aignal in the field, the value of 0, which is the other data, is selected at the multiplexer 236. In the case of performing an arithmetic operation employing the value of the coefficient B at the position of the line signal in the field, data shifted by 5 bits or multiplied by 2⁻⁵ are selected at the multiplexer 235 and summed at the summation circuit 234 to data shifted by 3 bits or multiplied by 2⁻³, so that, in effect, multiplication by (2⁻³+2⁻⁵) is made, and the summed data are selected at the multiplexer 236. As described above, the input line signal data are shifted in the direction of the lower order bits and the shifted data are summed to provide weighted line signals to reduce the circuit scale as compared with the conventional circuit for arithmetic operation. The values shown in Tables 4 and 5 show the values designed so that the circuit may be organized by the combination of the above bit shifting and summation. Next, physical gain and delay characteristics of formed line signals, with use of the values of the coefficient sets shown in Table 4 and 5, are explained. First, the case is explained in which the position of the line signal of the formed fields F A and F B is the third to the (L-1)th line (3≦n≦L-1). Fig 22 shows gain and delay characteristics when the values of the coefficient sets A1m, B1m are set to values for m=3 in Table 4. In this case, as shown in Fig.22, the gain G A is close to the gain G B so that flickers are suppressed sufficiently. The relative delay between the delay D A and the delay D B is about 1/2 line so that vertical image movement is also suppressed sufficiently. The vicinity of the upper and lower ends of the field F A and F B subjected to the above mentioned weighted mean calculating operation is now considered. When the values of the above described coefficient sets (those for m=3 in Tables 4 and 5) are used for the values of the weighting coefficient sets A1m, B1m, that is, when the values of the coefficient sets are fixed, as in the conventional practice, the values of the line signals at the position t on the second lines of the field F A and F B are expressed by x(2, t)=A1₃·v(3, t)+A2₃·v(2, t) +A3₃·v(1, t)+A4₃·v(0, t) y(2, t)=B1₃·v(3, t)+B2₃·v(2, t) +B3₃·v(1, t)+B4₃·v(0, t) Fig. 23 shows gain and delay characteristics for this case. As shown in this figure, the gains G A and G B differ considerably so that flickers are produced. This is the consequence of using the line signal value v(0, t) which is outside the effective video signal range. Although it may be contemplated to set the coefficients A4₃, B4₃ of the signals outside the effective video signal area simply to zero, without using the line signal value v(0, t) outside the effective video signal area, no satisfactory result is obtained with this method. Therefore, the value of the coefficients A1m, B1m are changed (in the case of using those for m=2 in Table 4 and 5) and the line signal values at the position t on the second lines of the field F A and F B are expressed by x(2, t)=A1₂·v(3, t)+A2₂·v(2, t) +A3₂·v(1, t)+A4₂·v(0, t) y(2, t)=B1₂·v(3, t)+B2₂·v(2, t) +B3₂·v(1, t)+B4₂·v(0, t) Fig. 24 shows gain and delay characteristics for this case. It is seen from comparison of Figs. 23 and 24 that the gains G A and G B are closer to each other. An explanation for this case is made by referring to Fig. 20 wherein the mark  indicates the line signals used for weight mean calculating operation and the mark ○ indicates the line signal not used for weight mean calculating operation. As shown in a portion surrounded by a broken line in Fig. 20, three line signal values v(1, t), v(2, t) and v(3, t) at the positon t on the first to third lines included in the effective video signal area are used, whereas the line signal value v(0, t) at the position t on the O'th line is not used. In other words, the coefficients A4₃, B4₃ of the O'th line signal (line signals outside the effective video signal range) are set to zero and the remaining coefficients are set so that the above condition is satisfied only by the above coefficients. Similarly, the values of the coefficient sets corresponding to m=1 in Tables 4 and 5 are used for producing the first line signal of the formed field, while the values of the coefficient sets corresponding to m=4 in Tables 4 and 5 are used for producing the last or the L'th line signal. In this manner by changing the values of the weighting coefficients in association with the line signal position in the field, bringing gain characteristics of the line signals of the two fields formed in each of the coefficient sets close to each other and by setting the values of the coefficient sets so that the relative delay of the line signal of the two fields is about 1/2 line, it becomes possible to suppress the flicker and vertical movement of the image in the vicinity of the picture to produce a satisfactory picture in its entirety. The case of realizing a variable coefficient multiplation circuit 214 using the above mentioned read-only-memory is explained with reference to Fig. 25. In this figure, the input terminal 221 corresponds to the input terminal 201 in Fig. 19 and is supplied with an input line signal. The input terminal 222 corresponds to the input terminal 202 in Fig. 19 and is supplied with a field position signal. The input terminal 222 is connected to the output of the A/B control circuit 219 in Fig. 19, and is fed with the A/B control signal. On the other hand, the output terminal 224 of the ROM 220 is connected to the summation circuit 218 of Fig. 1. Previously weighted line signal vaues are recorded in the ROM 220. Weighted line signals are produced by using the above mentioned three kinds of signals as the address signals and reading the data recorded in the ROM 220. Hence, with the above described embodiment of the present invention, by using two field line signals obtained by weighted mean calculating operation as the odd and even field line signals for a monitor receiver, it becomes possible to suppress flickers and vertical movement otherwise generated in the vicinity of upper and lower edges of the picture, and to suppress flickers and vertical movement of the picture in its entirety.

Claims: A video signal processing circuit for processing video signal sample data which is input thereto, comprising error correcting means (103) for performing error correction on said input video signal sample data and outputting both error-corrected sample data and error flags indicating the error states of the various error-corrected data, and error concealment means (105) supplied with said error-corrected data for performing error concealment on particular error-corrected data which are indicated by said error flags as still being in error, characterised in that said error concealment means (105) uses, for said performing of error concealment, error-corrected data which, relative to the said particular error-corrected data, are peripheral and/or temporally adjacent, said error concealment means having a plurality of different error concealment algorithms according to one of which said error concealment is performed on said particular error-corrected data, wherein the particular error concealment algorithm for the particular error-corrected data is selected on the basis of the error flags of the error-corrected data which, relative to the said particular error-corrected data, are peripheral and/or temporally adjacent. A video signal processing circuit according to claim 1, wherein said error concealment means includes weighted mean computing means, for computing a weighted mean of a plurality of error-corrected data to replace the said particular error-corrected data and control means for controlling the number of data used to compute the weighted mean on the basis of the error flags of said plurality of error-corrected data. A video signal processing circuit according to claim 1 or 2, wherein said error concealment means includes one-dimensional error concealment means (111) for performing one-dimensional error concealment using those error corrected data which are on the same line as that of the said particular error-corrected data, and two-dimensional error concealment means (112) supplied with data output from said one-dimensional error concealment means (111) along with said error flags, for performing error concealment on said error-corrected data indicated by said error flags as still being in error, using peripheral and/or temporally adjacent error-corrected data. A video signal processing circuit according to claim 3, wherein said two-dimensional error concealment means (112) comprises selection means (51-60) for selecting a concealment algorithm, and means for generating error-concealed data according to the concealment algorithm selected by said selection means. A video signal processing circuit according to claim 4, wherein said means for generating error-concealed data comprises a plurality of interpolating means (111, 61-63) for interpolating the error-concealed value of the said particular error-corrected data in a plurality of different directions using error-concealed data which are in the vicinity of the said particular error-corrected data, and switching means (64, 66) for switchably controlling the outputs of said plurality of interpolating means (111, 61-63) as a function of control signals from said selection means (51-60). The video signal processing circuit according to claim 5, wherein said selection means (51-60) selects a concealment algorithm on the basis of the output of means (117) which determine, in said different directions, linear combinations of error corrected data which are aligned in said different directions in the vicinity of said particular error corrected data, as an indication of the rate of change of data values in each of the different directions, and which rank the directions as to the concealment accuracy obtainable by interpolation by said plurality of interpolating means (111, 61-63) in said plurality of different directions, on the basis that the preferable direction is the direction in which the rate of change is slowest. The video signal processing circuit according to any one of the preceding claims, wherein said error concealment means includes error pattern detection means for detecting the pattern of error flags of at least said peripheral and/or temporally adjacent data, interpolating means (111, 61-63) for interpolating the said particular error-corrected data using said peripheral data, replacement means for replacing said particular error-corrected data using said temporally adjacent data, and selection means (51-60) for selecting as the means by which error concealment is performed one of said interpolating means and said replacement means on the basis of said detected pattern of error flags from said error pattern detection means. A video signal processing circuit according to claim 7, wherein said error concealment means includes delay means for delaying input error-corrected data by one field or frame period, said error pattern detection means includes means for reading and comparing corresponding pairs of said input error-corrected data and data output from said delay means in the vicinity of the said particular error-corrected data for determining the correlation between said corresponding pairs of data, and said selection means (51-60) controls whether or not the output from said delay means is to be taken out as error-concealed sample data on the basis of the output from said error pattern detection means indicating the pattern of error flags and said correlation between said corresponding pairs of data. A video processing circuit according to any one of the preceding claims, wherein said error concealment means further comprises counting means for counting the number of successive times error concealment is performed using data on which error concealment has already been performed, wherein said error concealment means process said error-corrected data differently when the count value from said counting means exceeds a predetermined variable upper limit. A video signal processing circuit according to any one of the preceding claims, wherein said error correcting means (103) perform error correction on sample data of input video signals using a product code associated with the sample data of input video signals and having at least a first and a second series of error correction code, said error correcting means (103) setting a gray flag for data determined to be error-free by said second series of the error-corrected code but determined to be in error by said first series of correction code, and wherein said error concealment means determine the difference between the value of the original sample data and the value of the error-concealed data, for those sample data for which the gray flag is set, said input data being used as the output error-corrected data when said difference is below a predetermined threshold.

Inventors: KUTNER MICHAEL A C O SONY CORP, TATSUZAWA KAICHI C O SONY CORP, KUTNER, MICHAEL A., C/O SONY CORPORATION, TATSUZAWA, KAICHI, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H04N5
IPC codes: H04N5, G11B20