Offset and slew-rate equalization and control for a pair of voltage-to-current transducers using the same reference voltage

Abstract: An offset and slew-rate equalization and control circuit for a pair of voltage-to-current transducers using the same reference voltage, V ref employs an unique operational amplifier core formed by a single input differential stage and a single intermediate gain stage and uses a pair of unitary gain output buffers for driving respectively the two feedback transistors (M₁, M₂) of the two transducers. The voltage signals detected across two sensing resistances (R₁, R₂) are alternately fed to the inverting input of the input differential stage by means of a first pair of analog switches driven by a pair of phase-opposed enabling signals (,  ). A second pair of analog switches driven by the same pair of signals functionally commutes the output of the intermediate gain stage on the input of one or the other of said unitary gain output stages. By means of a single trimming intervention for correcting the offset of the unique operational amplifier, the same precision and also a substantial identity of the slew-rate may be easily ensured for both transducers.

Description: 1. Field of the invention The present invention relates to a circuit for equalizing the offset and the slew-rate of a pair of voltage-to-current transducers using the same reference voltage. 2. Description of the prior art In regulation, control and analog/digital conversion systems, pairs of voltage-to-current transducer circuits using the same reference voltage (control voltage) are often employed. In these circuits it is comprehensively essential to guarantee an identical offset and slew-rate behaviour of the two transducers. Commonly the circuit employed is substantially the one shown in Fig. 1. The two operational amplifiers OP1 and OP2 use the same reference voltage V ref and constitute two feedback loops together with the respective feedback transistors M1 and M2; the two loops regulate the voltages V₁ and V₂ to a value equal to V ref . The currents flowing through the transistors M1 and M2 will be given by: I₁ = V₁/R₁ and I₂ = V₂/R₂ , respectively. Of course the two transistors M₁ and M₂ may be MOS transistors (e.g. DMOS) or bipolar transistors (e.g. NPN). The pair of phase-opposed GATE signals ( and  ) operatively enables the operational amplifiers OP1 and OP2, alternately. In such a circuit it is important to ensure precision of the regulated voltages V₁ and V₂ in respect to V ref , as well as of the respective response times to a step variation of the V ref value. The main causes of error are: residual offset differences between the two operational amplifiers OP1 and OP2; electrical potential differences between the ground potential of the sensing resistors R1 and R2 and the ground potential of the operational amplifiers OP1 and OP2; slew-rate differences between the operational amplifiers due to the capacitive pairing relative to the two compensation capacitors needed for determining a correct small-signal frequency response of the two amplifiers, beside differences of the current generators responsible for the charge and discharge time of the two compensation capacitors. In order to obviate to these problems it is normally necessary to carry out accurate internal trimmings on each one of the two operational amplifiers so as to minimize the residual offset of each operational amplifer. The block diagram of an operational amplifier is depicted in Fig. 2. The input differential stage and the intermediate gain stage have a gain commonly comprised between 300 and 1000 each and are followed by an unitary gain output stage or buffer, which may typically be an emitter follower stage. The emitter follower output stage reduces the output impedance so as to be able to drive relatively low impedance loads. SUMMARY OF THE INVENTION It has now been found that a substantial identity of residual offset and equalization of the slew-rate of the two transducers may be obtained using a lesser number of components and by carrying out a single offset correction trimming intervention, by employing the improved equalization and control circuit, object of the present invention. The circuit of the invention utilizes substantially a single control operational amplifier core, formed by a single input differential stage and a single intermediate gain stage and employs two distinct unitary gain output stages for driving the feedback transistors of the two voltage-to-current transducers. The voltages detected across the two sensing resistors are alternately fed to the differential input stage of the amplifier by employing two switches driven by the pair of GATE signals ( and  ), which signals, through another pair of switches, operatively connect the output of the intermediate gain stage to the input of one or of the other of the two unitary gain output stages. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is the circuit diagram of the offset and slew-rate control and equalization circuit of a pair of voltage-to-current transducers, in accordance with the prior art. Fig. 2 is a typical block diagram of an operational amplifier of the type employed in the control circuit of Fig. 1. Fig. 3 is the circuit diagram of an offset and slew-rate control and equalization circuit for a pair of voltage-to-current transducers, in accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT The circuit of the invention is shown in Fig. 3 using the same symbols and legends for indicating the same parts which have been already described in relation to Figures 1 and 2 which are illustrative of the prior art. The analog switches are schematically shown in Fig. 3 and for each one of them it is indicated the relative GATE signal which enables, i.e. closes, the switch. The pair of phase-opposed GATE signals, respectively  and  may be obviously obtained by employing an inverter for obtaining the inverted phase signal (  ). In the control circuit of the invention, the high gain stages of the two control loops are common while only the unitary gain output stage is "duplicated". The relative unitary gain output stage is selected by means of a respective analog switch driven by one of the signals of the pair of phase-opposed GATE signals. The advantage which is derived from this configuration is that, by carrying out a single trimming of the high gain stages (i.e. the differential input stage and the intermediate gate stage) it is possible to compensate the offset error between V ref and V₁, while automatically obtaining the same identical precision also between V ref and V₂ (by being the output stage's gain equal to 1). Also the slew-rate time is substantially equalized because primarily a single compensation capacitance C is used and therefore the criticality of capacitance pairing is eliminated. On the other hand, though a difference may still exist between the charging currents of the unique compensation capacitance C (because of differences of the currents generated by the current generators of the output stage), this difference may be easily minimized in view of the relatively ease in obtaining precision levels below 0.5% in this kind of pairing among, integrated current generators.

Claims: An offset and slew-rate equalization and control circuit for a pair of voltage-to-current transducers using the same reference voltage (Vref) each one of which substantially comprises a grounded sensing resistance (R₁, R₂) across which a voltage signal, essentially equal to said reference voltage, develops and a feedback transistor (M₁, M₂), having an emitter or source connected to said sensing resistance, a collector or drain terminal through which said current signal, function of said reference voltage, is generated and a base or gate to which a control signal produced on an output terminal by a control operational amplifier, enabled by a first enabling signal in phase opposition to a second enabling signal of a control operational amplifier of the other transducer of the pair, to a noninverting input of which is fed said reference voltage while to an inverting input of which said voltage signal is applied, characterized by comprising an unique control operational amplifier core formed by an input differential stage having an inverting input and a noninverting input and an output, an intermediate gain stage having an input connected to the output of said input differential stage and an output, and two distinct unitary gain output stages, each having an input capable of being connected to the output of said intermediate gain stage and an output respectively connected to the base or gate of one and of the other of said two feedback transistors; said reference voltage being applied to the noninverting input of said input differential stage; the inverting input of said input differential stage being alternately connected by means of analog switches driven by said phase-opposed enabling signals (,  ), to one and the other of said sensing resistances; the output of said intermediate gain stage being functionally connected alternately, by means of analog switches driven by said phase-opposed enabling signals, respectively to the input of one or the other of said unitary gain output stages.

Inventors: SALINA ALBERTO, SALINA, ALBERTO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H03F3
IPC codes: H03F3, H03F1