Semiconductor integrated circuit and method of manufacture thereof

Abstract: A semiconductor device comprises a p-type semiconductor substrate (17), an n-type semiconductor well (9) formed on the substrate and connected to a positive power supply (VDD), a p-type semiconductor source (3) formed within the n-type semiconductor well (9), a p-type semiconductor layer (201) formed within the n-type semiconductor well (9) and having a lower impurity concentration than the p-type semiconductor source (3), a first gate electrode (1) formed over a region between the p-type semiconductor source (3) and the p-type semiconductor layer (201) through an insulating film (48), an n-type semiconductor emitter (10) formed within the p-type semiconductor layer (201) within the n-type semiconductor well (9), a first conductive layer (51) formed over the n-type semiconductor well (9) to connect with said p-type semiconductor source (3), a p-type semiconductor well (12) formed on said p-type semiconductor substrate (17) adjacent to said n-type semiconductor well (9), said p-type semiconductor well being connected to a ground power source (VSS), an n-type semiconductor source (6) formed within the p-type semiconductor well (12), an n-type semiconductor layer (202) formed within the p-type semiconductor well (12) and having a lower impurity concentration than the p-type semiconductor source (6), a second gate electrode (2) formed over a region between the n-type semiconductor source (6) and the n-type semiconductor layer (202) through an insulating film (48), a p-type semiconductor emitter (11) formed within the n-type semiconductor layer (202), a second conductive layer (51-2) formed over the p-type semiconductor well (12) to connect with the n-type semiconductor source (6), and a third conductive layer (C) connected with the n-type semiconductor emitter (10) and the p-type semiconductor emitter (11).

Description: The present invention relates to a semiconductor integrated circuit and a method of manufacture thereof and, more particularly, to a semiconductor integrated circuit in which npn and pnp bipolar transistors and p-and n-channel MOSFETs are formed together on the same chip and a method of manufacture thereof. Hereinafter, a description is given of a conventional inverter gate circuit of a Bi-CMOS structure which is formed of complementary metal oxide semiconductor field effect transistors (CMOSFETs) and npn bipolar transistors with reference to Fig. 4. Referring to Fig. 4, there is shown a typical prior art inverter gate circuit formed of CMOS transistors and npn bipolar transistors. As shown in Fig. 4, the inverter gate circuit is of a totem pole type in which emitter 105 of a load driving npn bipolar transistor Q101 and collector 106 of npn bipolar transistor Q102 are connected together at node d. Npn bipolar transistor Q101 has its base T101 connected to drain 103 of a p-channel MOSFET T101 so as to be driven by MOSFET 101. Heretofore, each of four transistors T101, T102, Q101 and Q102 constituting the inverter gate circuit is formed within a separate region on a semiconductor substrate. For this reason, the number of regions for isolating transistors from each other increases, thus increasing the occupied area of the inverter gate circuit on the semiconductor chip. N-channel MOSFET T102 is of a source current supply type and thus susceptible to base potential Vb of npn bipolar transistor Q102 during operation. That is, the effective gate potential of n-channel MOSFET T102 will be given by the difference between input potential Vin of MOSFET T102 and base potential Vb of npn bipolar transistor Q102. This leads to insufficient driving of n-channel MOSFET T102. Where MOSFET T102 is not driven sufficiently, the collector current of npn bipolar transistor Q102 will decrease, making the inverter gate circuit slow in operation. This disadvantage becomes remarkable particularly when a low supply voltage is used. Moreover, because collector 106 of npn bipolar transistor Q102 is connected to node d, the collector potential varies with output levels. For this reason, collector 106 of transistor Q102 must be electrically isolated from other transistors Q101, T101 and T102. That is, it is desired that npn bipolar transistor Q102 be formed within a n-type well and n-channel MOSFET T102 be formed within a p-type well. For this reason, it is impossible to form bipolar transistor Q102 and MOSFET T102 within the same well. Thus, with the inverter gate circuit of the Bi-CMOS structure it is required to provide a device isolation region between bipolar transistor Q102 and MOSFET T102. This leads to an increase of the occupied area of the inverter gate circuit on a semiconductor chip. It is an object of the present invention to provide a semiconductor device which is highly reliable, small in size and operates at high speed. According to one aspect of the present invention, there is provided a semiconductor device comprising the features set out in Claim 1. A method of manufacturing a semiconductor device according to claim 1 is defined by Claim 10. Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention. Fig. 1 is a circuit diagram of an inverter circuit according to an embodiment of the present invention; Fig. 2 is a plan view of a semiconductor device constituting the inverter circuit of Fig. 1; Figs. 3A through 3E are sectional views at stages in production of the inverter circuit of Fig. 1; Fig. 4 is a circuit diagram of circuit not incorporating the present invention; and Fig. 5 is a circuit diagram of a NAND circuit according to the other embodiment of the present invention. Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention and a method of manufacture thereof will be described with reference to the accompanying drawings. Fig. 1 is a circuit diagram of an inverter gate circuit according to an embodiment of the present invention, Fig. 2 is a plan view of the inverter gate circuit on a semiconductor chip and Figs. 3A through 3E are sectional views at stages in production of the inverter gate circuit. In the inverter gate circuit of Fig. 1, an input voltage Vin is applied to an input terminal A which is connected to a node a. Node a is connected to gate 1 of a p-channel MOSFET T1 and gate 2 of an n-channel MOSFET T2. Source 3 of p-channel MOSFET T1 is connected to a node b which is connected to a power supply terminal C supplied with a supply voltage VDD. Drain 4 of p-channel MOSFET T1 is connected to base 7 of an npn bipolar transistor Q1. Source 5 of n-channel MOSFET T2 is connected to base 8 of a pnp bipolar transistor Q2. Drain 6 of MOSFET T2 is connected to ground. Emitter 10 of bipolar transistor Q1 is connected to a node c which is connected to an output terminal B from which an output voltage Vout is derived. Emitter 11 of bipolar transistor Q2 is also connected to node c. Collector 12 of bipolar transistor Q2 is connected to ground. According to such an inverter gate circuit, source 6 of n-channel MOSFET is directly connected to ground. Therefore, there is no decrease in the effective gate voltage of n-channel MOSFET T2 unlike the art not incorporating the present invention in which the base of an npn bipolar transistor is connected to the source of the n-channel MOSFET. Also, the use of pnp bipolar transistor Q2 in place of the npn transistor used in the prior art permits an inverter action even if the inverter gate circuit is not of a source current supply type. Because the inverter gate circuit of the present invention is not of a source current supply type, the effective gate input potential of n-channel MOSFET T2 becomes the input voltage Vin itself. Thus, it is possible to supply a larger base current to base 8 of pnp bipolar transistor Q2 which is connected to the drain 5 of n-channel MOSFET T2. Hence, pnp bipolar transistor Q2 can be driven by a larger collector current. This allows the inverter gate circuit to be operated at a much higher speed. With the circuit not incorporating to present invention, there is a need for the collector 106 of npn bipolar transistor Q102 to be electrically isolated from other transistors Q101, T101 and T102 because its collector potential varies with output levels. In other words, npn bipolar transistor Q102 cannot share a collector region of the same conductivity type with npn bipolar transistor Q101. For this reason, there is a problem of need for isolation regions. As shown in Fig. 1, however, the collectors of the pnp and npn bipolar transistors are opposite to each other in conductivity type. This permits pn junction isolation between transistors Q1 and Q2, thus obviating the necessity of provision of an isolation region between Q1 and Q2. Therefore, the inverter gate circuit can be operated at a high speed and formed in a small size. Furthermore, according to an embodiment of the present invention, to achieve a higher speed in operation and a smaller size of the inverter gate circuit, the layout of the semiconductor device is improved. Hereinafter, improvements in the layout of the inverter gate circuit will be described with reference to the plan view of Fig. 2 and a method of manufacture of the inverter gate circuit will be described with reference to Figs. 3A through 3E. Fig. 2 and Figs. 3A through 3E illustrate an inverter gate circuit which is improved in the pattern layout on a p-type semiconductor substrate. It is also possible to form the pattern-layout improved inverter gate circuit on an n-type semiconductor substrate. Constituent elements corresponding to those of the circuit shown in Fig. 1 are designated by like reference numerals. In Fig. 2, through not shown, a highly doped n+ buried diffusion layer and a highly doped p+ buried diffusion layer are formed on a p-type semiconductor substrate, which are shown in Figs. 3A through 3E. On the p-type semiconductor substrate is formed a p-type epitaxial layer 20. In p-type epitaxial layer 20, an n-type well region 9 is formed on the highly doped n+ buried diffusion layer not shown in Fig. 2. Likewise, a p-type well region 12 is formed on the highly doped p+ buried diffusion layer not shown in Fig. 2. A highly doped n+ diffusion layer 23 for assuring collector current flow is formed within n-type well region 9 in such a way to pierce the highly doped n+ buried diffusion layer not shown in Fig. 2. A contact hole 24 is formed in an oxide film (not shown in Fig. 2) formed on highly doped n-type semiconductor layer 23. A collector electrode (not shown in Fig. 2) is formed on highly doped n+ semiconductor layer 23 through contact hole 24. Highly doped n+ semiconductor layer 23, the highly doped n+ buried diffusion layer and part of n well region form the collector region of an npn bipolar transistor. Here the mention of part of n well region 9 is based on the ground that a p-channel MOSFET is further formed within n well region 9 as will be described later. Moreover, a highly doped p+ source diffusion region 3 is formed within n-type well region 9. A contact hole 29 is formed in an oxide film (not shown in Fig. 2) formed on highly doped source diffusion region 3. A source electrode (not shown in Fig. 2) is formed on highly doped p+ source diffusion layer 3 through contact hole 29. Region 201 is served as the drain diffusion and the base diffusion region in the n-type well 9. The impurity concentration of region 201 have a value that is desirable to the base diffusion region. A contact hole 30 is formed in an oxide film (not shown in Fig. 2) formed on highly doped n+ emitter diffusion region 10. An emitter electrode 31 formed of n-type polysilicon is formed on highly doped n+ emitter diffusion region 10 through contact hole 30. Emitter electrode 31 is formed integral with an emitter electrode 41 of a pnp bipolar transistor formed within p-type well region 12 as will be described below. That is, the emitter electrode is common to the npn bipolar transistor formed within n-type well region 9 and the pnp bipolar transistor formed within the p-type well region. A contact hole 32 is formed in an oxide film (not shown in Fig. 2) formed on emitter electrode 44. An emitter electrode (not shown in Fig. 2) is formed on emitter electrode 44 through contact hole 32. On the other hand, within p-type well region 12 is formed a highly doped p+ diffusion region 33 for assuring collector current flow in such a way as to pierce the higly doped p+ buried diffusion region not shown in Fig. 2. A contact hole 34 is formed in an oxide film (not shown in Fig. 2) formed on highly doped p+ semiconductor layer 33. A collector electrode (not shown) is formed on highly doped p+ semiconductor layer 33 through contact hole 34. Highly doped p+ semiconductor layer 33, the higly doped p+ buried semiconductor layer and part of p well region 2 form the collector region of an pnp bipolar transistor. Here the mention of part of p well region 12 is based on the ground that an n-channel MOSFET is further formed within p-well region 12. Within p-type well region 12 is further formed highly doped n+ source diffusion region 6. In an oxide film (not shown in Fig. 2) formed on highly doped n+ source diffusion region 6 is formed a contact hole 39 through which a source electrode (not shown) is formed on highly doped n+ source source diffusion region 6. Region 202 is served as the drain diffusion and the base diffusion region in the p-type well 12. The impurity concentration of region 202 have a value that is desirable to the base diffusion region. A highly doped p+ emitter diffusion region 11 is formed within lightly doped n-type base diffusion region 202. A contact hole 40 is formed in an oxide film (not shown in Fig. 2) formed on highly doped p+ emitter diffusion region 11. An emitter electrode 41 formed of p-type polysilicon is formed on highly doped p+ emitter diffusion region 11 through contact hole 40. Emitter electrode 41 is formed integral with emitter electrode 31 formed on n-type polysilicon of the npn bipolar transistor formed within n-type well region 9 as described above. Gate electrode 1 could be common to the p-channel and n-channel MOSFETs. Common gate electrode 1 is provided with a gate electrode unit 1 of the p-channel MOSFET so that a channel may be formed between source diffusion region 3 and drain diffusion region 201 of the p-channel MOSFET through a gate oxide film not shown. Gate electrode 1 is further provided with a gate electrode unit 2 of the n-channel MOSFET so that a channel may be formed between source diffusion region 6 and drain diffusion region 202 of the n-channel MOSFET through a gate oxide film not shown. A contact hole 46 is formed in an oxide film (not shown) formed on common gate electrode 1 provided with the two gate electrode units. A gate pullout electrode is formed on common gate electrode 1 through contact hole 46. Region 201 is served as the drain diffusion and the base diffusion region in the n-type well 9. The impurity concentration of region 201 have a value that is desirable to the base diffusion region. On the other hand, the drain of the n-channel MOSFET and the base of the pnp bipolar transistor are formed integral with each other within p-type well 12. As described above, because the collector regions of the bipolar transistors are opposite to each other in conductivity type, there is no need for an isolation region, permitting pn junction isolation. The symmetric disposition of corresponding elements formed within two well regions 9 and 12 will allow the emitter electrodes of the npn and pnp bipolar transistors to be formed integral with each other and the gate electrodes of the p-channel and n-channel MOSFETs to be formed integral with each other at the shortest distance. That is, the shortest wiring between corresponding regions may be made. This permits the device to be formed smaller and the number of contacts to be decreased. Thereby, much higher speed of operation will be achieved and the manufacturing yield will also be improved. With such a layout as shown in Fig. 2, input terminal A shown in Fig. 1 is connected to the gate electrodes through contact hole 46, output terminal B is connected to emitters 10 and 11 through contact hole 32, and power supply terminal C is connected to the collector 23 through contact hole 24. Power supply terminal C is also connected to source 3 through contact hole 29. Ground potential Vss is connected to collector 33 through contact hole 34 and to source 6 through contact hole 39. Source 6 of the n-channel MOSFET need not necessarily to be connected to power supply terminal C to which collector 23 is connected. That is, distinct from collector 23, source 6 may be connected to a second ground potential of, for example, minus several volts. Such a connecting means can apply a back gate bias to the n-channel MOSFET, reducing capacitance to achieve much higher speed of operation and make improvements in reliability. Moreover, source 3 of the p-channel MOSFET may be connected to a second ground potential which is plus several volts higher than collector 23. Likewise, much higher speed of operation and improvements in reliability will be achieved. A description is given below of a method of manufacturing the inverter gate circuit shown in Fig. 2 with reference to Figs. 3A through 3E. Corresponding parts are designated by like reference numerals in Figs. 3A through 3E. First, as shown in Fig. 3A, solid phase diffusion of, for example, antimony (Sb) is made in a predetermined position of p-type semiconductor substrate, thereby to form highly doped n+ buried diffusion layer 18. It is desirable that the surface density be 10 18 to 10 26 cm -3 and the sheet resistance be 100 Ω/ or below. Next, ion implantation and thermal diffusion of, for example, boron (B) is made to form highly doped p+ buried diffusion layer 19. At this point the surface density is controlled to 10 17 to 10 20 cm -3 . Subsequently, p-type epitaxial layer 20 is formed by means of, for example, chemical vapor deposition (CVD). It is desirable that the density of epitaxial layer 20 be 10 15 to 10 17 cm -3 and its thickness be 3 µ or below. As shown in Fig. 3B, ion implantation and thermal diffusion are next made to the surface of epitaxial layer 20 so that lightly doped n- well region 9 is formed to overlie highly doped n+ buried buried diffusion layer 18. Likewise, ion implantation and thermal diffusion are then made to the surface of epitaxial layer 20 to form lightly doped p- well region 12 which overlies highly doped p+ buried diffusion layer 19. In forming well regions 9 and 12, a period of time of the thermal diffusion step should be as short as possible. This is to prevent deteriorating of precise of n+ buried diffusion layer 18 and p+ buried diffusion layer 19 due to the thermal diffusion. The p-type epitaxial layer 20 may be used instead of forming the p-well region. Next, as shown in Fig. 3C, a field oxide layer 47 serving as an element isolation region is formed in a predetermined position of the surface of epitaxial layer 20 by means of, for example, the LOCOS (localized oxidation of silicon) method using selective oxidation. A highly doped N+ type semiconductor layer 23 for facilitating the flow of collector current is subsequently formed in a predetermined position of n- well region 9 in such a way as to pierce n+ buried diffusion layer 18 by means of ion implantation and thermal diffusion. A highly doped p+ type semiconductor layer 33 is subsequently formed in a predetermined position of p- well region 12 in such a way as to pierce p+ buried diffusion layer 19 by means of ion implantation and thermal diffusion. Next, a thin oxide film, which serves as a gate oxide film later, is formed over the entire surface by means of, for example, thermal oxidation. Then, ions are implanted into at least channel regions of the p-channel MOSFET formed in n- well region 9 and the n-channel MOSFET formed in p- well region 12 through the oxide film for controlling the threshold voltages of the MOSFETs. Next, for example, polysilicon, which is a gate material, is deposited over the entire surface by means of, for example, chemical vapor deposition (CVD). The entire surface is then coated with photoresist not shown. The photoresist is developed to a predetermined shape by photoetching method. Using the photoresist as a mask, the polysilicon layer and the thin oxide layer are sequentially etched to form gate electrode 1 and gate oxide film 48 of the p-channel MOSFET and gate electrode 2 and gate oxide film 48 of the n-channel MOSFET. As the gate material, silicide or metal may be used instead of polysilicon. Next, ions of, for example, arsenic (As) are selectively implanted into a region of p- well region 12 in which the source of the n-channel MOSFET is to be formed, thereby to form source diffusion layer 6. A diffusion layer 202 is selectively formed by means of ion implantation so as to extend over a region in which the drain of the n-channel MOSFET is to be formed and a region in which the base of the pnp bipolar transistor is to be formed. The diffusion layer is shared between the drain of the n-channel MOSFET and the base of the pnp bipolar transistor. Thereby, the number of manufacturing steps can be decreased. The impurity concentration of region 202 serving as the drain diffusion region and the base diffusion region have a value that is desirable to the base diffusion region. That is, region 202 is formed to have an impurity concentration which is 10 to 100 times lower than that of source region 6 of the n-channel MOSFET. As an example, the impurity concentration of source region 6 is 10 20 cm -3 or more and the impurity concentration of region 202 serving as the drain and base is 10 18 - 10 19 cm -3 . By provision of such a difference in impurity concentration between the source and drain, the drain is allowed to take the LDD structure. This can avoid localized concentration of electric field, making the occurrence of avalanche phenomenon difficult. As a result, the withstanding voltage property between the gate and drain and the reliability of the device can be improved. Next, region 202 serving as the base of transistor Q2 and the drain of transistor T2 is formed by an ion implantation step. The impurity concentration of region 201 is 10 to 100 times lower than that of source region 3. As a result, the withstanding voltage property between the gate and drain is improved and the reliability of the device is enhanced. This is the same as in the case of region 202 serving as the base of transistor Q2 and the drain of transistor T2. Region 202 is served as the drain diffusion and the base diffusion region in the p-type well 12. The impurity concentration of region 202 have a value that is desirable to the base diffusion region. Next, ions of, for example, boron (B) or boron fluoride (BF 2 ) are selectively implanted into predetermined source and drain regions of the p-channel MOSFET within n- well region 9, thereby forming source diffusion region 3. Region 201 is served as the drain diffusion and the base diffusion region in the n-type well 9. The impurity concentration of region 201 have a value that is desirable to the base diffusion region. Next, as shown in Fig. 3D, an insulation film 49 such as an oxide film is formed over the entire surface by means of, for example, CVD. Next, contact holes 30 and 40 are formed in that parts of insulating film 49 which correspond to predetermined emitter forming regions within n- well region 9 and p- well region 12 by means of, for example, photoetching method using photoresist. Ions of, for example, arsenic (As) are implanted into the npn bipolar transistor forming region within n- well region 9 and thermally diffused into p-type semiconductor layer 201 (solid phase diffusion from polysilicon), thereby to form a highly doped n+ emitter diffusion region 10. Next, ions of, for example, boron (B) or boron fluoride (FB 2 ) are implanted into the pnp bipolar transistor forming region within p-well region 12 and thermal diffused into n-type semiconductor layer 202 (solid phase diffusion from polysilicon), thereby to form a highly doped p+ emitter diffusion region 11. It is desirable that the thermal diffusion steps for emitter diffusion regions 10 and 11 should be performed simultaneously if possible. At least one of emitter diffusion regions 10 and 11 may be formed directly by ion implantation and thermal diffusion instead of the diffusion from the polysilicon. As the conductive material, metal, polycide or silicide may be used instead of polysilicon. MBE (Molecular Beam Epitaxy) may be used. In the case of metal, particularly aluminum, ion implantation should be made to drain/base diffusion region 201, 202 directly in forming emitter diffusion regions 10 and 11. Of course, both of the pnp and npn transistors or one of them may use aluminum. Next, by means of photoetching method using photoresist, patterning is made on the polysilicon to form common emitter electrode 44. Common emitter electrode 44 is implanted with n- impurities about over n-well region 9 and with p-type impurities about over p-well region 12 as described above. Next, an insulating film 50 such as a BPSG film is deposited over the entire surface by means of, for example, CVD and then flattened. Collector contact holes 24 and 34, source contact holes 29 and 39, an emitter contact hole 32 and a gate contact hole which is shown in Fig. 2 though not shown in Figs. 3A through 3E are formed in the insulating film by means of, for example, photoetching method using photoresist. Next, a metal material, usually aluminum (Al), is deposited over the entire surface by means of, for example, sputtering, and then patterned to form the circuit connections shown in Fig. 1. The VDD power supply metal line is connected to electrode 51. The Vout metal line is connected to electrode C. The ground metal line is connected to electrode 51-2. The electrode (gate electrode) to which the Vin metal line is connected is not shown. In forming p+ and n+ buried diffusion layers 18 and 19, one of them, for example, the p+ buried diffusion layer may be formed after the formation of epitaxial layer 20. The effect is to prevent deteriorating of precise due to the thermal process for the p+ buried diffusion layer. As an example, the p+ buried diffusion layer may be formed after the formation of element isolation region 47. After the formation of a thick mask material, ions of boron (B) are implanted into a predetermined region. At this point, an ion acceleration voltage is selected so that a predetermined depth is reached. In general, when the depth is 1.5 µm, an acceleration voltage on the order of MeV is required. The ion-implanted region is activated by the subsequent thermal process. In the case of the n+ buried diffusion layer, phosphorous (P) or arsenic (As) should be used. By such a manufacturing method, a layout-improved inverter gate circuit according to an embodiment of the present invention can be manufactured. With the embodiment described above, npn and pnp bipolar transistors are formed of vertical bipolar transistors. Alternatively, one of them may be formed of a lateral bipolar transistor. Common emitter electrode 44 is formed to extend across emitter 10 of the npn bipolar transistor and emitter 11 of the pnp bipolar transistor. Such a common emitter electrode helps to reduce the number of contact holes 32 and to connect n+ emitter electrode 31 and p+ emitter electrode 41 together. Alternatively, a separate contact hole and emitter electrode may be provided for each of n+ emitter electrode 31 and p+ emitter electrode 41. This approach may also be applied to the gate electrode. That is, a separate contact hole and gate electrode may be provided for each of gate electrode 1 of the n-channel MOSFET and gate electrode 2 of the p-channel MOSFET. Furthermore, with respect to electrode 51 formed to extend across collector 23 of the npn bipolar transistor and source 3 of the p-channel MOSFET, a separate collector electrode may be provided. Similarly, with respect to electrode 51-2 formed to extend across emitter 33 of the pnp bipolar transistor and source 6 of the n-channel MOSFET, a separate emitter electrode may be provided. Fig. 5 is a circuit diagram of a NAND circuit according to another embodiment of the present invention. In Fig. 5, a p-type MOSFET T3 is connected in parallel with T1 of the inverter gate circuit of Fig. 1 and an n-type MOSFET T4 is connected in series with T2. D is the other input terminal of the NAND circuit. Thereby, the NAND logical operation becomes feasible. Transistor T3 is formed within the same well as transistors T1 and Q1. Transistor T4 is formed within the same well as transistors T2 and Q2. This permits miniaturization of the device as is the case with the embodiment of Fig. 1. The LDD structure of transistors T3 and T4 is the same as that of transistors T1 and T2 of Fig. 1. Similarly, the device reliability is enhanced through the improvement in the withstanding voltage property between the gate and drain. As described above, according to the present invention, the problem of an increase in the number of device isolation regions resulting from the need of electrical isolation of the collector of the load driving bipolar transistor can be solved. This can provide a semiconductor integrated circuit which is small in size and fast in operation. Furthermore, the operating margin at a low supply voltage is also improved because the inverter gate circuit is of a grounded source type. Because the base of a bipolar transistor and the drain of a MOSFET are formed within the same diffusion region, both the pnp and npn bipolar transistors can be made very small and the number of contacts can be decreased. Moreover, the drain of a MOSFET is made lower in impurity concentration than the source. This LDD structure avoids localized concentration of electric field, making the occurrence of avalanche phenomenon difficult. Thereby, the withstanding voltage property between gate and drain is improved and the reliability of the device is enhanced. Therefore, a semiconductor integrated circuit which is smaller in size, faster in operation, highly reliable and good in manufacturing yield and a method of manufacture therefor can be provided. Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, shown and described herein. Accordingly, various modifications may be made without departing from the scope of the appended claims. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device comprising: a positive power source (VDD); a ground power source (VSS); a p-channel MOSFET (T1) having a first source (3) connected to said positive power source, a first gate (1) and a first drain (4); an npn bipolar transistor (Q1) having a first collector (9) connected to said first source, a first base (7) connected to said first drain and a first emitter (10); an n-channel MOSFET (T2) having a second drain (5), a second gate (2) and a second source (6) connected to said ground power source; and a pnp bipolar transistor (Q2) having a second emitter (11) connected to said first emitter, a second base (8) connected to said second drain and a second collector (12) connected to said ground power source; said first drain (4) and said first base (7) being formed within the same well and said second drain (5) and said second base (8) being formed within the same well, wherein the first drain is formed of a layer which as a whole has a lower impurity concentration than the impurity concentration of the first source, and the second drain is formed of a layer which as a whole has a lower impurity concentration than the impurity concentration of the second source. A semiconductor device according to Claim 1, wherein said first drain (4) and said first base (7) have the same structure and said second drain (5) and said second base (8) have the same structure. A semiconductor device according to Claim 1, wherein said first drain (4) and said first base (7) have the same impurity concentration and said second drain (5) and said second base (8) have the same impurity concentration. A semiconductor device according to Claim 1, wherein at least one of said npn and pnp bipolar transistors (Q1,Q2) is a vertical transistor. A semiconductor device according to Claim 1, further comprising: a second p-type MOSFET (T3) connected in parallel with said p-type MOSFET (T1) and formed within the same well as said p-type MOSFET; and a second n-type MOSFET (T4) connected in series with said n-type MOSFET (T2) and formed within the same well as said second n-type MOSFET (T2). A semiconductor device according to Claim 1, further comprising: a p-type semiconductor substrate (17); an n-type semiconductor well (9) formed on said substrate (17) and connected to said positive power supply (VDD); said first source (3) being formed within said n-type semiconductor well (9); a p-type semiconductor layer (201) formed within said n-type semiconductor well (9) and forming said first drain, the layer as a whole having a lower impurity concentration than said first source (3); said first gate (1) being formed over a region between said first source (3) and said p-type semiconductor layer (201) on an insulating film (48); said first emitter (10) being formed over said p-type semiconductor layer (201) within said n-type semiconductor well (9); a first conductive layer (51) formed over said n-type semiconductor well (9) to connect with said first source (3); a p-type semiconductor well (12) formed on said p-type semiconductor substrate (17) adjacent to said n-type semiconductor well (9), said p-type semiconductor well being connected to said ground power source (VSS); said second source (6) being formed within said p-type semiconductor well (12); an n-type semiconductor layer (202) formed within said p-type semiconductor well (12) and forming said second drain, the layer as a whole having a lower impurity concentration than said second source (6); said second gate (2) being formed over a region between said second source (6) and said n-type semiconductor layer (202) on an insulating film (48); said second emitter (11) being formed within said n-type semiconductor layer (202) within said p-type semiconductor well (12); a second conductive layer (51-2) formed over said p-type semiconductor well (12) to connect with said second source (6); and a third conductive layer (C) connected with said first emitter (10) and said second emitter (11). A semiconductor device according to Claim 6, further comprising: an n-type buried semiconductor layer (18) formed between said p-type semiconductor substrate (17) and said n-type semiconductor well (9) and having a higher impurity concentration than said n-type semiconductor well (9); a second n-type semiconductor layer (23) formed between said n-type buried semiconductor layer (18) and said first conductive layer (51) and having a higher impurity concentration than said n-type semiconductor well (9); a p-type buried semiconductor layer (19) formed between said p-type semiconductor substrate (17) and said p-type semiconductor well (12) and having a higher impurity concentration than said p-type semiconductor well (12); and a p-type second semiconductor layer (33) formed between said p-type semiconductor buried layer (19) and said second conductive layer (51-2) and having a higher impurity concentration than said p-type semiconductor well (12). A semiconductor device according to Claim 6, further comprising: a first emitter electrode (31) formed over said n-type semiconductor well (9) to connect with said first emitter (10); a second emitter electrode (41) formed over said p-type semiconductor well (12) to connect with said second emitter (11); and said first emitter electrode (31) forming a p-n junction with said second emitter electrode (41) and both said emitter electrodes (31,41) being connected to said third conductive layer (C) at said p-n junction. A semiconductor device according to Claim 6, further comprising: a second FET structure (T3) connected in parallel with a first FET structure (T1) within said n-type semiconductor well (9); and a fourth FET structure (T4) connected in series with a third FET structure (T2) within said p-type semiconductor well (12). A method of manufacturing a semiconductor device according to Claim 1 comprising: a first step of forming an n-type semiconductor well (9) and a p-type semiconductor well (12) on a substrate (17); a second step of forming a first p-type semiconductor layer (3) and a second p-type semiconductor layer (201), the second layer (201) as a whole having a lower impurity concentration than said first p-type semiconductor layer (3) within said n-type semiconductor well (9), forming a semiconductor gate electrode (1) over a region between said first p-type semiconductor layer (3) and said second p-type semiconductor layer (201) on an insulating film, forming a first n-type semiconductor layer (6) and a second n-type semiconductor layer (202), the second n-type layer (202) as a whole having a lower impurity concentration than said first n-type semiconductor layer (6), and forming a semiconductor gate electrode (2) over a region between said first n-type semiconductor layer (6) and said second n-type semiconductor layer (202) on an insulating film; and a third step of forming a third n-type semiconductor layer (10) within said second p-type semiconductor layer (201) and forming a third p-type semiconductor layer (11) within said second n-type semiconductor layer (202).

Inventors: MAEDA TAKEO, MAKITA KOJI, MOMOSE HIROSHI, MAEDA, TAKEO, MAKITA, KOJI, MOMOSE, HIROSHI, MAEDA, TAKEO, C/O INTELLECTUAL PROPERTY DIV., MAKITA, KOJI, C/O INTELLECTUAL PROPERTY DIV., MOMOSE, HIROSHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21