Method of controlling misfit dislocation

Abstract: A method of controlling misfit dislocation in the production of an epitaxial semiconductor wafer comprising a semiconductor substrate (1a) and, deposited thereon, an epitaxial layer (1b) having an impurity concentration differing from that of the semiconductor substrate (1a), characterised by controlling strain applied on the back surface of the semiconductor substrate (1a), prior to depositing the epitaxial layer (1b), and thereby controlling misfit dislocation in the near and interface between the semiconductor substrate (1a) and the epitaxial layer (1b). Strain may be applied by sand-blasting.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for producing an epitaxial wafer and more particularly to a method of controlling a misfit dislocation to be created in or near the interface between a semiconductor substrate of the epitaxial wafer and an epitaxial layer thereof during producing the epitaxial wafer. 2. Description of the Related Art Recently, the so-called epitaxial wafer comprising a semiconductor substrate of a lower resistivity and an epitaxial layer of a higher resistivity has gained attention as a starting wafer for a high integrated DRAM or a high-speed CMOS device. Metal impurity intrinsically contained in crystal or invading a wafer during producing the above semiconductor device is present at a junction in the wafer. The metal impurity causes various crystal defects and causes a current leakage or dielectric strength deterioration, so that the performance of the semiconductor device deteriorates. In order to avoid deterioration in the performance of the semiconductor device, various attempts have been made. In particular, exemplifying an epitaxial wafer, it has been thought that since the epitaxial wafer has a structure in which an epitaxial growth layer is epitaxially interfaced with a semiconductor substrate, the top surface layer of the epitaxial layer in and on which a semiconductor device is fabricated is remote from the back surface of the semiconductor substrate. Therefore, creating an extrinsic deformation or strain on the back surface of the semiconductor substrate cannot produce a desired gettering effect. For example, A.S.Salih et al have stated this fact in PP.419-421, Appl. Phys. Lett., Vol.46, No.4, February 15, 1985. On the other hand, H.Kikuchi et al have reported in PP.463-465, Appl. Phys. Lett., Vol.54, No.5, January 30, 1989 that they discovered in and near the interface between a high-doped and reduced crystal lattice spacing of the substrate of an p/p⁺-structured epitaxial wafer and a normal crystal lattice spacing of the epitaxial growth layer of the p/p⁺-structured epitaxial wafer and in particular, near the top surface of the substrate adjoining the epitaxial growth layer, a misfit dislocation caused by a misfit between the crystal lattice of the substrate and the normal crystal lattice of the epitaxial growth layer and that the misfit dislocation getters a metal impurity. FIG.5 illustrates a schematic longitudinal section of a p/p⁺-structured epitaxial wafer. In FIG.5, the epitaxial wafer generally indicated at 1 comprises a p⁺-type semiconductor substrate la and a p-type epitaxial layer 1b deposited on one major surface of the semiconductor substrate 1a. An impurity concentration of the semiconductor substrate 1a is 1 x 10¹⁸ atoms/cm³ or more and an impurity (i.e., boron) concentration of the epitaxial layer 1b is about 1 x 10¹⁵ atoms/cm³. The concentration is different by a factor of 10³ or more. The p/p⁺-structured epitaxial wafer 1 with such great impurity concentration difference is ready to create a misfit dislocation in the interface between the semiconductor substrate la and epitaxial layer 1b, which will depend on other specifications of the epitaxial wafer 1. This misfit dislocation getters a heavy metal present in the epitaxial wafer 1. FIG.6 represents results of measurements of distributions of the concentration of intentionally doped Cu in the depth of the p/p⁺-structured epitaxial layer and semiconductor substrate and the density of created misfit dislocation. As apparent from FIG.6, the misfit dislocations are created in the interface between the semiconductor substrate la and epitaxial layer 1b. The distribution of the density of the misfit dislocation well matches that of the concentration of the Cu so that part of the interface having the peak distribution of the density of the misfit dislocation effectively getters the Cu. The present inventors tested in detail how an epitaxial growth condition affects a creation of misfit dislocations and found out that the creation of misfit dislocations remarkably depended on a difference between impurity concentrations of an epitaxial growth layer and a substrate, the thicknesses of the epitaxial growth layer and substrate, etc. The present inventors also found out that intrinsic misfit dislocations present in the epitaxial wafer were non-uniform over the epitaxial wafer and the amount of the intrinsic misfit dislocations was small. FIGS.7 and 8 represent how the resistivity of a silicon crystal substrate and the thickness of an epitaxial layer characterize the frequency of creation of misfit dislocations when a p-type and 10 Ω cm epitaxial layer is grown on each of 530 µm p⁺-type silicon crystal substrates with <111> and <100> crystal orientations. In FIGS.7 and 8, the symbol of a white square represents the frequency of creation of 100 or more misfit dislocations in the case of the substrate of <100> crystal orientation, the symbol of a black square represents the frequency of creation of 100 or more misfit dislocations in the case of the substrate of <111> crystal orientation, the symbol of a white regular triangle represents the frequency of creation of above 50 and below 100 misfit dislocations in the case of the substrate of <100> crystal orientation, the symbol of a black regular triangle represents the frequency of creation of above 50 and below 100 misfit dislocations in the case of the substrate of <111> crystal orientation, the symbol of a white circle represents the frequency of creation of 50 or less misfit dislocations in the case of the substrate of <100> crystal orientation, and the symbol of a black circle represents the frequency of creation of 50 or less misfit dislocations in the case of the substrate of <111> crystal orientation. The values superimposed on the respective curves in broken lines represent bows of epitaxial wafers. As apparent from FIGS.7 and 8, the larger an epitaxial wafer bow, the greater the number of misfit dislocations. Herein, Lang's method of X-ray diffraction topography performs a (400) diffraction of the epitaxial wafer. The topographical images of misfit dislocations present in the epitaxial wafer were counted to provide the density of misfit dislocation of the epitaxial wafer. As apparent from the above description, the specifications of an epitaxial wafer determine the frequency of creation of intrinsic misfit dislocations in the epitaxial wafer. However, the gettering effect of only the intrinsic misfit dislocations present in the epitaxial wafer are insufficient to give an actual high integrated semiconductor circuit device. In addition, it is impractical that the specifications of the epitaxial wafer are selected to achieve the effective frequency of occurrence of intrinsic misfit dislocations ,i.e., the intrinsic gettering operation of the epitaxial wafer. Another gettering method for epitaxial wafer is the so-called IG method using a microdefect created by a precipitation of an oxygen concentration exceeding the solubility of oxygen in the epitaxial wafer. However, the IG method is impractical because of the non-uniformity and the poor repeatability of the gettering effect throughout an epitaxial wafer. In addition, formation of a Ge mixed crystal layer, during an epitaxial layer growth period, as disclosed by A.S. Salih et al above, uses the above-described misfit dislocation. This disclosure entails a technological problem in determining the mixing ratio of the Ge mixed crystal, and controlling the creation of a misfit dislocation thereby. D. Beauchiane et al , J. Electrochemical Soc. 136 (6), pages 1787-1793 (June 1989), disclose a method for the production of an epitaxial semiconductor wafer comprising an impurity-doped semiconductor substrate and, deposited thereon, an epitaxial layer having an impurity concentration smaller by a factor of at least 10³ than that of the semiconductor substrate. The method comprises subjecting the back surface of the semiconductor substrate to mechanical strain, by deposition of a film of silicon oxide, polysilicon or silicon nitride, and depositing the epitaxial layer on the strained substrate. IBM Technical Disclosure Bulletin 29 (4), page 1561 (Sept. 1986) describes a method for gettering impurities by controlled generation of misfit dislocations. In this method, when the doping concentration in an epitaxial layer is smaller than that of a silicon substrate, a mechanical stress is created at their interface, owing to a crystalline lattice mismatch. If this stress is large enough, by choosing the right substrate doping concentration and epitaxial silicon thickness, misfit dislocations as gettering sites are formed at the interface, and then impurities are gettered by the misfit dislocations. Mechanical damage on the back side of a wafer is described as one of the "widely used" techniques for creating stacking and dislocation faults for gettering sites. SUMMARY OF THE INVENTION According to the present invention, a method of controlling creation and density of misfit dislocations in the production of an epitaxial semiconductor wafer comprising an impurity-doped semiconductor substrate and, deposited thereon, an epitaxial layer having an impurity concentration smaller by a factor of at least 10³ than that of the semiconductor substrate, comprises subjecting the back surface of the semiconductor substrate to mechanical strain by the application of an abrasive under pressure, and depositing the epitaxial layer on the front surface of the strained substrate, thereby increasing the frequency, and controlling the density, of misfit dislocation in and near the interface between the semiconductor substrate and the epitaxial layer. DESCRIPTION OF THE INVENTION The mechanical strain involves the application of abrasive under pressure, for example by using a free abrasive, hard needle scribing or, preferably, sand-blasting. Both wet and dry sand-blasting are effective. Hard particles used in sand-blasting are preferably high-purity silica (SiO₂) powder, for preventing contamination. For example, in a p/p⁺-structured epitaxial wafer with boron added as an impurity, the crystal lattice spacing in the semiconductor substrate is decreased so that the crystal lattice in the region of the epitaxial layer near the interface is compressed to create naturally a lattice strain near the interface, thereby creating an intrinsic misfit dislocation. However, producing the predetermined extrinsic mechanical strain on the back surface of the semiconductor substrate prior to epitaxial growth further increases the frequency of creation of intrinsic misfit dislocation in the epitaxial wafer. Such increased misfit dislocations effectively getters mainly a metal impurity present in the epitaxial layer so as to improve the performance of various devices deposited in and/or near the top surface of the epitaxial layer. Thus, the method of the present invention of controlling a misfit dislocation remarkably increases the yield of nondefective of a high-integrated semiconductor device, for example. The extrinsic mechanical strain created by sandblast etc. on the back surface of the p⁺-type semiconductor substrate produces a counteraction to a shrunk crystal lattice present in the p⁺-type semiconductor substrate on the epitaxial layer. Despite the above-mentioned counteraction such extrinsic strain contributes to an increase of a misfit dislocation in and near the interface. It is apparent from an embodiment of the present invention described hereinafter that providing a mechanical extrinsic strain to the back surface of the wafer creates a high-density of misfit dislocation in or near the interface between the epitaxial layer and substrate. In addition, the present invention controls the amount of created extrinsic strains thereby to control the frequency or level of creation of misfit dislocation. In addition, the present invention uniformly creates an extrinsic strain on the back surface of a semiconductor substrate for epitaxial wafer thereby to uniformly create a misfit dislocations. BRIEF DESCRIPTION OF THE DRAWINGS FIGS.1(A) and 1(B) are illustrations of a process for producing an epitaxial wafer of an embodiment of the present invention, FIG.1(A) being a longitudinal section through a semiconductor substrate prior to a deposition of an epitaxial layer, FIG.1(B) being a longitudinal section through the epitaxial wafer; FIG.2 is a longitudinal section through the semiconductor substrate to which an extrinsic strain has been provided; FIG.3(A) is a schematic diagram of an epitaxial wafer with extrinsic strain; FIG.3(B) is a schematic diagram of an epitaxial wafer without extrinsic strain; FIG.4 is a graph representing a comparison between creations of misfit dislocation in the epitaxial wafer with extrinsic strain of FIG.3(A) and in the epitaxial wafer without extrinsic strain of FIG.3(B); FIG.5 is a longitudinal section through an epitaxial wafer; FIG.6 is a combined graph representing a TEM-image of misfit dislocations and a frequency distribution of the misfit dislocations, and a result of a secondary ion-mass spectrography of a Cu density in-depth profile when the top surface of the epitaxial wafer of FIG.5 is positively contaminated with Cu; FIG.7 is a graph representing a creation of misfit dislocation when the resistivity of a semiconductor substrate and the thickness of an epitaxial layer are changed; and FIG.8 is a graph representing a creation of misfit dislocation when the thickness of a semiconductor substrate and the resistivity of an epitaxial layer are changed. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of a process of the present invention for producing an epitaxial wafer will be described with reference to FIGS.1-4 hereinafter. FIG.1(B) illustrates a longitudinal section through an epitaxial wafer. In FIG.1(B), an epitaxial wafer indicated at 1 includes an p-type epitaxial layer 1b deposited on one major surface of a p⁺-type semiconductor substrate 1a of FIG.1(A). In the present embodiment, the impurity concentration of the semiconductor substrate 1a is 1 x 10¹⁸ atoms/cm³ or more and the impurity concentration of the epitaxial layer 1b is 1 x 10¹⁵ atoms/cm³ or less. A dopant for the semiconductor substrate 1a and epitaxial layer 1b was boron (i.e., B). Blasting SiO₂ particles to the back surface of the semiconductor substrate 1a by sandblast prior to a deposition of the p-type epitaxial layer 1b created an extrinsically strained layer 1c as shown in FIG.2 in order to cause a creation of misfit dislocations in the epitaxial wafer. The following test was conducted in order to establish the effect of the creation of the misfit dislocations in the epitaxial wafer produced by the above process: I. Test Conditions 1) Semiconductor substrate for epitaxial wafer The test employed a generally circular p-type semiconductor substrate produced by Czochralski process. The diameter of the semiconductor substrate was 100 mm. The crystal orientation thereof was <100>. The resistivity thereof was 0.002 Ω cm (Boron concentration: 5.7 x 10¹⁸ atoms/cm³). The thickness thereof was 525 µm. 2) Epitaxial layer The epitaxial layer was p-type. The thickness thereof was 3.3 µm. The resistivity thereof was 12 Ω cm (Boron concentration: 1.1 x 10¹⁵ atoms/cm³). The epitaxial layer was grown in a cylindrical furnace under the following conditions: i) Hydrogen flow: 140 l/min ii) Pressure: 1013 hPa (760 Torr) iii) Si-source: SiHCl₃ iv) Doping gas: B₂H₆ v) Growth rate: 1.0 µm/min 3) Extrinsic strain Sandblast created an extrinsic strain on the back surface of the semiconductor substrate. The LD density of the extrinsic strain is 45 x 10⁴. i) SiO₂ particle size: 4-5 µm diameter ii) Damage depth: 1 µm iii) Blast pressure: 9.8 N/cm² (1.0 kg/cm²) 4) Evaluation of misfit dislocation FIGS.3(A) and (B) are schematic diagrammatic views of the back surfaces of epitaxial wafers of a (400) diffraction taken by Lang's method of X-ray topography. In particular, FIG.3(A) represents a creation of misfit dislocations (misfit lines) in an epitaxial wafer with extrinsic strain and on the other hand, FIG.3(B) represents a creation of misfit dislocations in an epitaxial wafer without extrinsic strain. As apparent from FIGS.3 (A) and 3(B), only the epitaxial wafer with extrinsic strain of FIG.3(A) has a grid-shaped arrangement of misfit dislocations. FIG.4 represents the densities of misfit dislocation of an epitaxial wafer with extrinsic strain (LD density: 45 x 10⁴) and an epitaxial wafer without extrinsic strain, both the wafers having the same production conditions other than the presence or absence of extrinsic strain. Counting the number of misfit dislocations present in the whole epitaxial wafer without extrinsic strain directly from an X-ray topograph of this epitaxial wafer provides the density of misfit dislocation of the epitaxial wafer without extrinsic strain. On the other hand, the density of misfit dislocation of the epitaxial wafer with extrinsic strain was computed from the total number of misfit dislocations per about 1 cm² area of an X-ray topograph of this epitaxial wafer as a representative value, which expresses the number of dislocation lines crossing an imaginary line 1 cm long on the surface. This measurement of the density of misfit dislocation resulted in that a first epitaxial wafer comprising a semiconductor substrate la without extrinsic strain and an epitaxial layer 1b deposited on the semiconductor substrate la failed to produce many misfit dislocations and on the other hand, a second epitaxial wafer 1 comprising a semiconductor substrate la with extrinsic strain and an epitaxial layer 1b deposited on the semiconductor substrate la produced a multitude of misfit dislocations approximately 50 times those in the case of the first epitaxial wafer 1. The above embodiment of the present invention blasted SiO₂ particles to the back surface of the semiconductor substrate of the epitaxial wafer to create the extrinsic strain on the back surface of the semiconductor substrate. In addition, the above-described embodiment of the present invention has been applied to a case of depositing a p-type epitaxial layer on a p-type semiconductor substrate. The present invention is also applicable to the cases of depositing an n-type epitaxial layer on an n-type semiconductor substrate, an n-type epitaxial layer on a p-type semiconductor substrate, and a p-type epitaxial layer on an n-type semiconductor substrate.

Claims: A method of controlling density and creation of misfit dislocations in the production of an epitaxial semiconductor wafer comprising an impurity-doped semiconductor substrate (1a) and, deposited thereon, an epitaxial layer (1b) having an impurity concentration smaller by a factor of at least 10³ than that of the semiconductor substrate (1a), which method comprises subjecting the back surface of the semiconductor substrate (1a) to mechanical strain by the application of an abrasive under pressure, and depositing the epitaxial layer (1b) on the front surface of the strained substrate, thereby increasing the frequency, and controlling the density, of misfit dislocation in and near the interface between the semiconductor substrate (1a) and the epitaxial layer (1b). A method according to claim 1, wherein the semiconductor substrate is p-type. A method according to claim 2, wherein the epitaxial layer is p-type. A method according to claim 2, wherein the epitaxial layer is n-type. A method according to claim 1, wherein the semiconductor substrate is n-type. A method according to claim 5, wherein the epitaxial layer is p-type. A method according to claim 5, wherein the epitaxial layer is n-type. A method according to any preceding claim, wherein the application of strain includes sand-blasting. A method according to any preceding claim, wherein the impurity concentrations in the semiconductor substrate and in the epitaxial layer are respectively at least 10¹⁸ and 10¹⁵ or less atoms/cm³.

Inventors: MIKI KATSUHIKO, NARUKE YUKIO, MIKI, KATSUHIKO, NARUKE, YUKIO
Applicants: SHINETSU HANDOTAI KK, SHIN-ETSU HANDOTAI COMPANY LIMITED
Application year: 1990
Main classification: H01L21
IPC codes: H01L21