CPU-bus controller

Abstract: A synchronous bus controller which provides a functional control link between one or more microprocessors and an asychronous main input/output bus is provided. The bus controller includes a state machine and data bus width determining logic enabling the bus controller to initiate and control access operations between microprocessors and accessible devices on the main input/output bus when the microprocessor and the accessed device may have different data bus widths. The bus controller includes logic circuitry to determine the number of access cycles required to complete a requested access operation and detects the last access cycle of a current access operation to terminate an access operation and provide a ready signal to the microprocessor indicating that the bus controller is ready for the next access request.

Description: BACKGROUND OF THE INVENTION The present invention relates to microprocessor bus controllers and in particular to bus controllers incorporating state machine technology to provide a functional link between microprocessors having different size data widths, and a data bus which allows access to devices having different size data widths on the data bus. In a microprocessor controlled computer system such as a personal or desk top computer, the computer requires a set of electronic connections between the microprocessor and other devices making up the computer system. These communication lines are collectively called the input/output system or I/O bus. All messages in data pass between the microprocessor and other system components travel on the bus. A complete I/O bus includes several component parts: the data bus, lines over which data flows; the address bus, a set of lines that specify the memory addresses to which data will be transferred; and various support lines carrying control signals and power for the various devices on the bus. A bus controller initiates and controls all I/O bus cycles. The controller controls the interface to the I/O bus, the address and data buffers, the CPU, the direct memory access (DMA) device and other memory controllers. Prior art bus controllers were integrated into and functioned as a part of the microprocessor architecture. As microprocessor technology has advanced, bus controller technology has become separate and distinct. Similarly, as the number of peripheral devices available for use with various microprocessors has increased, it has become obvious that peripheral devices usable with one integrated microprocessor-bus controller architecture can not generally be used with the bus controller of another microprocessor. Separate microprocessor and bus controller architectures provide system design flexibility as well as facilitating interface of many peripheral devices among many different microprocessors. In the present state of the art, microprocessors are expected to interface with memory manage units, CRT controllers, floppy disc controllers, hard disc controllers, arithmetic cove processors and the like. In addition, it is well known that the next generation of 32-byte microprocessors must be able to interface with already existing peripheral devices without the immediate need for specifically designed bus controllers. However, even though the present day microprocessor and bus controller architectures are separated, bus controllers designed to interface with a specific type or range of types of microprocessors and peripheral devices are still limited to certain system configurations and further limit design flexibility for the next generation of microprocessors. See for example the well-known personal computer models known as the "PC XT" and "PC AT", manufactured and marketed by the IBM Corporation. Bus controllers are known in the art. International Publication No. WO 86/00436 describes a data processor having dynamic bus sizing. The data processor has a bus controller which is able to communicate with any of a plurality of system resources having different data port sizes using a communication bus which is a multiple of the port sizes. European Patent Publication No. 0 333 319 describes a single-chip microprogrammable sequencer having a bidirectional bus compatible with a number of common microprocessors. The sequencer provides a mechanism for detecting which type of microprocessor is connected to it and can automatically set the mode for compatibility with the particular microprocessor. U.S. Patent No. 4,580,213 describes a microprocessor having bus control logic which will automatically perform multiple bus cycles in response to a single request from a central microprocessor. Such prior art patents, however, do not provide the features of the invention described herein and as summarized in the following summary of the invention. SUMMARY OF THE INVENTION A microprocessor and I/O bus controller according to the principles of the present invention comprises a state machine I/O bus controller which provides a functional control link between the microprocessors and the main I/O data bus. The bus controller provides the signals required to control the data flow to and from the I/O bus. It further generates the control strobes required to facilitate communication between the microprocessors and plug in adapters of 8-,16- or 32-bit widths. While the interface between the microprocessors and the bus controller is synchronous in nature, the I/O bus interface may be asynchronous. The microprocessors can have a data width of 16 or 32 bits or more while the devices on the I/O bus can have data widths of 8, 16 or 32 bits. Any difference between the data width size of a microprocessor and the bus device accessed is automatically accommodated by the bus controller state machine. The use of a state machine within a bus controller provides the ability to change the function and timing of various signals quickly and easily, and also provides the means to change the bus cycle functionality and timing (in a dynamic sense) in response to I/O conditions or specific microprocessor access requests. The bus controller also provides reset control and clock generation logic for the computer system. In the bus controller of the present invention, the state machine senses and evaluates an access request from a microprocessor; i.e., what kind of processor 16- or 32-bit processor, and which bits have been requested, etc. Then the state machine evaluates the data bus width of the device which is being accessed by the microprocessor request to determine the proper action to be taken. For example, if a 32-bit microprocessor requests 32 bits of data from an 8 bit device, the bus controller accesses that 8-bit device 4 times in succession, to gather the requested data bits and then passes all 32 bits to the microprocessor simultaneously. Thus, the microprocessor and its controlling application software typically do not have to be aware of data bus widths, because the bus controller automatically accommodates any differences in data widths between the microprocessor and the accessed device. The bus controller includes logic to determine the number of I/O bus cycles required to satisfy a microprocessor data request to accommodate for the differences in data width sizes between a microprocessor and accessed device. Thus, while the bus controller will generate the 4 byte enable bytes required for any microprocessor access request, if a 16-bit wide microprocessor requests 16 bits of data from a 32-bit wide memory device, the bus controller will only access the memory device once to transfer the two bytes to satisfy the 16-bit data request. The implementation of the bus controller of the present invention also provides additional features. For example, if a microprocessor needs to access a co-microprocessor, which is physically not on the system main I/O bus, but on the microprocessor board, then the bus controller disables the data buffers to and from the main I/O bus to allow the microprocessor to access the co-microprocessor. Further, the bus controller generates special control signals that disables the I/O bus data buffers and the I/O bus control strobes generated to allow a read access to "private" on board system memory, to allow a much faster access than could be achieved through the system main I/O bus. The bus controller of the present invention can be implemented as a single VLSI component. This allows very efficient use of logic partition and reduction of the total computer system component devices. Furthermore, the system operates faster because of tighter logic integration. One aspect of the present invention is a bus controller for a computer system which has a microprocessor. The microprocessor has a data path with a microprocessor data path width. The computer system has controllable devices. Each controllable device has a respective data path with a device data path width. The controllable devices are coupled to an input/output bus. The bus controller controls input/output transfer operations on the input/output bus in response to microprocessor requests. The bus controller comprises a state machine coupled to the microprocessor and to the input/output bus. The state machine is responsive to command signals from the microprocessor and is responsive to response control signals from the controllable devices coupled to the input/output bus. The state machine generates input/output bus control signals based on the command signals and the response control signals from the controllable devices. The input/output bus and the controllable devices are responsive to the input/output bus control signals generated by the state machine. The state machine initiates and controls input/output transfer operations on the input/output bus in response to the microprocessor requests. The bus controller also comprises a width detector coupled to the microprocessor. The width detector determines the microprocessor data path width of the microprocessor and provides a microprocessor path width signal indicative of the microprocessor data path width. The bus controller further comprises a last cycle detector coupled to the microprocessor, to the input/output bus, to the width detector, and to the state machine. The last cycle detector detects the device data path width of the controllable devices based on the response control signals from the controllable devices. The last cycle detector responds to the command signals and to the input/output bus control signals to detect the last input/output transfer operation of a current microprocessor-requested operation based on the microprocessor path width signal, the device data path width of the controllable devices, the command signals, and the input/output bus control signals. The last cycle detector generates a last cycle signal which indicates detection of the last input/output transfer operation. The last cycle detector provides the last cycle signal to the state machine. Preferably, the state machine responds to the last cycle signal to generate a ready signal at the completion of the last input/output transfer operation of the current microprocessor-requested operation. The ready signal indicates that the bus controller is ready to receive a next requested operation. Preferably, the bus controller further comprises a status interpreter coupled between the microprocessor and the state machine to receive the command signals and to generate state machine stimulus signals in response to the command signals. The state machine responds to the state machine stimulus signals to initiate microprocessor-requested operations. The bus controller preferably further comprises a buffer controller coupled to the state machine, to the input/output bus, to the last cycle detector and to the enable detector. The buffer controller generates enable signals and direction control signals. A data path and address buffer is coupled to the buffer controller and to the input/output bus. The data path and address buffer controls data flow on the input/output bus in response to the enable signals and to the direction control signals. Also preferably, the bus controller further includes a master clock coupled to the state machine to produce a plurality of master clock signals. A clock signal generator is coupled to the state machine, to the status interpreter, and to the master clock. The clock signal generator generates a plurality of secondary clock signals in response to the plurality of master clock signals. At least one of the plurality of secondary clock signals is provided for use by the status interpreter. The bus controller preferably further comprises a reset controller coupled to the clock signal generator. The reset controller is responsive to a shutdown signal to generate a processor reset signal to reset the microprocessor. The state machine is responsive to the state machine stimulus signals to generate a shutdown signal and to provide the shutdown signal to the reset controller and to the last cycle detector. The reset controller generates the processor reset signal in response to the shutdown signal. The state machine is responsive to the state machine stimulus signals to generate a halt signal and to provide the halt signal to the last cycle detector. The last cycle detector responds to the halt signal to cause the state machine to execute a halt input/output operation wherein no controllable devices are accessed. Another aspect of the present invention is an input/output bus controller for a multiple processor computer system having controllable devices coupled to an input/output bus. The input/output bus controller controls processor-related operations on the input/output bus in response to processor requests and in response to response control signals from the controllable devices. The processor-requested operations each comprise a plurality of input/output transfer operations. The input/output bus controller comprises a processor interface coupled to the multiple processors and to the input/output bus. The processor interface detects a type of operation requested by the multiple processors based on the processor requests from the processors. The processor interface generates stimulus signals based on the type of operation requested. The processor interface comprises a last cycle detector responsive to the processor requests and to the response control signals to detect a last input/output transfer operation of a current processor-requested operation and to generate a last cycle signal indicative of the detection of the last input/output transfer operation. The bus controller further comprises an enable detector responsive to the processor requests and to the response control signals to determine the data width of the multiple processors and to generate enable signals which indicate the number of data bytes required to complete the current processor-requested operation. The bus controller comprises a status interpreter responsive to the processor requests and to the response control signals to determine a type of operation requested and to generate the stimulus signals based on the type of operation requested. The bus controller further comprises a state machine coupled to the input/output bus and to the processor interface. The state machine initiates and controls the processor-requested operations on the input/output bus in response to the stimulus signals from the processor interface and in response to the response control signals from the controllable devices. The state machine receives the last cycle signal from the last cycle detector. The bus controller includes a data path and address buffer coupled to the input/output bus to receive and store data and address information. The bus controller includes a buffer controller coupled to the state machine. The buffer controller receives inputs from the state machine, from the processor interface and from the input/output bus. The buffer controller is coupled to the data path and address buffer. The buffer controller generates enable and data flow control signals in response to the inputs to control the data path and address buffer to thereby control data flow and address flow on the input/output bus. The bus controller includes a master clock coupled to the state machine to produce a plurality of master clock signals. A clock signal generator is coupled to the state machine, to the status interpreter and to the master clock. The clock signal generator is responsive to the plurality of master clock signals to generate a plurality of secondary clock signals. At least one of the plurality of secondary clock signals is provided for use by the status interpreter. Each one of the multiple processors has a data width. The controllable devices have respective data widths. The bus controller controls the processor-requested operations between the multiple processors and the controllable devices based on the data widths of the multiple processors and based upon the data widths of the controllable devices. Preferably, the input/output bus controller further comprises a reset controller coupled to the clock signal generator. The reset controller is responsive to a shutdown signal to generate a processor reset signal to reset the multiple processors. Preferably, the input/output bus controller is implemented in a VLSI chip. Preferably, the state machine generates a halt signal in response to corresponding stimulus signals generated by the status interpreter. The state machine provides the halt signal to the last cycle detector. The last cycle detector is responsive to the halt signal to cause the state machine to execute a halt operation wherein no controllable devices are accessed. The state machine generates a shutdown signal and provides the shutdown signal to the reset controller and to the last cycle detector in response to corresponding stimulus signals generated by the status interpreter. The reset controller generates the processor reset signal in response to the shutdown signal. Also preferably, the input/output bus controller is a synchronous controller operating in synchronism with the master clock signals. Preferably, the input/output bus is an asynchronous bus. Preferably, the data width of one of the multiple processors is different from the data width of another of the multiple processors. Also preferably, the data width of at least one of the multiple processors is different from the data width of at least one of the controllable devices. A still further aspect of the present invention is a method of controlling access operations between controllable devices in response to command signals representing requested access operations from a processor and response control signals from the controllable devices, wherein the device data path width of the controllable devices may be different from the processor data path width of the processor. The method comprises the steps of determining a number of data bytes requested in a requested access operation; determining the data path width of the processor; determining the data path width of the controllable device accessed during the requested access operation; transmitting signals representing data, device control signals, address information signals and processor command signals along an interfacing input/output bus based on a type of requested access operation; generating input/output bus control signals to control the interfacing input/output bus in response to stimulus signals corresponding to the type of requested access operation; and determining in a last cycle detector a last cycle required to complete the requested access operation based on the number of data bytes requested, the processor data path width of the processor and the device data path width of the controllable device accessed during the requested access operation. The step of determining a last cycle comprises the steps of comparing a highest requested data byte address with a data byte address of a current access cycle; and generating a last cycle signal when the highest requested data byte address matches the current access cycle data byte address. The method includes the further step of generating in a state machine a ready signal in response to the last cycle signal. The ready signal indicates to the processor that a next access operation may be requested. Another aspect of the present invention is a bus controller which controls access operations between a controlling device and a controllable device based on operations request signals received from the controlling device and based on control signals from the controllable device. The controlling device and the controllable device each has a data path with a data path width. The controllable device is coupled to an input/output (I/O) bus. The bus controller comprises a controller interface coupled to the controlling device. The controller interface receives the operation request signals from the controlling device. The controller interface determines a type of operation the controlling device has requested. The controller interface determines a starting address for executing the operation requested based on the operation request signals. The controller interface determines the data path width of the controlling device based on the operation request signals. The bus controller also comprises a sequential circuit coupled to the controller interface and the I/O bus. The sequential circuit sequentially executes a number of access cycles based on the starting address for the operation requested and based on the type of operation requested. The sequential circuit provides a cycle status signal indicative of a status of the sequential access cycles currently being executed. The bus controller also includes a last cycle detector coupled to the controller interface, to the sequential circuit and to the I/O bus. The last cycle detector determines the data path width of the controllable device based on a signal received from the I/O bus. The last cycle detector determines whether an access cycle currently being executed by the sequential circuit is a last access cycle required to complete the operation requested based on the data path width of the controllable device, based on the cycle status signal, and based on the operation request signals. The last cycle detector provides a last cycle signal to the sequential circuit to indicate detection of a last required cycle. The sequential circuit continues execution of access cycles until the sequential circuit receives the last cycle signal. The sequential circuit ceases execution of access cycles in response to the last cycle signal. Preferably, the requested access operation is a data read operation and the controller interface comprises means coupled to the controlling device for determining bit locations on the data bus of the controlling device at which to provide data during the data read operation. Also preferably, the controller interface comprises a bit enable detector coupled to the controlling device to receive the operation request signals. The bit enable detector detects bits to be accessed by the controlling device and provides a bit signal indicative of the bits to be accessed. Also preferably, the controller interface comprises a status interpreter coupled to the controlling device to receive the operation request signals, to determine a type of operation requested based on the operation request signals, and to provide an operation type signal indicative of the type of operation requested. Preferably, the last cycle detector comprises an evaluator coupled to the bit enable detector, to the status interpreter and to the sequential circuit. The evaluator evaluates the operation request signals, the cycle status signal, the bit signal and the data path width of the controllable device to detect whether the present access cycle is the last required access cycle. Preferably, the sequential circuit is synchronous with the controlling device and the I/O bus is asynchronous with the controlling device. Preferably, the sequential circuit provides bus control signals to the I/O bus with desired timing based on the control signals from the controllable devices. Preferably, the sequential circuit provides a ready signal to the controlling device in response to ceasing execution of the access cycles. The ready signal indicates that the bus controller is ready to receive a subsequent operation request signal. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a typical microprocessor-controlled computer system incorporating an I/O bus and a CPU/Bus controller according to the principals of the present invention; Figure 2 is a block diagram of a CPU/Bus controller according to the principles of the present invention; Figures 3a, 3b and 3c are a functional block diagram of the CPU/Bus controller shown in figure 2; Figures 4a and 4b are a logic diagram of the state machine shown in figures 2 and 3a; FIGS. 5a and 5b are a logic diagram of the last cycle detect circuitry shown in Figures 2 and 3a; Figure 6 is a diagram showing the package and pin layout for a VS2I chip implementing the CPU/Bus controller of the present invention; Figures 7a-7d are timing diagrams showing the relationship between various signal waveforms in the CPU/Bus controller of Figures 3a-3c; and Figure 8 is a conceptual block diagram of an alternate implementation of the bus controller of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Figure 1 the microprocessor controlled computer system block diagram is shown. The system is controlled by a central processing unit (CPU) 11, such as a 32-bit microprocessor part number 80386, manufactured by Intel Corporation described in the Intel "Microprocessor and Peripheral Handbook", Volume One, Microprocessor, 1988, on pages 4-1 through 4-128, and is incorporated by reference as if fully set forth herein. The CPU 11 is connected through buffers 27 to the main system memory 13 via local bus 15 and a memory bus 16. Also connected to the local bus 15 is a math co-processor or NPU 17 and a direct memory access (DMA) controller 19. An 80-bit numeric processor extension, part number 80387, manufactured by Intel Corporation, may be used as the math co-processor 17. The main system memory 13, which can be expanded up to eight megabytes or more of page/interleaved memory, is also coupled to a memory controller 25 and to the address/data buffers 27 via memory bus 16. The CPU 11, NPU 17 and DMA controller 19 are also coupled to the address/data buffers 27 and the CPU/Bus controller 21 via the local bus 15. To provide access to the remaining components of the computer system, the microprocessors 13,17, the DMA controller 19 and main system memory 13 are coupled to the system main I/O bus 23 via the address/data buffers 27. The remaining system components such as floppy disc controller 29 and others as shown are connected to the system main I/O bus 23. The system main I/O bus 23 is a 32-byte wide "arbitrated" bus similar to the IBM Micro Channel or an Apple Computer, Inc's Nubus. The architecture of this type of I/O bus provides the capability of microprocessors on add-in cards connected to the bus, to act as "master" processors on a par with the main system microprocessor 11 and which may assume temporary control of the entire system. Arbitration circuitry (not shown) included in the I/O bus 23 architecture, allocates microprocessor bus access and assures that no one device can monopolize the I/O bus. The I/O bus 23, provides full support for add-on cards, allowing other devices such as graphic printer controllers, or high resolution graphic display boards to be added to this system. The use of the I/O bus 23 enables access to the devices on the I/O bus 23 and is controlled by the CPU/Bus controller 21. Referring now, also to Figure 2, a functional block diagram of the CPU/Bus controller 21 constructed according to the principles of the present invention is shown. The CPU/Bus controller 21 performs the I/O bus control functions for a multiprocessor computer system and acts as the functional control link between the microprocessors 11,17 and the main I/O bus 23. The CPU/Bus controller 21 controls the interface between the CPU 11, NPU 17, DMA controller 19, the main system memory 13, the address/data buffers 27 and the memory controller 25 and the main I/O bus 23. The CPU/Bus controller operations with the CPU 11 are synchronous in nature while the operations with the I/O bus 23 are essential asynchronous. The function link or interface between the CPU 11 and the I/O bus 23 is accomplished by a state machine 31 in the CPU/Bus controller 21. The CPU/Bus controller 21 comprises 8 blocks or sections. These blocks are the clock generator 43, reset control 41, status interpreter 33, byte enable detect 35, last cycle detect 39, state machine 31, access latches 45 and buffer control/byte enable 37. The major signals utilized by the CPU/Bus controller 21 are listed and defined in Appendix I attached hereto. The clock generation section of the CPU/Bus controller 21 generates clock signals for various other sections of the computer system and comprises the reset control block 41 and the clock generator block 43. The reset control circuit 41 provides the proper timing and pulse width for a microprocessor reset signal and a system reset signal derived from a raw reset signal. The reset control circuitry 41 couples the microprocessor reset signal to the clock generator 43 where the processor reset signal is synchronized with the processor clock. The clock generator 43 generates various clock signals to be used in other functional sections of the computer system; e.g., serial port communications and floppy disk controller functions. The main clock input signal, CLK48M, to the clock generator 43 has a frequency of 48 megaHertz (MHz). This 48 MHz clock signal is frequency divided to provide a peripherals clock, PERCLK, signal having a frequency of 1.846 MHz. The main clock input signal is also divided by 3 to provide a disk clock, DSK16M, signal of 16 MHz which can be used by the floppy disk controller or any other system element requiring a 16 MHz clock. A variable frequency clock, DSK96M, signal is derived from the main clock input signal and has a frequency of 9.6 MHz or 16 MHz depending on the state of the DKCK16 input signal to the clock generator circuit 43. A system clock, SYSCLK, signal is derived from the processor clock, CLKPRO, input to the clock generator 43 and has a frequency equal to one-half the frequency of the processor clock. The system clock is used to synchronize the CPU/Bus controller 21 with the microprocessor 11 and the memory controller 25. When the CPU 11 comprises a 80386 microprocessor, the processor clock has a frequency of 40 MHz which yields a system clock of 20 MHz. The status interpreter block 33, the byte enable detect block 35 and the last cycle detect block 39 comprise a CPU interface section in the CPU/Bus controller 21. This section responds to an access request from the CPU 11, as indicated for example, by a /ADS signal from the microprocessor 11 in the case of a 80386 microprocessor. The response can be in the form of a I/O bus access to memory or to a port location. The type of access requested is defined by the signals WRITE, DATA, and MEM/IO in the case of an 80386 microprocessor. This access can be a read or a write and typically takes place through the I/O Bus 23. In addition to normal read/write accesses, the CPU/Bus controller 21 also handles the system cycles for interrupt acknowledge, halt and shutdown. A halt access stops the microprocessor and is not an I/O bus operation in that no data transaction occurs. The shutdown access is also not an I/O bus operation, but in this case the CPU/Bus controller issues a reset signal to the microprocessor. In a normal cycle, the microprocessor concludes the I/O bus access request by sampling a READY signal generated by the CPU/Bus controller state machine 31 at the completion of an access request. When the microprocessor 11 detects the presence of the ready signal, the current access cycle will be concluded if the SYSCLK signal is active, and the next access requested may begin. The status interpreter block 33 interprets status information input from the I/O bus 23 and microprocessor request information input from the CPU 11 to detect that the microprocessor has requested a bus access or an access to the system memory 13. In accordance with Table 1 below, the status interpreter 33 determines what type of access has been requested and provides the proper stimulus signals to the state machine 31 to commence the proper I/O bus 23 cycle activity. PWRI PDAT PMEM S0N S1N INTERRUPT ACKNOWLEDGE 0 0 0 00 0 CODE READ (memory read) 0 0 1 1 0 IO READ 0 1 0 1 0 MEMORY READ 0 1 1 1 0 NA 1 0 0 1 1 HALT {address=2} 1 0 1 0 0 SHUTDOWN {address=0} 1 0 1 0 0 IO WRITE 1 1 0 0 1 MEMORY WRITE 1 1 1 0 1 In response to information and control signals from the CPU 11 and the I/O bus 23 the bit enable detect block 35 evaluates the data bus width of the microprocessor 11 and the bit enable signal input information in accordance with Table 2 for a 32-bit microprocessor and Table 3 for a 16-bit microprocessor to determine which data bits are being requested by the CPU 11. This information is then relayed to the I/O bus 23 as well as other sections of the CPU/Bus controller to properly access the requested data. The last cycle detect block 39 evaluates input information from the I/O bus 23, the byte enable detect block 35, the CPU/Bus controller state machine 31 and the data width of the device being accessed to determine if the current I/O bus 23 access cycle is the last access cycle needed to fulfill the current microprocessor 11 request. If the present bus access cycle is the last access cycle required, the CPU/Bus controller 23 generates a ready signal to the microprocessor to allow the microprocessor 11 to proceed with the next request. The last cycle detect block 39 also generates the bit enable (i.e., addresses) manipulation control signals for the buffer control/byte enable block 37. 32-BIT PROCESSOR PBE3N PBE2N PBE1N PBE0N CWLEN CBHEN CBLEN CBE3N CBE2N CBE1N CBE0N 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 16-BIT PROCESSOR PBE3N PBE2N PBE1N PBE0N CWLEN CBHEN CBLEN CBE3N CBE2N CBE1N CBE0N x 0 1 0 0 1 0 1 1 1 0 x 0 0 1 0 0 1 1 1 0 1 x 0 0 0 0 0 0 1 1 0 0 x 1 1 0 1 1 0 1 0 1 1 x 1 0 1 1 0 1 0 1 1 1 x 1 0 0 1 0 0 0 0 1 1 The CPU/Bus controller state machine 31 generates the proper I/O bus 23 control strobes for the I/O bus 23 after the CPU interface section has determined the type of I/O bus cycle requested by a system on board microprocessor such as CPU 11. The state machine 31 is a synchronous state machine which supplies the required bus control strobes with appropriate timing. The state machine 31 also generates data byte enable signals corresponding to the low order address lines, as well as the actual command strobes and system status signals. The state machine 31 also provides cycle status information signals internal to the CPU/Bus controller 21 to indicate which portion of the bus access cycle is currently being executed. In response to internal signals such as the last cycle signal on line 38 generated by the last access detect block 39 and external input signals to the CPU/Bus controller such as I/O ready signals and bus control strobe disable information (utilized in a fast on board memory access), the state machine 31 also generates the READY signal to the microprocessor 11. The buffer control/byte enable block 37 generates the control signals which control the data path buffers 27 to control the data flow between the CPU 11 and the I/O bus 23. The byte enable (ie., addresses) signals which are necessary for the devices on the I/O bus 23 to properly decode the access are also generated by the buffer control/byte enable block 37. There are 2 data bytes to be controlled in a 16-bit system and 4 data bytes in a 32-bit system. A portion of the data path comprise crossover buffers which steer data from the lower data word to the upper data word as well as from a lower byte to an upper byte. Three additional buffers can store information on the lower byte for presentation to the microprocessor on subsequent I/O bus commands. This is used when the microprocessor 11 requests a 16- or 32-bit access to an 8-bit device on the I/O bus 23. In this case, the CPU/Bus controller commands up to 4 I/O bus 23 accesses to satisfy the CPU 11 request. Each access request from the microprocessor 11 can generate up to 4 data bytes. In order to satisfy a microprocessor request the CPU/Bus controller may have to access the I/O bus 23 up to 4 times; for example, a 32-bit request to a 8-bit device will require 4 access cycles. The microprocessor 11, in the case of a 32-bit microprocessor can request up to 32 bits of data which requires 1 access cycle from a 32-bit device, 2 access cycles from a 16-bit device or 4 access cycles from an 8-bit device. Each block of 8 bits requested requires a data byte enable signal to be generated by the CPU/Bus controller. The number of bus access cycles required is a function of the microprocessor data width, the device data width and the request. When a request is made, the data starting address is provided to the CPU/Bus controller by the microprocessor 11. If the request is a 4-byte (i.e., 32 bits) request then the access cycle has to start at byte 0 or byte 4. A 2-byte request (i.e., 16 bits) can start at bytes 0, 1 or 2. Similarly, a 3-byte access can start at byte 0 or 1 and a 1-byte access can start at any byte level. Since a device access proceeds in a known sequence, once the state machine 31 knows when to commence the access cycles, all it then needs to know is when to stop the access operation; i.e., when the request has been satisfied. The last cycle detect block 39 determines when the process stops by comparing the current request information from the microprocessor, the accessed device data width size and the data byte address. The highest requested data byte address is compared with the current access cycle and the current data byte enable signal and a READY signal is generated when a match is found. The READY signal indicates to the CPU 11 that the access is complete and the data lines are valid. Appendix II attached hereto lists the I/O bus access combinations as a function of possible data bytes and access device size. Appendix III attached hereto lists the proper byte enable signals corresponding to the different states of the information signals input by the I/O bus 23 and the CPU 11. Appendix IV attached hereto lists the conditions under which the last cycle detect block 39 generates a LAST CYCLE signal to the state machine 31 on line 38. The preferred embodiment of the CPU/Bus controller 21 is implemented in one VLSI chip integrated circuit housed in a rectangular 68-pin package. Figures 3a, 3b, and 3c are a functional logic block diagram of the VLSI integrated circuit which implements CPU/Bus controller 21. Figures 4a and 4b are a detailed logic diagram of the CPU/Bus controller state machine 31 and Figures 5a and 5b are a detailed logic diagram of the last cycle detect block 39. The package layout and pin assignments are shown in Figure 6. Appendix V attached hereto lists the electrical specifications for the VLS1 chip package. Figures 7a through 7d are timing diagrams showing the relationship between the various CPU/Bus controller signals for pipelined and non-pipelined I/O bus access and for private memory access. Alternatively, the functions of the buffer control/byte enable block 37 may be implemented in sections of the address/data buffers 27 as shown in Figure 8 (the address/data buffers 27 may also be implemented as a separate VLSI chip). In this embodiment, the TTL buffers in the data buffer section 271 are controlled directly by address and byte enable signals which appear on the system main I/O bus 23. The data transfer enable bits (BHE and BLE) and the word enable bit utilized to select data addresses (WLE) are generated in the address buffer section 273. This provides for all of the address and byte enable signals to generated on the same chip and to have the same timing. While the present invention has been described in conjunction with a specific embodiment thereof, it will be understood by those skilled in the art that alternatives, modifications and variations in form and detail may be made without departing from the scope of the appended claims.

Claims: A bus controller (21) for a computer system having a microprocessor (11), having a data path with a microprocessor data path width, and having controllable devices (29), each controllable device (29) having a respective data path with a device data path width and being coupled to an input/output bus (23), said bus controller (21) controlling input/output transfer operations on said input/output bus (23) in response to microprocessor requests, said bus controller (21) comprising: a state machine (31) coupled to said microprocessor (11) and said input/output bus (23), said state machine (31) responsive to command signals from said microprocessor (11) and responsive to response control signals from said devices (29) coupled to said input/output bus (23); said state machine (31) generating input/output bus control signals based on said command signals and said response control signals from said controllable devices (29); said input/output bus (23) and said controllable devices (29) being responsive to said input/output bus control signals generated by said state machine (31); said state machine (31) initiating and controlling input/output transfer operations on said input/output bus (23) in response to said microprocessor requests; a width detector (35) coupled to said microprocessor (11), said width detector (35) determining the microprocessor data path width of said microprocessor (11) and providing a microprocessor path width signal indicative of said microprocessor data path width; and a last cycle detector (39) coupled to said microprocessor (11), to said input/output bus (23), to said width detector (35), and to said state machine (31), said last cycle detector (39) detecting said device data path width of said controllable devices (29) based on said response control signals from said controllable devices (29), said last cycle detector (39) responding to said command signals and said input/output bus control signals to detect the last input/output transfer operation of a current microprocessor-requested operation based on said microprocessor path width signal, said device data path width of said controllable devices (29), said command signals, and said input/output bus control signals; said last cycle detector (39) generating a last cycle signal (38) which indicates detection of said last input/output transfer operation and providing said last cycle signal (38) to said state machine (31). The bus controller (21) as defined in Claim 1, wherein said state machine (31) responds to said last cycle signal (38) to generate a ready signal at the completion of said last input/output transfer operation of said current microprocessor-requested operation, said ready signal indicating that said bus controller (21) is ready to receive a next requested operation. The bus controller (21) as defined in Claim 1, further comprising a status interpreter (33) coupled between said microprocessor (11) and said state machine (31) to receive said command signals and to generate state machine stimulus signals in response to said command signals, said state machine (31) responding to said state machine stimulus signals to initiate microprocessor-requested operations. The bus controller (21) as defined in Claim 3, further comprising: a buffer controller (37) coupled to said state machine (31), to said input/output bus (23), to said last cycle detector (39) and to said enable detector, said buffer controller (37) generating enable signals and direction control signals; and a data path and address buffer (27) coupled to said buffer controller (37) and to said input/output bus (23), said data path and address buffer (27) controlling data flow on said input/output bus (23) in response to said enable signals and to said direction control signals. The bus controller (21) as defined in Claim 3, further including: a master clock (CLK48M) coupled to said state machine (31) to produce a plurality of master clock signals: and a clock signal generator (43) coupled to said state machine (31), to said status interpreter (33), and to said master clock (CLK48M), said clock signal generator (43) generating a plurality of secondary clock signals in response to said plurality of master clock signals, at least one of the plurality of secondary clock signals being provided for use by the status interpreter (33). The bus controller (21) as defined in Claim 5, further comprising a reset controller (41) coupled to said clock signal generator (43), said reset controller (41) responsive to a shutdown signal to generate a processor reset signal (SYSRST) to reset said microprocessor (11). The bus controller (21) as defined in Claim 6, wherein: said state machine (31) is responsive to said state machine stimulus signals to generate a shutdown signal and to provide said shutdown signal to said reset controller (41) and to said last cycle detector (39), said reset controller (41) generating said processor reset signal (SYSRST) in response to said shutdown signal; and said state machine (31) is responsive to said state machine stimulus signals to generate a halt signal and to provide the halt signal to said last cycle detector (39), said last cycle detector (39) responding to said halt signal to cause said state machine (31) to execute a halt input/output operation wherein no controllable devices (29) are accessed. An input/output bus controller (21) for a multiple processor computer system having controllable devices (29) coupled to an input/output bus (23), said input/output bus controller (21) controlling processor-related operations on said input/output bus (23) in response to processor requests and in response to response control signals from said controllable devices (29), said processor-requested operations each comprising a plurality of input/output transfer operations, said input/output bus controller (21) comprising: a processor interface (33, 35, 39) coupled to said multiple processors (11, 17) and to said input/output bus (23), said processor interface (33, 35, 39) detecting a type of operation requested by said multiple processors (11, 17) based on said processor requests from said processors (11, 17), said processor interface (33, 35, 39) generating stimulus signals based on the type of operation requested, wherein said processor interface (33, 35, 39) comprises: a last cycle detector (39) responsive to said processor requests and to said response control signals to detect a last input/output transfer operation of a current processor-requested operation and to generate a last cycle signal (38) indicative of detection of said last input/output transfer operation; an enable detector (35) responsive to said processor requests and to said response control signals to determine the data width of said multiple processors (11, 17) and to generate enable signals which indicate the number of data bytes required to complete the current processor-requested operation; and a status interpreter (33) responsive to said processor requests and to said response control signals to determine a type of operation requested and to generate said stimulus signals based on the type of operation requested; a state machine (31) coupled to said input/output bus (23) and to said processor interface (33, 35, 39), said state machine (31) initiating and controlling said processor-requested operations on said input/output bus (23) in response to said stimulus signals from said processor interface (33, 35, 39) and in response to said response control signals from said controllable devices (29), said state machine (31) receiving said last cycle signal (38) from said last cycle detector (39); a data path and address buffer (27) coupled to said input/output bus (23) to receive and store data and address information; a buffer controller (37) coupled to said state machine (31), said buffer controller (37) receiving inputs from said state machine (31), from said processor interface (33, 35, 39) and from said input/output bus (23), said buffer controller (37) coupled to said data path and address buffer (27), said buffer controller (37) generating enable and data flow control signals in response to said inputs to control said data path and address buffer (27) to thereby control data flow and address flow on said input/output bus (23); a master clock (CLK48M) coupled to said state machine (31) to produce a plurality of master clock signals; and a clock signal generator (43) coupled to said state machine (31), to said status interpreter (33) and to said master clock (CLK48M), said clock signal generator (43) responsive to said plurality of master clock signals to generate a plurality of secondary clock signals, at least one of the plurality of secondary clock signals being provided for use by said status interpreter (33); wherein: each one of said multiple processors (11, 17) has a data width; said controllable devices (29) have respective data widths; said bus controller (21) controls said processor-requested operations between said multiple processors (11, 17) and said controllable devices (29) based on the data widths of the multiple processors (11, 17) and based upon the data widths of said controllable devices (29). An input/output bus controller as defined in Claim 8, further comprising a reset controller (41) coupled to said clock signal generator (43) and responsive to a shutdown signal to generate a processor reset signal (SYSRST) to reset said multiple processors (11, 17). An input/output bus controller (21) as defined in Claim 8, wherein said input/output bus controller (21) is implemented in a VLSI chip. An input/output bus controller (21) as defined in Claim 9, wherein: said state machine (31) generates a halt signal in response to corresponding stimulus signals generated by said status interpreter (33), said state machine (31) providing said halt signal to said last cycle detector (39), said last cycle detector (39) responsive to said halt signal to cause said state machine (31) to execute a halt operation wherein no controllable devices (29) are accessed; and wherein said state machine (31) generates a shutdown signal and provides said shutdown signal to said reset controller (41) and said last cycle detector (39) in response to corresponding stimulus signals generated by said status interpreter (33), said reset controller (41) generating said processor reset signal (SYSRST) in response to said shutdown signal. An input/output bus controller (21) as defined in Claim 8, wherein said input/output bus controller (21) is a synchronous controller operating in synchronism with the master clock signals. An input/output bus controller (21) as defined in Claim 12, wherein said input/output bus (23) is an asynchronous bus. The input/output bus controller (21) as defined in Claim 8, wherein the data width of one of said multiple processors (11, 17) is different from the data width of another of said multiple processors (11, 17). The input/output bus controller (21) as defined in Claim 8, wherein the data width of at least one of said multiple processors (11, 17) is different from the data width of at least one of said controllable devices (29). A method of controlling access operations between controllable devices (29) in response to command signals representing requested access operations from a processor and response control signals from said controllable devices (29) wherein the device data path width of said controllable devices (29) may be different from the processor data path width of said processor, said method comprising the steps of: determining a number of data bytes requested in a requested access operation; determining the data path width of the processor; determining the data path width of the controllable device (29) accessed during the requested access operation; transmitting signals representing data, device control signals, address information signals and processor command signals along an interfacing input/output bus (23) based on a type of requested access operation; generating input/output bus control signals to control the interfacing input/output bus (23) in response to stimulus signals corresponding to the type of requested access operation; determining in a last cycle detector (39) a last cycle required to complete the requested access operation based on the number of data bytes requested, the processor data path width of the processor and the device data path width of the controllable device (29) accessed during the requested access operation, said step of determining a last cycle comprising the steps of: comparing a highest requested data byte address with a data byte address of a current access cycle; and generating a last cycle signal when said highest requested data byte address matches said current access cycle data byte address; and generating in a state machine (31) a ready signal in response to said last cycle signal, said ready signal indicating to said processor that a next access operation may be requested. A bus controller which controls access operations between a controlling device (11) and a controllable device (29) based on operations request signals received from the controlling device (11), and based on control signals from the controllable device (29), the controlling device (11) and the controllable device (29) each having a data path with a data path width, and the controllable device (29) being coupled to an input/output (I/O) bus (23), said bus controller (21) comprising: a controller interface (33, 35) coupled to the controlling device (11), said controller interface (33, 35) receiving the operation request signals from the controlling device (11), said controller interface (33, 35) determining a type of operation the controlling device (11) has requested, said controller interface (33, 35) determining a starting address for executing the operation requested based on the operation request signals, said controller interface (33, 35) determining the data path width of the controlling device (11) based on the operation request signals; a sequential circuit (31) coupled to the controller interface (33, 35) and the I/O bus (23), the sequential circuit (31) sequentially executing a number of access cycles based on the starting address for the operation requested and based on the type of operation requested, the sequential circuit (31) providing a cycle status signal indicative of a status of the sequential access cycles currently being executed; and a last cycle detector (39), coupled to the controller interface (33, 35), to the sequential circuit (31) and to the I/O bus (23), said last cycle detector (39) determining the data path width of the controllable device (29) based on a signal received from the I/O bus (23), said last cycle detector (39) determining whether an access cycle currently being executed by the sequential circuit (31) is a last access cycle required to complete the operation requested based on the data path width of the controllable device (29), based on the cycle status signal, and based on the operation request signals, wherein the last cycle detector (39) provides a last cycle signal (38) to the sequential circuit (31) to indicate detection of a last required cycle, the sequential circuit (31) continuing execution of access cycles until the sequential circuit (31) receives the last cycle signal (38), and the sequential circuit (31) ceasing execution of access cycles in response to the last cycle signal (38). The bus controller as defined in Claim 17, wherein the requested access operation is a data read operation and wherein the controller interface (33, 35) comprises: means coupled to the controlling device (11) for determining bit locations on the data bus of the controlling device (11) at which to provide data during the data read operation. The bus controller as defined in Claim 17, wherein the controller interface (33, 35) comprises: a bit enable detector coupled to the controlling device (11) to receive the operation request signals, said bit enable detector detecting bits to be accessed by the controlling device (11) and providing a bit signal indicative of the bits to be accessed. The bus controller as defined in Claim 19, wherein the controller interface (33, 35) comprises: a status interpreter (33) coupled to the controlling device (11) to receive the operation request signals, to determine a type of operation requested based on the operation request signals, and to provide an operation type signal indicative of the type of operation requested. The bus controller as defined in Claim 20, wherein the last cycle detector (39) comprises: an evaluator (CMPBYT) coupled to the bit enable detector, to the status interpreter (33) and to the sequential circuit (31), said evaluator (CMPBYT) evaluating the operation request signals, the cycle status signal, the bit signal and the data path width of the controllable device (29) to detect whether the present access cycle is the last required access cycle. The bus controller as defined in Claim 17, wherein the sequential circuit (31) is synchronous with the controlling device (11) and wherein the I/O bus (23) is asynchronous with the controlling device (11). The bus controller as defined in Claim 22, wherein the sequential circuit (31) provides bus control signals to the I/O bus (23) with desired timing based on the control signals from the controllable devices (29). The bus controller as defined in Claim 17, wherein the sequential circuit (31) provides a ready signal to the controlling device (11) in response to ceasing execution of the access cycles, the ready signal indicating that the bus controller (21) is ready to receive a subsequent operation request signal.

Inventors: LARSON RONALD J, LARSON, RONALD J.
Applicants: AST RESEARCH INC, AST RESEARCH, INC.
Application year: 1990
Main classification: G06F13
IPC codes: G06F13