Remote control unit

Abstract: A signal output apparatus particularly suitable for wireless remote control unit is disclosed. This signal output apparatus includes a CPU section (102); an output data storage section (101) for storing an output data given by the CPU section; a main clock signal generator section (102); a count section (104) for generating a timing signal for representing the output data in accordance with the main clock signal generated by the main clock signal generator; an output control section (103) for generating an output control signal whose level changes with the contents of the output data, in response to the timing signal; and a signal output section (105) for receiving the main clock signal and the output control signal for outputting the main clock signal intermittent in response to the level change of the output control signal. The main clocks are modulated by the output control section and signal output section of the signal output apparatus.

Description: BACKGROUND OF THE INVENTION The present invention relates to a signal output apparatus, and more particularly to a signal output apparatus suitable for use as a wireless remote control unit (commander) which transmits temporarily stored data to a controlled apparatus. Various types of output apparatus are known which output control signals or the like to a controlled apparatus. For example, in the case of a VTR, a wireless remote control unit with a built-in CPU, temporarily stores data such as reserved program recording data which include the date and time of program start/end, channel number, and the like, and thereafter outputs the data to a controlled VTR. A conventional signal output apparatus is constructed as shown in Fig. 4. Under control of a CPU section 102, data entered by an operator is temporarily stored in an output data storage unit 101 having a RAM, decoder and the like. When the data is to be outputted, the CPU section 102 fetches the data and controls main clocks (carrier) (A2) to be outputted from a signal output section 105 in accordance with the fetched data. Main clocks from the CPU section 102 have the waveform as shown in Fig. 5B. A time count section 104 instructs the control timings when the main clocks (A2) are outputted. Each time an instruction is received, the CPU section 102 sends a set command or a reset command to the signal output section 105. This command is composed of an output control signal (A1) such as shown in Fig. 5A. Data "0" is represented by a combination of one period t of high level and one period t of low level, whereas data "l" is represented by a combination of one period t of high level and three periods 3t of low level. For example, data "0110" stored in the output data storage section 101 are converted into a signal Al shown in Fig. 5A. At the rising edge of the output control signal A1, a set command is sent to the signal output section 105, and at the falling edge thereof, a reset command is sent to the signal output section 105. The signal output section 105 outputs main clocks when it receives the set command and stops outputting them when the reset command is received. The data are outputted as the signal A3 as shown in Fig. 5C. All the processes for generating an output control signal Al from given data are executed by the CPU section 102. Accordingly, during executing these processes, the CPU section 102 cannot execute other processes. Furthermore, it requires much labor and time for obtaining software used for the execution of these processes by the CPU section, thereby resulting in an increased cost. SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal output apparatus wherein even while a signal is outputted, a CPU section can execute other processes at the same time. It is another object of the present invention to provide a signal output apparatus capable of reducing cost by eliminating the labor and time for obtaining software used for processing the output of a carrier. According to the present invention, there is provided a signal output apparatus comprising: a CPU section; output data storage means for storing an output data from said CPU section; main clock signal generating means for outputting a main clock signal; a count circuit for receiving said main clock signal and for outputting a timing signal equal to a predetermined number of said main clock signals; and signal output means, wherein said signal output apparatus further comprises: output control means for generating an output control signal comprised of "0" data and "1" data according to said output data, said "0" and "1" data being expressed by different combinations of high level period and low level period, in response to said timing signal, wherein said output control means includes: an address selection circuit for decoding an address signal output by said CPU section and selecting an address of said output data storage means, a parallel-to-serial circuit for time sequentially outputting the data in said output data storage means at an address selected by said address selection circuit, and a one-data variable counter receiving a logical AND between an output from said count circuit and an output from said parallel-to-serial circuit at said selected address and outputting said output control signal; said signal output means receiving said main clock signal and said output control signal for outputting said main clock signal intermittently in response to a level change of said output control signal. Further features of the invention appear from dependent claims 2 to 6. In particular, data to be outputted are first given from a CPU section and temporarily stored in an output data storage section. The data are then given to an output control section to generate an output control signal in accordance with the frequency of a signal given from a count section. The output control signal controls a signal output section to thereby output a signal composed of intermittent main clocks. In this case, if the CPU section executes the processes for generating an output control signal from data given by the output data storage section, it cannot execute other processes. However, since not the CPU section but the output control section executes the processes required for controlling a carrier, the CPU section can execute other processes at the same time, thereby improving the process efficiency. The output control section includes an address selection circuit, a parallel-to-serial circuit, and an output control circuit. With such hardware arrangement, cost can be reduced by eliminating labor and time for obtaining software used for the execution of such processes by the CPU section. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the structure of a signal output apparatus according to an embodiment of this invention; Fig. 2 is a circuit diagram of the signal output apparatus shown in Fig. 1; Figs. 3A to 3E show signal waveforms at various circuit portions of the signal output apparatus shown in Figs. 1 and 2; Fig. 4 is a block diagram showing the structure of a conventional signal output apparatus; and Figs. 5A to 5C show signal waveforms at various circuit portions of the signal output apparatus shown in Fig. 4. DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of this invention will be described with reference to the accompanying drawings. The structure of a wireless remote control unit as an embodiment of this invention is shown in Fig. 1. As compared with the structure of a conventional apparatus shown in Fig. 5, there are provided additional circuits including an output control section 103 between a CPU section 102 and a signal output section 105, and those circuit portions for amplifying and transmitting a signal. Data entered by an operator are temporarily stored in an output data storage section 101 under the control of the CPU section 102. When the data are to be outputted, the data is fetched not by the CPU section 102 but by the output control section 103. Upon receipt of a start command from the CPU section 102, the output control section 103 outputs an output control signal to a signal output section 105 in accordance with the period of a signal outputted from a time count section 104. Instead of the CPU section 102, the output control section 103 receives the data temporarily stored in the output data storage section 101, and executes the processes for generating the output control signal which controls the output of the signal output section 105. Accordingly, the CPU section 102 can execute other processes at the same time. A signal outputted from the signal output section 105 is amplified by an amplifier 106. The amplified signal drives an infrared light emitting diode in a transmitter section 107 to thereby output a remote control signal. A signal outputted from the remote controller may be an ultrasonic wave, electromagnetic wave or the like. A more particular circuit of the apparatus having the above-described fundamental structure will be described with reference to Fig. 2. This circuit shown in Fig. 2 corresponds to the output data storage unit section, output control section 103, time count section 104, and signal output section 105 among the circuit blocks shown in Fig. 1. The output control section 103 includes an address selection circuit provided for respective addresses of the output data storage section 101, a parallel-to-serial circuit 201 for time sequentially rearranging parallel data at each address into serial data, an AND circuit 203 for obtaining a logical AND between the outputs from the parallel-to-serial circuit and from the time count section 104, a one-data variable counter 204 for generating an output control signal, and a data counter and decoder 205. The output data storage section 101 stores (n + 1) four-bit data (n is an integer). Using the stored data, the circuit elements of the output control section 103 generate the output control signal B5 and output it to the signal output section 105. First, the data counter decoder 205 receives a start command from the CPU section 102 and an address signal of the output data storage section 101 which is then decoded. Address selection signals 500, 501, ..., 50n for selecting the addresses 0 to n are outputted to the address selection circuit 202, and parallel-to-serial signals for obtaining four-bit serial signals are outputted to the parallel-to-serial circuit 201. For example, assuming that address "0" is selected, the level of signal 500 corresponding to address "0" among the address selection signals 500 to 50n is changed to thereby open only the gate 202 of the address selection circuit 202. In addition, the levels of signals 401 to 404 are sequentially changed to open the gates 1201a, 1201b, 1201c, and 1201d of the parallel-to-serial circuit 201 in this order recited. Accordingly, the data stored in memory cells 1101a to 1101d at address "0" are serially outputted as signal 303 from the parallel-to-serial circuit 201. The time count unit 104 is supplied, from the CPU section 102, with a main clock signal B1 (Fig. 3A) having a period T as shown in Fig. 3. The time count section 104 generates a signal B2 (Fig. 3B) having the period 4T and supplies it to the AND circuit 203. The AND circuit 203 obtains a logical AND between the signal B2 and signal 303 from the gate 1202 of the address selection circuit 202. This logical AND is sent as a data signal 304 to the one-data variable counter 204. Accordingly, the data signal corresponding to the period 4T of the signal B2 is supplied to the one-data variable counter 204. The one-data variable counter 204 converts the data signal 304 into an output control signal B5 (Fig. 3E) which controls the output of the signal output section 105. The data signal 304 of "1" is converted into a signal B3 shown in Fig. 3C having four periods (16T) of the signal B2 including one period (4T) of high level and three periods (12T) of low level. The data signal 304 of "0" is converted into a signal B4 shown in Fig. 3D having two periods (8T) of the signal B2 including one period (4T) of high level and one period (4T) of low level. The converted output control signal B5 and the clock signal B1 from the CPU section 102 are supplied to an AND gate 105a to output the logical AND which is a signal 307. For example, it is assumed that data "1010" are stored in respective memory cells of the data storage section 101 at address "0" and data "0111" are stored at address "1". In outputting these data serially, the gates of the parallel-to-serial circuit 201 and address selection circuit 202 are controlled by the signals from the data counter and decoder 205 as described previously. First, the data at address "0" are sequentially outputted to the one-data variable counter 204 as a signal at section a of the output control signal B5 shown in Fig. 3E. A carrier output controlled or modulated by the signal B5, i.e., a signal 307 (B6), is outputted from the signal output section 105. After completion of outputting the data at address "0", the gates of the parallel-to-serial circuit 201 and address selection circuit 202 are controlled by the data counter and decoder 205. Accordingly, the data "0111" stored at address "1" are sequentially outputted to the one-data variable counter 204 as a signal at section b of the output control signal B5 shown in Fig. 3E. A carrier controlled or modulated by the signal B5, i.e., a signal 307, is outputted from the signal output section 105. In the above manner, the data at addresses "0" to "n" in the data storage section 101 are sequentially outputted. According to this embodiment, the processes necessary for the data output are executed not by the CPU section but by the output control section constructed of the address selection circuit 202, parallel-to-serial circuit 201, AND circuit 203, one-data variable counter 204, and data counter and decoder 205. Accordingly, the CPU section 102 is released from such signal output processes and can execute other processes at the same time, thereby improving the process efficiency. Furthermore, although software for the execution of such processes by the CPU section must be provided with much labor and time, such labor and time can be eliminated by hardware processing as in this embodiment, thereby reducing the cost. The above embodiment has been given as one example and is not intended to limit the scope of the present invention. For example, a circuit different from that shown in Fig. 2 may also be used. The output control section in particular may take various forms with similar advantageous effects if only it can generate the control signal which modulates a carrier by the stored data. Furthermore, the function of the output control section may be realized by providing another CPU section so that processes other than the signal output process can be executed at the same time. However, this case is less cost effective than the hardware arrangement of an embodiment dedicated to the signal output process. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A signal output apparatus comprising: a CPU section (102); output data storage means (101) for storing an output data from said CPU section; main clock signal generating means for outputting a main clock signal (B1); a count circuit (104) for receiving said main clock signal (B1) and for outputting a timing signal (B2) equal to a predetermined number of said main clock signals; and signal output means (105), characterized in that said signal output apparatus further comprises: output control means (103) for generating an output control signal (B5) comprised of "0" data and "1" data according to said output data, said "0" and "1" data being expressed by different combinations of high level period and low level period, in response to said timing signal, wherein said output control means includes: an address selection circuit (202) for decoding an address signal output by said CPU section and selecting an address of said output data storage means, a parallel-to-serial circuit (201) for time sequentially outputting the data in said output data storage means at an address selected by said address selection circuit, and a one-data variable counter (204) receiving a logical AND between an output from said count circuit and an output from said parallel-to-serial circuit at said selected address and outputting said output control signal; said signal output means (105) receiving said main clock signal and said output control signal for outputting said main clock signal intermittently in response to a level change of said output control signal. A signal output apparatus according to claim 1, wherein said main clock signal generating means is included in said CPU section (102). A signal output apparatus according to claim 1, wherein said count circuit (104) includes means for generating a signal obtained from said main clock signal (B1) through frequency division. A signal output apparatus according to claim 3, wherein the signal from said signal output means is a logical AND between said main clock signal (B1) and said output control signal (B5). A signal output apparatus according to claim 1, further comprising conversion means (107) for receiving said intermittent main clock signal and generating a remote control signal. A signal output apparatus according to claim 5, wherein said conversion means (107) is means for converting into infrared light.

Inventors: OKANUMA HIDEYUKI, SAGINAO KAZUTERU, OKANUMA, HIDEYUKI, SAGINAO, KAZUTERU
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H04B1
IPC codes: H03J1, H04Q9, H04B1