Bandgap reference voltage circuit

Abstract: In a CMOS bandgap reference circuit (100), the respective collectors of two lateral parasitic NPN transistors (106, 108) are connected to the two nodes of a current mirror (110). The emitter circuit of the first parasitic NPN transistor (106) includes a resistor (116), whereby the base-emitter junction current densities of the parasitic NPN transistors (106, 108) are maintained at a preselected ratio. A second resistor (118) common to the emitter circuit of both parasitic NPN transistors (106, 108) is provided, whereby the difference in base-emitter potentials between the first and second transistors has a positive temperature coefficient and the base-emitter voltage of the second parasitic NPN transistor (108) has a negative temperature coefficient so as to cancel out the above positive coefficient. The temperature independent volatage across the common resistor (118) and the base-emitter junction of the second transistor (108) is buffered by a unity gain amplifier (120). The output of the unity gain amplifier (120) is used to drive the parasitic NPN transistors (106, 108) and also comprises the reference voltage.

Description: The present invention relates to a circuit for providing a bandgap reference voltage. Reference voltage circuits are commonly used in analog to digital converters, regulated power supplies, comparator circuits and also in some types of logic circuits. A particularly useful type of reference voltage circuit is the "bandgap" reference circuit, also known as the V BE reference circuit, which aims to generate a voltage having a positive temperature coefficient with the same magnitude as the negative temperature coefficient of V BE . The value of V BE is then added to the generated voltage to cancel out the temperature dependency. One type of parasitic NPN bipolar transistor available from standard CMOS technology comprises a vertical transistor with its emitter, base and collector corresponding, respectively, to the source-drain n+ region, the p-well region, and the n- silicon substrate. The collector of such a transistor is located in the substrate, so that the transistors are suitable for use in a common collector configuration only. Fig. 1 illustrates a known reference voltage circuit 10 which makes use of vertical parasitic transistors. A voltage VCC is applied to a terminal 12, which corresponds to the substrate of the CMOS integrated circuit. Circuit ground is provided at terminal 14. A pair of transistors 6, 8 comprise parasitic NPN transistors, each of which employs the IC substrate as its collector, a P-well as its base, and an N-type drain/source region as its emitter. A pair of resistors 20 and 22, of the same value, comprise load resistors for the transistors 6, 8 respectively. A resistor 24 is connected in the emitter circuit of the transistor 6 to develop a temperature sensitive voltage across it. A differential amplifier 26 has inputs connected across the equal valued resistors 20 and 22, and provides an output voltage V REF which is fed back to drive the bases of the transistors 6, 8. As a result of this feedback, the potentials across the differential amplifier inputs at nodes 27 and 28 are equal (assuming amplifier 26 to be perfect, i.e. having infinite gain and input impedance). Even so, the current density in the emitter of transistor 6 is less than that of transistor 8 due to the voltage developed across the resistor 24. Hence the transistors 6, 8 exhibit different base-emitter potential Δ V BE given by ΔV BE =V BE8 -V BE6 = kT g ℓn( I 8 I 6 A 6 A 8 ) wherein T is absolute temperature, k is the Boltzman constant, q is the charge of an electron, and I₈/I₆, A₆/A₈ are the ratio of the current and emitter area of transistors 8 and 6 respectively. The difference in base-emitter potential Δ V BE between transistors 6 and 8 appears across the resistor 24 with a positive temperature coefficient. Since the current producing the voltage V R24 across the resistor 24 also flows through the resistor 20, Δ V BE , having a positive temperature coefficient, is imposed across the resistor 22. Since the resistors 20, 22 are matched and the respective potentials at nodes 27 and 28 are maintained equal, a positive temperature coefficient attributable to Δ V BE is also imposed across the resistor 22. Since the base-emitter voltage of transistor 8, V BE8 , is of negative temperature coefficient, the coefficient imposed on the resistor 22 can be used to offset the coefficient of V BE8 . The value of Δ V BE is set by establishing the respective emitter areas of the transistor 6, 8 at an appropriate ratio with the same I₆ and I₈, in accordance with equation (1). Temperature compensation is achieved by adjusting the values of R₂₀, R₂₂ and R₂₄. Unfortunately, ideal CMOS amplifier devices suitable for use as the amplifier 26 are not available. Practical CMOS differential amplifiers have a temperature dependent input offset voltage that reduces the effectiveness of the bandgap reference circuit 10. The effect of the input offset voltage VOS on the bandgap reference circuit 10 is given by: V REF =V BE8 +( R 20 R 24 ℓn n )V T +(1+ R 20 R 24 ) v OS The input offset voltage of a CMOS differential amplifier typically is high and a value of greater than 2 mV is common. The ratio of (1+R₂₀/R₂₄) is high also and a value of 10 is common. Applying these common values, an error of 20 mV appears at the output of the amplifier 26, which does not permit the potential at nodes 27 and 28 to be maintained at equal values. Moreover, the input offset voltage is temperature dependent. The effect of this temperature dependency on the bandgap reference circuit 10 is given by: ∂V REF ∂T = ∂V BE8 ∂T +( R 20 R 24 ℓn n ) ∂V T ∂T +(1+ R 20 R 24 ) ∂V OS ∂T It will be appreciated that the offset voltage temperature dependency term ∂V OS / ∂T is multiplied by the ratio (1+R₂₀/R₂₄), which further degrades performance of the bandgap reference 10. Several approaches have been taken in order to overcome the performance limitations of the bandgap reference 10. One approach is to improve the performance of the differential amplifier employed in the bandgap reference circuit 10, but this approach places significant restraints on the design of the amplifier 26. In any event, many of the features responsible for the temperature dependent input offset voltage also are process sensitive. Another approach is typified by United States Patent Number 4,375,595, issued 1 March 1983 to Ulmer et al. However, this and other such approaches increase circuit complexity and chip cost. Recently, parasitic lateral NPN transistors have been used in the design of improved CMOS bandgap reference circuits. Two such circuits are disclosed in Degrauwe et al., "CMOS voltage references using lateral bipolar transistors", in IEEE Journal of Solid State Circuits, Vol. SC-20, No. 6, December 1985, pp. 1151-57. As shown in Figures 7(a) and 7(b) of the Degrauwe et al. article, these circuits are lateral bipolar transistors in combination with a current mirror, an output amplifier, and a voltage controlled current source. Unfortunately, the voltage controlled current source itself is fairly complex, being implemented by five additional resistors and an additional lateral transistor. Hence the size of the bandgap circuit is increased. Yet another approach is disclosed in United States Patent Number 4,588,941, issued 13 May 1986 to Kerth et al. This approach however does not address the effect offset voltages have upon the temperature dependency of bandgap reference circuits. US 4349778 discloses a reference voltage source circuit having a current mirror including first and second sourcing bipolar transistors. The output stage comprises a single bipolar transistors configured as an emitter follower. This circuit requires an undesirably large frequency compensation capacitor. It would be advantageous if a reference circuit could be provided which does not exhibit at least some of the above disadvantageous features of known circuits. The present invention seeks to provide a relatively simple and cost effective CMOS bandgap reference circuit having an improved temperature stability, particularly with regard to the approach described in US 4,588,941 which does not address the effect offset voltages have upon the temperature dependency of bandgap reference circuits. In particular, the invention seeks to provide a bandgap reference voltage circuit that has reduced initial voltage reference error and temperature drift. According to the present invention, there is provided a bandgap voltage reference circuit having first and second bipolar transistors each having a base a collector, and an emitter, a current mirror having a first output terminal connected to the collector of the first bipolar transistor and having a second output terminal connected to the collector of the second bipolar transistor, a first resistor having a first end connected to the emitter of the first bipolar transistor and having a second end connected to the emitter of the second bipolar transistor, a second resistor having a first end connected to the emitter of the second bipolar transistor and having a second end connected to ground potential, and an amplifier having an input terminal connected to the collector of the second bipolar transistor and having an output terminal connected to the base of each of the first and second bipolar transistors, the bandgap voltage reference circuit being characterised by the current mirror having first and second cascoded MOS transistors and third and fourth cascoded MOS transistors, the first MOS transistor having its source connected to a supply voltage VCC and its drain connected to its gate, the second MOS transistor having its source connected to the drain of the first MOS transistor and its drain connected to its gate and to a collector of the first bipolar transistor, the third MOS transistor having its source connected to VCC and its gate connected to the gate of the first MOS transistor, and the fourth MOS transistor having its source connected to the drain of the third MOS transistor, its gate connected to the gate of the second MOS transistor and its drain connected to the collector of the second bipolar transistor, the amplifier having a fifth MOS transistor with its source connected to VCC and its gate connected to the gate of the first MOS transistor, a sixth MOS transistor with its source connected to the drain of the fifth MOS transistor, and its gate connected to the collector of the second bipolar transistor and its drain connected to ground potential, and a third parasitic transistor having its collector connected to VCC, its base connected to the source of the sixth MOS transistor and its emitter connected to the base of each of the first and second bipolar transistor, wherein the potential between the emitter of the transistor and ground potential comprises a reference potential. Preferably, the base-emitter junction areas of the first and second bipolar transistors and the values of the first and second resistors are selected so as to provide temperature dependence of the reference voltage ∂V REF / ∂T, in accordance with the expression: ∂V REF ∂T = ∂v BE2 ∂T + [ R 1 R 2 ℓn n ] ∂V T ∂T where V BE2 is the base-emitter junction potential of the second bipolar transistor, R₁ and R₂ are the resistivity of the first and second resistors respectively, and n is the ratio of the base-emitter area of the first bipolar transistor to the base-emitter area of the second bipolar transistor. The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a schematic diagram of a known bandgap reference circuit; Fig. 2 is a generalised schematic diagram of a bandgap reference circuit; Fig. 3 is a detailed schematic diagram of the bandgap reference circuit of Fig. 2; and Fig. 4 is a perspective view showing, in cross-section, a portion of a parasitic NPN transistor used in the bandgap reference circuit of Fig. 2. A reference voltage circuit 100 is illustrated in Fig. 2 which is suitable for fabrication according to standard CMOS processes. A supply votlage VCC is applied at a terminal 102, and circuit ground is provided at a terminal 104. A pair of transistors 106, 108 comprise parasitic lateral NPN transistors, which include respective free collectors 126, 128 and respective gates 122, 124 which are biased as described below. A current mirror 110 comprising current sources 112, 114 provides a current I112 to the NPN transistor 106 and a current I114 to the transistor 108, and maintains the magnitude of the currents I112, I114 equal. A resistor 116 is provided in the emitter circuit of the transistor 106, and a resistor 118 is provided in the emitter circuits of both transistors 106, 108. A unity gain amplifier 120 has its input connected to the collector of the transistor 108, and provides the reference voltage V REF at its output. V REF is fed back to the base of each of the transistors 106 and 108. The operation of the bandgap reference circuit 100 is as follows. The transistors 106, 108 are driven by V REF . When the transistor 106 pulls an incremental amount of current out of the source 112 of current mirror 110, source 114 provides an equal increment of current into transistor 108. Hence the current mirror 110 forces the current I112 into the collector of the transistor 106 and the current I114 into the collector of the transistor 108 to be of equal magnitude. The transistors 106, 108 are fabricated with substantially identical diffusion profiles but, because of the difference in emitter area, the current densities across the base-emitter regions of transistors 106, 108 are not equal. The different current densities result in different potentials across the base-emitter junctions of the transistors 106, 108, given by ΔV BE =V BE108 -V BE106 = [ kT g ] ℓn [ J 108 J 106 ] The difference in base-emitter potential V BE between the transistors 106, 108 appears across the resistor 116 for the following reason. Two branches connect the node at the base of the transistors 106, 108 and the node 117, and the potential across one of the branches is V BE108 while the potential across the other branch is the same of the voltage drop across the resistor 116 ("V₁₁₆") and V BE106 . Node 117 forces V R116 + V BE106 to equal V BE108 , or V R116 = V BE108 - V BE106 Since applying equation 4 to the transistors 106, 108 yields the relationship ΔV BE = V BE108 - V BE106 , it follows that V R116 equals ΔV BE . The current producing V R116 also produces a voltage drop across the resistor 118, which has a positive temperature coefficient as is evident from the sign of ΔV BE . The positive temperature coefficient attributable to ΔV BE is imposed across the resistor 118, and is effective for offsetting the negative temperature coefficient of V BE108 . The value of V REF is determined in accordance with the following expression: V REF =V BE108 +[ R 118 R 116 ℓn)] V T where n is the ratio of emitter areas of the transistors 106, 108. The appropriate ratio is established either by appropriately sizing the respective base-emitter regions or by connecting an appropriate number of identical transistors in parallel. The temperature stability of the bandgap reference 100 is given by: ∂V REF ∂T = ∂V BE108 ∂T + [ R 118 R 116 ℓn n ] ∂V T ∂T Typically, ∂V BE108 /∂T is about -2.0 mV/degree C and ∂V T /∂T is about +0.085 mV/degree C. The values of n and the ratio R₁₁₈/R₁₁₆ are selected to render ∂V REF /∂T zero, whereby a zero temperature coefficient is achieved. The detailed schematic illustration of the bandgap reference 100 shown in Fig. 3 is similar to Fig. 2, except that the current mirror 110 and the amplifier 120 are shown in greater detail. The current mirror 110 comprises a CMOS current mirror of conventional cascade design. When the parasitic NPN transistor 106 draws an incremental current through reference PMOS transistors 130, 132, the source-drain voltage of the transistor pairs 130, 134 and 132, 136 is increased equally. Hence the transistors 134, 136 produce an approximately equal increment of current into the node 137. To reduce offset in the current mirror 110, the mirror 110 is designed to be as symmetrical as possible, and the transistors 130, 132, 134, 136 are designed as large area transistors. The transistors 130, 134 are operated in the full saturation region to minimise the sensitivity to V cc variation. The amplifier 120 comprises a conventional two-stage source follower amplifier. The gate of a first stage PMOS transistor 138 is connected to the collector of transistor 108, and the drain is connected to ground. The base of the second stage, a conventional parasitic vertical NPN transistor 140, is connected to the source of the transistor 138 and provides a low output impedance at its emitter, from which V REF is taken. The collector of the transistor 140 is provided in the substrate of the chip, which is connected to the voltage VCC. An MOS transistor 139 is connected between VCC and the source of the transistor 138 so as to provide a current path therebetween. The gate of the transistor 139 is connected to the gate circuits of the transistors 130, 134 of the current mirror 110, which maintains the operation of the transistor 139 in deep saturation. For proper operation of the lateral transistors 106, 108, VCC is applied to the substrate, which forms the collectors 126, 128 of the associated vertical transistors, and the respective gates 122, 124 are biased below their threshold voltage. The latter is achieved, for example, by connecting the gates 122, 124 to ground 104, as shown, or to the emitters of the transistors 106, 108 respectively. A transistor 200, suitable for use as transistors 106, 108 is shown in Fig. 4. The transistor 200 is realised by way of a p-well CMOS process, although other CMOS processes are also suitable. A p-well 204 is provided in an n-substrate 202. A lateral parasitic NPN transistor is obtained from a concentric layout that includes a circular n+ diffusion region 206 which functions as an emitter, surrounded by a ring-like p- region 210 of the p-well 204 which functions as a base, surrounded in turn by a ring-like n+ diffusion region 212 which functions as a collector. Connection is made to the base 210 through a p+ diffusion region 208. A polysilicon gate 216 overlays the base 210 and is insulated therefrom by a gate oxide layer 218. A vertical parasitic NPN transistor is obtained from the emitter 206 and the substrate 202 using a region 214 of the p-well 204 between the emitter 206 and the substrate 202 as the base. Connection to the region 214 is made through a p+ region 208, and connection to the substrate 202 is made through a n+ doped region 220. As the lateral transistor is more important than the vertical transistor when the parasitic transistor 200 is used as the transistor 106 or 108, the length of the base 210 (i.e. gate 216) is minimised and the perimeter-to-surface ratio of the emitter 206 is maximised. Contact is made to the various regions 206, 208, 212, 216 and 220 in any suitable manner, as is well known in the art. The transistor 200 is operated as follows. Note that the collector 212 of the lateral transistor is not tied to the substrate, while the collector 220 of the vertical transistor is so tied. The lateral transistor is made operational by biasing the gate 216 far below its threshold voltage in order to create an accumulation layer in the region 210, thereby preventing MOS transistor operation between the regions 206 and 212. The base 208, emitter 206, and collector 212 are suitably biased as discussed above. The associated vertical transistor is active since the substrate (i.e. the collector 220) is tied to VCC. Typical values for the components of the bandgap reference circuit 100 are outlined below, for VCC equal to 5.0 volts and V REF equal to 1.235 volts. The transistor 106 is laid out as eight individual transistors (n=8). The transistor 108 is laid out as an individual transistor. The transistor 108 and the individual transistors, which combine to form the transistor 106, are substantially identical. The transistor 140 is realised in such a way as to provide a good drive capability. This is done by combining multiple individual transistors in parallel or by laying out the transistor with a large emitter area to boost the drive capability. The resistors 116 and 118 are p+ resistors having resistances of 1000 ohms and 7500 ohms respectively. Hence, the ratio R₁₁₈/R₁₁₆ is 7.5. The offset in the current mirror 110 is minimised by designing the mirror to be as symmetrical as possible. In addition, each transistor 130, 132, 134, 136 is designed with a large area. The bandgap reference 100 requires no trimming because there is no offset term in the reference generation circuit path. While the invention is described with respect to the embodiment set forth above, the invention should not be limited by the specific type of transistor 200 used, or to any specific resistivity values and bias voltage values.

Claims: A bandgap voltage reference circuit having first (106) and second (108) parasitic bipolar transistors, each having a base, a collector, and an emitter, a current mirror (110) having a first output terminal connected to the collector of the first (106) bipolar transistor and having a second output terminal connected to the collector of the second bipolar transistor (108), a first resistor (116) having a first end connected to the emitter of the first bipolar transistor (106) and having a second end connected to the emitter of the second bipolar transistor (108), a second resistor (118) having a first end connected to the emitter of the second bipolar transistor (108) and having a second end connected to ground potential, and an amplifier (120) having an input terminal connected to the collector of the second bipolar transistor (108) and having an output terminal connected to the base of each of the first (106) and second (108) bipolar transistors, the bandgap voltage reference circuit being characterised by the current mirror (110) having first (130) and second (132) cascoded MOS transistors and third (134) and fourth (136) cascoded MOS transistors, the first MOS transistor (130) having its source connected to a supply voltage VCC and its drain connected to its gate, the second MOS transistor (132) having its source connected to the drain of the first MOS transistor (130) and its drain connected to its gate and to a collector of the first bipolar transistor (106), the third MOS transistor (134) having its source connected to VCC and its gate connected to the gate of the first MOS transistor (130), and the fourth MOS transistor (136) having its source connected to the drain of the third MOS transistor (134), its gate connected to the gate of the second MOS transistor (132) and its drain connected to the collector of the second bipolar transistor (108), the amplifier (120) having a fifth MOS transistor (139) with its source connected to VCC and its gate connected to the gate of the first MOS transistor (130), a sixth MOS transistor (138) with its source connected to the drain of the fifth MOS transistor (139), its gate connected to the collector of the second bipolar transistor (108) and its drain connected to ground potential, and a third parasitic transistor (140) having its collector connected to VCC, its base connected to the source of the sixth MOS transistor (138) and its emitter connected to the base of each of the first (106) and second (108) bipolar transistors, wherein the potential between the emitter of the transistor (140) and ground potential comprises a reference potential. A circuit as claimed in claim 1, wherein the first (106) and second (108) bipolar transistors comprise lateral NPN transistors, and the third bipolar transistor (140) comprises a vertical NPN transistor. A circuit as claimed in claim 1 or 2 wherein the base-emitter junction areas of the first (106) and second (108) bipolar transistors and the values of the first (116) and second (118) resistors are selected so as to provide a temperature dependence of the reference voltage ∂V REF / ∂T in accordance with the expression: ∂V REF ∂T = ∂v BE2 ∂T + [ R 1 R 2 ℓn n ] ∂V T ∂T where V BE2 is the base-emitter junction potential of the second bipolar transistor (108), R₁ and R₂ are the resistivity of the first (116) and second (118) resistors respectively, and n is the ratio of the base-emitter area of the first bipolar transistor (106) to the base-emitter area of the second bipolar transistor (108). A circuit as claimed in claim 3, wherein said selected ∂V REF / ∂T is zero. A circuit as claimed in any preceding claim, wherein the base-emitter junction areas of the first (106) and second (108) bipolar transistors and the values of the first (116) and second (118) resistors are selected to provide a reference voltage V REF in accordance with the expression: V REF =V BE2 + [ R 1 R 2 ℓn n ] V T A circuit as claimed in any preceding claim, wherein the circuit portion comprising the first and second cascode CMOS amplifiers is of a symmetrical design, and the first (130), second (132), third (134) and fourth (136) MOS transistors comprise large area transistors.

Inventors: TUN-JEN CHENG FRED, TUN-JEN CHENG, FRED
Applicants: SAMSUNG SEMICONDUCTOR INC, SAMSUNG SEMICONDUCTOR, INC.
Application year: 1990
Main classification: G05F3
IPC codes: H01F27, G05F3, H01L27, H01L21