Circuit and method for conditioning erased eeproms prior to programming

Abstract: Relatively low-energy conditioning pulses are applied to the floating gates (11) of all of the cells (10) prior to programming an erased array of electrically-programmable, electrically-erasable, read­ only-memory (EEPROM) cells (10) to provide a compressed distribution of voltage thresholds.

Description: BACKGROUND OF THE INVENTION This invention relates to an EEPROM as indicated in the preambles of claims 1, 13, 15 are apparent from GB-A-2 028 615. In particular, it relates to a circuit for, and a method for, conditioning erased EEPROMs of the single-transistor type prior to applying electrical programming pulses. The electrical conditioning pulses compress the range of threshold voltages, the range resulting from erasure of the programming charges stored on floating gates of electrically-erasable, electrically-programmable read-only-memories (EEPROMs). The compressed range of erased threshold voltages permits more reliable operation of the EEPROM array after subsequent programming. EEPROM arrays are comprised of rows and columns of floating gate memory cells. Each column and row may contain hundreds of cells, all of the cells in each column having source-drain paths connected in parallel by bitlines and all of the control gates in each row connected to a wordline. Prior to first programming, or perhaps after erasure by ultraviolet light, the source-drain paths of the cells have a uniform voltage threshold Vt, perhaps 2.5 volts, because the floating gates are neutrally charged (having neither an excess of electrons nor a deficiency of electrons). That uniform threshold voltage may be increased or decreased by doping the channel region during manufacture. After programming, the source-drain paths of the programmed cells have voltage thresholds Vt distributed over a range of perhaps +6 volts to +9 volts. The distribution of threshold voltages among individual cells is caused by processing variations, including variations in thicknesses of tunnelling regions and variations in coupling ratios of the control-gate voltages to the floating gates. After electrical erasure of all of the cells, the threshold voltages Vt may be distributed over a perhaps 2-volt range, the upper and lower voltage values of the range depending on the strength of the erasing pulses. Using a lower-strength erasing pulses, the range may be from perhaps +1.5 to +3.5 volts with the majority of the cells having erased threshold voltages Vt near +2.5 volts. With higher-strength erasing pulses applied, the distribution may range from perhaps 0 to +1.5 volts with the majority of cells having erased threshold voltages Vt less than +1.0 volt. Cells with erased threshold voltages less than that set during the manufacturing process have deficiencies of electrons, or positive charges, on their floating gates. The positive charges cause the channel regions under such gates to be enhanced with electrons. As defined herein, an erased threshold voltage of zero or negative value represents a cell which is conductive with no voltage applied to its control gate. One of the problems associated with EEPROMs of the type without split gates is the difficulty of reading memory arrays after some of the cells have been over-erased. Because the channel regions of the over-erased cells are in parallel with all of the source-drain paths of other cells in a columns, inaccuracies during reading operation may occur where the stored data in those columns is short-circuited by the over-erased cells, which may be conductive because of positive charge enhancement. The problems of over-erasure may be avoided by constructing cells with pass gates, or split gates, in which the channel between source and drain comprises two series sections, one section having the control gate separated from the channel region by the gate dielectric, the second region having the floating gate separated from the channel region by the gate dielectric. However, such memory cells require more area on a silicon chip than do cells without split gates. The problem of over-erasure may also be minimized by performing multiple erasing operations, each operation increasing the erasing energy applied to the floating gate. Between each operation, the voltage thresholds of all of the cells may be checked to see that a given maximum voltage threshold is not exceeded. However, that procedure does not provide correction for any cells that may be over-erased. Alternatively, a similar procedure may be used to check between increased-energy erasing pulses to determine that the minimum erased threshold voltage does not become less than some value greater than zero. However, this does not always guarantee that the highest erased voltage threshold is low enough. The highest erased voltage threshold will determine the speed at which the memory will operate. Consequently, there is a need for a circuit and a method to improve the erased voltage threshold distribution of individual memory arrays prior to programming in order to minimize the required cell area in an integrated-circuit non-volatile memory array without sacrificing performance due to excessively high or low threshold voltages. SUMMARY OF THE INVENTION The circuit and method of this invention are specified in claims 1, 13, 15. They provide for erasure of the cells of a memory array, then for application of relatively low-energy conditioning pulses to the floating gates of the cells prior to programming the array. The circuit and method of this invention utilize the fact that the same cells that tend to erase easily (those cells having low erased threshold voltages) also tend to charge with lower energy programming pulses. Such cells may, for example, either have a thinner dielectric between floating gate and substrate or have a higher cling ratio of the control gate voltage to the floating gate. Therefore, a low-energy programming pulse will move the lower voltage thresholds through a greater increment of voltage, thereby compacting the voltage threshold distribution. In addition, the circuit and method of this invention utilize the fact that those cells having higher programmed threshold voltages also tend to have more electrons trapped within their surfaces. Therefore, the gates of such cells are at a higher negative potential with respect to cell sources, for example, and require erasing pulses of comparatively less energy to cause electrons to channel or tunnel to those sources. Narrowing, or compressing, the voltage threshold distribution is achieved by applying "soft" programming and/or erasing pulses. Where both types of pulses are used, each successive reversal of pulses may have a different energy than that of the previously applied pulses of the same type. BRIEF DESCRIPTION OF THE DRAWINGS The novel features of this invention are set forth in the appended claims. The invention, its features, and its advantages are described below in conjunction with the following drawings: Figure 1 is a representation of an array of memory cells and associated circuitry according to this invention. Figure 2(a) illustrates a possible distribution of threshold voltages of an array of memory cells after manufacture or after ultraviolet-type of erasure and before programming and illustrates a possible distribution of threshold voltages after programming. Figure 2(b) illustrates example distributions of threshold voltages of the array of memory cells after erasure. Figure 2(c) illustrates example distributions of the erased threshold voltages of the array of memory cells after conditioning using the procedures and circuitry of this invention. DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT Referring to Figure 1, an electrically-programmable, electrically-erasable, read-only-memory (EEPROM) array is shown. Cells 10 include a charge-storage means, illustrated as a floating gate 11. The control gates 12 of each cell 10 in a row are connected to wordlines 13. The cells 10 are presumed to be of the type that does not include a split gate, or a pass gate. The cells 10 of Figure 1 are shown connected in a virtual-ground type of array, although this invention applies equally to cells 10 that are connected with separate bitlines 14 for each column of sources 15 and each column of drains 16. The source-drain paths, including the channel regions 17, of each cell 10 in a column are connected in parallel. Because of the parallel connection, a conductive cell 10 in that column will short-circuit all of the other cells 10 in that column. In particular, if one of the cells 10 in a column is over-erased, the channel region 17 will be enhanced with electrons attracted by the positively charged floating gate 11, and the cell 10 will be conductive with minimal volts applied to its source-drain path. A column of cells 10 that is short-circuited by one or more over-erased cells 10 is difficult, perhaps impossible, to read if the cell is constructed without a pass gate. Programming of cells 10 is accomplished by programming circuit means 18, which is connected to wordlines 13 and bitlines 14 of the array through peripheral circuitry 19. Peripheral circuitry 19 includes logic circuitry for connecting various inputs and outputs to the wordlines and bitlines of the array. Programming circuit means 18 and peripheral circuitry 19 cause pulsed programming electric fields adjacent surfaces or parts of the floating gates of the memory cells 10 of the EEPROM array, the electric fields directed away from the surfaces or parts of the floating gates. As illustrated by curve A of Figure 2(a), the cells 10 of an array have, in general, a uniform initial threshold voltage Vts prior to programming of those cells 10. After programming, as illustrated by curve B of Figure 2(a), the cells 10 have distributed voltage thresholds Vt above a minimum programmed voltage threshold Vtp, the distribution being caused by random processing variations. For example, some of the cells 10 may have thinner dielectrics, perhaps resulting from a process that is location dependent. Other cells 10 may have smaller-area channel regions 17, perhaps because of variations in masking size. The programmed threshold voltage distribution B is illustrated as a Gaussian or bell-shaped distribution in Figure 2(a), although actual distributions have a variety of shapes depending on particular types of processing variations. Prior to programming, cells 10 are erased by erasing circuit means 20, which is connected to wordlines 13 and bitlines 14 of the array by peripheral circuitry 19. Erasing circuit means 20 and peripheral circuitry 19 cause pulsed electric fields adjacent a surface or part of each or the floating gates of the memory cells 10 of the EEPROM array, the electric fields directed toward the surface or part of each floating gate. Erasure of the cells 10 of the same array will also result in distributed threshold voltages, caused both by processing variations and by programming voltage variations. Example distributions of erased threshold voltages are shown in Figure 2(b) as a bell-shaped curves, even though actual distributions will not necessarily have that shape. Curve C of Figure 2(b) illustrates a prior-art type of erased voltage threshold distribution in which the cells are tested between application of erasing pulses of different energy levels until all of the cells have voltage thresholds below a prescribed maximum threshold voltage Vtmax. A disadvantage of the prior-art method is that some of the cells may be over-erased in order to achieve the maximum threshold limitation, Vtmax. Curve D of Figure 2(b) illustrates a type of erased voltage threshold distribution in which cells 10 are tested between application of erasing pulses of different energy levels until all of the cells 10 have voltage thresholds above a prescribed minimum threshold voltage Vtmin. A disadvantage of this method is that some of the cells 10 may have threshold voltages that exceed the minimum programmed threshold voltage Vtp. Curve E of Figure 2(b) illustrates an extreme type of erased voltage threshold distribution in which some of the cells 10 are over-erased and in which some of the cells 10 remain programmed. In accordance with this invention, the magnitudes of the erased threshold voltages are adjusted by programming circuit means 18, and perhaps also by erasing circuit means 20, to result in a compressed distribution of threshold voltages. The mean threshold voltage may be different than the initial threshold voltage Vts set during processing by doping of the channel regions. As illustrated by curve C′ of Figure 2(c), application of low-energy pulsed conditioning electric fields by programming circuit means 18 has changed the erased voltage distribution of curve C of Figure 2(b), increasing the threshold voltages of cells with enhanced channels 17 and with lower threshold voltages to result in a more compact erased threshold voltage distribution. As discussed above, the shape of curve C′ may, in practice, different from the illustrated bell shape. The conditioning pulses are generally applied between the wordlines 13 and bitlines 14 of the array and result in pulsed conditioning electric fields that are directed away from a surface or part of each floating gate 11. Similarly, as illustrated by curve D′ of Figure 2(c), application of low-energy pulsed conditioning electric fields by erasing circuit means 20 has changed the erased voltage distribution of curve D of Figure 2(b), decreasing the threshold voltages of programmed cells and of cells with higher erased threshold voltages to result in a more compact erased threshold voltage distribution. The conditioning pulses are generally applied between the wordlines 13 and bitlines 14 of the array and result in pulsed conditioning electric fields that are directed toward a surface or part of each floating gate 11 of the array. As illustrated by curve E′ of Figure 2(c), application of alternating low-energy conditioning pulses by programming circuit means 18 and by erasing circuit means 20, in either order, has changed the erased voltage distribution of curve E of Figure 2(b) to a compact shape that has eliminated both programmed and over-erased cells 10. The relatively low-energy conditioning pulses applied between wordlines 13 and bitlines 14 may have a voltage, or a current, that is perhaps 90% or less of that normally used to program all of the cells 10 of the array to a voltage threshold above Vtp. For example, if the voltage of the pulses normally used to program, or erase, the cells 10 of the array is +20 volts, conditioning voltage pulses of perhaps +15 volts might be applied to the control gates 12 of all of the cells 10 of the array prior to programming, assuming that the pulse length is the same. As is well-known, a part of the voltage comprising the 15 or 20 volt pulses may be applied to the sources 15 or to the drains 16 prior to application of the conditioning voltage pulses to the control gates 12. As is also well-known, a fraction of the pulse energies applied between the control gates 12 and the source-drain paths of cells 10 is coupled to the floating gates 11. The relative energy levels of the conditioning pulses, as compared to the programming and/or erasing pulses, may be controlled by current-limiting circuitry or by pulse-length circuitry, or by other means of controlling energy-related product of voltage, current and time. For example, if the pulse length of the programming, erasing and conditioning pulses is the same, it may be desirable to include circuitry in programming circuit means 18 and erasing circuit means 20 that causes the product of the current and voltage of the conditioning pulses to be less than perhaps 80% of the product of the voltage and current of the programming and/or erasing pulses. Similarly, if the same voltage or current is to be used for programming, erasing and conditioning pulses, it may be desirable to include circuitry than limits the length of the conditioning pulses to less than perhaps 80% of the length of the programming and erasing pulses. Of course, circuitry may be included to change the relative energy levels of the conditioning pulses by changing the voltage, the current and the length of the conditioning pulses such that the product of the three factors is less than perhaps 80% of the product of the three factors for the programming and/or erasing pulses. After the cells 10 have been conditioned, individual cells may be programmed. The voltage thresholds of the programmed cells 10 will again be distributed over a range, perhaps of shape illustrated by curve B of Figure 2(a). Prior to performing the erasing operations described herein, it is better practice to program all of the cells 10 using programming circuit means 18. While this invention has been described with respect to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Upon reference to this description, various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art. It is contemplated that the appended claims will cover any such modifications or embodiments that fall within the scope of the invention.

Claims: A method for conditioning an EEPROM array prior to programming said array, the method comprising: erasing the memory cells of said array by causing pulsed erasing electric fields adjacent the floating gates of each of said cells of said array, said erasing electric fields directed toward said floating gates, characterized by conditioning all of said cells by applying pulsed conditioning electric fields adjacent parts of said floating gates of said cells, said pulsed conditioning electric fields having less field energy than the energy of pulsed electric fields used for programming or erasing said cells of said memory array. The method of Claim 1 wherein said pulsed conditioning electric fields are directed away from said floating gates. The method of Claim 1 wherein said pulsed conditioning electric fields are directed toward said floating gates. The method of Claim 1 wherein said pulsed conditioning electric fields are alternately directed toward and away from said floating gates. The method of Claim 1 wherein said pulsed conditioning electric fields are alternately directed away from and toward said floating gates. The method of Claim 1 wherein all of said cells are programmed prior to erasing all of said cells. The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is caused by a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array. The method of Claim 1 wherein the field energy of each of said conditioning pulsed electric fields is caused by a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array and wherein the voltage of said pulsed voltage is less than 90% of the pulsed voltage used to program individual cells of said memory array. The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is caused by a pulsed current applied between a wordline of said memory array and a bitline of said memory array. The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is caused by a pulsed current applied between a wordline of said memory array and a bitline of said memory array and wherein the current of said pulsed current is less than 90% of the pulsed current used to program individual cells of said memory array. The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is determined by the length of a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array. The method of Claim 1 wherein the field energy of each of said pulsed conditioning electric fields is determined by the length of a pulsed voltage applied between a wordline of said memory array and a bitline of said memory array and wherein the length of said pulsed voltage is less than 80% of the length of the pulsed voltage used to program individual cells of said memory array. An electrically-erasable, electrically-programmable, read-only-memory array, comprising: rows and columns of memory cells, wherein all of the memory cells in a column are connected to bitlines and wherein all of the memory cells in a row are connected to a wordline, wherein each said memory cell has charge-storing means insulated from said wordline connected to said memory cell and insulated from each of said bitlines connected to said memory cell, wherein memory storage in said cell is determined by low and high voltage thresholds between bitlines connected to said cell, and wherein an initial low voltage threshold is set during manufacture of said cell; programming circuit means for providing programming voltages to said charge-storing means via said wordlines and bitlines; erasing circuit means for providing erasing voltages to said charge-storing means via said wordlines and bitlines; characterized in that said programming circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of a programming pulse for programming all of said memory cells. The array of Claim 13 wherein said erasing circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of an erasing pulse for erasing all of said memory cells. An electrically-erasable, electrically-programmable, read-only-memory array, comprising: rows and columns of memory cells, wherein all of the memory cells in a column are connected to bitlines and wherein all of the memory cells in a row are connected to a wordline, wherein each said memory cell has charge-storing means insulated from said wordline connected to said memory cell and insulated from each of said bitlines connected to said memory cell, wherein memory storage in said cell is determined by low and high voltage thresholds between bitlines connected to said cell, and wherein an initial low voltage threshold is set during manufacture of said cell; programming circuit means for providing programming voltages to said charge-storing means via said wordlines and bitlines; erasing circuit means for providing erasing voltages to said charge-storing means via said wordlines and bitlines; characterized in that said erasing circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of an erasing pulse for erasing all of said memory cells. The array of Claim 15 wherein said programming circuit means conditions said memory cells by applying a conditioning pulse having less energy than that of a programming pulse for programming all of said memory cells.

Inventors: MCELROY DAVID J, MCELROY, DAVID J
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1990
Main classification: G11C16
IPC codes: G11C16, G11C17