Photoelectric conversion apparatus

Abstract: A photoelectric conversion apparatus includes a photoelectric conversion element, a first storage unit for storing a signal from the photoelectric conversion element, a second storage unit for storing noise from the photoelectric conversion element, a buffer unit for buffering output signals from the first and second storage units, a capacitor unit connected to the buffer unit, and a resetting unit connected to both sides of the capacitor unit.

Description: The present invention relates to a photoelectric conversion apparatus and, more particularly, to a photoelectric conversion apparatus for removing noise included in a signal photoelectrically converted by a photoelectric conversion element. In a conventional photoelectric conversion apparatus, when a signal photoelectrically converted by a photoelectric conversion element is to be read out, an unnecessary component such as a dark signal or a drive noise from the photoelectric conversion element is often included in and output together with the readout signal. The dark signal is a dark current of a photosensor, and the drive noise is noise generated when the photosensor is driven to read out a signal. In order to remove these noise components from a photoelectric conversion element, the present inventor proposed a photoelectric conversion apparatus having the following arrangement in JP-A-1-122277. Fig. 1 is a partial circuit diagram showing an arrangement of the above photoelectric conversion apparatus. Referring to Fig. 1, noise from a photoelectric conversion element is stored in a capacitor C₁ via a MOS transistor Qh₁, and a signal from the photoelectric conversion element is stored in a capacitor C₂ via a MOS transistor Qh₂. The stored noise and signal are sequentially transferred, via a buffer amplifier Qh₅ and a MOS transistor Qh₉, to an output signal line AL by MOS transistors Qh₃ and Qh₄ controlled by pulses  A and  B , respectively. Thereafter, the noise is removed from the signal. Since a signal and noise are passed through the same amplifier Qh₅ to remove the noise such as fixed pattern noise from the signal, noise from the photoelectric conversion element and offset noise generated by the amplifier can be simultaneously removed. The present inventor also proposed a photoelectric conversion apparatus having the following arrangement in JP-A-1-245769 and EP-A-0302675. Fig. 2 is a partial circuit diagram showing an arrangement of the above photoelectric conversion apparatus. First, as shown in Fig. 2, MOS transistors Qh and Qhr are turned on, one terminal of a capacitor C₁ is grounded, and a MOS transistor Q VC is turned off, thereby floating the emitter of a photoelectric conversion element S. As a result, noise from the photoelectric conversion element is stored in the capacitor C₁ and a capacitor C V . Assume that a potential obtained in this state is Vn. A signal is stored in the base of the photoelectric conversion element S, and a pulse  VC during a storage period is raised to clear the capacitor C V . At this time, the potential changes from Vn to GND. If the transistors Qh and Qhr are kept OFF, the potential at the output side of the capacitor C₁ is -Vn. The signal from the photoelectric conversion element S is transferred to and stored in the capacitor C V . At this time, the potential rises from GND by Vs. Meanwhile, the potential at the output side of the capacitor C₁ rises from -Vn by Vs. By turning on the transistor Qh, a signal from which noise components are removed can be output. Of the above two photoelectric conversion apparatuses, however, the former photoelectric conversion apparatus must comprise high-precision and high-speed clamp circuit and sample-and-hold circuit as external circuits in order to remove noise from the photoelectric conversion element and offset noise from a point sequential signal. In addition, it is difficult to apply an IC arrangement to the entire apparatus. Furthermore, in order to incorporate these circuits in a single chip, positive and negative pulses must be used for the clamp or sample-and-hold circuit. In the latter photoelectric conversion apparatus, when an output signal is passed through a buffer amplifier, offset noise generated by the amplifier is superposed on the signal. EP-A-0260954 discloses, in Figures 5 and 20, an arrangement in which a capacitor is provided in an output circuit, so as to receive amplified versions of a noise signal and a photoelectric conversion signal placed in succession on a horizontal line. The output side of the capacitor is earthed while the input side receives a noise signal, and then the output side of the capacitor floats while the input side receives the photoelectric conversion signal, so that the output side of the capacitance provides the photoelectric conversion signal with the noise signal cancelled from it. According to the present invention there is provided a photoelectric conversion apparatus as set out in claim 1. The remaining claims set out optional features. A photoelectric conversion apparatus in an embodiment of the present invention, comprises: a photoelectric conversion element; first storage means for storing a signal from the photoelectric conversion element; second storage means for storing noise from the photoelectric conversion element; buffer means for buffering output signals from the first and second storage means; capacitor means connected to the buffer means; and resetting means connected to both sides of the capacitor means. According to the above embodiment, the output side of the capacitor means is reset to be a predetermined potential (in this case, GND) by the resetting means provided at the output side of the capacitor means, and noise from the photoelectric conversion element is transferred from the second storage means to the capacitor means via the buffer means (in this case, a potential is Vn). After the output side of the capacitor means is floated, the input side of the capacitor is reset to be a predetermined potential (in this case, GND) by the resetting means provided at the input side of the capacitor means. At this time, the potential at the input side of the capacitor means changes from Vn to GND, and that at the output side of the capacitor means changes from GND to -Vn. A signal from the photoelectric conversion element is transferred from the first storage means to the capacitor means via the buffer means (in this case, a potential is Vs). At this time, the potential at the input side of the capacitor means changes from GND to Vs, and that at the output side of the capacitor means rises by Vs from -Vn to Vs - Vn. In this manner, noise from the photoelectric conversion element can be removed. At the same time, noise from the buffer means can be removed since a subtraction is performed after both the noise components from the signal and the photoelectric conversion element are passed through the same buffer means. A photoelectric conversion apparatus in another embodiment of the present invention, comprises: a plurality of buffer means each for receiving a sensor signal via first switching means and receiving a predetermined voltage via second switching means; a plurality of output lines each connected to a corresponding one of the buffer means; a plurality of charge storage means each connected to a corresponding one of the output lines; and resetting means connected to input and output sides of each of the charge storage means. In this embodiment noise of the buffer means is removed by the following operation. The output side of the charge storage means connected in series with the buffer means is set at a predetermined potential (V GN ) by the resetting means, and the second switching means is turned on to store an electrical charge via the buffer means, thereby setting a potential at the input side of the charge storage means to be a potential (V B + V N ) obtained by adding a noise component (V N ) of the buffer means to a predetermined potential (V B ). Note that the input side of the charge storage means may be set at a predetermined potential (V I ) beforehand to obtain a potential of V B + V N + V I . In this embodiment, however, V I is set as V I = 0. The output side of the charge storage means is then opened and floated, and the first switching means is turned on to apply a signal voltage (V S + V N ) obtained by adding the noise component (V N ) of the buffer means to a signal voltage V S to the input side of the charge storage means. At this time, a potential variation at the input side of the charge storage means is represented by (V S + V N ) - (V B + V N ) = V S - V B (note that V S - V B > 0 ). Meanwhile, the potential at the output side of the charge storage means rises by V S -V B to be V GN + V S - V B in accordance with the variation at the input side. In this manner, the noise component V N generated by the buffer means is removed. The photoelectric conversion apparatus of this embodiment obtains a sensor signal from which noise generated by the buffer means is removed by using the above noise correction circuit. A subtractor used in an embodiment of the present invention, comprises: first switching means connected to a first signal source; second switching means connected to a second signal source; and capacitor means commonly connected to output sides of the first and second switching means, wherein a signal of one of the first and second signal sources is output to the capacitor means, and then a signal from the other signal source is output to the capacitor means, thereby extracting a difference signal of the signals from the first and second signal sources from an output side of the capacitor means. In the subtractor having the above arrangement, the first switching means connected to the first signal source is used to output a signal from the first signal source to the capacitor means (in this case, a potential of the capacitor means is V1), and a reference potential at the output side of the capacitor means is set to be, e.g., GND. Thereafter, the second switching means connected to the second signal source is used to output a signal from the second signal source to the capacitor means (in this case, the potential of the capacitor means is V2). As a result, a potential variation at the input side of the capacitor means becomes V2 - V1. Meanwhile, the potential at the output side of the capacitor means varies from the reference potential to V2 - V1. That is, a difference signal representing a difference between the signals from the first and second signal sources can be output from the output side of the capacitor means. Embodiments of the present invention, given by way of non-limiting example, will now be described with reference to the accompanying drawings. Fig. 1 is a partial circuit diagram showing an arrangement of a photoelectric conversion apparatus disclosed in JP-A-1-122277; Fig. 2 is a partial circuit diagram showing an arrangement of a photoelectric conversion apparatus disclosed in JP-A-1-245769 and EP-A-0302675; Fig. 3 is a schematic circuit diagram showing an arrangement of a photoelectric conversion apparatus embodying the present invention; Fig. 4 is a timing chart for explaining an operation of the photoelectric conversion apparatus shown in Fig. 3; Fig. 5 is a partial circuit diagram showing a photoelectric conversion apparatus embodying the present invention including a removing circuit for a pulse leakage component; Fig. 6 is a schematic block diagram showing an arrangement of an image reader; Fig. 7 is a circuit diagram showing an embodiment of a noise correction circuit used in the photoelectric conversion apparatus of the present invention; Fig. 8 is a timing chart for explaining an operation of the noise correction circuit shown in Fig. 7; Fig. 9 is a circuit diagram for explaining a basic arrangement of a subtractor used in an embodiment of the present invention; Fig. 10 is a timing chart for explaining an operation of the subtractor shown in Fig. 9; Fig. 11 is a circuit diagram of a photoelectric conversion apparatus showing an embodiment of the subtractor; Fig. 12 is a timing chart for explaining the embodiment of the subtractor shown in Fig. 11; Fig. 13 is a circuit diagram of a photoelectric conversion apparatus showing another embodiment of the subtractor; and Fig. 14 is a timing chart for explaining the embodiment of the subtractor shown in Fig. 13. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a photoelectric conversion apparatus according to the present invention will be described in detail below with reference to the accompanying drawings. Fig. 3 is a schematic circuit diagram showing an embodiment of a photoelectric conversion apparatus according to the present invention. As shown in Fig. 3, a photoelectric conversion element S is connected to a capacitor C N via a transistor T₁ and is connected to a capacitor C S via a MOS transistor T₂. The capacitors C N and C S are connected to a buffer amplifier Tr₂ and a MOS transistor T BC controlled by a pulse  BC via MOS transistors T H1 and T H2 controlled by a shift register. The shift register is controlled by pulses  HS ,  H1 , and  H2 . An output from the buffer amplifier Tr₂ is transferred to an output signal line SL. Note that the output signal line SL has a parasitic capacitor C H . A portion A at the output signal line SL side is reset by a MOS transistor T HBC controlled by a pulse  BC . The output signal line SL is connected to a MOS transistor T SH controlled by a pulse  H2 and a MOS transistor T HC1 controlled by a pulse  HC1 via a coupling capacitor C C . The MOS transistor T HC1 resets a portion B at the output side of the coupling capacity C C . The MOS transistor T SH is further connected to a capacitor C S and a MOS transistor T HC2 . The MOS transistor T HC2 resets a portion C at the output side of the MOS transistor T SH . An operation of the photoelectric conversion apparatus having the above operation will be described below with reference to Fig. 4. Fig. 4 is a timing chart for explaining the operation of the above photoelectric conversion apparatus. Noise from the photoelectric conversion element S is stored in the capacitor C N via the MOS transistor T₁ under the control of a pulse  T1 . A signal from the photoelectric conversion element S is stored in the capacitor C S via the MOS transistor T₂ under the control of a pulse  T2 . When the pulse  H1 goes to high level, the MOS transistor T H1 is turned on, and the noise stored in the capacitor C N is stored in the coupling capacitor C C via the MOS transistor T H1 and the buffer amplifier Tr₂. Since the pulse  HC1 is at high level and the MOS transistor T HC1 is kept ON, a potential of the portion B at the output side of the coupling capacitor C C is kept at GND. Therefore, while a potential V₂ of the portion B is at GND, a noise voltage of +Vn₁ is stored as a potential V₁ of the portion A of the output signal line SL. The pulse  HC1 is switched to low level, and the MOS transistor T HC1 is turned off, thereby floating the portion B. In addition, the pulse  BC is switched to high level, and the MOS transistor T HBC is turned on, thereby decreasing the potential of the portion A from the noise voltage of +Vn₁ to GND. At this time, a noise voltage of -Vn₁ having a polarity opposite to that of the noise voltage of +Vn₁ appears as the potential V₂ of the portion B. The pulse  BC is switched to low level, and the MOS transistor T HBC is turned off. Thereafter, by switching the pulse  H2 to high level, the MOS transistor T H2 is turned on, and the signal stored in the capacitor C S is transferred to the coupling capacitor C C via the MOS transistor T H2 and the buffer amplifier Tr₂. At this time, the potential of the portion A rises from GND to a signal voltage of Vs₁. In accordance with the potential rise in the portion A, the potential of the portion B rises by the potential Vs₁ from a noise voltage of -Vn₁ to a potential of Vs₁ - Vn₁, i.e., a potential including only signal components obtained by canceling noise voltage components. That is, the sensor noise and the buffer amplifier noise are cancelled. Since the sample-and-hold MOS transistor T SH is turned on when the voltage Vs₁ - Vn₁ appears in the portion B, a voltage V₃ appears in the portion C. By sampling and holding, a signal having a high duty ratio and free from noise components can be obtained. Fig. 5 is a partial circuit diagram showing a photoelectric conversion apparatus embodying the present invention including a pulse leakage component removing circuit. Referring to Fig. 5, when a MOS transistor or the like is pulse-driven, a pulse leakage component is generated due to capacitance division of a pulse caused by the gate capacitance or an overlap capacitance between the source (drain) and the gate of the MOS transistor and a signal line capacitance. The pulse leakage component is also generated by a parasitic capacitance between pulse wiring and a signal line. As shown in Fig. 5, such a leakage component can be removed by arranging a circuit having the same arrangement as that of a signal reading circuit in parallel with the signal reading circuit to perform differential processing. A practical arrangement of an image reader to which the present invention is applied will be described below. Fig. 6 is a schematic block diagram showing the arrangement of the image reader. Referring to Fig. 6, an original 501 is mechanically moved relative to a reading unit 505 in a direction indicated by an arrow Y. Image reading is performed by scanning in a direction indicated by an arrow X by an image sensor 504 as a photoelectric conversion apparatus of the present invention. Light from a light source 502 is reflected by the original 501, and the reflected light forms an image on the image sensor 504 through an imaging optical system 503. The image sensor 504 stores carriers corresponding to the intensity of the incident light and outputs the carriers as a photoelectrically converted image signal. This image signal is digital-converted by an A/D converter 506 and fetched as image data in an internal memory of an image processing unit 507. The fetched data is subjected to, e.g., shading correction and color correction and transmitted to a personal computer 508, a printer, or the like. When image signal transfer of X-direction scanning is finished in this manner, the original 501 is moved relatively in the Y direction, and the above operation is repeatedly performed, thereby converting the total image of the original 501 into an electrical signal and extracting the signal as image information. In the above embodiment, the present invention is applied to an image reader using a line sensor. The present invention, however, can be applied to not only a line sensor but also, e.g., an area sensor. As has been described above in detail, according to the photoelectric conversion apparatus, noise included in a signal from a photoelectric conversion element and offset noise generated by a buffer amplifier in a read system can be removed in a single chip. In addition, if a bias voltage is applied to a bipolar transistor buffer amplifier, the noise removal of a coupling capacitance system provided at the output side of the buffer amplifier allows this bias voltage to be cancelled. Furthermore, since a sample-and-hold circuit is included, a sensor signal having a high S/N ratio can be output An embodiment of a noise correction circuit according to the present invention will be described in detail below with reference to the accompanying drawings. Although an application of the noise correction circuit of the present invention is not limited to a photoelectric conversion apparatus, a photoelectric conversion apparatus will be exemplified as a suitable application. Fig. 7 is a circuit diagram showing an arrangement of the noise correction circuit used in the photoelectric conversion apparatus of the present invention. Fig. 7 shows an arrangement of a circuit for reading out a sensor signal from a photoelectric conversion unit having m pixels via a buffer amplifier as a buffer means. Referring to Fig. 7, output lines L₁, L₂, and L₃ are connected to buffer amplifiers B₁₁ to B 1n , B₂₁ to B 2n , and B₃₁ to B 3n , respectively, each corresponding to m/3 pixels. Transistors M₁₁ to M 1n ( n = m/3 ) are connected to the input sides of the buffer amplifiers B₁₁ to B 1n connected to the output line L₁, respectively. Transistors M₂₁ to M 2n ( n = m/3 ) are connected to the input sides of the buffer amplifiers B₂₁ to B 2n connected to the output line L₂, respectively. Transistors M₃₁ to M 3n ( n = m/3 ) are connected to the input sides of the buffer amplifiers B₃₁ to B 3n connected to the output line L₃, respectively. The transistors M₁₁ to M 1n , M₂₁ to M 2n , and M₃₁ to M 3n are ON/OFF-controlled by pulses ₁₁ to  1n , ₂₁ to  2n , and ₃₁ and  3n , respectively. Sensor signals V s1 to V sm of the respective signals are selected by the pulses ₁₁ to  1n , ₂₁ to  2n , and ₃₁ to  3n and output to the output lines L₁ to L₃ via the transistors M₁₁ to M 1n , M₂₁ to M 2n , and M₃₁ to M 3n and the buffer amplifiers B₁₁ to B 1n , B₂₁ to B 2n , and B₃₁ to B 3n connected to these transistors. Transistors N₁₁ to N 1n are connected to the input sides of the buffer amplifiers B₁₁ to B 1n , respectively, transistors N₂₁ to N 2n are connected to the input sides of the buffer amplifiers B₂₁ to B 2n , respectively, and transistors N₃₁ to N 3n are connected to the input sides of the buffer amplifiers B₃₁ to B 3n , respectively. The transistors N₁₁ to N 1n , N₂₁ to N 2n , and N₃₁ to N 3n are ON/OFF-controlled by pulses ₃₀ to  3n-1 , ₁₁ to  1n , and ₂₁ to  2n , respectively. A reference voltage V B can be applied to the input sides of the buffer amplifiers B₂₁ to B 2n via the transistors N₁₁ to N 1n , N₂₁ to N 2n , and N₃₁ to N 3n , respectively. Capacitors C N1 , C N2 , and C N3 are connected in series with the output stages of the output lines L₁, L₂, and L₃, respectively, and the input sides of the capacitors C N1 , C N2 , and C N3 are connected to reset power sources via transistors, M R1 , M R2 , and M R3 , respectively, so that a reset voltage V GN can be applied thereto. The transistors M R1 , M R2 , and M R3 are ON/OFF-controlled by output read pulses ₂, ₃, and ₁, respectively. The output sides of the capacitors C N1 , C N2 , and C N3 are connected to a sample-and-hold circuit (S/H circuit) via transistors M T1 , M T2 , and M T3 , respectively. The transistors M T1 , M T2 , and M T3 are controlled by the output read pulses ₁, ₂, and ₃, respectively, and the signal charges stored in the capacitors C N1 , C N2 , and C N3 are read out to the S/H circuit under the control of the output read pulses ₁, ₂, and ₃, respectively. The output sides of the capacitors C N1 , C N2 , and C N3 are connected to reset power sources via transistors M C1 , M C2 , and M C3 , respectively, so that the reset voltage V GN can be applied thereto. The transistors M C1 , M C2 , and M C3 are ON/OFF-controlled by the output read pulses ₃, ₁, and ₂, respectively. The output sides of the transistors M T1 , M T2 , and M T3 are connected to reset power sources via transistors M F1 , M F2 , and M F3 , respectively, so that the reset voltage V GN can be applied thereto. The transistors M F1 , M F2 , and M F3 are ON/OFF-controlled by the output read pulses ₂, ₃, and ₁, respectively. An operation of the noise correction circuit having the above arrangement will be described below. Fig. 8 is a timing chart for explaining an operation of the noise correction circuit. As has been described above with reference to Fig. 7, the pulses ₁, ₂, and ₃ ON/OFF-control the transistors M T1 , M T2 , and M T3 to select the output lines L₁, L₂, and L₃, respectively, and ON/OFF-control the transistors M R1 to M R3 , M C1 to M C3 , and M F1 to M F3 to reset the output lines L₁, L₂, and L₃, respectively. Pulses ₁₁, ₂₁, ₃₁, and ₃₀ are some of pulses output from a scanning circuit in synchronism with the pulses ₁, ₂, and ₃, and only one of them is output during one sensor operation cycle. With reference to a timing chart shown in Fig. 8, a noise correction read operation of an input signal V S1 to the output line L₁ will be described below. First, the transistor N₁₁ is turned on by the pulse ₃₀ to input a predetermined voltage V B to the buffer amplifier B₁₁. A the same time, the transistor M C1 is turned on by the pulse ₃ to set the output side of the capacitor C N1 at a fixed voltage V GN . Assuming that a signal including a noise component output via the buffer amplifier B₁₁ is V B + V N , the capacitor C N1 holds a potential of V B + V N . When the transistor M₁₁ is turned on by the pulse ₁₁ to input the sensor signal V S1 to the buffer amplifier B₁₁, a noise component at the same level as that obtained when the predetermined voltage V B is input via the buffer amplifier B₁₁ is generated as V S1 + V N . At the same time this signal V S1 + V N is output from the buffer amplifier B₁₁, the transistor M C1 is turned off by the pulse ₃ to float the capacitor C N1 . At this time, a signal change in the capacitor C N1 is as follows. That is, at the beginning, a potential V B + V N is held at the input side of the capacitor C N1 , while the potential V GN is held at its output side. When the signal of V S1 + V N is applied, a potential change at the input side of the capacitor C N1 is V S1 - V B , while the potential at its output side changes by V S1 - V B to be V S1 - V B + V GN , thereby removing the noise component V N generated by the buffer amplifier B₁₁. Since the transistor M T1 is kept ON by the pulse ₁, the signal having the potential V S1 - V B + V GN is input to the S/H circuit. Thereafter, the transistors M R1 and M F1 are turned on by the pulse ₂, and the potentials of the respective wiring portions are reset to prepare for next signal reading. The above series of operations are similarly performed for the output lines L₂ and L₃. As is apparent from the timing chart in Fig. 8, the output signals are supplied to the S/H circuit in the order of the pulses ₁, ₂, and ₃ and extracted as continuous signals. In this embodiment, an output line is divided into three or more lines, and scanning pulses and output read pulses of the respective lines are efficiently combined. Therefore, a noise correction operation can be performed by using the same number of pulses as that used in a circuit not having a noise correction circuit, and the signal processing can be efficiently performed within a short time period. Note that in the above embodiment, the potential V B is preferably set to be a value at which the same noise as that generated when the signal is input to a buffer amplifier is generated by the buffer amplifier. In the above embodiment, however, the potential V B may be a potential at the same level as a dark signal level of the sensor. As has been described above in detail, using the noise correction circuit, noise generated by the buffer means can be removed by a simple circuit arrangement. A photoelectric conversion apparatus using the present embodiment can prevent gain reduction in an output unit and improve a read time efficiency by using the above noise correction circuit. An embodiment of a subtractor according to the present invention will be described in detail below with reference to the accompanying drawings. Fig. 9 is a circuit diagram for explaining a basic arrangement of the subtractor used in an embodiment of the present invention. Referring to Fig. 9, this subtractor comprises a connection terminal S₁ to a first signal source, a MOS transistor M₁ for ON/OFF-controlling a signal from the first signal source by using a clock  A , a connection terminal S₂ to a second signal source, and a MOS transistor M₂ for ON/OFF-controlling a signal from the second signal source by using a clock  B . The MOS transistors M₁ and M₂ are commonly connected at a node P₁, and then to a capacitor C. The capacitor C is connected to an output amplifier A₁. A terminal of the capacitor C at the node P side is connected to a MOS transistor M₄ which is ON/OFF-controlled by a clock  C so that a charge stored in wiring and the capacitor can be reset. A terminal of the capacitor C at the output amplifier A side is connected at a node P₂ to a MOS transistor M₃ which is ON/OFF-controlled by the clock  A so that a reference potential (V R ) can be applied thereto. An operation of the subtractor having the above arrangement will be described below. Fig. 10 is a timing chart for explaining the operation of the above circuit. Referring to Fig. 10, when the pulse  A rises at a timing t0 to turn on the MOS transistors M₁ and M₃, the signal voltage V₁ from the first signal source is read out to the node P₁ and at the same time the node P₂ is reset to the reference potential (V R ). When the clock  A falls at a timing t1 to turn off the MOS transistors M₁ and M₃, the node P₂ is set in a high-impedance state. When the clock  B rises at a timing t2 to turn on the MOS transistor M₂, the signal voltage V₂ (in this case, V₂ > V₁) from the second signal source is read out to the node P₁. At this time, the potential at the node P₁ rises from V₁ to V₂, and the potential at the node P₂ rises from the reference potential V R by (V₂ - V₁) due to the capacitor C provided between the contacts P₁ and P₂. Therefore, the amplifier A₁ outputs a signal corresponding to the difference signal (V₂ - V₁). When the clock  B falls at a timing t3 to turn off the MOS transistor M₂ and the clock  C rises at a timing t4 to turn on the MOS transistor M₄, charges stored in the wiring and the capacitor at the node P₁ side are reset to prepare for next signal reading. A photoelectric conversion apparatus embodying the present invention and using such a subtractor will be described below. Fig. 11 is a circuit diagram showing an arrangement of a photoelectric conversion apparatus using the subtractor. As shown in Fig. 11, MOS transistors M₁₁ to M 1n are connected to the bases of sensor transistors Q₁ to Q n , respectively, and a voltage V BB is applied thereto under ON/OFF control of a pulse  BR . The emitters of the sensor transistors Q₁ to Q n are connected to MOS transistors M₂₁ to M 2n , respectively, and are further connected to capacitors C P1 to C Pn and capacitors C D1 to C Dn via MOS transistors M₃₁ to M 3n and MOS transistors M₄₁ to M 4n , respectively. The MOS transistors M21 to M2n are ON/OFF-controlled by a pulse  VRS so that a voltage V VR can be applied to the emitters of the sensor transistors Q₁ to Q n respectively. The MOS transistors M₃₁ to M 3n are ON/OFF-controlled by a pulse  TP , and the MOS transistors M₄₁ to M 4n are ON/OFF-controlled by a pulse  TD . The capacitors C P1 to C Pn and the capacitors C D1 to C Dn are connected to MOS transistors M₅₁ to M 5n and MOS transistors M₆₁ to M 6n via buffers B₁₁ to B 1n and buffers B₂₁ to B 2n , respectively. The gates of the MOS transistors M₅₁ and M₆₁, M₅₂ and M₆₂, ..., M 5n and M 6n are commonly connected and sequentially scanned by a shift register. By sequentially controlling the shift register, the signals stored in the capacitors C P1 and C D1 , C P2 and C D2 , ..., C Pn and C Dn are transferred onto horizontal transfer lines ℓ₁ and ℓ₂. The horizontal transfer lines ℓ₁ and ℓ₂ are connected to a subtractor constituting unit X. Note that the subtractor constituting unit X is equivalent to the subtractor described above except that the reference potential V R is GND in the unit X. In the subtractor constituting unit X, the same reference symbols as in the above subtractor denote the same parts and a detailed description thereof will be omitted. Fig. 12 is a timing chart for explaining an operation of the above circuit. At a timing t1, a clock  TP rises to turn on the MOS transistors M₃₁ to M 3n , and storage end timing signals (including fixed pattern noise) are simultaneously transferred to the temporary storage capacitors CP1 to CPn for all the pixels. When the clock  TP falls to turn off the MOS transistors M₃₁ to M 3n at a timing t2 and a clock  BR falls to turn on the transistors M₁₁ to M 1n at a timing t3, the base potentials of the sensor transistors Q₁ to Q n are reset to be V BB for all the pixels (this is called a perfect reset operation). When the clock  BR rises to turn off the transistors M₁₁ to M 1n at a timing t4 and a clock  VRS rises to turn on the transistors M₂₁ to M 2n at a timing t5, the emitter potentials of the sensor transistors Q₁ to Q n are reset to be V VR (this is called a transition reset operation). From a timing t6 to a timing t7 during this transition reset operation, a clock  TD rises to turn on the transistors M₄₁ to M 4n , and the potential at the end of the transition reset operation, i.e., the potential at the start of the storage operation is transferred to the capacitors C D1 to C Dn . Storage of new signals into the sensor transistors Q₁ to Q n is started at the timing t7, and the storage end timing signals (including the fixed pattern noise) transferred to the capacitors C P1 to C Pn and C D1 to C Dn and storage operation start timing outputs are sequentially output via the buffers B₁₁ and B 1n , the MOS transistors M₅₁ to M 5n , the horizontal transfer line ℓ₂, the buffers B₂₁ to B 2n , the MOS transistors M61 to M6n, and the horizontal transfer line ℓ₁, respectively. An output operation of the storage end timing signal (including the fixed pattern noise) and the storage start timing output is performed as follows. That is, the shift register applies a clock ₁ to the MOS transistors M₅₁ and M₆₁, and carriers of the capacitors C P1 and C D1 are read out onto the horizontal transfer lines ℓ₂ and ℓ₁ via the buffers B₁₁ and B₂₁, respectively. By using the subtractor of the present invention described above, a differential signal obtained by subtracting a dark output from an optical signal is extracted. Since the clock  A is at high level during the first half of the readout operation, i.e., between timings t8 to t9, the MOS transistors M₁ and M₃ are in an ON state. Therefore, the potentials at the nodes P₁ and P₂ are GND which is an output level upon storage start. Since the clock  B is at high level during the second half of the readout operation, i.e., between timings t9 to t10, the MOS transistor M₂ is in an ON state, and the potential at the node P₁ changes from V N to V S+N (storage end timing signal level). At this time, since the node P₂ is in a floating state, the potential at the node P₂ rises from the GND level by the potential rise (V S ), and this level is finally output. Thereafter, at a timing t10, the clock ₁ from the shift register goes to low level and the clock  C rises. In the first half (timings t10 to t11) of the clock  C , the clock  A goes to high level to turn on the transistors M₁ and M₃, and the nodes P₁ and P₂ and the horizontal transfer line ℓ₁ are reset. In the second half (timings t11 to t12) of the clock  C , the clock  B goes to high level to turn on the transistor M₂, and the horizontal transfer line ℓ₂ is reset. The above series of read operations are sequentially performed to output an optical signal for each pixel. In this case, even if the storage start timing output level varies for each pixel, only the storage end timing signal level not including the fixed pattern noise is output to the output terminal. Therefore, optical information having a high S/N ratio can be obtained. Fig. 13 is a circuit diagram showing an arrangement of another photoelectric conversion apparatus using the subtractor. Fig. 14 is a timing chart for explaining the basic arrangement of the subtractor. As shown in Fig. 13, this embodiment is a photoelectric conversion apparatus of a 4-line read system in which outputs from pixels are divided into upper and lower stages, each of which is further divided into upper and lower stages. A sensor constituting unit and a subtractor constituting unit of each line of four horizontal transfer lines are equivalent to those of the first embodiment, and detailed arrangements and operations thereof will be omitted. As shown in Figs. 13 and 14, clocks  C1 ,  C2 ,  C3 , and  C4 are sequentially scanned to output a storage start timing output and a storage end timing signal to horizontal transfer lines ℓ 1a and ℓ 2a , ℓ 1b and ℓ 2b , ℓ 1c and ℓ 2c , and ℓ 1d and ℓ 2d , respectively. Subtractor constituting units X a to X d correspond to the subtractor constituting unit X in the above embodiment shown in Fig. 11 except that no amplifier is included in these units. MOS transistors M 1a to M 4a , M 1b to M 4b , M 1c to M 4c , and M 1d to M 4d correspond to the transistors M₁ to M₄, respectively, and capacitors C₁ to C₄ correspond to the capacitor C. Outputs from nodes Q₁ to Q₄ of the subtractor constituting units X a to X d are connected to MOS transistors M 5a to M 5d which are ON/OFF-controlled by the clocks  C3 ,  C4 ,  C2 , and  C1 , respectively. The MOS transistors M 5a and M 5b are commonly connected via an amplifier A₂ to a MOS transistor M₆ which is ON/OFF-controlled by a clock  A0 . The MOS transistors M 5c and M 5d are commonly connected via an amplifier A₃ to a MOS transistor M₇ which is ON/OFF-controlled by a clock  B0 . The MOS transistors M₆ and M₇ are commonly connected to a capacitor C S and an amplifier A₄. The nodes Q₁, Q₂, Q₃, and Q₄ shown in Fig. 13 have potentials Q₁, Q₂, Q₃, and Q₄ shown in Fig. 14, respectively, and the amplifier A4 outputs V out . In the embodiment shown in Fig. 11, an optical signal is output during a 1/4 period of the clock ₁. In this embodiment shown in Fig. 13, however, the horizontal signal line is divided into four parts, and the phases of the four parts are offset by 90°C. Therefore, an optical signal continuously appears at the output terminal. In addition, a sample-and-hold function is provided by the capacitor C S . The above photoelectric conversion apparatus can be applied to the image reader as shown in Fig. 6. As has been described in detail above, by using the subtractor, a circuit can be easily integrated since a circuit constituting member such as a differential amplifier which is difficult to be integrated need not be used. Therefore, a compact apparatus can be manufactured at low cost.

Claims: A photoelectric conversion apparatus comprising: a capacitance (CC, CN, C); a plurality of photoelectric conversion devices (S, Q1 to Qn) coupled to provide signals to the input side of the capacitance (CC, CN, C); switch means (THC1, MC, M3) to connect the output side of the capacitance to a fixed potential, control means for conducting a succession of signal processing operations in each of which a first signal is applied to the input side of the capacitance while the output side is tied to the fixed potential and subsequently a second signal is applied to the input side of the capacitance while the output side is floating so as to create at the capacitance an output signal which varies from the fixed potential by the difference between the first and second signals, one of the first and second signals being a photoelectric conversion signal derived from a said photoelectric conversion device and the other being a noise signal; and further switch means (THBC, MR, M4) for connecting the input side of the capacitance to a fixed potential between the first and second signals, characterised in that the photoelectric conversion apparatus comprises a plurality of buffer amplifiers (Tr2, B) having their outputs coupled to a common output line for coupling signals from the buffer amplifiers to the input side of the said capacitance (CC, CN, C) and each having its input coupled to receive signals from a said photoelectric conversion device, whereby the said photoelectric conversion signals and the said noise signals applied to the input side of the capacitance during the signal processing operations are output from the buffer amplifiers. Apparatus according to claim 1 in which the photoelectric conversion signal and the noise signal applied to the input side of the capacitance (C) during the same signal processing operation are output by different buffer amplifiers (B). Apparatus according to claim 1 in which the photoelectric conversion signal and the noise signal applied to the input side of the capacitance (CC, CN) during the same signal processing operation are output by the same buffer amplifier (tr2, B). Apparatus according to any one of claims 1 to 3 in which the noise signal is derived from the photoelectric conversion device. Apparatus according to claim 4 in which the noise signal is a dark current signal. Apparatus according to any one of the preceding claims which comprises storage means (CN, CS; CP, CD) to store the photoelectric conversion signal and the noise signal before they are applied to the capacitance. Apparatus according to claim 3 in which the noise signal is obtained by applying a predetermined potential (VB) to the input of the buffer amplifier (B). Apparatus according to claim 7 in which the noise generated in the buffer amplifier (B) when the predetermined potential (VB) is applied is substantially the same as the noise generated in the buffer amplifier (B) when the photoelectric conversion signal from the photoelectric conversion device is applied. Apparatus according to claim 7 in which the predetermined potential (VB) is substantially the same as the dark level signal from the photoelectric conversion device. Apparatus according to any one of claims 3, 7, 8 and 9 which comprises a plurality of said capacitances, their output sides being coupled to a common output. Apparatus according to any one of the preceding claims in which the switch means (THC1, MC, M3) comprises an insulated-gate FET. Apparatus according to any one of the preceding claims in which the further switch means (THBC, MR, M4) comprises an insulated-gate FET. Apparatus according to any one of the preceding claims which is a line sensor. Apparatus according to any one of claims 1 to 12 which is an area sensor.

Inventors: HASHIMOTO SEIJI C O CANON KABU, TAKEDA MASAMI C O CANON KABUSH, UENO ISAMU C O CANON KABUSHIKI, HASHIMOTO, SEIJI, C/O CANON KABUSHIKI KAISHA, TAKEDA, MASAMI, C/O CANON KABUSHIKI KAISHA, UENO, ISAMU, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H04N5
IPC codes: H04N5