Apparatus for transferring electric charges

Abstract: A charge transferring apparatus comprising, e. g., a buried type charge coupled device in which a pair of transfer electrodes (7, 8) located at the most down­ stream point of a charge transfer direction is driven by a drive pulse (H₀) other than that (H₁,H₂) for any other pair of transfer electrodes and a potential well formed at the pair of the transfer electrodes located at the most downstream point is made shallower than that at any other pair of transfer electrodes allowing the output dynamic range of a charge transfer device to be increased for improving the output quality.

Description: BACKGROUND OF THE INVENTION: (1) Field of the Invention The present invention relates to an apparatus for transferring electric charges and, more particularly, relates to an apparatus for transferring electric charges in which the transferring electrodes are constituted by a plurality of transferring electrodes which are adjoined together in a charge transfer direction and a plurality of pairs of the electrodes are arranged along the transfer direction. (2) Background of the art Solid-state image sensing devices including charge coupled devices (CCDs) have been used for photographic elements in video cameras, still cameras, and so forth. A structure of output ports for horizontal (output) register portions in these image sensing devices has been proposed. It is necessary to enhance transferring efficiency in a transferring apparatus such as the horizontal register since the output dynamic range of the output register must be widened to some degree. It is not easy to achieve both enhanced transferring effeciency and widened output dynamic range. In other words, to provide a sharp (clearly focused, high resolution) video image with high transferring efficiency, it is necessary to deepen a whole potential of a charge transferring channel to raise a potential relative a zero potential. However, to deepen the whole potential is to narrow the dynamic range of a floating diffusion region (the floating diffusion region denotes an n ++ type semiconductor region disposed at a position corresponding to a lower side of the output port of the output register downstream of an output port electrode). That is to say, since the dynamic range of the floating diffusion region is determined according to a difference between the potentials of the dynamic range of the floating diffusion region and that of the output gate electrode, the potential difference becomes correspondingly smaller if the potential at the output gate electrode side is deepened. Hence, it is difficult to enhance the transferring efficiency without narrowing the dynamic range. If the potential of the floating diffusion region is deepened, the output dynamic range can be widened. However, it is necessary to make higher the power supply voltage applied to a precharge drain region (the precharge drain region denotes an n ++ type semiconductor region formed on a surface portion of the n type semiconductor region at a position slightly downstream and spaced apart from the floating diffusion region). If the power supply voltage (Vdd) is increased, an amplifier (the amplifier which detects and amplifies the potential of the floating diffusion electrode) would largely consume the power and would make the drain voltage applied to an MOS (Metal Oxide Semiconductor) transistor constituting the amplifier higher, to a value equal to or nearly equal to the breakdown voltage that the MOS transistor inherently provides. Due to variations in the fabrication process there might appear gaps between the transfer gate electrodes placed on top of the transfer channel of the register. These gaps result in that regions in the transfer channel are not influenced by any electrical transfer field. This has a negative impact on the transfer efficiency. SUMMARY OF THE INVENTION: It is an object of the present invention to provide a charge transferring apparatus which can widen an output dynamic range and enhance the transferring efficiency without increase in the power supply voltage. The above-described object can be achieved by providing an apparatus as specified in claim 1. The overlap of one electrode with an adjacent electrode guarantees that the whole surface of the buried n-channel is covered by at least one electrode. Thus, even when taking into account variations in the fabrication process, an increased efficiency of the transfer operation is provided since there is no gap between adjacent electrodes BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is an explanatory view of a circuit structure of an electric charge transferring apparatus according to the present invention. Fig. 2 is a model view of potential in the charge transferring apparatus shown in Fig. 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT: Reference will hereinafter be made to the drawings in order to facilitate a better understanding of the present invention. Fig. 1 shows a preferred embodiment of a charge transferring apparatus according to the present invention. In Fig. 1, numeral 1 denotes n type semiconductor substrate made of silicon. Numeral 2 denotes a P type semiconductor region formed on the semiconductor substrate 1 and mumeral 3 denotes an n type semiconductor region selectively formed on a surface of the P type semiconductor region 2. In addition, a plurality of n - type semiconductor regions 4, 4, ---, are formed on a surface of and are arranged at predetermined intervals of distances along a charge transfer direction. The n - type semiconductor regions 4, 4, ---, are called transfer regions. Storage regions 5, 5, -- are provided between the respective transfer regions 4, 4, ---. It is noted that an electric charge transfer channel to transfer a signal charge is formed along the transfer direction if the transfer regions 4, 4, ---, and storage regions 5, 5, --- are alternately arranged. Furthermore, a transfer electrode 7 and storage electrode 8 are formed on each transfer region 4 and each storage region 5 via an insulating layer 6 made of ,e.g., SiO 2 . Each pair of transfer electrodes (denoted by portions attached with H o , H 1 , and H 2 ) is constituted by one transfer electrode 7 and one storage electrode 8 installed at downstream of the corresponding transfer electrode with respect to the transfer channel. Each transfer electrode 7 and storage electrode 8 are electrically interconnected, constituting one transfer electrode pair as shown in Fig. 1. Each pair of the transfer electrodes receives one bi-phase drive pulse H o , H 1 , and H 2 . An n ++ type semiconductor region selectively formed on the surface portion of the n type semiconductor region 3 is formed as a floating diffusion region 10 placed at a position on the n type semiconductor region downstream of the output gate electrode 9. A precharge drain region 11 is constituted by the n ++ type semiconductor region formed on the surface of the n type semiconductor region 3 and is placed at a position slightly spaced apart from and downstream of the floating diffusion region 10. The precharge drain region 11 receives a power supply voltage of, for example, plus twelve (+12) volts, or a multiple thereof. A precharge gate electrode 12 is formed on a portion between the floating diffusion region 10 and precharge drain region 11 via the insulating layer 6. The precharge gate electrode 12 receives a precharge gate pulse the voltage of which varies in synchronization with the bi-phase drive pulses H 1 and H 2 . An amplifier 13 is provided to detect and amplify the potential at the floating diffusion region 10. It is noted that, in the preferred embodiment, the pair of the transfer electrodes 7 and 8 adjacent to the charge detecting portion constituted by the floating diffusion region 10 and amplifier 13 is electrically separated from the other transfer electrodes and is driven by an exclusive drive pulse H o . The drive pulse H o is in the same phase as the drive pulse H 1 (,i.e., 5 volts). The voltage applied to the storage regions 5, 5, --- is the same as that of the drive pulse H 1 when the signal electric charge is stored in the respective storage regions. However, in the preferred embodiment, the voltage, when the signal electric charge is swept out, (,i.e., - 4 volts) is set to several volts lower than the drive pulse H 1 (,i.e., zero volts). That is to say, the swing range of the voltages of the exclusive drive signal H o becomes larger than those in a previously proposed transferring apparatus. The potential applied to the output gate electrode 9 is not, e.g., +2 volts as in the previously proposed charge transferring apparatus but indicates a value in the vicinity of 0 volts, as is shown in Fig. 2, which is about 2 volts lower than that in the previously proposed charge transferring apparatus. Hence, according to such a construction of a charge transferring apparatus, the potential well of the output gate is about 2 volts lower (shallower) than in the previously proposed charge transferring apparatus. In addition, the potential well of the pair of the transfer electrodes 7, 8 located at the most downstream point of the transfer channel and adjacent to the charge detecting portion 10 when sweeping out the charge in the storage region 5 and transfer region 4 is also about 2 volts shallower than that in the previously proposed charge transferring apparatus. Hence, without increase in the power supply voltage, the output dynamic range can be widened. Furthermore, if an impurity concentration in the transfer regions 4 and storage regions 5 is properly set, it is possible to widen the output dynamic range properly, deepening the whole potential well. This makes a transfer electric field stronger. Hence, the transferring efficiency can be enhanced, assuring the output dynamic range to some degree. A sharp and clear output waveform can, thus, be provided. In the preferred embodiment described above, the present invention is applicable to bi-phase drive type floating diffusion amplification (FGA) charge transferring apparatus. However, the present invention can be applied to bi-phase or quadruple-phase type CCDs provided that they are buried type CCDs (BCCDs). In addition, the present invention can be applied to floating gate amplifying type charge transferring devices. As described hereinabove, since the pair of transfer electrodes located adjacient to the charge detecting portion is driven by a drive pulse different from other pairs of transfer electrodes and the potential well of the last pair of the transfer electrodes, when the signal electric charge is transferred to the output gate portion at the last pair of the transfer electrodes, is made shallower than other pairs of transfer electrodes, the output dynamic range can be widened without increase in the power supply voltage, and the potential well in the transfer channel can wholly be deepened so that transfer efficiency can be improved. It will fully be appreciated by those skilled in the art that the forgoing description has been made in terms of the preferred embodiments and various changes and modifications may be made without departing from the scope of the present invention which is to be defined by the appended claims.

Claims: A charge transfer apparatus, comprising: a) a plurality of electrodes aligned in a charge transfer direction including a plurality of first electrodes (8, 8, 8) storing signal charges and a plurality of second electrodes (7, 7, 7) transferring the signal charges downstream in the charge transfer direction, each of said first electrodes being electrically interconnected to a corresponding second electrode to form first, second and third electrode pairs, the electrode pair at the most downstream point being a first electrode pair which is electrically separated from the second and third electrode pairs; b) a charge detection portion (10, 13) adjacent to the first electrode pair; c) an output gate electrode (9) provided between the first electrode pair and the charge detecting portion; and d) a drive pulse generator for generating a first exclusive drive pulse (H 0 ) for the first electrode pair and second and third drive pulses (H 2 , H 1 ) for the second and third electrode pairs, respectively, wherein the voltage swing of said first drive pulse (H 0 ) is larger than the voltage swing of the second drive pulse (H 1 ), so that a potential well formed at the first electrode pair is shallower than that of the third electrode pair, and said first drive pulse (H 0 ) and is in phase with the third drive pulse (H 1 ) and in opposite phase with the second drive pulse (H 2 ), characterized in that a portion of said second electrodes (7, 7, 7) respectively being adjacent to one of said first electrodes (8, 8, 8) overlaps vertically with the adjacent first electrodes (8, 8, 8). A charge transfer apparatus according to claim 1, wherein each of said first electrodes (7) is formed on a storage region of an n type semiconductor region (4) via an insulating layer (6), each of said second electrodes (8) is formed on a transfer region (5) of n - type semiconductor region located between each storage region of the n type semiconductor region (4). A charge transfer apparatus according to claim 1 or 2, further including an output gate electrode (12) formed between said first electrode pair (7, 8) and said charge detecting portion (10, 13) and said output gate electrode (12) receiving a zero-volt potential. A charge transfer apparatus according to anyone of claims 1 to 3, wherein the first drive pulse (40) applied to said first electrode pair has a higher voltage than the zero-voltage potential when the storage region stores signal charges and a lower voltage than the zero-voltage potential when the transfer region sweeps out the signal charges. A charge transfer apparatus according to anyone of claims 2 to 4, wherein said transfer region and storage region are formed on a surface of a p type semiconductor region (2) formed on an n type semiconductor substrate (1). A charge transfer apparatus according to anyone of claims 3 to 5, wherein the charge detecting portion (10, 13) comprises an n ++ type semiconductor region (11) located at downstream of and adjacent to the output gate electrode (12) and an amplifier (13).

Inventors: KUMESAWA TETSURO, MATSUI HIROMICHI, KUMESAWA, TETSURO, MATSUI, HIROMICHI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: G11C19
IPC codes: H01L29, H01L21, G11C19, H01L27