An amplifier circuit

Abstract: An amplifier circuit comprises first to third amplifying stages (10,12,14), a constant current source (18) and a feedback circuit (16). The minimum value of current flowing through the output-stage transistor of the amplifier circuit is limited chiefly by the action of the feedback circuit (16) so as to prevent the output-stage transistor from becoming cut off even when an excessive input signal is applied. This will realize high-speed circuit operation. Also, a minimum value of current flowing through the output-stage transistor is limited so as to prevent an excessive output current. This will realize protection of the amplifier circuit against overcurrent.

Description: The present invention relates to an amplifier circuit for high-speed operation, which is protected from excess current. Recently, there has been increasing demand for a high-speed large-scale integrated circuit which is capable of handling a large current for driving a peripheral circuit. Demand exists for an analogue LSI as well as a digital LSI. It is necessary to speed up the operation of an analogue circuit and to drive it with a large current. Thus, an amplifier such as an operation amplifier must be speeded up or subjected to a large current drive. It is necessary to drive the analogue circuit with a large current. Thus, the LSI itself and the peripheral circuit must be protected from an excess current upon an excess load such as a load short-circuit by a current-limiting function provided to the LSI itself or to the peripheral circuit. Figure 1 shows an example of a differential amplifier circuit (such as a comparator) composed of a CMOS. T 1 and T 2 are a pair of differential N-channel driving transistors and T 3 and T 4 form a current mirror circuit by using a P-channel load transistor. T 5 is a P-channel transistor in the output stage and I 1 and I 2 are constant current sources. +IN and -IN, respectively, are the non-inverting and inverting inputs, and OUT is the output. In this differential amplifier circuit, T 1 turns on and T 2 turns off when -IN > +IN. Thus, the voltage level of node N 3 then increases, thereby turning T 5 off and providing the output OUT with L level. Conversely, T 1 turns off and T 2 turns on when -IN < +IN. Thus, the voltage level of node N 3 decreases, thereby turning T 5 on and providing output OUT with H level. When the transistor operates in saturation region, the above recited ON state means that a current larger than the standard operating point current is caused to flow and the OFF state means that a current smaller than the standard operating point current is caused to flow. As shown in Figure 2A, when an excess difference input voltage V (-IN) - V (+IN) is applied to this circuit, T 1 turns on and T 2 turns off, thereby enabling transistor T 1 to cause a whole output current of a constant current source I 1 to flow and enabling transistor T 2 to cause a current I T2 to be 0. The current of transistor T 1 is equal to that of transistor T 3 , and T 3 and T 4 form a current mirror circuit. Thus, the current of T 4 is proportional to the current of T 3 (the current of T 4 is the same as the that of T 3 .) Accordingly, the current I T4 of transistor T 4 tends to increase as shown in Figure 2C, but the current I T4 can not flow as transistor T 2 is turned off. Transistor T 4 is strongly driven and the voltage drop between the drain and source becomes almost 0. Thus, the potential V N3 of node N 3 increases to the source voltage V DD . Thus, transistor T 5 turns off and the output voltage V OUT becomes equal to the voltage V SS (which is 0 Volts in this embodiment). If the excess difference input ends instantaneously as shown in Figure 2A, and thereafter the input difference becomes 0, transistors T 1 and T 2 turn on and cause I 1 /2 to flow. This I 1 /2 is equal to the current caused to flow by transistors T 3 and T 4 . Node N 3 is driven at the voltage V DD by the excess difference input. When the difference input is 0, the voltage decreases more. However, when I T4 is equal to I T2 , it takes time for node N 3 to discharge the charge therein. Thus, the potential N 3 of node N 3 gradually decreases, as shown in Figure 2D. When the voltage V N3 is less than V DD - V th (where V th is the threshold voltage of transistor T 5 ), transistor T 5 turns on, thereby causing the current I T5 to flow and voltage V OUT to increase. As stated above, if an excess input is applied to the amplifier, the internal voltage of the amplifier deviates from its normal operation and takes time to be restored. Thus, it can not perform a normal operation within a restoring period, and high-speed operation is not achieved. To solve this problem, the prior art is provided with the countermeasure shown in Figure 3. In Figure 3A, diodes D 1 and D 2 of reverse parallel connection are connected between nodes N 2 and N 3 , thus limiting the amplitude of the potential of node N 3 and tending to produce high-speed operation. The limitation of the amplitude when the potential of node N 3 tends to increase to the voltage V DD , can only be performed by diode D 1 . In Figure 3B, the current sources I 3 and I 4 are inserted between the nodes N 2 to N 3 and the low potential side source V SS to prevent transistors T 3 and T 4 from being in a non-current state when transistors T 1 or T 2 are cut off by the excess input and to prevent the potential increase in nodes N 2 and N 3 from being excessive. In Figure 3C, transistors T 6 and T 7 are connected between the nodes N 2 and N 3 and node N 1 , and transistors T 6 and T 7 are controlled by -IN and +IN so that T 7 is on when T 1 is off and T 6 is on when T 2 is off, thereby preventing transistors T 3 and T 4 from being in a non-current state and preventing an excess potential increase in nodes N 2 and N 3 . The same parts are represented by the same symbols throughout the all drawings. However, in the circuit shown in Figure 3A, the CMOS IC should be formed of a MOS diode. When the CMOS IC is formed of junction type diodes D 1 and D 2 , a parasitic thyristor is formed, causing latch up phenomena. The circuits shown in Figures 3B and 3C do not perform an amplitude limitation directly. Thus, they can not achieve a sufficient effect and can not perform a sufficient high speed operation. Next, the excess current is discussed. If a load short-circuit occurs, an excess output current flows and the transistor in the output stage is destroyed. In a small-current FET, a load short-circuit does not cause a great problem as the load current is suppressed because of the saturation characteristics of a small current FET, but a circuit having a large current-driving capability has the problem of a load short-circuit. Figure 4 shows an example of a circuit in which an excess current is prevented by using an emitter-follower. Q 1 to Q 6 are bipolar transistors forming a differential pair at the input stage. The non-inverting and inverting inputs +IN and -IN are applied to the bases of transistors Q 4 and Q 3 . Transistors Q 5 and Q 6 form a current mirror. I 5 - I 8 form a constant current source, bipolar transistors Q 10 - Q 12 form an output stage, Q 7 - Q 9 form the driving stage, C 1 is a phase compensation capacitor, R 1 is a current sensing resistor, D 5 - D 7 are level shifting diodes, and Q 13 is a bipolar transistor. Resistor R 1 and transistor Q 13 prevent an excess current. When the load current increases and hence the voltage drop across the resistor R 1 increases, transistor Q 13 is be turned on, and the base current of the Darlington pair Q 10 and Q 11 is bypassed. As a result, transistors Q 10 and Q 11 are driven in the direction such that they are turned off and the load current is prevented from becoming excessive. More specifically, when an external load is supplied at a current I from the output terminal OUT, the current I is mainly supplied through Q 11 and R 1 . When the current I increases and hence the voltage drop IR 1 across the resistor R 1 exceeds V BEO (the specific base-to-emitter voltage of approximately 0.6-0.7 volts) of the transistor Q 13 , the transistor Q 13 will begin to conduct. Then, the base voltage of Q 10 and hence the base voltage of Q 11 will be decreased and the emitter voltage of Q 11 and the output voltage at OUT will be subsequently decreased, thereby reducing the supply current I to the external load. Finally, the current I will be limited to a level which satisfies IR 1 ≒ 0.6 - 0.7 volts (in other words, to the extent that Q 13 begins to conduct a current). The circuit of Figure 4, which performs a current limiting function, is a bipolar transistor circuit, not a CMOS circuit. With a CMOS amplifier, a source follower does not have as low an impedance as an emitter follower of a bipolar amplifier. Thus, a CMOS circuit corresponding the the circuit of Figure 4 is not used. In a CMOS configuration, the currents of transistor T 5 and current source I 2 are made high in Figure 1, thereby providing high-current driving capability. With the system of Figure 3A adapted to speed up the operation of the CMOS amplifier, there are problems with the protection diodes D 1 and D 2 . With the systems of Figures 3B and 3C, on the other hand, a sufficient effect cannot be expected. There is a bipolar transistor amplifier sufficient for overcurrent limiting, as shown in Figure 4, but there is no satisfactory CMOS amplifier. IEEE 1987 Solid State Circuits Conference Vol.30, Feb. 1987 pages 168, 169, 385, K.-Y. Toh et al, discloses a matched impedance NMOS amplifier having a block diagram similar to Figure 5 of the attached drawings. However the aim of this circuit is to provide impedance matching and it does not address the problems dealt with by the present invention, namely overcurrent limitation and avoidance of cut-off states, by a circuit able to cope with high speeds. It is therefore an object of the present invention to provide an amplifier circuit which is adapted for high-speed circuit operation and overcurrent prevention. According to a first aspect of the present invention there is provided an amplifier circuit comprising: a first, second and third amplifying stage and a feedback circuit, characterised by the first amplifying stage comprising a first transistor having a gate or base for receiving a first input voltage and a second transistor having a gate or base for receiving a second input voltage the first transistor and the second transistor forming a differential pair of driving transistors; the second amplifying stage, comprising a third transistor connected in series with a first constant current source, located between a first power source and a second power source, the third transistor having a gate or a base connected to an output node of the first amplifying stage and outputting a voltage level in accordance with a voltage level at the output node; the third amplifying stage, comprising a fourth transistor connected in series with a second constant current source, located between the first power source and the second power source, the fourth transistor having a gate or a base connected to the output node and outputting an output current being a fixed proportion of an output current of the third transistor; and the feedback circuit comprising a fifth transistor connected between the output node and the second power source, the fifth transistor having a gate or a base connected to a first node which connects the fourth transistor and the second constant current source and being turned ON by a potential drop at the first node caused by a potential rise at the output node and operable to control the potential rise at the output node. According to a second aspect of the invention there is provided an amplifier circuit comprising: a first, second and third amplifying stage and a feedback circuit, characterised by the first amplifying stage comprising, a first transistor having a gate or a base for receiving first input voltage, a second transistor having a gate or a base for receiving a second input voltage, a seventh transistor, and an eighth transistor, in which the first transistor and the second transistor form a first differential pair of driving transistors, the seventh transistor and the eighth transistor form a current mirror circuit, the first transistor and the seventh transistor are connected in series with a fourth constant current source and are located between a first power source and a second power source, and the second transistor and the eighth transistor are connected in series with the fourth constant current source and are located between the first power source and the second power source; the second amplifying stage, comprising a third transistor connected in series with a first constant current source, and located between the first power source and the second power source, the third transistor having a gate or a base connected to an output node of the first amplifying stage which connects the second transistor and the eighth transistor and outputting a voltage level in accordance with a voltage level at the output node; the third amplifying stage, comprising a fourth transistor connected in series with a second constant current source, and located between the first power source and the second power source, the fourth transistor having a gate or a base connected to the output node and outputting a current being a fixed proportion of an output current of the third transistor; and the feedback circuit comprising a ninth transistor connected between the fourth constant current source and the connecting point of a gate or a base of the seventh transistor and a gate or a base of the eighth transistor, the ninth transistor having a gate or a base connected to a first node which connects the fourth transistor and the second constant current source and being turned ON according to a rise in potential at the first node to raise the potential at the output node when an output current of the third transistor becomes equal to or larger than a predetermined value. An embodiment of the present invention considered at the block diagram level comprises an amplifier circuit having a first amplifying stage for receiving an input signal and amplifying it to provide an output signal, a second amplifying stage for receiving the output signal of the first amplifying stage and amplifying it to provide an output signal, a third amplifying stage for receiving the output signal of the first amplifying stage and having its output terminal connected to a constant current source, and a feedback circuit connected between the junction of the third amplifying stage and the constant current source and the first amplifying stage, the ratio of an output current of the second amplifying stage to that of the third amplifying stage being fixed and the feedback circuit controlling the output of the first amplifying stage only when the potential at the junction of the third amplifying stage and the constant current source is either above or below a specified potential. For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings in which:- Figure 1 is a circuit diagram of a conventional CMOS amplifier circuit; Figures 2A through 2F are diagrams which illustrate the operation of the amplifier circuit shown in Figure 1; Figures 3A through 3C are circuit diagrams of conventional CMOS amplifier circuits adapted for high-speed circuit operation; Figure 4 is a circuit diagram of a conventional bipolar transistor amplifier circuit adapted for overcurrent protection; Figure 5 is a basic block diagram illustrating the principle of the present invention; Figure 6 is a circuit diagram of an amplifier circuit according to the first embodiment of the present invention; Figures 7A through 7H are diagrams which illustrate the operation of the amplifier circuit shown in Figure 6; Figure 8 is a circuit diagram of an amplifier circuit according to the second embodiment of the present invention; Figures 9A through 9H are diagrams which illustrate the operation of the amplifier circuit shown in Figure 8; and Figure 10 is a circuit diagram of an amplifier circuit according to the third embodiment of the present invention. As illustrated in Figure 5, the amplifier circuit of the present invention is composed of three amplifying stages 10, 12 and 14; a constant current source 18; and a feedback circuit 16. The first amplifying stage 10 receives an input signal IN and provides an output signal to the second and third amplifying stages 12 and 14. The output of the second amplifying stage 12 is used as the output OUT of the present amplifier circuit. The output of the third amplifying stage 14 is connected to inputs of the constant current source 18 and the feedback circuit 16. The output of the feedback circuit 16 is connected to the first amplifying stage 10. The second and third amplifying stages 12 and 14 are set such that their output currents are in a constant ratio. The feedback circuit 16 is adapted to control the first amplifying stage 10 only when the input signal of the feedback circuit 16 is above or below a fixed level. The first and third amplifying stages 10 and 14, the constant current source 18 and the feedback circuit 16 form a negative feedback control system. In th amplifier circuit, the input signal IN is amplified by the amplifying stages 10 and 12 to provide the output OUT, and the output of the amplifying stage 10 is controlled by the negative feedback control system including the amplifying stage 14. The output signals of the amplifying stages 12 and 14 are obtained in terms of current and the output currents are in a fixed ratio. The voltage at node N, which is the junction of the amplifying stage 14 and the constant current source 18, is determined by the difference between the output current of the amplifying stage 14 and the current of the constant current source 18. The feedback circuit 16 feeds the voltage at the node N back to the amplifying stage 10, thereby controlling the output of the amplifier 10 only when the voltage at node N is higher or lower than a fixed voltage. Assuming that the output currents of the amplifying stages 12 and 14 are I T5 and I T8 , respectively, I T5 and I T8 are related by : I T5 = A I T8 where A is a constant. Assuming that the current of the constant current source 18 is I 5 and the voltage at the node is V, V becomes high when I T8 - I 5 > 0, and low when I T8 - I 5 < 0. When V is high, the feedback circuit 16 limits the maximum value of current drawn from the output OUT, thereby preventing overcurrent or preventing the current-sinking transistor of the amplifying stage 12 from becoming cut off, thereby achieving high speed circuit operation. When V is low, on the other hand, the feedback circuit limits the maximum value of sink current, thereby preventing overcurrent or preventing the output-stage transistor of the amplifying stage 12 from being cut off, thereby achieving high-speed circuit operation. Figures 6, 8 and 10 illustrate the first, second and third embodiments of the present invention, respectively. Comparisons of these Figures with Figure 1 show that each has a P-channel transistor T 8 and a constant current source I 5 added to it. A P-channel transistor T 9 is further added to the circuit in Figure 6; an N-channel transistor T 10 to the circuit in Figure 8; and P-channel transistors T 9 and T 18 , an N-channel transistor T 10 and a constant current source I 15 to the circuit in Figure 10. T 1 through T 4 and I 1 form the amplifying stage 10 of Figure 5, T 5 and I 2 form the amplifying stage 12, T 8 and T 18 form the amplifying stage 14, and I 5 and I 15 form the constant current source 18. T 9 in Figure 6, T 10 in Figure 8 and T 9 and T 10 in Figure 10 each correspond to the feedback circuit 16 of Figure 5. The first embodiment, illustrated in Figure 6, is adapted to prevent the output-stage transistor T 5 from becoming cut off, thereby achieving high-speed circuit operation. The operation of the first embodiment is described below with reference to Figures 7A through 7H. In the circuit of Figure 6, the currents of I 2 and T 5 are normally equal when OUT is midway between V DD and V SS . Since they have the same characteristics, transistors T 5 and T 8 will conduct the same current I 2 . Since I 5 and I 2 are set such that I 5 < I 2 , the potential at node N 4 is raised to a level in the neighborhood of V DD . Therefore, T 9 is normally turned off. As in the circuit of Figure 1, when excessively different input signals such as those illustrated in Figure 7A are applied in a direction to cause V (+IN) < V (-IN) , transistor T 1 will be turned on, while transistor T 2 will be turned off. Thus, the voltage drop across T 4 decreases so that the potential at N 3 approaches V DD as transistors T 3 and T 4 of the current mirror circuit are driven to cause a current I 1 to flow. This decreases the currents of T 5 and T 8 so that the output voltage at OUT decreases immediately, as shown in Figure 7H, and after some delay the current I T8 of T 8 becomes smaller than I 5 , as shown in Figure 7E. Consequently, the potential V N4 at N 4 will also be lowered, as shown in Figure 7F. When the potential V N4 at N 4 becomes lower than the potential V N3 at N 3 by at least the the threshold voltage V th of the transistor T 9 , T 9 will begin to conduct so that current flows from N 3 to V SS . At this point the elevation of the potential at N 3 is stopped. In this stage, transistors T 8 and T 5 each conduct the current I 5 . That is, they are not in the cut-off state. Thus, when the excessive input is removed, the amplifier circuit can immediately prepare to accommodate the next input signal. In the conventional circuit illustrated in Figure 1, when an excessive input signal is applied, T 5 is placed in the cut-off state so that, even if the excessive input signal is removed, no response can be made until T 5 gets out of the cut-off state. However, the circuit of the present embodiment can attain remarkable high-speed circuit operation because T 5 and T 8 are not cut off even when an excessive input signal is applied. Thus, when the excessive input signal is removed, the circuit can immediately prepare to accommodate the next input signal. Note, that the gain factors β 5 and β 8 of transistors T 5 and T 8 are set to satisfy β 5 /β 8 = A/1, and I 5 = I 2 /A - α< I 2 /A. Here, A may be either A ≧ 1 or A ≦ 1, and α may be any value that satisfies 0 < α < I 2 /A. Next, the second embodiment, shown in Figure 8, is adapted to limit the current of the output-stage transistor T 5 to protect the circuit against overcurrent. As illustrated in Figure 8, the amplifier circuit of the present embodiment may be considered to have a configuration in which feedback is provided to an amplifier having the same arrangement as the circuit of Figure 1 through transistors T 8 and T 10 and the constant current source I 5 . In this case, the amplifier operates so as to hold its output voltage V OUT constant even if a variation occurs in a load (R L , I OUT , etc.). That is, when R L becomes small so that I OUT increases and V OUT decreases, the -IN voltage of Figure 8 (= V OUT ) also decreases. Thus, the current of T 1 (= the current of T 3 = the current of T 4 ) decreases and the current of T 2 increases. As a result, the potential at N 3 falls. Then, the current of T 5 increases, thereby preventing V OUT from decreasing. Assuming that T 8 and T 5 have the same characteristics and I 5 > I 2 , since normally I T8 = I T5 = I 2 < I 5 , the voltage of N 4 is in the neighborhood of V SS and thus T 10 is turned off. When I OUT increases, it is limited to a fixed value as shown in Figures 9A through 9G. That is, when I OUT increases and thus I T5 (= I T8 ) increases, resulting in I T8 ≧ I T5 , the potential at N 4 rises. When the potential at N 4 becomes higher than that at N 1 by at least the threshold voltage V th of T 10 , T 10 conducts, causing current to flow in T 3 and T 4 . Thus, the potential at N 3 is raised, thereby preventing the currents of T 5 and T 8 from increasing further. As a result, I OUT is limited. Thus, according to the present embodiment, satisfactory overcurrent protection can also be realized by a CMOS amplifier circuit. The third embodiment, illustrated in Figure 10, is adapted to keep the output-stage transistor T 5 from becoming cut off and to limit the current to simultaneously realize high-speed circuit operation and overcurrent protection. As shown in Figure 10, the circuit of the present embodiment combines the circuits of Figure 6 and Figure 8. That is, T 8 , T 9 , N 4 and I 5 in Figure 10 are adapted to high-speed circuit operation and correspond to T 8 , T 9 , N 4 and I 5 , respectively, in Figure 6. Also, T 18 , T 10 , N 14 and I 15 in Figure 10, are adapted to overcurrent protection and correspond to T 8 , T 10 , N 4 and I 5 , respectively, in Figure 8. The operation of the present embodiment may also be considered to be a combination of the operations of the embodiments shown in Figure 6 and Figure 8. That is, when -IN > +IN, T 5 is cut off. However, T 5 is prevented from becoming cut off by the same operation as in the circuit of Figure 6, thus enabling fast recovery. In addition, even if the output current I OUT increases, it will be limited by the same operation as the circuit of Figure 8. The above embodiments are directed to only CMOS amplifier circuits. However, the amplifier circuits of the present invention may be composed of bipolar transistors only. In this case, it is necessary only that the N-channel MOS transistors be replaced with NPN bipolar transistors and the P-channel MOS transistors be replaced with PNP bipolar transistors. In operation as well, the amplifier circuits using bipolar transistors are the same as the corresponding CMOS amplifier circuits illustrated in the drawings and described above. As described above, according to the present invention, a maximum value and/or a maximum value of current in the output stage transistor of an amplifier circuit can be limited, thereby achieving fast recovery after application of an excessive input signal. This is because the output transistor is prevented from becoming cut off and/or because the circuit is protected by output current limitation.

Claims: An amplifier circuit comprising: a first (10), second (12) and third (14) amplifying stage and a feedback circuit (15), characterised by the first amplifying stage (10) comprising a first transistor (T 1 ) having a gate or base for receiving a first input voltage (-IN) and a second transistor (T 2 ) having a gate or base for receiving a second input voltage (+IN) the first transistor (T 1 ) and the second transistor (T 2 ) forming a differential pair of driving transistors; the second amplifying stage, (12) comprising a third transistor (T 5 ) connected in series with a first constant current source (I 2 ), located between a first power source (V DD ) and a second power source (V SS ), the third transistor (T5) having a gate or a base connected to an output node (N 3 ) of the first amplifying stage (10) and outputting a voltage level in accordance with a voltage level at the output node (N 3 ) ; the third amplifying stage (14), comprising a fourth transistor (T 8 ) connected in series with a second constant current source (I 5 ), located between the first power source (V DD ) and the second power source (V SS ), the fourth transistor (T 8 ) having a gate or a base connected to the output node (N 3 ) and outputting an output current being a fixed proportion of an output current of the third transistor (T 5 ) ; further characterised by the feedback circuit (16) comprising a fifth transistor (T 9 ) connected between the output node (N 3 ) and the second power source (V SS ), the fifth transistor (T 9 ) having a gate or a base connected to a first node (N 4 ) which connects the fourth transistor (T 8 ) and the second constant current source (I 5 ) and being turned ON by a potential drop at the first node (N 4 ) caused by a potential rise at the output node (N 3 ) and operable to control the potential rise at the output node (N 3 ). An amplifer circuit according to claim 1, further comprising a sixth transistor (T 18 ) connected in series with a third constant current source (I 15 ) and being located between the first power source (V DD ) and the second power source (V SS ), wherein a gate or a base of the sixth transistor (T 18 ) is connected to the output node (N 3 ), the ratio of the output current of the sixth transistor (T 18 ) to that of the third transistor (T 5 ) is fixed, the first amplifying stage (10) further comprises a seventh transistor (T 3 ), eighth transistor (T 4 ), and fourth constant current source (I 1 ), the seventh transistor (T 3 ) and the eighth transistor (T 4 ) form a current mirror circuit, the first transistor (T 1 ) and the seventh transistor (T 3 ) are connected in series with the fourth constant current source (I 1 ) and are located between the first power source (V DD ) and the second power source (V SS ), the second transistor (T 2 ) and the eighth transistor (T 4 ) are connected in series with the fourth constant current source (I 1 ) and are located between the first power source (V DD ) and the second power source (V SS ), the feedback circuit (16) further comprises a ninth transistor (T 10 ) connected between the fourth constant current source (I 1 ) and a connection point of the gate or the base of the seventh transistor (T 3 ) and the gate or the base of the eighth transistor (T 4 ), a gate or a base of the ninth transistor (T 10 ) is connected to a second node (N 14 ) which connects the sixth transistor (T 18 ) and the fourth constant current source (I 1 ), and when the output current of the third transistor (T 5 ) becomes equal to or larger than a predetermined value, the ninth transistor (T 10 ) turns ON in accordance with a rise in potential at the second node (N 14 ) to raise the potential at the output node (N 3 ). An amplifier circuit comprising: a first (10), second (12) and third (14) amplifying stage and a feedback circuit (15), characterised by the first amplifying stage (10) comprising, a first transistor (T 1 ) having a gate or a base for receiving first input voltage (-IN), a second transistor (T 2 ) having a gate or a base for receiving a second input voltage (+IN), in which the first transistor (T 1 ) and the second transistor (T 2 ) form a first differential pair of driving transistors, the second amplifying stage (12), comprising a third transistor (T 5 ) connected in series with a first constant current source (I 2 ), and located between the first power source (V DD ) and the second power source (V SS ), the third transistor (T 5 ) having a gate or a base connected to an output node (N 3 ) of the first amplifying stage which connects the second transistor (T 2 ) and an eighth transistor (T 4 ) and outputting a voltage level in accordance with a voltage level at the output node (N 3 ); the third amplifying stage (14), comprising a fourth transistor (T 8 ) connected in series with a second constant current source (I 5 ), and located between the first power source (V DD ) and the second power source (V SS ), the fourth transistor (T 8 ) having a gate or a base connected to the output node (N 3 ) and outputting a current being a fixed proportion of an output current of the third transistor (T 5 ); further characterised by the first amplifying stage (10) further comprising a seventh transistor (T 3 ), and an eighth transistor (T 4 ) , the seventh transistor (T 3 ) and the eighth transistor (T 4 ) form a current mirror circuit, the first transistor (T 1 ) and the seventh transistor (T 3 ) are connected in series with a fourth constant current source (I 1 ) and are located between a first power source (V DD ) and a second power source (V SS ), and the second transistor (T 2 ) and the eighth transistor (T 4 ) are connected in series with the fourth constant current source (I 1 ) and are located between the first power source (V DD ) and the second power source (V SS ); and the feedback circuit (16) comprising a ninth transistor (T 10 ) connected between the fourth constant current source (I 1 ) and the connecting point of a gate or a base of the seventh transistor (T 3 ) and a gate or a base of the eighth transistor (T 4 ), the ninth transistor (T 10 ) having a gate or a base connected to a first node (N 4 ) which connects the fourth transistor (T 8 ) and the second constant current source (I 5 ) and being turned ON according to a rise in potential at the first node (N 4 ) to raise the potential at the output node (N3) when an output current of the third transistor (T 5 ) becomes equal to or larger than a predetermined value. The amplifier circuit according to claim 1, 2 or 3 in which said first amplifying stage, said third amplifying stage and said feedback circuit form a negative feedback loop. The amplifier circuit according to claim 1 or claim 2, in which said negative feedback loop is arranged to limit the minimum current flowing through the third transistor (T 5 ) contained in said second amplifying stage (12), thereby preventing said third transistor from becoming cut off. The amplifier circuit according to claim 1, claim 2 or claim 5, in which said negative feedback loop is arranged to limit the maximum current flowing through the third transistor (T 5 ) contained in said second amplifying stage (12), thereby preventing an excessive output current. An amplifier circuit according to any one of claims 1 to 6, in which transistors contained in said first, second and third amplifying stages and said negative feedback circuit are MOS transistors. An amplifier circuit according to any one of claims 1 to 6, in which transistors contained in said first, second and third amplifying stages and said negative feedback circuit are bipolar transistors.

Inventors: KOBAYASHI OSAMU, KOBAYASHI, OSAMU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H03F1
IPC codes: H03F3, H03F1