Cache miss prediction method and apparatus

Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.

Description: Field of the Invention This invention relates to the art of data processing systems which include a cache memory feature and, more particularly, to a method and apparatus for predicting memory cache misses for operand calls and using this information to transfer data from a main memory to cache memory to thereby lower the cache miss ratio. Background of the Invention The technique of employing a high speed cache memory intermediate a processor and a main memory to hold a dynamic subset of the information in the main memory in order to speed up system operation is well known in the art. Briefly, the cache holds a dynamically variable collection of main memory information fragments selected and updated such that there is a good chance that the fragments will include instructions and/or data required by the processor in upcoming operations. If there is a cache "hit" on a given operation, the information is available to the processor much faster than if main memory had to be accessed to obtain the same information. Consequently, in many high performance data processing systems, the "cache miss ratio" is one of the major limitations on the system execution rate, and it should therefore be kept as low as possible. The key to obtaining a low cache miss ratio is obviously one of carefully selecting the information to be placed in the cache from main memory at any given instant. There are several techniques for selecting blocks of instructions for transitory residence in the cache, and the more or less linear use of instructions in programming renders these techniques statistically effective. However, the selection of operand information to be resident in cache memory at a given instant has been much less effective and has been generally limited to transferring one or more contiguous blocks including a cache miss address. This approach only slightly lowers the cache miss ratio and is also an ineffective use of cache capacity. The article "Cache miss history table" published in the IBM TDB, vol. 25, no. 11B, of April 1983, pages 5978-5980, discloses that a cache can predict accesses based on the sequence of cache accesses. The history of cache misses is maintained by building and updating a cache miss history table. Each entry in the table contains a current miss address field and a next miss address field. The table is accessed by using a portion of the cache line address on which the processor missed. The information in the table is used to prestage cache lines. Thus, those skilled in the art will understand that it would be highly desirable to provide means for selecting operand information for transitory storage in a cache memory in such a manner as to significantly lower the cache miss ratio, and it is to that end that the present invention is directed. Objects of the Invention It is therefore a broad object of this invention to provide an improved cache memory in a data processing system. It is another object of this invention to provide a cache memory particularly characterized by exhibiting an improved cache miss ratio in operation. It is a more specific object of this invention to provide a cache memory incorporating circuitry for effectively predicting cache misses. In another aspect, it is an object of this invention to provide a cache memory selection process in which the cache miss ratio for operands is significantly lowered. Summary of the Invention These and other objects of the invention are achieved by a method and a special purpose apparatus in the cache memory which stores recent cache misses and searches for patterns therein, as defined in the claims. Any detected pattern is employed to anticipate a succeeding cache miss by prefetching from main memory the block containing the predicted cache miss. Description of the Drawing The subject matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, may best be understood by reference to the following description taken in conjunction with the subjoined claims and the accompanying drawing of which: FIG. 1 is a generalized block diagram of a typical data processing system employing a cache memory and therefore constituting an exemplary environment for practicing the invention; FIG. 2 is a flow diagram illustrating, in simplified form, the sequence of operations by which the invention is practiced; FIG. 3 is a logic diagram of a simple exemplary embodiment of the invention; and FIG. 4 is a logic diagram of a more powerful exemplary embodiment of the invention. Detailed Description of the Invention Referring now to FIG. 1, there is shown a high level block diagram for a data processing system incorporating a cache memory feature. Those skilled in the art will appreciate that this block diagram is only exemplary and that many variations on it are employed in practice. Its function is merely to provide a context for discussing the subject invention. Thus, the illustrative data processing system includes a main memory unit 13 which stores the data signal groups (i.e., information words, including instructions and operands) required by a central processing unit 14 to execute the desired procedures. Signal groups with an enhanced probability for requirement by the central processing unit 14 in the near term are transferred from the main memory unit 13 (or a user unit 15) through a system interface unit 11 to a cache memory unit 12. (Those skilled in the art will understand that, in some data processing system architectures, the signal groups are transferred over a system bus, thereby requiring an interface unit for each component interacting with the system bus.) The signal groups are stored in the cache memory unit 12 until requested by the central processing unit 14. To retrieve the correct signal group, address translation apparatus 16 is typically incorporated to convert a virtual address (used by the central processing unit 14 to identify the signal group to be fetched) to the real address used for that signal group by the remainder of the data processing system to identify the signal group. The information stored transiently in the cache memory unit 14 may include both instructions and operands stored in separate sections or stored homogeneously. Preferably, in the practice of the present invention, instructions and operands are stored in separate (at least in the sense that they do not have commingled addresses) memory sections in the cache memory unit 14 inasmuch as it is intended to invoke the operation of the present invention as to operand information only. The present invention is based on recognizing and taking advantage of sensed patterns in cache misses resulting from operand calls. In an extremely elementary example, consider a sensed pattern in which three consecutive misses ABC are, in fact, successive operand addresses with D being the next successive address. This might take place, merely by way of example, in a data manipulation process calling for successively accessing successive rows in a single column of data. If this pattern is sensed, the likelihood that signal group D will also be accessed, and soon, is enhanced such that its prefetching into the cache memory unit 14 is in order. The fundamental principles of the invention are set forth in the operational flow chart of FIG. 2. When a processor (or other system unit) asks for an operand, a determination is made as to whether or not the operand is currently resident in the cache. If so, there is a cache hit (i.e., no cache miss), the operand is sent to the requesting system unit and the next operand request is awaited. However, if there is an cache miss, the request is, in effect, redirected to the (much slower) main memory. Those skilled in the art will understand that the description to this point of FIG. 2 describes cache memory operation generally. In the present invention, however, the address of the cache miss is meaningful. It is therefore placed at the top of a miss stack to be described in further detail below. The miss stack (which contains a history of the addresses of recent cache misses in consecutive order) is then examined to determine if a first of several patterns is present. This first pattern might be, merely by way of example, contiguous addresses for the recent cache misses. If the first pattern is not sensed, additional patterns are tried. Merely by way of example again, a second pattern might be recent cache misses calling for successive addresses situated two locations apart. So long as there is no pattern match, the process continues through the pattern repertoire. If there is no match when all patterns in the repertoire have been examined, the next cache miss is awaited to institute the process anew. However, if a pattern in the repertoire is detected, a predictive address is calculated from the information in the miss stack and from the sensed pattern. This predictive address is then employed to prefetch from main memory into cache the signal group identified by the predictive address. In the elementary example previously given, if a pattern is sensed in which consecutive operand cache miss operand addresses ABC are consecutive and contiguous, the value of the predictive address, D, will be C + 1. In order to optimize the statistical integrity of the miss stack, the predictive address itself may be placed at the top of the stack since it would (highly probably) itself have been the subject of a cache miss if it had not been prefetched in accordance with the invention. Since speed of operation is essential, the invention may advantageously be embodied in a hard wired form (e.g., in a gate array) although firmware control is contemplated. Consider first a relatively simple hardwired implementation shown in FIG. 3. A miss stack 20 holds the sixteen most recent cache miss addresses, the oldest being identified as address P with entry onto the stack being made at the top. Four four-input electronic switches 21, 22, 23, 24 are driven in concert by a shift pattern signal via line 25 such that: in a first state, addresses A, B, C, D appear at to respective outputs of the switches; in a second state, addresses B, D, F, H appear at the outputs; in a third state, addresses C, F, I, L appear at the outputs; and in a fourth state, addresses D, H, L, P appear at the outputs. Subtraction circuits 26, 27, 28 are connected to receive as inputs the respective outputs of the electronic switches 21, 22, 23, 24 such that: the output from the subtraction circuit 26 is the output of the switch 21 minus the output of the switch 22; the output from the subtraction circuit 27 is the output of the switch 22 minus the output of the switch 23; and the output from the subtraction circuit 28 is the output of the switch 23 minus the output of the switch 24. The output from the subtraction circuit 26 is applied to one input of an adder circuit 31 which has its other input driven by the output of the electronic switch 21. In addition, the output from the subtraction circuit 26 is also applied to one input of a comparator circuit 29. The output from the subtraction circuit 27 is applied to the other input of the comparator circuit 29 and also to one input of another comparator circuit 30 which has its other input driven by the output of the subtraction circuit 28. The outputs from the comparator circuits 29, 30 are applied, respectively, to the two inputs of an AND-gate 32 which selectively issues a prefetch enable signal. Consider now the operation of the circuit shown in FIG. 3. As previously noted, miss stack 20 holds the last sixteen cache miss addresses, address A being the most recent. When the request for the signal group identified by address A results in a cache miss, circuit operation is instituted to search for a pattern among the addresses resident in the miss stack. The electronic switches 21, 22, 23, 24 are at their first state such that address A is passed through to the output of switch 21, address B appears at the output of switch 22, address C appears at the output of switch 23 and address D appears at the output of switch 24. If the differences between A and B, B and C, and C and D are not all equal, not all the outputs from the subtraction circuits 26, 27, 28 will be equal such that one or both the comparator circuits 29, 30 will issue a no compare; and AND-gate 32 will not be enabled, thus indicating a "no pattern match found" condition. The switches are then advanced to their second state in which addresses B, D, F, H appear at their respective outputs. Assume now that (B - D) = (D - F) = (F - H); i.e., a sequential pattern has been sensed in the address displacements. Consequently, both the comparators 29, 30 will issue compare signals to fully enable the AND-gate 32 and produce a prefetch enable signal. Simultaneously, the output from the adder circuit 31 will be the predictive address (B + (B - D)). It will be seen that this predictive address extends the sensed pattern and thus increases the probability that the prefetched signal group will be requested by the processor, thereby lowering the cache miss ratio. If a pattern had not have been sensed in the address combination BDFH, the electronic switches would have been advanced to their next state to examine the address combination CFIL and then on to the address combination DHLP if necessary. If no pattern was sensed, the circuit would await the next cache miss which will place a new entry at the top of the miss stack and push address P out the bottom of the stack before the pattern match search is again instituted. Consider now the somewhat more complex and powerful embodiment of the invention illustrated in FIG. 4. Electronic switches 41, 42, 43, 44 receive at their respective inputs recent cache miss addresses as stored in the miss stack 40 in the exemplary arrangement shown. It will be noted that each of the electronic switches 41, 42, 43, 44 has eight inputs which can be sequentially selectively transferred to the single outputs under the influence of the shift pattern signal. It will also be noted that the miss stack 40 stores, in addition to the sixteen latest cache miss addresses A - P, three future entries WXY. Subtraction circuits 45, 46, 47 perform the same office as the corresponding subtraction circuits 26, 27, 28 of the FIG. 3 embodiment previously described. Similarly, adder circuit 48 corresponds to the adder circuit 31 previously described. Comparator circuit 49 receives the respective outputs of the subtraction circuits 45, 46, and its output is applied to one input of an AND-gate 38 which selectively issues the prefetch enable signal. Comparator circuit 50 receives the respective outputs of the subtraction circuits 46, 47, but, unlike its counterpart comparator 30 of the FIG. 3 embodiment, its output is applied to one input of an OR-gate 39 which has its other input driven by a reduce lookahead signal. The output of OR-gate 39 is coupled to the other input of AND-gate 38. With this arrangement, activation of the reduce lookahead signal enables OR-Gate 39 and partially enables AND-gate 38. The effect of applying the reduce lookahead signal is to compare only the outputs of the subtraction circuits 45, 46 in the comparator circuit 49 such that a compare fully enables the AND-gate 38 to issue the prefetch enable signal. This mode of operation may be useful, for example, when the patterns seem to be changing every few cache misses, and it favors the most recent examples. With the arrangement of FIG. 4, it is advantageous to try all the patterns within pattern groups (as represented by the "YES" response to the ">1 PATTERN GROUP?" query in the flow diagram of FIG. 2) even if there is a pattern match detected intermediate the process. This follows from the fact that more than one of the future entries WXY to the miss stack may be developed during a single pass through the pattern repertoire or even a subset of the pattern repertoire. With the specific implementation of FIG. 4 (which is only exemplary of many possible useful configurations), the following results are obtainable: SWITCH STATE PATTERN GOAL 0 ABCD W 1 ACEG X 2 ADGJ Y 3 BDFH W 4 BEHK X 5 CFIL W 6 CGKO X 7 DHLP W The goal states are searched in groups by switch state; i.e.: Group 1 includes switch states 0, 1, 2 and could result in filling future entries WXY; Group 2 includes states 3, 4 and could result in filling entries WX; Group 3 includes states 5, 6 and could also result in filling entries WX; and Group 4 includes state 7 and could result in filling entry W. When a goal state is reached that has been predicted, the search is halted for the current cache miss; i.e., it would not be desirable to replace an already developed predictive address W with a different predictive address W. Those skilled in the art will understand that the logic circuitry of FIGs. 3 and 4 is somewhat simplified since multiple binary digit information is presented as if it were single binary digit information. Thus, in practice, arrays of electronic switches, gates, etc. will actually be employed to handle the added dimension as may be necessary and entirely conventionally. Further, timing signals and logic for incorporating the inventive structure into a given data processing system environment will be those appropriate for that environment and will be the subject of straightforward logic design.

Claims: Method for predicting cache request addresses for prefetching signal groups from a main memory into a cache memory in a data processing system, wherein said cache memory is repeatedly interrogated to determine whether an address corresponding to a cache request address is stored therein, said data processing system including a stack for storing cache miss addresses, said method including the step of A) upon the occurrence of a cache miss when the cache memory is interrogated, entering the cache request address corresponding to said cache miss into said stack; characterized by the further steps of: B) examining the cache request addresses in said stack to determine whether an address pattern can be found by examining a set of entries of the stack on equal differences between the contents of consecutive entries of the set; and C) (1) if no pattern is determined in step (B), returning to step (A), but (2) (i) if a pattern is determined in step (B), generating a predicted cache request address based on said pattern and at least one of said cache request addresses present in said stack, wherein said predicted cache request address is pointing to a signal group stored in said main memory; (ii) using said predicted cache request address to obtain the signal group identified by said predicted cache request address from said main memory and to write such signal group into the cache memory, and (iii) returning to step A). The method of claim 1, wherein said stack is a first in - first out stack, further characterized by: in step (A), said cache request address is entered into the top of said stack. The method of claim 1, wherein in step B), said address pattern is one of a plurality of searchable predetermined address patterns. The method of claim 3, wherein step (B) of examining the cache request addresses present in the stack comprises the steps of: (B) (1) selecting, from among said plurality of address patterns, a current address pattern; (B) (2) examining said cache request addresses present in said stack for a match with said current address pattern; (B) (3) if said current address pattern does not match the cache request addresses present in said stack, determining whether all of said plurality of predetermined address patterns have been examined, and (B) (4) if said current address pattern does not match the cache request addresses present in said stack and not all of said predetermined address patterns have been examined, selecting as said current address pattern a different one of said address patterns than said current address pattern previously selected in step (B) (1) and then returning to step (B) (2). The method of claim 4, wherein said plurality of predetermined address patterns comprises a plurality of pattern groups, the plurality of pattern groups comprising a current pattern group which includes said current address pattern. The method of claim 5, wherein step (B)(4) comprises the steps of: (B)(4)(1) determining whether all of said address patterns in said current pattern group have been examined; and (B)(4)(2) if not all of said address patterns in said current pattern group have been examined, selecting from said current pattern group as said current address pattern a different one of said address patterns than said current address pattern previously selected; and (B)(4)(3) if all of the address patterns in said current pattern group have been examined, selecting as said current address pattern one of said address patterns from a different pattern group than said current pattern group. Method of claim 6 further comprising the steps of: (C)(2)(ii)(a) if said current address pattern matches the cache request addresses present in said stack, selecting as said current address pattern one of said address patterns from a different pattern group than the previously selected current pattern group; and (C)(2)(ii)(b) if there is at least one of said pattern groups in which none of said predetermined address patterns has been examined, returning to step B). The method of claim 1, wherein a cache miss is the result of the absence in said cache memory of called information requested of said cache memory. The method of claim 1, wherein step C)(2) further comprises the step of placing said predicted cache request address at the top of said stack. Apparatus for generating a predicted cache request address for prefetching signal groups from a main memory into a cache memory in a data processing system in which a cache memory thereof is repeatedly interrogated to determine whether an address corresponding to a cache request address is stored therein, which stored address corresponds to information also stored in said cache memory; wherein said data processing system includes a store (20) for holding a plurality of said cache request addresses in respective cells thereof; said apparatus being characterized by: a plurality of switches (21-24; 41-44), each of said switches (21-24; 41-44) having a plurality of input terminals, an output terminal and a control terminal, such that a control signal applied to said control terminal causes said switch to couple one of said input terminals to said output terminal; said control signal being delivered to said control terminals to cause the input terminals of said switches (21-24; 41-44) to be successively coupled to said output terminals; a circuit for coupling each of said input terminals of said switches (21-24; 41-44) to one of said cells; a plurality of first arithmetic circuits (26-28; 45-47), each of said first arithmetic circuits (26-28; 45-47) having a pair of input terminals and an output terminal, the input terminals of each of said first arithmetic circuits (26-28; 45-47) being coupled to the respective output terminals of two of said switches (21-24; 41-44), each of said first arithmetic circuits (26-28; 45-47) performing an arithmetic operation on the two cache request addresses received by its input terminals from the two cells of said store coupled to said input terminals by said two switches and delivering a signal at its output terminal which represents the result of said arithmetic operation; a plurality of comparators (29, 30; 49, 50), each of said comparators (29, 30; 49, 50) having a pair of input terminals and an output terminal, the input terminals of each of said comparators (29, 30; 49, 50) being coupled to the respective output terminals of two of said first arithmetic circuits (26-28; 45-47), each of said comparators (29, 30; 49, 50) comparing the two arithmetic result signals received thereby and delivering a signal at its output terminal denoting whether said result signals are alike; and a second arithmetic circuit (31) having a pair of input terminals and an output terminal, a first input terminal of said second arithmetic circuit (31) being coupled to the output terminal of one of said switches (21-24; 41-44) and the second input terminal of said second arithmetic circuit (31) being coupled to the output terminal of one of said first arithmetic circuits (26-28; 45-47), said second arithmetic circuit (31) performing an arithmetic operation on the request address received by said first input terminal and the arithmetic result represented by the signal received by said second input terminal and delivering an output signal at its output terminal which represents the result of said arithmetic operation performed by said second arithmetic circuit (31); whereby, when the signals delivered at the output terminals of all of said comparators (29, 30; 49, 50) denote that the compared arithmetic results are alike, the arithmetic result represented by the concurrent output signal of said second arithmetic circuit (31) represents said predicted cache request address. The apparatus of claim 10, wherein said plurality of first arithmetic circuits (26-28; 45-47) comprises a plurality of subtraction circuits, each of said subtraction circuits for generating a value representing a displacement between two of said cache request addresses. The apparatus of claim 11, further comprising a first logic gate (32; 38) having a plurality of inputs separately coupled to the output terminals of at least two of said comparators (29, 30; 49, 50)for selectively outputting a prefetch enable signal when said first logic gate (32; 38) is fully enabled. The apparatus of claim 12, further comprising a second logic gate (39) driving at least one of the inputs of said first logic gate (38), said second logic gate (39) having inputs coupled to receive the output of at least one of said comparator circuits (49, 50) and a selectively applied reduce lookahead logic signal, such that application of the reduce lookahead logic signal to said second logic gate (39) partially enables said first logic gate (38) and thereby eliminates said at least one of said comparator circuits (49, 50) from consideration in the issuance of said prefetch enable logic signal. The apparatus of claim 13, wherein said first logic gate (32; 38) is an AND gate and said second logic gate (39) is an OR gate.

Inventors: RYAN CHARLES P, RYAN, CHARLES P.
Applicants: INTEL CORP, INTEL CORPORATION
Application year: 1990
Main classification: G06F12
IPC codes: G06F12, G06F9