Delay generator

Abstract: A delay generator (15) having very high accuracy and stability over temperature variations and time, is suited for very short delay times, such as in clock recovery circuits in very high-speed digital data transmission systems. A delay line (20), having one end either open or shorted and a round-trip delay time of τ, is driven by a voltage source (24), the output impedance thereof being matched to the delay line, and a current source (23). The current source and the voltage source are driven by an input signal V(t) to be delayed. The voltage source is provided by a transistor operating as a voltage follower, which also operates to provide as an output a signal V out (t) dependent on the difference between the input signal and the voltage on the delay line. This output serves as the output of the delay generator, the input signal delayed by the time τ.

Description: This invention relates to delay generators. Most data communication systems require the synchronization of a local sampling clock to an incoming digital data stream to optimally sample the incoming data stream and control the decoding thereof. Typically, the synchronization must extract the local sampling clock from the incoming digital data itself. With many very high-speed systems, the synchronizing process is complicated by the data format of the digital data stream having relatively few data transitions from which a local clock can be derived, e.g., non-return-to-zero (NRZ) coding. The NRZ format allows for a relatively large amount of data which may be transmitted within a given bandwidth, the bandwidth being dictated by regulation or tariff, transmission media capacity, or the capacity of the electronics coupling to the transmission media. At very high speeds (e.g., 10 9 -10 10 bits per second, referred to here as 1-10 Giga-bits per second, or Gbs), the traditional methods of deriving the local clock are not sufficient, because of many factors, such as, delay stability with time and temperature, cost, delay symmetry, physical size, or the inability to be monolithically integrated with other electronic circuits. US-A-2892938 discloses a delayed pulse generator utilizing a single-ended delay line. The delay line receives an input signal pulse to be delayed from a cathode follower. A differential amplifier subtracts the input signal from the signal delayed by the the delay line to achieve an output pulse that is delayed approximately twice the propagation delay of the transmission line. WESTERN ELECTRIC, RT206 Technical Digest, no.15, July 1969; M.N.BLANCHARD: "Double pulse generator" discloses a double pulse generator that uses input pulses delayed by a single-ended delay line to provide a second pulse. ELECTRONIC LETTERS, vol.22, no.1, January 1986, pages 38-39; R.GANGOPADHYAY et al.: "Timing recovery in optical receivers for NRZ signalling" discloses a clock recovery apparatus that uses a delay and an exclusive-OR gate to generate a series of output pulses harmonically related to the clock rate of incoming data. The output pulses are created by the exclusive-OR gate multipling the incoming data by the data delayed by the delay. It is further desirable to provide a delay generator operable at very high speeds that is both relatively inexpensive to manufacture and have reasonably stable delays with temperature and aging. Further, such a delay generator should be adaptable to operate over a relatively wide range of delays and be readily integratable with other electronic circuits. In particular, the delay generator should be able to provide the relatively very short delays necessary for very high-speed digital communication systems, such as high-speed optical data links and the like. According to this invention there is provided a delay generator as claimed in claim 1. A clock recovery system for use in optical data links or the like may include a delay generator in accordance with the invention and responsive to an input signal for delaying the input signal by substantially one-half the symbol interval of the input signal; a multiplier, responsive to the input signal and the delayed input signal from the delay generator, having an output; and filtering means, coupled to the output of the multiplier, to pass signals from the multiplier, that have a frequency substantially equal to the symbol rate of the input signal, to an output. The invention will now be described with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of the receiver portion of an exemplary high-speed optical data link; FIG. 2 is a simplified schematic of an exemplary delay generator used in FIG. 1; FIGs. 3 and 4 are models of the circuit shown in FIG. 2 to facilitate understanding of the invention; FIG. 5 is an exemplary graph (not to scale) of signals in the exemplary delay generator with a short-circuit termination; FIG. 6 is an exemplary graph (not to scale) of signals in the exemplary delay generator with an open circuit termination; and, FIG. 7 is a simplified schematic of another exemplary delay generator, similar to that shown in FIG. 2 but for differential operation. Detailed Description In FIG. 1, an exemplary receiver portion 10 of an high-speed optical data link (not shown) is diagramed. A photodiode 11 converts received optical pulses and converts them to electrical signals which are amplified by amplifier 12. The amplified pulses are coupled to a conventional sample and decode circuit 13 and to a clock recovery circuit 14. A local clock signal is derived by the clock recovery circuitry 14 so that the incoming data is correctly (optimally) sampled and decoded as valid received data. The clock recovery circuitry 14 is shown here using a delay-and-multiply technique, discussed above. As shown, a delay generator 15, which will be discussed in detail below, delays the amplified pulses from the amplifier 12 by an amount substantially equal to one-half the symbol rate of the received data. Multiplier 16 multiplies the amplified pulses with the delayed amplified pulses, the results of which are passed to a filter means 17, shown here as a bandpass filter with a center frequency of substantially the symbol rate of the incoming data. Although shown here as a bandpass filter, filter means 17 may be implemented as a phase-locked loop (PLL). The delay generator 15 may be implemented by the circuit shown in FIG. 2. A delay line 20, having a characteristic (or surge) impedance Z 0 , is terminated at one end with an impedance different from Z 0 , preferably a shorting stub 21 or an open circuit. The improper end termination allows for a round-trip propagation delay of a signal applied to the input 22 of the delay line 20 of τ seconds, referred to here as just τ. A means, comprising transistors 23 and 24, impresses across the inputs 22 an instantaneous voltage substantially equal to the input signal voltage v(t). Transistor 24 also operates as a differencing means to determine the difference in voltage between the voltage of the input signal v(t) and the voltage v L (t) across the input 22 of the delay line 20. For purposes here, transistor 24, operating as a voltage (source) follower, in conjunction with transistor 23 operating as a controlled current source, forces v L (t) to be substantially equal to the instantaneous voltage of the input voltage v(t). By instantaneous voltage, we mean the voltage impressed on the delay line before the so-impressed voltage (signal) has propagated down the delay line 20, reflected off the open end of the delay line 20 or the shorting stub 21, and propagated back through the delay line 20 to input 22. It is understood, as will be shown below, that when the signal has so reflected and returned to the input 22, the voltage thereon will be substantially canceled. The transconductance (g m24 ) of transistor 24 is chosen such that the output impedance of the transistor 24, as viewed at the source terminal thereof and in parallel with the output resistance of the transistor 23, is substantially equal to the characteristic impedance of the delay line 20. This properly terminates the delay line 20 and absorbs the reflected signals therefrom, as will be explained in more detail below. The drain terminal of transistor 24 couples to a load resistor 25 having a resistance of R 25 . The voltage drop thereon, v out (t), is the delayed input signal v(t), which can be represented as Kv(t-τ). The constant K is determined by the drain current i(t) from transistor 24, the resistance R 25 , the transconductance g m24 , and the input signal v(t), as will be shown below. To understand the operation of the delay generator 15, an electrical model 30 thereof is shown in FIG. 3, using the shorting stub 21. Using an open delay line 20 will be discussed below. Controlled current source 31, corresponding to transistor 23, has a current proportional to the input signal v(t), shown here as g m23 v(t). Transistor 24 (FIG. 1) is modeled as a voltage source 32 and resistor 33, the resistance being substantially 1/g m24 , or as stated above, the characteristic impedance of the delay line 20, ignoring any output impedance of transistor 23 (FIG. 2). The resulting voltage across the delay line 20 inputs 22 is v L (t). If the transconductances g m23 and g m24 substantially the same, it can be shown that the circuit model 30 may be simplified to what is shown in FIG. 4 to determine the voltage v L (t). In this case, the model 30 (FIG. 3) becomes the model 40 with a voltage source 41 having a voltage twice that of source 32 in FIG. 3. Resistor 42 has the same resistance as resistor 33 in FIG.3 (substantially Z 0 ). For purposes here, the input signal, v(t), is a pulse having a duration longer than the round-trip delay of the delay line 20, τ. The resulting voltage v L (t) is graphed in FIG. 5 (not to scale). The resulting voltage v L (t) is a pulse having an amplitude of A and a period of substantially τ, the round-trip delay time of the delay line 20. The polarity of the pulse is dependent on the polarity of the input signal, v(t); when v(t) goes positive, v L (t) is a positive pulse of amplitude A and when v(t) goes negative, v L (t) is a negative pulse of amplitude A. It should be noted that the amplitude of v L (t) is substantially equal to the amplitude of the input signal v(t). Returning to FIG. 3, the voltage v o (t) can be determined as the voltage drop across the resistor 33. The voltage v o (t) is then v(t)-v L (t). Referring again to FIG. 5, the voltage v o (t) can be graphically determined from v(t) and v L (t) as determined above. As shown, v o (t) is the input signal v(t) delayed by the time τ. Hence, the input signal v(t) is delayed by the round-trip delay time through the delay line 20, τ. Similarly, when shorting stub 21 (FIGs. 3 and 4) is not used (delay line 20 is open-circuited), the resulting voltage v L (t) is shown in FIG. 6 (not to scale). The voltage v L (t) is a double pulse of amplitudes A and 2A, the length of the amplitude A portion being substantially τ. As before, if the signal v L (t) is subtracted from the input signal v(t), then v o (t) is a negative going pulse of amplitude A. As shown, this is the input signal v(t), inverted, and delayed by τ. Hence, the input signal v(t) is delayed by the round-trip delay time through the delay line 20, τ, and inverted. As stated above, the transconductances g m23 , g m24 should be substantially equal so that the amplitude of v L (t) is substantially equal to that of v(t). However, transistor 24, operating as a source (voltage) follower may not provide a voltage substantially equal to v(t) as shown by voltage source 32 in FIG. 3. Since the transconductance g m24 is primarily used to determine the output impedance of transistor 24, the transconductance g m23 may be varied to compensate for inaccuracies of the source follower function of transistor 24. The voltage v o (t) is impressed across the gate and source of transistor 24 in FIG. 2. This voltage, v o (t), multiplied by the transconductance of the transistor 24, g m24 , is the output current i(t). This current multiplied by the resistance of resistor 25, R 25 , is then the output signal v out (t), which is delayed by τ and proportional to the input signal v(t): v out (t)≈R 25 g m24 v(t-τ)≈Kv(t-τ) In FIG. 2, the input signal to transistor 24 is v(t) and -v(t) to transistor 23, which may be inconvenient to generate with precise alignment, i.e., the phases are substantially 180° out of phase. Hence, it is preferred that the delay generator be a fully differential implementation of the delay generator 15. One such exemplary implementation is shown in FIG. 7. Operation of the differential delay generator 60 is similar to that discussed in connection with the operation of the delay generator 15 of FIG. 2. As shown, v(t) is not referenced to a fixed potential and is a fully differential signal. Similarly, the output signal, v out (t) is fully differential. Transistors 61, 62 operate as current sources, corresponding to transistor 23 of FIG. 2. Transistors 63, 64 operate as voltage followers, load impedances to delay line 20, and differencing means, corresponding to transistor 24 of FIG. 2. Also resistors 65, 66 correspond to resistor 25 of FIG. 2. It is noted that transistor 61 is cross-coupled to transistor 64, as are transistors 62 and 63, such that the proper phase of the input signal v(t) is provided to the voltage follower transistors 63, 64 and to the current source transistors 61, 62 for proper operation of the delay generator 60. Level shifting circuitry 67, 68, shown here as fixed voltage sources, provide the proper DC offset necessary for the input signal v(t) to drive both the current source transistors 61, 62 and the voltage follower transistors 63, 64. Current source 69 allows for the common mode voltage of the input signal v(t) to vary without affecting the operation of the delay generator 60. It is further noted that the output impedances of the transistors 63, 64 are effectively placed in series, so that the output impedances thereof must be adjusted lower, each approximately one-half the characteristic impedance, Z 0 , of the delay line 20. If, instead of shorting the delay line 20 with stub 21, the delay line 20 is open-circuited, delay generator 60 will provide the desired delay τ (when delay line 20 is sized to provide the desired delay τ) (t) but the output signal V out (t) will have the opposite polarity to that provided when using the shorted delay line 20. Although the operation of the delay generator (15, FIG. 2 or 60, FIG. 7) is described above using either a shorted- or an open-circuited delay line 20, other terminations are possible. It is understood that terminating the end of the delay line 20 with an impedance different from the characteristic impedance thereof will allow for the necessary signal reflection by the delay line 20. It is preferable to use an open- or a short-circuited delay line 20 to maximize the amplitude of the reflected signals therefrom. Having described the preferred embodiment of this invention, it will now be apparent to one of skill in the art that other embodiments thereof may be devised.

Claims: A delay generator (15) including: a delay line (20) having a characteristic impedance Z 0 , first and second ends, the first end being terminated in an impedance different from Z 0 , and a round-trip delay time τ; a voltage source (24;63,64) serving also as differencing means (24;63,64), responsive to an input signal (V(t)) and connected to the second end of the delay line, for generating at an output the difference between the input signal voltage and an instantaneous voltage (V L (t)) across the second end of the delay line; wherein there is provided a current source (23;61,62), responsive to the input signal, connected to the second end of the delay line; wherein the combination of the current source and the voltage source has an impedance substantially equal to the characteristic impedance of the delay line; and wherein voltage from the voltage source is combined with the current from the current source to provide, for a time period following a change in the input signal (V(t)) substantially corresponding to the round-trip delay time τ, a change in the instantaneous voltage across the second end of the delay line substantially equal to the change in the voltage of the input signal, whereby the output of the differencing means is the input signal delayed by the round-trip delay time of the delay line, τ. A clock recovery system (14) for use in optical data links or the like, including: a delay generator (15) as claimed in claim 1 and responsive to an input signal, for delaying the input signal by substantially one-half the symbol interval of the input signal; a multiplier (16), responsive to the input signal and the delayed input signal from the delay generator, having an output; and filtering means (17), coupled to the output of the multiplier, to pass signals from the multiplier that have a frequency substantially equal to the symbol rate of the input signal, to an output. A delay generator as claimed in claim 1, wherein the voltage source and the differencing means includes: a first transistor (24;63,64) having an input and first and second outputs, the conductivity of the transistor between the first and second outputs being determined primarily by the difference in voltage between the input and the first output, the input being responsive to the input signal, the first output being connected to the second end of the delay line; and a load resistor (25;65,66) connected to the second output of the transistor, wherein the output of the differencing means is the voltage across the load resistor,and the transconductance of the first transistor is chosen such that the series impedance, provided at the first output of the first transistor, is substantially equal to the characteristic impedance of the delay line. A delay generator as claimed in claim 3, wherein the current source includes: a second transistor (23;61,62) having an input and two outputs, the input being responsive to the input signal, and the outputs being connected to the second end of the delay line; wherein the transconductance of the second transistor is substantially equal to the transconductance of the first transistor.

Inventors: RANSIJN JOHANNES GERARDUS, RANSIJN, JOHANNES GERARDUS
Applicants: AT & T CORP, AT&T CORP.
Application year: 1990
Main classification: H03K5
IPC codes: H04L7, H04L25, H03K5