Semiconductor integrated circuit for video signal processing

Abstract: A video reproduction signal-processing circuit is an integrated circuit and is incorporated in a video tape recorder. In this integrated circuit, a dropout-­ detecting circuit (11) generates a dropout signal, and a limiter circuit (19) and a wave-shaping circuit (22) jointly output a noncorrelation/correlation signal. The dropout signal and the noncorrelation/correlation signal are first added together by an adder circuit (12), and are then output from the integrated circuit through a single output terminal (13).

Description: The present invention relates to an integrated circuit which may be incorporated in a video tape recorder for the processing of video signals. More particularly, it relates to a video signal-processing semiconductor integrated circuit used for the processing, such as dropout compensation, comb filtering of luminance signals, chroma noise reduction, or the like. In general, a video tape recorder (hereinafter referred to as a VTR) is provided with a dropout compensator (DOC). This dropout compensator prevents a non-signal portion from being included in the frequency-modulated (FM) signal reproduced from the magnetic tape, so as to reproduce a noise-free image on a screen. The VTR is also provided with a noncorrelation/correlation processing circuit, so as to carry out the chroma noise reduction processing. The noncorrelation/correlation processing circuit generates a noncorrelation/correlation signal by use of a luminance signal obtained by demodulating the reproduced FM signal. In a conventional VTR, the dropout compensator and the noncorrelation/correlation processing circuit are formed in the same integrated circuit but are completely independent of each other. In addition, DOC pulses produced from the dropout compensator and noncorrelation/correlation pulses are output from the integrated circuit through their respective output terminals. Since the dropout compensator and the noncorrelation/correlation processing circuit are formed independently of each other in the conventional VTR, output terminals have to be provided for them independently of each other. The preamble of claim 1 reflects such a circuit. An integrated circuit recently developed for VTRs is provided with many functions, and therefore has an increased number of output terminals. However, an increase in the number of output terminals necessitates an increase in the chip size, thus resulting in an increase in the cost for manufacturing the VTR. It is therefore desirable that the number of output terminals be as small as possible. JP-A-59 37 788 (corresponds to Patent Abstracts of Japan, vol. 8, no. 127 (E-250)(1564) 14.06.1986) shows a line correlation and dropout compensating circuit comprising an electronic switch for selecting a signal delayed by a line when dropout is detected on the current line. A subtraction means is provided for obtaining a difference component between the delayed signal and the current signal. However the difference signal is not used to generate a correlation signal. The present invention has been developed in consideration of the above circumstances, and an object of the present invention is to provide video signal-processing semiconductor integrated circuit which incorporates both a dropout compensator and a noncorrelation/correlation processing circuit and which enables reduction of the number of output terminals. The present invention provides a video signal-processing semiconductor integrated circuit as set out in claim 1. Fig. 1 is a block circuit diagram showing a video signal-processing semiconductor integrated circuit according to one embodiment of the present invention; Fig. 2 is a circuit diagram showing a specific circuit arrangement of part of the circuit shown in Fig. 1; Fig. 3 is a waveform chart illustrating the waveforms of the signals produced at major points of the circuit shown in Fig. 1; and Fig. 4 is a waveform chart illustrating the waveform of one of the signals shown in Fig. 3. Fig. 1 shows the internal circuit arrangement of a video signal-processing semiconductor integrated circuit according to one embodiment of the present invention. Referring to Fig. 1, a reproduction FM signal (PB-FM), which is obtained from a video tape by a magnetic head (not shown), is supplied to a dropout-detecting circuit 11. This dropout-detecting circuit 11 detects the amplitude level of the reproduction FM signal and produces a dropout compensation pulse (i.e., a DOC pulse) if the detected amplitude level temporarily becomes very low or if it becomes zero. The dropout compensation pulse is supplied to an adder circuit 12. An output of this adder circuit 12 is supplied to an external circuit through an output terminal 13. In the meantime, a reproduction luminance signal (PB-Y), which is produced by a demodulating circuit (not shown) as a result of the demodulation of the above-mentioned reproduction FM signal, is supplied, in parallel, to a delay circuit 14, a subtraction circuit 15, and an adder circuit 16. In the delay circuit 14, the reproduction luminance signal is delayed by a time interval corresponding to one horizontal period, and the delayed signal is supplied to the subtraction circuit 15. In the subtraction circuit 15, the signal delayed by the delay circuit 14 is subtracted from the reproduction luminance signal which is not delayed, and a signal obtained by this subtraction is supplied to an amplifier circuit 17. In this amplifier circuit 17, the signal is amplified to have a predetermined level. The level-amplified signal is supplied to the first one of a pair of input terminals of a limiter circuit 19 by way of a first resistor element 18. It is also supplied to the second one of the input terminals of the limiter circuit 19 by way of a second resistor element 20. The limiter circuit 19 is of a differential amplification type. A capacitor 21, used for both the bypassing of a.c. signals and the accumulation of d.c. signals, is inserted between the second input terminal of the limiter circuit 19 and a ground potential point. Due to the second resistor element 20 and the capacitor, only the d.c. components of the level-amplified signal are input to the second input terminal of the limiter circuit 19. In the limiter circuit 19, the level-amplified signal supplied from the amplifier circuit 17 is compared with its d.c. components input to the second input terminal and is limited on the basis of a predetermined slice level. The signal, thus limited is supplied to the adder circuit 16. It is also supplied to the adder circuit 12 by way of a waveform-shaping circuit 22. An output of the adder circuit 12 is supplied to an external point of the integrated circuit through the output terminal 13. An output of the adder circuit 16 is supplied to a circuit (not shown) formed within the integrated circuit. Fig. 2 is a circuit diagram showing the specific circuit arrangement of the limiter circuit 19 included in the integrated circuit shown in Fig. 1. As is shown in Fig. 2, the limiter circuit 19 includes a differential transistor pair 31 made up of transistors 33 and 34. These transistors 33 and 34 are connected together at their emitters, and their bases respectively receive the signals which the amplifier circuit 17 supplies through the first and second resistor elements 18 and 20. The limiter circuit 19 also includes a load circuit 32 connected to the differential transistor pair 31. The capacitor 21 mentioned above is connected between the base of one transistor 33 of the differential transistor pair 31 and the ground potential point. A d.c. bias potential used for determining the slice level is applied to the base of transistor 33. A signal obtained by superimposing a.c. signal components on the d.c. bias potential is supplied to the base of the other transistor 34 of the differential transistor pair 31. In the above circuit arrangement, the output of the limiter circuit 19 is in a correlation state if its level is lower than the slice level of the limiter circuit 19, and is in a noncorrelation state if its level is higher than the slice level. In short, the output of the limiter circuit 19 is a noncorrelation/correlation signal. The adder circuit 16 adds this noncorrelation/correlation signal to its original signal (i.e., the reproduction luminance signal), so that an output of the adder circuit 16 is a comb filter output, i.e., a signal obtained by causing a luminance signal to pass through a comb filter. The adder circuit 12 adds the noncorrelation/correlation signal to the DOC pulse (which is output from the dropout-detecting circuit 11). The resultant signal is output from the output terminal 13 and is supplied to an external point of the integrated circuit. As is understood from the above, signals of two kinds (which, in the prior art, are output from their respective output terminals independently of each other) are output from one terminal 13 in the circuit of the embodiment. Thus, the number of output terminals used in the embodiment circuit is smaller than that of the prior art. Incidentally, since the signals of two kinds are output from one output terminal, they have to identified on the side of an external circuit which performs processing in response to them. This signal identification can be easily performed by causing the adder circuit 12 to generate voltage levels having three difference values, as will be described below. Fig. 4 is an enlarged waveform chart illustrating the waveform of the signal output from the output terminal 13. When the dropout-detecting circuit 11 generates a DOC pulse, the signal output from the output terminal 13 has the lowest level (i.e., a DOC level). When the noncorrelation/correlation signal is in a correlation state, the signal output from the output terminal 13 has a noncorrelation level higher than the lowest level. When the noncorrelation/correlation signal is in a noncorrelation state, the signal output from the output terminal 13 has the highest level (i.e., a normal level). Therefore, the above-mentioned signals of two kinds can be identified and detected by simply providing two level-detecting circuits for an external circuit (not shown) connected to the output terminal 13, namely: a first level-detecting circuit whose slice level is between the DOC level and the noncorrelation level and which detects whether the input level is higher or lower than the slice level; and a second level-detecting circuit whose slice level is between the noncorrelation level and the normal level and which detects whether the input level is higher or lower than the slice level. With the signals of two kinds being detected in this manner, the circuit supplied with the signal output from the output terminal 13 carries out dropout compensation by use of the DOC pulse, or carries out chroma noise reduction by use of the noncorrelation/correlation signal. As described in the foregoing, the present invention can provide a video signal-processing semiconductor integrated circuit which incorporates both a dropout compensator and a noncorrelation/correlation processing circuit and which enables reduction of the number of output terminals. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A video signal-processing semiconductor integrated circuit, comprising: dropout signal-generating means (11), supplied with a frequency-modulated video reproduction signal (PB-FM), for generating a dropout signal (DOC) when the video reproduction signal has an amplitude level lower than a predetermined value; delay means (14) for delaying a luminance signal (PB-Y), obtained by demodulating the video reproduction signal (PB-FM), by one horizontal period; subtraction means (15) for obtaining a difference component between the luminance signal delayed by the delay means (14) and the luminance signal not delayed by the delay means (14); and noncorrelation/correlation signal-generating means (18,19,20,21,22) for deriving a noncorrelation/correlation signal from the difference component obtained by the subtraction means (15); characterised by adder means (12) for adding the dropout signal and the noncorrelation/correlation signal together and generating a signal obtained by the addition; and one output terminal (13) for outputting the signal generated by the adder means to an external region, wherein said noncorrelation/correlation signal-generating means (18,19,20,21,22) includes: a limiter (19) for slicing a signal representing the difference component obtained by said subtraction means; and wave-shaping means (22) for shaping the waveform of an output of the limiter (19) to form the noncorrelation/correlation signal. A video signal-processing semiconductor integrated circuit according to claim 1, characterised by further comprising: further adder means (16) for adding the luminance signal (PB-Y) to the noncorrelation/correlation signal, so as to produce a comb filter output.

Inventors: HAGINO HIDEYUKI, HAGINO, HIDEYUKI, HAGINO, HIDEYUKI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H04N9
IPC codes: H04N5, H04N9, G11B20