BINARY FLOATING POINT ARITHMETIC ROUNDING IN CONFORMANCE WITH IEEE 754-1985 STANDARD

Abstract: A method and a high speed processor (HSP) incorporating that method are set forth for processing signals representing outputs generated by remainderless division algorithms (102) and remainderless square root algorithms so as to obtain rounded outputs (112) conforming to the IEEE 754-1985 binary floating point arithmetic standard. The method and procedure of the present invention allow the solutions of floating-point computations to be rounded such that sign bits, as well as binary bits, of the rounded results are in full compliance with all guidelines of the stated standard.

Description: BINARY FLOATING POINT ARITHMETIC ROUNDING IN CONFORMANCE WITH IEEE 754-1985 STANDARD Background Of The Invention Fixed point division and square root algorithms have long been in use. Such algorithms comply with the IEEE 754-1985 binary floating point arithmetic standard, hereafter designated IEEE FPS, for rounding because each iteration of the algorithm computes a bit that is identical to the corresponding bit in the infinitely precise result and because the remainder of the calculation can always be determined. Remainderless algorithms have been utilized to provide faster computation for division and square root determination, in that such algorithms may often be computed more quickly than the fixed point counterparts. In particular, utilizing restoring and non-restoring algorithms, computation time is proportional to a word length divided by a radix; more particularly, algorithm computation time is linearly related to the word length. Utilizing convergent algorithms, computation time is proportional to a log, to a base of a convergence rate, of a word length divided by an initial approximation accuracy; more particularly, algorithm computation time is related to the log of the word length. However, remainderless algorithms for division and square root determination may generate results that are numerically very near, but bitwise very different from the infinitely precise result. Hence such algorithms may provide rounded results that are not in compliance with the IEEE FPS. Thus, there is a need for a method of rounding results from remainderless algorithms for division and square root determination such that the rounded result conforms with the cited standard. Summary Of The Invention The need for a method of rounding results obtained by utilizing remainderless algorithms for division and square root determination such that the results are in accordance with the IEEE FPS is substantially met by the method and high speed processor incorporating that method of the present invention. The present invention sets forth a method and high speed processor for processing electrical signals representing outputs generated by implementation of remainderless division algorithms and remainderless square root algorithms, the outputs being rounded to a rounding precision having a least significant bit, the rounding precision specified by a precision given in an IEEE FPS, and the desired rounding mode implemented being applied corresponding to an IEEE FPS rounding mode. The output utilized, C, is generated by remainderless division utilizing a dividend value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign, or by remainderless square root determination utilizing an input value S, having a magnitude, IS1, and a sign. C has a magnitude, a sign conforming to the IEEE FPS, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, C being in an extended precision wherein the extended precision has a greater precision than the rounding precision. In one embodiment of the present invention, for remainderless division, INI, D, and C are obtained and for remainderless square root determinations, I SI and C are obtained. C is utilized to determine at least one of two rounding values, L and H, each having a magnitude and a sign, and H having a least significant bit (lsb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the rounding mode specified by the IEEE FPS. At least one of the two rounding values, L and H, is utilized to generate an intermediate value A that is related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS. Then the implementation of the invention method obtains a magnitude of a product value: for remainderless division, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude IA * DI or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude IA * Al. The implementation then generates a status: for a remainderless division algorithm, a divide status comprising "less than" if IA * DI is less than INI, "equal to" if IA * DI equals INI, and "greater than" if I A * DI is greater than INI; and, for a remainderless square root algorithm, a square root status comprising "less than" if IA * Al is less than ISI, "equal to" if IA * Al equals ISI, and "greater than" if IA * Al is greater than ISI. The implementation selects the rounding value L or H relative to at least the divide status or the square root status as a rounded result value R in the rounding precision in conformance with the desired rounding mode specified by the IEEE FPS. Brief Description Of The Drawings FIG. 1 depicts a flow diagram of the method of the present invention for remainderless division rounding pursuant to the IEEE FPS. FIG. 2 depicts a flow diagram of the method of the present invention for remainderless square root rounding pursuant to the IEEE FPS. FIG. 3 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Rounding To Nearest (Even) mode with the round bit set. FIG. 4 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Rounding To Nearest (Even) mode with the round bit clear. FIG. 5 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Zero mode with the round bit set. FIG. 6 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Zero mode with the round bit clear. FIG. 7 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Positive Infinity mode with the round bit set and the sign of C positive. FIG. 8 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Positive Infinity mode with the round bit clear and the sign of C positive. FIG. 9 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Positive Infinity mode with the round bit set and the sign of C negative. FIG. 10 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Positive Infinity mode with the round bit clear and the sign of C negative. FIG. 11 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit set and the sign of C positive. FIG. 12 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit clear and the sign of C positive. FIG. 13 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit set and the sign of C negative. FIG. 14 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit clear and the sign of C negative. FIG. 15 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round To Nearest (Even) mode with the round bit set. FIG. 16 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round To Nearest (Even) mode with the round bit clear. FIG. 17 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round Toward Zero mode with the round bit set. FIG. 18 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round Toward Zero mode with the round bit clear. FIG. 19 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round Toward Positive Infinity mode with the round bit set. FIG. 20 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round Toward Positive Infinity mode with the round bit clear. FIG. 21 illustrates relative numberline positions in . remainderless square root determination for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit set. FIG. 22 illustrates relative numberline positions in remainderless square root determination for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit clear. FIG. 23 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round To Nearest (Even) rounding mode. FIG. 24 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Zero rounding mode. FIG. 25 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Positive Infinity rounding mode. FIG. 26 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Negative Infinity rounding mode. FIG. 27 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Zero rounding mode with truncation. FIG. 28 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round To Nearest (Even) rounding mode with truncation. FIG. 29A and 29B is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Positive Infinity rounding mode with truncation. FIG. 30A and 30B is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Negative Infinity rounding mode with truncation. FIG. 31 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round To Nearest (Even) rounding mode. FIG. 32 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round Toward Zero or Round Toward Negative Infinity rounding mode. FIG. 33 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round Toward Positive Infinity rounding mode. FIG. 34 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round To Nearest (Even) rounding mode with truncation. FIG. 35 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round Toward Zero or Round Toward Negative Infinity rounding mode with truncation. FIG. 36 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round Toward Positive Infinity rounding mode with truncation. FIG. 37 depicts a block diagram of a computer hardware implementation of the present invention. Best Mode For Carrying Out The Invention FIG. 1, generally depicted by the numeral 100, illustrates one embodiment of steps executed by a high speed processor (HSP) incorporating a method of the present invention for rounding an output C (102) of a rounding precision having a least significant bit, the rounding precision typically specified by a precision given in the IEEE 754-1985 binary floating point arithmetic standard, hereafter referenced as IEEE FPS, utilizing a desired rounding mode defined by a IEEE FPS rounding mode, the output generated by remainderless division utilizing a dividend value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign. As used herein, certain terms are defined as follows: trunc (x) is defined as a number in the rounding precision nearest to x which has a magnitude that is less than or equal to a magnitude of x; for IEEE FPS sign magnitude format trunc (x) can be computed by discarding all bits to the right of the least significant bit of the rounding precision; nextaway (x) is defined as: nextafter (x, -H») if signed x is positive, and nextafter (x, -«) if signed x is negative; this function is the next representable floating point number in the rounding precision after x that has a magnitude larger than Ixl; and the nextafter function is defined according to the IEEE definition of same. A first data storage and manipulation unit obtains and utilizes an output C, represented by at least one electrical signal and generated by remainderless division implementing a dividend value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign, wherein C has a magnitude, a sign conforming to the IEEE FPS, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, and C is in an extended precision wherein the extended precision has a greater precision than the rounding precision (102). A first determining unit generates at least one of two rounding values L and H, each having a magnitude, a sign, and being represented by at least one electrical signal, and H having a least significant bit (lsb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the rounding mode specified, by the IEEE FPS ( 104). Single extended precision, double extended precision, as well as higher extended precisions may be utilized as the extended precision. The magnitude of L is less than the magnitude of H, and the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision. The first determining unit determines the rounding values L and H (104) as follows: incorporating an IEEE Round To Nearest (Even) procedure. as set forth in FIG. 3, FIG. 4, and FIG. 23, the rounding value L is trunc (C) and the rounding value H is equal to nextaway (L) (2304); incorporating an IEEE Round Toward Zero procedure, as set forth in FIG. 5 and FIG. 24, the round bit of C (2402) is set and the rounding value H is equal to nextaway [trunc (C)], and L = nextafter (H,0) (2404); incorporating an IEEE Round Toward Zero procedure, as set forth in FIG. 6 and FIG. 24, the round bit of C (2402) is clear and the rounding value H is equal to trunc(C), and L = nextafter (H,0) (2406); incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 7 and FIG. 25, the round bit of C (2402) is set, the sign of C (2502) is positive, the value of L is equal to nextaway [trunc(C)], and H = nextaway (L) (2504); incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 8 and FIG. 25, the round bit of C (2402) is clear, the sign of C (2502) is positive, the value of L is equal to trunc(C), and H = nextaway (L) (2506); incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 9 and FIG. 25, the round bit of C (2402) is set, the sign of C (2502) is negative, the value of H is equal to nextaway [trunc(C)], and L = nextafter (H,0) (2508); incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 10 and FIG. 25, the round bit of C (2402) is clear, the sign of C (2502) is negative, the value of H is equal to trunc(C), and L = nextafter (H,0) (2510); incorporating an IEEE Round Toward Negative Infinity procedure, as set forth in FIG. 11 and FIG. 26 the round bit of C (2402) is set, the sign of C (2602) is positive, the value of H is equal to nextaway [trunc(C)], and L = nextafter (H,0) (2608); incorporating an IEEE Round Toward Negative Infinity procedure, as set forth in FIG. 12 and FIG. 26, the round bit of C (2402) is clear, the sign of C (2602) is positive, the value of H is equal to trunc(C), and L = nextafter (H,0) (2610); incorporating an IEEE Round Toward Negative Infinity procedure, as set forth in FIG. 13 and FIG. 26, the round bit of C (2402) is set, the sign of C (2602) is negative, the value of L is equal to nextaway [trunc(C)],and H = nextaway (L) (2304); and incorporating an IEEE Round Toward Negative Infinity procedure, as set forth in FIG. 14 and FIG. 26, the round bit of C (2402) is clear, the sign of C (2602) is negative, the value of L is equal to trunc(C), and H = nextaway (L) (2604). A second determining unit then determines A (FIG. 1 , 106), represented by at least one electrical signal and related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS (104), wherein A is determined as follows: incorporating an IEEE Round To Nearest (Even) procedure, as set forth in FIG. 23, the value of A is set to one-half the sum of the value of L plus the value of H (2306); incorporating an IEEE Round Toward Zero procedure, as set forth in FIG. 24, the value of A is set to the value of H (2408); incorporating an IEEE Round Toward Positive Infinity procedure and the sign of C (2502) is positive, as set forth in FIG. 25, the value of A is set to the value of L (2512); incorporating an IEEE Round Toward Positive Infinity procedure, and the sign of C (2502) is negative, as set forth in FIG. 25, the value of A is set to the value of H (2514); incorporating an IEEE Round Toward Negative Infinity procedure and the sign of C (2602) is positive, as set forth in FIG. 26, the value of A is set to the value of H (2514); and incorporating an IEEE Round Toward Negative Infinity procedure and the sign of C (2602) is negative, as set forth in FIG. 26, the value of A is set to the value of L (2512). A third determining unit then determines a magnitude of a product value, IA * DI (108), represented by at least one electrical signal, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude I A * Di. Next, a fourth determining unit compares IA * DI with INI and generates a status (110), represented by at least one electrical signal, as follows: a divide status comprising "less than" if IA * DI is less than INI, "equal to" if IA * DI equals INI, and "greater than" if I A * DI is greater than INI. A fifth determining unit then determines a rounded result value R (112), relative to at least the fourth determining means and represented by at least one electrical signal, in the rounding precision in conformance with the desired rounding mode specified by the IEEE FPS, as follows: incorporating an IEEE Round To Nearest (Even) rounding mode, as set forth in FIG. 23, selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than" (2312). and equal to L if the divide status is "greater than" (2314); incorporating an IEEE Round To Nearest (Even) rounding mode, as set forth in FIG. 23, using the divide status of "equal to" further includes a step of setting R equal to L if the lsb of H (2310) is equal to one (2314), or setting R equal to H if the lsb of H (2310) is equal to zero (2312); incorporating an IEEE Round Toward Zero rounding mode, as set forth in FIG. 24, selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than" (2312), equal to L if the divide status is "greater than" (2314), or setting R equal to H if the divide status is "equal to" (2312); incorporating an IEEE Round Toward Positive Infinity rounding mode, as set forth in FIG. 25, selecting L or H using the divide status and wherein the sign of C (2502) is positive further includes a step of setting R equal to H if the divide status is "less than" (2312), equal to L if the divide status is "greater than" (2314), or setting R equal to L if the divide status is "equal to" (2314); incorporating an IEEE Round Toward Positive Infinity rounding mode, as set forth in FIG. 25, selecting L or H using the divide status and wherein the sign of C (2502) is negative further includes a step of setting R equal to H if the divide status is "less than" (2312), equal to L if the divide status is "greater than" (2314), or setting R equal to H if the divide status is "equal to" (2312); incorporating an IEEE Round Toward Negative Infinity rounding mode, as set forth in FIG. 26, selecting L or H using the divide status and wherein the sign of C (2602) is positive further includes a step of setting R equal to H if the divide status is "less than" (2312), equal to L if the divide status is "greater than" (2314), or setting R equal to H if the divide status is "equal to" (2312); and incorporating an IEEE Round Toward Negative Infinity rounding mode, as set forth in FIG. 26, selecting L or H using the divide status and wherein the sign of C (2602) is negative further includes a step of setting R equal to H if the divide status is "less than" (2312), equal to L if the divide status is "greater than"(2314), or setting R equal to L if the divide status is "equal to" (2314). Another embodiment of the present invention incorporates a truncation of I A * DI to the precision of INI (114) after determination of I A * DI, determination of whether the inexact status, as defined by the IEEE FPS, of the truncated IA * DI is set or clear (116), obtaining the divide status (110), and determining R (112), represented by at least one electrical signal, as follows: incorporating an IEEE Round Toward Zero procedure, as set forth in FIG. 27, the value of the rounded result R (112) is determined as follows: for a divide status of "greater than," R is set equal to the value of L (2314), for a divide status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a divide status of "equal to," and a clear inexact status bit, R is set equal to the value of H (2312), and for a divide status of "less than," R is set equal to the value of H (2312); incorporating an IEEE Round To Nearest (Even) procedure. as set forth in FIG. 28, the value of the rounded result R (1 12) is determined as follows: for a divide status of "greater than," R is set equal to the value of L (2314), for a divide status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a divide status of "equal to," a least significant bit of H = 0 (2310), and a clear inexact status bit, R is set equal to the value of H (2312), for a divide status of "equal to," a least significant bit of H = 1 (2310), and a clear inexact status bit, R is set equal to the value of L (2314), and for a divide status of "less than," R is equal to the value of H (2312), and incorporating an IEEE Round Toward Positive Infinity procedure where the sign of C is positive as set forth in FIG. 29A and 29B, the value of the rounded result R (112) is determined as follows: for a divide status of "less than," R is set equal to the value of H (2312), and for a divide status of "greater than" or "equal to," R is set equal to the value of L (2314). incorporating an IEEE Round Toward Positive Infinity procedure where the sign of C is negative as set forth in FIG. 29A and 29B, the value of the rounded result R (112) is determined as follows: for a divide status of "greater than," R is set equal to the value of L (2314), for a divide status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a divide status of "equal to," and a clear inexact status bit, R is set equal to the value of H (2312), and for a divide status of "less than," R is set equal to the value of H (2312); incorporating an IEEE Round Toward Negative Infinity procedure where the sign of C is positive as set forth in FIG. 30A and 30B, the value of the rounded result R (112) is determined as follows: for a divide status of "greater than," R is set equal to the value of L (2314), for a divide status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a divide status of "equal to," and a clear inexact status bit, R is set equal to the value of H (2312), and for a divide status of "less than," R is set equal to the value of H (2312); incorporating an IEEE Round Toward Negative Infinity procedure where the sign of C is negative, as set forth in FIG. 30A and 30B, the value of the rounded result R (112) is determined as follows: for a divide status of "less than," R is set equal to the value of H (2312), and for a divide status of "greater than" or "equal to," R is set equal to the value of L (2314). FIG. 2, generally depicted by the numeral 200, illustrates one embodiment of steps executed by a high speed processor (HSP) incorporating a method of the present invention for rounding an output C (202) of a rounding precision having a least significant bit, the rounding precision typically specified by a precision given in the IEEE 754-1985 binary floating point arithmetic standard, hereafter referenced as IEEE FPS, utilizing a desired rounding mode defined by a IEEE FPS rounding mode, the output generated by remainderless square root determination utilizing an input value S, having a magnitude, ISI, and a sign. Certain terms, as used herein, are defined as stated above: trunc (x), nextaway (x), and the nextafter function. A first data storage and manipulation unit obtains and utilizes an output C, represented by at least one electrical signal and generated by remainderless square root determination, implementing an input value S, having a magnitude, ISI, and a sign, wherein C has a magnitude, a sign conforming to the IEEE FPS, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, and C is in an extended precision or a modified mode simulating extended precision wherein the extended precision has a greater precision than the rounding precision (202). A first determining unit generates at least one of two rounding values L and H, each having a magnitude, a sign, and being represented by at least one electrical signal, and H having a least significant bit (lsb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the rounding mode specified by the IEEE FPS ( 104). Single extended precision, double extended precision, as well as higher extended precisions may be utilized as the extended precision. The magnitude of L is less than the magnitude of H, and the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision. The first determining unit determines the rounding values L and H (104) as follows: incorporating an IEEE Round To Nearest (Even) procedure, as set forth in FIG. 15 and FIG. 31, the rounding value L is equal to trunc (C) (2304); incorporating an IEEE Round To Nearest (Even) procedure, as set forth in FIG. 16 and FIG. 31, the rounding value H is equal to nextaway (L) (2304); incorporating an IEEE Round Toward Zero procedure as set forth in FIG. 17 and FIG. 32, or an IEEE Round Toward Negative Infinity procedure as set forth in FIG. 21 and FIG. 32, where the round bit of C (2402) is set, the rounding value H is equal to nextaway [trunc(C)], and the rounding value L is equal to nextafter (H,0) (2404); incorporating an IEEE Round Toward Zero procedure as set forth in FIG. 18 and FIG. 32, or an IEEE Round Toward Negative Infinity procedure as set forth in FIG. 22 and FIG 32, where the round bit of C (2402) is clear, the rounding value H is equal to trunc(C),and the rounding value L is equal to nextafter (H,0) (2406); incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 19 and FIG. 33, where the round bit of C (2402) is set, the rounding value L is equal to nextaway [trunc(C)], and the rounding value H is equal to nextaway (L) (2504); and incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 20 and FIG. 33, where the round bit of C (2402) is clear, the rounding value L is equal to trunc(C), and the rounding value H is equal to nextaway (L) (2506). A second determining unit then determines A (106) as follows: incorporating an IEEE Round Toward Zero procedure or an IEEE Round Toward Negative Infinity procedure, as set forth in FIG. 32, the value of A is set to the value of H (2408); incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 33, the value of A is set to the value of L (2512); A third determining unit then determines IA * Al (204) by multiplying the intermediate value A times itself to obtain a magnitude I A * Al. Next, a fourth determining unit compares IA * Al with ISI and generates a status (206) as follows: a square root status comprising "less than" if IA * Al is less than ISI, "equal to" if IA * Al equals ISI, and "greater than" if IA * Al is greater than ISI. A fifth determining unit then determines a rounded result value R (112) in the rounding precision in conformance with the desired rounding mode specified by the IEEE FPS, as follows: incorporating an IEEE Round To Nearest (Even) rounding mode, as set forth in FIG. 31, selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" (2312), and equal to L if the square root status is "greater than" (2314); incorporating an IEEE Round To Nearest (Even) rounding mode, as set forth in FIG. 31, using the square root status of "equal to" further includes a step of setting R equal to L if the lsb of H (2310) is equal to one (2314), or setting R equal to H if the lsb of H (2310) is equal to zero (2312); incorporating an IEEE Round Toward Zero or an IEEE Round Toward Negative Infinity rounding mode, as set forth in FIG. 32, selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" (2312), equal to L if the square root status is "greater than" (2314), or setting R equal to H if the square root status is "equal to" (2312), and incorporating an IEEE Round Toward Positive Infinity rounding mode, as set forth in FIG. 33, selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than"(2312), equal to L if the square root status is "greater than" (2314), or setting R equal to L if the square root status is "equal to" (2314). Another embodiment of the present invention incorporates a truncation of IA * Al to the precision of ISI (208) after determination of IA * Al (204), determination of whether the inexact status, as defined by the IEEE FPS, of the truncated I A * Al is set or clear (210), obtaining the square root status (206), and determining R (112) as follows: incorporating an IEEE Round Toward Zero procedure or a Round Toward Negative Infinity, as set forth in FIG. 35, the value of the rounded result R (112) is determined as follows: for a square root status of "greater than," R is set equal to the value of L (2314), for a square root status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a square root status of "equal to," and a clear inexact status bit, R is set equal to the value of H (2312), and for a square root status of "less than," R is set equal to the value of H (2312); incorporating an IEEE Round To Nearest (Even) procedure, as set forth in FIG. 34, the value of the rounded result R ( 112) is determined as follows: for a square root status of "greater than," R is set equal to the value of L (2314), for a square root status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a square root status of "equal to," a least significant bit of H = 0 (2310), and a clear inexact status bit, R is set equal to the value of H (2312), for a square root status of "equal to," a least significant bit of H = 1 (2310), and a clear inexact status bit, R is set equal to the value of L (2314), and for a square root status of "less than," R is equal to the value of H (2312), and incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 36, the value of he rounded result R (112) is determined as follows: for a square root status of "less than," R is set equal to the value of H (2312), and for a square root status of "greater than" or "equal to," R is set equal to the value of L (2314). for a square root status of "equal to," R is set equal to the value of L (2314). FIG. 37, generally depicted by the numeral 3700, illustrates a block diagram of a computer hardware implementation of the invention. In one embodiment the first data storage and manipulation unit obtains the inputs, INI, D, and C for remainderless division, and ISI and C for remainderless square root determination and sends those values to the program control unit (3702). The said values traverse the bus (3710), and are placed in memory (3712). The ALU (3706) performs the computations as previously described, utilizing the status register (3708) to indicated inexact status. The program memory (3704) maintains the instructions for carrying out the invention. A first determining unit in the ALU (3706) generates L and H as previously described. The second determining unit in the ALU (3706) determines A as previously described, a third determining unit in the ALU (3706) determines IA*DI or IA*AI as previously set forth, a fourth determining unit in the ALU (3706) determines the divide status or the square root status as described above, and a fifth determining unit in the ALU (3706) selects the correct rounding result R as previously described. In another embodiment, as in FIG. 23 - 36, a digital signal processing method of the present invention for generating IEEE 754-1985 binary floating point arithmetic standard, hereafter designated IEEE FPS, compliant remainderless division and square root determination outputs in systems utilizing those operations allocates at least one first data storage and manipulation device for selection, storage, and manipulation of an output value C from a remainderless division of a dividend value N and a divisor value D, or a remainderless square root determination of an input value S (102, 202), utilizing a dividend value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign, or by remainderless square root determination utilizing an input value S, having a magnitude, ISI. That method allocates at least one data storage and manipulation device for manipulating the output value C to obtain at least one of two possible rounding values, H and L, one that will be compliant with the IEEE FPS (104), and further allocates at least one data storage and manipulation device for manipulating at least one of the possible rounding values, H and L, to determine an intermediate value A. The method also allocates at least one data storage and manipulation device for obtaining a magnitude of a product of the intermediate value A and a predetermined checking value in the following manner: for remainderless division, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude I A * D I or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude IA * Al. The method allocates at least one data storage and manipulation device for obtaining a comparison output of the magnitude of the product IA * DI or IA * Al with a second predetermined checking value as follows: for a remainderless division algorithm, a divide status comprising "less than" if IA * DI is less than INI, "equal to" if IA * DI equals INI, and "greater than" if IA * DI is greater than INI, and for a remainderless square root algorithm, a square root status comprising "less than" if IA * Al is less than ISI, "equal to" if IA * Al equals ISI, and "greater than" if I A * Al is greater than ISI. The method further allocates at least one data storage and manipulation device for selecting the possible rounding value R relative to at least the comparison output such that the rounding value corresponds to the output value C rounded in compliance with the IEEE FPS. The selection of R will be dependent on other factors, as stated above. In another embodiment a system utilizes the method of the invention to enable correlation of rounding an output C from remainderless division or remainderless square root determination with an IEEE 754-1985 binary floating point arithmetic standard, hereafter designated IEEE FPS, utilizing control signal sets and inputs, and process control devices responsive to control signal sets for controlling the computation process. Control signal sets and inputs include, among others, for remainderless division inputs values of a dividend value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign, and an output value C or for remainderless square root determination an input value S, having a magnitude, ISI, and a sign, and an output value C. Process control devices and a plurality of sensors include manipulation and data storage devices for carrying out the procedures set forth in the flow diagrams described above. A controller includes at least one manipulation device for utilizing the input values to obtain a rounding value corresponding to the output value C rounded in compliance with the IEEE FPS, according to the method of the invention described above. It will be apparent to one skilled in the art that: the present invention may be entirely embodied in the ALU itself, the status determining step may be accomplished in many fashions, including subtraction, the least significant bit of L may be alternatively utilized to determine a rounded result in conformance with the IEEE FPS, and the divide and square root status determinations may be otherwise designated. Although FIG. 3 through Fig. 22 would appear to indicate that the difference between the approximation C and an infinitely precise result P is required to be less than one-half of an lsb for proper operation of this invention, the actual difference between C and P must be one-quarter of an lsb. The resolution between adjacent numbers changes when an exponent, as defined by the IEEE FPS, changes by one. As the IEEE exponent increments, the resolution of the significand, as defined in the IEEE FPS, is cut in half. Thus the difference between the infinitely precise result P and the approximation C must be less than one-half of an lsb of the smallest resolution, or equivalently, that difference must be less than one-quarter of an lsb of a coarser resolution so that that difference is less than one-half lsb of a finer resolution. What is claimed is:

Claims: CLAIMS 1. A digital arithmetic unit for a high speed processor (HSP) for performing a set of mathematical operations to obtain a value R in conformance with a IEEE 754-1985 binary floating point arithmetic standard, hereafter referenced as IEEE FPS, of rounding pursuant to acquiring an output value C, in extended precision, in response to a remainderless division utilizing a signed dividend value N, having a magnitude, |N|, and a sign, and a signed divisor value D, having a magnitude, |D|, and a sign, or in response to a remainderless square root determination utilizing an input value S, having a magnitude, |S|, and a sign, characterized by: A) first data storage and manipulation means for manipulating and storing the output value C such that C has a magnitude, a sign, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, C being in an extended precision where the extended precision has a greater precision than the rounding precision; B) first determining means responsive to the first data storage and manipulation means for generating at least one of two rounding values L and H, each having a magnitude and a sign, and H having a least significant bit (lsb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS; C) second determining means responsive to the first data storage and manipulation means and to the first determining means for generating an intermediate value A related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS; D) third determining means responsive to the second determining means for generating a magnitude of a product value: for remainderless division, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude | A * D | or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude I A * A I; E) fourth determining means responsive to the third determining means for generating, for a remainderless division algorithm, a divide status comprising "less than" if |A * D| is less than |N|, "equal to" if |A * D| equals |N|, and "greater than" if |A * D| is greater than |N|, and for generating, for a remainderless square root algorithm, a square root status comprising "less than" if |A * A| is less than |S|, "equal to" if |A * A| equals |S|, and "greater than" if |A * A| is greater than |S|; F) fifth determining means responsive to the first determining means relative to at least the fourth determining means, for selecting L or H from step (B) above relative to at least the divide status or the square root status in step (E) as a rounded result value R in the rounding precision in conformance with the desired IEEE FPS rounding mode. 2. The HSP of claim 1 , wherein the extended precision is one of: single extended precision and double extended precision. 3. The HSP of claim 1, wherein the rounding precision is one of: single precision and double precision. 4. The HSP of claim 1 , wherein one of: the magnitude of L is less than the magnitude of H; the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision. 5. The HSP of claim 1 , wherein one of: A) for remainderless division incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is trunc (C) and the rounding value H is equal to nextaway (L); the value of A is set to one-half the sum of the value of L plus the value of H; selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than" and equal to L if the divide status is "greater than"; and using the divide status of "equal to" further includes a step of setting R equal to L if the lsb of H is equal to one, or setting R equal to H is the lsb of H is equal to zero; B) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc (C)] and L = nextafter (H.0); the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;" C) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and L = nextafter (H,0); the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;" D) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set and the sign of C is positive, the value of L is equal to nextaway [trunc(C)] and H ■ nextaway (L); wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" E) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear and the sign of C is positive, the value of L is equal to trunc(C) and H = nextaway ( ); wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" F) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set and the sign of C is negative, the value of H is equal to nextaway [trunc(C)] and L = nextafter (H,0); wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;" G) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear and the sign of C is negative, the value of H is equal to trunc(C) and L = nextafter (H.O); wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" H) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is set and the sign of C is positive, the value of H is equal to nextaway [trunc(C)] and L ■ nextafter (H,0); and wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;" I) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is clear and the sign of C is positive, the value of H is equal to trunc(C) and L - nextafter (H.O); wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;" J) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is set and the sign of C is negative, the value of L is equal to nextaway [trunc(C)] and H = nextaway (L); wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" and K) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is clear and the sign of C is negative, the value of L is equal to trunc(C) and H = nextaway (L); wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to." 6. The HSP of claim 1 , wherein one of: A) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is equal to trunc (C); the value of A is set to one-half the sum of the value of L plus the value of H; selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to L if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the lsb of H is equal to one, or setting R equal to H if the lsb of H is equal to zero; B) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value H is equal to nextaway [trunc (C)]; the value of A is set to one-half the sum of the value of L plus the value of H; selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the lsb of H is equal to one, or setting R equal to H if the lsb of H is equal to zero; C) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc(C)] and the rounding value L is equal to nextafter (H,0); the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;" D) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and the rounding value L is equal to nextafter (H,0); the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;" E) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set, the rounding value L is equal to nextaway [trunc(C)] and the rounding value H is equal to nextaway (L); the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to;" and F) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear, the rounding value L is equal to trunc(C) and the rounding value H is equal to nextaway (L); the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to." 7. A method of rounding outputs to a rounding precision having a least significant bit, the rounding precision typically specified by a precision given in the IEEE 754-1985 binary floating point arithmetic standard, hereafter referenced as IEEE FPS, utilizing a desired rounding mode defined by a IEEE FPS rounding mode, the output C generated by remainderless division utilizing a dividend value N, having a magnitude, |N|, and a sign, and a divisor value D, having a magnitude, |D|, and a sign, or by remainderless square root determination utilizing an input value S, having a magnitude, |S|, and a sign, the said method comprising the steps of: A) obtaining an output value C that has a magnitude, a sign conforming to the IEEE FPS, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, C being in an extended precision wherein the extended precision has a greater precision than the rounding precision, C being obtained from an indicated remainderless division algorithm utilizing a signed dividend value N and a signed divisor value D or a remainderless square root algorithm utilizing an input value S, and the signed output value C being represented by at least one electrical signal; B) generating at least one of two rounding values L and H, each having a magnitude and a sign, and H having a least significant bit (lsb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the rounding mode specified by the IEEE FPS, and represented by at least one electrical signal; C) generating an intermediate value A related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS, and represented by at least one electrical signal; D) generating a magnitude of a product value: for remainderless division, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude | A * D [ or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude | A * A |, wherein |A * D| or |A * A I is represented by at least one electrical signal; E) generating, for a remainderless division algorithm, a divide status comprising "less than" if |A * D| is less than |N|, "equal to" if |A * D| equals |N[, and "greater than" if |A * D| is greater than |N|, and generating, for a remainderless square root algorithm, a square root status comprising "less than" if |A * A| is less than |S|, "equal to" if |A * A| equals |S|, and "greater than" if |A * A| is greater than |S|, the status generated being represented by at least one electrical signal; F) selecting L or H from step (B) above relative to at least the divide status or the square root status in step (E) as a rounded result value R in the rounding precision in conformance with the desired rounding mode specified by the IEEE FPS, the rounded result value R selected being represented by at least one electrical signal. 8. The method of claim 7, wherein the extended precision is one of: single extended precision and double extended precision. 9. The method of claim 7, wherein the rounding precision is one of: single precision and double precision. 10. The method of claim 7, wherein one of: the magnitude of L is less than the magnitude of H; the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision. 1 1 . The method of claim 7, wherein one of: A) for remainderless division incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is trunc (C) and the rounding value H is equal to nextaway (L); the value of A is set to one-half the sum of the value of L plus the value of H; selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than" and equal to L if the divide status is "greater than"; and using the divide status of "equal to" further includes a step of setting R equal to L if the lsb of H is equal to one, or setting R equal to H is the lsb of H is equal to zero; B) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc (C)] and L - nextafter (H,0); the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;" C) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and L « nextafter (H.O); the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;" D) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set and the sign of C is positive, the value of is equal to nextaway [trunc(C)] and H = nextaway (L); wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" E) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear and the sign of C is positive, the value of L is equal to trunc(C) and H = nextaway (L); wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" F) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set and the sign of C is negative, the value of H is equal to nextaway [trunc(C)] and L = nextafter (H,0); wherein the sign of C is negative, the value of A is set to the value of H; and selecting or H using the divide status and wherein the sign of C is negative further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;" G) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear and the sign of C is negative, the value of H is equal to trunc(C) and L = nextafter (H.O); wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" H) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is set and the sign of C is positive, the value of H is equal to nextaway [trunc(C)] and L - nextafter (H,0); and wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;" I) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is clear and the sign of C is positive, the value of H is equal to trunc(C) and L - nextafter (H,0); wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;" J) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is set and the sign of C is negative, the value of L is equal to nextaway [trunc(C)] and H = nextaway (L); wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" and K) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is clear and the sign of C is negative, the value of L is equal to trunc(C) and H = nextaway (L); wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to." 12. The method of claim 7, wherein one of: A) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is equal to trunc (C); the value of A is set to one-half the sum of the value of L plus the value of H; selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to L if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the lsb of H is equal to one, or setting R equal to H if the lsb of H is equal to zero; B) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value H is equal to nextaway [trunc (C)); the value of A is set to one-half the sum of the value of L plus the value of H; selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to if the lsb of H is equal to one, or setting R equal to H if the lsb of H is equal to zero; C) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc(C)] and the rounding value L is equal to nextafter (H,0); the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;" D) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and the rounding value L is equal to nextafter (H,0); the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;" E) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set, the rounding value L is equal to nextaway [trunc(C)] and the rounding value H is equal to nextaway (L); the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to;" and F) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear, the rounding value L is equal to trunc(C) and the rounding value H is equal to nextaway (L); the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to."

Inventors: LINDSLEY BRETT LOUIS, LIU CLIF, LINDSLEY, BRETT, LOUIS, LIU, CLIF
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1990
Main classification: G06F7
IPC codes: G06F7