Semiconductor memory having improved data readout scheme

Abstract: A semiconductor memory device capable of readouting stored data at a high speed and with low power consumption is disclosed. The semiconductor device comprises a sense amplifier for amplifying a data signal stored in a selected memory cell, a data latch circuit for latching the output signal of the sense amplifier, a switching circuit for outputting the output signal of the data latch circuit, and an output circuit for receiving the output signal of the sense amplifier and the output signal of the switching circuit and generating a data output signal. It further comprises at the power supply side switcing means for keeping the sense amplifier in operative state as long as data signal is amplified in response to a sense enable signal.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a semiconductor memory, and more particularly to a readout circuit of a static memory. Description of the Prior Art A known data readout circuit for a static memory disclosed in U.S. Patent No. 4,766,572 is constructed on the basis of knowledge that a signal readout from a memory cell and amplified by a sense amplifier is transferred through a data latch circuit to an output circuit, and the delay associated with the activation of the data latch circuit is principal cause for the delay of data output, in such way that both the signal amplified by the sense amplifier and the output signal of the data latch circuit are applied to a switching circuit, and then the output of the switching circuit is supplied to the output circuit. During the sense amplifier is maintained operative, the switching circuit allows transfer and output of the amplified signal. Once the sense amplifier is deactivated, it transfers the output of the data latch circuit to output it to the output circuit. Thus the output signal is held at the data output terminal of the memory. In other words, the amplified signal from the sense amplifier is supplied to the output circuit before the data latch circuit is operated, and earlier according to such, output signal appears at the output terminal, with effect of reducing period of time between application of an address onto the memory and appearance of data output, that is access time. While the output of the data latch circuit is transferring, the switching circuit disconnects the output terminal thereof from the output terminal of the sense amplifier because of preventing the change in the potential at the output terminal of the sense amplifier resulting from the deactivation of the sense amplifier from affecting adversely the output of the switching circuit, that is, the output of the data latch circuit supplied to the output circuit. Increment of memory capacity and improvement in operating speed are required endlessly. The readout speed of the above-mentioned prior art has been dissatisfactory in these days, too. SUMMARY OF THE INVENTION Objects of the Invention It is an object is to provide a semiconductor memory capable of readouting data at higher speed. Another object of the invention is to provide a semiconductor memory having an improved construction of readout circuit. The present invention is based on the knowledge of the readout circuit disclosed in U.S. Patent No. 4,766,572, that when the amplified signal is transferred from the sense amplifier through the switching circuit to the output circuit, considerable delay results because of the switching circuit. The switching circuit causes prolongation of the data (output) readout time by the sum of the time it takes for the switching gate permitting the transfer of the amplified signal to turn ON and the time it takes for the amplified signal to pass through the transfer gate. According to an embodiment of the invention, means are provided for disconnecting the output terminal of the sense amplifier from power supply when it is deactivated so as to prevent inducing variation in the potential of the output terminal. The disconnection means makes it unnecessary to provide a switching gate between the output terminal of sense amplifier and the input terminal of the output circuit. Therefore, the output terminal of the sense amplifier is directly connected to the input terminal of the output circuit without the intermediation of switching gate. The output terminal of the sense amplifier is connected, for one thing, to the input terminal of the data latch circuit, and the output of the data latch circuit is connected to the input terminal of the output circuit through the switching gate of the switching circuit. When the switching gate of the switching circuit is in ON state, therefore, high impedance state is made between the output terminal of the sense amplifier and two terminals of the power supply. The semiconductor memory according to the invention is defined in claim 1. Another preferred embodiment of the present invention is defined in claim 2. The invention has the advantage that the output signal of the sense amplifier can be applied to the output circuit without any delay, and this not only contributes to reducing the time it takes for readout data to appear at the output terminal of the output circuit or the data output terminal but also thereby enables faster data readout. BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other objects, features and advantages of this invention will become more apparent reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a block diagram of a semiconductor memory in the prior art; Fig. 2 is a schematic diagram of the switching circuit in Fig. 1; Fig. 3 is a schematic diagram of the memory cell matrix in Fig. 1; Fig. 4 is a timing diagram illustrative of readout operation from the prior art semiconductor memory; Fig. 5 is a block diagram of a first embodiment of semiconductor memory embodying the present invention; Fig. 6 is a schematic circuit diagram of the memory cell matrix in Fig. 5; Fig. 7 is a schematic diagram of the switching circuit in Fig. 5; Fig. 8 is a timing diagram illustrative of readout operation from the semiconductor memory in Fig. 5; Fig. 9 is a circuit diagram schematically illustrating the memory cell matrix which is a component of a second embodiment of the present invention; Fig. 10 is a schematic diagram of the data latch circuit which is a component of the second embodiment; and Fig. 11 is a schematic diagram of the switching circuit which is a component of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION Out of the operation of the prior art memory readout circuit disclosed in U.S. Patent No. 4,766,572, the part involving the present invention will be described below referring to Figs. 1 through 4. The other part is detailed in the same U.S. Patent. Referring to Figs. 1 and 4, an address buffer 101 detects change of address signal A i and outputs address change detection signal  i for a certain period as of 10 ns to a clock generator 113 and at the same time outputs complementary address buffer signals A i ′ and A i ′ to a X decoder 105 and Y decoder 106. A chip select buffer 102, upon receiving chip select signal CS , outputs chip select change signal  CS for a certain period to the clock generator 113 and simultaneously outputs chip select buffer signal CS′ to a data input control circuit 108 and a data output control circuit 112. When no write enable signal WE is input, signal WE′ from a write enable buffer and the signal CS′ activate the data control circuit 112 which outputs the input signal receiving at the input end of it from the output terminal D OUT of it. When write enable signal WE is input, write enable buffer 104 outputs WE′ without outputting WE′. Thus the data output control circuit 112 does not operated. Instead the data input control circuit 108 is operated and applied to data input terminal D IN . Then complementary data input buffer signals D′ IN and D′ IN produced in a data input buffer 103 are supplied from there to the memory cell matrix 109. Clock generator 113 receives two change detection signal  i and  CS and generates in turn four control signals  X ,  S ,  SW and  L as shown in Fig. 4. The clock generator firstly generates a word line activating signal  X which is supplied to a word line drive circuit 107. After the lapse of a certain period, it generates sense enable signal  S , which activates a sense amplifier in the memory cell matrix 109. After the lapse of another certain period, it also cause a switching signal  SW to rise and supplies the resulting signal to the switching circuit 114. After the lapse of a further certain period, it finally outputs a data latch signal  L to the data latch circuit 110 which is operated. The four control signals  L ,  S ,  SW , and  X drop in turn. Word line drive circuit 107 supplies X address signal X i from X address decoder 105 to word line W i as long as word line activating signal  X stays at high level. Referring to Fig. 3, in memory cell matrix 109, each bit line pair B L0 , B L0 , ..., B Li , B Li , ... get precharged to high level through a p-channel precharge transistor Q₉₁ from power supply Vcc. Y address signal Y i from Y address decoder 106 causes one of CMOS transfer gates 902, 902 to turn ON and one of the bit line pair (in this prior art, BL i and BL i ) is connected to a pair of data lines DB and DB′ of the sense amplifier 903. As the result, both input transistors Q₈₀ and Q₈₁ sense amplifier 903 turn ON. Since the activating signal  S is at low level, however, n-channel transistor Q₈₂ is in OFF state, and so no current flows. Electric charge is supplied from power supply Vcc through p-channel transistors Q₈₃ and Q₈₄ connected to form a current mirror circuit output, and thus the output terminal of input transistor Q₈₀ is at high level. This is received by n-channel transistor Q₈₆ of an inverter, which is in ON state. Accordingly the output terminal of the inverter, that is the output terminal RB of sense amplifier 903 is at low level. The rise of word line activating signal  X causes X address signal X i to be supplied to word line W i , and in turn, memory cell 901 is selected. In response to this memory contents, a pair of bit lines BL i and BL i change in potential. Now assuming that BL i change to low level and BL i is kept at high level, then as shown in Fig. 4, change of  x causes change of bit line BL . While the data line DB of sense amplifier 903 stays high level, DB goes to low level, input transistor Q₈₀ turns ON, and input transistor Q₈₁ turns OFF. Then sense amplifier activating signal  S rises, causing activating transistor Q₈₂ to turn ON, resulting, in turn, in change of the output terminal of input transistor Q₈₀ to low level, in turn-off of n- channel transistor Q₈₆ and turn-on of p-channel transistor Q₈₅ of the inverter, and in application of the high level of the power supply Vcc to output terminal RB. In this way the output data of the selected cell within memory cell matrix 109 is amplified by sense amplifier 903 and output as an amplified signal RB. Output signal RB of the sense amplifier is supplied to both data latch circuit 110 and switching circuit 114. In response to data latch signal  L , data latch circuit 110 is activated and the output LB of it rises. Referring to Fig. 2 as well, both the output RB of the sense amplifier and the output LB of the data latch circuit are input into the switching circuit 114. In switching circuit 114, each input is connected to a common output SB through the first CMOS transfer gate consisting of n-channel transistor Q₂₀ and p-channel transistor Q₂₁ and the second CMOS transfer gate consisting of n-channel transistor Q₂₃ and p-channel transistor Q₂₄, respectively. While switcing control signal  SW is held at low level (before it rises), the second CMOS transfer gate is in ON state, and thus signal LB from the data latch circuit is supplied as switcing output SB to data output circuit 112. Rise (change to high level) of switching control signal  SW causes the second CMOS transfer gate to turn OFF, and instead the first CMOS transfer gate to turn ON, and thus signal RB from the sense amplifier is supplied as switching output SB to data output circuit 112. As shown in Fig. 4, in response to sense amplifier output RB, switching output SB rises and in turn, also output data D OUT rises and is output as a high level data. After data latch signal  L is dropped, data latch circuit 110 still holds its output LB at high level. Then trailing switching control signal  SW causes the first and second CMOS transfer gates of switching circuit 114 to turn OFF and ON, respectively, and thus the switching output SB (which corresponds to inputs into data output circuit 110) is switched from sense amplifier output RB into latch circuit output LB. The data contents (high level) of it however remains unchanged. Then sense amplifier activating signal  S drops, and causes transistor Q₈₂ in sense amplifier 903 (Fig. 3) to turn OFF, resulting in return of the output of transistor Q₈₀ back to high level, which causing sense amplifier output RB to go to low level. By this change of RB, however, owing to that the first CMOS transfer gate of switching circuit 114 is in OFF state, switching circuit output SB is unaffected, and therefore both latch output LB and data output circuit 112 remain unchanged. Referring to Fig. 4, readout of data output D OUT begins under the timing determined by the time when input of data output circuit (switching output SB in this prior art) begins to change. Readout output from the memory cell matrix, that is, sense amplifier output RB, begins to change a period D₀ earlier than does so switching output SB. In other words, this prior art has an disadvantage that input into the data output circuit delays by period D₀ with respect to the data readout from the sense amplifier. This delay D₀ is expressed as D₁ + D₄, where D₁ is the delay until the rise of switching signal  SW and D₄ is the time it takes for the first CMOS transistor gate of switching circuit 114 to turns ON and then for sense amplifier output RB to transfer therethrough. On assumption that the equivalent resistance when both transistors Q₂₀ and Q₂₁ in Fig. 2 which constitute the first CMOS transfer gate are in ON state is 1 KΩ, and the capacity of the switching output bus line SB is 3 pF, then delay time induced by the pass of the signal through the first CMOS transfer gate amounts to about 3 nS. It is noted that upon comparison with the access time of the semiconductor memory, assuming such as 30 nS, delay D₀ is considerable. DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to Figs. 5 through 8, a first embodiment of the invention will be described below: Referring to Figs. 5 and 6, the first embodiment is different from the prior art illustrated in Figs. 1 through 3 in the following respects: The construction of a sense amplifier 503 within a memory cell matrix 509, the construction of a switching circuit 514, and the direct connection of sense amplifier output RB to a data output circuit 112. Correspondent parts or components are designated by the same reference characters and description of them is omitted. The sense amplifier 503 of the first embodiment diagrammed schematically in Fig. 6 comprises input n-channel transistors Q₅₀ and Q₅₁ of which gates are connected to a pair of data lines DB and DB , respectively; input p-channel transistors Q₅₃ and Q₅₄ connected to the outputs of transistors Q₅₀ and Q₅₁, respectively, and constituting a current mirror circuit; and an activating n-channel transistor Q₅₂ of which the gate receives sense amplifier activating signal  S and the other electrodes each are connected to the common terminal of input transistors Q₅₀ and Q₅₁ and ground, respectively; and a breaking p-channel transistor Q₅₅ of which the gate receives sense amplifier activating signal  S through an inverter 400 and the other electrodes each are connected to the common source of p-channel transistors Q₅₃ and Q₅₄ and power supply Vcc, respectively. Since amplifier output RB outputs from the output terminal of input transistor Q₅₁. When enable signal  S is held at high level, transistors Q₅₂ and Q₅₅ are in ON state, and hence the sense amplifier is held in activated state, during which readout data from the memory cells on data bus lines DB and DB is amplified and the amplified data is output at sense amplifier output RB. When sense enable signal  S is held at low level, both n-channel transistor Q₅₂ and p-channel transistor Q₅₅ are in OFF state so that high impedance stands between sense amplifier output RB, and power supply Vcc and ground GND, respectively. The potential of sense amplifier output RB therefore remains unchanged even if  S changes to low level, and in turn, data output circuit 112 is unaffected. In accordance with the present invention, for this reason, sense amplifier output RB can be connected directly to data output circuit 112 without needing it to connect them through the transfer gate. Switching circuit 514 therefore, as shown in Fig. 7, comprises only transistors Q₂₃, Q₂₄ constituting the second CMOS transfer gate, and inverter 250, that is, those remaining as the result of the removal of Q₂₃, Q₂₄ constituting the second CMOS transfer gate from the prior art switching circuit shown in Fig. 2. In the following, the readout operation of this Example will be described ith reference to the timing diagram shown in Fig. 8 as well. When the semiconductor memory is executing selection at low level of chip select input signal CS , address decoder output signal X i and address decoder output Y j change with changing address signal A i . Once address signal A i changes, address change detection signal  i is generated, resulting, in sequential rise (from low level to high level) of word line clock signal  X , switching control signal  SW , sense enable signal  S and data latch signal  L . Rise of word line activating signal  X causes word line W i supplied with address decoder output signal X i , and nothing else, to rise from low level to high level, thereby data held in memory cell 901 begins to appear on bit lines BL, BL . On the other hand, only address decoder output signal Y j is selected, and in turn the only transfer gate 902 is opened. As the result, only the data of memory cell 901 is transferred to data bus lines DB, DB of sense amplifier 503. Rise of sense enable signal  S causes sense amplifier 503 to activate, and in turn, data corresponding to memory cell data appears on readout data RB of sense output. Slightly before memory data appears at readout data RB, switching control signal  SW rises, this causing transfer gate transistors Q₂₃, Q₂₄ between output LB of data latch 110 and latch output SB, that is, input of data output circuit 112 to turn OFF. Accordingly readout data appears, through sense amplifier 503, on readout data RB from sense amplifier and supplied directly to data output control circuit 112 without being disturbed by latch data LB. Then data D OUT of the same phase as that of readout data RB is output on the data output terminal. On the other hand, data latch signal  L rises after the lapse of a sufficient time following the appearance of readout data on readout data RB. Reason of delaying the timing of data latch signal  L resides in avoiding error due to noise pulses which may happen to appear on address signal A i . Rise of data latch signal  L causes, in data latch 110, transfer gate 226 to open, and readout sense amplifier output data RB is latched into flip-flop circuit 227, and data of the same phase as readout data RB is output to latch data LB. Then after the above-mentioned readout steps of data output D OUT complete, sequential drop of data latch signal  L , sense enable signal  S , switching control signal  SW , and word line activating signal  X are caused, thus serial readout operation finishes. The drop of sense enable signal  S turns transistors Q₅₂ and Q₅₅ OFF so that sense amplifier 503 becomes again high impedance state. Subsequently drop of switching control signal  SW causes transfer gate transistors Q₂₃, Q₂₄ of switching circuit 514 to turn ON so that data latch output LB is connected to input of data output circuit 112. Transfer gate transistors Q₂₃, Q₂₄ are in ON state, and hence latch output LB is connected to sense amplifier output RB, too. In sense amplifier 503, however, output terminal RB is in disconnected state to ground GND and power supply Vcc, and hence unchanged in potential, and in turn, latch data LB is unaffected. As the result, sense amplifier output RB can be applied directly to the data output circuit, this permitting delay D₀ of access time due to intermediate of the transfer gate of the switching circuit in the prior art to nullify. As described above, according to the prevent invention, high speed semiconductor memory device permitting in short access time can be realized by the construction that while sense amplifier is staying in nonoperative state, simultaneously sense amplifier is held in high impedance, state, as described above, so as to eliminate the transfer gate on the line which is a time delaying element or factor involved in access time. Description will be given on a second embodiment of the invention with reference to Figs. 9 through 11. For the purpose of allowing dual readout, the second embodiment comprises sense amplifier 1202 (Fig. 9) of memory cell matrix 1201, data latch 1301 (Fig. 10) and switching circuit 1401 (Fig. 11) each in place of sense amplifier 503 of memory cell matrix 509, data latch 110 and switching circuit 514, respectively, in Example 1. Sense amplifier 1202, as diagrammed schematically in Fig. 9, is a parallel arrangement of two sense amplifiers 503 stated in the first embodiment such that two types of data lines DB, DB are connected in inverted relation to allow readout data from the sense amplifier to form complementary signals, that is, positive phase RB and inverse phase RB . This construction permits realization of fast access time compared with Example 1. Likewise each of data latch 1301 and switching circuit 1401, as diagrammed schematically in Fig. 10 and 11, respectively, are parallel arrangements of two data latch 110 and switching circuit 514 stated in the first embodiment, respectively. Sense amplifier readout data RB, RB is applied in parallel to latch circuit 1301 and connected to switching outputs SB, SB . Latch outputs LB, LB are input in parallel into switching circuit 1401. Like the first embodiment, the second embodiment permits realization of semiconductor memory device having high speed access time by the construction of creating the state such that transfer gates on the lines which are involved in access time are removed. As described above, according to the invention permits realization of shorter access time in virtue of the construction that while data of data latch is being output, sense amplifier is held in such high impedance state that transfer gates on the lines which is a time delaying element or factor involved in access time were substantially eliminated.

Claims: A semiconductor memory comprising a sense amplifier (503, 1202) for amplifying a data signal read out from a selected memory cell (901), a latch circuit (110) for latching the output signal (RB, RB ) of said sense amplifier, a switching circuit (514, 1401) connected to the output terminal of said latch circuit, and an output circuit (112) having an input terminal connected to the output terminal of said switching circuit (514, 1401) and an output terminal for outputting a data output signal (D out ), characterized in that the input terminal of the output circuit is further directly connected to the output terminal of said sense amplifier (503, 1202) and in that the output circuit is adapted for receiving at least one of the ouput signal (RB, RB ) from said sense amplifier (503, 1202) and the output signal of said switching circuit (514, 1401) and in that said sense amplifier (503, 1202) includes means (Q52, Q55, 400) for making a high impedance between the output terminal of said sense amplifer and two terminals of a power supply. A semiconductor memory device as claimed in claim 1, wherein said sense amplifier (503, 1202) amplifies a data signal (DB, DB ) in response to a first control signal ( s ) and transfers the amplified data signal (RB, RB ) to said output terminal thereof; and said latch circuit (110) latches said amplified data signal (RB, RB ) in response to a second control signal ( L ) generated while said first control signal ( S ) is present; and said switching circuit turns ON and supplies the output signal (LB, LB ) of said latch circuit to said output circuit (112), in response to a third control signal ( SW ) during a desired period except the period when said first control signal ( S ) is present, wherein said high impedance is maintained between said output terminal of said sense amplifier and the two terminals of the power supply during a desired period of time except the period when said first control signal is present.

Inventors: KOBAYASHI YASUO C O NEC CORPOR, KOBAYASHI, YASUO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G11C7
IPC codes: G11C11, G11C7