Process for forming CMOS field effect transistors

Abstract: In a process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of p-channel and n-channel transistors, complementary transistors (14,16) are formed using a single photolithographic mask (13) and a fabrication sequence which begins with p-channel transistor source/drain (17) formation. Thereafter, the p-­ channel transistor source/drain regions are metalized (19), n-channel transistor lightly doped drain regions are formed, and sidewall dielectric (27) spaced n-­ channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-­ channel transistor source/drain metalization (19) suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types.

Description: This invention relates to processes of the kind for forming CMOS field effect transistor integrated circuits, including the steps of: forming in an active region of a semiconductor substrate first and second polysilicon gate electrodes with underlying gate dielectrics defining respective p-channel and n-channel field effect transistors. A process of the kind specified is known from US-A- 4,703,551. According to this known process, polysilicon gate structures having overhang masks are provided on a substrate and oxidized to form relatively thick sidewall oxide. Next, the PMOS device is masked and n+ source/drain regions are implanted, whereafter the sidewall oxide of the NMOS device is partially etched. Then the NMOS overhang mask is removed and a low energy implant effected to form LDD (lightly doped drain) regions. Next, the PMOS mask is removed, the NMOS device is masked, the p+ source and drain regions are implanted, the PMOS sidewall oxide is partially etched, the PMOS overhang mask is removed and an n+ PMOS guard band diffusion is formed around the PMOS LDD regions. Finally, a blanket p-type implant is effected to simultaneously form a guard band diffusion around the NMOS LDD region and form the PMOS LDD diffusion. The known process is complex and involves the use of a plurality of photolithographic masks. EP-A- 0 292 042 also discloses a process involving a plurality of photolitographic masks. It is an object of the present invention to provide a simple process of the kind specified which provides a high performance CMOS structure. Therefore, according to claim 1 of the present invention, there is provided a process of the kind specified including the steps of: forming a capping dielectric layer over said first and second polysilicon gate electrodes; forming a photolithographic mask over said second polysilicon gate electrode and associated field effect transistor source/drain regions; doping said substrate in the presence of said photolithographic mask to form source/drain regions in said semiconductor substrate aligned to said first polysilicon gate electrode and removing said mask; characterized by the steps of:; selectively forming metallic regions over said source/drain regions of said first polysilicon gate electrode; lightly doping source/drain regions of said second polysilicon gate electrode in alignment with said second polysilicon gate electrode, using said metallic regions as a mask; forming a sidewall dielectric for said second polysilicon gate electrode; and heavily doping said source/drain regions of said second polysilicon gate electrode in alignment with said sidewall dielectric, using said metallic regions as a mask. It will be appreciated that a process according to the invention has the advantage of being simple, in that only a single photolithographic mask is utilized, yet a high performance CMOS structure is achieved since the lower mobility of the p-type regions is compensated for by the metallic regions, while hot electron trapping effects in the n-channel device are compensated for by the lightly doped source/drain structure. Thus, a simple process achieves structurally asymmetric p-channel and n-channel devices, such that a high performance CMOS device is provided. In brief summary, a preferred practice of the present invention begins with the stage of CMOS field effect transistor fabrication at which patterned doped polysilicon gate electrodes are situated at appropriate locations within an active region of a semiconductor substrate and are separated from the substrate by a gate dielectric layer of silicon dioxide. According to the preferred process, the substrate with associated gate electrodes is thereupon subject to an oxidizing environment. During such oxidation, the heavily doped polysilicon electrodes oxide at nominally ten times the rate the undoped or very lightly doped substrate monocrystalline silicon undergoes oxidation. Thereafter, a photoresist layer is deposited and photolithographically processed to expose the gate electrode and source/drain regions of the p-channel transistor. A p-dopant implant is then accomplished to create self-aligned p-type source/drain regions. Next, an oxide etch is employed to remove the thin oxide layer over the surface of the source/drain region silicon without exposing the polysilicon gate electrode, this attributable to the differentially greater thickness of polysilicon based oxide. The single photoresist mask used in the present process is then stripped. A selective deposition of refractory metal such as tungsten, or a selective retention of refractory metal silicide follows, with such deposition or retention occurring solely in the regions of exposed silicon corresponding to the p-channel transistor source/drain regions. Such metal or silicide then serves as a mask to succeeding implants. An LDD dose implant with n-type impurity is then accomplished to form LDD source/drain regions in relative alignment with the n-channel gate electrode, while the p-channel source/drain regions are masked by the metalization. A conformal silicon dioxide deposition and succeeding anisotropic etch of such oxide to the substrate surface produces extended sidewall oxide regions for the n-channel transistor. A heavy dose n-type impurity doping by implant concludes the fabrication cycle, by forming source/drain regions in an electrical continuum to the LDD regions of the n-channel transistor. Fabrication of CMOS field effect transistors according to the present process minimizes the number of photolithographic masks required, produces a low resistivity shunting metallic region coextensive with the source/drain regions of the p-channel transistor and creates n-channel field effect transistors with integral LDD features. The concluding structure can be readily interconnected using conventional metalization techniques. One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which:- Figs. 1-10 are schematic cross sections of an active region in a semiconductor substrate at incremental stages of CMOS device fabrication practiced according to the features of the present invention. Fig. 1 illustrates by schematic cross section an embodying segment of a monocrystalline silicon substrate or wafer 1 with complementary transistor active regions shown generally at 2 separated by field oxide 10. A lightly doped n-well region 5 is also depicted. The substrate 1 has formed thereupon an oxide gate dielectric layer 3, approximately 17.5 nanometers thick, and individually patterned doped polysilicon gate electrodes 4 and 6, approximately 350 nanometers thick. Such structure represents the starting point for the process of the present invention. The impurity concentrations in polysilicon electrodes 4 and 6 is nominally 10²¹ ions per cubic centimeter of phosphorus. Substrate 1 and n-well region 5 are very lightly doped at conventional levels. As a first step in the preferred practice of the present invention, the substrate is subjected to an oxidation performed in a wet oxygen environment at approximately 950:C for approximately 75 minutes. The operation is preferably practiced to accentuate the differences in the oxidation rates between the very lightly doped substrate 1/well 5 and the heavily doped polycrystalline silicon electrodes 4/6, so that the thickness of the oxide 7 on the surface of substrate 1 is significantly less than that of oxides 8, 9, 11 and 12 grown onto the side and top surface of polysilicon electrodes 4 and 6. See Fig. 2. For instance, at the conclusion of the oxidation, oxide layer 7 is nominally 10 nanometers thick while oxides 8, 9, 11 and 12 are in the range of 100 nanometers thick. This dramatically different rate of oxidation is attributable to both the impurity concentrations in and the crystalline compositions of the respective materials. Photoresist 13 is then photolithographically patterned to cover the n-channel field effect transistor 14 gate electrode and source/ drain regions while exposing the same for p-channel transistor 16. As shown in Fig. 3, the source/drain regions 17 of p-channel transistor 16 are formed in alignment with gate electrode 4. P-type ions 18 are implanted through thin oxide 7 to form source/drain regions 17 in substrate 1 while photoresist 13 masks the n channel transistor at 14. Implantation is preferably performed through thin oxide 7 to protect the silicon surface of substrate 1 from implant damage. A representative implantation involves a dose of 5 X 10⁵ boron ions per square centimeter implanted with an energy of 30K electrons volts. The cross section illustrated in Fig. 4 shows the p-channel transistor 16 following etch of oxide 7, preferably an anisotropic etch, to expose the surface of the silicon substrate 1 in the source/drain regions 17 while retaining, as a consequence of the thicker layer, a residual silicon dioxide layer 18 over gate electrode 4 and sidewall oxide 8 on either side of gate electrode 4. Layer 18 should be at least 10 nanometers thick. Given the relative thicknesses of layers 7 and 9 (Fig. 3), the concluding thickness of layer 18 provides significant margin to moderate over-etch and preclean operations directed to the silicon surfaces at source/drain regions 17. The preferred use of an anisotropic etch retains the sidewall oxide layers 8 substantially intact, to ensure complete electrical separation between gate electrode 4 and source/drain regions 17 following metalization. An alternative practice of the etching operation would involve the use of a classic wet etch to remove all exposed oxide at a proportional rate. The wet etch is preferred where source/drain region surface damage must be minimized. Another practice of the invention in the context of the anisotropic oxide etch concluding with the structure in Fig. 4 would involve a continuation of the etch until oxide 18 is completely removed and the upper surface of polysilicon gate electrode 4 is exposed. This is a less desirable practice of the invention in that limited oxide-to-silicon selectivity of available anisotropic etch processes will produce measurable silicon surface erosion in source/drain regions 17, recessing the levels thereof. This practice would expose the surface of gate electrode 4 for selective deposition of metal or silicide formation. Fig. 5 shows the structure of the substrate following the strip of photoresist mask 13. Note, in particular, that according to the preferred practice of the invention gate electrode 4 of p-channel field effect transistor 16 as well as gate electrode 6 of n-channel field effect transistor 14 are fully enclosed within silicon dioxide, and further that the silicon surfaces of source/drain regions 17 of p-channel transistor 16 are exposed while the corresponding, yet to be formed, source/drain regions of the n-channel transistor 14 remain covered by silicon dioxide layer 7. Fig. 5 also portrays that the structure is relatively smooth and devoid of joints or cavities which might trap contaminates during the extensive cleaning commonly required to prepare for a selective deposition or formation of metalization. Selective deposition of a refractory metal follows, producing the structure illustrated in Fig. 6. Although selective deposition of tungsten is the preferred operation to form metalization 19 onto the exposed silicon of source/drain regions 17, it remains possible to substitute other refractory metal or silicide formation practices. The use of commercially available selective tungsten deposition equipment ensures that metal 19 forms only onto surfaces having exposed silicon. Stated in the alternative, the surfaces of silicon dioxide, or silicon nitride where applicable, do not provide nucleation sites for metal formation during such selective deposition. Note that if one alternate practice of the present invention were implemented, where oxide 18 is absent from the top surface of gate electrode 4, a selective deposition of metal would also occur on the top surface of polysilicon gate electrode 4. The illustrated practice of the invention is preferred in that the risk of a metal bridging between the metal overlying gate electrode 4 and metal 19 deposited onto source/drain regions 17 is eliminated. The concepts set forth above are fully applicable to refractory metals other than tungsten. Metalization 19 can also be selectively formed over source/drain regions 17 as a silicide of refractory metals such as titanium, cobalt, platinum, tungsten, or tantalum. According to this practice of the invention, the base metal is blanket deposited onto the structure depicted in Fig. 5 and then subjected to a thermal environment suitable to react such metal with the exposed silicon, forming a metallic silicide. A selective etch which removes the metal but not the silicide follows. An undesirable aspect of this method for forming the metalization 19, in contrast to the selective deposition of a refractory metal, is the stress introduced by the volumetric expansion of metalization 19 in the course of silicide compound formation. Fig. 7 illustrates the next stage in the preferred fabrication sequence. As shown, a low dose implant 21 of n-type dopant is undertaken to form lightly doped n-type regions 22 self-aligned to gate electrode 6 of n-channel field effect transistor 14. A preferable practice involves a dose of 5 X 10¹³ ions per square centimeter of phosphorus implanted with an energy of 40K electron volts to form LDD regions 22. Metalization 19 masks the source/drain regions 17 of p-channel transistor 16 from the counter-doping effects which would otherwise be produced by implant 21. Again, thin oxide layer 7 prevent damage to the silicon surface. Since polysilicon gate electrodes 4 and 6 are commonly very heavily doped from the onset, implant 21, as well as previously practiced p-type implant 18 (Fig. 3) have negligible effect on the gate electrode conductivity. The structure depicted in Fig. 8 is obtained by conformally depositing a layer 23 of silicon dioxide onto the structure shown in Fig. 7. The absence of severe topological excursions facilitates the conformal deposition of the oxide without reentry problems and with commercially available fabrication equipment. The thickness of deposit oxide 23 is nominally 250 nanometers. An anisotropic etch of oxide follows and is continued until the surface of polysilicon gate electrodes 4 and 6, metalization 19, and LDD source/drain regions 22 are exposed. A representative anisotropic etch which is relatively selective in removing oxide at a rate significantly greater than polysilicon, monocrystalline silicon, or tungsten refractory metal involves the use CHF3:0₂ etchant in a reactive ion etching chamber. At the conclusion of this etch, sidewall oxide layers or spacers are retained adjacent each vertical wall of the structure last illustrated in Fig. 7. For example, there are shown in Fig. 9 oxide residuals 24 adjacent gate electrode 4, sidewall oxide residuals 26 adjacent metalization 19/field oxide 10 and, most importantly, sidewall oxide residuals 27 on either side of gate electrode 6 of n-channel transistor 14. Fabrication according to the unique sequence defined by the present invention concludes, as shown in Fig. 10, with a heavy dose source/drain implant 28 to form the heavily doped n-type source/drain regions 29 of n-channel field effect transistor 14. Again, metalization 19 serves as a mask to prevent any counter-doping of the p-channel transistor source/drain regions 17. As illustrated, implant masking by sidewall oxides 27 produces lightly doped drain regions 31 for n-channel transistor 14. A representative implant 28 involves the use of arsenic at a dose of 6 X 10¹⁵ ions per square centimeter and at an energy of 75K electrons volts. Fabrication of the CMOS integrated circuit is concluded in relatively conventional manner, including first an anneal sequence to activate and slightly diffuse, into further alignment with the gate electrodes, the various implanted source/drain dopants. Dielectric depositions, contact/via etchings, and metalizations to electrically interconnect the electrical nodes of the p-channel transistor 16 and n-channel transistor 14 are performed in known manners. In reflecting upon the present process and its concluded structure, recall that p and n-channel field effect transistors were differentiated during formation using a single photolithographic mask. Furthermore, note that the concluding structure exhibits features refined to compensate for the individual idiosyncrasies of the two transistor types. For example, the lower mobility of the p-type doped source/drain regions is offset by the coextensive presence of refractory metal or silicide metalization 19. Consequently, the source/drain region resistances of p-channel transistor 16 do not materially contribute to the transistor's transconductance characteristics. At the same time, the susceptibility of n-channel field effect transistors to hot electron trapping effects is mitigated by the integration of LDD source/drain regions into the conventional heavily doped source/drain region structures. The present process thereby produces CMOS transistors having structural asymmetry particularly suited to the needs and capabilities of both p-channel and n-channel field effect transistors.

Claims: A process of forming CMOS field effect transistor integrated circuits, including the steps of: forming in an active region of a semiconductor substrate (1) first and second polysilicon gate electrodes (4,6) with underlying gate dielectrics defining respective p-channel and n-channel field effect transistors; forming a capping dielectric layer (8,9,11,12) over said first and second polysilicon gate electrodes (4,6); forming a photolithographic mask (13) over said second polysilicon gate electrode (6) and associated field effect transistor source/drain regions (29,31); doping said substrate (1) in the presence of said photolithographic mask (13) to form source/drain regions (17) in said semiconductor substrate (1) aligned to said first polysilicon gate electrode (4); and removing said mask (13); characterized by the steps of: selectively forming metallic regions (19) over said source/drain regions (17) of said first polysilicon gate electrode (4); lightly doping (22) source/drain regions (29,31) of said second polysilicon gate electrode (6) in alignment with said second polysilicon gate electrode (6), using said metallic regions (19) as a mask; forming a sidewall dielectric (27) for said second polysilicon gate electrode (6); and heavily doping said source/drain regions (29,31) of said second polysilicon gate electrode (6) in alignment with said sidewall dielectric (27), using said metallic regions (19) as a mask. A process according to claim 1, characterized in that said step of forming of a capping dielectric layer (8,9,11,12) involves an oxide growth having a differential oxidation rate between said silicon substrate (1) and the gate electrode polysilicon and the further step of removing grown silicon dioxide from said source/drain regions (17) aligned to said first polysilicon gate electrode (4) before removing said photolithographic mask (13). A process according to claim 2, characterized in that a portion of said capping layer of silicon dioxide is retained over said first polysilicon gate electrode (4) following the removal of the grown silicon dioxide from said source/drain regions (17) aligned to said first polysilicon gate electrode (4). A process according to claim 3, characterized in that the selective formation of metallic regions (19) involves a selective deposition of a refractory metal. A process according to claim 3, characterized in that the selective formation of metallic regions (19) involves the steps of: blanket depositing a metal layer; conditioning the substrate (1) to selectively react the deposited metal with substrate silicon in the source/drain region (17) aligned to said first polysilicon gate electrode (4); and selectively removing unreacted metal. A process according to claim 4 or claim 5, characterized in that said sidewall dielectric (27) for said second polysilicon gate electrode (6) is formed by: conformally depositing silicon dioxide (23); and anisotropically etching the silicon dioxide (23) to expose said source/drain regions (19,21) aligned to said second gate electrode (6). A process according to claim 6, characterized in that the light doping of said source/drain regions (19,21) in alignment with said second polysilicon gate electrode (6) uses n-type impurity to form LDD regions (22) aligned to said second polysilicon gate electrode (6).

Inventors: GIOIA SAMUEL C, GIOIA, SAMUEL C.
Applicants: AT & T GLOBAL INF SOLUTION, AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC.
Application year: 1990
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27