Apparatus for digitally controlling the D.C. value of a processed signal

Abstract: A digital D.C. control system includes a multiplexer (22), a digital-to-analog converter (24), a capacitor (30), offset generating circuitry (26,27,28) and clamping circuitry (33,34 or 42,44,46). A digital signal (from 20) to be D.C. controlled and a digital brightness control signal (from 16) are alternatively coupled by the multiplexer to the input of the digital-to-analog converter. The output from the digital-to-analog converter is coupled to a system output terminal via the capacitor. When the signal is applied to the digital-to-analog converter a fixed D.C. offset is applied to the interconnection of the converter and capacitor. During preselected intervals the D.C. control value is coupled to the digital-to-analog converter concurrently with the system output terminal being clamped (through 33 or 44) to a fixed reference and the D.C. offset circuitry being disabled (at 27). This combination of apparatus permits controlling the D.C. level of a digitally processed signal without affecting the dynamic range of the digital signal.

Description: This invention relates to signal processing circuitry and particularly systems which employ both digital and analog circuitry. In digital signal processing systems in which an analog signal is converted to pulse code modulated PCM (e.g., binary) form, processed in PCM format and then converted back to analog form, it is desirable to constrain the number of bits per sample to the smallest number consistent with the desired quantization resolution and dynamic range of the signal. In fact, however, the number of bits per sample may increase as the samples progress through the digital system and the required bit capacity of the digital-to-analog converter may exceed the sample bit width of the analog to digital converter. This is particularly true in processing video signals. Consider, for example, a digitally processed luminance signal which represents a black and white video image. The average brightness of the image is dependent upon the D.C. or average amplitude of the luminance signal. If the dynamic range of the luminance signal is exactly equivalent to the maximum value which can be represented by the bit width of the processing system, brightness control cannot be digitally implemented without clipping the signal peaks, on the one hand, or expanding the system bit width on the other hand. In general both alternatives are undesirable since they either compromise performance or increase system cost. Consider also a pix-in-pix video system wherein video images from separate sources are simultaneously displayed on exclusive portions of a single display screen. Generally, it is desirable that the average brightness of both images be approximately equal so that the viewer's attention is not significantly attracted to only one of the two images. In order to insure that the average brightness of the two images is approximately equal, typical pix-in-pix receivers will cause the two signals representing the two images to be clamped to like D.C reference values. It is herein recognized as desirable to provide the function of a digital D.C. level control in a digital and analog video processing system without expanding the system bit width or compromising the signal quality. US-A-4663668 describes a television receiver arranged selectively to display images from several input signal sources, wherein clamping circuits are provided to establishing a constant black image reference level for all the input signals. However, the problem of digitally implementing brightness control of a video signal in a digital and analog processing system without expanding the system bit width or compromising the signal quality is not addressed in this reference. The present invention provides a signal processing apparatus comprising a source of digital video signals having recurring blanking intervals; and digital-to-analog converting means having input and output ports; characterized by a source of digital brightness control signals; a capacitor having a first electrode coupled to the output port of said digital-to-analog converting means, and having a second electrode for providing an output signal; a multiplexer having first and second signal input ports respectively coupled to said digital video signal source and to said digital brightness control signal source, and having an output port coupled to said input port of said digital-to-analog converting means; means for controlling said multiplexer so as to pass signals from said second signal input port of said multiplexer to said output port of said multiplexer during recurrent intervals substantially coincident with said blanking intervals and to pass signals from said first signal input port of said multiplexer to said output port of said multiplexer during intervening intervals; means for providing a DC offset potential to said first electrode during said intervening intervals, said offset potential providing means being disabled during said recurrent intervals substantially coincident with said blanking intervals; and means for clamping said second electrode to a reference potential during said recurrent intervals substantially coincident with said blanking intervals. The present invention includes a digital control system for adjusting the average value or D.C. value of a processed signal. This system incorporates a digital-to-analog converter having circuitry connected to its output terminal for selectively offsetting the D.C. level of the output signal from the converter. The output connection of the digital-to-analog converter is coupled to one electrode of a capacitor. The other electrode of the capacitor is coupled to an output terminal of the system and selectably coupled to a source of reference potential. Digital signals to be converted and D.C. control values are selectively coupled to the digital-to-analog converter via a multiplexer. The reference potential is coupled to the capacitor at predetermined intervals concurrently with the D.C. control values being coupled to the digital-to-analog converter. At other intervals when the digital signals are coupled to the digital-to-analog converter, the output of the digital-to-analog converter is D.C. offset by the circuitry for selectively offsetting its output signal. FIGURE 1 is a waveform diagram useful in describing the invention. FIGURE 2 illustrates a block diagram of analog and digital signal processing circuitry included in a pix-in-pix video signal processor incorporating an embodiment of the invention. The invention will be described in the environment of a picture-in-picture video signal processing system though it is to be understood that it has significantly broader applications. Referring to FIGURE 1, approximately one horizontal line of a standard NTSC type baseband composite video signal is illustrated. The signal includes a horizontal synchronizing component, a reference frequency or burst component, a blanking level component and an information component. The amplitudes of the particular components are standardized and measured in IRE units with the tip of the horizontal synchronizing component being the most negative at minus 40 IRE units and the maximum value of the information component being the most positive at 100 IRE units. The blanking level is at zero IRE and is a few IRE blacker than the normal black level displayed in an image. If the horizontal synchronizing pulse is stripped from the signal, the average brightness of the image represented by the video information is a linear function of the average or D.C. value of the video information over the line interval. Refer now to FIGURE 2 which illustrates in part the general processing apparatus of a pix-in-pix system. In FIGURE 2, two video signals, A and B, from respective sources 10 and 12, which may be conventional tuner-If-detector circuits, are applied to a switch 14. Switch 14 is controlled by system control circuitry 16 responsive to user input, to route one or both of the input signals A and B to respective main video and pix-in-pix signal processing paths. The main video processing path includes circuitry 18 which may include circuitry for extracting synchronizing signals to generate deflection and blanking signals, and for conditioning the video information component for application to a display device, etc. Output signal from the processing circuitry 18 is coupled to a buffer amplifier 32. The output signal provided by buffer amplifier 32 is coupled to one input of a multiplexing circuit 38. Signal from the pix-in-pix processing path is coupled to a second input terminal of the multiplexing circuit 38. Multiplexing circuit 38 is conditioned by a control signal from the pix-in-pix processor to selectively time division multiplex the main video signal and the pix-in-pix signal (as is known in the video signal processing art) to generate a signal formatted to display the pix-in-pix image as an inset in the main image. The output, 40, of the multiplexing circuit 38 is coupled to further processing circuitry (not shown) for conditioning the signal for display. Known pix-in-pix processors are of two general types, those which process composite video signals and those which process component video signals. In the former case the further processing circuitry will include apparatus to separate luminance and chrominance signals and for generating R, G, and B signals related to the primary colors. In this instance circuitry 18 will include minimal processing circuitry. In component systems luminance and chrominance signals are processed separately. Component systems require somewhat duplicative circuitry of that illustrated in FIGURE 2 to process both components. In this instance the circuitry 18 will include circuitry to separate the luminance and chrominance components and the further processing circuitry subsequent the multiplexer 40 will be simplified. In the discussion to follow assume that the apparatus of FIGURE 2 is processing either composite video signal or the luminance component of a video signal. The pix-in-pix processing path includes processing circuitry 20 whose primary purpose is to synchronize the second video signal to the main video signal and to compress the second video signal. The processing circuitry 20 may include an analog-to-digital converter for converting the analog video signal to PCM signals. In addition it will include a field or frame memory for storing the PCM video signal and timing circuitry for synchronizing the writing of signal to memory and reading of signal from memory, etc. Synchronized PCM samples from the processing circuitry 20 are coupled to the digital-to-analog converter 24, wherein they are converted to analog form and thereafter coupled, via buffer amplifier 36 to the multiplexing circuit 38. For the purpose of this disclosure the contents of circuitry 20 are not important. Suffice it to say that the bit width of the PCM samples comports with the bit width of the sample input port of the digital-to-analog converter (DAC). In this example it is assumed that processor 20 processed the video signal in 6 bit, two's complement, samples, and that the most negative binary sample provided by the processor 20 corresponds to the blanking level of the video signal. In terms of IRE units (FIGURE 1) the 64 possible states of the six bit samples span the 100 IRE video information range. Positive 31 units corresponds to 100 IRE; negative 32 units corresponds to zero IRE or blanking level; and zero units corresponds to 50 IRE. Note, in general, whether the system is processing composite or component signals it is not necessary to store and/or output either the horizontal synchronizing or burst components of the secondary signal. The components may be used internal to circuitry 20 but are not required for further processing. Therefore, circuitry 20 can, without compromising signal integrity, arrange the 64 PCM states to correspond to the 0-100 IRE video information range. Consider that the secondary video signal level is 100 IRE in the 6-bit system described and it is desired to a) increase the average brightness level, b) not increase the bit capacity of the DAC 24 or clip the video signal and c) perform the function digitally. Obviously, if a constant binary value is added to the PCM video signal to raise the brightness level additional bits must be added to the samples to preclude clipping the occurrences of maximum signal values, and thus the bit capacity of the DAC 24 must be increased contrary to one of the above conditions. Consider that the main and secondary video signals are sourced from different channels and may have blanking levels diverging from zero IRE due to adverse transmission conditions. This situation may tend to establish the average brightness of the two signals at significantly different levels even for like initial conditions. Significantly differing brightness levels between the main and inset image may create viewer annoyance. Therefore, it is desirable to incorporate apparatus to clamp the D.C. or average levels of the main and secondary video signals to the same value. Both of the foregoing functions may be performed with the addition of a current source, a capacitor, two switches and a multiplexer as follows. First, it is assumed that the DAC 24 provides an output current, which is converted to an output voltage by virtue of the resistor 28 connected between the output terminal of DAC 24 and supply potential. Also assume that DAC 24 provides zero current for a PCM input value of negative 32. Thirdly, assume that either the control circuit 16 or the processor 20 is arranged to provide brightness control values. The brightness control values are coupled to one input port of a multiplexer 22. PCM video signal from the processor 20 are coupled to a second input port of multiplexer 22, the output port of which is coupled to DAC 24. The multiplexer 22 is conditioned by a signal, B L , (connection 19) provided by the main signal processor, to couple the brightness control values to the DAC during the horizontal blanking intervals and to couple the video signal to the DAC during active video. A constant current source 26 is coupled to the output port of the DAC 24 via a switch 27. The switch 27 is conditioned by the signal B L to close during active video. The capacitor 30 couples the output port of the DAC 24 to the buffer amplifier 36. A resistor 34 is coupled from the output of the buffer amplifier 32 (main video signal) to the interconnection of capacitor 30 and buffer amplifier 36 via a further switch 33. Switch 33 is conditioned by a clamp signal C L , generated in processor 18, to close during the horizontal blanking interval when the blanking level is present and to open for the duration of the active video information. Note that switch 33 may be closed during the burst component of a composite video signal since the average value of burst is equal to the blanking level. The value of resistor 34 must be high enough relative to the output impedance of buffer amplifier 32 so that the output potential of amplifier 32 is not affected. It need not be high enough to suppress completely, at capacitor 30, any A.C. ripple from the main video signal. The clamp/brightness circuitry operates as follows. The current source 26 supplies a current equal to 1/N th the range of currents provided by DAC 24. This current is applied during active video and is conducted by resistor 28 to develop an offset potential of 1/N th the potential range developed by the output current provided by the DAC 24. During the blanking interval switch 33 is closed and the blanking level of the main video signal is impressed on the capacitor 30 establishing an equal valued blanking level on the secondary video signal. While switch 33 is closed, multiplexer 22 is conditioned to apply a brightness level control value to the input port of the DAC 24 and switch 27 is open circuited. Consider first that the brightness level control value is equal to 1/N th the dynamic range of the DAC. The DAC 24 will develop an output current equal to 1/N th its maximum output current and develops a potential across resistor 28 equal to 1/N th the range of potentials that can be developed by the DAC current alone. At the end of the blanking interval switch 33 is open circuited disconnecting the main and secondary video signals with the main signal blanking level established on the output electrode of capacitor 30. In addition, switch 27 is closed and the multiplexer 22 is conditioned to couple the secondary video signal to the DAC 24. Assume that the secondary video signal has a value equal to the blanking level so that the DAC 24 provides zero output current. Current source 26 applies the 1/N th valued current to resistor 28 so that after switchover no D.C. potential change occurs across the resistor 28. If no D.C. potential change occurs at the output connection of the DAC (input connection of capacitor 30) no D.C. change will occur at the output electrode of capacitor 30. The average brightness level of the secondary video signal will therefore be referenced to the blanking level of the main video signal which was applied to capacitor 30 via switch 33. Now consider altering the brightness level of the secondary video. If a brightness control value which is greater (lesser) than 1/N times the dynamic range of the DAC is coupled to the DAC during the blanking interval, when the switch 27 is closed and the video signal is coupled to the DAC, a D.C. shift of ΔV will occur across the resistor 28. For example, assume a brightness control value of 2/N times the dynamic range of the DAC. During blanking (with switch 27 open and switch 33 closed) a potential of 2/N the dynamic range of the DAC is coupled to the input electrode of capacitor 30 and the main video blanking level is coupled to the output electrode. Then switch 33 is opened, secondary video signal is applied to the input of the DAC and switch 27 is closed coupling the 1/N current source to the capacitor 30. The D.C. level at the input side of capacitor 30 is reduced by ΔV = 2/N - 1/N = 1/N times the dynamic range of the DAC. This potential change ΔV is coupled across capacitor 30 reducing the brightness level by ΔV. Conversely, if during the blanking interval a brightness level of minus 32 (zero output current value) were applied to the DAC, a positive D.C. potential shift ΔV of 1/N times the dynamic range of the DAC will be coupled across capacitor 30. With the foregoing arrangement the brightness level of the secondary video signal can be adjusted upward by 1/N th the dynamic range of the DAC and downward by (N-1)/N times the dynamic range of the DAC. This D.C. adjustment is accomplished without altering the dynamic range or the bit width of the DAC or the digital processing circuitry. The foregoing example has been directed to circuitry for changing the D.C. or brightness level of a video signal in a pix-in-pix receiver. A more generalized arrangement applicable to digitally controlling the D.C. level of a video or other signal is indicated by elements 42, 44 and 46. In the general embodiment, elements 42-46 are utilized in place of switch 33, resistor 34 and the main video signal. In this embodiment, during the time interval when switch 27 is open, switch 44 is closed, coupling a reference potential V REF provided by the potential source 46 to the output side of the capacitor 30. D.C. control of the output signal is made relative to the value V REF . The FIGURE 2 arrangement incorporated a current source 26 cooperating with a current-output type DAC to provide a voltage offset. It will readily be appreciated that such potential offset values may also be incorporated with voltage-output type DAC's using known potential level shifter circuits.

Claims: Signal processing apparatus comprising: a source (20) of digital video signals having recurring blanking intervals; and digital-to-analog converting means (24) having input and output ports; characterized by a source (16) of digital brightness control signals; a capacitor (30) having a first electrode coupled to the output port of said digital-to-analog converting means, and having a second electrode for providing an output signal; a multiplexer (22) having first and second signal input ports respectively coupled to said digital video signal source and to said digital brightness control signal source (16), and having an output port coupled to said input port of said digital-to-analog converting means; means (18, 19) for controlling said multiplexer so as to pass signals from said second signal input port of said multiplexer to said output port of said multiplexer during recurrent intervals substantially coincident with said blanking intervals and to pass signals from said first signal input port of said multiplexer to said output port of said multiplexer during intervening intervals; means (26, 27) for providing a DC offset potential to said first electrode of the capacitor (30) during said intervening intervals, said offset potential providing means being disabled during said recurrent intervals substantially coincident with said blanking intervals; and means (33, 34) for clamping said second electrode of the capacitor (30) to a reference potential during said recurrent intervals substantially coincident with said blanking intervals. Apparatus in accordance with claim 1 further characterized in that said offset potential providing means comprises a current source (26) having a current output terminal; and switching means (27) for coupling said current output terminal to said first electrode during said intervening intervals and for decoupling said current output terminal from said first electrode during said recurrent intervals substantially coincident with said blanking intervals. Apparatus in accordance with claim 1 or 2 further characterized by means (18, 32) for providing additional video signals synchronized with said video signals from said source, wherein said reference potential corresponds to the blanking level exhibited by said additional video signals during said blanking intervals.

Inventors: CANFIELD BARTH ALAN, FLING RUSSELL THOMAS, CANFIELD, BARTH ALAN, FLING, RUSSELL THOMAS
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS, INC.
Application year: 1990
Main classification: H04N5
IPC codes: H03M1, H04N5, H04N11, H04N7