Semiconductor device manufacturing method

Abstract: In a method of manufacturing a semiconductor device of polycide gate structure, a polysilicon layer (4) is formed on the gate insulation film (3). The polysilicon layer and the gate insulation film are selectively removed to form an opening (11) which reaches the semi­ conductor substrate (1) in the polysilicon layer and the gate insulation film. After this, a silicide film (6) is formed directly on the polysilicon layer and an exposed part of the semiconductor substrate and then ion-implantation is effected to form source and drain regions. According to the manufacturing method, since the silicide film is formed in direct contact with the semiconductor substrate, charges caused by the ion-­ implantation can be easily discharged into the semicon­ ductor substrate. Therefore, no a te charge will occur. Further, the gate oxide film is prevented from being brought into contact with the masking photoresist layer (5) by the presence of the polysilicon layer. There­ fore, damage of the surface of the gate oxide film due to the direct contact with the photoresist layer will not occur and unwanted material may be prevented from being injected from the photoresist layer into the gate oxide film.

Description: This invention relates to a method for manufacturing semiconductor devices of polycide gate structure, and more particularly to a method used for manufacturing semiconductor devices having a thin gate oxide film. In a MOS transistor manufacturing process, semiconductor impurity is ion-implanted into a semiconductor substrate to form source and drain regions. At this time, charges caused by the ion-implantation are injected into the gate electrode so as to charge the gate electrode (gate charge). The gate charging increases the potential of the gate electrode so that the gate oxide film may be subject to dielectric breakdown by the electric field created between the substrate and the gate electrode when the gate oxide film is thin. In order to solve this problem, the ion-implantation is generally effected with the gate electrode layer and the silicon substrate held in contact with each other. With the gate electrode layer kept in contact with the silicon substrate, charges caused by the ion-implantation will not be stored in the gate electrode but discharged into the substrate. In order to set the gate electrode layer in contact with the silicon substrate, it is necessary to remove the contact portion of the gate electrode layer by the photolithographic process, for example, and form a contact hole for connection with the gate oxide film. In the process of forming the contact hole, a photoresist film of a predetermined pattern is formed on the thin gate oxide film and the gate oxide film is selectively etched to form the contact hole using the resist film as a mask. However, formation of the photoresist layer on the thin gate oxide film may significantly degrade the quality of the surface of the gate oxide film and increase the weak-point density. Further, material mixed into the photoresist layer may be injected into the gate oxide film to lower the electrical stability of the gate oxide film. As described above, in the conventional manufacturing method, there are problems that the gate oxide film may be damaged in the manufacturing process and unwanted material will be injected into the gate oxide film. From US-A-4,788,160 a process for manufacturing a semiconductor device comprising shallow silicided junctions is known. After the formation of source/drain implants in and of a polysilicide control electrode on a semiconductor substrate, a metal layer is formed by sputtering on the surface of the device. The metal layer is heat-treated to form metal silicide at those parts of the layer which are adjacent to silicon or polysilicon by consuming the silicon or polysilicon. Only where the metal overlies an oxide layer, the metal layer remains unsilicided. After the metal is reacted with the silicon or polysilicon, an implant step is performed to implant impurities through the surface into the metal silicide. At this step of the process, the metal silicide contacts only the soure/drain implants provided in the semiconductor substrate. WO 87/00967 relates to the problem to avoid dielectric breakdown in a gate oxide film by shorting the gate to the substrate via a metal layer. This problem is solved by depositing a metal that will be used to silicide the source, drain and gate regions before the ion implantation process. The gate surrounded with spacers is formed before the step of depositing a metal layer will be performed. It is the object of this invention to provide a semiconductor device manufacturing method capable of suppresseing the gate charge at the time of ion-implantation and preventing the occurrrence of damage to the gate oxide film in the manufacturing process and injection of unwanted material into the gate oxide film. The above object is solved by the method steps as mentioned in claim 1. Advantageous embodiments of this invention are described in the subclaims. According to the method of this invention, since the silicide film is formed in direct contact with the semiconductor substrate, charges caused by the ion-implantation can be easily discharged into the semiconductor substrate. Therefore, no gate charge will occur. Further, the gate oxide film is prevented from being brought into contact with the photoresist layer by the presence of the polysilicon layer. Therefore, damage of the surface of the gate oxide film due to the direct contact with the photoresist layer will not occur and unwanted material may be prevented from being injected from the photoresist layer into the gate oxide film. In a case where the withstanding voltage of the contact portion between the silicide layer and the semiconductor substrate is lower than that of the gate and the substrate of the transistor, portions of the silicide layer and the polysilicon layer which lie between the transistor region and the contact region are selectively removed so as to separate a region acting as the gate electrode portion from the semiconductor substrate. As a result, it becomes unnecessary to set the upper limit of the operation voltage range of the semiconductor device lower than the withstanding voltage of the contact portion. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1L are cross sectional views of semiconductor structures in respective steps of a manufacturing method according to one embodiment of this invention; and Figs. 2A to 2C are cross sectional views of semiconductor structures in respective manufacturing steps in a modification of the embodiment explained with reference to Figs. 1A to 1L. There will now be described a manufacturing method according to an embodiment of this invention with reference to the accompanying drawings. This embodiment is made by applying the manufacturing method of this invention to a method for manufacturing a semiconductor device having transistor elements. Figs. 1A to 1L are cross sectional views of semiconductor structures in respective steps of a manufacturing method according to the embodiment of this invention. The cross sectional views show the cross sections taken along lines extending in the lengthwise direction of the gate electrode of the transistor element and therefore the source and drain regions are not shown. As shown in Fig. 1A, an element isolation region (SiO 2 region) 2 is formed in a p-type silicon substrate 1 by the thermal oxidation method. After this, as shown in Fig. 1B, a thin oxide film (SiO 2 film) 3 with a film thickness of 100 Å (10Å=1nm), for example, is formed by the thermal oxidation method on a transistor region 21 and a contact area 22 which are isolated from the element isolation regions 2. Part of the oxide film 3 which lies on the transistor region 21 constitutes a gate oxide film. Then, as shown in Fig. 1C, a polysilicon layer 4 is formed by the CVD method to a thickness of approx. 1500 Å. After this, as shown in Fig. 1D, n-typr impurity such as As + is ion-implanted into the polysilicon layer 4 to enhance the electrical conductivity thereof. Instead of the As + implantation, phosphorus may be diffused into the polysilicon layer 4. In the As + ion-implantation performed during this step, a charge-up will not occur in the polysilicon layer 4, since the polysilicon layer 4 is generally connected to the ground during the ion-implantation step via the conductive wafer-holder (not shown) of an ion-implanting device (not shown), for holding the semiconductor wafer (the semiconductor structure), the wafer-holder generally being grounded. Next, as shown in Fig. 1E, a photoresist layer 5 is formed on the polysilicon layer 4 and then patterned to form an opening in the contact area. With the photoresist film 5 used as a mask, the polysilicon layer 4 and the gate oxide film 3 are selectively etched to form an opening 11 which reaches the substrate 1 in the contact area 22 as shown in Fig. 1F. After this, the photoresist layer 5 is removed, and as shown in Fig. 1G, a metal silicide layer such as a tungsten silicide (WSi) layer 6 is formed to a thickness of approx. 3000 Å by the CVD method. The silicide layer 6 is formed to extend into the opening 11 so as to be made in contact with the exposed portion of the substrate. Then, as shown in Fig. 1H, the metal silicide layer and polysilicon layer 4 are patterned to form a polycide gate electrode 12 of a predetermined pattern. Next, as shown in Fig. 1I, for example, As + is ion-implanted to an impurity density of 1 × 10 15 cm -2 , for example, as an n-type impurity source used for forming source and drain regions (as described before, since the cross sections are taken along lines extending in the lengthwise direction of the transistor element and therefore the source and drain regions are not shown. In the drawing, the source and drain regions lie behind and before the paper in the transistor region 21). Since the silicide layer 6 is formed in direct contact with the substrate 1, charges caused by the ion-implantation are discharged into the substrate via the silicide layer 6. As a result, almost no charge is stored in the gate electrode layer 12. That is, substantially no gate charge occurs. After this, the heat treatment is effected to activate implanted As + so as to form source and drain regions. At this time, As+ implanted into the silicide layer 6 is diffused into the substrate 1 via the contact area between the silicide layer 6 and the substrate 1 to form an n-type diffusion layer 7 in in that part of the substrate 1 which corresponds to the contact area 22 as shown in Fig. 1J. Then, as shown in Fig. 1K, an interlayer insulation film 8 of SiO 2 , for example, is formed on the entire surface of the resultant structure by the CVD method and is patterned to form an opening which reaches the silicide layer 6. Next, as shown in Fig. 1L, a metal layer 9 of aluminum, for example, is formed on the entire surface of the resultant structure by the sputtering method and is patterned to form a gate electrode lead-out layer 9. As is clearly understood from the above embodiment, in the manufacturing method of this invention, the silicide layer 6 is formed in direct contact with the substrate 1 so that charges caused by the ion-implantation may be discharged via the substrate. As a result, unwanted gate charge will not occur. Further, the polysilicon layer 4 is formed between the gate oxide film 3 and photoresist layer 5 and thus the gate oxide film 3 is not formed in direct contact with the resist layer. Therefore, occurrence of damage to the surface area of the gate oxide film 3 caused when the resist layer 5 is formed in direct contact with the gate oxide film 3 can be prevented and injection of unwanted material from the resist layer into the gate oxide film can also be prevented. In a case where the withstanding voltage of the pn junction between the substrate 1 and the n-type diffusion layer 7 is not sufficiently high for the operation of the device, portions of the silicide layer 6 and the polysilicon layer 4 which lie on the element isolation region 2 between the transistor region 21 and the contact area 22 are etched out to isolate an area of the electrode layer 22 acting as the gate electrode from the substrate 1 as shown in Fig. 2A. As a result, the operation voltage of this device will not be limited by the withstanding voltage of the pn junction. The succeeding manufacturing process is the same as that in the former embodiment. That is, as shown in Fig. 2B, an interlayer insulation film 8 of SiO 2 , for example, is formed on the entire surface of the resultant structure by the CVD method and is patterned to form an opening which reaches the silicide layer 6. Then, as shown in Fig. 2C, a metal layer 9 of aluminum, for example, is formed on the entire surface of the resultant structure by the sputtering method and is patterned to form a gate electrode lead-out layer 9. If the gate electrode is formed in contact with the substrate at one place, charges can be smoothly discharged into the substrate. Therefore, it is extremely advantageous from the viewpoint of effective use of the chip area that the manufacturing method of this invention is used for manufacturing semiconductor devices in which a gate electrode is formed as a continuous layer extending over a plurality of memory cells. In the former embodiment, a single-layered gate structure is used. However, a two-layered or multi-layered gate structure can be applied in this invention. Further, in the former embodiment, the gate electrode layer is formed with the polycide gate structure of the polysilicon layer and WSi layer. However, the silicide layer is not limited to the WSi layer but a MoSi, TiSi layer or the like can be used as the silicide layer. The deposition method of the silicide layer is not limited to the CVD method, and the sputtering method or the like can be used. Further, it is possible to use an n-type silicon substrate instead of the p-type silicon substrate. In this case, it is necessary to use p-type impurity such as boron (B) as the impurity to be implanted instead of the n-type impurity.

Claims: A method of manufacturing a semiconductor device having a polycide gate structure, characterized by the steps of: forming element isolation region (2) in a first conductivity type silicon substrate (1) to define in the silicon substrate a transistor region (21) and a contact region (22) which are separated from each other by the element isolation region (2); forming an oxide film (3) on said transistor region (21) and said contact region (22) of said silicon substrate; forming a polysilicon layer (4) with an opening (11), which polysilicon is doped with a second conductivity type impurity said opening exposing said contact region of said silicon substrate; forming a metal silicide layer (6) on said polysilicon layer and said exposed contact region of said silicon substrate; patterning said polysilicon layer (4) and said metal silicide layer (6) to form a polycide gate electrode (12); and ion-implanting said second conductivity type impurity followed by an activation heat treatment to form source and drain regions in said transistor region and a diffusion layer (7) in said contact region. A manufacturing method according to claim 1, characterized by further comprising the step of: selectively removing said silicide layer (6) and said polysilicon layer (4) to separate an area acting as a polycide gate electrode from said semiconductor substrate. A manufacturing method according to claims 1 or 2, characterized in that the step of forming said silicide layer (6) includes a CVD process. A manufacturing method according to claims 1 or 2, characterized in that the step of forming said silicide layer (6) includes a sputtering process. A manufacturing method according to claims 1 or 2, characterized in that said silicide layer (6) is a WSi layer. A manufacturing method according to claims 1 or 2, characterized in that said silicide layer (6) is a MoSi layer. A manufacturing method according to claims 1 or 2, characterized in that said silicide layer (6) is a TiSi layer.

Inventors: MORI SEIICHI, MORI, SEIICHI, MORI, SEIICHI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L29