Communications interface apparatus with decimating circuit

Abstract: An apparatus adaptable for use with an analog-digital conversion device (14) for effecting communications between an analog device (12) and a digital device (24), the analog-digital conversion device converting incoming analog signals received from the analog device to incoming digital signals. The apparatus has a digital signal processing circuit (18) for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device. The digital signal processing circuit is comprised of a plurality of modules (19) which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation.

Description: The present invention is directed to a communications interface apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device. Specifically, in its preferred embodiment, the present invention is used in effecting communications between a voice-band device, such as a telephone, and a data processing device. The present invention receives digital signals from an analog-digital conversion device, decimates those incoming digital signals to produce decimated incoming digital signals representative of the received incoming digital signals. The decimated incoming digital signals are recognizable by the data processing device. In the manufacturing of interface devices such as the present invention, separate circuit designs are often utilized to effect different numbers of iterations of decimation of signals produced by analog-to-digital conversion circuitry. Often there is duplication of engineering effort in designing such variously capable decimation circuitry. Such duplicate engineering effort results in each newly designed digital signal processing circuit involving essentially as much design effort and cost as a wholly new circuit. IEEE Solid State Circuit Conference 31, Feb. 1988, pages 202, 203, 372-374, discloses a known interface apparatus comprising a front end LSI and two decimators to reduce the sampling rate. Multirate Digital Signal Processing by Crochiere et al, Pages 193-196 discloses multi-stage decimation. The present invention is designed to overcome some of the expense of duplication of engineering effort to design variously capable digital signal processing circuits. The invention is carried out in accordance with the appended claims. We describe an apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device, having a digital signal processing circuit for decimating incoming digital signals received from the analog-digital conversion device, and providing a decimated incoming digital signal to the digital device. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimat Accordingly, there is provided an apparatus adaptable for use in effecting communications between an analog device and a digital device which is modularly configured to facilitate satisfying differing system requirements. There is further provided an apparatus adaptable for use in effecting communications between an analog device and a digital device, the manufacture of which may be accomplished with economies of engineering design effort. There is further provided an apparatus adaptable for use in effecting communications between an analog device and a digital device which is inexpensive to adapt to various system requirements. In the accompanying drawings, by way of example only: Fig. 1 is a schematic block diagram of a system embodying the present invention, Fig. 2 is an electrical schematic diagram of the decimation circuit in Fig. 1, Fig. 3 is a space-time domain matrix representation of the decimation circuit for implementation of the decimation transfer function. Fig. 4 is a schematic block diagram illustrating the modular design of the decimation circuit. In Fig. 1, an analog device 12, such as a telephone voice instrument, is connected to an analog-digital circuit 14. Typically, the analog device 12 operates in the audio frequency range, approximately 300 Hz to 3.4 KHz. The analog-digital circuit 14 samples the incoming analog signal which is conveyed from the analog device 12 via line 16. The sample rate of the analog-digital circuit 14 is, in the preferred embodiment, approximately 2 MHz. Some advantages are incurred by the high frequency sampling by the analog-digital circuit 14: for example, a higher frequency of operation allows for closer spacing of components in the invention when the invention is configured as an integrated circuit, i.e., a silicon chip construction; and the high frequency sampling allows for a more accurate digital representation of the incoming analog signal. The analog-digital circuit 14 converts the incoming analog signal received on line 16 to an incoming digital signal and conveys that incoming digital signal to a decimation circuit 18 via line 20. The decimation circuit 18 receives the incoming digital signal on line 20, performs a decimation operation upon that signal, and outputs a decimated incoming digital signal on line 22. In the preferred embodiment, the incoming decimated digital signal is produced at a frequency of approximately 16 KHz, a frequency which still allows for obtaining the advantages of high frequency close spacing of components in a silicon chip structure and high resolution of the digital representation of the incoming analog signal. The incoming decimated digital signal is presented to the digital device 24 via line 22. The digital device 24 is, commonly, a device such as a data processing device or a computerized communications switching apparatus. An electrical schematic diagram of the preferred embodiment of the present invention is presented in Fig. 2. For purposes of clarity in describing the preferred embodiment of the present invention, like elements will be labelled with like reference numerals throughout this description. In Fig. 2, an analog-digital circuit 14 receives incoming analog signals on line 16 from an analog device (not shown in Fig. 2). Further, the analog-digital circuit 14 conveys incoming digital signals to a decimation circuit 18 via lines 20a and 20b. The decimation circuit 18 is preferably comprised of digital input circuit 66, first digital cell circuit 68, second digital cell circuit 70, second digital cell circuit 72, and output circuit 92. The first digital cell circuit 68 is preferably comprised of a shift register R0 receiving an input from multiplexer 74 and providing an output to a one bit adder SA1, a multiplexer 96, and a shift register R1B. The output of the programmable logic array 78 is applied to shift register R1B via line 100. The output of multiplexer 96 is applied to a shift register R1A. The output of shift register R1A is applied to a multiplexer 104 as well as fed back to the multiplexer 96. Also applied to the multiplexer 104 is the output of shift register R1B. The output of multiplexer 104 is applied to multiplexer 84 as well as to one bit adder SA1. The output of multiplexer 84, which is also the output of first digital cell circuit 68, is applied to one bit adder SA2 of second digital cell circuit 70 as well as to shift register R0. Second digital cell circuit 70 further comprises a multiplexer 106 which also receives the output of multiplexer 84. The output of shift register R2 is applied to multiplexer 108 as well as fed back to multiplexer 106 and applied to one bit adder SA2. Also provided to multiplexer 108 is the output of one bit adder SA2. The output of multiplexer 108, which is also the output of second digital cell circuit 70, is applied to one bit adder SA3 and multiplexer 110 of second digital cell circuit 72. Further in second digital cell circuit 72, the output of one bit adder SA3 is applied to multiplexer 112 and the output of multiplexer 110 is applied to shift register R3. The output of shift register R3 is applied to multiplexer 112, to one bit adder SA3, and to multiplexer 110. The output of multiplexer 112, which is also the output of second digital cell circuit 72, is applied to output circuit 92. Specifically, the output of multiplexer 112 is applied to scaling subcircuit 114 which applies a scaled output to shift register R4. The output of shift register R4 is provided via multiplexer 94 to input bus 24a via line 22. The decimation circuit 18 conveys decimated incoming digital signals to the input bus 24 of a digital device (only the input bus 24 of a digital device is illustrated in Fig. 2) via line 22. The analog-digital circuit 14, as illustrated in Fig. 2, includes counter 44 and digital-to-analog converter 46. The decimation circuit 18, when it receives an incoming digital signal from the analog-digital circuit 14 via lines 20a and 20b, decimates the incoming digital signal in a manner to be described in greater detail below. The digital input circuit 66 is preferably comprised of a multiplexer 74, a shift register 76, and a programmable logic array 78. When the analog-digital circuit 14 provides an incoming digital signal on lines 20a and 20b, the decimation circuit 18 is appropriately clocked to decimate incoming digital signals from the analog-digital circuit 14. Thus, each such succeeding digital pulse from the analog-digital circuit 14 is applied to the digital input circuit 66 at two points. The current count output of the analog-digital circuit 14 is applied via line 20a to the multiplexer 74, and the shift register 76 receives and stores a history of the pulse signals which appear on line 20b. The structure of the digital input circuit 66 is particularly adapted to the step-wise up and down signalling characteristic of the output of a first order integrator, which is employed in the preferred embodiment of the analog-digital circuit 14 wherein steps up and down are of a predetermined amount for each clock cycle. Such a structure saves hardware and saves having the decimation-interpolation circuit operate at high speed. For purposes of illustration, the preferred embodiment of the present invention illustrated in Fig. 2 accomplishes a decimation by a factor of 16 implemented in a four stage structure which implements the following transfer function: 1/256 (1+z -1 ) 2 (1+z -2 ) 2 (1+z -4 ) 2 (1+z -8 ) 2 =H D (z) For example, for a sampling rate by the analog-digital circuit 14 of 2.048 MHz, the decimator output would be 128 KHz. For purposes of this illustrative example, it is assumed that the analog-digital circuit 14 employs a 6-bit digital-analog converter and a sigma-delta modulator of a first order type. Of course, the present invention can be used for larger digital analog converters and for higher order sigma-delta modulators. The architecture of the decimation circuit 18 requires that the transfer function of Equation (1) be partitioned so that the second digital cell circuit 72 is preceded by all other sections of the decimation circuit 18 (i.e., digital input circuit 66, first digital cell circuit 68 and second digital cell circuit 70) to form a transfer function: H D (z) = 1/256 [H 1D (z)*H 2D (z)] where H 2D (z) is implemented in the first digital cell circuit 70 and second digital cell circuit 72, i.e., (1+z -8 ) 2 in Equation (1). The factor 1/256 is a scaling factor. Therefore, transforming Equation (1) into Equation (2) yields: H D (z) = 1/256 [(1+z -1 ) 2 (1+z -2 ) 2 (1+z -4 ) 2 ](1+z -8 ) 2 The term within the brackets [ ] of Equation (3) may be expanded to produce the following: H D (z) = 1/256 [1+2z -1 + 3z -2 + 4z -3 + 5z -4 + 6z -5 + 7z -6 + 8z -7 + 7z -8 + 6z -9 + 5z -10 + 4z -11 + 3z -12 + 2z -13 + z -14 ] And: H 2D (z) = [1 + 2z -8 + z -16 ] The annotation z -m indicates the value of z, m time periods past. By this partitioning method, H 1D (z) may be implemented in the programmable logic array 78 and the first digital cell circuit 68 and H 2D (z) may be implemented in the second digital cell circuit 70, and the second digital cell circuit 72. The time-domain implementation of Equation (4) is: y 1 (n)=x(n) + 2x(n-1) + 3x(n-2) + ... + x(n-14) Since the sigma-delta modulator employs a first order scheme, the difference, defined as d i , between successive counter values can only be ±1, i.e., x(n-1), can only differ from x(n) by ±1, x(n-2) can only differ from x(n-1) by ±1, and so on. Therefore the time-domain implementation of Equation (6) can be expressed as: y 1 (n) = x(n) + 2[x(n) - d 1 ] + 3[x(n) - d 2 - d 3 ] + ... + [x(n)- d 1 - d 2 - ... - d 14 ] where d i =±1, for i=1, 2, ..., 14. Expanding Equation 7 yields: y 1 (n) = 64x(n) - 63d 1 - 61d 2 - 58d 3 - 54d 4 - 49d 5 - 43d 6 - 36d 7 - 28d 8 - 21d 9 - 15d 10 - 10d 11 - 6d 12 - 3d 13 - d 14 The factors d i are representative of the successive outputs of analog-digital circuit 14 which also controls the incrementing or decrementing of the counter 44. The outputs D i are successively shifted in shift register 76 and are used as an address to the programmable logic array 78. The address is D 14 ... D 1 and comprises a succession of 1's and 0's, "1" meaning count up (d i =+1) and "0" meaning count down (d i =-1) By substituting all of the possible combinations of d 14 , ... d 1 , (i.e., 2 13 combinations) where d i =+1 or -1 for i=1, .... 14 into Equation (8), one could determine the contents of the programmable logic array 78. For example, for the address: D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Successive outputs for the analog-digital circuit 14 are all 0, which forces the counter 44 to decrement. Substituting d 14 , ... d 1 = -1 in Equation (8) yields: y 1 (n) = 64x(n) + 448 Thus, for the preferred embodiment illustrated in Fig. 2, the programmable logic array 78, with an input address of 0 ... 0, would yield an output value of +448. This result indicates that y 1 (n) is the sum of x(n), the present sample (provided to the shift register R0 via multiplexer 74), plus the sum of all the previous 14 samples. It is preferred that the output of the digital input circuit 66 be divided by 8. Consequently, every 8 clocks of the shift register 76, which holds the programmable logic array 78 address, is followed by a load of the counter 44 into shift register R0 via the multiplexer 74, with six zeroes added to the least significant end of the analog-digital circuit 14 output to produce 64 times x(n) (the first term of Equation (8)). The remaining terms of Equation (8) are calculated by the programmable logic array 78. The terms of Equation (8) are added using the bit serial adder SA1 in the first digital cell circuit 68 to determine the value of H 1D (z). The time-domain implementation of H 2D (z) is: y 2 (n) = y 1 (n) + 2y 1 (n-1) + y 1 (n-2) In the time domain, H 1D (z) is an input used in calculating H 2D (z). Thus, effectively, the time-domain output y 2 (n) is the time-domain result of the total transfer function H D (z). The second digital cell circuits 70, 72 produce another decimation of ÷2 to give an overall reduction in sampling rate of 16. The next successive expression of H 2D (z) is: y 2 (n+1) = y 1 (n+2) + 2y 1 (n+1) + y 1 (n) A comparison of Equations (10) and (11) clearly illustrates that successive samples (i.e., input values to H 2D (z)) are shifted up by two places each clock cycle to produce the decimation by a factor of ÷2. The first digital cell circuit 68, the second digital cell circuit 70, and the second digital cell circuit 72 implement the H D (z) transfer function as illustrated in Fig. 3. Referring to Fig. 3, columnar divisions of a matrix are delineated T 0 , T 1 , T 2 , ... to indicate successive time periods, each period being eight clock pulses in duration. Row divisions are representative of the various registers R0, R1A, R1B, R2, R3, and R4 and their associated serial adders SA1, SA2, and SA3 within the decimation-interpolation circuit 18. Accordingly, each box in the matrix of Fig. 3 represents the function(s) performed by a specific register and serial adder during a specific time period. As illustrated in Fig. 3, during the time period T 0 -T 1 , the quantity 64x(n) is loaded into register R0. Also, first digital cell circuit 68, second digital cell circuit 70, and second digital cell circuit 72 are triggered; the output of the programmable logic array 78 is loaded into register R1B and the contents of register R0 and register R1B are added to yield the quantity y 1 (n). Further during the time period T 0 -T 1 , the quantity y 1 (n) is added with the contents of register R2 by one bit adder SA2 to yield the quantity y 1 (n) + 2y 1 (n-1), using a scaling function provided by appropriate timing. Still within the time period T 0 -T 1 , the quantity y 1 (n) + 2y 1 (n-1) is shifted to second digital cell circuit 72 and combined with the then-residing contents of register R3 using one bit adder SA3 to yield the result y 1 (n) + 2y 1 (n-1) + y 1 (n-2). The quantity y 1 (n) remains in register R2. Finally, within the period T 0 -T 1 , the quantity y 1 (n) + 2y 1 (n-1) + y 1 (n-2) is shifted into register R4 in the output circuit 92 in scaled format, i.e., ÷256. During the second eight clock pulse period, T 1 -T 2 , the quantity 64x(n) is again loaded into register R0, first digital cell circuit 68 is triggered and its output is loaded into register R2, and the contents of register R2 are loaded into register R3. The programmable logic array 78 contents are loaded into register R1B and the quantity y 1 (n+1) is calculated by serial bit adder SA1, combining the contents of register R0 and register R1B. Thus, register R2 now contains y 1 (n+1) and register R3 now contains y 1 (n). During the third eight clock pulse period, T 2 -T 3 , the first digital cell circuit 68, the second digital cell circuit 70, and the second digital cell circuit 72 are triggered and the output of the programmable logic array 78 is combined with the 64x(n) information concurrently loaded into register R0 to produce the quantity y 1 (n+2). Serial adder SA2 computes the quantity y 1 (n+2) + 2y 1 (n+1) and register R2 retains the quantity y 1 (n+2) in storage. Serial adder SA3 calculates the quantity y 1 (n+2) + 2y 1 (n+1) + y 1 (n). The output of serial adder SA3 is then loaded into register R4 and the output which was previously loaded into register R4 during time period T 0 -T 1 is transferred to input bus 24a via line 22. Thus, during the time period T 0 -T 1 , a first value of H 2D (z) in the form of Equation (10) was loaded into register R4, i.e., y 1 (n) + 2y 1 (n-1) + y 1 (n-2). During the time period T 2 -T 3 , there is loaded into register R4 the next successive expression of H 2D (z) in the form of Equation (11), i.e., y 1 (n+2) + 2y 1 (n+1) + y 1 (n), and the first value of H 2D (z) is clocked through the multiplexer 94 of output circuit 92 to input bus 24a via line 22. Referring to Fig. 4, a schematic block diagram illustrating the modular design of the preferred embodiment of the present invention is presented. In Fig. 4, an analog device 12 sends incoming analog signals via a line 16 to an analog-digital circuit 14. The analog-digital circuit 14 passes incoming digital signals to a decimation circuit 15 via line 20. The decimation circuit 18 is comprised of decimator module 19. Additional decimator modules may be added to effect further decimation as desired; such additional optional decimator modules are represented in Fig. 4 by the dotted-line representation for decimator module 19a. The decimator module 19 is comprised of a digital input circuit 66, a first digital cell circuit 68, and second digital cell circuits 70, 72, 73. Second digital cell circuits within a given decimator module 19 may be added to effect greater degrees of decimation as desired, as indicated by second digital cell circuits 72 and 73. Additional decimator modules 19a necessarily will contain second digital cell circuits 70a and 72a; the number of second digital cell circuits 70a, 72a need not be identical among the various decimator modules 19, 19a. The last of the second digital cell circuits 73 in the decimator module 19 provides input to second digital cell circuit 70a of a subsequent decimator module 19a. The last second digital cell circuit 72a of the last decimator module 19a provides outputs to output circuit 92 from which decimated incoming digital signals are passed via line 22 to digital device 24. It is to be understood that, while the detailed drawings and specific examples given describe preferred embodiments of the invention, they are for the purpose of illustration only, that the apparatus of the invention is not limited to the precise details and conditions disclosed, and that various changes may be made therein without departing from the scope of the invention which is defined by the following claims.

Claims: A decimating circuit (18) having a plurality of stages each providing an iteration of decimation for decimating an incoming digital signal, the circuit (18) comprising: an input circuit (66) for receiving the digital signal and producing a corresponding clocked digital signal, a first digital cell circuit (68) responsive to the clocked digital signal to provide a first of the decimation stages, and a second digital cell circuit (70) responsive to the output of the first cell to provide a second of the decimation stages, characterised in that at least one additional decimation stage is provided, each additional stage comprising a digital cell circuit (72,73) identical to the second digital cell circuit (70) and responsive to the output of the preceding second cell circuit and further characterised in that each second digital cell circuit comprises: a first multiplexer (106,110) receiving the output of the previous cell; a register (R2,R3) receiving the output of the first multiplexer (106,110), the output data from the register being fed back into the first multiplexer (106,110), a serial adder (SA2,SA3) receiving the output data from the register (R2,R3) and the output of the previous cell; and a second multiplexer (108, 112) receiving the output of the serial adder (SA2,SA3) and the output data from the register (R2,R3), the output of the second multiplexer providing the input to the next cell. A decimating circuit according to claim 1, wherein the input circuit (66), first cell (68) and second cell or cells (70,72,73) form a first module (19), and wherein one or more of the second digital cell circuits (70a,72a) are added to the first module to form a second module (19a). A decimating circuit as claimed in claims 1 or 2, wherein the input circuit includes a shift register (76) and a programmable logic means (78) for producing the clocked digital signal. A decimating circuit as claimed in claim 3, wherein the input circuit (66) includes a shift register (76) and a programmable logic array (78) connected to the output of the shift register, wherein the shift register receives the incoming digital signal and a clock signal and the programmable logic array (78) provides the clocked digital signal to the first digital cell circuit (68) in response to the output of the shift register (76).

Inventors: ASGHAR SAFDAR M, BARTKOWIAK JOHN G, ASGHAR, SAFDAR M., BARTKOWIAK, JOHN G.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1990
Main classification: H03H17
IPC codes: H03M1, G06F3, H04B14, H03H17