Microprocessor incorporating cache memory

Abstract: A microprocessor incorporating a cache memory (1 and 2) comprises a control register (7 and 8) for storing a control information for controlling a purge operation per page for the cache memory (1 and 2), a setting portion for setting the control information into the control register (7 and 8), a comparing portion (9) for comparing a target address for the purge operation set in the control register (7 and 8) with an address in the cache memory (1 and 2), and an issue portion (6) for issuing a command for the purge operation to the comparing portion (9) in accordance with the control information when the target address agrees with the address in the cache memory (1 and 2), wherein, the comparing portion (9) transmits an instruction for the purge operation based on the command given from the issue portion (6) to the cache memory (1 and 2) .

Description: This invention relates to a microprocessor including a cache memory therein. EP-A-198 231 describes a microprocessor which can purge the content of its cache memory on a non-selective basis only. In a conventional microprocessor including a cache memory, the cache memory has a means for purging only the whole information stored in the cache memory when a purge operation for the information stored thereof is required. Thus it is not possible to purge only a part of the information stored in the conventional cache memory. This type of cache memory therefore can be fully applicable only to a microprocessor incorporating a small amount of cache memory, for example having not more than 4K bytes. However, the conventional cache can not be fully used in today's microprocessors including a cache memory having large capacity or scale. For example, in a microprocessor incorporating a larger scale cache memory, the whole information stored in the cache memory must be purged even when a purge operation for only part of the information is required. Accordingly, the purge operation for the cache memory is inefficient. In other words, the information stored in the cache memory can not be partially deleted by using the ability of the conventional microprocessor. The conventional microprocessor is unable to execute an operation for purging a part of the cache memory. Therefore when the purging operation for only part of the information is required, the operational efficiency of the entire microprocessor is reduced. FR-A-2 621 407 describes a microprocessor having a cache memory which can be subjected to a selective purge operation. An object of the present invention is to provide a microprocessor incorporating a cache memory which can operate with greater efficiency. According to the invention, there is provided a microprocessor incorporating a cache memory, storing pages of data, comprising: a control register for storing control information indicative of a selected one of a plurality of cache handling operations relevant to purging the cache memory, said control information including a page address for purging; setting means for transferring the control information to the control register; comparing means for comparing the page address for purging with respective page addresses stored in the cache memory; and issue means, responsive to the result of comparing by the comparing means, for providing a command to the cache memory in accordance with the control information in order to initiate said selected one of a plurality of cache handling operations for the entry identified by the page address for purging. Thereby, in the microprocessor incorporating a large scale cache memory the purge operation for every page can be executed efficiently. A larger effect can be obtained when the microprocessor according to the present invention is used in today's general purpose microprocessor incorporating a cache memory having a large scale and capacity. These and other objects, feature and advantages of the present invention will be mote apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings, in which: Fig.1 is a schematic block diagram of a microprocessor including a cache memory of an embodiment according to the present invention; Fig.2 is a constructional diagram of two control registers, namely an instruction cache control register and data cache control register, used for control of the cache memory as shown in Fig.1; Fig.3 is a diagram for comparison among commands in accordance with the control information; Fig.4 shows a constructional diagram of a data cache memory incorporated in the microprocessor; Fig.5 shows in detail a constructional diagram of a cache memory 2, a control register 8, a command issue portion 43 as an issue means 6, and a comparing means 42 incorporated in the microprocessor as shown in Fig.1; and Fig.6 is a diagram of a microprocessor of another embodiment according to the present invention. Embodiments of the invention will be described with reference to diagrams. Fig.1 shows a schematic block diagram of a microprocessor incorporating cache memories as a first embodiment according to the present invention. In the same diagram, reference numbers 1 and 2 designate cache memories, respectively called an instruction cache memory and a data cache memory. In this embodiment, these cache memories can be operated by page addressing when a purge operation is required. Of course, like conventional microprocessors, other operations such as writing, reading and others can be executed per bit, sector, page, or entire location. Instructions and data transferred from the outer memory 3 or others are stored in the instruction cache memory 1 or the data cache memory 2 through bus lines 4. Reference number 5 shows a setting means for setting purge control information for the purge operation per page of the cache memory 1 or 2 into the instruction cache control register 7 or the data cache control register 8. Reference number 6 shows an issue means for issuing a command for the purge operation per page into a comparing means 9 in accordance with the purge control information stored in the instruction cache control register 7 or the data cache control register 8. When all pages in the cache memory 1 or 2 are to be purged, the issue means transmits directly the command for the purge operation to the cache memory 1 or 2. Comparing means 9 compares a target address for the purge operation stored in the control register 7 or 8 with a page address in the cache memory 1 or 2 so as to transfer a purge control signal as an instruction for the purge operation to the cache memory 1 or 2. When the target address is equal to the page address of the instruction cache memory 1 or the data cache memory 2, the page in the cache memory 1 or 2 designated by the page address is purged by the instruction based on the command as the purge control signal issued by the issue means. Hereinafter, operation of the microprocessor having the construction described above will be explained. First, purge control information for purging a page of the cache memory 1 or 2 is inputted into the setting means 5 through the bus line 4. The setting means decodes the purge control information so as to judge whether it is an instruction for a purge operation of the instruction cache memory 1 or of the data cache memory 2. The purge control information is given to the instruction cache control register 7 or the data cache control register 8 by the setting means 5. Next, the instruction cache control register 7 or the data cache control register 8 decodes the purge control information and then outputs an instruction command to the issue means 6. According to the instruction command, the issue means 6 issues the command into the cache memory 1 or 2 through the comparing means 9 only when the target address set in the instruction cache control register 7 or the data cache control register 8 is equal to the address of a page in the cache memory 1 or 2. Then, the purge operation for the instruction cache memory 1 or the data cache memory 2 is executed for the data designated by the page address in accordance with the instruction for the purge operation based on the command issued by means of the issue means 6. Thereby, the purge operation is finished. Purge operation of both cache memories 1 and 2 can be executed by the same operation described above. By the way, the setting means 5, the instruction cache control register 7, the data cache control register 8, the issuing means 6, and the comparing means 9 can be controlled by software, for example a microprogram stored in the microprocessor. Fig. 2 shows a constructional diagram for the purge control information and the purge control data stored in the instruction cache control register 7 and the data cache control register 8 by the setting means 5. In the same diagram, a physical page number is stored into the part designated by the bits of 0 to 19th (the field length is 20 bits), 203 and 204. These two registers 7 and 8 have the same format. The portion designated by the 27th bit is a cache dump area or CD so as to dump the content of the cache memories when it is one (1). The portion designated by the 28th bit is a cache enable area or CE so as to select whether a purge operation of the cache memories is executed or not. The portion designated by the 29th bit is a snoop enable portion or SE in order to select whether snoop processing is executed or not. The portion designated by the 30th bit is a cache clear portion or CC so as to select whether the entire cache memory is purged or not. The portion designated by the 31st bit is an entry purge portion or EP to select whether an entry in the cache memory is purged or not. The purge operation for the cache memories 1 and 2 is indicated and then executed by the purge control information having the construction described above. Fig.3 is a diagram for comparison among commands in accordance with the control information, and these commands are issued to the cache memories 1 and 2 by the issue means in accordance with the purge control information kept in the control registers 1 and 2 as shown in Fig. 2. In the same diagram, reference character "*" denotes the state of don't care. As clearly shown in Fig. 3, when the purge operation per page is required for the cache memory, the command 3 is issued by the issue means. When the purge operation for all the pages in the cache memory is selected, the command 2 is chosen by it. In this manner of the embodiment according to the present invention, the purge operation for the cache memories is executed by using the command based on the purge control information as described above. Fig. 4 shows a constructional diagram of a microprocessor, particularly showing the cache memory. In the same diagram, reference number 8 is a cache control register such as the instruction and data cache control registers 7 and 8 as shown in Fig. 1. Reference character "TLB" denotes a Translation Lookaside Buffer. In the TLB, reference character LA is a portion keeping a virtual address used for indirect addressing mode, (hereinafter the virtual address is called the "logical address") and PA is a portion for storing a physical address as used for direct addressing mode. Reference number 48 is a comparator for comparing the physical address stored in the TLB with an address per page of the data cache memory 2. A tag portion 44 of the data cache memory 2 comprises a valid bit 61 or V, a physical address PA, a modified bit 63 or M, and an effective bit group 64 designated by V0, V1, V2 and V3. The valid bit 61 shows whether data or content of the page designated by the cache control register is effective data or not, namely whether the purge operation for the page may be executed or not. The modified bit 63 is used for indicating an intention to replace the content of the page. Bit group 64 indicates status information. Fig. 5 shows in detail a construction diagram of the cache memory 2, the cache control register 8, the command issue portion 43 as the issue means 6, and the comparator 42 according to the microprocessor as shown in Fig.1. In the following explanation, the case in which the setting means 5 as shown in Fig. 1 indicates a purge operation for the data cache memory will be explained. First, the setting means 5 (not shown in Fig. 5) sets purge information per page into the data cache control register 8 for the data cache memory 2. The command issue portion 43 transfers the target address of the purging operation to the comparator 42. The pointer 41 is incremented by one (1) and then the address in the data cache memory 2 designated by the pointer 41 is compared with the address temporarily stored in the comparator 42 by the comparator 42. When the target address agrees with the page address, the comparator 42 transmits an address agreement signal to the command issue means 43. Then, the control signal for purging the page indicated by the target address is given into the data cache memory 2. Thereby, the purge operation is completed. In the embodiment as described above, the purge operation for the data cache memory is explained. In addition, the purge operation for the instruction cache memory can be executed by using the same operation. Fig. 6 shows a diagram of a microprocessor of another embodiment according to the present invention. The construction of Fig. 6 differs from that of the microprocessor as shown in Fig. 5 by the presence of comparators 51, 52, 53 ... which are incorporated for each physical page address of the data cache memory 2. The command issue portion 43 receives address agreement signals, each of which indicates information whether the target address agrees with the page address in the data cache memory connected to the comparator or not, applied from comparators 51, 52, 53,..... Each comparator transfers the information to the command issuing portion 43. The pointer 41 used in the embodiment as shown in Fig. 5 therefore need not be used in the present embodiment. Accordingly, the searching speed of a target address for purging operation is higher than that of the microprocessor as shown in Fig.5. In the microprocessors as described above, the command issue portion as the issue means and the comparators as the comparing means are simply added into the conventional microprocessor so that the purge operation per page can be realized. Moreover, only one comparator is incorporated in the microprocessor as shown in Fig. 5. On the other hand, there is the comparator provided per page constituting the data cache memory in the embodiment as shown in Fig.6. However, the present invention is not limited by the above embodiments. For example, the pointer and comparator may be incorporated into each of a plurality of groups each of which comprises plural pages in the microprocessor so as to obtain a similar effect. Moreover, in the embodiments, the cache memory comprises the instruction cache memory and the data cache memory. However, this invention is not limited to the embodiments described above. For example, even when the number of cache memories is only one, we can get the same effect. Furthermore, in the embodiments, the purge control information has the field of 32 bits. However, the present invention is not limited to the embodiments. We can use a field having a suitable length so as to obtain the same effect. In addition, when the present invention is applied to a microprocessor having a cache memory capacity of 4K bytes or more, we can further get the most effective result. Various modifications will become possible for those skilled in the art after the teaching of the present disclosure without departing from the scope thereof as defined in the claims.

Claims: A microprocessor incorporating a cache memory (1,2), storing pages of data, comprising: a control register (7,8) for storing control information indicative of a selected one of a plurality of cache handling operations relevant to purging the cache memory, said control information including a page address for purging; setting means (5) for transferring the control information to the control register (7,8); comparing means (9) for comparing the page address for purging with respective page addresses stored in the cache memory (1,2); and issue means (6), responsive to the result of comparing by the comparing means, for providing a command to the cache memory (1,2) in accordance with the control information in order to initiate said selected one of a plurality of cache handling operations for the entry identified by the page address for purging. A microprocessor according to Claim 1, wherein the cache memory comprises an instruction cache memory (1) and a data cache memory (2). A microprocessor according to Claim 2, wherein the control register comprises an instruction cache control register (7) for storing the control information for controlling the operation of the instruction cache memory (1) and a data cache control register (8) for storing the control information for controlling the operation of the data cache memory (2). A microprocessor according to Claim 2 or 3, wherein capacities of the instruction cache memory (1) and the data cache memory (2) are 4 K bytes or more. A microprocessor according to Claim 2, wherein only one comparing means (42) is incorporated for each of the instruction cache memory (1) and the data cache memory (2). A microprocessor according to Claim 2, wherein a comparing means (51,52,53 ...) is incorporated for each page in the instruction cache memory (1) and the data cache memory (2). A microprocessor according to Claim 2, wherein a comparing means is incorporated for each group of pages constituting the instruction cache memory (1) and the data cache memory (2). A microprocessor according to Claim 1, wherein the command comprises a cache dump field (CD) to cause a dump of the content of the cache memory (1,2), a cache enable field (CE) to select whether a purge operation of the cache memory (1,2) is executed or not, a snoop enable field (SE) to select whether a snoop processing is executed or not, a cache clear portion (CC) to select whether the whole contents of the cache memory (1, 2) are purged or not, and an entry purge portion (EP) to select whether a page in the cache memory (1, 2) is purged or not. A microprocessor according to Claim 8, wherein the control register (7, 8) comprises at least a field to set a physical address, and a field to set the command.

Inventors: KATO RIKAKO, TAKAI HIROYUKI, KATO, RIKAKO, TAKAI, HIROYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F12
IPC codes: G06F12