Circuit for testability

Abstract: Disclosed is a circuit for testability to be provided in a logic circuit comprising a plurality of functional groups which are respectively composed of a plurality of register groups (100 to 107) respectively comprising a plurality of resisters having the same functions. The circuit for testability is characterized by composition in which each the register group (100 to 107) is corresponding to each scan path (SP100 to SP107), and each the scan path (SP100 to SP107) is selected by an address decoder (118), further each the register group (100 to 107) carries out input and output of data to bus lines (IB0 to IB7) through the corresponding scan path (SP100 to SP107), whereby register groups can be divided so as to separate tests on an internal logic circuit of the functional blocks (22, 24) and tests on a logic circuit related to I/O signals of the functional blocks (22, 24). Further disclosed is another circuit for testability characterized by composition in which scan paths respectively corresponding to register groups (100 to 107) which are inputted test data and those outputted test data in functional blocks (22, 24) as objects in the tests are connected to the same bus lines, whereby the number of the bus lines to be required can be reduced.

Description: CIRCUIT FOR TESTABILITY BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a circuit for testability on a logic circuit or the like to be packaged on a system LSI, and particularly to composition of scan paths for serial scanning. Description of the Prior Art Recently, a logic circuit which is packaged on a system LSI becomes large in scale, thus the length of a testing time of the circuit becomes one of problems in manufacture thereof. As an effective method of testing the logic circuit, for example, a parallel scan method and a serial scan method are known. Of these, in the parallel scan method, it is possible to designate addresses of any given registers which are objects of the test in the logic circuit. Accordingly, the method can effectively carry out various tests in the case. However, it requires a lot of circuit elements only for the test, and the whole scale of the system becomes unnecessarily large. While, in the serial scan method, addresses of a serial group of registers are designated so that reading and writing on each of the register groups are conducted. Namely, since the address designation is conducted corresponding to each the register group, the method requires relatively few circuit elements for the address designation as compared with the parallel scan method. However, in this case, the whole bodies of the register groups whose addresses are to be designated should be scanned even if it is unnecessary, thus it takes so much time. As a countermeasure against the problems, there are a method in which a plurality of scan paths are scanned at the same time by internal buses, and a method in which scan paths are provided in respective functional blocks in the logic circuit so that tests on the functional blocks are independently carried out. The last method in the above describe, that is, the method in which scan paths are provided in the respective functional blocks, is superior in that the functional blocks can be tested independently. However, when the mutual relations among the respective functional blocks are tested as a combinational circuit in which are arranged input and output portions of the functional blocks, dummy test data should be set even in register groups other than those which are objects of the tests on the functional blocks. Accordingly, the test requires so much time. Such a testing circuit is known from US-A-4.698.588. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a circuit for testability which can efficiently carry out tests on respective functional blocks and a combinational circuit defined among the respective functional blocks. The object of the invention is solved by a circuit for testability to be provided in a logic circuit composed of a plurality of functional blocks, comprising: a plurality of register groups obtained by division of a plurality of registers included in the functional blocks, one portion of the register groups being composed of registers other than those related to the input and output of the functional blocks; scan paths for scanning the register groups so as to carry out input and output of storage contents of the register groups respectively corresponding thereto, each of the scan paths being connected to a common bus of the logic circuit and carrying out the input and output of the test data through the common bus, and control means for designating addresses of the scan paths and controlling input and output of test signals for the register groups respectively corresponding to the scan paths, characterised in that another portion of the plurality of the register groups included in the functional blocks is composed of registers only related to input and output of the functional blocks, and in that the plurality of the register groups included in the functional blocks are respectively connected to different signal lines of the common bus. According to the above-mentioned composition in the circuit for testability of the present invention, only addresses of the scan paths to be connected to the register groups related to the input and output can be carried out when the tests on the combinational circuit defined among the respective functional blocks are conducted. Thus, the tests can be efficiently carried out. These and other objects, features and advantages of the present invention will be more apparent from the following description of preferred embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a schematical block diagram of a system LSI having a circuit for testability according to the present invention; Fig. 2 is a block diagram of a logic circuit having a circuit for testability, which is an embodiment according to the present invention; and Fig. 3 is a block diagram of a logic circuit having a circuit for testability, which is another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENT Hereinafter, embodiments of the present invention will be described with reference to Figs. 1, 2 and 3. Fig. 1 is a schematical block diagram of a system LSI having a circuit for testability according to the present invention. In the diagram, reference numerals 12 and 14 respectively designate functional blocks including a combinational circuit, a group of storage means and the like. Moreover, 16 indicates a testing control circuit, and 18 shows a common bus for connecting the functional blocks 12, 14 and the testing control circuit 16, further 20 shows an internal bus which is used for input and output of data transmitted between the functional blocks 12 and 14. The above-mentioned functional blocks 12 and 14, testing control circuit 16, common bus 18 and internal bus are all incorporated in a one-chip LSI. In LSI 10 having composition as stated above, operational tests on the functional blocks 12 and 14 are carried out under control of the testing control circuit 16. Fig. 2 is a block diagram of a logic circuit having a circuit for testability, which is an embodiment of the present invention. In the same diagram is shown a circuit for testability of a logic circuit, which is mainly composed of functional blocks 22 and 24. The functional blocks 22 and 24 respectively and mainly comprise functional circuit 26 and 28 for effecting processes corresponding to the respective functions thereof, and input-output (I/O) control circuits 30 and 32 for controlling input and output between the functional blocks 22 and 24. While, register groups 100, 101, 102, 103, 104, 105, 106 and 107 in the embodiment respectively comprise four registers, for example flip-flops (F/F), as storage means. Moreover, these register groups 100 - 107 are respectively connected to scan paths SP100, SP101, SP102, SP103, SP104, SP105, SP106 and SP107. While the four F/F which compose each the register group are connected in series to the scan paths. Additionally, switch elements 110, 111, 112, 113, 114, 115, 116 and 117 are provided as selecting means for the respective scan paths. These switch elements are selected and driven through signal lines of the address bus A0 - A7 by a decoder 118 which is one of control means. In such a manner, the decoder 118 outputs control signals for designating register groups to be objects in the tests. Therefore the switch elements become active or inactive states. Incidentally, the registers in the embodiment are divided into groups based on predetermined functions thereof. For example, the registers are classified into registers belonging to functional circuits, ones belonging to output control circuits and others to input control circuits, and one register group is formed with registers of the same function. In connection of the respective scan paths SP100 - SP107 and the common bus 108, the scan paths SP100 - SP107 are connected different bus lines IB0 - IB7 respectively. Namely, in this case, scan paths which can be selected and operated at the same time are connected to different bus lines as explained in more detail hereinafter. The register group 100 is connected to the bus lines IB0 and IB1 through the scan path SP100, 101 is connected to IB2 and IB3 through SP101, 102 is connected to IB4 and IB5 through SP102, 103 is connected to IB6 and IB7 through SP103, 104 is connected to IB0 and IB1 through SP104, 105 is connected to IB2 and IB3 through SP105, 106 is connected to IB4 and IB5 through SP106, and 107 is connected to IB6 and IB7 through SP107. Next, explanations on operation of the circuit for testability in this embodiment having the above-mentioned composition will be given. When the functional circuits 26 and 28 are independently tested, the decoder 118 generates and transmits control signals to the switch elements 110 - 117. Then through scan paths to be selected by the signals, input and output of data to the register groups belonging to the selected scan paths are conducted. For example, when the scan path SP100 is selected, the four registers composing the register group 100 become objects in the test. Next, explanations on tests among the respective blocks will be given. In this case, the switch elements 112, 113, 114 and 115 are selected by the decoder 118. Therefore, the selected switch elements become active. Namely, test data are inputted into the register groups 104 and 102 through the signal lines of the common bus IB0, IB1, IB4, and IB5 (which will be omitted as common bus lines hereinafter) so as to determine test conditions of the I/O control circuits 30 and 32. With respect to the operational results of the I/O control circuits 30 and 32, the data are outputted through the common bus lines IB2, IB3, IB6 and IB7 by scan of the register groups 105 and 103. Time T t1 required for the test between the functional blocks is obtained in the following manner. When the longer one of scan times in the scan paths SP102 and SP104 is L1, and the longer one of scan times in the scan paths SP103 and SP105 is L2, the time T t1 to be required for the test can be approximately shown by the following equation: T t1 ≒ (L1 + L2) X T c where T c is a time required for the scan of each the register (flip-flop). Table 1 shows relations of the input and output of the test data in the respective register groups on the operation of this embodiment as described above. In the table, numeral 1 in the row of Input means input of the test data to each the corresponding register group, and numeral 1 in the row of Output means output of the operational results from each the register group to the internal bus 108 through the corresponding switch elements. While, numeral 0 in the table means that neither input nor output was conducted. As apparently shown in the table, since only register groups 102, 103, 104 and 105 have to be operated on the combinational tests between the I/O control circuits 30 and 32, the tests can be conducted with great efficiency. Fig. 3 is a compositional diagram of a logic circuit including a circuit for testability, which is another embodiment of the present invention. In the diagram, reference characters SP200, SP201, SP202, SP203, SP204, SP205, SP206 and SP207 designate scan paths respectively corresponding to register groups 100 - 107. In the respective scan paths SP200 - SP207 are provided switch elements 210 - 217 which are selected and driven by a decoder 218. The driving manner in this case is the same as described in the first embodiment. Reference numeral 208 indicates a common bus which comprises six bus lines IB′0, IB′1, IB′2, IB′3, IB′4 and IB′5. Moreover, in the drawing, the register group 100 is connected to the bus lines IB′0 and IB′1 through the scan path SP200, 101 is connected to IB′2 and IB′3 through SP201, 102 is connected to IB′4 and IB′5 through SP202, 103 is connected to IB′4 and IB′5 through SP203, 104 is connected to IB′0 and IB′1 through SP204, 105 is connected to IB′0 and IB′1 through SP205, 106 is connected to IB′2 and IB′3 through SP206, and 107 is connected to IB′4 and IB′5 through SP207. In the circuit for testability of this embodiment, when the functional circuits 26, 28 and the combinational circuit to be formed between the I/O control circuits 30 and 32 are tested independently, scan-out of the registers which are used for input is not carried out at a time of input of test data. Namely, scan out of the registers relating to input is not conducted. To the contrary, scan-in of the registers which are used for output is not carried out at a time of output of the test data. Accordingly, the scan paths SP202 and SP203 respectively connected to the register groups 102 and 103 can be connected to the same bus lines IB′4 and IB′5. Namely, when the functional circuit 26 is tested, test data are inputted into the register group 103 through the scan path SP203 from the bus line IB′5. While, contents of the register group 102 are outputted to the bus line IB′4 through the switch elements 212. Moreover, when the I/O control circuit 30 is tested, test data are inputted into the register group 102 through the scan path SP202 from the bus line IB′5. While, contents of the register group 103 are outputted to the bus line IB′4 through the switch elements 213. Similarly, the scan paths SP204 and SP205 respectively connected to the register groups 104 and 105 can be connected to the same address buses IB′0 and IB1. Accordingly, the common bus 208 which should be required in the embodiment can be composed of the six address buses, so that the size of a system LSI to be composed therewith can be reduced so much. Table 2 shows relations between input and output of the test data in the respective register groups 100 - 107 of the circuit for testability of this embodiment. In the table, numeral 1 means that either input or output of the test data was carried out, while numeral 0 means that neither input nor output was carried out. As apparently shown in the table, the circuit for testability according to the embodiment can perform combinational tests (of the I/O control circuit 30 and 32) between the functional blocks 22 and 24 using only the register groups 102, 103, 104 and 105. Accordingly, it is not necessary to set dummy test data in the register groups 100, 101, 106 and 107 which are not directly related to the tests. In the above embodiments, the register groups 100, 101, 102, 103, 104, 105, 106 and 107 are respectively composed of four registers (F/F), however, the respective numbers of the registers (F/F) in these register groups may be different from one another. Generally, in a logic circuit, the number of registers (F/F) composing each register group differs per register group. Accordingly, in case of an ordinary circuit for testability for which is required setting test data (including dummy data) in the whole body of register groups in functional blocks, and when the number of registers belonging to register groups which do not contribute to the tests is larger than that of registers in register groups which contribute to the tests, time T t required for the tests can be expressed by the following equation: T t ≒ 2 X L₃ X T c where L₁ is the number of registers in a register group requiring a longest time to be scanned in register groups to which the test data are inputted, L₂ is the number of registers in a register group requiring a longest time to be scanned in register groups from which results of the tests are outputted, L₃ is the number of registers which do not contribute to the tests, and these L₁, L₂ and L₃ satisfy L₃ > L₁ and L₃ > L₂ . Moreover, in the above equation, coefficient 2 shows that these L₃ pieces of registers are scanned twice so as to input the test data first and then output the result data from these functional circuits. While, since the following equation: 2 X L₃ > (L₁ + L₂) can be established, the relation between T t and the above mentioned time T t1 which is required for the tests between the functional blocks can be expressed by the following equation: T t > T t1 . Accordingly, the time required for the tests becomes inefficiently long when the number of registers in the register groups becomes large. To the contrary, in the circuit for testability according to the embodiment, since it is possible to set the test data only in the register groups which contribute to the tests, the efficiency on test can be much improved. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A circuit for testability to be provided in a logic circuit composed of a plurality of functional blocks, comprising: a plurality of register groups (100 to 107) obtained by division of a plurality of registers included in the functional blocks (22, 24), one portion of the register groups (100 to 107) being composed of registers other than those related to the input and output of the functional blocks (22, 24); scan paths (SP100 to SP107) for scanning the register groups (100 to 107) so as to carry out input and output of storage contents of the register groups (100 to 107) respectively corresponding thereto, each of the scan paths (SP100 to SP107) being connected to a common bus (108) of the logic circuit and carrying out the input and output of the test data through the common bus (108), and control means (118) for designating addresses of the scan paths (SP100 to SP107) and controlling input and output of test signals for the register groups (100 to 107) respectively corresponding to the scan paths (SP100 to SP107), characterised in that another portion of the plurality of the register groups (100 to 107) included in the functional blocks (22, 24) is composed of registers only related to input and output of the functional blocks (22, 24), and in that the plurality of the register groups (100 to 107) included in the functional blocks (22, 24) are respectively connected to different signal lines of the common bus (108). A circuit for testability according to claim 1, characterised in that switch means (110 to 117) is provided to each of the scan paths (SP100 to SP107), each the switch means (110 to 107) is connected to the controlling means (118), and selection of each the scan paths (SP100 to SP107) is carried out by each the switch means (110 to 107). A circuit for testability according to claim 1, characterised in that both of the register groups (100 to 107) related to the input and those related to the output are connected to the same signal lines (IB′0, IB′1) in the common bus (208). A circuit for testability according to claim 1, further characterised by: first scan paths for effecting input and output of storage contents of one portion of the register groups belonging to the circuit portion related to the input and output; second scan paths for effecting input and output of storage contents of the other portion of the register groups belonging to the circuit portion related to the functions other than the input and output; and the first and the second scan paths are respectively and independently provided. A circuit for testability according to claim 4, characterised in that the first scan paths further comprise scan paths related to input and thos related to output respectively. A circuit for testability according to claim 4, characterised in that the register groups (100 to 107) comprise shift registers respectively.

Inventors: TANAKA KOICHI, YAGUCHI TOSHIYUKI, TANAKA, KOICHI, YAGUCHI, TOSHIYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F11
IPC codes: G06F11, G01R31