Improved sense circuit for storage devices such as non-volatile memories, with enhanced sensing discrimination

Abstract: The sense circuit, for recognizing the virgin or programmed status of cells in storage devices, comprises a differential amplifier (DA) having a first input (X o ) connected to a number of selectable matrix cells (T vm , T pm ) through a first uncoupling circuit (INV c , T cu ), a second input (Y o ) connected to a number of selectable reference virgin cells (T vr1 , T vr2 ) through a second uncoupling circuit (INV R , T ru ), respective matrix and reference load transistors (T CL , T RL ) connected between each input of the amplifier and a supply voltage, and a current generator (T s , T b , T o ) connected in parallel to the matrix cells and controlled by the first input of the amplifier to draw a current equal to a predetermined fraction of the current flowing through said first input.

Description: This invention is concerned with a memory having an improved sense circuit for recognizing the virgin or programmed status of the cells in storage devices such as CMOS non-volatile memories, having an enhanced discrimination between virgin and programmed cells of the storage device. In circuits made with COMS technology, where programmable components are used to make non-volatile memories (ROM, EPROM, EEPROM, FLASH), It is necessary to provide a reference system which is able to recognize programmed elements (which are turned off) from non-programmed, or virgin, elements (which are turned on). Recognition is achieved by comparing the current I vr in a virgin reference cell with the current in the matrix element or cell which it is desired to read. The latter current will ideally be zero for a programmed cell (I pm ), non-zero for a virgin cell (I vm ). In order to have a balanced comparison where the discrimination value lies at the middle between I vm and I pm , it is known to shift the discrimination threshold by means either of differently sized loads on the matrix cell and on the reference cell (unbalanced loads), or of an auxiliary current I vr /2 added to the current from the matrix cell under scrutiny (constant or variable offset current). A memory circuit with a constant offset current is known from EP-A-326004. In either case, the difference of the reading from the threshold for a virgin cell and for a programmed cell never exceeds half the value of the current in the virgin cell (I vm /2). Moreover, with the offset current technique, where autonomously implemented current mirrors are used for generating the offset current, the performance may decay further if the electrical characteristics of the transistors in the current mirror are not perfectly identical to the other components of the storage device. Accordingly, the main object of the invention is to provide a semiconductor memory circuit with an improved sense circuit for recognizing the virgin or programmed status of the cells in storage devices, which widens the effective difference of the matrix cell current from the threshold current both for the virgin and for the programmed cell, thus enhancing the discrimination capability of the sense circuit. The invention achieves the above and other objects and advantages, such as will appear from the following disclosure, with a semiconductor memory circuit as defined in claim 1. The invention will now be described in more detail with reference to a preferred embodiment, given by way of illustrative and nonlimiting example, and with the aid of the attached drawings, wherein: Fig. 1 is a diagram of a first preferred embodiment of a memory circuit with a sense circuit according to the invention; Fig. 2 is a diagram of a second preferred embodiment of a memory circuit with a sense circuit according to the invention; and Fig. 3 is an illustrative current-voltage plot showing various current quantities plotted against an increasing supply voltage for a sense circuit according to Fig. 1 or 2. Fig. 1 shows a sense circuit for CMOS EPROMs according to an embodiment of the invention, with partly illustrated arrays of matrix cells and reference cells, all of which are N-channel. T vm and T pm are a virgin cell and a programmed cell, respectively, which are part of a matrix of cells or transistors (not shown fully) of an EPROM storage device made with CMOS technology. Each of the cells T vm and T pm has a grounded source, a gate connected to a row line RV or RP, respectively, and a drain connected to a culumn line CL terminating, via a select multiplexer not shown, into a first input X of a sensing amplifier SA further described below. T vr1 and T vr2 are two virgin reference cells, corresponding to matrix cells T vm and T pm , respectively, and each of the reference cells has a grounded source, a gate connected to the row line RV or RP of the corresponding matrix cell, and a drain connected to a reference line RL terminating into a second input Y of the sensing amplifier SA. Sensing amplifier SA comprises a basic differential amplifier DA, of any conventional design, having a first input X o and a second input Y o , and two P-channel load transistors T CL and T RL , having their drains tied to a supply voltage V cc and their gates driven by the respective inputs X o and Y o of differential amplifier DA. The sensing amplifier SA further comprises respective uncoupling circuits, each comprising a series N-channel transistor T cu resp. T ru , and an inverter INV C resp. INV R , which drive their respective sources and are driven by inputs X and Y, respectively, of the sensing amplifier. These uncoupling circuits also act as preamplifiers for the input signals. The sources of T CL and of T RL are connected to inputs X o and Y o of differential amplifier DA, and, moreover, they are tied to each other through an equalizing P-channel transistor T eq , which is turned on to momentarily short-circuit inputs X o and Y o and loads T CL and T RL during a time slice preceding evaluation, as known in the art. Each of the row lines can be selectively driven high by means not shown, as well known in the art, to select the matrix cell at the crosspoint of the selected column and row. If the selected cell is virgin, such as T vm , a current I vm is caused to flow through it, while, if the selected cell is programmed, such as T pm , an ideally null current I pm will be caused to flow through it. When a matrix cell is selected, the reference cell T vr1 or T vr2 tied to its row line will also be selected, and a current I vr will be caused to flow through it. A current mirror is associated to the selected column line, comprising a P-channel transistor T s having its drain tied to supply voltage V cc , its source connected to ground through a diode-connected, N-channel transistor T b , and its gate connected to input X o of differential amplifier DA, to be driven by the voltage level existing on such input, so that a current equal to 1/4 of the current I DA entering input X o of amplifier DA is forced through T b . The voltage developed across T b drives the gate of a further N-channel transistor T o , which is connected between column line CL and ground. The net effect is to create an offset current I DA /4 in parallel to the selected matrix cell T vm or T pm . With the circuit arrangement described above, a mode of offset current operation is obtained where the offset, rather than being constant, depends on the biasing on the matrix cell and the reference cell being selected. More particularly, as described below, the offset current will be larger if the selected matrix cell is virgin, smaller if the matrix cell is programmed. The difference between the discrimination threshold and the current reading for any given matrix cell is thereby increased above the theoretical limit in conventional sense circuits, either with offset current or with unbalanced loads, and the discrimination performance and tolerance to parameter variation is enhanced. The operation of the circuit of Fig. 1 will now be described. As known to the person skilled in the art, T eq is on while the row and line select operation is taking place, and therefore loads T CL and T RL are shorted to each other during the propagation time, and equal currents flow in both loads. In this condition, when a virgin matrix cell T vm is selected, the following relationship holds: I ov = (I vr + I vm + I ov )/4 where I vr , I vm , I pm have the meanings defined above, and I ov is the offset current when a virgin cell is selected. When a programmed matrix cell is selected, the following equality holds: I op = (I vr + I pm + I op )/4 where I op is the offset current when a programmed cell is selected. In the ideal case, I vr = I vm = I v , and I pm = 0. Eqs. (1) and (2) then reduce to: I ov = (2I v + I ov )/4 I op = (I v + I op )/4, or I ov = (2/3)I v I op = (1/3 )I v . The following inequalities follow: I v < (5/3)I v for a virgin cell, and I v > (1/3)I v for a programmed cell. In other words, a virgin cell will still be correctly evaluated, even if, due to parameter variations or to extreme values of the supply voltage, the current sensed should be larger than (3/2)I v (the governing relationship for a conventional offset current sense circuit). Moreover, the offset current (I ov or I op ) is obtained from the matrix elements themselves, not from a different (though similar) device: therefore, the accuracy of the current is improved. The above situation can be better understood from the diagram of Fig. 3, where the lines show how the values of several current quantities of interest change as the supply voltage V cc varies from 0 V upwards. Line A shows the current I v in a virgin cell; dashed line B shows the current I v /2 which is the discrimination limit for a programmed cell in a conventional circuit; line C is the same limit (current (1/3)I v ) for the circuit of Fig. 1. Similarly, dashed line D shows the current (3/2)I v which is the discrimination limit for a virgin cell in a conventional circuit; and line E is the same limit (current (5/3)I v ) for the circuit of Fig. 1. The ratio 1/4 of the offset current to the load current, or "mirror ratio", may be changed to other values, with a corresponding change in the constants of Eqs. (5) and (6). With a mirror ratio of, say, 1/3, Eqs. (5) and (6) become: I v < 2I v for a virgin cell, and I v > (1/2)I v for a programmed cell. With a mirror ratio 1/5: I v < (5/4)I v for a virgin cell, and I v > (1/4)I v for a programmed cell. The above relationships (i.e. (3) and ff.) hold for I pm = 0. If, as would be the case in the real world, this is not true, then Eq. (6) should read: I v > (1/3)I v + I pm , or (2/3)I v > I pm , i.e., the current in a programmed cell should not exceed 2/3 of the current in a virgin cell for the sensing to be correct. This, again, is an improvement over the performance of a conventional circuit in the same circumstances. It should be noted that all the above equations refer to the initial condition of the sense circuit, i.e. before the offset currents have been modified by the operation of the sense circuit. As soon as T eq has been turned off (i.e. during evaluation), the mirrored current I ov or I op will be increased if a virgin cell has been selected, and decreased if a programmed cell has been selected. Fig. 2 shows an alternative embodiment of the invention, similar to the first embodiment, except that the load transistors, rather than being diode-connected, are cross-connected. The operation of this embodiment is substantially the same as described above, but the cross-connection is a positive feedback that enhances the dynamic range of the signals, both at inputs X and Y, and at inputs X o and Y o . Two preferred embodiments of the invention have been disclosed above, but it is understood that changes may be made to it by a man skilled in the art. In particular, although the expression "programmed" used above suggests that programmation has been achieved by application of electrical biases, it should in fact be understood also to cover programmation achieved by means of masks during the manufacturing process, e.g. in the production of ROMs.

Claims: A semiconductor memory comprising: a plurality of selectable matrix cells (T vm , T pm ) for storing data; a plurality of selectable reference virgin cells (T vr1 , T vr2 ); a current generator (T s , T b , T o ); and a sensing amplifier (SA) for recognizing the virgin or programmed status of said matrix cells (T vm , T pm ) in said memory, said sensing amplifier (SA) comprising: a differential amplifier (DA), a first uncoupling circuit (INV c , T cu ), a second uncoupling circuit (INV R , T ru ), and respective matrix and reference load transistors (T CL , T RL ), said differential amplifier (DA) having a first input (X O ) connected to a number of said selectable matrix cells (T vm , T pm ) through said first uncoupling circuit (INV c , T cu ) and a second input (Y O ) connected to a number of said selectable reference virgin cells (T vr1 , T vr2 ) through said second uncoupling circuit (INV R , T ru ), said matrix and reference load transistors (T CL , T RL ) being connected between a respective input (X o , Y o ) of the differential amplifier (DA) and a supply voltage (V cc ), CHARACTERIZED IN THAT said current generator (T s , T b , T o ) is connected in parallel to said selectable matrix cells (T vm , T pm ) and is controlled by the first input (X o ) of the differential amplifier (DA) to draw an offset current equal to a predetermined fraction of the current flowing through said first input (X o ), said current generator (T s , T b , T o ) being adapted to draw a larger offset current if the selected matrix cell (T vm , T pm ) is a virgin one and a smaller offset current if the selected matrix cell (T vm , T pm ) is a programmed one. The semiconductor memory of claim 1, CHARACTERIZED IN THAT said current drawn by said current generator (T s , T b , T o ) is from 1/3 to 1/5 of the current flowing through said first input (X o ). The semiconductor memory of claim 2, CHARACTERIZED IN THAT said current drawn by said current generator (T s , T b , T o ) is 1/4 of the current flowing through said first input (X o ). The semiconductor memory of one or more of claims 1 to 3, CHARACTERIZED IN THAT said current generator (T s , T b , T o ) includes a current mirror (T b , T o ) driven by a control transistor (T s ) controlled by the same voltage controlling the gate of one of said load transistors (T CL , T RL ). The semiconductor memory of one or more of claims 1 to 4, CHARACTERIZED IN THAT said first and said second uncoupling circuits (INV c , T cu , INV R , T ru ) each comprises a series transistor (T cu , T ru ) controlled by the output of a respective inverter (INV c , INV r ) having its input connected to said matrix cells (T vm , T pm ) and to said reference virgin cells (T vr1 , T vr2 ) respectively. The semiconductor memory of one or more of claims 1 to 5, CHARACTERIZED IN THAT the first and second inputs (X o , Y o ) of the differential amplifier (DA) are connected through an equalizing transistor (T eq ) which is turned on to momentarily short-circuit said inputs (X o , Y o ) during a time slice preceding evaluation.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: G11C16
IPC codes: G11C29, G11C16, G11C17, G11C7