FEEDBACK CLAMPING CIRCUIT

Abstract: A feedback clamping circuit controlled by digital information which can operate stably even when the information is given from a noisy source such as a VTR, and a disk, by controlling the gain or dead zone width of a feedback loop according to the result of decoding control code signals contained beforehand in the input signal and the result of measuring the amount of noises contained in the input signal.

Description: TECHNICAL FIELD The present invention relates to a feedback clamping circuit suitable for processing such as a digital information or the like. BACKGROUND ART FIG. 8 shows a conventional digital feedback clamping circuit whose output is processed by an A/D converter. Referring to the figure, an input signal from an input terminal 1 is clamped by a clamping circuit 2 to a predetermined clamping potential during a period of a clamping pulse from a terminal 3. The clamped signal is then A/D-converted by an A/D converter 4 and then fed to an output terminal 5. A part of the output signal from the A/D converter 4 is supplied to a difference detector 6, in which it is compared with a reference potential (or clamping potential) during a period of a pulse indicative of a reference potential period (or clamping potential period) supplied from a terminal 7. Then, a difference therebetween is amplified by an inverting amplifier 8, D/A-converted by a D/A converter 9 and then supplied through a low-pass filter 10 to the clamping circuit 2 as the clamping potential, thereby effect the feedback operation such that both inputs to the difference detector 6 become always constant. In the case of the feedback clamping circuit constructed as shown in FIG. 8, if the gain of the amplifier 8 and the time constant of the low-pass filter 10 in the feedback loop are made constant when the noise amount of the input terminal from the input terminal 1 is large, then the clamping potential applied to the clamping circuit 2 will be fluctuated by the noise. To solve this problem, the gain of the amplifier 8 must be lowered or the time constant of the low-pass filter 10 must be increased, which degrades the clamping capability. In a known feedback clamping circuit (JP-A-62 128 674), a output signal of a level shifter is compared with a clamping potential. The level shifter is controlled by an error voltage in response to a comparison of the input signal with an reference signal. The error voltage is also supplied to a filter and the output of the filter is added to a reference voltage. As a result, the input that includes much noise can be clamped accurately at the reference level. In this case, high frequency components of the input signal are used to clamp the input signal. In view of the above aspect, the present invention is to provide a clamping circuit which can effect the stable clamping operation even when a source is a source having a large noise amount. A feedback clamping circuit according to the present invention is characterised by the features of Claim 1. The circuit comprises a clamp means for holding the potential of an input signal at a stable clamping potential. An A/D converter receives at its input the output of the clamp means and is outputting a digital output signal. A feedback loop provides the clamping potential based on the digital output signal. The feedback loop comprises identifying means, for identifying a digital control code from the digital output signal. The control code is part of the input signal. The control code being used to control the input/output characteristic of the amplifier. The feedback clamping circuit comprises identifying means for identifying a digital control code signal previously involved in the input signal from the digital output signal to produce the predetermined control signal, whereby the control signal changes the gain or width of dead zone of the amplifier. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram of a circuit configuration showing a first embodiment of the present invention, FIGS. 2 to 5 are graphs of input and output characteristics of an amplifier according to the present invention, FIGS. 6 and 7 are diagrams used to explain operation of the present invention, respectively, and FIG. 8 is a diagram of a circuit configuration showing a conventional example. BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will hereinafter be described in detail with reference to FIGS. 1 to 7. FIG. 1 shows a circuit configuration of a first embodiment according to the present invention. In the figure, like parts corresponding to those of FIG. 8 are marked with the same references and therefore need not be described in detail. According to this embodiment, a control code identifying device 20 is provided at the rear stage of the A/D converter 4 to identify a control code involved in a signal developed at the output side of the A/D converter 4, thereby identifying the kind of the input signal. Then, the gain of the inverting amplifier 8 or the width of the dead band is controlled in response to the identified output. To this end, the input and output characteristic of the inverting amplifier 8 is set in advance in any one of characteristics shown in FIGS. 3 to 5. Input signals supplied to the input terminal 1 might be a BS broadcasting signal and signals such as those supplied from a VTR, a DISC or the like. Proper control codes are generally allotted to the VTR and the DISC because the signal systems of the latter are different from that of the BS broadcasting. Therefore, the kind of the signals (BS/VTR/DISC) and the signal system can be identified by the control code and the signal processing conforming to the kind of the input signal becomes possible. FIG. 6 shows an example of the control code. Assuming that the control code, for example, is formed of of successive 25 bits, then it will be appreciated that the BS broadcasting or other source is allotted to 19'th bit. Therefore, if 19'th bit is "0", then the source is the BS broadcasting while if it is "1", then the source is other source. Further, a control code for identifying the source such as the DISC, VTR or the like is allotted to 20'th bit. If it is "0", then the source is the DISC while if it is "1", then the source is the VTR. Furthermore, 25'th bit is allocated to the control code which is used to identify the noise amount of the source. If it is "0", then the source has a small noise amount while if it is "1", then the source has a large noise amount. A code allocation shown in FIG. 7, for example, is created on the basis of the control code of FIG. 6, whereby the source and the noise amount can be identified. If 20'th bit, for example, is "1" and 25'th bit is "0", then it will be appreciated that the source is a VTR having a small noise amount and an excellent S/N ratio. If 20'th bit is "1" and 25'th bit also is "1", then it will be appreciated that the source is a VTR having a large noise amount and a poor S/N ratio. Further, if 20'th bit is "0" and 25'th bit also is "0", then it will be appreciated that the source is a DISC having a small noise amount. If 20'th bit is "0" and 25'th bit is "1", then it will be appreciated that the source is a DISC having a large noise amount. Accordingly, since the source is identified as the BS broadcasting if 19'th bit is identified as "0" as a result of the identification of the control code identifying device 20, regardless of the status of other code bit, the input and output characteristic of the inverting amplifier 8 is controlled as shown in FIG. 2. If on the other hand it is determined by the identification that 19'th bit is "1", then the signal processing is carried out in accordance with the code allocation of FIG. 7. More specifically, when the input and output characteristic of the inverting amplifier 8, for example, is set to the characteristic shown in FIG. 3, if it is determined by the code identifying device 20 that 20'th bit is "1" and 25'th bit is "1", or the code is "11" as shown in FIG. 7, then the source is the VTR having a large noise amount, thereby widening a gain decrease area a 1 of FIG. 3. If 20'th bit is "1" and 25'th bit is "0", or the code is "10" as shown in FIG. 7, then the source is the VTR having a small noise amount, thereby narrowing the gain decrease area a 1 of FIG. 3. If it is determined by the code identifying device 20 that 20'th bit is "0" and 25'th bit is "1", or the code is "01" as shown in FIG. 7, then the source is the DISC having a large noise amount, thereby widening the gain decrease area a 1 of FIG. 3. If 20'th bit is "0" and 25'th bit is "0", or the code is "00" as shown in FIG. 7, then the source is the DISC having a small noise amount, thereby narrowing the gain decrease area a 1 of FIG. 3. Further, when the input and output characteristic of the inverting amplifier 8, for example, is set to the characteristic shown in FIG. 4, if it is determined by the code identifying device 20 that 20'th bit is "1" and 25'th bit is "1", or the code is "11" as shown in FIG. 7, then the source is the VTR having a large noise amount, thereby widening a dead area width a 2 of FIG. 4. If 20'th bit is "1" and 25'th bit is "0", or the code is "10" as shown in FIG. 7, then the source is the VTR having a small noise amount, thereby narrowing the dead area width a 2 of FIG. 4. If it is determined by the code identifying device 20 that 20'th bit is "0" and 25'th bit is "1", or the code is "01" of FIG. 7, then the source is the DISC having a large noise amount, thereby widening the dead area width a 2 of FIG. 4. If 20'th bit is "0" and 25'th bit is "0", or the code is "00" as shown in FIG. 7, then the source is the DISC having a small noise amount, thereby narrowing the dead area width a 2 of FIG. 4. Furthermore, when the input and output characteristic of the inverting amplifier 8, for example, is set to the characteristic shown in FIG. 5, if it is determined by the code identifying device 20 that 20'th bit is "1" and 25'th bit is "1", or the code is "11" as shown in FIG. 7, then the source is the VTR having a large noise amount, thereby widening a gain decrease area and a dead area width a 3 of FIG. 5. If 20'th bit is "1" and 25'th bit is "0", or the code is "10" as shown in FIG. 7, then the source is the VTR having a small noise amount, thereby narrowing the gain decrease area and the dead area width a 3 of FIG. 5. If it is determined by the code identifying device 20 that 20'th bit is "0" and 25'th bit is "1", or the code is "01" as shown in FIG. 7, then the source is the DISC having a large noise amount, thereby widening the gain decrease area and the dead area width a 3 of FIG. 5. If 20'th bit is "0" and 25'th bit is "0", or the code is "00" as shown in FIG. 7, then the source is the DISC having a small noise amount, thereby narrowing the gain decrease area and the dead area width a 3 of FIG. 5. The output signal from the inverting amplifier 8 whose gain or dead area width is controlled as described above is D/A-converted by the D/A converter 9 and supplied through the low-pass filter 10 to the clamping circuit 2 as the clamping potential. Thus, even when an input signal having a relatively large noise amount is input to this clamping circuit, the clamping potential can be prevented from being fluctuated and the stable clamping operation can be effected.

Claims: A feedback clamping circuit comprising: a clamp means (2) for holding the potential of an input signal at a stable clamping potential; an A/D converter (4) for receiving at its input the output of said clamp means (2) and for outputting a digital output signal; a feedback loop (8, 9, 10) comprising an amplifier (8) for providing said clamping potential based on said digital output signal; the clamping circuit further comprising identifying means (20; 30), for identifying a digital control code from the digital output signal, the said control code being part of the said input signal, the said control code being used to control the input/output characteristic of said amplifier (8). A feedback clamping circuit according to claim 1 wherein said control signal changes the gain of said amplifier (8). A feedback clamping circuit according to claim 1 wherein said control signal changes the width of dead area of said amplifier (8).

Inventors: HARADA SHIGERU, NAGATSU YOSHIHIDE, HARADA, SHIGERU, NAGATSU, YOSHIHIDE
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H03G11
IPC codes: H03G7, H03G11