Circuit for internal current limiting in a fast high side power switch

Abstract: A current limiting circuit (200, 300, 400) for instantaneously limiting the peak current of a fast high side power switch (212) or power FET has a reference switch (213) or FET, a first comparator (218), a current source I CL , control circuitry (209), and a clamping circuit (238). The reference FET (213) is smaller than the power FET (212). The first comparator compares the voltage drop across the power FET (212) and compares it with the voltage drop across the reference FET (213) and produces a signal COMPOUT which initiates the turn-off of the power FET (212) if the voltage drop across the power FET (212), caused by a load current flowing through it, is greater than or equal to the reference FET voltage drop induced by I CL . The clamp circuit (238), having diodes (D₁, D₂) and a tracking current source I' CL , disconnects the FETS (212, 213) from the comparator (218) when they are OFF. The circuit (200, 300, 400) may also have a second comparator (250) which protects the power switch (212) from a short circuit condition in the circuit (200, 300, 400).

Description: The present invention broadly relates to power circuitry, especially of the type employing a control circuit for limiting the current in a power switch and preferred embodiments of the invention involve limiting the current in a high side switch and protecting the switch from short circuits. In integrated circuits, control circuitry is often integrated with the power circuitry for protecting the switching elements from excessive current, voltage, temperature, etc. Two conventional current limiting circuits are the "Classic" power MOS circuit and the current mirror circuit. Referring to Figure 1, the "classic" power MOS circuit 10 having a MOS FET 12, a current-sense resistor (R S ), an amplifier 16 with fixed gain (A I ), a comparator 18, a lowpass filter 20 and a flip flop 22 is shown. The classic circuit 10 is a "low-side" power switch since the switching circuitry 10 is located beneath a load 24 and between ground 26. R S carries the entire load current I L and senses the current. R S typically has a small sense resistance in order to minimize the power dissipated across the sense resistor, R S . The voltage is amplified by the amplifier 16 and input into the comparator 18 for comparison with a reference voltage, V CL . V CL is the current limit voltage and it is selected, knowing the resistance of R S , to correspond to the particular current limiting threshold so that when the voltage across R S is greater than or equal to V CL , the current limit circuit 10 cuts off further current flow though the FET 12. When the voltage across R S is greater than or equal to V CL , the comparator 18 outputs a signal 34 which the flip flop 22 responds to. The flip flop 22, in the example, is a Q flip flop. Thus if the signal out of the comparator 18 is high, Q out is low, and an invertor 36 inverts Q which shuts off the FET switch 12. The signal out of the switch 12 is filtered by the low pass filter 20 prior to amplification in order to filter out any false current spikes which occur when a diode (not illustrated) from the load 24 is reverse biased. The diode does not shut off instantaneously and thus false current spikes are generated as the diode acts like a short circuit initially. If the spikes are not filtered then the comparator 18 may output incorrect comparison results. While the circuit 10 is simple to construct, it has several disadvantages: a large amount of power is dissipated in R S ; in a fully internal current limit, the temperature coefficient T C of R S needs to be accounted for since the resistance of R S changes with temperature; and a lowpass filter 20, or a comparable device, is necessary to protect against false limit triggering during the recovery-time of the external catch diode. In addition, since the reverse recovery time of conventional diodes falls within a range that covers usually more than an order of magnitude (e.g., between 25 nsec and 350 nsec), the attainable minimum pulse-width, during the current-mode operation, is limited to accommodate for poor diode recovery time. The longer the recovery time (diode), the more limited the smallest duration of ON time that can be controlled. Thus, the circuit 10 is slowed since the pulse-width has to be large enough to accommodate for the diode recovery time, and thus, the circuit is not well suited for use in fast circuits. Referring to Figure 2, a conventional sense-FET or current mirror circuit 50 having two MOS FETs 52, 53 in parallel is shown. The first MOS FET 52 is called the Power FET (or Power switch) since it is larger than the second MOS FET 53, called the Sense FET. The FETS 52, 53 have the same characteristics since they are fabricated on the same silicon wafer. The current mirror circuit 50 is a low side power switch since the switch circuitry is below the load 64 and between ground 66. Unlike the classic circuit 10, the current mirror circuit 50 does not measure the current through the power switch 52. Rather, the load current I L is mirrored at a lower level through the sense FET 53. The current I S in the sense FET 53 is much smaller than the current I P in the power FET 52. However, since the two FETS 52, 53 have substantially the same characteristics, the devices are proportional to one another. The current I P in the power FET 52 can be determined if the sense FET current I S is known, since the two currents I P , I S are related to one another. Using a sense FET 53 reduces the amount of power that is dissipated in R S because, although the sense FET 53 mimics the power FET current I P , it does so at a substantially lower magnitude of current than the power FET current I P ; (e.g., I S is 0.05% of I P ). Hence, R S only carries approximately 1/2000 to 1/10000 of the total power from the load 64. This is because the sense FET 53 is made substantially smaller than the Power FET 52. The current in the sense FET I S is sensed and, filtered prior to being amplified by amplifier 56. The amplified signal is compared with a current limit voltage signal V CL in a comparator 58. Again when the voltage dropped through R S is greater then V CL , the comparator 58 outputs a signal which triggers a flip flop 72; the signal out of the flip flop 72 is inverted by inverter 76 and the Power Switch 52 is switched OFF. The comparator 58 does not switch ON the power FET 52 until after the reverse recovery current moves through the power FET 52. While, the current mirror circuit 50 alleviates the power dissipation problem in R S , the current mirror circuit 50 has the same disadvantages as the classic circuit 10. The circuit 50 also has the disadvantage of being nonlinear, which is undesirable in some applications. It is difficult to use this design in high-side switches because the point normally assumed to be ground or an unchanging potential in low-side switches is the point, in high-side switches, which is connected to the load, and thus the voltage continuously changes. Reference is now made to Figure 3 wherein the sense-FET current limit circuit 80 is used in a high-side switch. In the high-side switch, the sense FET circuit 80 is similar to the current mirror circuit 50, except that the sensing circuitry 80 is located above the load 94 and ground: the Power FET 82 and sense FET 83 are located between the power supply V S . Hence, V CL is referenced to the output of the power switch 82; not to ground as in the low-side switch 50. In a high-side switch, the common mode input voltage 84, of the current amplifier 86 and the comparator 88 are tied to the output of the power switch 82 and thus, the common mode input voltage 84 is equivalent to the output of the power switch 82. The disadvantage with this design is that the output of the power switch 82 moves at an extremely high speed of approximately 500-1000 V/µsec between ground and V S during every on-off cycle. In A 30A 30V DMOS Motor Controller and Driver , I.E.E.E. International Solid-State Circuits Conference (Feb. 18, 1988), a circuit for a current limiting operational amplifier having a sensing resistor and sense FET used in a Figure 3-type configuration is believed to be illustrated. The circuit has a power FET and a sense FET and uses the voltage drop across a sensing resistor R s to sense the source current of the power FET. The circuit also has two comparator circuits, one being used when the power FET is ON and the other being used when the power FET is OFF. The invention is directed to a current control circuit for use in a switching regulator circuit. The current control circuit has a power switching device, which is turned off and on to supply current to a load over a periodic, controllable duration of time, and the circuit is responsive to the voltage drop across the power switching device. The power switching device has an internal resistance when it is conducting current so that there is a determinable and measurable voltage drop across the power switching device for a specified current flowing through the power switching device. The current control circuit comprises reference means for providing a reference voltage and means for comparing the voltage drop across the power switching device and said reference voltage. The current control circuit has means responsive to the comparing means to switch off the power switching device when the current limit voltage is reached. These features, set forth in the preamble of claim 1, are known from DE-A-3 430 961. The current limit voltage are determined by the circuit having a reference means coupled to the power device for providing a value of resistance which tracks or mimics change in the resistance of the power device. The reference means is biased by a reference current source which sets up a current limit voltage on the reference means. The voltage drop across the reference means and the power device may be compared to determine when the current limit level has been reached. The circuit may have biasing means for biasing the circuit when the power device is turned off to provide reference current with a current path. In addition, the circuit may also have means for monitoring the voltage drop across the power device and switches off the power device if the voltage drop across the power device is not below a preselected level during a preselected time period. It is therefore an object of the invention to provide a circuit to internally limit the current in fast high side power switches. It is advantageous that the On resistance of the circuit's power switch can be used as a sense resistor. It is advantageous that a circuit can be provided which limits the common mode voltage range of the current limit comparator and keeps it in the active linear operating mode during both the on and off times of the power switching element to provide the fastest possible current limit operation. It is advantageous that a circuit can be providedwhich protects the power switch during a short circuit condition. It is also advantageous that a current limit circuit for fast high side switches can be provided which does not dissipate large amounts of power across sense resistors or require a filtering-type device to protect against false limit triggering. These, and further objects and advantages of the present invention will be made clear or will become apparent during the course of the following description of the preferred embodiment of the present invention. In the accompanying drawings: Figure 1 is a circuit diagram of a classic current-limit circuit; Figure 2 is a circuit diagram of current mirror circuit in a low side switch; Figure 3 is a circuit diagram of a current mirror circuit in a high side switch; Figure 4 is a circuit diagram of a current mirror circuit embodying the present invention; Figure 5 is circuit diagram of another embodiment of the present invention; Figures 6a-6f are timing diagrams for circuit of Figure 5; Figure 7 is another circuit diagram embodying the present invention. Figures 8a-8k are diagrams corresponding to the circuit of Figure 7 for the no short circuit condition; and Figures 9a-9l are diagrams similar to Figures 8a-8k, for the short circuit condition. Referring to Figures 4 and 5, current limiting circuits 200, 300, for instantaneously limiting the peak current of high-side switches, are shown. The circuit 200 is comprised of two FETs 212, 213: a power FET 212 and a reference FET 213; a comparator 218; a current source (I CL ); a control circuitry 209 including a flip flop 222 and an inverter 236; and a clamping and decoupling circuit 238. The reference FET 213 is substantially smaller than the Power FET 212 and, in the preferred embodiment, the FETS are MOS FETs. The power MOS-FET 212 consists of N cells and the reference MOS-FET 213 consists of n cells where n>=1 and N>>n. The Power FET 212 has three terminals 202, 203, 204: the first terminal 202 is connected to a supply voltage V S ; the second terminal 203 is connected to the control circuitry 209 which turns the power FET 212 ON and OFF; and the third terminal 204 is the output terminal, which is connected to a load, 224. The reference FET 213 also has three terminals: the first terminal 205 is connected to V S , second terminal 206 is connected to the second terminal 203 of the power FET 212 and the third terminal 207 is connected to the current source, I CL . The ON resistance of the power MOS transistor 212 can be viewed as operating like a current sense resistor. However, because of the variability of the ON resistance of such devices over temperature and processing variations, the second FET (or reference FET) 213 is employed to provide an ON resistance which is proportional to and which tracks the ON resistance variations of the Power FET 212. Because the ON resistance of reference FET 213 is proportional to and tracks the ON resistance of Power FET 212, I CL can be set up to provide a reference voltage across reference FET 213 against which the voltage drop across the Power FET 212 can be compared. I CL therefore can be selected to produce a voltage drop across the reference FET 213 which equals the voltage drop across the power FET 212 when the current through the power FET 212 equals the level at which current limiting is desired to occur. The ON resistance of the reference FET 213 is dependent upon process parameters and temperature, and weakly dependent on the voltage between the second terminal 206 and the third terminal 207 if V GS >> V TH , where V TH is the threshold voltage of the FET 212. The voltage drop across the turned-on power MOS-FET 212 is much higher than the maximum allowed voltage drop on the prior art sense resistors R S in the sense-FET type current limit circuits 50, 80 which required an amplifier 56, 86 in order to increase the sense voltage into the comparators 58, 88. Hence, no current amplifier (A I ) is needed, and therefore the physical layout of the circuit is smaller than the physical layout in the sense-FET current limit circuits 50, 80. The reference FET 213 establishes the current limit set point. The load 224 is connected to the output of the power FET 204. A voltage, V₁, out of the Power FET 212 is input into the comparator 218 for comparison with a voltage, V₂, out of the reference FET 213. The comparator output COMPOUT is input into the logic circuitry 209 and triggers the logic circuitry 209 to output a signal which controls whether the power FET 212 is to be turned ON/OFF. The current source I CL establishes a known current through the reference FET 213 and the reference voltage V2 is determined by the ON resistance of FET 213. Since the two FETS 212, 213 have the same characteristics, the ON resistance of the Power FET 212 is related to the ON resistance of the Reference FET 213. The resistance of FET 213 differs from the ON resistance of the FET 212 based upon the size of the FET, but both devices 212, 213 have the same ON resistance per unit area. The first input terminal of the comparator, IN1, is connected to the Power FET output terminal 204 through the clamping and decoupling circuitry 238. The second input terminal, IN2, is connected to the reference FET output terminal 207 through the clamping and decoupling circuitry 238. The comparator 218 compares the voltage drop across the power FET 212 to the voltage drop across the reference FET 213. It outputs a signal COMPOUT which initiates the turn-off of the power FET 212 if the voltage drop across the Power FET 212, caused by the load current flowing through the power FET 212, is equal to or greater than the reference FET voltage drop induced by the current source I CL . The load current, I LOAD , is switched ON by the power FET 212 and if the power switch 212 is turned ON, the voltage, V₂ from the reference FET 213 is set by the reference FET's ON resistance R ONREF and I CL where V₂ = V S - R ONREF * I CL - V D where R ONREF = the ON resistance of the reference FET 213 I CL = the current limit V D = voltage drop on the clamp and decoupling circuitry 238 The comparator 218 compares V₂ with V₁ where V₁ = V S - R ONPWR * I LOAD - V D where R ONPWR = the ON resistance of the power FET 212 The comparator 218 resets the input flip-flop 222 in the logic circuitry 209 and turns OFF the power switch 212 (power FET) when V₁ ≦ V₂. Hence, the power switch 212 is turned OFF if: R ONREF * I CL ≦ R ONPWR * I LOAD R ONPWR /R ONREF approximately equals n/N since the per cell resistance of the two devices 212, 213 is approximately equal since they are fabricated on the same piece of silicon under the same processing conditions. Hence, the load current, I LOAD is limited to I LOAD = I CL * N/n, where I LOAD is the current limit level. Hence, I LOAD can be programmed by the current I CL since I CL << I LOAD . The clamping circuitry 238 clamps the inputs to the comparator IN1, IN2 when the FETs 212, 213 are OFF to keep the comparator's 218 inputs within their active linear common mode voltage range so that the comparator 218 does not signal over current to the logic circuit 222. In addition, the clamping circuit 238 connects the comparator 218 to the FETs 212, 213 when they are ON and disconnects them when they are OFF. Referring to Figures 6 a-e also, when the power switch 212 is OFF (V₂ < V₁) as illustrated in Figures 6a and 6d, the comparator output COMPOUT is low, and as shown in Figure 6e, the comparator 218 cannot reset the flip-flop 222 until V₁, the voltage out of the power FET 212, rises to nearly its final potential. By this time a current spike 225, (illustrated in Figure 6b), caused by the reverse recovery time of a blocking diode D in the load 224 is almost entirely over. The reverse recovery current 225 for the blocking diode D is present for a time t₁, during which the comparator 218 remains off. The comparator 218 is not effected by the current spike 225 which could cause false triggering of the comparator 218. The reverse recovery current 225 also produces a delayed change in the voltage V₃ out of the power FET 212. Referring to Figures 6b and c concurrently, V₃ goes negative during the reverse recovery time t₁ of the blocking diode and then rises to its final potential V S -V DSPWR (source voltage - the drain source voltage for the power FET) after the spike 225 has passed. It is believed that, in this manner, the current limit circuit 200 inherently gates out the "false" current spike 225 thereby eliminating the need for a lowpass filter and decreases the time required for performing the current limit operation. Referring to Figure 5, another current limit control circuit 300 similar to the control circuit 200 in Figure 4 is illustrated. The circuit 300 has a load 224 and a clamp circuit 238 having a pair of diodes D1, D2, a tracking current source I′ CL , and two bipolar junction transistors, Q1 and Q2. Similar elements are referenced with the same reference numerals/names. The load 224 includes an inductor L O , a catch diode D, a capacitor C O , and a load resistor R L . The current limit circuitry 300 monitors and limits the load 224 by limiting the maximum peak current that is permitted to flow through the inductor L O . The inductor voltage changes instantaneously but the inductor current changes slowly since V LO = L O di dt The clamp and decoupling circuit 238 is inserted between a clamp bias voltage, V BIAS and the comparator inputs IN1, IN2. V BIAS is generated relative to the supply voltage V S and it is selected so that Q1 and Q2 are OFF when FETs 212 and 213 are conducting, even at load currents which are slightly higher than I LOAD . The clamp bias voltage V BIAS has roughly the same temperature coefficient as the ON-resistance of the power FET 212. When the power FET 212 and reference FET 213 are ON, the clamp circuit 238 is not active and does not effect how the circuitry 300 operates. V₂ will not be higher than V S - I CL * R REF and V₁ is not clamped by Q1. However, when the FETs 212, 213 are OFF, D1 and D2 become reverse biased and the clamp circuit 238 clamps the inputs of the comparator IN1, IN2 so that the voltage on IN1 is always more positive than the voltage on IN2. Hence, the comparator output COMPOUT is low and it does not signal over current. In addition the common mode voltage swing on the inputs of the comparator IN1, IN2 is limited to a substantially smaller value than the voltage swing on the output terminal 204 of the power FET 212 when FETs 212 and 213 are OFF. In this manner, it is ensured that the comparator 218 is always in its active common mode range and there is a recovery time after turn-on. In addition, diodes D₁ and D₂ are inserted between the comparator input terminals IN1, IN2 and the output terminals 204, 207 of the power FET 212 and reference FET 213. The anode of D₁ is connected to the output terminal of the power FET 204, and the cathode of D₁ is connected to the first input terminal IN1 of comparator 218 and to the tracking current source I′ CL . The tracking current source I′ CL tracks the current of the current source I CL . The anode of D₂ is connected to the output terminal 207 of reference FET 213 and the cathode of D₂ is connected to the second input terminal IN2 of the comparator 218 and to the current source I CL . D₁ and D₂ are blocking diodes which act like switches. D₁ and D₂ disconnect the FETs 212, 213 sources 204,207 from the comparator inputs IN1, IN2 during the FETs' 212, 213 OFF time. Being reverse biased, the diodes D₁, D₂ take up the voltage difference between V BIAS and the FETs' 212, 213 output voltage which is approximately 0. Hence the diodes D1, D2 and the clamp circuit 238 limit the common mode voltage transient of the comparator's inputs IN1, IN2 thereby ensuring that the comparator inputs IN1, IN2 are always within their active common mode range and the highest possible operating speed without any recovery time. Reference is made again to Figures 6a-6f illustrating the timing diagrams for the circuit 300 of Figure 5. Figure 6a is a timing diagram illustrating when the power switch 212 is ON, (i.e., when there is a voltage potential between the gate and source of the FET). Figure 6b is a timing diagram illustrating the load current I LOAD when the power FET 213 is ON/OFF. The diode's reverse recovery time is t₁ and the reverse recovery current 225 looks like a "spike"; at t₂ the diode D reaches an equilibrium and the diode voltage begins to reverse and the diode current begins to decrease. The ratio of t₁ to t₂ depends upon the softness of the recovery characteristic of the catch diode. However, usually t₂ < 0.2t₁, where t₂ <= 20-50 nsec. In most cases the inherent delay of the comparator 218 takes care of the portion of t₂ during which I LOAD > I LOAD . When very soft recovery diodes and very fast comparators are employed, some delay (filtering) may be needed (LPF in Fig. 5). Yet, the delay needed is about an order of magnitude less than the delay needed in the classical circuit 10. Hence, this small time delay can be achieved by resistor and capacitor values available in monolithic integrated circuits. No external components are required as in the case in the substantial analog time delay of previous approaches. As illustrated, after the diode's reverse recovery times t₁, t₂ have passed, the load current increases to I LOAD PEAK , the maximum current that is allowed to flow to the load. When the maximum load current is achieved, the power switch 212 is to be turned OFF, and the comparator 218 outputs a signal, COMPOUT, as illustrated in Figure 6e, to shut off the power switch 212. Figure 6e is a timing diagram of the comparator output COMPOUT. When the power FET 212 is ON, the diode D is OFF and the current I LOAD in the inductor rises linearly, with a slope of dI L dt The comparator 218 is disabled by the clamp circuit 238 during most of the diode D recovery time (t₁) thus avoiding false limit triggering. COMPOUT is about zero When the power FET 212 is ON. But, at the end of the power switch 212 ON time, when the inductor current reaches its peak value I LOAD PEAK, V₁ approximately equals V₂, COMPOUT goes high and the power switch 212 is turned OFF. Referring to Figure 6c, voltage V₃ is the voltage measured at the output of the power switch 212. V₃ initially goes negative during the diode's D reverse recovery time t₁ but then it rises to its final level of V S - V DSPWR , where V DSPWR is the drain to source voltage of FET 212. V₃ and I LOAD rapidly decreases when the FET 212 is shut OFF. Referring also to Figure 6d, the voltages V₁ and V₂ are shown when the power switch 212 is ON and OFF. As illustrated, initially, when the power switch 212 is OFF, V₁ >V₂. When the switch is ON, V₁ remains greater than V₂, but as the duration of the ON time increases, the voltage difference between V₁ and V₂ decreases such that when V₂ substantially equals V₁, the power switch 212 is turned OFF, and V₁ resumes being greater than V₂. Thus, V₁ is greater than V₂ when the power switch 212 is OFF and when the switch 212 is ON. The switch 212 is turned OFF when V₁=V₂. Referring to Figure 6f, concurrently with Figure 6b, when the switch 212 is OFF, the inductor current I LO is conducted by diode D. The inductor current I LO decreases linearly until the power switch 212 is turned ON again, at which point the inductor L O begins to store up energy and thus, the inductor current I LO increases linearly. Reference is now made to Figure 7 which shows another current limit circuit 400 similar to the circuit of Figure 5, but having been modified to protect the power switch 212 if there is a short circuit between the output of the power switch 204 (V₃) and ground. If there is a short circuit in the circuit of Figure 5, comparator 218 remains disabled and the power switch 212 is unprotected. The clamp circuit 238 disables the comparator 218 because otherwise, the comparator 218 would indicate overcurrent in the OFF state and it would not allow the switch 213 to be turned ON. A second comparator 250 monitors the voltage V₃ at the output of the power FET 212 to determine if the voltage, V₃, out of the power switch 212 rises above the bias voltage V BIAS when the Power FET 212 is ON. If it does, it means that power FET 212 is operating normally and is protected against over current by comparator 218. As previously discussed, V BIAS is selected so that Q1 and Q2 are OFF even when the load current is greater than I LOAD . V BIAS should be chosen so that V s - V BIAS > V s -V₃ under any circumstance if the switch 213 is ON and the load current is smaller or equivalent with the maximum possible current limit value. For example, in the preferred embodiment, V BIAS is two times the current limit value. The second comparator 250 has two input terminals IN21 and IN22 and an output terminal COMPOUT2. The voltage out of COMPOUT2 is V₁₀. IN21 is connected to the Power FET 212 output 204, through the D1 diode (V₁). IN22 is connected to V₄, a voltage slightly above the clamped (minimum) value of V₁. COMPOUT2 is connected to a timer-logic circuit 254 comprising a second flip-flop FF2, a delay element 253, a lock out circuit 256, and an OR gate OR1. V₁ is the voltage on the first input IN21 into the second comparator 250 and V₄ is the voltage on the second input IN22. Reference is now made to Figure 7 concurrently with Figures 8a-8k which illustrate the no short circuit condition. Figure 8a is a diagram illustrating the clock pulses received by FF1, Figure 8b illustrates the load current I LOAD , when the power FET 212 is ON/OFF where the spike 225 is the reverse recovery current and I LOAD PEAK is the peak load current turned OFF. Figure 8c is a diagram illustrating the voltage V₃ out of the power FET 212 where the voltage initially stays negative during the diode reverse recovery time. The voltage then rises to its final level when power FET 212 is ON and decreases rapidly when the FET 212 is shut OFF. Referring to Figure 8d, the power switch 212 is ON when V₁ > V₂. Initially, when the power switch 212 is OFF, V₁ > V₂ and when the switch 212 is ON, V₁ remains greater than V₂ but as the inductor current is increasing during the ON time, the voltage difference between V₁ and V₂ decreases such that when V₂ substantially equals V₁, the power switch 212 is turned OFF and V₁ resumes being greater than V₂. Referring to Figure 8e, V₄ is the clamp voltage which is set higher than the drain source voltage of the power FET 212 at the maximum foreseeable load current (e.g., two times the maximum drain source voltage of FET 212). Referring particularly to Figures 8e - 8k, in the no short circuit condition, when power FET 212 is ON, V₁ > V₄ and the second comparator 250 outputs a logic high into OR1. The Q output from FF1 is also input into OR1. The logic high on output OR1 generated by the second comparator's output COMPOUT2 keeps a logic one on the CLEAR input of FF2, which in turn keeps the Q output of FF2 low. The lock-out circuit 256 is not triggered because it is triggered by a logic 1. The output of the lock-out circuit V₇ is delayed. V7 is input into a second OR gate OR2 along with COMPOUT. COMPOUT is high when V₁ approximately equals V₂ as illustrated in Figure 8i. OR2 outputs a logic high when COMPOUT=1. The OR2 output V₉ is input into the clear of FF1 where Q remains high and Q is a logic low as illustrated in Figure 8k. Q is then input into an inverter which inverts Q or V₅ from a logic low to a logic high. Q or V₅ corresponds to the output Q of FF1. When Q is low, the power FET 212 is ON. After having been inverted by an invertor, Q is input into a delay element 253 having a delay of t delay . The delay time, t delay , is selected to be long enough to accommodate for the reverse recovery time of the worst case diode. In the preferred embodiment, a delay time of 5 - 600 nsec is a selected. In addition, the clamp voltage V S - V₄ is set higher than the drain-source voltage of FET 212 at the maximum foreseeable load-current (e.g., two times the maximum of V DS ). V₆ corresponds to the output of the delay element 253 which is the CLOCK input of FF2. Its positive going transition triggers FF2 t d after the turn ON of the Power FET 212 unless it is cleared through the second comparator 250, as is the case during normal operation as discussed above. Since R DSON of FET 212 is highly temperature dependent, the clamp voltage V₄ selected will be valid over a wide temperature range only if V B has approximately the same temperature coefficient as R DSON , where V B = V S - V BIAS . R DSON has a temperature coefficient of approximately +6800 ppm/°C. V B can achieve approximately the same temperature coefficient T C as R DSON by using a diffused resistor with a T CR of 2000-3000 ppm/°C and a current source (I BIAS ) with a temperature coefficient T CIB = 6800 - T CR . Referring to Figures 8f and 8h, V₁₀ is the voltage signal out of the second comparator 250. When the power switch 212 turns on V₃ goes high, and V₁₀ goes high also. V₁₀ goes high because the comparator 250 senses that V₁ is higher than V₄. Hence, as long as V₁₀ is high, the Q output of FF2 and the output V₇ of the lock out circuit 256 cannot go high. Referring to Figure 8g, V₆ is the voltage out of the delay circuit 253. The delay circuit 253 is triggered when switch 212 is turned on and V₆ is a positive edge when the preset time delay t delay has passed. When the positive edge of V₆ comes, V₁₀ is still high and V₆ cannot set FF2 so the delay cannot initiate turn off of the circuit 400. Thus, as long as V₁ is greater than V₄, the short circuit protection circuitry is not active. Referring to Figures 9a - 9l diagrams corresponding to the short circuit condition for the circuit of Figure 7 are illustrated. If V₃ rises above V₄, then the power switch 212 is operating normally and the current through the FET 212 is limited by the comparator 218. If, due to a short circuit, or an excessive load on the output of the power switch 212, V₃ can not rise above V₄, then the signal out of the delay element 253 triggers the second flip-flop 252, after a preset delay time has elapsed. The second flip-flop 252, in turn, sends a signal to the first flip-flop 222 to clear the flip-flop 222, so that the power switch 212 is turned OFF. When there is a short circuit, the lockout circuit 256 which may be a one shot, keeps the CLEAR input of the first flip-flop FF1 high for a predetermined time in order to ensure that the power switch 212 cannot be turned ON before the predetermined time has elapsed. The lock out circuit 256 disables the power FET 212 when the second comparator 250 turns off the power switch 212 in order to limit the maximum duty cycle in short circuit. The maximum duty-cycle during short circuit is limited to t delay /t lockout and thus the average current of the power switch 212 is limited. As diagrammed in Figure 9b, the load current I LOAD is greater than the current limit level and as shown in Figure 9c, the voltage V₃ out of the power FET 212 is very small in comparison to the load current I LOAD . V₁ remains higher than V₂ because of the clamp circuit 238. (Figure 9d) The clamp voltage V₄ is higher than V₁ (Figure 9e) such that the second comparator 250 output V₁₀ is a logic zero (Figure 9f) and the delay element 253 outputs a delayed clock signal V₆ after the associated delay time (Figure 9g). The positive edge of V₆ sets V₇ (Figure 9h). When V₆ is high, FF2 is triggered and V₇ is set through the lock-out circuit 256 to be positive. V₇ remains positive for a predetermined time: the duration of the lock-out time, t lockout . All further input clock pulses are ignored and, in this way, FFI is disabled. Q V₅ out of FF1 is 1 and FET 212 is shut OFF until the lockout-time has elapsed, since the invertor inverts Q thereby keeping the power FET 212 OFF. In this manner the OFF period is extended to ensure that the duty cycle is short during the short circuit condition. Having thus described the invention, it is recognized that those skilled in the art many make various modifications or additions to the preferred embodiment chosen to illustrate the invention without departing from the scope of the claims.

Claims: A current control circuit for use in a switching regulator circuit of the type which includes a power switching device (212) that is turned off and on to supply current to a load (224) over a periodic, controllable duration of time, wherein the power switching device has an internal resistance when it is conducting current so that there is a determinable and measurable voltage drop across the power switching device for a specified current flow through the power switching device, the control circuit comprising reference means (213) for providing a reference voltage and means (218) for comparing the voltage drop across the power switching device and said reference voltage; and means (209) responsive to the comparing means for turning the power switching device off when a current limit through said power switching device is reached, characterized in that the reference means (213) is coupled to the power switching device (212) to be switched in synchronism therewith and for providing a value of resistance which is proportional to and which tracks changes in the internal resistance of the power switching device; and that means (I CL ) are provided for supplying a reference current to the reference means, wherein the amount of reference current supplied is selected so that there is a voltage drop across the reference means which substantially equals the voltage drop across the power switching device when said current limit level of current is flowing through the power switching device. The circuit of claim 1 wherein the means for comparing has associated therewith an active common mode voltage range and further includes: means (238) for clamping the inputs of the means (218) for comparing when the power switching device is turned off so that the means (218) for comparing operate in the active common mode voltage range and do not signal overcurrent. The circuit of claim 2, wherein the common mode voltage swing on the inputs of the means (218) for comparing, when the power device is off, is limited relative to the voltage drop across the power switching device. The circuit of claim 2 or 3, wherein the means for clamping comprises a transistor (Q2). The circuit of one of the claims 1 to 4, further including: means (250) for monitoring the voltage drop across the power switching device (212) and for switching off the power switching device if the voltage drop across the power switching device is not below a preselected level during a preselected time period. The circuit of one of the claims 2 to 5, further comprising: means (D1, D2) for disconnecting the means (218) for comparing from the power switching device (212) and the reference means (213) when the power switching device is off. The circuit of claim 6, wherein the disconnecting means (D2) further disconnects the reference current from the reference means (213) when the power switching device is off.

Inventors: SZEPESI TAMAS S, SZEPESI, TAMAS S.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1990
Main classification: H02H7
IPC codes: G05F3, H03K17, H02M3