Shielded transistor device

Abstract: The invention comprises a shielded transistor device whose drain is surrounded by a gate comprising an annular ribbon of polysilicon. The gate is connected to a trackable potential that fluctuates but is keyed to a voltage slightly above the average between the positive and negative circuit bias. The shielded transistor device allows the operational amplifier circuit of which it is a part to function at 2extended voltage levels of 12 volts.

Description: The invention relates to transistorized circuitry, and more particularly to transistorized circuits that are workable in a 12 volt range, where the transistors themselves are not ordinarily operative above 5 to 6 volts. In the design of conventional operational amplifier circuitry utilizing CMOS technologies, it has been known that higher operational voltages are desirable. The higher operating voltages provide low output impedance per device size, greater dynamic range and avoidance of early clipping. Higher voltages have been limited in such circuitry due to the low field threshold turn-on voltages of the transistors resulting from field parasitics. Also, higher doping on the drain junctions forces lower break-down from drain-to-source and drain-to-bulk. A bipolar action usually takes place from the higher field around the drains, which limits the operating voltages, and forces narrow design constraints. In many other circuit applications, it is necessary to employ both low supply and high supply sources. To improve the speed of audio processing chips (CODECS), it is desirable to use small transistors (in the sub-micron region) to gain both speed and density. But for the on chip analog-to-digital and digital-to-analog conversion, higher voltage swings are desirable to provide a greater dynamic range, avoid early clippings and, to provide a very clean low impedance mid-level ground. In DMOS devices where threshold voltages are close to 3 volts, a driver with at least 4 times the threshold voltage, i.e., 12 volts, is desired in order to provide low turn-on impedance. Accordingly, higher voltage MOS transistors have been fabricated by surrounding the drain with a high resistance layer of Al polycrystalline silicon (polysilicon). The high resistance layer prevents field concentration near an edge of a gate electrode. Such a teaching is presented in United States Patent Nos. 4,614,959, issued to: Nakagawa on September 30, 1986; and 4,766,474, issued to Nakagawa et al on August 23, 1988. While the aforementioned shielding is effective for its intended purposes, it nevertheless has some drawbacks: a) such devices usually require special doping processes that add to the complexity and cost of manufacture; and b) such shielding, while providing higher operating voltages, usually falls short of operation voltage levels above 10 volts, that are required for high performance circuits. It is known from EP-A-0060989 to provide high voltage tolerant FET circuits by the use of shield structures surrounding source/drain diffusion pockets, the shields being tied to an appropriate potential which in some cases is the associated gate potential. It is also known from The Patent Abstracts of Japan, Vol. 5, No. 55, April 16 1981 and JP-A-56-6539 to provide a bias circuit within a signal level converting circuit in which the bias circuit combines positive and negative power voltages to produce a mean voltage that will not fluctuate as much as the respective power voltages. According to the present invention there is provided an integrated operational transistorized amplifier circuit comprising a plurality of operating stages including a first differential stage followed by a plurality of cascading transistor devices, an output stage, a source of a positive and a negative voltage, wherein each stage has dual transistors operatively biased to a mean bias voltage slightly above an average of said positive and negative voltages, and the circuit further comprises a transistor device shielded from other components of the integrated circuit and connected to the said plurality of operating stages, the shielded transistor device having a drain electrode encircled by a gate electrode, and the gate electrode being connected to the said mean bias voltage thereby protecting the circuit from voltage breakdown associated with voltage swings whereby the voltage difference between said positive and negative voltages is approximately twice the breakdown voltage of the transistor components of the operating stages. The operational voltages (both input and output) of the shielded transistor device can therefore be above the process capability, i.e., above the transistor field thresholds and snap-back limitations. This is accomplished without modifying the ordinary fabricating processes, thus keeping costs in check. In a preferred embodiment of the invention, the gate electrode comprises an annular ribbon of polysilicon. The drain electrode is made small, such that the surface area of the surrounding gate electrode is at least 5 times that of the drain electrode surface area. The circular configuration also provides improved heat dissipation which, in conjunction with the electrical shielding capabilities, increases the operational voltage level of the device. The operating voltage of the transistor device may therefore exceed the 10 volt threshold, and the transistor may operate at a voltage of about 12 volts. A box-like field plate shield surrounding the transistor device provides further electrical isolation, as do channel stops that are disposed between the transistor device and other components. Noise is effectively suppressed in the circuit by placing a capacitor between the mean bias voltage and the transistor gate electrode. In the accompanying drawings, by way of example only: FIGURE 1 is a chip plan view of a transistor device embodying the invention; FIGURE 2 is a schematic diagram of an operational amplifier circuit incorporating the transistor device of FIGURE 1; and FIGURES 2a and 2b are sectional views depicting the masking stages in the CMOS process for fabricating the circuit illustrated in FIGURE 2. Generally speaking, the illustrated transistor device features an operational amplifier circuit constructed with a novel shielded transistor device that provides for operation of the circuit at extended voltage levels generally above those that normally cause breakdown of the transistor. The transistor device has its gate connected to a source of potential that fluctuates and is keyed to a level above the average of the positive and negative circuit bias. Referring to FIGURE 1, a chip plan view of two transistors Q₃ and Q₄ is shown. The aforementioned transistors are also illustrated in greater detail in the circuit diagram of FIGURE 2, described below. Each transistor Q₃ and Q₄ respectively comprises a P⁺ drain electrode that has a reduced surface area of about 20% to 30% of an average sized drain electrode. The P⁺ drain electrode is made circular instead of square, to provide a uniform temperature gradient. This results in improved offset due to heat dissipation and changes of width masking etching on Q₁ and Q₂, which in turn improves the electrical operation of the device 10. The drain electrode 1 is encircled by a gate electrode 2 fabricated from Al polycrystalline silicon (polysilicon). The gate electrode 2 functions as a shield for the drain electrode 1. The gate electrode 2 is fabricated as an annular ribbon of approximately 5 to 7 times the surface area of the drain electrode 1. The contact 5 of the gate electrode 2 is connected to a trackable source of circuit potential that electrically shields the transistor device 10, as will be explained in more detail hereinafter with reference to FIGURE 2. A P⁺ source electrode 3 surrounds the gate electrode 2. A field plate shield 4 of polysilicon surrounds the entire transistor device 10, and is connected to the positive circuit potential, V CC . Referring to FIGURE 2, an operational amplifier circuit 20 is shown in a circuit schematic. This linear operational amplifier is a complex circuit that functions in a range of twice the normal output voltage usually utilized because of component constraints. The operational amplifier 20 has a first differential state using P⁻ channel transistors and two N⁻ channel devices in series that are biased at the middle of the voltage supply. A second state gain utilizes cascading N-channel devices, enclosed drain N⁻ channel current sources, and an output stage for low output impedance drive. The operational amplifier circuit 20 is a twin tub CMOS process consisting of eleven conventional masking steps described with reference to FIGURES 2a and 2b, respectively. Referring to FIGURE 2a, a P⁻ well mask 50 is first put into an N⁻ substrate 51 (step 1). A source drain mask is then applied (step 2) followed by a field implant mask (step 3) and a poly gate mask (step 4), as illustrated in FIGURE 2b. A P⁺ implant mask 52 is next inserted in the N⁻ substrate 51 (step 5), and an N⁺ implant mask 53 (step 6) is then inserted, as shown. A first contact mask (step 7) is fabricated, followed by a first metal mask (step 8). A second contact mask (step 9) is then followed by a second metal mask (step 10). A final scratch protection mask (step 11) completes the fabrication process. The amplifier operates at 12 volts even though the transistors usually degrade at approximately 5 volts and fail at 6 volts. Part of the prior art circuit limitations result from the use of single transistors such that the circuit performance is limited by these characteristics of the transistors. The transistors have low threshold voltage due to parasitic fields and higher doping on the drains junction. A bipolar action results from the higher field around the drains. In order to operate in the 12 volt range, the operational amplifier circuit 20 of this invention uses dual transistors throughout, and shielded transistor device 10 (shown in phantom box) of FIGURE 2, and in the chip plan view of FIGURE 1. The middle point A of the transistor device 10 is connected to a trackable source of potential shown in the circuit 30 (phantom box). The trackable potential fluctuates, but is always keyed or fixed to a value equivalent to a potential slightly above the average of the positive, V CC bias and the negative, V BB- bias. Circuit 30 features P⁻ well resistors R₁ and R₂, respectively, and two transistors Q N and Q M . The Q N and Q M transistors are used in the potential source circuit 30 to provide balance to the circuit 20 that features dual transistors throughout, and whose transistors are tied to the potential at point A. The transistor device 10 utilizing the enclosed drains 1 and the trackable gate voltage of point A shield the rest of the circuit from the breakdown usually associated with voltage swings or during slewing. Point B of circuit 30 would be a true average of the positive and negative bias; usually about 1 volt, for example: V B = 7 volts - 5 volts 2 The voltage at point A is approximately 2 volts (more exactly, V B + V Threshold(Qn) ; a better operating voltage. The total supply voltage output at point "t" is approximately 12 volts, and point "B" swings from V CC -1 volt to V BB (total voltage of approximately 11 volts). A grounded capacitor C X provides suppression of noise and ripple in circuit 20.

Claims: An integrated operational transistorized amplifier circuit comprising a plurality of operating stages including a first differential stage followed by a plurality of cascading transistor devices (Q11-Q19), an output stage, a source of a positive and a negative voltage (V CC , V BB ), wherein each stage has dual transistors operatively biased to a mean bias voltage slightly above an average of said positive and negative voltages (V CC , V BB) , and the circuit further comprises a transistor device (10) shielded from other components of the integrated circuit and connected to the said plurality of operating stages, the shielded transistor device (10) having a drain electrode (1) encircled by a gate electrode (2), and the gate electrode (2) being connected to the said mean bias voltage thereby protecting the circuit from voltage breakdown associated with voltage swings whereby the voltage difference between said positive and negative voltages (V CC , V BB ) is approximately twice the breakdown voltage of the transistor components of the operating stages. An amplifier circuit according to claim 1, wherein said shielded transistor device (10) functions at levels of operation generally in excess of 10 volts. An amplifier circuit according to claim 1 or claim 2, further comprising a field plate shield (4) disposed about said shielded transistor device (10). An amplifier circuit according to claim 3, wherein said field plate shield (4) comprises a box-shaped ribbon of polysilicon. An amplifier circuit according to any one of the claims 1-4 wherein the gate electrode (2) encircling the drain electrode (1) comprises an annular ribbon of polysilicon. An amplifier circuit according to any one of the claims 1-5 wherein said shielded transistor device (10) is shielded from other components in said circuit by a channel stop. An amplifier circuit according to any one of the preceding claims wherein the surface area of said gate electrode (2) is in excess of five times the surface area of said drain electrode (1). An amplifier circuit according to any one of the preceding claims further comprising a capacitor element (6) disposed between said mean bias voltage and said gate electrode (2) for reducing noise.

Inventors: MOYAL MIKI, MOYAL, MIKI
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, H03K17, H03F3, H01L27, H01L21