Ground velocity sensor with drop-out detection

Abstract: A transmitter (28) emits a signal at a frequency (ft) derived from an oscillator (222). The reflected signal (fr) is received by a receiver (30) and applied to count down a first counter (244). A second counter (246) simultaneously counts down a reference frequency (fc) derived from the oscillator (222). When the first counter (244) reaches zero the contents of the second counter (246) represent Doppler velocity. A dropout detector (238) detects when the received signal level falls below a threshold value and sets a flip-flop (242) which stays set until the dropout ends. While the flip-flop (242) is set it prevents both counters (244, 246) counting.

Description: This invention relates to a sensor for sensing the relative velocity between one object moving relative to another, such as the ground velocity of a vehicle, such as an agricultural vehicle. On most agricultural and off-highway equipment in use today, vehicle speed or velocity is sensed by a magnetic pickup which senses the wheel speed. However, there are problems with this measurement technique. To solve these problems, Doppler-type ground speed sensing systems have been proposed. The velocity, Vg, can be determined from the frequency shift between the received and transmitted signals, Δf, by a modified Doppler equation: (1) Vg = (c Δf) ÷ (ft 2 COS α) where α is the angle of the signal transmission axis from horizontal, where c is the speed of sound, and where ft is the transmitted signal frequency. It is known to process Doppler signals by means of various pulse counting arrangements, e.g. US-A 3 893 076 and GB-A 2 101 831. In such systems, the magnitude of the received signal can fluctuate considerably in amplitude due to variations in the reflectivity of the ground and due to momentary destructive interference among wave fronts from the various reflecting areas of the ground. Large fluctuations in the receive signal magnitude can cause periods of "drop-out" during which the received frequency is not detectable because the received signal magnitude is too low. These periods of signal drop-out can cause such systems to produce an erroneous or biased velocity output signal. US-A 3,893,076 discloses a digital speed sensing system wherein counters contain numbers which represent the time intervals corresponding to successive groups of 5 cycles of a mixed Doppler frequency. These numbers are indicative of the sensed speed. Signal drop-out compensation is provided by a subtractor, comparator and logic circuit coupled between the counters and the system output. If the difference between the numbers in the two counters is large enough, such as when signal drop-out occurs, then the subtractor and comparator operate via logic gates to prevent updating of a register into which one of the numbers is otherwise placed. Such a system has a drawback in that, because the drop-out detection circuit is "downstream" of the counters, it is possible that two consecutive intervals could be the same, even though both intervals contain signal drop-outs. If this occurs, then the register would be updated with a misleading number which would not truly represent the actual speed. Furthermore, such a system is complex and would be expensive to produce. The object of the present invention is to provide a speed sensing system with a simple and reliable system for compensating for fluctuations in the amplitude of the reflected or received signal. The system according to the invention is defined in claim 1 below. The preferred embodiment of the present invention includes a master clock from which all time is derived, a transmit amplifier and transducer, a receive amplifier and transducer, a digital frequency detector and a signal dropout sense and hold circuit. The master clock is divided down to the transmit frequency (40 kHz is preferred) to drive the transmit amplifier and transducer. The received echo is amplified, squared, and sent to the frequency detector, where the difference between its period and that of the transmit signal is measured. This difference is proportional to speed. The frequency detector contains two down counters. One is driven by the received signal, the other is driven by a reference signal whose frequency is derived from the master clock. The receive counter initializes and turns on and off the second counter. During each measurerment interval, the second counter measures the number of reference clock cycles that occur during a particular number (1280) of receive cycles. Since the transmit frequency is also derived from the master clock, each count of the clock counter represents a feed fraction of a transmit cycle. Therefore, the final count represents the difference between the transmit and receive periods in-terms-of-the-transmit-period , not in terms of an independent reference. This makes the detector output insensitive to drift in the master clock frequency or to changes in the characteristics of circuit components. At the end of each measurement interval, the final count is latched for output and the counting process begins again. The drop-out detector monitors the amplitude of the received signal. Drop-out is considered to occur when this amplitude drops below the minimum level for which true Doppler shift can reliably be detected. When the drop-out condition occurs the two counters are inhibited and the frequency detector waits until the drop-out condition ceases. At this time, counting resumes. The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a simplified schematic drawing of a speed sensing system, Fig. 2 is a schematic block diagram of a preferred embodiment of a signal processing unit, according to the present invention, and Figs. 3 to 9 are detailed circuit diagrams of various portions of Fig. 2. The ground speed sensing system 10 includes a continuous ultrasonic transmitter and receiver unit 12 for mounting on a vehicle lower frame member 14. The unit 12 has transmit and receive horns 16 and 18, preferably aimed in a forward direction at an angle α of approximately 37 degrees from horizontal. A signal processing unit 220 provides an ultrasonic transmit signal T to the unit 14 and receives a signal from the unit 14. The horns can be conventional ultrasonic horns. The horns 16 and 18 are coupled to a corresponding conventional ultrasonic transmitter 28 and receiver 30 (Fig. 2). The transmitter 28 preferably transmits continuously at a transmit frequency ft of 40 kHz. The output of the receiver 30 will be a reflected signal R with frequency fr. Cross talk between the transmitter and receiver is preferably eliminated by using cork to acoustically isolate the horns 16 and 18 from each other or by suspending the horns via known rubber "shock mounts" by placing a sonic baffle or partition between the horns and by using cork to acoustically enclose portions of the horns from which ultrasonic energy could otherwise escape. If the horns 16 and 18 are aimed towards the ground in the forward direction with respect to vehicle motion, then the reflected signal, R, will have a reflected frequency, fr, which will be higher than ft if the vehicle and system 10 are moving forward. Conversely, fr will be lower than ft if the vehicle and system 10 are moving in reverse. As best seen in Fig. 2, the signal processing circuit 220 includes an oscillator 222 with a 4 MHz master clock frequency which is applied to a frequency divider unit 224. Unit 224 provides a 40 kHz transmit frequency signal, a 500 kHz clock frequency, fc, and a calibrate frequency, fcal, of 40816 Hz. The 40 kHz signal is transmitted via power amplifier 226 to transducer 28 and transmit horn 16, which generates the 40 kHz ultrasonic transmit signal. The reflected ultrasonic signal is received by horn 18 and receiver transducer 30 which generates the reflected signal R with frequency fr. The signal R is amplified by preamp 232 and by receiver amplifier 234 and is then applied to inputs of squaring circuit 236 and of drop-out detect circuit 238. The output of drop-out detect circuit 238 is normally low, but goes high when the peak amplitude of the output of amp 234 stays below a threshold of 2.0 volts, for example. A switch 240 receives the transmit frequency ft and the calibrate frequency fcal from 224 and receives the reflected frequency fr from 236. Switch 240 couples a selected one of these frequencies to the C input of a synchronizing flip-flop 242 and to the C input of receive down counter 244 via 1 microsecond delay 248. An inhibit of disable drop-out output of switch 240 is coupled to the drop-out detector 238. The D or data input of D-type flip-flop 242 is coupled to the output of drop-out detect circuit 238, the set S input is coupled to the "0 out" terminal of receive down counter 244, and the Q output is coupled to the inhibit, Inh, inputs of receive down counter 244 and of clock down counter 246. The receive down counter 244 also has its clock input coupled to the output of switch 240 via 1 microsecond delay 248. A 12-bit binary word (equal to decimal 1280, for example,) is applied to the preset data pins of down counter 244. The "0-out" terminal of down counter 244 is also coupled via 1 microsecond delay 250 to the +T input of monostable multivibrator or one-shot 252. The inverted Q output of "latch" one-shot 252 is coupled to the inverted read input of latch 254 and to the +T input of monostable multivibrator or one-shot 256. The Q output of "preset" one-shot 256 is coupled to the preset control inputs of clock and receive down counters 246 and 244 via OR gate 257. OR gate 257 also is coupled to a resistor and capacitor circuit 259. Circuit 259 and OR gate 257 operate to reset counters 244 and 246 when the system power (from which +15 volts is derived) is turned on. The clock input C of down counter 246 receives the 500 kHz frequency fc from frequency divider unit 224. The 12 least significant bits of a binary word (equal to 16000 +512 or binary 100 0000 1000 0000) are applied to the preset data pins of clock down counter 246. The number 16000 is equal to the number of the cycles of the clock frequency fc which will occur in the time taken up by 1280 cycles of the transmit frequency ft...(500,000 ÷ 40,000) x 1280. The contents of the down counter 246 is communicated to latch 254 via a 10 bit data bus. The latch 254 is coupled via a 10 bit data bus to a digital to analog converter 258 and to output amplifer 260. An offset level may be applied via summer 262 and the scaling amplifier provides the output voltage Vo. The clock down counter preset offset of 512 is chosen so that the full range of forward and reverse speeds of the vehicle can be represented by positive clock down counter values. This is necessary if the D/A converter 258 treats all digital numbers from latch 254 as positive. However, if a D/A converter with negative number capability is used, then no offset is needed. In this latter case, the resulting final clock down counter numbers would be positive for forward speeds, zero for zero speeds and negative for reverse speeds. Mode of Operation of Preferred Embodiment During normal operation, the switch 240 selects the fr frequency from squaring amp 236. Down counters 244 and 246 are simultaneously preset to predetermined numbers upon generation of a preset pulse by preset one-shot 256. Receive down counter is preset to 1280 (binary 10100000000). Clock down counter is preset to the 12 least significant bits of 16512 which is binary 000 1000 0000. Then, assuming no signal drop-out condition is detected by drop-out detector 238, the receive down counter 244 counts down at a rate equal to the frequency fr of the reflected signal, which frequency is applied to the clock input C of receive down counter. By rewriting the Doppler equation, (1), it follows that the frequency shift ΔF = fr - ft is approximately 82.87 Hz per mile per hour of ground speed Vg: (2) Δf = (Vg x ft x 2 cos α ) ÷ c Thus, it follows that receive down counter 244 will generally count down from 1280 to 0 in around approximately 30.727 miliseconds for a forward ground speed of 20 mph, in 32 miliseconds for a ground speed of 0.0 mph, and in approximately 32.335 miliseconds for a rearward ground speed of 5 mph. Thus, receive down counter 244 establishes a variable time interval equal to the time occupied by a predetermined number of cycles of the reflected frequency fr. At the same time, the 500 kHz square wave clock frequency fc from frequency divider 224 is applied to the clock input c of clock down counter 246 so that it counts down from its preset value at a 500 kHz rate. The counters 244 and 246 continue counting down at their respective rates until receive down counter 244 reaches 0, at which point its 0-out output generates a low-to-high transition (0 - 1). This 0 - 1 transition is applied to the set S input of flip-flop 242 so that the normally low Q output of flip-flop 242 and the INH inputs of both down counters 244 and 246 go high, thus inhibiting further down counting by both down counters 244 and 246. After a 1 microsecond delay due to delay 250, the 0 - 1 transition of the 0-out of 244 also causes latch one-shot 252 to generate a negative 1 microsecond pulse. The positive going (or trailing) edge of this pulse causes latch 254 to read the contents of clock down counter 246. To a very close approximation, the final number N in the clock down counter 246 will be defined by the equation: (3) N = ((Δf x Nc x Nd) ÷ (ft x Nt)) + 512 where Δf is equal to fr - ft, Nc is the number of receive cycles over which the receive period is measured (1280), Nd is the ratio of the master clock frequency (4 MHz) to the transmit frequency ft (40 KHz) and Nt is the ratio of master clock frequency to the clock counter input frequency (500 kHz). For example, for ground speeds of forward, 20 mph, O mph and reverse 5 mph, the latch 254 will contain values of approximately 1173, 512 and 345, respectively. Thus, the contents of latch 254 is linearly related to ground velocity. This can also be shown by substituting equation (2) for Δf in equation (3) to obtain the following equation: (4) N = ((Vg x 2 cos α x Nc x Nd) ÷ (Nt x c)) + 512. Thus, it can be seen that the final count number N is dependent only on the physical quantities Vg and α and on the digital quantities Nc, Nd, and Nt. It is insensitive to drift in the 4 MHz master clock frequency since this frequency is cancelled out in the derivation of equation 4. Now, the negative pulse from latch one-shot 252 also causes preset one-shot 256 to generate a positive 1 microsecond pulse which presets both counters 244 and 246 and returns the 0-out output of down counter 244 back to its initial low state. Then, the next rising edge of the pulse train from switch 240 resets Q of flip-flop 242 and the Inh inputs of counters 244 and 246 back to their initial low states so that counters 244 and 246 can start down counting again. The D/A converter 258 converts the contents of latch 254 into an analog voltage so that, for example, a 1 count change in the latch contents corresponds to voltage change of 9.77 milivolts at the output of D/A converter 258. The output of D/A converter 25b is amplified by amplifier 260. Then, offset and scale factors may be applied via summer 262 and variable amp 264 to obtain an output voltage Vo which is proportional to the latch contents N, and thus, to the ground speed Vg. Now, when the amplitude of the reflected signal R is at normal levels, then the output of drop-out detector 238 is low and the system operates as just described. However, the reflected signal amplitude may "drop out" due to variations in terrain reflectivity or due to destructive interference among wave fronts from the various reflecting areas of the terrain. This signal drop-out condition can cause a speed sensing system to produce erroneous ground speed values. In this preferred embodiment of the present invention, the output of the drop-out detect circuit 238 and the D input of flip-flop 242 go high when this drop-out condition occurs. Then, on the next rising edge of the pulse train from switch 240, the Q output of flip-flop 242 goes high, thus inhibiting both down counters 244 and 246, as long as the drop-out condition exists. When the drop-out condition ends, the output of drop-out detect circuit 238 and the D input of flip-flop 242 go back low. Then, on the next low to high transition of the pulse train from 240, the Q out of flip-flop 242 goes back low and down counters 244 and 246 resume counting. In this manner, the drop-out condition does not degrade the velocity information. A testing capability is provided for this system by the addition of switch 240. In the normal operating position (shown), switch 240 connects the output of squaring circuit 236 to receive down counter 244 so that the system operates as described previously. If switch 240 is in the "zero" position, then the 40 kHz transmit frequency is coupled to receive down counter 244 so that if the system is operating properly, the contents of latch 54 will indicate a zero ground speed. If switch 240 is in its "CAL" position, then a calibrate frequency fcal of 40.816 kHz is coupled to receive down counter 244 so that the contents of latch 254 should indicate a predetermined forward ground speed. When switch 240 is in the "zero" or "calibrate" positions, it causes drop-out detector 238 to remain in its low output state so that a drop-out condition does not interfere with the test function. It should be understood that this invention could be used to sense velocities other than vehicle ground speed. For example, if the horns 16 and 18 were aimed at a rotating tire, a measure of tire rotation speed could be obtained. Similarly, if the horns were aimed at any object moving with respect to the horns, such as a straw mat moving through a combine, then this invention would sense the velocity of that moving object. The following are tables of the recommended values for the components shown in the preferred embodiment of Figs. 3 - 9. Table A corresponds to Figs. 3, 4 and 6 - 8. Table B corresponds to Fig. 9 and elements 234 and 236 of Fig. 5. Table C corresponds to elements 230 and 232 of Fig. 5.

Claims: A Doppler velocity sensor wherein pulses at a received frequency (fr) derived by a receiver (30) from a signal reflected from a relatively moving target to which is transmitted a signal at a fixed, transmitted frequency (ft), with a counter (244) for counting the received pulses, characterized in that: (a) the counter (244) counts a fixed number of the received pulses (fr) (b) a second counter (246) simultaneously counts pulses at a reference frequency (fc) and contains a value representative of relative velocity when the first counter (244) has counted the fixed number of received pulses, (c) a drop-out detector (238) senses when the level of the signal received by the receiver (30) falls below a predetermined value and then provides a dropout signal (D/O), (d) a control device (242) suspends counting by both counters during the existence of the dropout signal (D/O), in which the control device comprises a flip-flop (242) with a clock input receiving the received pulses (fr), a data input (D) receiving the dropout signal (D/O), and an output (Q) connected to inhibit inputs (Inh) of both counters (244, 246), the flip-flop clocking to a state in which the counters are inhibited in the presence of the dropout signal (D/O) on the data input (D), in which the flip-flop (242) has a set input (S) connected to a zero output (O) of the first counter so as to be set to the said state when the first counter (244) has counted down to zero, in which the sensor further comprises a first monostable multivibrator (252) having an input coupled to the zero output terminal (0) of the first counter (244) and having an output coupled to the input of a second monostable multivibrator (256) which has an output connected to reset terminals (PE) of the first and second counters (244, 246) so as to reset these to first and second initial values respectively, the sensor further comprising an OR gate (257) with a first input coupled to the output of the second monostable multivibrator (256), an output coupled to the reset terminals (PE) of the first and second counters (244, 246), and a second input coupled to ground through a resistor (R24) and coupled to a switched terminal which is energized when system power is turned on through a capacitor (C21), so that when the switched terminal is energized, a momentary signal is transmitted through the capacitor (C21) and OR gate (257) to the reset terminals (PE), thereby to reset the first and second counters (244, 246) to their initial values. A Doppler velocity sensor according to Claim 1, characterized by a latch (254) with data inputs coupled to receive the contents of the second counter (246) and with a read input coupled to the output of the first monostable multivibrator (252) so that firing of the first monostable multivibrator causes the latch (254) to read and store therein the contents of the second counter (246).

Inventors: FERGUSON LARRY WAYNE, PENFOLD GARN FARLEY, PHELAN JAMES JOSEPH, FERGUSON, LARRY WAYNE, PENFOLD, GARN FARLEY, PHELAN, JAMES JOSEPH
Applicants: DEERE & CO, DEERE & COMPANY
Application year: 1990
Main classification: G01S15
IPC codes: G01S15