Method of manufacturing a non-volatile semiconductor memory device

Abstract: The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device which comprises a field-effect transistor in which a control gate (CG) is stacked on a floating gate (FG) through an insulating film (25). This method comprises the steps of forming said floating gate (FG) made of a semiconductor layer and said control gate (CG) made of a layer containing a refractory metal stacked on said floating gate (FG); covering said floating gate (FG) and said control gate (CG) by a film (29; 30) which prevents a diffusion of metal atoms and transmits oxygen; and forming a semiconductor oxide film (25) on side walls of at least said floating gate (FG) by executing a thermal oxidation.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device. Description of Related Art Hitherto, as one kind of nonvolatile semiconductor memory device, an ultraviolet erasable EPROM (Erasable and Programmable Read Only Memory) has been known which has a capacity that is gradually becoming greater. However, when the capacity of an EPROH increases, defective bits can occur due to problems of manufacturing which, results in the deterioration in the yield of EPROMs. Therefore, for EPROMs which have a large capacity, generally, redundant bits so as to compensate for defective bits and a redundant bit programming circuit so as to select the redundant bits are provided in the memory device, and the defective bits are replaced by redundant bits to compensate for the defective bits. In this case, the redundant bit programming circuit is ordinarily constructed with EPROM memory transistors. However, when data in the EPROM itself is erased, ultraviolet rays are also irradiated onto the redundant bit programming circuit. Therefore, to prevent the data written in the redundant bit programming circuit from being erased by the irradiation of the ultraviolet rays, it is necessary to take countermeasures so as not to irradiate the ultraviolet rays onto the EPROM memory transistors of the redundant bit programming circuit. Hitherto, as a countermeasure for such purpose, in general, the upper portion of the EPROM memory transistors for the redundant bit programming circuit has been covered by a first layer of aluminum (A1) film which form wirings so as to thereby shield the upper portion from light. However, even when the EPROM memory transistors for the redundant bit programming circuit are shielded from light by a first layer of Al film as mentioned above, the following problems still exist. First, since the space between the first layer of Al film and a semiconductor substrate is fairly large, the ultraviolet rays which entered from the portions which are not shielded from the light by the Al film cause a multiple reflection between the surface of the semiconductor substrate and the lower surface of the Al film, so that the ultraviolet rays easily enter the EPROM memory transistors under the Al film. Second, it is necessary to form Al wirings for the source region, drain region, and control gate, and since it is necessary to maintain certain distances between the Al wirings, when the ultraviolet rays are irradiated, the ultraviolet rays enter from the regions between the Al wirings. To prevent this, it is necessary to change the shapes of the source region, drain region, and control gate, so that the area for the EPROM memory transistors for the redundant bit programming circuit becomes large. Moreover, in spite of such a large area structure, it is difficult to sufficiently suppress the irradiation of the ultraviolet rays to the EPROM memory transistors for the redundant bit programming circuit. On the other hand, as disclosed in JP-A-2-79477, which is not part of the prior art, the applicant of the present invention has proposed a nonvolatile semiconductor memory device and a manufacturing method in which a phospho-silicate glass (PSG) film containing phosphorus of 1 to 8 weight %, a silicon nitride (Si 3 N 4 ) film, and an arseno-silicate glass (AsSG) film or a boro-phospho-silicate glass (BPSG) film are sequentially formed on a floating gate, and by using such a structure, the data retention characteristics of an EPROM or an EEPROM (Electrically Erasable and Programmable Read Only Memory) can be improved. As mentioned above, by using the three layer structure comprising PSG/Si 3 N 4 /AsSG or PSG/Si 3 N 4 /BPSG as the interlayer insulating film, the data retention characteristics can be improved. However, when the integration density increases and contact holes become small, the following problems result. These problems will be described in detail hereinbelow with reference to FIGS. 1A and 1B. FIGS. 1A and 1B show a conventional manufacturing method of an EPROM. As shown in FIG. 1A, according to the conventional manufacturing method of an EPROM, a field insulating film 102, a gate insulating film 103, a floating gate FG", a control gate CG", insulating films 104 and 105, and a source region 106 and a drain region 107 of, for instance, an N - -type are formed on a p-type silicon (Si) substrate 101, for example. Then a PSG film 108, an Si 3 N 4 film 109, and an AsSG film 110 are formed as interlayer insulating films on the whole surface. As already mentioned above, a BPSG film can be also used in place of the AsSG film 110. Then, a resist pattern (not shown) in which portions corresponding to contact holes to be formed is formed on the AsSG film 110. Then the AsSG film 110, Si 3 N 4 film 109, PSG film 108, and gate insulating film 103 are sequentially etched by using the resist pattern as mask. Thus, as shown in FIG. 1B, contact holes C 1 ' and C 2 ' are formed. Then the resist pattern is removed. A reflow of the AsSG film 110 is then executed by performing a thermal treatment. Thus, the shoulder portions of the contact holes C 1 ' and C 2 ' are set into a smooth round shape as shown by alternate long and short dash lines in FIG. 1B. Then, an Al film and An Al-Si alloy film to form wirings are formed by a sputtering method or an evaporation method. Prior to this as a pre-processing, light etching is first executed by using an etchant of the hydrofluoroic acid (HF) system. Then, after the Al film or Al-Si alloy film has been formed, this film is patterned into a predetermined shape by etching, thereby forming wirings (not shown) which respectively come into contact with the source region 106 and drain region 107 through the contact holes C 1 ' and C 2 '. However, during the above described light etching, the PSG film 108 which is exposed on the inside of the contact holes C 1 ' and C 2 ' is also etched into a shape as shown by broken lines in FIG. 1B. Thus, there is a problem such that the shapes of the contact holes C 1 ' and C 2 ' after completion of the light etching deteriorate and there is the danger that the shape deterioration results in a cause of a defective contact or the like. On the other hand, in the EPROM and EEPROM, hitherto both the floating gate and the control gate are formed with an N - -type polycrystalline Si film. In recent years, in accordance with the requirements for realization of large capacity and high speed of the EPROM and EEPROM, as the material of the control gate, it has been necessary to use a low resistivity material such as polycide film in which a silicide film of a refractory metal such as tungsten silicide (WSi 2 ) film or molybdenum silicide (MoSi 2 ) film is formed on an N - -type polycrystalline Si film or refractory metal film. When a thermal oxide film of good quality is formed on the side walls around the floating gate, good data retention characteristics are obtained. However, for this purpose, it is desired to execute the thermal oxidation at a temperature of 1000°C or higher. In e.g. the EPROM or the EEPROM having a high integration density, there is generally used a so-called double self-alignment method in which a floating gate and a control gate are formed by simultaneously patterning using one mask. According to the double self-alignment method, the side surfaces of the floating gate in the direction of channel length (direction connecting a source region and a drain region) of a memory transistor are formed so as to be self-aligned with the control gate. Therefore, in the case where the control gate was formed by, for instance, a polycide film, upon thermal oxidation to form an oxide film on the side walls of the floating gate, a refractory metal silicide film such as a WSi 2 film is exposed. However, in this state, if the thermal oxidation of a high temperature of, e.g., 1000°C or higher is executed, there is a large possibility such that refractory metal atoms such as tungsten (W) cause an out-diffusion from the refractory metal silicide film. The refractory metal atoms which caused the out-diffusion are taken into an Si substrate, a thermal oxide film is formed around the floating gate, a thermal oxide film is formed on e.g. the Si substrate, so that a trap level or the like is formed. Such refractory metal atoms easily become a cause of leakage for a cause of breakdown of the oxide film. For the improvement of the data retention characteristics, the present applicant has proposed in Japanese Patent Laid-Open PUblication No. Hei 2-31466 a method whereby by executing a thermal oxidation in a state in which a control gate and a floating gate are covered by a semiconductor layer such as a polycrystalline Si film or the like, a semiconductor oxide film of good film quality is formed on the side walls of the floating gate. US-A- 4613956 and EP-A-0298430 both disclose methods of manufacturing comprising the features of the preamble of appended claim 1. OBJECTS AND SUMMARY OF THE INVENTION It is an object of the invention to provide a method of manufacturing a nonvolatile semiconductor memory device by which a nonvolatile semiconductor memory device of good data retention characteristics can be manufactured without causing an out-diffusion of metal atoms included in the control gate upon thermal oxidation to form a semiconductor oxide film on side walls of the floating gate. To solve this object the present invention provides a method as specified in claim 1. Preferred embodiments of the invention are apparent from the subclaims. For the film which prevents the diffusion of metal atoms and transmits oxygen, for instance, it is possible to use an SiO 2 film, a PSG film, an AsSG film, a BPSG film, or the like. For the semiconductor layer constructing the floating gate, for instance, a polycrystalline Si film can be used. The above, and other, objects, features and advantages of the present invention will become readily apparent from the following detailed description thereof which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are cross sectional views for explaining a conventional manufacturing method of an EPROM; Figs. 2A to 2F are cross-sectional views for explaining a method of manufacturing an EPROM according to an embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the invention will be described hereinbelow with reference to the drawings. FIGS. 2A to 2F show a manufacturing method of an EPROM according to an second embodiment of the invention. In the embodiment, as shown in FIG. 2A, a gate insulating film 42 such as an SiO 2 film, a polycrystalline Si film 43 of, for instance, an n + -type to form a floating gate, an insulating film 44 such as an SiO 2 film, and a polycide film 45 to form a control gate are formed on, for instance, a p-type Si substrate 41 in which a field insulating film (not shown) is formed and the isolation between devices has previously been executed. A resist pattern 46 of a predetermined shape is formed on the polycide film 45 by lithography. The polycide film 45 comprises: for instance, an n - -type polycrystalline Si film 45a in which impurities such as P are doped; and a refractory metal silicide film 45b such as a WSi 2 film or a MoSi, film formed on the film 45a. In the state shown in FIG. 2A, it is assuned that the polycrystalline Si film 43 to form the floating gate has already been patterned with respect to the direction perpendicular to the cross section shown in FIG. 2A. Then, in accordance with the double self-aligned method, the polycide film 45, the insulating film 44, and the polycrystalline Si film 43 are anisotropically etched in the direction perpendicular to the surface of the substrate by, for instance, the RIE method by using the resist pattern 46 as a mask. Thus, as shown in FIG. 2B, a floating gate FG and a control gate CG are formed in a self-aligned manner. Then, as shown in FIG. 2C, by using the resist pattern 46 as a mask, n-type impurities such as P are ion implanted into the p-type Si substrate 41 at a low concentration. Thus, for example, n-type semiconductor regions 47 and 48 of low impurity concentrations are formed in a self-aligned manner with respect to the floating gate FG and control gate CG. As shown in Fig. 2D, for instance, an SiO 2 film 49 is then formed on the whole surface by, e. g., the CVD method as a cap layer which prevents the diffusion of metal atoms and transmits oxygen (O 2 ). The floating gate FG and control gate CG are completely covered by the SiO 2 film 49. For example, by using an atmospheric pressure CVD method, the SiO 2 film 49 can be formed at a low temperature of, for instance, about 400 °C. A thermal oxidation at a high temperature of, for instance, about 1000 °C or higher is executed in a state in which the floating gate FG and control gate CG are covered by the SiO 2 film 49 as mentioned above. Thus, as shown in Fig. 2E, an SiO 2 film 50 is formed by the thermal oxidation method on the sidewalls of the floating gate FG and the control gate CG which are in contact with the SiO 2 film 49. A thickness of SiO 2 film 50 is set to, e. g., about 5 to 10 nm (50 to 100 Å). Upon such a thermal oxidation, since the side surface of the control gate CG made of a polycide film is covered by the SiO 2 film 49, it is prevented that refractory metal atoms such as W are diffused out from the refractory metal sill-cide film 45b which forms the control gate CG upon thermal oxidation. The SiO 2 film 50 is also formed on the surface of the p-type Si substrate 41 in the portions on both sides of the floating gate FG by the thermal oxidation. Then, by anisotropically etching the SiO 2 film 49 in the direction perpendicular to the substrate surface by, e. g., the RIE method, as shown in Fig. 2F, a side-wall spacer 51 made of SiO 2 is formed. Subsequently, by using the sidewall spacer 51 as a mask, n-type impurities such as arsenic As are ion-implanted into the p-type Si substrate 41 at a high concentration. Thus, a source region 52 and a drain region 53 of, for example, the n + -type having n-type low impurity concentration portions 52a and 53a are formed into the p-type Si substrate 41 in the lower portion of the side wall spacer 51 in a self-aligned manner with respect to the floating gate FG and the control gate CG. Here, the low impurity concentration portions 52a and 53a are formed by parts of the semiconductor regions 47 and 48 of the low impurity concentrations which have already been formed. A memory transistor comprising the floating gate FG, control gate CG, source region 52, and drain region 53 has an LDD structure in which the electric field near the drain region 53 is reduced by the low impurity concentration portion 53a. According to the embodiment, by executing a thermal oxidation in a state in which the control gate CG made of the polycide film 45 and the floating gate FG are covered by the SiO 2 film 49, the SiO 2 film 50 is formed on the side walls of the floating gate FG and the control gate CG. Therefore, the out-diffusion of the refractory metal atoms from the refractory metal silicide film 45b constructing the control gate CG upon thermal oxidation can be prevented. Due to this, it is possible to solve the problems such as formation of the trap level which is caused because the out-diffused refractory metal atoms are taken into the p-type Si substrate 41, SiO 2 film 50 formed around the floating gate FG, gate insulating film 42, etc. and a breakdown of the SiO 2 film 50, gate insulating film 42, and the like. On the other hand, since the out-diffusion of the refractory metal atoms can be prevented as mentioned above, the thermal oxidation can be executed at a higher temperature. Moreover, since the thermal oxidation is performed through the SiO 2 film 49, the thermal oxidation is stably performed at a relatively slow speed. Thus, the SiO 2 film 50 of good film quality can be formed on the side walls of the floating gate FG, so that an EPROM of good data retention characteristics can be manufactured. In the embodiment, a refractory metal film can be also used as a material to form the control gate CG. On the other hand, although the embodiment has been described above with respect to the case where the memory transistor has an LDD structure, the memory transistor does not always need to have the LDD structure. Having described specific preferred embodiments of the present invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to these precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the invention as defined in the appended claims. For instance, although the above embodiments have been described with respect to the case where the invention was applied to an EPROM, the invention can be applied to an EEPROM and other various kinds of floating gate memory devices. According to the invention, since the thermal oxidation is executes in a state in which the floating gate and the control gate were covered by the film which prevents the diffusion of the metal atoms and transmits oxygen, upon thermal oxidation to form the semiconductor oxide film on the side walls of the floating gate, the out-diffusion of the metal atoms contained in the control gate does not occur, and a nonvolatile semiconductor memory device of good data retention characteristics can be manufactured.

Claims: A method of manufacturing a non-volatile semiconductor memory device which comprises a field-effect transistor in which a control gate (CG) is stacked on a floating gate (FG) through an insulating film (44), comprising the steps of: forming said floating gate (FG) made of a semiconductor layer and said control gate (CG) made of a layer containing a refractory metal stacked on said floating gate (FG); covering said floating gate (FG) and said control gate (CG) by a film (49) which prevents a diffusion of metal atoms and transmits oxygen; and forming an oxide film (50) on sidewalls of said floating gate (FG) and said control gate (CG) by executing a thermal oxidation, characterized in that said oxide film (50) is formed by a thermal oxidation after and beneath said film (49) which prevents a diffusion of metal atoms and transmits oxygen, said film (49) which prevents a diffusion of metal atoms and transmits oxygen is formed at low temperature while said oxide film (50) is formed by a thermal oxidation at high temperature. A method of manufacturing a non-volatile semiconductor memory device according to claim 1, wherein said layer containing a refractory metal is a polycide film (45) or a refractory metal film. A method of manufacturing a non-volatile semiconductor memory device according to claim 1 or 2, wherein said film (49) which prevents a diffusion of metal atoms and transmits oxygen is a silicon dioxide film, a phospho-silicate glass film, an arseno-silicate glass film, or a boro-phospho-silicate glass film. A method of manufacturing a non-volatile semiconductor memory device according to any of claims 1 to 3, wherein said oxide film (50) is a silicon dioxide film formed by a thermal oxidation.

Inventors: NAKAMURA AKIHIRO, NODA MASANORI, NAKAMURA, AKIHIRO, NODA, MASANORI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L27