Clipping circuit

Abstract: The clipping circuit has a voltage reference (3) and a transconductance (5) connected to a voltage input (Vin). The input is connected through the transconductance (5) to an output resistor (Rout). The voltage output is taken between the output resistor and the transconductance (5). The voltage reference (3) has a third current source (I₃) feeding a diode connected transistor (Q₁) and a resistor (R₁). A second current source (I₂) feeds into the resistor after the transistor. The base of the diode connected transistor (Q₁) is connected to the voltage input. The transconductance (5) has a second transistor (Q₂) whose base is connected to the voltage input, collector sinks current from a fourth current source and emitter feeds current to a resistor (R₂). A first current source (I₁) feeds. current to a third transistor (Q₃) and to a current mirror. The base of the third transistor (Q₃) is connected between the fourth current source (I₄) and the collector of the second transistor (Q₂). The current mirror draws current from the output resistor (Rout) and feeds current to between the emitter of the second transistor (Q₂) and its associated resistor (R₂). The transconductance creates a feed back loop such that a change in the first and second current sources creates a steady-state current drawn through the resistor (R₂) that is one-half of the first current source current. The circuit produces symmetrical clipping of an input voltage signal at the voltage output.

Description: This invention relates to clipping circuits. More particularly, it relates to such circuits for clipping signals substantially symmetrically. BACKGROUND OF THE INVENTION Clipping is the limiting of the amplitude of an output signal when an input signal is above a given amplitude. Typically clipping occurs when the amplitude of the output signal reaches one of the supply rails, or an output stage driving transistor reaches its maximum output current by going into saturation or reaching maximum drive current. For many applications, especially audio applications as described in US-A-4 004 242, it is desirable that clipping be performed symmetrically. Asymmetrical clipping introduces even harmonics to the output signal. Even harmonics do not naturally occur in audio signals and their presence can produce noticeable distortion for a listener. Where clipping occurs as a result of the output signal amplitude reaching a supply rail at a different amplitude, with respect to the normal bias point of the output stage, from the amplitude at which the driving transistor reaches its maximum output current asymmetrical clipping will occur. As a result, most output stages for applications where symmetrical clipping is desirable set the output stage bias point to be midway between one supply rail and the output voltage when the driving amplifier reaches its maximum output current. Typically, an output stage will consist of a bipolar junction transistor (BJT) amplifier whose emitter is connected to one supply rail and whose collector is connected through a resistor to the other supply rail. The input to the output stage is a current at the base of the transistor, while the output of the output stage is at the collector of the transistor. The only factor limiting upward signal excursion, assuming the other supply rail is a positive supply rail, is the difference between the bias point at the output and the positive supply rail. This difference is easily controlled. On the other hand the factors limiting downward signal excursion are the current gain of the amplifier, the driving current at the base of the amplifier and the saturation point of the amplifier. These factors are processing sensitive and interdependent. In order to obtain substantially symmetrical clipping each factor is set up at the time of processing and cannot be adjusted thereafter. In order to change the amount of clipping it is necessary to have separately processed circuits with each of the factors set for each desired clipping level. SUMMARY OF THE INVENTION A clipping circuit in accordance with the invention comprises: (a) a voltage reference stage having generating means for producing a reference voltage and an output port connected to said generating means for outputting said reference voltage; (b) a transconductance stage having control means coupled to said output port of said voltage reference stage and, a first current source coupled to said control means, said first current source including means for generating a drive current having a first pre-determined value; (c) said transconductance stage further including a gain stage coupled to said first current source for receiving current therefrom, said gain stage also being coupled to said control means; (d) an input port for receiving an input signal, said input port being coupled to said output port of said voltage reference stage and to said control means; (e) said control means including means responsive to said input signal for controlling the amount of said drive current flowing from said first current source to said gain stage; (f) said gain stage including means responsive to the amount of said drive current received thereby for generating an output current proportional to the amount of said drive current received by said gain stage and for making said output current of said gain stage have a pre-determined maximum value proportional to said first pre-determined value; (g) and bias means including feedback mean connect to said control means for biasing said control means to control said gain stage for said output current of said gain stage to have in the absence of any input signal, a steady-state value which is substantially one-half of said pre-determined maximum value. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, which show a preferred embodiments of the present invention, and in which: Figure 1 is a block diagram of a clipping circuit according to the preferred embodiment of the present invention; Figure 2 is a circuit diagram of the clipping circuit of Figure 1; Figure 3 is a detailed circuit diagram of the clipping circuit of Figure 1 and Figure 4 is a circuit diagram of the voltage reference stage with added impedance. Referring to Figure 1, a symmetrical clipping circuit 1, in accordance with the invention, has a voltage reference stage 3 and a transconductance stage 5. The voltage reference stage 3 and the transconductance stage 5 are connected together and through a coupling capacitor C in to a voltage input V in . The voltage reference stage 3 outputs a reference voltage V R . The output of the transconductance stage 5 is connected through a resistor R out to a first supply rail V s . An output voltage, V o , is provided between R out and the output of the transconductance stage 5. The transconductance stage 5 outputs a current I o as a function of the voltage input Vin and includes a source of limited drive current I D . I D is limited in the sense that it has a given maximum current. The reference voltage V R sets a bias output current I obias for the circuit 1. V R and I D are matched so that a change in V R is matched by a change in I Dmax such that the bias output current I obias is substantially one-half of a maximum output current I omax . It will be seen that a change in V in changes the input voltage to the transconductance stage 5, which will cause a change in the drive current I D . As discussed, to ensure the symmetrical clipping circuit 1 modifies the output bias current I obias so that it remains substantially one-half of the maximum output current I omax . The output voltage V o is equal to V s - R out x I o . During steady state operation, the output current equal to output bias current I obias and V obias is V s - I obias x R out . The maximum upward signal swing from V obias , assuming V s is positive with respect to the output of the transconductance stage 5 and I o is negative, occurs when I obias is zero and is therefore I obias x R out . The maximum downward signal swing from V obias is I omax x R out - I obias x R out . As I omax = 2 I obias the maximum downward signal swing from V obias is I obias x R out . Thus the upward and downward signal swings are matched. R out acts as a linear current controlled voltage source. Referring to Figure 2, the transconductance stage 5 may be implemented using a gain controlled block A between I D and V o . The gain block A is driven by the drive current I D . The gain of block A is controlled in that the gain is known and can be implemented using a substantially processing insensitive component. As the gain of block A is controlled the relationship between the proportion of I D and the output current I o is not affected by processing. Connected between the source of drive current I D and the voltage reference V R is a voltage to current converter 7 outlined in dashed lines. The voltage to current converter 7 determines the amount of drive current I D to be supplied to the controlled gain block A. The amount of drive current I D is one-half of the difference between maximum and minimum drive current when there is a steady-state signal at the input to the transconductance stage 5. Otherwise, the amount of drive current I D is proportional to the input to the transconductance stage 5 unless the maximum or minimum drive current is reached. For the simplest implementation the minimum drive current should be set to zero (i.e. the source of drive current is shut off) and the maximum output current I omax is twice the steady-state output current I obias . When this happens V o swings between V s when the drive current is zero and 2R out I obias from V S . This guarantees symmetrical clipping. In order to communicate when the steady-state has been reached and what proportion of the maximum drive current is flowing, the controlled gain block A is connected back to the voltage to current converter 7. This connection provides a feedback loop 10. The voltage reference stage 3 has a current controlled first voltage source V 1 connected between a second supply rail, in this case ground GND, and the output of the voltage reference V R . The first voltage source V 1 is controlled by a second current source I 2 . The voltage to current converter 7 has a current controlled second voltage source V 2 and a voltage controlled current sink I s . The current control input of the second voltage source V 2 is connected to the current sink I s and to the gain block A via the feedback loop 10. The voltage control of the current sink I s is connected between the second voltage source V 2 and the input to the transconductance 5. The current sink is connected to the source of driving current I D . In operation, based on the voltage input V in the voltage to current converter 7 determines the proportion of maximum drive current I D presently flowing from the gain block A and represented in part as the voltage across the second voltage source V 2 . An increase in the second voltage source will decrease the voltage at the control input to the current sink I s , thereby decreasing the current being sunk. This decreases the output of the voltage to current converter 7 and decreases the amount of drive current I D . Additionally it decreases the sunk current flowing into the current control input of the second voltage source V 2 . Accordingly when the input voltage V in reaches a steady-state value the transconductance stage and the drive current I D 5 will also reach a steady-state. Referring now to Fig. 3, the current controlled first voltage source V i has been implemented using a diode connected first BJT Q 1 fed by a third current source I 3 and connected through a first passive element to the second supply rail GND. The first passive element is a resistor R 1 . The reference voltage V R is output at port 30 which also constitutes the input port for the transconductance stage 5. The signal input port for the circuit 1 for receiving Vin, is indicated at 32. A second current source I 2 is connected to Q 1 and R 1 . The voltage controlled current sink I s is a second BJT Q 2 whose base is connected to the base of Q 1 , and hence the input voltage Vin via the port 30 and the capacitor Cin, and whose emitter is connected to the controlled gain block A implemented by Q 4 and Q 5 as will be later described. The current controlled second voltage source V 2 is a passive element, in this case a resistor R 2 , connected between the emitter of Q 2 and ground. The source of driving current I D has a first current source I 1 , fourth current source I 4 , and a third BJT Q 3 . I 4 is connected to the collector of Q 2 and the base of Q 3 . I 1 is connected to the collector of Q 3 . The emitter of Q 3 is connected to ground. The controlled gain block A has current mirror connected fourth and fifth BJTs Q 4 , Q 5 . The collector of Q 4 is connected to I 1 and the collector of Q 5 is connected to the output voltage V o . The emitters of Q 4 , Q 5 are connected to the emitter of Q 2 . In operation, the collector current of Q 5 is the output current I o . As previously discussed, the condition of operation for symmetry is I obias = ½ I omax . To show how the circuit of Figure 3 achieves this condition it is assumed for simplicity that the gain block A has a gain of 1. A current mirror is used to implement the gain block A as the gain of a current mirror is easily controlled during processing by fixing the ratio of the physical areas of the BJTs. It is further assumed that I 4 is approximately equal to I 3 , Q 1 and Q 2 have substantially the same gain and R 1 has substantially the same resistance as R 2 . I 3 will flow through Q 1 and I 3 and I 2 will flow through R 1 . It will be evident that the voltage drop across the resistor R 1 in the emitter junction of Q 1 creates the reference voltage at the base of Q 1 . Looking at the transconductance stage 5, as the gain of the current mirror comprising the gain block A is unity, the current flowing in the collectors of Q 4 and Q 5 will be substantially the same. The maximum drive current flowing into the gain block A will be I 1 , i.e. when Q 3 shuts off. Therefore I omax is substantially equal to I 1 . It will be seen by applying an input voltage V in , the circuit 1 is biased and the resultant current flowing in the feedback loop 10 from the gain block A is 2I 1 or 2I obias . Symmetrical clipping, i.e. I obias = ½ I omax is achieved by making the current source I 1 substantially equal to the current source I 2 . Applying the well-known Kirchhoff's Voltage Law around the emitter-base loop of transistors Q 1 and Q 2 , the following expression is obtained: -V R1 - V BE1 + V BE2 + V R2 =0. Since I 3 is substantially the same as I 4 , and Q 1 and Q 2 are matched, the V b 's of Q 1 and Q 2 will be substantially the same and drop out of the above expression. Then, V R1 is equal to V R2 . Applying the well-known Ohms law, the following expression is obtained: (I 2 + I 3 )R 1 = (I 4 + 2I 1 )R 2 (I 2 + I 3 )R 1 = (I 4 + 2I obias )R 2 Since, R 1 is substantially the same as R 2 , and I 3 is substantially the same as I 4 , the above expression reduces to 2I obias = I 2 . Therefore, if I 1 is substantially equal to I 2 , then I obias is equal to ½ I 1 or 1/2 I Dmax . Should I 2 not substantially equal twice I obias then the voltage across R 2 will be too high or too low. Should the voltage across R 3 be too low, Q 2 will turn on harder, drawing current away from the base of Q 3 . Less current will flow from I 1 into Q 3 and more into the gain block A. More current will flow out of the gain block A and R 2 to raise the voltage across R 2 until I obias reaches ½ I 2 . The opposite effect will occur when the voltage across R 2 is too high. Thus if I 1 is substantially the same as I 2 then I obias will be one-half of I omax . The gain of Q 2 must be sufficiently high not to draw away significant current from Q 3 affecting the mirroring process. Q 3 acts as a current controlled current sink sinking current away from I 1 (all or part of I 1 ) and Q 4 , Q 5 each output a current which is proportional to the current received by Q 4 . It is possible to make devices where I obias is substantially one-half of I omax without having I 1 and I 2 , I 3 and I 4 , R 1 and R 2 , Q 1 and Q 2 , and Q 4 and Q 5 substantially the same. It is important though to match these components to ensure the ultimate circuit 1 does meet the I obias is substantially one-half I omax criterion. For example, where Q 5 has twice the gain of Q 4 the gain of the gain block A will be approximately 2. I omax will be twice I 1 . As discussed to achieve symmetrical clipping I obias must be ½ I omax and therefore I obias must be equal to I 1 . At equilibrium I 2 must be set to 1.5 I 1 . In these circumstances I 2 should equal one-half the gain of the gain block A plus one-half, multiplied by I 1 . Other matching of the components will be evident to those skilled in the art. Another advantage of the circuit 1 is that the small signal voltage gain is independent of the clipping level. For a change in V in , the V be of Q 2 will leg behind the change causing the voltage across R 2 to change. The change in the voltage across R 2 will draw a proportionally different current through the gain block A into R 2 . This changes I o by one-half the change in the current in the gain block A. V o will change by a factor of R out times the change in I o . Thus the small signal gain of the circuit is approximately R out x α, R 2 1 + α where α is the gain of the gain block A. Referring now to Figure 4, a resistor R 3 between the base and collector of Q 1 , and a resistor R 4 between the collector of Q 1 and the connection of the coupling capacitor C in and the base of Q 2 , may be added to increase the input impedance seen by V in . R 3 and R 4 should be matched, and for simplest implementation be substantially the same, to keep the mirroring effect of Q 1 and Q 2 .

Claims: A clipping circuit (1) comprising: (a) a voltage reference stage (3) having generating means (Q 1 , R 1 , I 2 , I 3 ) for producing a reference voltage (V R ) and an output port (30) connected to said generating means for outputting said reference voltage; (b) a transconductance stage (5) having control means (Q 2 , Q 3 ) coupled to said output port (30) of said voltage reference stage (3), and a first current source (I 1 ) coupled to said control means (Q 2 , Q 3 ), said first current source (I 1 ) including means for generating a drive current having a first pre-determined value; (c) said transconductance stage (5) further including a gain stage (Q 4 ,Q 5 ) coupled to said first current source (I 1 ) for receiving current therefrom, said gain stage (Q 4 , Q 5 ) also being coupled to said control means (Q 2 , Q 3 ); (d) an input port (32) for receiving an input signal (Vin), said input port (32) being coupled to said output port (30) of said voltage reference stage (3) and to said control means (Q 2 , Q 3 ); (e) said control means (Q 2 , Q 3 ) including means (Q 2 , Q 3 ) responsive to said input signal (Vin) for controlling the amount of said drive current (I 1 ) flowing from said first current source (I 1 ) to said gain stage (Q 4 , Q 5 ); (f) said gain stage (Q 4 , Q 5 ) including means (Q 4 , Q 5 ) responsive to the amount of said drive current (I 1 ) received thereby for generating an output current (I o ) proportional to the amount of said drive current (I 1 ) received by said gain stage (Q 4 , Q 5 ) and for making said output current (I o ) of said gain stage (Q 4 , Q 5 ) have a pre-determined maximum value proportional to said first pre-determined value (I 1 ); (g) and bias means (10, R 2 , I 4 ), including feedback means (10) connect to said control means (Q 2 , Q 3 ) for biasing said control means (Q 2 , Q 3 ) to control said gain stage (Q 4 , Q 5 ) for said output current (I o ) of said gain stage (Q 4 , Q 5 ) to have in the absence of any input signal (Vin), a steady-state value which is substantially one-half of said pre-determined maximum value. A circuit according to Claim 1, wherein said pre-determined maximum value of said output current (I o ) is substantially equal to said first pre-determined value (I 1 ). A circuit according to Claim 1 or 2, wherein said feedback means (10) comprises means connected from said gain stage (Q 4 , Q 5 ) to said control means (Q 2 , Q 3 ) for feeding back to said control means (Q 2 , Q 3 ) a current which is proportional to said output current (I o ). A circuit according to Claim 3, wherein the voltage reference stage (3) includes a second current source (I 2 ) and a first current controlled voltage source (R 1 , Q 1 ) coupled to said output port (30) and connected to said second current source (I 2 ) for generating said reference voltage (V R ). A circuit according to Claim 4, wherein said control means (Q 2 , Q 3 ) includes a voltage controlled current sink (Q 2 ) coupled to said output port (30), a second current controlled voltage source (R 2 ) connected to said voltage controlled sink (Q 2 ) and to said feedback means (10), said voltage controlled current sink (Q 2 ) including means coupled to said first current source (I 1 ) and responsive to the voltage difference between said second current controlled voltage source (R 2 ) and said output port (30) for causing said control means to sink current from said first current source (I 1 ) in proportion to said voltage difference. A circuit according to Claim 5 and further including a pair of voltage supply rails (V s , GND), wherein said voltage reference stage (3) includes a third current source (I 3 ), said first current controlled voltage source (R 1 ) comprising a first passive element (R 1 ) having two terminals and a diode connected first bi-polar junction transistor (Q 1 ) with its base connected to said output port (30) and to said third current source (I 3 ) and with its emitter connected to the first terminal of said first passive element (R 1 ) and to said second current source (I 2 ), and the second terminal of said first passive element (R 1 ) being connected to one of said supply rails (GND). A circuit according to Claim 6, wherein said second current controlled voltage source (R 2 ) comprises a second passive element (R 2 ) having two terminals, said transconductance stage (5) includes a fourth current source (I 4 ) and said voltage controlled current sink comprises a second bi-polar junction transistor (Q 2 ) having its base connected to said output port (30) and its collector connected to said fourth current source (I 4 ) and coupled to said first current source (I 1 ) and its emitter connected to one terminal of said second passive element (R 2 ) and to said feedback means (10) and wherein the other terminal of said second passive element (R 2 ) is connected to one of said supply rails (GND). A circuit according to Claim 7, wherein the first (Q 1 ) and second bipolar (Q 2 ) junction transistors have substantial the same gain, said first (R 1 ) and second (R 2 ) passive elements are resistors having substantially the same resistances, and the current in said first (I 1 ) and second (I 2 ) current sources are substantially the same. A circuit according to Claim 7, wherein the current in said second (I 2 ) current source is substantially equal to the current in said first current (I 1 ) source multiplied by one-half of the gain of the gain stage (Q 4 , Q 5 ) plus one-half. A circuit according to Claim 7, wherein the gain of said gain stage (Q 4 , Q 5 ) is substantially equal to one and the currents in said first (I 1 ) and second (I 2 ) current sources are substantially the same. A circuit according to Claim 10, wherein said control means (Q 2 , Q 3 ) includes a current controlled current sink (Q 3 ) coupled to said voltage controlled current sink (Q 2 ) and to said first current source (I 1 ) and having means for sinking current from said first current source (I 1 ) and for receiving an output current from said voltage controlled current sink (Q 2 ). A circuit according to Claim 11, wherein said current controlled current sink is a bi-polar junction transistor (Q 3 ) with its collector connected to said first current source (I 1 ) and coupled to said gain stage (Q 4 , Q 5 ) and with its base connected to the collector of said second bi-polar junction transistor (Q 2 ) and to said fourth current source (I 4 ) and with its emitter connected to one of said supply rails (GND). A circuit according to Claim 12, wherein said gain stage (Q 4 , Q 5 ) is a current mirror having means for receiving current from said first current source (I 1 ) and for producing a mirror output current (I o ) from said transconductance stage (5) and for sending current received from said first current source (I 1 ) and said output current (I o ) to said feedback means (10). A circuit according to Claim 13, wherein said gain stage (Q 4 , Q 5 ) comprises a diode connected fourth bi-polar junction transistor (Q 4 ) and a fifth bi-polar junction transistor (Q 5 ), the base and collector of said fourth bi-polar junction transistor (Q 4 ) being connected to the base of said fifth bi-polar junction transistor (Q 5 ) the emitters of said fourth (Q 4 ) and fifth (Q 5 ) bi-polar junction transistors being connected to said feedback means (10), and the collector of said fourth bi-polar junction transistor (Q 4 ) being connected to said first current source (I 1 ) and to the collector of said current controlled current sink (Q 3 ). A circuit according to Claim 14, wherein the gains of said fourth (Q 4 ) and fifth (Q 5 ) bi-polar junction transistors are substantially the same. A circuit according to Claim 14 and further comprising a substantially linear current controlled voltage source (R out ), and a circuit output port (V o ), said linear current controlled voltage source (R out ) being connected between the other one of said supply rails (V s ) and the collector of said fifth bi-polar junction transistor (Q 5 ), and said circuit output port (V o ) being connected to the collector of said fifth bi-polar junction transistor (Q 5 ). A circuit according to Claim 16, wherein said linear controlled voltage source comprises a third resistor (R out ). A circuit according to Claim 17, wherein the gain of the circuit is R out R 2 1 + g Where, R out is the resistance of said third resistor (R out ), R 2 is the resistance of said second passive element, and g is the gain of said gain stage (Q 4 , Q 5 ). A circuit according to Claim 18, wherein said voltage reference stage (3) further includes a fourth resistor (R 3 ) and a fifth resistor (R 4 ), said fourth resistor (R 3 ) being connected between the base and the collector of said first bi-polar junction transistor (Q 1 ), and said fifth resistor (R 4 ) being connected between the collector of the first bi-polar junction transistor (Q 1 ) and said output port (30) of said reference voltage stage (3). A circuit according to Claim 19, wherein said fourth (R 3 ) and fifth resistor (R 4 ) have substantially the same resistance. A circuit according to any one of the preceding claims and further including a coupling capacitor (Cin) and a circuit input (32), said coupling capacitor (Cin) being connected between said circuit input (32) and the input port (32).

Inventors: ARMSTRONG STEPHEN WADE, ARMSTRONG, STEPHEN WADE
Applicants: GENNUM CORP, GENNUM CORPORATION
Application year: 1990
Main classification: H03G11
IPC codes: H03G11