Microprocessor cooperating with a coprocessor

Abstract: A microprocessor, which can be coupled externally with a coprocessor in order to extend an instruction set, includes a first set of terminals to be coupled to the coprocessor for data transfer between the microprocessor and the coprocessor, and a second set of terminals to be coupled to an external memory other than the coprocessor for data transfer between the microprocessor and the external memory. The microprocessor also includes a first but control unit connected to the first set of terminals for controlling the first set of terminals, independently of the second set of terminals, thereby to control the data transfer between the microprocessor and the coprocessor, and a second but control unit connected to the second set of terminals for controlling the second set of terminals, independently of the first set of terminals, thereby to control the data transfer between the microprocessor and the external memory.

Description: Background of the Invention Field of the invention The present invention relates to a microprocessor, and more specifically to a microprocessor which can extend an instruction by a coprocessor externally coupled with the microprocessor, as well as to a microprocessor system comprising a microprocessor, an external unit and a coprocessor, and to a method for performing a data transfer in said system. Description of related art In general, a microprocessor has to be assembled on a semiconductor chip of a limited size. Therefore, although performance of the microprocessor were sacrificed to some extent, an independent function is assembled on another chip or LSI which is independent of and external to the microprocessor. With various functions assigned to different single-chip LSIs, it is possible to prevent the chip size of the microprocessor from being increased to a size which cannot be manufactured under the current technique, and also to avoid increase of a cost caused by increase of the chip size. Particularly, in microprocessors of 16 bits or more which have been required to have a high degree of performance and a high degree of function, a microprocessor is closely coupled to various LSIs having a floating point arithmetic operation, a memory management mechanism, a memory buffer (cache) mechanism, and others. If these functions are assembled within the microprocessor, a system having a high function and a small size can be realized. However, these functions have been realized externally of the microprocessor for the reason as mentioned above. An LSI provided externally to the microprocessor in order to extend an instruction set for the microprocessor is generally known as a coprocessor. Typical functions of the coprocessor include a floating point arithmetic operation. Conventional microprocessors of 4 bits and 8 bits and some types of microprocessors of 16 bits had have only instructions handling integers, because applications had been relatively simple. With expanding application fields, however, it is becoming required to execute a floating point arithmetic operation at a high speed. The conventional microprocessors have executed the floating point arithmetic operation in a software manner by combining instructions for handling integers, since the conventional microprocessors did not involve instructions for floating point arithmetic operations. As a result, the conventional microprocessors can have only a floating point arithmetic operation performance extremely lower than an integer arithmetic operation performance. In general, a coprocessor for a floating point arithmetic operation is closely coupled to a microprocessor so as to execute a floating point arithmetic operation in place of the microprocessor when the coprocessor itself detects or is notified from the microprocessor that the microprocessor tries to execute an instruction for the floating point arithmetic operation (actually, the microprocessor cannot execute the floating point arithmetic operation). When the coprocessor for the floating point arithmetic operation is in a condition of executing the floating point arithmetic operation, the microprocessor can execute an instruction other than the instruction for the floating point arithmetic operation. For example, in a typical conventional system having a microprocessor coupled to a coprocessor for a floating point arithmetic operation, the microprocessor of for example 32 bits are coupled to an external memory and the coprocessor for the floating point arithmetic operation through a data bus of 32 bits, an address bus of 32 bits and status signal lines. The status signal lines are used for notify a kind of bus cycle, timing signals, etc. generated by the microprocessor, to the coprocessor and the memory. On the other hand, the coprocessor outputs to the microprocessor a busy signal notifying that the coprocessor is in a condition of executing the floating point arithmetic operation. In brief, the microprocessor includes therein a bus control unit coupled to the data bus, the address bus and the status signal lines, an instruction decoder coupled to the bus control unit for decoding an instruction fetched by the bus control unit, and an instruction execution unit for executing the instruction decoded by the instruction decoder. When an instruction other than that for the floating point arithmetic operation (called "normal instruction" hereinafter) is executed, the normal instruction is fetched from the external memory to the bus control unit of the microprocessor in an instruction fetch bus cycle, and decoded by the instruction decoder. As a result, the kind of an operation, the kind of operands (for example, register/memory, read/write, etc.) and others are notified to the execution unit. When there is a memory read operand, the execution unit instructs to the bus control unit so as to start an operand read bus cycle. A memory operand stored in the external memory is transferred (or read) to the bus control unit of the microprocessor in the operand read bus cycle. On the other hand, if there is a register operand, a general register ordinarily provided within the execution unit is selected as the operand. After the memory operand is prepared in the bus control unit of the microprocessor, data of the memory operand is supplied to the execution unit of the microprocessor and an actual execution of the instruction is performed. Then, if the execution unit of the microprocessor is previously notified by the instruction decoder of the microprocessor that the result of the instruction execution is returned or written to the external memory, the execution unit operates to instruct the bus control unit so as to start an operand write bus cycle, and at the same time to transfer the result of the instruction execution (i.e., data to be written to the memory) to the bus control unit of the microprocessor. Thus, the result of the instruction execution is transferred (or written) to the external memory in the operand write bus cycle. In the case of executing a floating point arithmetic operation, the same operation as that for the normal instruction is performed until the kind of operation and the kind of operands are notified by the instruction decoder. Floating point data stored in the external memory ordinarily consists of 32 bits or more (64 bits or 80 bits), and therefore, cannot be all fetched to the bus control unit of the microprocessor in only one operand read bus cycle. Namely, a plurality of operand read bus cycles are required for completely fetching the floating point data After the floating point data is completely fetched, the execution unit of the microprocessor instructs to start a coprocessor operand write bus cycle, so that the floating point data temporarily stored in the bus control unit of the microprocessor is transferred (or written) to the coprocessor. This transfer also in most cases requires a plurality of bus cycles, for the reason as mentioned above. On the other hand, the kind of operation decoded by the instruction decoder and supplied to the execution unit of the microprocessor is converted (or reconstructed) by the execution unit to a format (command) which can be decoded by the coprocessor. The commend generated by the execution unit of the microprocessor is transferred to the bus control unit, and at the same time, the execution unit instructs the bus control unit so as to start the coprocessor write bus cycle. If the command is transferred (or written) to the coprocessor in the coprocessor write bus cycle, the coprocessor starts an arithmetic operation of the floating point data which had been transferred before the transfer of the command. When the coprocessor is in a condition of executing the arithmetic operation of the floating point data, the coprocessor outputs the busy signal to the microprocessor for notifying that the coprocessor is in a busy condition. On the other hand, if the microprocessor detects the busy signal from the coprocessor, the microprocessor judges that the execution of the floating point operation instruction has not yet been completed, and therefore, the microprocessor cannot start an execution of a next instruction. Namely, the microprocessor waits until the busy signal outputted from the coprocessor is brought into a ready condition. When the coprocessor has completed the execution of the floating point operation instruction, the coprocessor brings the busy signal into the ready condition, so that the microprocessor can know the completion of the execution of the floating point operation instruction. At this time, similarly to the case of the execution of the normal instruction, if it has been notified by the instruction decoder to the execution unit that it is required to return the result of the operation to the external memory, the execution unit of the microprocessor then starts a coprocessor operand read cycle, so that the result of the operation is first transferred (or read out) to the bus control unit. Thereafter, the execution unit of the microprocessor instructs the bus control unit of the microprocessor so as to cause the bus control unit to transfer the result of the execution to the external memory in the operand write bus cycle. As seen from the above, an assignment of the execution of the floating point operation from the microprocessor to the coprocessor requires the coprocessor operand write bus cycle, the coprocessor write bus cycle, and the coprocessor operand read bus cycle, which are inherently unnecessary to the microprocessor. As mentioned hereinbefore, each of the coprocessor operand write bus cycle and the coprocessor operand read bus cycle is performed twice or more in most cases, and therefore, the bus cycles inherently unnecessary to the microprocessor are substantially many. In addition, when an arithmetic operation (for example, addition) for two operands is to be executed, if both of the two operands are memory operands, the coprocessor operand write bus cycle is required for each of a first operand and a second operand. For example, if a floating point arithmetic operation is executed for two items of 64-bit length floating point data stored in the external memory, four coprocessor operand write bus cycles, one coprocessor write bus cycle and two coprocessor operand read bus cycles are required because the floating point arithmetic operation is executed by the coprocessor. Recently, in order to elevate performance, some of microprocessors have adopted a so-called pipelined structure which can simultaneously treat a plurality of instructions, for example, by simultaneously processing a fetching of an instruction, a decoding of another instruction, and an execution of still another instruction, or by further increasing stages for these operations.. The pipelined system is advantageous in that since the processing of instructions can be divided into some number of stages, an apparent execution performance is increased. However, this advantage can be obtained by ensuring that an allocated instruction processing is performed in each stage without delay. For example, an ideal performance of the pipelined system cannot be obtained if there occurs a so-called pipeline hazard in which one stage requires the result of a processing made in a succeeding stage, or a bus neck in which a stage cannot start a necessary bus cycle because an external data bus indispensable to the pipelined system is in use by another stage. As mentioned above, in a conventional microprocessor associated with a coprocessor, since an address bus and a data bus commonly used by the microprocessor, an external memory and the coprocessor are occupied for some constant time for a data transfer required in a floating point arithmetic operation, the bus neck has occurred. Furthermore, if the coprocessor has an high processing speed, the coprocessor quickly completes execution of its assigned operation. For example, a conventional coprocessor for a floating point arithmetic operation can process at the order of 10 clocks the four fundamental rules of arithmetic operations which are frequently used. On the other hand, the number of clocks for using the data bus often exceeds the clock number for the arithmetic operation. This has been a serious problem since the microprocessor becomes to have a large amount of overhead. EP-A-0,092,429 discloses a special instruction processing unit for a data processing system. The described apparatus is characterized by a separate coprocessor bus which is provided additionally to the system bus. Further, since the coprocessor itself also contains an instruction decoding unit, the coprocessor is capable of determining by itself which operands are to be fetched from the memory via the microprocessor into the coprocessor, thereby reducing the necessary amount of information about the operands which have to be transferred from the microprocessor to the coprocessor. Summary of the Invention Accordingly, it is an object of the present invention to provide a microprocessor, a microprocessor system, and a method for performing a data transfer in said system which have overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a microprocessor which is used in combination with a coprocessor and which can elevate availability of a system bus by an external device other than the coprocessor. The above and other objects are achieved in accordance with the present invention as defined in independent claims 1 and 2. Dependent claims 3 and 5 define particular embodiments of the invention. In the system in accordance with the present invention, the second set of terminals of the microprocessor can be coupled to the external device through a system bus, and the first set of terminals of the microprocessor can be coupled to the coprocessor through an additional bus, different from the system bus. Therefore, the microprocessor can perform data transfer between the microprocessor and the coprocessor by use of the additional bus, without intermediary of the system bus between the microprocessor and the external device. In other words, the data transfer bus between the microprocessor and the coprocessor is separated from the data transfer bus between the microprocessor and the external device. Therefore, the rate of use of the system bus between the microprocessor and the external device at the time of an instruction execution extended by the coprocessor, can be decreased. Accordingly, the generation of the bus neck can be restrained. In a pipelined system, furthermore, since an instruction processing can be smoothly performed in each stage of the pipelined system, the system can execute a stream of instructions with a small amount of overhead. In addition, if the first set of terminals of the microprocessor are made to have the same structure of the second set of terminals, namely, if the additional bus coupled between the microprocessor and the coprocessor is made the same in structure as the system bus coupled between the microprocessor and the external device, the coprocessor which has been coupled to the system bus in a conventional system, can be coupled to the additional bus and hence the first set of terminals of the microprocessor, without modifying the coprocessor, and without modifying an interface of the coprocessor. The additional bus between the microprocessor and the coprocessor is used only for coupling between the microprocessor and the coprocessor, and therefore, is permitted to be small in driving current and has only a small load capacitance, differently from the system bus to be coupled with a large amount of bus resources including a memory, an input/output device, etc. Therefore, an interface of the coprocessor to be electrically coupled to the additional bus can be made simple. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of an embodiment of the microprocessor in accordance with the present invention coupled to a coprocessor; Figure 2 is a timing chart illustrating the bus cycle for the coprocessor bus coupled between the microprocessor and the coprocessor in the system shown in Figure 1; Figure 3 illustrates the bus cycle realized in the system shown in Figure 1; Figure 4 is a block diagram illustrating an example of the execution unit and the coprocessor bus control unit in the microprocessor shown in Figure 1; and Figure 5 is a block diagram of another embodiment of the microprocessor in accordance with the present invention coupled to a coprocessor. Description of the Preferred embodiments Referring to Figure 1, there is shown a block diagram of an embodiment of the microprocessor in accordance with the present invention coupled to a coprocessor. A 32-bit microprocessor, which is generally shown by Reference Numeral 10 and is designated by "CPU" in the drawing, is coupled to an external memory 12 through a 32-bit data bus 14 (D 0-31 ) and a 32-bit address bus 16 (A 0-31 ). The CPU 10 is also coupled to the memory 12 through status signal lines 18 so as to output a group of status signals S including the kind of bus cycle, a timing and others to the memory 12. The data bus 14, the address bus 16 and the status signal lines 18 will be generally called a "system bus" hereinafter. A bus cycle executed by using the system bus is ordinarily composed of two clocks in both of a read cycle and a write cycle. However, the bus cycle can be extended to more than two clocks in response to a bus cycle extension request signal (not shown) generated by the memory 12. A coprocessor for a floating point arithmetic operation is generally shown by Reference Numeral 20 and is designated by "FPU" in the drawing. This coprocessor FPU 20 is coupled to the CPU 10 through a 32-bit data bus 22 (CD 0-31 ) and a 9-bit address bus 24 (CA 0-8 ). In addition, the coprocessor FPU 20 is coupled to receive a write signal WR and a strobe signal DS of the status signals from the CPU 10 through signal lines 26 and 28. These status signals WR and DS notifies to the coprocessor FPU 20 the kind of bus cycle and the timing generated by the CPU 10. Here, the data bus 22, the address bus 24, the status signal lines 26 and 28 will be generally called a "coprocessor bus" hereinafter. On the other hand, the coprocessor FPU 20 outputs to the CPU 10 a busy signal BUSY indicating that the FPU 20 is in a condition of executing a floating point arithmetic operation. In brief, the CPU 10 includes a bus control unit 32 (designated by "BCU" in the drawing) for controlling generation of the bus cycle in the system bus, an instruction decoding unit 34 (designated by "IDU" in the drawing) for decoding an instruction code fetched by the BCU 32, an execution unit 36 (designated by "EXU" in the drawing) for actually executing the instruction decoded by the IDU 34, and a coprocessor bus control unit 38 (designated by "CBCU" in the drawing) for controlling generation of the bus cycle in the coprocessor bus. The bus control units BCU 32 and CBCU 38 are controlled by the execution unit EXU 36, In particular, the coprocessor bus control unit CBCU 38 is controlled by the execution unit EXU 36 so as to generate a bus cycle for the coprocessor bus so that data transfer (read/write) is performed through the data bus 22 between the CPU 10 and the coprocessor FPU 20. Data to be transferred (or written) to the coprocessor FPU 20 is temporarily set in the coprocessor bus control unit CBCU 38 by the execution unit EXU 36. On the other hand, data to be transferred (or read) from the coprocessor FPU 20 is fetched by the coprocessor bus control unit CBCU 38 to the execution unit EXU 36. The bus cycle generated for the coprocessor bus under control of the coprocessor bus control unit CBCU 38 is composed of 3 clocks (states C1, C2 and C3) in both of a read cycle and a write cycle as shown in Figure 2. However, a control for extending the bus cycle for the coprocessor bus is not performed, and therefore, the bus cycle for the coprocessor bus will terminate with three clocks without exception. In this regard, the bus cycle for the coprocessor bus is different from the bus cycle for the system bus. Accordingly, since the control for extending the bus cycle is not required in the coprocessor bus control unit CBCU 38, the coprocessor bus control unit CBCU 38 can be constructed simply in comparison with the bus control unit BCU 32, and furthermore, an interface between the CPU 10 and the coprocessor 20 can be made of a simple circuit and can be timed easily. In the case of reading from the coprocessor FPU 20 to the CPU 10, a content of an internal register (not shown) of the coprocessor FPU 20 designated by the address bus 24 (CA 0-8 ) is fetched through the data bus 22 (CD 0-31 ) to the coprocessor bus control unit 38 at an end of the state C3 as shown in Figure 2. By detecting a high level of the write signal WR and a low level of the strobe signal DS , the coprocessor FPU 20 can know that the read bus cycle is started by the CPU 10. In the case of writing from the CPU 10 to the coprocessor FPU 20, data outputted onto the data bus 22 (CD 0-31 ) from the coprocessor bus control unit 38 is written to an internal register (not shown) of the coprocessor FPU 20 designated by the address bus 24 (CA 0-8 ), at an end of the state C3 as shown in Figure 2. By detecting a low level of the write signal WR and a high level of the strobe signal DS , the coprocessor FPU 20 can know that the write bus cycle is started by the CPU 10. Since the address bus 22 of the coprocessor bus is composed of 9 bits, 512 different internal registers of the coprocessor FPU 20 can be read and written at a maximum by the address bus 22 (CA 0-8 ). Now, an operation of the shown system will be explained in detail. However, an operation of the system in the case of executing an normal instruction is the same as that in the conventional microprocessor explained hereinbefore, and therefore, will be omitted for simplification of description. Before explaining the execution of a floating point arithmetic operation, it is assumed for simplification of description that a floating point data is composed of 32 bits, and an operand in question is stored in the memory 12. For example, it is assumed that there is given a "FADD.S reg.mem" instruction which instructs to add a 32-bit floating point data stored in the memory to a value stored in a data register within the coprocessor FPU 20, and to return and write the result of the addition to the memory. Processing performed until the kind of operation and the kind of operand are notified to the execution unit EXU 36 from the instruction decoder IDU 34, namely, an operand address calculation and an instruction decoding, are the same as those in the conventional system. A floating point data stored in the memory 12 is transferred (or read) to the bus control unit BCU 32 by an operand read bus cycle MEMR which is started under a request of the execution unit EXU 36. Then, the execution unit EXU 36 transfers the read data from the bus control unit BCU 32 to the coprocessor bus control unit CBCU 38, and at the same time instructs the coprocessor bus control unit CBCU 38 to start a coprocessor operand write bus cycle CPOW. For this coprocessor operand write bus cycle CPOW, a value for selecting a data port within the coprocessor FPU 20 has been loaded onto the coprocessor address bus 24, and with the coprocessor operand write bus cycle CPOW, the floating point data read from the memory is transferred to the coprocessor FPU 20 and written to the selected data port of the coprocessor FPU 20. On the other hand, similarly to the conventional system, the kind of operation notified to the execution unit EXU 36 from the decoder IDU 34 for execution of the instruction, is reconstructed to a command by the execution unit EXU 36. This command generated by the execution unit EXU 36 is transferred to the coprocessor bus control unit CBCU 38, and the execution unit EXU 36 causes the coprocessor bus control unit CBCU 38 to start a coprocessor write bus cycle CPWR. For this coprocessor write bus cycle CPWR, a value for selecting a command port within the coprocessor FPU 20 has been loaded onto the coprocessor address bus 24, and with the coprocessor write bus cycle CPWR, the command is transferred (or written) to the coprocessor FPU 20. As a result, the coprocessor FPU 20 starts a floating point additional operation on the basis of the floating point data transferred to the data port of the coprocessor FPU 20 prior to the supply of the command and a content of a data register selected by a designation included in the command transferred in the command port of the coprocessor FPU 20. In addition, the busy signal BUSY is brought to a low level, so that the execution of the operation in the coprocessor FPU 20 is detected by the execution unit EXU 36. If the operation in the coprocessor FPU 20 is completed, the result of the operation is temporarily set in the data port of the coprocessor FPU 20, and at the same time, the busy signal BUSY is brought to a high level. Since it has been notified by the decoder IDU 34 that after the operation of the coprocessor FPU 20 is completed, the result of the operation should be returned and written to the memory 12, the execution unit EXU 36 starts a coprocessor operand read bus cycle CPOR, so that the result of operation is transferred to the coprocessor bus control unit CBCU 38 once. For this coprocessor operand read bus cycle CPOR, a value for selecting a data port within the coprocessor FPU 20 has been loaded onto the coprocessor address bus 24. Then, the execution unit EXU 36 transfers the result of operation to the bus control unit BCU 32, and causes the bus control unit BCU 32 to transfer (or write) the result of operation to the memory 12 by an operand write bus cycle MEMW. Referring to Figure 3, the above mentioned bus cycle realized in the system shown in Figure 1 is illustrated. As seen from Figure 3, the data bus 14 of the system bus is occupied by the bus cycles "FETCH", "MEMR", and "MEMW", and the coprocessor data bus 22 is occupied by the bus cycles "CPOW", "CPWR" and "CPOR". Namely, since the bus cycles "CPOW", "CPWR" and "CPOR" for transferring the floating point data, the command and the result of operation are executed by using the coprocessor bus, the available time of the system bus is increased in comparison with the conventional system in which the system bus has been occupied by all of the bus cycles "FETCH", "MEMR", "CPOW", "CPWR", "CPOR" and "MEMW". Accordingly, the CPU 10 can fetch an instruction code for an instruction next to the floating point arithmetic operation, or can access a memory operand, by utilizing the increased available time of the system bus, specifically a time after the bus cycle "MEMR" and before the bus cycle "MEMW". Turning to Figure 4, there is shown a block diagram illustrating an example of the execution unit EXU 36 and the coprocessor bus control unit CBCU 38. The execution unit EXU 36 and the coprocessor bus control unit CBCU 38 are coupled to an internal data bus EBUS 40 of 32 bits. The execution unit EXU 36 includes a general register group 42 designated by "GR" in the drawing and coupled to the internal data bus EBUS 40, an operation unit 44 designated by "ALU" in the drawing, having a binary arithmetic and logic unit therein and coupled to the internal data bus EBUS 40, and a controller 46 designated by "CNT" in the drawing. This controller CNT 46 operates to generate various control signals for internal resources within the execution unit EXU 36 and resources externally of the execution unit EXU 36, and to respond to various status signals so as to perform a sequence control. In ordinary cases, the controller CNT 46 is realized by using microprograms. On the other hand, the coprocessor bus control unit CBCU 38 includes a 32-bit bidirectional latch 48 designated by "CPDR" in the drawing, and coupled to the internal data bus EBUS 40 and the coprocessor data bus 22, a 9-bit latch 50 designated by "CPAR" in the drawing, and having an input coupled to the internal data bus EBUS 40 and an output coupled to the coprocessor address bus 24, and a coprocessor bus cycle controller 52 designated by "CPBCNT" in the drawing. The bidirectional latch CPDR 48 is controlled by the control signals generated from the controller CNT 46, so as to latch data on the internal data bus EBUS 40, and to transfer a content of the bidirectional latch CPDR 48 itself to the internal data bus EBUS 40. The latch CPAR 50 is controlled by the control signals generated from the controller CNT 46, so as to latch nine lower bits of data on the internal data bus EBUS 40. The coprocessor bus cycle controller CPBCNT 52 is controlled by the control signals generated from the controller CNT 46, so as to control a sequence for the coprocessor bus cycle, and also to generate the strobe signal DS and the write signal WR . In addition, the coprocessor bus cycle controller CPBCNT 52 controls terminals of the latches CPDR 48 and CPAR 50 and a latch timing of the latch CPDR 48 from the coprocessor data bus 22. The busy signal BUSY is supplied to the controller CNT 46 together with the other status signals, so that it is utilized for the sequence control. If the floating point data or the command transferred to the coprocessor FPU 20 violates a predetermined format, or if an exception such as an overflow occurs in the course of the operation of the coprocessor FPU 20, the coprocessor FPU 20 generates an error signal ERR (not shown) indicating detection of occurrence of the exception, to the execution unit EXU 36. In response to the error signal ERR indicating the occurrence of the exception, the execution unit EXU 36 reads (or transfers) through the coprocessor data bus 22 a status port of the coprocessor FPU 20 indicating the status of the coprocessor FPU 20, and then, performs an exception processing. In the above mentioned embodiment, the example of operation between the memory operand and the register operand has been explained. In this case, the data transfer is performed three times by using the coprocessor bus. If the three data transfers were performed by using the system bus as in the conventional system, at least six clocks (three transfers multiplied by two clocks) should have been lost. In a typical coprocessor which can execute a floating point addition operation of 32 bits with eight clocks, the loss of the six clocks for the data transfer means a decrease to 60 % in the processing performance. On the other hand, the above embodiment can ensure the processing performance of 100 %. In the case of executing a 64-bit floating point addition operation between a memory operand and another memory operand, a transfer time of 12 clocks (three transfers × two bus cycles × two clocks) is required. In this case, the conventional system should have decreased the processing performance to 40 %. Furthermore, the above mentioned embodiment is not required to extend the bus cycle for the coprocessor in order to control the coprocessor bus, and therefore, an external circuit for extending the bus cycle in response to an access to the coprocessor is unnecessary. Accordingly, if the operation speed of the processor is too high, and therefore, if the bus cycle of the coprocessor bus is too high for accessing to the coprocessor, the bus cycle of the coprocessor bus control unit CBCU 38 can be extended by providing the CPU 10 with an input terminal which can allow to select an extension of a fixed clock number bus cycle. In the embodiment shown in Figure 1, the single coprocessor 20 has been coupled to the coprocessor bus. However, a plurality of coprocessors 20A and 20B each having a chip select terminal CS can be coupled commonly to the coprocessor bus, as shown in Figure 5. In Figure 5, elements similar or corresponding to those shown in Figure 1 are given the same Reference Numerals, and explanation thereof will be omitted. A portion of the coprocessor address bus 24 is coupled to a decoder 54, which generates a first chip select signal CS0 selecting the coprocessor 20A and a second chip select signal CS1 selecting the coprocessor 20B. These chip select signals CS0 and CS1 are supplied to the chip select terminals of the coprocessors 20A and 20B, respectively, The decoder 54 can generates either or both of the chip select signals CS0 and CS1 in accordance with the value on the coprocessor bus 24. The busy signal terminals of the coprocessors 20A and 20B are commonly connected to the CPU 10 and pulled up by a pull up resistor 56 to a high level. Namely, the busy signal terminals of the coprocessors 20A and 20B are connected to the CPU 10 through a wired OR circuit, so that if either of the coprocessors 20A and 20B is in a busy condition, the busy signal BUSY is applied to the CPU 10. In the second embodiment, since a plurality of coprocessors are coupled to the single coprocessor bus, it is possible to simultaneously execute different floating point arithmetic operations, or to execute the same floating point arithmetic operation for different floating point data. Therefore, the second embodiment can have a floating point arithmetic operation capability higher than that of the first embodiment.

Claims: A method for performing data transfer in a system comprising at least one microprocessor (10) one coprocessor (20), and one external unit (12), said microprocessor (10) having a first control means (32) for data transfer between the microprocessor (10) and the external unit (12) through a system bus, and a second control means (38) for data transfer between the microprocessor (10) and the coprocessor (20) through a coprocessor bus, said method comprising the steps of: fetching data required for an operation to be executed from the external unit (12) through the system bus under control of the first control means (32), determining whether said operation is to be executed by the coprocessor, said method being characterized in that if said operation is to be executed by said coprocessor, said method further comprising the steps of: transferring operand data required for the operation to the coprocessor in a coprocessor operand write bus cycle (CPOW) under control of said second control means and transferring instruction data required for the operation to the coprocessor under control of the second control means (38) in a coprocessor write bus cycle (CPWR), after execution of said operation transferring back the result of the operation from the coprocessor (20) to the microprocessor (10) under control of said second control means (38) in a coprocessor operand read bus cycle (CPOR), independently of the first control means (32), and returning said result from the microprocessor (10) to the external unit (12) under control of said first control means (32), wherein said second control means (38) controls said data transfer between said microprocessor (10) and said coprocessor (20) independently of said first control means (32) such that said first control means (32) can fetch an instruction code next to the floating point arithmetic instruction or can access a memory operand all the time during the execution of said coprocessor operand write bus cycle (CPOW), during the execution of said coprocessor write bus cycle (CPWR), during the operation time of said coprocessor and during the execution of said coprocessor operand read bus cycle (CPOR). A microprocessor comprising: a first control means (32) coupled to a first set of terminals to be connectable to an external unit (12), for controlling the data transfer between said microprocessor (10) and said external unit (12) through a system bus; a second control means (38) coupled to a second set of terminals to be connectable to a coprocessor (20) through a coprocessor bus and being able to control the transfer of an operand between said microprocessor (10) and said coprocessor (20) by performing an coprocessor operand write bus cycle (CPOW), to control the transfer of an instruction between said microprocessor (10) and said coprocessor (20) by performing a coprocessor write bus cycle (CPWR), and to control the transfer of the result of the operation from the coprocessor (20) to the microprocessor by performing a coprocessor operand read bus cycle (CPOR), said microprocessor being characterized in that said first control means (32) and said second control means (38) are adapted to be able to respectively control said data transfer between said microprocessor (10) and said external unit (12) and said data transfer between said microprocessor (10) and said coprocessor (20) independently of each other such that said first control means (32) can fetch an instruction code next to the floating point arithmetic instruction or can access a memory operand all the time during the execution of said coprocessor operand write bus cycle (CPOW), during the execution of said coprocessor write bus cycle (CPWR), during the operation time of said coprocessor, and during the execution of said coprocessor operand read bus cycle (CPOR). A microprocessor according to claim 2, said microprocessor further comprising: an instruction decoder (34) coupled to the first control means (32) and being adapted to decode an instruction fetched by the first control means (32), an execution unit (36), said execution unit being coupled to receive the instruction decoded by the instruction decoder (34) and being adapted to control the first (32) and second control means (38) on the basis of the received decoded instruction such that when an operation is to be executed by the coprocessor (20), said first control means (32) fetches from the external unit (12) through the first set of terminals data required for the operation to be executed by said coprocessor (20), and said fetched data is transferred through said second set of terminals to the coprocessor (20) under control of said second control means (38), and after the execution of the operation by the coprocessor (20), the result of the operation is transferred from the coprocessor (20) to said microprocessor (10) under control of said second control means (38) and then under control of said first control means (32) to said external unit (12). A microprocessor system comprising at least one microprocessor (10) as defined in claim 2, one coprocessor (20) and one external unit (12). A microprocessor system according to claim 4, characterized in that said system includes a second coprocessor (20B) coupled to the microprocessor (10), said system being adapted to said first coprocessor (20A) and said second coprocessor (20B) being capable of executing an operation assigned thereto independently of each other.

Inventors: KANEKO HIROAKI, KANEKO, HIROAKI, KANEKO, HIROAKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G06F9
IPC codes: G06F15, G06F9