Bitline segmentation in logic memory arrays

Abstract: The memory array circuit this invention provides connection of segmented bitlines (11) to bitline decoding circuitry (18) while, at the same time, providing connection of combined wordlines (14) to wordline decoding circuitry (19). The segmentation and decoding connections permit faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines (14) in each of the segments, effectively increasing the wordline pitch at the wordline decoder (19), while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs.

Description: BITLINE SEGMENTATION IN LOGIC ARRAYS BACKGROUND OF THE INVENTION This invention relates to segmentation of bitlines in integrated-circuit logic memory arrays. The speed of access to information contained in non-volatile memory arrays is largely dependent on the capacitance of the bitlines and the wordlines. Those capacitances are a function of choices that include the lengths of the bitlines and wordlines, pitch, bar size and aspect ratio, and process parameters. In general, small capacitances are required for fast access time during operation of memory arrays. Conventional segmentation with separate driver circuitry for each segmented wordline and for each segmented bitline is generally impermissible because that method of reducing the access time delay requires an unacceptable increase in driver circuit area on integrated circuit chips. Virtual-ground arrays, such as those of U.S. Patent 4,281,397 issued July 28, 1981 and assigned to Texas Instruments Incorporated, permit a very efficient use of space for memory cells. As the size of each floating-gate memory cell decreases and as the number of memory elements in each row and each column increases, the lengths of the wordlines and bitlines generally remain the same. Therefore, the capacitance and the access time delay associated with those bitlines and wordlines also remain approximately the same. However, as the number of cells increases, there is a need for a smaller access time delay in retrieving the increased amount of information contained in the dense memory arrays. Accordingly, there is a need for a circuit arrangement that permits rapid access time during operation of virtual-ground memory circuit arrays while at the same time minimizing the increase in area required for driver circuitry on those arrays. SUMMARY OF THE INVENTION The circuit arrangement of this invention includes segmentation of bitlines for connection to bitline decoding circuitry while, at the same time, combining wordlines of the various segments for connection to wordline decoding circuitry. The segmentation and decoding connection described and claimed herein permits faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines in each of the segments, effectively increasing the wordline pitch at the wordline decoder, while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs. BRIEF DESCRIPTION OF THE DRAWINGS The novel features of this invention are set forth in the appended claims. The invention, its features, and its advantages are described below in conjunction with the following drawings: FIG. 1 illustrates a schematic diagram, in partial block form, of a prior-art virtual-ground memory array. FIG. 2 illustrates a schematic diagram, in partial block form, of electrical connections for example of segmented bitlines and segmented virtual-ground lines according to one embodiment of this invention. FIG. 3 illustrates a schematic diagram, in partial block form, of an alternative connection for the virtual-ground column lines of FIG. 2. DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT Referring to FIG. 1, a prior-art virtual-ground memory array similar to that described in U.S. Patent No. 4,281,397 is illustrated in schematic form. Ground-column, or virtual-ground, lines 10 and output-column lines, or bitlines, 11 are connected in non-segmented form to first and second electrodes, or sources and drains, 12 and 13 of floating-gate memory cells C. Virtual-ground arrays typically have a difference of one between the number of output-column lines 11 and the number of virtual-ground lines 10. Wordlines 14 are connected to control electrodes, or control gates, 15 of the floating-gate memory cells 00-77. A megabit array may have perhaps 1024 rows and 1024 columns of memory cells C. Each output-column line 11 of the prior-art circuit of FIG. 1 is connected at one end through a first logic switch, illustrated as a pass-gate transistor, 16 to one or more input/output circuits I/O, which include sense amplifiers and other circuitry for programming and reading the memory cells C. Each ground-column line 10 is connected at one end to a source of potential Vdd and at the other end through a second logic switch, illustrated as a pass-gate transistor, 17 to a source of reference potential, Vss, shown as the circuit ground. Potential source Vdd may include a resistor or a diode-conneoted transistor in series with an energy source. Each of the gates of first pass-gate transistors 16 is connected to a separate output of column decode circuit 18. Each of the gates of second pass-gate transistors 17 is also connected to an output of a column decode circuit 18. The circuit elements of column decode circuit 18 may, of course, be distributed throughout the array to minimize the chip area required for conductors. Each wordline 14 of the prior-art circuit of FIG. 1 is separately connected to an output of row decode circuit 19. The circuit elements of row decode circuit 19 may also be distributed throughout the array to minimize the chip area required for conductors. Referring to FIG. 2, in accordance with this invention ground-column lines 10 and output-column lines 11 are segmented and are connected to the source and drain electrodes of segmented columns of memory cells in each of several modules M. A megabit array, for example, has been constructed with eight rows and two columns of modules M, each module M having 128 rows and 512 columns of such memory cells. The segmented column lines 11 of FIG. 2 have less capacitance than the capacitance of the longer column lines of prior-art Figure 1, assuming the same type of fabrication is used and assuming the same total number of memory cells in the same size array. Consequently, the access time to each memory cell is improved. Each module M typically has a difference of one between the number of segmented output-column lines 11 and the number of segmented ground-column lines 10. Each segmented output-column line 11 is connected at one end through a first pass-gate transistor 16 to one or more input/output circuits I/O. Each segmented ground-column line 10 is connected at one end to a voltage supply source Vdd and at the other end through a second pass-gate transistor 17 to a source of reference potential, Vss, shown as the circuit ground. Each of the gates of first pass-gate transistors 16 is connected to a separate output of column decode circuit 18. Each of the gates of second pass-gate transistors 17 is also connected to an output of column decode circuit 18. Each wordline 14 of a module M of FIG. 2 is electrically connected to one wordline 14 of each of the other modules M. Each set of series and parallel connected wordlines 14 is connected to a separate output of row decode circuit 19, which requires fewer levels of decode circuitry as compared to the row decode circuit 19 of FIG. 1 because of the fewer number of output signals required. While the wordlines 14 of modules M other than the selected wordline 14 of the selected module M are energized during operation, the segmented ground-column lines 10 and the segmented output-column lines 11 allow operation to be limited to the cell selected, as explained hereinafter. Assuming the same number of memory cells C in FIG. 1 and FIG. 2 with the same number of equivalent unsegmented rows and columns, the number of outputs of the column decode circuit 18 of FIG. 2 is greater than the number of outputs of the column decode circuit 18 of FIG. 1 because of the increased number of second pass-gate transistors 17 and first pass-gate transistors 16. However, under the same assumption, the number of outputs of the row decode circuit 19 of FIG. 2 is less than the number of outputs of the row decode circuit 19 of FIG. 1 because of the decreased number of wordline 14 connections. For example, if the modules M of FIG. 2 are formed such that the wordlines 14 of the FIG.1 array are divided into eight equal groups, then the number of required wordline 14 decode signals furnished by row decode circuit 19 is divided by a factor of eight as compared to the number required in FIG. 1. At the same time, however, the number of segmented ground-column lines 10 and segmented output-column lines 11 is multiplied by a factor of perhaps slightly more than eight as compared to the number required in FIG. 1, requiring the number of signals from column decode circuit 18 to be multiplied by that factor. (If a virtual-ground configuration is used, the number is slightly more than eight because each module M may have an even number of segmented output-column lines 11 and an odd number of segmented ground-column lines 10.) Therefore, column decode circuit 18 of FIG. 2 requires added levels of logic circuitry in comparison to column decode circuit 18 of FIG. 1. However, row decode circuit 19 of FIG. 2 requires fewer levels of logic circuitry in comparison to row decode circuit 19 of FIG. 1, resulting in little overall change in driver circuit space required, yet the speed of FIG. 2 non-volatile memory array is improved over the speed of the FIG. 1 non-volatile memory array. Referring to FIG. 3, the first pass-gate transistors 16 of each module M may be connected to one or more input output circuits I/O through third logic switches, shown as pass-gate transistors, 20. Similarly, the second pass-gate transistors 17 of each module M may be connected to reference voltage source Vss through fourth logic switches, shown as pass-gate transistors, 21. First and third logic switches 16 and 20 may be combined and may be located with the decoder circuitry, as may second and fourth logic switches 17 and 21. The columns of the various modules may be connected in parallel or may be operated in parallel. The column decode circuit 18 of FIG. 3 requires the same levels of decoding signals as the column decode circuit 18 of FIG. 2. The gates of third pass-gate transistors 20 and fourth pass-gate transistors 21 are connected to outputs of column decode circuit 18, which must have the same level of complexity as the column decode circuit 18 of FIG. 2. Use of third pass-gate transistors 20 or fourth pass-gate transistors 21 to select modules is advantageous because of the reduction in parasitic loading compared to the loading with all of the second pass-gate transistor 17 or first pass-gate transistor 16 outputs on a common node, as in FIG. 2. The virtual-ground lines 10 need not be decoded at each line as shown in the FIGS. Instead, the virtual-ground lines 10 may be passed to decoded lines that are decoded in another location, thereby reducing the space requirement for the virtual-ground decoder circuitry of decoder 18 and reducing the number of transistors in series located within the array boundary. This is important for EPROMs because the paths in the array must conduct large currents for programming. The series transistors that are moved out of the array boundary can be located in a less confined area where the larger size will not impact the spacing between cells. Bitlines 11 and virtual-ground lines 10 may have different functions in the read and programming modes. For example, bitlines 11 may be grounded when selected in the program mode and may be connected to the sense amplifier when selected in read mode. At the same time, virtual-ground lines 10 may be connected to high voltage when selected in the program mode and may be grounded when selected in the read mode. The circuit of this invention may be used for non-virtual-ground memory arrays, in which case the decoding circuitry for virtual-ground lines 10 is not needed. And where virtual-ground lines 10 are used, the virtual-ground lines 10 may not be segmented as shown in the FIGS. 2 and 3, while the bitlines 11 remain segmented. High capacitance virtual-ground lines 10 are not a problem because they can be driven easily. Area would be saved by eliminating the need for pass gate transistors between each module for the virtual-ground lines 10. However, elimination of the segmented virtual-ground lines 10 may cause adverse results during electrical programming. While this invention has been described with respect to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Upon reference to this description, various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art. It is contemplated that the appended claims will cover any such modifications or embodiments that fall within the scope of the invention.

Claims: A nonvolatile memory array comprising: a plurality of rows of modules (M), each said module (M) including a plurality of rows of memory cells and a plurality of columns of memory cells, wherein each memory cell has a control electrode and a current path between first and second electrodes; a plurality of row lines (14) in each said module (M) each said row line (14) connected to said control electrodes of each memory cell in a respective one of said rows of memory cells, a plurality of ground-column lines (10) and of segmented output-column lines (11), each of said first electrodes of said memory cells connected to a said ground-column line (10), each of said second electrodes of said memory cells connected to a said segmented output-column line (11), each said segmented output-column line (11) connected to an input/output circuit line through a first logic switch (16), each module having its corresponding output-column line segments a row decode means (19) for selecting and accessing said row lines (14), a column decode means (18) for selecting and activating said segmented output-column lines (11), wherein each of said row lines (14) of a said module (M) is electrically connected to a row line (14) of each of the others of said modules (M) and wherein outputs of said column decode means (18) are electrically connected to control electrodes of said first logic switches (16). The memory array of claim 1, wherein said ground-column lines (10) of said memeory array are segmented, wherein each said ground-column line (10) is electrically connected at one end to a voltage supply source (VDD) and is electrically connected at the other end through a second logic switch (17) to a source of reference potential (VSS), and wherein outputs of said column decode means (18) are electrically connected to control electrodes of said second logic switches (17). The memory array of claim 1, wherein each of said first logic switches (16) of a said module (M) is electrically connected to said input/output circuit through a third logic switch (20) and wherein said third logic switch (20) is electrically connected to an output of said column decode means (18). The memory array of claim 1, wherein said ground-column line (10) of said memory array is segmented, wherein each of said first electrodes of memory cells in each of said plurality of columns of cells in a module (M) is connected to a said segmented ground-column line (10), wherein each said ground-column line (10) is electrically connected at one end to a voltage supply source (VDD) and is electrically connected at the other end through a second logic switch (17) to a source of reference potential (VSS), wherein outputs of said column decode means (18) are electrically connected to control electrodes of said second logic switches (17), wherein each of said second logic switches (17) of a said module (M) is electrically connected to said source of reference potential (VSS) through a third logic switch (21), and wherein said third logic switch (21) is electrically connected to an output of said column decode means (18).

Inventors: DOLBY DEBRA J, SCHRECK JOHN F, DOLBY, DEBRA J., SCHRECK, JOHN F.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1990
Main classification: G11C5
IPC codes: G11C8, G11C16, G11C5, G11C7