MOS type semiconductor memory device

Abstract: A MOS type semiconductor memory device provided with an improved word line reset circuit is disclosed. The memory device comprises word lines digit lines intersecting with the word lines; means for precharging the digit lines during a resetting period; a row decorder provided for selecting one of the word lines, and the word line reset circuit includes word line reset means connected between a reference potential and the word lines, respectively, the word line resetting means being adapted to provide a current path between the reference potential and corresponding one of the word lines during the resetting period and a current path between the reference potential and each of said non-selection word lines during the active period; and control means for making an effective resistance of the current path of the word line resetting means to a first value during the active period and to a second value during the resetting period, the second value being larger than the first value.

Description: BACKGROUND OF THE INVENTION The present invention relates to a MOS type semiconductor memory device constituted with MOS transistors and, particularly, to a MOS type semiconductor memory device having a redundancy function and transistors for resetting word lines. In a MOS type semiconductor memory device (MOS memory) such as DRAM or SRAM, etc., a number of memory cells are arranged in a matrix form of rows (X) and colums (Y), word lines for selecting memory cells in the respective rows are arranged in the row direction and digit lines for transmitting data of memory cells in the respective columns are arranged in the column direction. For a reset period, the word lines are set at a reference potential such as ground potential through word line resetting transistors. In this case, the respective digit lines have been precharged to a predetermined voltage. For an active period, only one word line is selected and its potential is raised to a power source level. The remaining word lines are connected through the word line resetting transistors to the reference potential. In a MOS memory constructed as mentioned above, it is assumed that there is a defective column and there is a leak current path between a digit line and a word line in the defective column. In this case, the function of the MOS memory is maintained by substituting a redundant column provided preliminarily for the defective column. However, since, in this case, the digit line in the defective column is still precharged, a current flows from the precharge power source through the leak current path, the word line, and the resetting transistor to the reference potential during the reset period, causing power consumption during resetting (stand-by-period) to be increased. SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS type semiconductor memory device capable of lowering power consumption caused by current flowing through a short-circuit between a word line and a digit line when the digit line is replaced by a redundant digit line. The invention is defined in Claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block circuit diagram showing a main portion of a conventional MOS memory; Fig. 2 is a diagram illustrating a problem of leak current path in the conventional MOS memory; Fig. 3 is a circuit diagram showing an embodiment of the present invention; Fig. 4 is a timing chart showing an operation of the embodiment shown in Fig. 3; and Fig. 5 is a block circuit diagram showing another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION PRIOR ART DESCRIPTION A conventional MOS memory will be described with reference to Figs. 1 and 2. Memory cells MC are arranged in a matrix form of rows (X) and columns (Y). In the row direction, word lines WL1 to WLm are arranged and, in the column direction, digit lines D1 to Dn are arranged. These digit lines D1 to Dn are connected through a precharge transistor QP having a gate supplied with a precharge signal P1 to a precharge power source terminal Vp. The word lines WL1 to WLm are connected to row decorder units 1-1 to 1-m, respectively. The row decorder unit 1-1 is composed of a dynamic NAND gate formed of series connected N channel MOS transistors (NMOSTs) Q1 to Q3 to gates of which address signals X1 to X3 are supplied, respectively, and a P channel MOS transistor (PMOST) Q4, an inversion latch portion composed of PMOSTs Q5 and Q6 and an NMOST Q7 and a word drive portion composed of NMOSTs Q8 and Q9. An NMOST Q10 is a word line resetting transister having a gate connected to an output node N1 of the NAND gate. The remaining row decorder units have the same constructions as the decorder unit 1-1 except that combinations of true and complement of the address signals X1 to X3 therefor. In each X decorder unit 1, when it is not selecting a corresponding word line, the node N1 has been precharged to the power source level. A drain of the transistor Q10 is connected to a word line WL, its gate to the node N1 and its source to the ground potential point. When the X decorder 1 is not selecting a corresponding word line while its operation is in a word line selection mode or when it is operating in precharge mode, the word line WL is discharged to ground potential through the transistor Q10. The transistor Q10 functions, mainly, to prevent the non-selected word lines WL from floating. With an increase of integration density of MOS type semiconductor memory device, the use of redundancy circuit is becoming usual. In the redundancy system, it is usual to replace a unit including a defective cell in a memory cell array and a word line and a digit line associated therewith by a new unit. Further, the redundancy circuit operates to produce a inhibit signal for making a word line drive signal for the word line associated with the defective cell and an activation signal of a column selection (Y) switch for the digit line associated with the defective cell inoperable and to make a drive signal for a redundant word line or a column selection (Y) switch activation signal of a redundant digit line operable. Although, in Fig. 1, the digit lines D1 to Dn are provided for the columns, respectively, it should be noted that, as shown in Fig. 2 which shows some memory cells in more detail, each of the digit lines includes a pair of digit lines such as D1 and D1 and these digit line pairs are precharged by respective precharge circuits PC. It is now assumed that, for a short-circuit (represented by a resistance R in Fig. 2) of the digit line D1 and the word line WL, the digit line pair D1 and D1 are replaced by a redundancy digit line pair DR and DR , as shown in Fig. 2. As mentioned previously, the Y switches QY1 and QY1′ are not activated due to the generation of the inhibit signal inhibiting an activation of the Y switch when the redundancy circuit is used. Instead thereof, the redundancy Y switches QYR and QYR′ are activated. Therefore, signals on the redundancy digit line pair DR and DR are sent to input/output lines I/O and I/O . For the excluded digit lines D1 and D1 , a sense amplifier SA1 is still operative although the Y switches QY1 and QY1′ are not. Therefore, the precharge is performed for the digit lines D1 and D1 . The conventional MOS type semiconductor memory device mentioned hereinbefore includes the word line resetting transistors Q10 and, when the digit lines D1 and D1 and the word line WL are short-circuited and thus the digit lines D1 and D1 are replaced by the redundancy digit lines DR and DR , the precharge of the digit lines D1 and D1 is still performed. Therefore, leak current flows through a leak current path shown by a chain line in Fig. 2, resulting in an increase of power consumption in the stand-by period in which the precharge is to be performed. An embodiment of the present invention will now be described with reference to Figs. 3 and 4. In Figs. 3 to 5, elements and portions corresponding to those shown in Figs. 1 and 2 are depicted by same reference numerals and detailed description thereof are omitted. Fig. 3 is a circuit diagram of the first embodiment of the present invention, showing a word line drive portion thereof. Although, in the conventional MOS type semiconductor memory device shosn in Fig. 1, the gate potential of the transistor Q10 is controlled by the node N1 of the X decorder unit 1-1, it is performed by an output VG of a switch circuit 2-1 in this embodiment. The gate voltage VG is a combination of a potential supplied from the node N1 of the X decorder unit 1-1 through a transfer gate QT1 and an intermediate voltage VH supplied from an intermediate potential generation circuit (not shown) through a transfer gate QT2. VH may be, for example, about a half of the power source voltage Vcc. A signal  A has a high level during the word line selection and a low level during precharge. The transfer gate QT1 is turned on by the signal  A of high level and off by the same signal of low level. Similarly, the transfer gate QT2 is turned off by the signal  A of high level and on by the same signal of low level. Fig. 4 shows a potential variation of the gate potential VG when the X decorder unit 1-1 is selecting a word line and when it is not selecting the word line. The gate potential VG becomes the source voltage Vcc during the word line selection (TA) and takes an intermediate potential VH during the precharge (TP). A floating of the non-selected word line WL is caused mainly by coupling noise due to a digit line and a word line adjacent thereto during the word line selection operation and there is substantially no floating during precharge operation. Therefore, the operation is substantially not affected by reduced current flowing through the word line resetting transistor Q10 due to the gate potential VG thereof lowered to the intermediate potential VH during the precharge operation. As shown in Fig. 2, when there is a short-circuit R between the word line WL and the digit line D1, it is possible to prevent current from increasing during the stand-by period including the precharge operation period, by lowering the gate potential VG of the transistor Q10 during the precharge operation. Fig. 5 shows a circuit diagram of a second embodiment of the present invention. This embodiment differs from the conventional MOS semiconductor memory device shown in Fig. 1 in that a transistor Q11 is provided at an end of each word line opposite to the end to which the word line resetting transistor Q10 is connected. The transistor Q11 is controlled by a precharge signal P2 supplied to its gate. The precharge signal P2 has a high level during the word line selection and a low level during the precharge operation. When the word line is not selected during the word line selection period, the word line WL is discharged through the transistors Q10 and Q11. During the precharge operation, the transistor Q11 is turned off due to the fact that its gate becomes low level and, therefore, the word line WL is discharged by only through the transistor Q10. Therefore, the current value necessary to discharge the word line during the precharge operation is reduced, resulting in the same effect as obtained in the first embodiment. According to this embodiment, the size of the word line resetting transistor Q10 can be minimized, which is advantageous in designing masks. As described hereinbefore, the present invention which comprises means for making current flowing between the word line and the ground potential point during precharge operation smaller than that flowing when the word line is not selected during the word line selecting operation provides an effect that an increase of power consumption during stand-by period when there is a short-circuit between the word line and the digit line, etc., is prevented.

Claims: A MOS type semiconductor memory device comprising a memory cell array including a plurality of memory cells (MC) arranged in rows and columns, word lines (WL) arranged in the rows, respectively, and digit lines arranged in the columns, respectively; means for precharging said digit lines during a resetting period (TP); row decoder units (1) provided for said word lines, said row decoder units being energized during active period (TA) such that only one of them provides an output at a selection level and the remaining decoder units provide outputs at non-selection level; word line resetting means (Q10, Q11) connected between a reference potential and said word lines, respectively, said word line resetting means being adapted to provide a current path between said reference potential and corresponding one of said word lines during said resetting period and a current path between said reference potential and each of said non-selection word lines during said active period; characterised by control means (2) for making an effective resistance of said current path of said word line resetting means to a first value during said active period and to a second value during said resetting period, said second value being larger than said first value. The semiconductor memory device according to claim 1, wherein said word line resetting means includes a reset transistor (Q10) coupled between the corresponding word line (WL) and said reference potential, and said control means (2) includes first means (QT2) for supplying a gate of said reset transistor with an intermediate voltage during said resetting period, and a signal of the opposite logic level to the output of the corresponding decoder unit, during said active period. The semiconductor memory device according to claim 1, wherein said word line resetting means includes a first reset transistor (Q10) coupled between one end of the corresponding word line and the reference potential and a second reset transistor (Q11) coupled between the other end of said corresponding word line and the reference potential.

Inventors: MATSUI YOSHINORI C O NEC CORPO, MATSUI, YOSHINORI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G11C8
IPC codes: G11C8, H01L27, G11C11