Static memory

Abstract: A static memory in which polysilicon thin film transistors (Q4; Q6) serve as load elements in a memory cell, and the gate electrodes (16; 18) of the poly­ silicon thin film transistors (Q4; Q6) are formed of diffusion regions. In the static memory, high quality uniform TFTs are formed, and the oxidation films of the TFTs can be thin, without using a complex manufacturing technique.

Description: The invention relates to a static memory having the features a) - c) of claim 1 and disclosed in EP-A2-0 104 616. The channels of the driving MOS transistors are formed by island regions extending perpendicular and parallel to the channel lengths of the load transistors. The technical background of the invention will be briefly outlined hereinafter. In a static memory a polysilicon thin film transistor may be used as a load element of each memory cell. Recently, a static memory (SRAM), which has polysilicon thin film transistors (hereinafter abbreviated as TFTs) in place of high-resistance load elements constituted by a polysilicon layer, has been developed. The SRAM memory cell having a TFT is located between a complete CMOS memory cell and a memory cell having a high-resistance load element made of a polysilicon layer. Hence, this is a memory cell of the next generation having the advantages of both types of the memory cell. More particularly, the SRAM memory cell can be integrated as high as the latter, and consumes as low power in the static state and operates stably as the former. The equivalent circuit of the SRAM memory cell having TFTs is shown in Fig. 1. One ends of transfer gates Q1 and Q2 are respectively connected to bit lines BL and BL , and the other ends thereof, to memory nodes A and B, respectively. The gates of the transfer gates are connected to a word line WL. The drains of an n-channel MOS transistor Q3 and a p-channel TFT Q4 are connected to a memory node A. The gates of transistors Q3 and Q4 are connected to a memory node B. The source of the transistor Q3 is connected to the earth potential V SS , and the source of the transistor Q4 to the source potential V CC . Similarly, the drains of an n-channel MOS transistor Q5 and a p-channel TFT Q6 are connected to the memory node B. The gates of the transistors Q5 and Q6 are connected to the node A. The source of the transistor Q5 is connected to the earth potential V SS , and the source of the transistor Q6 to the source potential V CC . In the above-described memory cell, the transistors Q3 and Q4, and the transistors Q5 and Q6 respectively constitute complementary MOS inverters. The TFT is used as a load element for each of these complementary MOS inverters. Since the TFT serves as a transistor, when the TFT is in an OFF state, substantially no current flows in the memory cell, and when the TFT is in an ON state, a current flows which is much larger than in the case where the conventional high resistance load element is used in the memory cell. There are two types among the SRAM memory cells having TFTs as load elements. The first type is shown in Figs. 2A and 2B and the second type is shown in Figs. 3A and 3B. Fig. 2A is a pattern plan view showing a structure of the memory cell and Fig. 2B is a cross sectional view taken along line B-B′ of Fig. 2A. As these figures show, the SRAM cell comprises a p-type semiconductor region 51; a field insulating film 52; an n + diffusion region 53 serving as a source or drain region of the n-channel MOS transistor; a first polysilicon layer 54 serving as the gate electrode of the n-channel MOS transistor and the gate electrode of the p-channel TFT gate electrode; a second thin polysilicon layer 55 serving as a channel region and source and drain regions of the p-channel TFT; a channel region 56 of the TFT formed in the second polysilicon layer 55, to which substantially impurity concentration is low; a silicide layer 57 serving as an earth wiring; a silicide layer 58 serving as a main word line; an aluminum layer 59 serving as a first bit line BL; and an aluminum layer 60 serving as a second bit line BL . In the above-described structure, as shown in Figs. 2A and 2B, the channel of the n-channel MOS transistor extends in the same direction as that of the TFT. In other words, the channel regions of the n-channel MOS transistor and the TFT extend horizontally (Fig. 2A). In the TFT, since the channel, source and drain region are formed above the gate electrode, the source and drain regions cannot be self-aligned with the gate electrode, unlike in an ordinary MOS transistor in which the channel, source and drain regions are formed below the gate electrode. In particular, in manufacturing the TFT, it is impossible to use the gate electrode as a mask for forming a channel region, when ions are injected to form source and drain regions. For this reason, the channel length of a TFT must be longer and accordingly the memory size is larger than in an n-channel MOS transistor in which the source and drain regions can be formed in a self-aligning manner. To solve this drawback, offsets can be provided in the memory cell as shown in Figs. 2A and 2B. However, this method is disadvantageous because the allowance for alignment is small, resulting in difference in the characteristic of the TFTs. Therefore, the method is not of practical use to manufacture an SRAM memory cell. Fig. 3A is a pattern plan view showing a structure of the memory cell and Fig. 3B is a cross sectional view taken along the line C-C′ of Fig. 3A. As is illustrated in Figs. 3A and 3B, this SRAM memory cell comprises a p-type semiconductor region 71; a field insulating film 72; an n + -diffusion region 73 (not shown in Fig. 3A) serving as a source or drain region of the n-channel MOS transistor; a first polysilicon layer 74 serving as a gate electrode of the n-channel MOS transistor; a second polysilicon layer 75 serving as a gate electrode of a p-channel TFT; a third thin polysilicon layer 76 serving as a channel region and source and drain regions of the p-channel TFT; and a channel region 77 of the TFT formed in the third polysilicon layer 76, in which substantially impurity concentration is low and which is kept at a high resistance. The first polysilicon layer is used as both a word line WL and an earth wiring, and the third polysilicon layer is used as a wiring for conducting the source potential V CC . The n + -diffusion region is not shown in Fig. 3A. In the above-described structure, in addition to the gate electrode 74 of the n-channel MOS transistor, the gate electrode 75 of the TFT is formed above the n-channel MOS transistor. The third thin polysilicon layer 76 serving as the channel region and the source and drain regions of the TFT are formed thereon. The structure is similar to that of Figs. 2A and 2B in that the TFT cannot be formed in a self-aligning manner. However, it is different in that the channel of the TFT extends perpendicularly to that of the n-channel MOS transistor, as is clearly shown in Figs. 3A and 3B. In other words, the channel of the n-channel MOS transistor extends perpendicularly to the plane of Fig. 3B, whereas the channel of the TFT extends horizontally. For this reason, the channel length of the TFT can be sufficiently long regardless of the channel length of the n-channel MOS transistor, thus overcoming the drawback due to the small alignment allowance. However, as is shown in Fig. 3B, the structure is very complicated because of the three polysilicon layers. Moreover, one memory cell has seven contact holes to connect the polysilicon layers to one another, in addition to the contact holes connecting each of the polysilicon layers to the bit lines and the word lines. Further, the gate oxide film of the TFT must be formed of an interlayer film accumulated on the polysilicon layer. The accumulated film is inferior to a thermal oxide film in terms of the characteristics such as the number of pin holes, the withstanding voltage, and the uniformity. Also, it is difficult to form the film thin. The conventional SRAM memory cell shown in Fig. 2 has the following drawbacks: (1) the channel length of the TFT, which is not a self-aligning element, cannot be sufficiently long; (2) it is difficult to form a uniform TFT; and (3) since the interlayer accumulating film formed between the polysilicon layers is used as a gate oxide film of the TFT, it is difficult to form the accumulating film thin. The conventional SRAM memory cell shown in Fig. 3 has the following drawbacks: (1) a complicated manufacturing technique is required to form the memory cell because of the three-layers polysilicon structure; (2) seven contact holes are required for interconnection in the memory cell; and (3) since the interlayer accumulating film formed between the polysilicon layers is used as a gate oxide film of the TFT, it is difficult to form the accumulating film thin. This invention has been made in consideration of the above drawbacks of the prior art, and its object is to provide a static memory, in which uniform TFTs having good characteristic are formed, a gate oxide film of the TFT can be thin, with a simple manufacturing technique. In the static memory of this invention a polysilicon thin film transistor is used as a load element in a memory cell, and the gate electrode of the polysilicon thin film transistor is constituted by a diffusion region. The static memory of this invention has the features indicated in claim 1. Preferred embodiments of the invention are indicated in the dependent claims. According to the present invention, since the gate electrodes of the polysilicon thin film transistor is formed of diffusion regions, the structure of the memory cell, which has two polysilicon layers, is similar to the conventional static memory having high-resistant load elements made of polysilicon layers. As a result, the process of manufacturing the memory of this invention is compatible with that of the conventional memory. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing an equivalent circuit of a memory cell having TFTs; Fig. 2A is a pattern plan view showing a structure of the conventional memory cell; Fig. 2B is a cross sectional view taken along the line B-B' shown in Fig. 2A; Fig. 3A is a pattern plan view showing a structure of another conventional memory cell; Fig. 3B is a cross sectional view taken along the line C-C' shown in Fig. 3A; Fig. 4A is a pattern plan view showing a structure of the memory cell used in a static memory of the present invention; Fig. 4B is a cross sectional view taken along the line A-A′ shown in Fig. 4A; Fig. 4C is a cross sectional view taken along the line B-B′ shown in Fig. 4A; and Fig. 4D is an enlarged plan view showing a part of the pattern shown in Fig. 4A. There will now be described an embodiment of this invention with reference to the accompanying drawings. Figs. 4A to 4D show an SRAM memory cell used in a static memory according to the present invention. Fig. 4A is a plan view showing a pattern of the memory cell; Fig. 4B is a cross sectional view taken along the line A-A′ shown in Fig. 4A; Fig. 4C is a cross sectional view taken along the line B-B′ shown in Fig. 4A; and Fig. 4D is an enlarged plan view showing a part of the pattern shown in Fig. 4A. The equivalent circuit of the memory cell is the same as that shown in Fig. 1. The memory cell shown in Figs. 4A and 4B comprises a p-type semiconductor region 11; a field insulating film 12; an n + diffusion region 13 serving as a source or drain region of the n-channel MOS transistor Q1; an n + diffusion region 14 serving as a drain or source region of the n-channel MOS transistor Q1; an n + diffusion region 15 serving as a source or drain region of the n-channel MOS transistor Q2; an n + diffusion region 16 serving as a drain or source region of the n-channel MOS transistor Q2 and also serving as a drain region of the n-channel MOS transistor Q5; an n + diffusion region 17 serving as a source region of the n-channel MOS transistor Q5; an n + diffusion region 18 serving as a drain region of the n-channel MOS transistor Q3; an n + diffusion region 19 serving as a source region of the n-channel MOS transistor Q3; gate electrodes 20 of the n-channel MOS transistors Q1 and Q2 formed of a first polysilicon layer; a gate electrode 21 of the n-channel MOS transistor Q5 formed of the first polysilicon layer; a gate electrode 22 of the n-channel MOS transistor Q3 formed of the first polysilicon layer; a second polysilicon layer 23 of about 200 Å thick, for example; a CVD oxide film 24 formed on the second polysilicon layer 23; a BPSG film 25 formed on the CVD oxide film 24; a CVD oxide film 26 formed on the BPSG film 25; a BPSG film 27 formed on the CVD oxide film 26; and bit lines 28 and 29, made of aluminum film, formed on the BPSG film 27. The above-mentioned CVD oxide film 24, BPSG film 25, CVD oxide film 26, and BPSG film 27 are accumulated surface protecting films. However, any other surface protecting films can be used in place of these films. One of the bit lines, 28 is connected to the n + diffusion region 13 through a contact hole 30, and the other bit line 29 is connected to the n + diffusion region 15 through a contact hole 31. The n + diffusion region 14 and the gate electrode 21 of the n-channel MOS transistor Q5 are connected through a contact hole 32, and the gate electrode 21 and the second polysilicon layer 23 are connected through a contact hole 33. The n + diffusion region 16 and the gate electrode 22 of the n-channel MOS transistor Q3 are connected through a contact hole 34, and the gate electrode 22 and the second polysilicon layer 23 are connected through a contact hole 35. Further, the n + diffusion region 18 serving as a drain region of the n-channel MOS transistor Q3 and the gate electrode 21 of the n-channel MOS transistor Q5 are connected through a contact hole 36. P-type impurities are introduced into most part of the second polysilicon layer 23, making the layer low resistive. However, substantially no impurities are introduced into a region 37 of the polysilicon layer 23, which faces the n + diffusion region 16, maintaining the region 37 high resistive. As shown in Fig. 4C, which is a cross sectional view taken along the line B-B′ of Fig. 4A, the region 37 serves as a channel region of the TFT Q4. The region 37 is superimposed on the n + diffusion region 16 with a thermal oxide film 38 interposed therebetween, which is formed by thermal-oxidizing the n + diffusion region 16. Similarly, substantially no impurities are introduced into a region 39 of the polysilicon layer 23, which faces the n + diffusion region 18, thus maintaining the region 39 high resistive. The region 39 serves as a channel region of the TFT Q6, and is superimposed on the n + diffusion region 18 with a thermal oxide film (not shown) interposed therebetween, which is formed by thermal-oxidizing the n + diffusion region 18. In the memory cell thus arranged, the n + diffusion regions 18 and 16 respectively serving as drain regions of n-channel MOS transistors Q5 and Q3 are also used as the gate electrodes of the TFTs Q4 and Q6. Fig. 4D is an enlarged view showing the TFT Q4 and the n-channel MOS transistor Q5 shown in Fig. 4A. The gates of the TFTs Q4 and Q6 extend perpendicularly to those of the n-channel MOS transistors Q5 an Q3. More particularly, the gates of the TFTs Q4 and Q6 extend in the horizontal direction, and the gates of the transistors Q5 and Q3 extend in the longitudinal direction in the drawing (Fig. 4A). As has been described above, the channel regions of the TFT Q4 and Q6 are respectively constituted by the regions 37 and 39 of the polysilicon layer 23, each having a low impurity concentration. In addition, the gate electrodes are constituted by the n + diffusion regions and face the channel regions with the thermal oxide film inperposed therebetween. For this reason, the TFTs Q4 and Q6 cannot be formed in the self-aligning manner. However, the channel length can be determined at a desired value. Thus, the channels of the TFTs Q4 and Q6 can be formed sufficiently long without increasing the size of the memory cell. Moreover, the gate oxide films of the TFTs Q4 and Q6 are formed of thermal oxidation film superior in characteristic, e.g., the number of pin holes, the withstanding voltage, and the uniformity. Hence, a thin and high quality gate oxide film can be formed without a special technique, and thus the difficulty in the manufacturing process can be overcome. In addition, the memory cell of the above-described embodiment has a two-polysilicon layers structure, which is the same as in the conventional SRAM memory cell of a high-resistant load type. For this reason, the manufacturing process of the memory cell of the invention is similar to that of the conventional SRAM, having high compatibility with the conventional process. Further, the memory cell of the present invention has only five contact holes. Thus, in the memory cell of the above-described embodiment, high quality and uniform TFTs are formed, the gate oxide film of the TFT can be formed thin, not requiring a complicated manufacturing technique. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A static memory, comprising: a) a semiconductor substrate (11); b) first and second driving MOS transistors (Q3;Q5) of a first channel conductivity type, each (Q3;Q5) having source and drain regions (19,18;17,16) and a gate electrode (22;21), the source and drain regions (19,18;17,16) of said first and second driving MOS transistors (Q3;Q5) being formed in said semiconductor substrate (11); and c) third and fourth load MOS transistors (Q4;Q6) of a second channel conductivity type, each (Q4;Q6) having source and drain regions (23,23;23,23) and a gate electrode (16,18), the source and drain regions (23,23;23,23) of said third and fourth load MOS transistors (Q4;Q6) being formed in a polysilicon thin film, the gate electrodes (16;18) thereof comprising diffusion regions in said semiconductor substance (11); characterised in that d) the entire channel lengths of said first and second driving MOS transistors (Q3;Q5) are substantially perpendicular to channel lengths of said third and fourth load MOS transistors (Q4;Q6). The static memory according to claim 1, characterized in that said source and drain regions (18,19;16,17) of said first and second driving MOS transistors (Q3;Q5) comprise diffusion regions formed in said semiconductor substrate (11), said drain regions (18;16) of said first and second driving MOS transistors (Q3;Q5) respectively comprising said gate electrodes (16;18) of said third and fourth load MOS transistors (Q4;Q6). A static memory according to claim 1, characterized in that a) the drain (18) of said first driving MOS transistor (Q3) is connected to a first memory node (A), the source (19) of said first transistor (Q3) is connected to a first reference potential (V ss ), and the gate electrode (22) of said first transistor (Q3) is connected to a second memory node (B) ; b) the drain (16) of said second driving MOS transistor (Q5) is connected to said second memory node (B), the source (17) of said second transistor (Q5) is connected to said first reference potential (V ss ), and the gate electrode (21) of said second transistor (Q5) is connected to said first memory node (A); c) said third MOS transistor (Q4) has its gate electrode (16) formed of the drain diffusion region (16) of said second transistor (Q5); the source (23) of said third transistor (Q4) is connected to a second reference potential (Vcc), and the drain (23) thereof is connected to said first memory node (A); and d) said fourth MOS transistor (Q6) has its gate electrode (18) formed of the drain diffusion region (18) of said first driving MOS transistor (Q3) ; the source (23) of said fourth transistor (Q6) is connected to said second reference potential (Vcc), and the drain (23) thereof is connected to said second memory node (B). A static memory according to claim 2, characterized in that gate insulating films (38;38) adjacent the gate electrodes (16,18) of said third and fourth MOS transistors (Q4;Q6) are formed of thermally-grown films formed on said drain diffusion regions (23;23) of said second and first driving MOS transistors (Q5;Q3), respectively.

Inventors: OCHII KIYOFUMI, OCHII, KIYOFUMI, OCHII, KIYOFUMI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, G11C11, H01L21