A nonvolatile semiconductor memory device and a method of manufacturing thereof

Abstract: A nonvolatile semiconductor memory device having memory cells in which a control gate (CG) is stacked on a floating gate (FG) through an insulating film. The memory device has redundant memory cells so as to compensate defective memory cells and a transistor to select the redundant memory cells and the redundant memory cells and the transistor to select the redundant memory cells are formed by a nonvolatile memory transistor. The transistor to select the redundant memory cells has a structure in which the upper surface and side walls of a floating gate are covered by a control gate or a structure in which the floating gate and control gate are covered by a light shielding film and an antireflection film formed under the light shielding film. In a nonvolatile semiconductor memory device having memory cells of a structure in which a control gate is stacked on a floating gate through an insulating film, a phospho-­ silicate glass film is formed on side walls of the floating gate and the control gate and a silicon nitride film and an arseno-silicate glass film or boro-phospho-silicide glass film are sequentially formed so as to cover the control gate. A method of manufacturing a nonvolatile semiconductor memory device of a structure in which a control gate is stacked on a floating gate through an insulating film, comprises the steps of: forming the floating gate made of a semiconductor layer and the control gate made of a layer containing a refractory metal which is stacked on the floating gate; covering the floating gate and the control gate by a film which prevents a diffusion of metal atoms and transmits oxygen; and forming a semiconductor oxide film on side walls of at least the floating gate by executing a thermal oxidation.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the device. Description of Related Art Hitherto, as one kind of nonvolatile semiconductor memory device, an ultraviolet erasable EPROM (Erasable and programmable Read Only Memory) has been known which has a capacity that is gradually becoming greater. However, when the capacity of an EPROM increases, defective bits can occur due to problems of manufacturing which, results in the deterioration in the yield of EPROMs. Therefore, for EPROMs which have a large capacity, generally, redundant bits so as to compensate for defective bits and a redundant bit programming circuit so as to select the redundant bits are provided in the memory device, and the defective bits are replaced by redundant bits to compensate for the defective bits. In this case, the redundant bit programming circuit is ordinarily constructed with EPROM memory transistors. However, when data in the EPROM itself is erased, ultraviolet rays are also irradiated onto the redundant bit programming circuit. Therefore, to prevent the data written in the redundant bit programming circuit from being erased by the irradiation of the ultraviolet rays, it is necessary to take countermeasures so as not to irradiate the ultraviolet rays onto the EPROM memory transistors of the redundant bit programming circuit. Hitherto, as a countermeasure for such purpose, in general, the upper portion of the EPROM memory transistors for the redundant bit programming circuit has been covered by a first layer of aluminum (Al) film which form wirings so as to thereby shield the upper portion from light. However, even when the EPROM memory transistors for the redundant bit programming circuit are shielded from light by a first layer of Al film as mentioned above, the following problems still exist. First, since the space between the first layer of Al film and a semiconductor substrate is fairly large, the ultraviolet rays which entered from the portions which are not shielded from the light by the Al film cause a multiple reflection between the surface of the semiconductor substrate and the lower surface of the Al film, so that the ultraviolet rays easily enter the EPROM memory transistors under the Al film. Second, it is necessary to form Al wirings for the source region, drain region, and control gate, and since it is necessary to maintain certain distances between the Al wirings, when the ultraviolet rays are irradiated, the ultraviolet rays enter from the regions between the Al wirings. To prevent this, it is necessary to change the shapes of the source region, drain region, and control gate, so that the area for the EPROM memory transistors for the redundant bit programming circuit becomes large. Moreover, in spite of such a large area structure, it is difficult to sufficiently suppress the irradiation of the ultraviolet rays to the EPROM memory transistors for the redundant bit programming circuit. US-A-4805138 discloses an electrically programmable memory cell of a type having a source, a drain, a floating gate and a control gate formed over a semiconductor substrate, i.e. a memory transistor. Such memory transistors rely on avalanche injection of electrons to an electrically isolated floating gate in order to program the device. The charge stored on this floating gate may be removed by exposing it to UV light. In order to achieve a so-called nonvolatile memory transistor, i.e. a transistor the programmed condition of which is unaffected by UV light, this reference discloses a metal shield completely encapsulating the memory transistor down to the surface of the substrate. Electrical interconnections between metal contacts and the source, drain and control gate regions, respectively, are formed by coupling regions within the substrate. EP-A-0227549 discloses in its introductory part an electrically programmable memory comprising first memory cells and second memory cells the cell transistors thereof being of the floating gate type. Said second memory cells are for storing addresses of malfunctional first memory cells. The second memory cells are covered by a light shield layer of, for example, aluminium to prevent them from being erased by ultraviolet light. OBJECTS AND SUMMARY OF THE INVENTION It is, therefore, an object of the invention to provide a nonvolatile semiconductor memory device which can improve the ultraviolet erasure resistance characteristics of a transistor to select redundant memory cells. According to an aspect of the invention, there is provided a nonvolatile semiconductor memory device having the features of appended claim 1. The control gate is formed by a material which does not transmit ultraviolet rays such as a polycrystalline silicon film, a polycide film or the like. The above, and other, objects, features and advantages of the present invention will become readily apparent from the following detailed description thereof which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross sectional view showing an ultraviolet erasable EPROM according to a first embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the invention will be described hereinbelow with reference to the drawings. FIG. 1 shows an ultraviolet erasable EPROM according to the first embodiment of the invention. As shown in FIG. 1, in the ultraviolet erasable EPROM according to the first embodiment, a field insulating film 2 such as an SiO 2 film is formed on the surface of a p-type Si substrate 1, for instance, thereby accomplishing isolation between devices. A gate insulating film 3 such as an SiO 2 film is formed on the surface of the active region surrounded by the field insulating film 2. In the memory cell section and in the redundant bit section, a floating gate FG is formed on the gate insulating film 3. The floating gate FG is formed by an n + -type polycrystalline Si film in which impurities such as phosphorus (P) are doped. Reference numeral 4 denotes an insulating film such as a SiO 2 film, a SiO 2 /silicon nitride (Si 3 N 4 )SiO 2 film (ONO film) or a NO film. A control gate CG is stacked on the floating gate FG above the insulating film 4. The control gate CG is formed by, for instance, an n + -type polycrystalline Si film, a polycide film in which a refractory metal silicide film such as a WSi 2 film is formed on the n + -type polycrystalline Si film, or the like. On the other hand, in this case, the floating gate FG And control gate CG are forred in a self-aligned manner with respect to the direction of the channel length. Reference numeral 5 shows an insulating film such as an SiO 2 film. On the other hand, a source region 6 and a drain region 7 of, for example, n + -type are formed in the p-type Si substrate 1 in a self-aligned manner with respect to the floating gate FG and control gate CG. An EPROM memory transistor is formed by the floating gate FG, control gate CG, source region 6, and drain region 7. A memory cell and a redundant bit (redundant memory cell) are formed by the EPROM memory transistor. In the redundant bit programming circuit section, a floating gate FG′ is formed on the gate insulating film 3. The floating gate FG′ is formed by, e.g., an n + -type polycrystalline Si film similarly to the floating gate FG. A control gate CG′ is stacked on the floating gate FG′ through the insulating film 4. The control gate CG′ is formed by an n + -type polycrystalline Si film, a polycide film, or the like which does not transmit ultraviolet rays. In this case, the control gate CG′ is formed so as to cover the floating gate FG′, so that the upper surface and side walls of the floating gate FG′ are covered by the control gate CG′. On the other hand, a source region 8 and a drain region 9 of, for example, the n + -type are formed in the p-type Si substrate 1 in a self-aligned manner with respect to the control gate CG′. An EPROM memory transistor is formed by the floating gate FG′, control gate CG′, source region 8, and drain region 9. A redundant bit programming circuit is formed by the EPROM memory transistor. Reference numeral 10 denotes an interlayer insulating film such as a PSG film. An example of a method of manufacturing the ultraviolet erasable EPROM according to the first embodiment constructed as mentioned above will now be described. As shown in FIG. 1, after the isolation between devices is executed by forming the field insulating film 2 by selectively thermally oxidizing the surface of the p-type Si substrate 1, the gate insulating film 3 is formed on the surface of the active region which is surrounded by the field insulating film 2 by a thermal oxidation method. Then, after forming a polycrystalline Si film which forms the floating gate over the whole surface by, e.g., a CVD method, n-type impurities such as P are doped onto the polycrystalline Si film at a high concentration, thereby forming an n + -type polycrystalline Si film. After that the n + -type polycrystalline Si film is patterned by etching. In the memory cell section and in the redundant bit section, the n + -type polycrystalline Si film is set to a predetermined width in the direction perpendicular to a cross section shown in FIG. 1. In the redundant bit programming circuit section, the n + -type polycrystalline Si film is patterned like an island. Then the insulating film 4 is formed on the n + -type polycrystalline Si film by, e.g., the thermal oxidation method. Subsequently, then a polycrystalline Si film so as to form the control gate is formed onto the whole surface by, e.g., the CVD method, n-type impurities are doped into the polycrystalline Si film in a manner similar to the above described method thereby forming an n + -type polycrystalline Si film. Then a resist pattern (not shown) of the shape corresponding to the control gate CG is formed on the n + -type polycrystalline Si film in the memory cell section and in the redundant bit section. On the other hand, a resist pattern (not shown) of the shape corresponding to the control gate CG' is formed on the n + -type polycrystalline Si film in the redundant bit programming circuit section. Then, by using those resist patterns as masks, the n + -type polycrystalline Si film to form the control gate, the insulating film 4, and the n + -type polycrystalline Si film to form the floating gate are anisotropically etched in the direction perpendicular to the surface of the substrate by, e.g., a reactive ion etching (RIE) method. Due to this, as shown in FIG. 1, in the memory cell section and redundant bit section, the floating gate FG and control gate CG have the same width and are formed in a self-aligned manner. On the other hand, in the redundant bit programming circuit section, the control gate CG' which has a larger width than the floating gate FG' is formed. Then, after the resist patterns are removed, the insulating film 5 is formed by, e.g., the thermal oxidation method. Subsequently, by using the control gates CG and CG' and the floating gates FG as masks, n-type impurities such as arsenic (As) are ion implanted into the p-type Si substrate 1 at a high concentration. Due to this, in the memory cell section and in the redundant bit section, the n + -type source region 6 and drain region 7 are formed in the p-type Si substrate 1 in a self-aligned manner with respect to the floating gate FG and control gate CG. On the other hand, in the redundant bit programming circuit section, the n + -type source region 8 and drain region 9 are formed in the p-type Si substrate 1 in a self-aligned manner with respect to the control gate CG'. Then, the interlayer insulating film 10 is formed on the whole surface by, e.g., the CVD method. Then, an objective EPROM is completed using steps of forming contact holes and Al wirings (not shown) and the like. As mentioned above, according to the first embodiment, since the memory has a structure in which the floating gate FG' of the EPROM memory transistor which forms the redundant bit programming circuit is covered by the control gate CG' made of a material which does not transmit ultraviolet rays, when ultraviolet rays are irradiated to the EPROM to erase data in the memory cell section, in the redundant bit programming circuit, the ultraviolet rays will be prevented from irradiating the floating gate FG' due to the control gate CG'. Thus, the ultraviolet erasure resistance characteristics of the redundant bit programming circuit are improved and it is possible to prevent data in the redundant bit programming circuit from being erased by irradiation of the ultraviolet rays. On the other hand, the memory cells and redundant bits (redundant memory cells) are constructed by the EPROM memory transistors in a small area. Therefore, in the memory cell section and redundant bit section, the EPROM memory transistors can be formed at a high integration density and the write/erase characteristics are good. On the other hand, the area of EPROM memory transistor of the redundant bit programming circuit section increases by an amount corresponding to the increased area of the control gate CG' and the write characteristics are also inferior to those of the EPROM memory transistors in the memory cell section and in the redundant bit section. However, since the number of EPROM memory transistors in the redundant bit programming circuit section is ordinarily so small so as to be about ten to a hundred and the programming is executed on a tester, such drawbacks actually do not cause any problems. As shown in FIG. 1, in the above first embodiment, it is also possible to use a structure in which semiconductor regions 13 and 14 of low impurity concentrations of, for example, n-type are formed between the source region 8 and the floating gate FG' and between the drawing region 9 and the floating gate FG', respectively.

Claims: A nonvolatile semiconductor memory device having memory cells each comprising a first floating gate transistor in which a control gate is stacked on a floating gate through an insulating film; a plurality of redundant ones of said memory cells for compensating detective ones of said memory cells; and a plurality of second floating gate transistors for selecting said redundant memory cells, each second floating gate transistor having a control gate stacked on a floating gate through an insulating film, the floating gate being shielded from light; characterised in that each second floating gate transistor for selecting said redundant memory cells has a structure in which the upper and side walls of the floating gate are covered by the control gate. A nonvolatile semiconductor memory device according to claim 1, wherein a redundant bit programming circuit is formed by said transistors for selecting said redundant memory cells. A nonvolatile semiconductor memory device according to claims 1 or 2, wherein each control gate of said transistors for selecting said redundant memory cells is formed of a polycrystalline silicon film or a polycide film.

Inventors: NAKAMURA AKIHIRO, NODA MASANORI, NAKAMURA, AKIHIRO, NODA, MASANORI, NAKAMURA, AKIHIRO C/O SONY CORPORATION, NODA, MASANORI C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L27