Signal processing method and system.

Abstract: A method of and system for processing a digital signal are disclosed. Disclosed also are an electric power system digital controlling system and a digital relay system which utilize the signal processing system for obtaining physical quantities of a voltage and a current inputted from the electric power system. An analog signal is sample-held. The sample-held data is converted into digital data which is then filtering-processed. Arithmetic processing is effected based on the data from a digital filter means. In this digital filter means, a blocking zone of the digital filter is set to a higher frequency zone than a passage zone of the analog signal. A sampling frequency is set so that a noise generating region is larger than the blocking zone. The synthesis noises are thereby caused in the blocking zone.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed generally to a digital signal processing method and system, and more particularly, to a digital signal processing method and system suited to convert AC signals of an electric power system into digital signals and detect an electric quantity of the AC signals from the converted digital signals. This invention also relates generally to a signal processing system for obtaining a physical quantity of effective values of input signals of voltages and currents which are inputted from an electric power system, an electric power system digital control system and a digital relay system which utilize this signal processing system, and more particularly, to those suitable for digital signal processing to digitally converting the input signals. 2. Description of the Prior Art As disclosed in Japanese Patent Laid-Open Publication N0.121420/1988 or stated from p.12 onwards in "A Report of the Electric Engineering Association", No.12, Vol.105, Japan, 1985, a known convectional system of this type is employed for an electric power system digital protective relay. This type of system comprises an input unit, processing unit, a settling unit and an output unit. Incorporated into this input unit is a digital signal processor including an analog filter for eliminating high frequencies, a sample hold circuit, a multiplexer, and A/D converter and a buffer. This system adopts the following construction. Higher harmonic components overlapped with fundamental harmonics are eliminated from analog input signals by means of the analog filter. Output signals of the analog filter are sampled with a period of 600 Hz, thereby converting the analog signals into digital signals. Impedances or magnitudes of a voltage or current of the electric power system are obtained from the digital signals. The relay is thus operated. Based on the conventional techniques given above, the analog filter is capable of eliminating the higher harmonic components overlapped with the analog input signals and disturbance noises as well. No consideration is, however, given to noises caused in the portions subsequent to the analog filter, such noises including, e.g., the disturbance noises and those incidental to errors in quantization of the A/D converter. This in turn causes a disadvantage of generating an error in arithmetic value of digital data due to those noises. The following is a description in greater detail. A sampling frequency is set at 600 Hz. In a frequency region, the noises are produced concomitantly with the quantization errors and the disturbance noises when effecting sampling. This frequency region is overlapped with a passage zone (frequency region of analog input signal) of the analog filter. In consequence, the analog input signals can not be separated from the noises concomitant with the disturbance noises and the quantization errors. It follows that these noises cause arithmetic errors. For this reason, it is impossible to sufficiently enhance a performance of resolving power of the A/D converter. Known as an electric power control system which utilizes this type of system is a voltage/reactive power control system stated on pp.1200-1201 in a report of "The 946th National Meeting of The Electric Engineering Association" in 1987. When driving this type of electric power control system, a common practice is detection of effective values of the AC signals of the electric power system. On the occasion of the detection of effective values of the AC signals, the following method has hitherto been adopted. The AC signals are inputted to the filter for attenuating the higher harmonic components thereof. A frequency of the AC signal is detected from an output signals of the filter. A gain of the output signal of the filter is corrected based on the detected frequency. On the basis of the corrected signal, the effective value of the AC signal is calculated. According to this method, even when the frequency of the AC signal fluctuates, the gain is corrected to keep the filter output signal at a constant level. It is therefore possible to obtain the effective values corresponding to the fluctuations in frequency. There arise, however, the following problems inherent in the prior art. Sufficient concerns are, as will be explained later, not paid to characteristics of the input filter. If the frequency of the AC signal fluctuates, the electric quantity of the AC signals can not accurately be obtained in some cases. (1) Since the input filter is composed of an analog filter, there are caused a scatter in elements, a deterioration in property due to a change with a passage of time and an inter-channel scatter. (2) The input signal is sampled at 600 Hz (or 720 Hz: electrical angle of 30° of fundamental harmonic). It is therefore required that an intricate algorithm be executed to obtain the frequency with a high accuracy. Besides, a multiplicity of arithmetic units are required to be added. (3) A gain characteristic of the input filter is fixed. Hence, when the frequency of the input signal fluctuates, it is also required that the gain be corrected. (4) When the frequency of the AC signal fluctuates, the fundamental harmonic of the fluctuated AC signal can not sufficiently be attenuated. This results in an increase in detection error of the effective value. SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal processing method and a system to which this method is applied, the method and the system being capable of enhancing an arithmetic accuracy of digital data by separating noises incidental to quantization errors and disturbance noises from analog input signals. This object is met by the method of claim 1 and the system of claim 7. Preferred embodiments are disclosed in the depending claims. To accomplish the foregoing objects, according to one aspect of the present invention, there is provided a method of processing a digital signal, comprising the steps of: converting an analog signal into a digital signal after sampling the analog signal; effecting a filtering process on the digital data by use of a digital filter; setting a blocking zone of the digital filter to a higher frequency zone than a passage zone of the analog signal when arithmetically processing the filtering-processed digital data; and setting a sampling frequency so that a region in which noises are caused due to disturbance noises and a quantization error becomes larger than the blocking zone of the digital filter. Based on this method adopted therein, a 1/N frequency (N: the integer greater than 2) of the sampling frequency is set to a zero point frequency of the digital filter. The attenuation characteristics and the zero point frequency of the digital filter are settable in accordance with actually measured values of the noises incidental to the quantization error and the disturbance noises. Besides, the noise generating region associated with the disturbance noises and the quantization error and its magnitude are arithmetically obtained, and the zero point frequency and the attenuation characteristics of the digital filter are settable based on these arithmetic results. To accomplish the foregoing objects, according to another aspect of the present invention, there is provided a system for processing a digital signal, comprising: a sample hold means for sample-holding an analog signal; an analog-to-digital converting means for converting the data held by the sample hold means into digital data; a digital filter means for effecting a filtering process on the digital data outputted from the analog-to-digital converting means; and a digital processing means for executing arithmetic processing on the basis of the digital data outputted from then digital filter means, characterized by the digital filter means in which a blocking zone of the digital filter is set to a higher frequency zone than a passage zone of the analog signal, and a sampling frequency of the sample hold means is set so that a noise generating region associated with disturbance noises and a quantization error becomes larger than the blocking zone of the digital filter means. Based on the system thus constructed, a zero point frequency of the digital filter means is set to a 1/N frequency (N; the integer greater than 2) of the sampling frequency. Adopted is the digital signal processing system in which the zero point frequency of the digital filter means is set to a 1/N frequency (N: the integer greater than 2) of the sampling frequency. According to the present invention having the above-described constructions, the foregoing objects are fulfilled by the following action. Namely, the analog signal undergoes sampling and A/D conversion, whereby the analog signal becomes a discrete signal having the 1/N frequency (N: integer greater than 2) of the sampling signal. For this reason, if sampling is performed at a high velocity, the frequencies of the synthesis noises including the disturbance noises and those incidental to the quantization error can be increased. Hence, the sampling frequency is set so that the synthesis noise generating region is larger than the blocking zone of the digital filter. As a result, the synthesis noises can be produced in the blocking zone of the digital filter. The blocking zone of the digital filter is set in a higher frequency zone than the passage zone of the analog signal. The synthesis noises can thereby be removed. This in turn makes it possible to increase the S/N ratio of the digital data. The highly accurate data can be also obtained. When setting the attenuation characteristics of the digital data, the zero point frequency of the digital filter is set to the 1/N frequency of the sampling frequency. The synthesis noises can remarkably be reduced. The noise components and the frequency components of the noises concomitant with the quantization error are caused at random. The attenuation characteristics of the digital filter are set from the results of analyzing the frequencies. It is therefore feasible to decrease the errors, corresponding to the state where the noises are generated. The analog signal is sampled with the period smaller than the arithmetic period of digital arithmetic processing. The errors can considerably be reduced. The resolving power greater than that of the A/D converting means can be obtained. The frequency of the AC signal is detected from the output signal of the digital filter. The gain characteristic of the digital filter is adjusted in accordance with the detected frequency. Consequently, even when the frequency of the AC signal fluctuates, the higher harmonics of the AC signals can invariably be eliminated. The precise electric quantity of the AC signals can be also acquired from the output signals of the digital filter. Besides, even if the gain characteristic of the input filter is not constant with respect to the frequency, the physical quantity gain of the effective value obtained from the AC signal or the filtering-processed AC signal is corrected by the gain correcting means on the basis of the frequency-gain characteristics. The physical quantity obtained increases in accuracy. The effective value is procured from the gain-corrected peak value, and hence the detection accuracy is further improved. In this case, fast sampling is effected with the period which is 1/24 or under of the fundamental frequency of the AC signal. With this arrangement, the zero-cross point relative to the frequency detection can be detected with the high accuracy. The frequency associated with the gain correction is also detectable with the high accuracy. As a result, the gain is corrected accurately. The sampling process is carried out at the high speed. Hence, the peak value is acquired simply by making a comparison with the absolute value of the input AC signal. In this case, where the digital signal processor is employed for calculating the peak value, the intricate numerical calculations can be executed at the high velocity. The peak value is arithmetically obtained from the data of several samples. When the digital input filter is constructed by use of the digital signal processor, the problems inherent in the above-mentioned analog filter can be obviated. Besides, highly accurate and stable filter characteristics are easily attainable for the plurality of channels. The characteristics, which could not be obtained by the analog filter, are procured. The frequency-gain characteristics of the digital input filter are so set that the gain is constant within the range of constant frequencies. As explained earlier, the necessity for the gain correction is eliminated. The peak value and the effective value can be acquired with the high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS Other object and advantages of the present invention will become apparent during the following discussion taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram showing one embodiment of the present invention; FIGS. 2A and 2B are diagrams showing characteristics of a digital filter depicted in FIG. 1; FIGS. 3A through 3E are waveform diagrams of assistance in explaining sampling methods both of the present invention and of the prior art; FIG. 4 is a block diagram illustrating another embodiment of this invention; FIGS. 5A and 5B are diagrams showing characteristics of the digital filter depicted in FIG. 4; FIG. 6 is a block diagram illustrating an IIR type filter; FIG. 7 is a block diagram illustrating an FIR type filter; FIG. 8 is a diagram showing an applied example of the IIR type filter; FIGS. 9A through 9C are diagrams showing characteristics of frequencies when using the filter illustrated in FIG. 8; FIGS. 10 and 11 are flowcharts of assistance in explaining the action when the present invention is applied to an adaptive filter; FIG. 12 is a block diagram depicting an electric power system control/protective system to which the present invention is applied; FIG. 13 is a flowchart of assistance in explaining the action exhibited in FIG. 12; FIG. 14 is a diagram showing phasic characteristics of the electric power system control/protective system; FIG. 15 is a flowchart of assistance in explaining the action of a reactance relay; FIG. 16 is a diagram showing operating waveforms corresponding to a flow of processing; FIG. 17 is a block diagram depicting an analog input unit of the electric power system control/protective system; FIG. 18 is a block diagram illustrating a DSP; FIGS. 19A and 19B are diagrams of assistance in explaining operation timings of the analog input unit; FIGS. 20A and 20B are diagrams showing phasic characteristics of the electric power system control/protective system to which the present invention is applied; FIG. 21 is a diagram showing a dynamic impedance of the reactance relay to which the present invention is applied; FIGS. 22A and 22B are diagrams showing phasic characteristics of a distance relay to which the present invention is applied; FIG. 23 is a block diagram showing a process of detecting voltage effective value of the electric power system to which the present invention is applied; FIG. 24 is a flowchart of assistance in explaining the action exhibited in FIG. 23; FIG. 25 is a diagram showing frequency characteristics of the system depicted in FIG. 23; FIG. 26 is a block diagram depicting a signal analyzer to which the present invention is applied; FIG. 27 is a block diagram depicting a voice signal processor to which the present invention is applied; FIG. 28 is a block diagram showing a digital data recorder to which the present invention is applied; FIGS. 29A and 29B are block diagrams illustrating a digital audio system to which the present invention is applied; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will hereinafter be described with reference to the accompanying drawings. Referring first to FIG. 1, a digital signal processing system is composed of a sample holder 101, an A/D converter 102, a digital filter 103 and a digital processing unit 104. An analog signal is inputted to the sample holder 101 from an analog sensor 100. The analog sensor 100 is constructed to convert data of a variety of analog quantities of, e.g., an electric current, a voltage, a speed, a pressure and a temperature into voltages. The analog signals of the analog sensor 100 are inputted to the sample holder 101. The sample holder 101 sample-holds these signals. The held data are then outputted to the A/D converter 102. The A/D converter 102 converts the input data into digital data. The thus converted data are outputted to the digital filter 103. The digital filter 103 effects filtering on the input data, thereby extracting data of a specified frequency component from a group of input data. The extracted data is outputted to the digital processing unit 104. Based on the input data, the digital processing unit 104 effects a variety of arithmetic operations. The processing unit 104 then outputs the arithmetic results. After making an attempt to measure the output signals of the analog sensor 100, as clarified from FIG. 3A, the signal components of the analog signals turned out to contain higher-order harmonic components. To be specific, the analog signals contain noises, so-called disturbance noises induced to a power supply as noise components. Such disturbance noises are also caused in an input of the A/D converter 102 as well as in an output of the sample holder 101. The analog signal is sampled at a sampling frequency fs = 600 Hz. A waveform at this time is illustrated in FIG. 3B. When analyzing the frequency, as shown in FIG. 3C, the noise is produced within a passage zone of the analog signal. It could be confirmed that this noise component is generated depending on a frequency that is 1/N (N is an integer larger than 2) as small as the sampling frequency fs. To cope with this, as illustrated in FIGS. 2A and 2B, in accordance with this embodiment, a blocking zone T2 of the digital filter 103 is set to have a frequency higher than in a passage zone T1 of the analog signal. Simultaneously, the sampling frequency fs of the sample holder 101 is so set that a noise generating region associated with a quantization error and the disturbance noises as well is larger than the blocking zone T2 of the digital filter 103. More specifically, where frequencies f1 - f2 are set in the passage zone, a frequency region f2 - 1/2 fs is set to serve as the blocking zone T2. In the case of setting characteristics of the digital filter 103, it is enough to allow for a portion that is less than one-half of the sampling frequency fs as a frequency region handled on the sampling theorem. Therefore, it follows that the frequency-gain characteristics are set to attenuate, e.g., a portion of the frequencies f2 - 1/2 fs. Based on the foregoing configuration, as illustrated in FIG. 3D, the analog signal is sampled at a sampling frequency fs = 3 kHz. In this case, as shown in FIG. 3E, synthesis noises 107 containing the disturbance noises and the noises incidental to the quantization error deviate from the passage zone T1. It was confirmed that the noises 107 are produced within the blocking zone T2 of the digital filter 103. Namely, the synthesis noises can be separated from the analog signal. This in turn makes it possible to process the digital signal with a high accuracy. An embodiment developed from the one shown in FIG. 1 will next be explained referring to FIG. 4. In this embodiment, a different component is a digital filter 200, and other components are the same as those in the previous embodiment. The same components are therefore marked with the like symbols, and the description thereof is omitted. The synthesis noises containing both the disturbance noises and the noises concomitant with the quantization error are generated depending on the 1/N frequency (N is the integer) of the sampling frequency fs. As illustrated in FIGS. 5A and 5B, zero point frequencies F1 - F6 of the digital filter 200 are set to match with the frequencies of noises 202. Owing to this setting, the noises can be more attenuated. In this case, all the frequencies, which are contained in the blocking zone T2 and are 1/N of the sampling frequency fs, are selected as the zero point frequencies of the digital filter 200. Alternatively, only the zero point frequencies assuming higher levels are selectable from actually measured values of the noise levels. The synthesis noises are produced at random. For this reason, the zero point frequencies can be set by predicting the frequencies at which a good deal of synthesis noises are caused. Besides, as will be mentioned later, the noise generating frequencies are detected. A configuration and characteristics of the digital filter 200 can be adaptively modified so that the detected frequencies become the zero point frequencies of the digital filter 200. Moreover, the A/D converter 102 is constructed to have a 12-bit resolving power. In this case, when employing the digital filter 200 exhibiting the characteristics shown in FIGS. 5A and 5B, it is feasible to obtain a resolving power greater than that of the A/D converter 102. The following is a description of an embodiment of the digital filter 200 with reference to FIGS. 6 and 7. FIGS. 6 and 7 each show a typical block conceptual configuration of the digital filter 200. FIG. 6 illustrates an IIR (Infinite-extent Impulse Response) type filter. FIG. 7 illustrates an FIR (Finite-extent Impulse Response) type filter. Turning to FIG. 6, when the degree is secondary, the filter consists of adder blocks 301 through 304, filter coefficient blocks 305 through 309, a delay block 310 for delaying a signal Wn by 1/T (T: period) and a delay block 311 for delaying a signal Wn-1 by 1/T. Input signals Xn are subjected to filtering to generate filter output data Yn. The signal Wn and the data Yn in the filter described above are expressed by the following arithmetic formulae (1) and (2): Wn = Xn + Wn-1 . B1 + Wn-2 . B2 Yn = Wn . A0 + Wn-1 . A1 + Wn-2 . A2 Based on the foregoing configuration, there are attainable a variety of filters expressed by the following formulae (3) to (7) by adjusting the filter coefficients 305 through 309: (low-pass filter) H(z) = 1-B 1 + B 2 . 4 (1+Z -1 ) 2 1-B1.Z -1 + B2.Z -2 (band-pass filter) H(z) = 1-B 2 2 . 1 - Z -2 1-B1.Z -1 + B2.Z -2 (high-pass filter) H(z) = 1 + B 1 + B 2 . 4 (1-Z -1 ) 2 1-B1.Z -1 + B2.Z -2 (notch filter) H(z) = 1 + B 2 2 . 1-r.Z -1 + Z -2 1-B1.Z-1 + B2.Z-2 where r = 2.cos2πfo.T T: sampling period fo: blocking frequency (all-pass filter) H(z) = Z -2 - B1.Z -1 + B2 1-B1.Z -1 + B2.Z -2 Note that z is the transfer function, and Z corresponds to s of the analog system (s = jw, z = e jw ) The filter depicted in FIG. 7 comprises adder blocks 320 and 321, filter coefficient blocks 322 to 324, a delay block for delaying an input signal X'n by 1/T and a delay block 326 for delaying a signal X'n-1 by 1/T. The input signals X'n are filtering-processed, and output data Y7n are thereby outputted. The input signal X'n in the thus constructed filter is given by the following arithmetic formula (8): X'n = A'0.A'n + A'1.X'n-1 + A'2.X'n-2 To obtain desired attenuation characteristics, the filter explained above is cascade-connected. When employing the filters given above, this embodiment adopts the following arrangement. As will be stated later, a digital filter means using a DSP (digital signal processor) performs filtering on the input signals. The arithmetic operation is repeatedly performed per sampling period on the basis of the predetermined filter coefficient. As a result, the time-division filtering process is effected softwarewise according to the number of input points. It is therefore possible to correspond to an increase or decrease in the number of input points, changes in characteristic and standardization of a printed board. Namely, if a signal system for 12 channels is needed, the analog filters for 12 channels are also required. When using the filter in this embodiment, however, the filter may be constructed softwarewise corresponding to the number of channels. Filtering is attainable by employing no analog filter. Hence, there exists absolutely no factor for an initial value deviation, as seen in the analog filter, of an element such as a resistor or capacitor, fluctuations in the element value due to the ambient temperatures and a deterioration of the element because of reductive changes. A higher performance can be attained, and any adjustment can be eliminated. Besides, an externally attached inspection circuit becomes unnecessary. It is feasible to correspond to the changes in characteristic by use of the internal software. In consequence, the manufacturing steps can remarkably be reduced, and the maintenance is also unnecessary. The following is an explanation of an embodiment where in error frequency components are detected, the configuration and characteristics of the digital filter 200 are modified to further reduce the errors. The explanation starts with touching on an example of changing the characteristics of the digital filter 200 with reference to FIG. 8. The digital filter 200 depicted in FIG. 8 is of an IIR type. The Filter 200 can be constructed depending entirely on the coefficients of the filter coefficient blocks 305, 307 and 309. For instance, the filter is configured as a low-pass filter. In this case, a coefficient A0 of the filter coefficient block 305 is set such as A0 = 1.0. In the filter coefficient block 307, a coefficient A1 = 2.0. In the filter coefficient block 309, a coefficient A2 = 1.0 For forming a notch filter in order to provide a zero point, the coefficients may be set as follows: A0 = 1, A2 = 2 cos wnT, and A2 = 1.0. (However, wn = 2 π fn, fn: zero point frequency). The filter characteristics-e.g., a central frequency f 0 and a selectivity Q-are attainable by modifying coefficients B1 and B2 of the filter coefficient block 306 to fulfill desired characteristics. FIGS. 9A to 9C show examples of frequency-gain characteristics of a low-pass filter 402, a band-pass filter 403 and a notch filter 403. Next, a processing content in the embodiment of FIG. 4 will be described in detail with reference to FIGS. 10 and 11. FIG. 10 shows an example where in an initial process indicated by a block 511, a frequency analysis of error is carried out; a filter coefficient to reduce the error is derived; and a normal process indicated by a block 512 is executed based on this filter coefficient. The following is a description of a specific content. At a step 500, the digital data are at first stored in a data memory. At this moment, initialization of clearing of the data memory and the like is effected. There is made a judgment as to whether or not the digital data are inputted from the A/D converter 102 (step 501). When inputting the digital data (step 502), whether n-pieces, e.g., 512 pieces of digital data are inputted or not is judged (step 503). Processes up to the steps 501 - 503 continue till the n-pieces of digital data are inputted. When the number of data reaches the value of n, a spectrum analysis about the data is carried out (step 504). This spectrum analysis is performed by use of FFT arithmetic (fast Fourier transform). Based on the spectrum analysis, the frequencies of noises generated in regions other than the passage zone T1 are detected. Thereafter, the filter coefficients are derived to make the detected frequencies match with the zero point frequencies of the digital filter 200 (step 505). To be specific, when setting the zero point frequencies by use of the notch filter, the filter coefficients can be obtained by the following equations (9) through (13): A0 = 1.0 A1 = 2 coswnT A2 = 1.0 B1 = 4Q coswoT 2Q + sinwoT B2 = 2Q sinwoT 2Q + sinwoT where wn: 2 fn wo: 2 fo fn: the zero point frequency fo: the cut-off frequency Q: the selectivity T: the sampling period The initial process is carried out to make zero the error generating frequency by use of the above-mentioned arithmetic formulae. At this stage, the characteristics and configuration of the filter are determined. Namely, a specific number of stages at which the filter is connected to the cascades is determined. As a matter of fact, the error generating frequency does not largely varies. Hence, even when setting the characteristics and configuration of the filter at the initial time,there is caused no problem in terms of practical use. Next, the action moves to a process of block 512. As an on-line process, whether there is a data input interrupt or not is judged (step 506). If the interrupt exists, the data are inputted (step 507). Subsequent to this step, the digital filtering process is executed by using the digital filter coefficients obtained at the initial time, thereby reducing the errors (step 508). The digital operation is performed based on the data in which the input data undergo filtering (step 509) The data pursuant to the arithmetic result are outputted (step 510). In the embodiment of FIG. 10, the frequency analysis of the error is effected at the initial time. The filter coefficients are set pursuant to the analytic result. A contrasting arrangement of an embodiment shown in FIG. 11 will be given. The error frequency analysis is performed per sampling. The filter coefficients are adaptively modified to constantly considerably reduce the error frequency components. The following is an explanation of a concrete example. To begin with, initial setting such as clearing of the data memory is executed (step 600). A judgment as to whether there is a data input interrupt or not is made (step 601). If the interrupt exists, the data are inputted (step 602). An on-line spectrum analysis is effected based on the input data (step 603). This spectrum analysis helps the error frequency analysis. In accordance with this analytic result, the digital filter coefficients are obtained to reduce the frequency components of the detected noises (step 604). Subsequently, after acquiring the filter coefficients, the input data undergo the filtering process (step 605). Next, the digital operation is carried out based on the filtering-processed data (step 606). This arithmetic result is outputted (step 607). A series of these operations are repeated per period T, thus calculating the digital data. In this embodiment, the configuration and characteristics of the filter are adaptively modified. It is therefore possible to decrease the noises corresponding to a situation where the noises are produced concomitantly with the quantization error and the disturbance noises caused at random. Besides, the highly accurate digital arithmetic process can be actualized. FIG. 12 illustrates a block construction where the digital signal processing system of this invention is applied to an electric power digital protective relay system. The system depicted in FIG. 12 incorporates protective relay processing functions allocated to nine kinds of units. The digital signal processing system of this invention is applied to an analog input unit 700 among these units. These units are a system control unit 605 for a multiprocessor system, the analog input unit 700 for performing an A/D conversion of the analog input and also a digital filtering process, a relay arithmetic unit 701, a sequence processing unit 702, a settle/display processing unit 706, a digital I/0 unit 703, an accident detecting unit 709, an auxiliary relay unit 704 and a surface panel unit 710. The units 700 to 702 and 704 to 706 are connected to each other via a general-purpose system bus B1. The sequence processing unit is connected to the digital I/0 unit 703 via an I/0 bus B2 different from the system bus B1. A relay arithmetic part 707 and a sequence processing part 708 within the accident detecting unit 709 are connected to each other through an I/0 bus B3 different from the buses B1 and B2. Note that the system incorporates a power supply unit by which the respective units are driven. Next, an outline of the electric power digital protective relay system will be explained with reference to FIGS. 13 through 16. At a step 2001, the electric power system information on, e.g., a voltage and current of a transmission line is inputted. Furthermore, an analog quantity is converted into a digital quantity. At a step 2002, an electric quantity for detecting or controlling an accident is derived. The derivation of the electric quantity includes magnitudes of the voltage and current in the event of the accident in the electric power system, an impedance Z, a resistance R and a reactance X up to the point of time when causing the accident, an accident direction and further an accident frequency. At a step 2003, the electric quantity derived at the step 2002 is compared with a predetermined settled value to given a comparative judgment. As a result of the comparative judgment, if judged as an accident, the action moves to a step 2004. At the step 2004, whether the accident conditions judged at the step 2003 continue or not is judged. If the conditions continue, the action moves to a step 2005. At the step 2005, the information is stored because of the judgment as the accident. At a step 2006, system sequence processing (including a combination of a timer with external conditions) is carried out based on a variety of relay operations stored at the step 2005. In the case of the judgment as the accident, a cut-off instruction to a circuit breaker is issued. At a step 2007, the system is inspected and monitored. The electric power digital control protective system repeatedly executes the above-mentioned processes during a period that is n-times (n is the integer) as large as the sampling period T of the analog input. FIG. 14 shows an example of characteristic a known reactance relay (for one element) and a mho relay (for one element). In FIG. 14, the symbol jx represents an induction reactance of the impedance. At a the step 2002, approximately 30 to 50 relay elements are processed. An expected sequence process corresponding to the system is effected based on the outputs of these relay elements at a step 2006. The symbols Z 1 and Z 2 shown in FIG. 14 designate settled values. In the case of the protective relay, a protective range is conditional to these values. These settled values are modified on line by handling of a man from outside of the system when modifying the electric power system and the protective range incidental thereto. FIG. 15 illustrates an example of a processing flow of the reactance relay depicted in FIG. 14. FIG. 16 shows an example of processed waveforms corresponding to the respective processing steps of FIG. 15. The symbols S1 through S6 in FIG. 5 correspond to those of FIG. 16. In this reactance relay, voltage/current data are at first inputted (steps 1 and 2). A variety of arithmetic operations are effected on the voltage-current data (steps S3 - S7). The arithmetic results are compared with the settled values (step S8). If the arithmetic results are larger than the settled values, a counter (not illustrated) for examining a duration of an abnormal state is incremented by +1 (step S9). Subsequently, whether a count value of this counter becomes greater than a predetermined count value or not is examined (step S10). If greater than the predetermined value, this is judged as a status where the relay should be worked. An output of the element relay is set to 1 (step S11). Whereas if not, the output of the element relay is set to 0. The relay remains non-operated (step S12). If the arithmetic results are smaller than the settled values at the step S8, however, the counter is cleared (step S13). As a matter of course, the output of the element relay is 0 (step S14). In the second place, the analog input unit of the electric power digital protective system to which the present invention is applied will be explained. Turning to FIG. 17, the symbols 6a-1 through 6a-N represent low-pass filters (employed for preventing a reflected error attributed chiefly to sampling and hereinafter abbreviated to LPFs). These filters serve to input analog signals in1 through inN inputted from outside and also eliminate the higher harmonics overlapped with the input signals. The symbols 6b-1 to 6b-N denote sample hold (hereinafter abbreviated to S/H) circuits; 6c a multiplexer (abbreviated to MPX); 6d an analog-to-digital (abbreviated to A/D) converting circuit; and 6e a dual port RAM (DPRAM) based buffer memory for A/D converted data. The symbol 6f designates a DSP (Digital Signal Processor); 6j a program memory (ROM) for storing an instruction of the DSP 6f; 6h a local bus; 6i a dual port data memory for transferring and receiving the data to and from a system bus; 6k a system bus interface circuit; and 6l a system bus. Designated at 6g is a timing generating circuit for controlling operations of the S/H circuits 6b-1 through 6b-N, the MPX 6c, the A/D circuit 6d and the buffer memory 6e. The timing generating circuit 6g also transmits an interrupt signal to the DSP 6f. In the embodiment discussed above, there is exemplified a construction in which individual ICs and LSIs are combined. The individual ICs and LSIs can, however, be integrated into one LSI. For instance, referring to FIG., 17, the components of the analog unit-i.e., LPS, S/H, MPX and A/D converter-are integrated into one LSI. The DPS, ROM, buffer memory and data memory are also integrated into one LSI, thereby remarkably compactly miniaturizing the circuit. An additional easy-to-understand arrangement will be given. The ICs and LSIs associated with the respective functions shown in FIG. 17 are integrated into one LSI. In this manner, the circuit is further miniaturized compactly. The digital filter arithmetic operation explained earlier is effected by the DSP 6f of FIG. 17. Namely, the digital filter arithmetic operation, as described before, requires a multiplicity of repetitions of effecting a product-sum operation of decimal point data. For this reason, the DSP capable of performing the product-sum operation at a high speed is preferable. The DSP is classified into a fixed point arithmetic type and a floating point arithmetic type. According to this invention, the processor for executing the digital filter arithmetic operation is applicable to both types. However, the floating point arithmetic type DSP is more desirable. It is because a wider dynamic range can be secured, and there is no necessity for particular awareness about an overflow or underflow. Next, the DSP 6f will be described. FIG. 18 is a diagram showing in detail a construction of one embodiment of the DSP 6f. The DSP in this embodiment, as illustrated in the Figure, comprises: an address register 1200 for specifying an address of an external memory; a data register 1201 used as a parallel port; a data RAM 1203; an (m-bit x m-bit) fast parallel multiplier 1204; a ROM 1205 for instruction; an ALU (Arithmetic Logic Unit) 1207 for performing addition and subtraction; a register 1208 such as an accumulator; a control circuit 1209 for controlling an interrupt of control signals (a, b and c) with respect to the outside; and an internal bus 1210 within the DSP. The multiplier 1204 multiplies contents of input signals A and B during one instruction cycle. A result C thereof is outputted to the internal bus 1210. The ALU 1207 adds the data from the internal bus 1210 to the data of the register 1208. A result thereof is written to the register 1208. Note that the DSP is, as is widely known, capable of carrying out the product-sum operation during one instruction cycle and also effecting pipe line processing. Hence, the DSP is characteristically able to compute the numeric values of fixed and floating point data at a high speed. In this respect, the general-purpose microprocessor incorporating no floating point arithmetic unit is slow of processing and therefore unapplicable. FIGS. 19A to 19D show examples of a processing timing of the analog input unit depicted in FIG. 17. As illustrated in the Figures, the analog input unit is capable of processing in the following three cases depending on the system applied. In the first case, as shown in FIG. 19B, for example, the digital filter arithmetic operation is performed with a period of 3 kHz. After finishing the digital filter arithmetic operation for 5 samples, the arithmetic results are transferred to the control/protective arithmetic unit. It is feasible to synchronize with the arithmetic unit having a period of 600 Hz. In the second case, as illustrated in FIG. 19C, the digital filter arithmetic operation is effected with a period of 3 kHz. The arithmetic results are transferred to the control/protection arithmetic unit similarly with the period of 3 kHz. In the third case, as shown in FIG. 19D, the control/protective arithmetic operation is carried out with the period of 3 kHz together with the digital filter arithmetic operation. That is, the DSP depicted in FIG. 18 executes the filter and control/protective arithmetic operations. In the second and third cases, the arithmetic processing is thereby speeded up. There will next be given an example of advantages of characteristics improved by applying this invention to an electric power digital protective relay. FIG. 20A and 20B show phasic characteristics of a reactance relay applied to a back-up protection of the transmission line. FIG. 20A shows the phasic characteristics in the prior art system (the analog filter is applied). FIG. 20B shows the phasic characteristics in the system to which this invention is applied. In these two systems, the arithmetic of the reactance relay is based on absolutely the same algorithm. The arithmetic formula and conditions of the reactance relay will be given as follows: where I: the current value, Z: the settled value, N: the number of integrations, V: the voltage value, K: the comparative value, the settled value: 1 the frequency: 50 Hz the current: 5A As is obvious from FIG. 20A, in the prior art system an imperfect operating zone between a non-operating zone and an operating zone is wide. Namely, this implies that a dynamic impedance error is large. In accordance with this embodiment, the dynamic impedance error (an error of the operated impedance with respect to a settled impedance) at a characteristic angle (phase angle of 90°) exhibits 3 - 4 %. On the other hand, in the system to which the present invention shown in FIG. 20B is applied, the imperfect operating zone between the non-operating zone and the operating zone is narrow. Namely, this implies that the dynamic impedance error is rather smaller than in the prior art system. This embodiment gives an example where the dynamic impedance error at the characteristic angle exhibits 1 % or less. FIG. 21 shows an example of the dynamic impedance characteristics of the reactance relay. Referring to FIG. 21, the dynamic impedance characteristics in the prior art system are indicated by dotted lines 1500a and 1500b. Solid lines 1501a and 1501b indicate the dynamic impedance characteristics of this invention. As can be clarified from this characteristic diagram, the imperfect operating zone in the dynamic impedance characteristics of this invention is narrower than in the prior art system. Apparently, the accuracy can be extremely increased (high sensitivity). The sensitivity is 3 to 5 times as high as that in the prior art system. FIG. 22A and 22B show the physical characteristics when the present invention is applied to an input unit of a distance relay for obtaining a resistor R and a reactance L up to an accident point in conformity with a differential equation. FIG. 22A shows an example of characteristics based on the prior art method. FIG. 22B shows an example according to the present invention. As is obvious from the Figures, the example to which this invention is applied exhibits such characteristics that a width of the imperfect operating zone between the operating zone and the non-operating zone is quite narrow, and the highly increased accuracy (high sensitivity) is, it can be understood, attainable. FIG. 23 shows an example of a process block configuration for detecting voltage effective values of the electric power system, to which this invention is applied. the aforementioned DSP 1100 depicted in FIG. 17 arithmetically executes the processes of the respective blocks. This is applied to, e.g., an electric power system voltage/reactive power control system. Referring to FIG. 23, the numeral 1701 denotes a digital filter processing block to which this invention is applied. Attenuated in this block are the higher harmonics overlapped with the input signals Vi, offset components, the disturbance noises and the quantization error. In particular, the filter coefficients are set so that low-order harmonics which are n-times (multiple of integer) the fundamental harmonics, the disturbance noises and the quantization error frequency becomes zero point frequencies of the digital filters or come to the vicinity thereof. A large amount of attenuation is thus obtained. Next, a signal frequency is obtained in a block 1702 by using the filtering-processed data. Incidentally, an input data frequency, i.e., an electric power system frequency fluctuates ( + 1 through 3 Hz). It is therefore necessary to correct a gain which fluctuates due to the frequency characteristics of the digital filter. In a block 1703, the gain of the input data is corrected by employing the frequency obtained in the block 1702. Subsequently, the filtering-processed input data the gain of which has been corrected is obtained in a block 1704. Obtainment of the peak value involves the use of, for instance, a peak value holding method or the following arithmetic equation. V = v(t) 2 + v(t + Δt) 2 - 2V(t)V(t + Δt) cosω Δt sin ω Δt Δ t: the sampling interval ω = 2πf f: the detected frequency Next, the effective value is acquired by use if the peak value in a block 1705. An averaging process is effected for increasing the accuracy in a block 1706. In this way, the effective value of the input data can be obtained with an accuracy of 0.01 % or under. As a matter of course, the digital filter, shown in the block 1701, to which this invention is applied is indispensable for attaining the increased accuracy. The following is an explanation of an embodiment of another method of detecting the voltage effective value of the electric power system, to which this invention is applied. An outline of processing will be explained. Synchronizing with external synchronous signals corresponding to the frequencies of the input signals, the input signals are sampled and then undergo an A/D conversion. Subsequently, the input signals undergo digital filtering to obtain the voltage effective value. The sampling frequency is, so to speak, adaptively modified under the external conditions. The filter characteristics are thus modified. The voltage effective value is obtained with a high accuracy by the same algorithm (e.g., the data for one period is squared and integrated). This is applied to a static reactive power compensating system of the electric power system. Turning to FIG. 24, whether or not there exists a data input interrupt is judged at a step 1800. At this time, an interrupt signal, as explained earlier, synchronizes with the frequency of the input signal transmitted from the electric power system. If there exists the interrupt, the data is inputted at a step 1801. Effected thereafter at a step 1802 is the arithmetic process of the digital filter to which this invention is applied. Namely, the frequencies at which the disturbance noises and the quantization error are generated fall within the blocking zone of the digital filter. As a result, the voltage effective value detection shown in a step 1803 is subjected to no adverse influence. At a step 1803, the voltage effective value is obtained by performing the following arithmetic: In this case, the sampling frequency is varied corresponding to the frequency of the input signal. The algorithm is therefore constant irrespective of the frequency of the input signal. The detected voltage effective value is outputted at a step 1804. FIG. 25 shows an example of frequency-gain characteristics of the digital filter used at the step 1802. For instance, a characteristic 1805 is modified into a characteristic 1806, corresponding to a change in the frequency of the input signal from the electric power system. The frequencies at which the disturbance noises and the quantization error are caused change in proportion to the sampling frequencies. Hence, the error reductive effects remain as they are. The voltage effective value can, as a matter of course, be detected with an extremely high accuracy. An embodiment of a digital signal processing system to which this invention is applied will next be explained. Turning attention to FIG. 26, there is illustrated a signal analyzing system. In this embodiment, physical quantities (displacement, velocity, pressure, temperature, etc) are transduced into electric potentials by means of a transducer 3001. Outputs of this transducer 3001 are typically digitized at regular time intervals. That is, the outputs thereof are converted into digital quantities by an A/D converter 3002. These digital quantities undergo a spectrum analysis by use of, e.g., a spectrum analyzer 3004, wherein the frequency analysis relative to an amplitude, phase, electric power or energy is effected. In this case, where this invention is applied to the spectrum analysis, the quantization errors caused due to the A/D conversion can remarkably be reduced. This in turn accomplishes the highly accurate spectrum analysis. A digital filter 3004 eliminates the high frequency components of the A/D converted data or extracts the specific signal frequency components, thereby obtaining the highly accurate data. Note that the numeral 3005 represents a correlating unit for seeking correlation functions between the signal taken in and other signals. In FIG. 26, the present invention is applicable to the portion for filtering after effecting the A/D conversion. The highly accurate signal analyzing system (e.g., the spectrum analyzer) can be therefore constructed. FIG. 27 illustrates an example of configuration of a voice signal processing system, i.e., a CODEC (coderdecoder) system. A voice signal is taken in by an analog sensor 4001. The voice signal is, after being A/D converted by an A/D converter 4002, subjected to a process such as echo canceling in a digital signal processor 4003. The voice signal is D/A converted into an analog signal by a D/A converter 4004. Analog control is performed by an analog controller 4005 with the aid of the analog signal. Referring to FIG. 27, this invention is applicable to the portion for echo canceling by use of the digital signal processor as well as to the A/D converting portion. FIG. 28 shows an example of configuration of a digital data recorder system. Referring to FIG. 28, a plurality of analog input signals are taken in by an analog sensor 5001. These signals are changed over by an analog multiplexer 5002 and sequentially A/D converted by an A/C converter 5003. The thus converted signals undergo digital signal processing by a digital signal processor 5004. The resultant data are stored in a recorder 5005. In FIG. 28, the present invention is applicable to the portions relative to the A/D conversion and the digital signal processor. The input signals are storable with a fidelity. FIGS. 29A and 29B show examples of a digital audio system. In this system, a sound source 6001 is processed by an analog processing unit 6002. The resultant signals are A/D converted by an A/D converter 6003. The data thereof are subjected to digital processing in a processing unit 6004 preparatory to recording by a sound recorder 6005. When reproducing the sound, more digitally recorded signals 7001 are processed in a processing unit 7002. The data thereof are D/A converted by a D/A converter 7003. The analog signals are then processed in a processing unit 7004 and thereby outputted as a sound from a speaker 7005. In FIGS. 29A and 29A, the present invention is applicable to portions associated with digital processing and the A/D conversion in the sound recording system. It is therefore feasible to record the sound source with a fidelity. A signal-to-noise ratio (S/N ratio) is remarkably improved.

Claims: A method of processing a digital signal, comprising the steps of: converting an analog signal into a digital signal after sampling the analog signal; and effecting a filtering process on the digital data by use of a digital filter (103, 200); characterised by the steps of: setting a blocking zone (T 2 ) of said digital filter (103, 200) to a frequency zone higher than a passage zone (T 1 ) of the analog signal when arithmetically processing the filtering-processed digital data; and setting a sampling frequency (fs) so that a synthesis noise generating region associated with disturbance noises and a quantization error becomes larger than said blocking zone of said digital filter. The method of claim 1, wherein a frequency equalling 1/N (N is an integer greater than 2) of said sampling frequency (fs) is set to a zero point frequency (fn) of said digital filter (103, 200). The method of claim 2, wherein said zero point frequency (fn) and an attenuation characteristics of said digital filter (103, 200) are set in accordance with an actually measured value of noises incidental to the disturbance noises and the quantization error. The method of claim 2, wherein the noise generation region associated with the disturbance noises and the quantization error and its magnitude are arithmetically obtained, and the zero point frequency (fn) and the attenuation characteristics of said digital filter (103, 200) are set based on the arithmetic results. The method of claim 2, wherein the noise generating region associated with the disturbance noises and the quantization error and its magnitude are subjected to a spectrum analysis, and the zero point frequency (fn) and the attenuation characteristics of said digital filter (103, 200) are set from the analytic results. The method of any of claims 1 to 5, wherein the analog signals are sampled with a period smaller than an operating period of a digital operating process. A system for processing signals, comprising: sample hold means (101) for sample-holding analog signals; A/D converting means (102) for converting the data held by said sample hold means into digital data; a digital filter (103, 200) for effecting a filtering process on the digital data outputted from said A/D converting means; and digital processing means (104) for executing arithmetic processing, executing a spectrum analysis, effecting an echo cancelling process or effecting an arithmetic process on the basis of the digital data outputted from said digital filter, characterised in that a blocking zone (T 2 ) of said digital filter (103, 200) is set to a frequency zone higher than a passage zone (T 1 ) of the analog signal; and a sampling frequency (fs) of said sample hold means (101) is set so that a synthesis noise generating region associated with disturbance noises and a quantization error becomes larger than said blocking zone of said digital filter. The system of claim 7 used for processing a digital signal, wherein said sample hold means (101) is for sample holding an analog signal; and said digital processing means (104) is for executing arithmetic processing on the basis of the digital data outputted from said digital filter (103, 200). The system of claim 7 used for processing a digital signal for an electric power system, wherein said sample hold means (101) is for sample-holding analog signals relative to physical quantities of an object for analysis; and said digital processing means (104) is for executing a spectrum analysis on the basis of the digital data outputted from said digital filter (103, 200). The system of claim 7 used for analysing a digital signal, wherein said sample hold means (101) is for sample-holding an analog signal relative to a physical quantity of an object for analysis, and said digital processing means (104) is for executing a spectrum analysis on the basis of the digital data outputted from said digital filter (103, 200). The system of claim 7 used for processing a voice signal, wherein said sample hold means (101) is for sample-holding an analog signal relative to a voice, and said digital processing means (104) is for effecting an echo cancelling process on the digital data outputted from said digital filter (103, 200). The system of claim 7 used for recording digital data, wherein said sample hold means (101) is for sequentially sample-holding a plurality of analog signals; and said digital processing means (104) is for executing an arithmetic process on the basis of the digital data outputted from said digital filter (103, 200). The system of claim 7 used in a digital audio system, wherein said sample hold means (101) is for sample-holding an analog signal relative to a voice; and said digital processing means (104) is for effecting an arithmetic process on the basis of the digital data outputted from said digital filter (103, 200). The system of any of claims 7 to 13, wherein a zero point frequency (fn) of said digital filter means (103) is set to a frequency equalling 1/N (N is an integer greater than 2) of said sampling frequency (fs).

Inventors: CHIBA TOMIO, KAWAI TADAO, KAWAKAMI JUNZO, KIDO MITSUYASU, KUDO HIROYUKI, CHIBA, TOMIO, KAWAI, TADAO, KAWAKAMI, JUNZO, KIDO, MITSUYASU, KUDO, HIROYUKI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1990
Main classification: H02J13
IPC codes: H04B14, H02J13, G01R19, H02J3