Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing a oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) (20,30) are provided in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one (20) of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one (30) of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.

Description: METHOD AND APPARATUS FOR DETECTING OSCILLATOR STUCK FAULTS IN A LEVEL SENSITIVE SCAN DESIGN (LSSD) SYSTEM The present invention relates to a method and apparatus for stuck fault testing an oscillator and more particularly to a method and apparatus for stuck fault testing an oscillator adapted for use with a Level Sensitive Scan Design (LSSD) system and testing technique of the type disclosed and defined in U.S. patent Nos. 3,783,254, 3,761,695, 3,784,907 and 4,268,903. Due to the complexity and the extremely great number of circuit functions contained on a single large scale integrated (LSI) device or chip, the LSSD system and testing technique have been widely used. An oscillator is susceptible to stuck faults or permanent static bit failures where a clock oscillator signal is fixed at either a logical one "1" or a logical zero "0." U.S. Patent No. 4,268,903 generally discloses the LSSD system and testing technique and a computer system including a maintenance interface compatible with LSSD design for synchronizing the operation of a service processor and a central processing unit. Various testing techniques have been employed to identify stuck faults in oscillators. Many testing techniques utilize a separate reference pulse which requires additional logic to generate and that is also subject to failure. Examples of such testing techniques are disclosed in U.S. patent Nos. 4,374,361, 4,399,412, 4,467,285 and a publication entitled "PULSE CHECKING CIRCUIT" by P.J. Veneziano, IBM Technical Disclosure Bulletin, Vol. 9, No. 5, October 1966, p.473. Other significant disadvantages of the above and many of the known testing methods are that LSSD compatibility is not provided and a special reporting logic is required. Many testing methods that are compatible with LSSD testing techniques disable the system oscillator during diagnostic subroutines so that an oscillator stuck fault cannot be identified. For example, U.S. Patent No. 4,542,509 discloses a method and apparatus for fault testing a clock distribution network that includes a plurality of clock signal lines for distributing a clock signal from a system oscillator. The fault testing apparatus includes a test latch for storing either a logical value one "1" or a logical value "0" and a decoder for connecting any one of the clock signal lines to the test latch. During the fault testing method the system oscillator is effectively disconnected from the clock distribution network under test. EP-A-0 280 848 entitled "On-chips on-line ac and dc clock tree error detection system" assigned to the assignee of the present application discloses a test circuit for producing a "fail" signal if a clock path driver circuit develops an AC or DC defect. The circuit comprises a time delay block for providing a delayed clock signal and its complement with a delay that exceeds the signal propagation time through the clock receiver and driver. The circuit additionaly includes a latch which is clocked by the complement of the delayed clock signal to receive the drive signal and to generate pulses which do not overlap in time with the pulses of the delayed clock signal during normal circuit operation. The circuit also includes a gate for detecting such a pulse overlap and for generating an error signal to indicate an AC or DC fault. A need exists for a method and apparatus for detecting oscillator stuck faults that facilitates error reporting with the LSSD scan function and that does not require additional input/output pins or other special changes to individual chips. Important objects of the present invention are to provide an improved method and apparatus for fault testing an oscillator; to provide such a fault testing method and apparatus adapted for use with a Level Sensitive Scan Design (LSSD) system and testing technique; to provide such a fault testing method and apparatus that facilitates failure reporting utilizing a LSSD scan function; to provide such a fault testing method and apparatus that does not require special signals from or special changes in other components in the system; and to provide such a fault testing method and apparatus that facilitates efficient and reliable error detecting operations. These objects are provided by the method according to the present invention as defined in claim 1. In brief, the objects and advantages of the present invention are achieved by a method and apparatus for identifying stuck faults in an oscillator used for providing a oscillator input signal to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of test shift register latches (SRLs) are provided in the integrated circuit chip. A logical one signal is applied to a functional data input of the test SRLs. The oscillator input signal is applied to a data clock input of a first one of the test SRLs and an inverted oscillator input signal is applied to the data clock input of a second one of the test SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault in the oscillator. The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the embodiment of the invention illustrated in the drawings, wherein: FIG. 1 is a block diagram of a testing system which may be employed in carrying out the testing method of the invention; and FIG. 2 is a timing diagram illustrating the control signals which may be employed in carrying out the testing method of the invention. Referring now to the drawings, in FIG. 1 there is illustrated a block diagram representation of a stuck fault testing logic system according to the invention generally designated by the reference numeral 10. Fault testing logic system 10 advantageously is implemented as a part of an integrated circuit chip for providing stuck fault diagnostics of an oscillator providing a clock oscillator signal to the chip. A clock oscillator signal indicated at a line 12 labelled OSCILLATOR INPUT is applied to a first input of a two-input AND gate 14 of the testing logic system 10. An inverted enable diagnostics signal indicated at a line 16 labelled -ENABLE DIAGNOSTICS is applied to the other input of AND gate 14. The enable diagnostics signal is activated high at least with each initial program load (IPL) and during LSSD scan testing functions. Otherwise the enable diagnostics signal is deactivated low. Referring also to FIG. 2, the -ENABLE DIAGNOSTICS signal 16 provides a logical 0 signal during LSSD scan testing functions and a logical 1 signal during normal data functions. The output of AND gate 14 indicated at a line 18 is applied to a data clock input of a first test shift register latch (SRL) labelled STUCK AT 0 and designated by the reference numeral 20. An inverted clock oscillator signal indicated at a line 22 is generated at the output of an INVERTER gate 24. The inverted -clock oscillator signal is applied to a second two-input AND gate 26. The -ENABLE DIAGNOSTICS signal 16 is applied to the other input of AND gate 26. The output of AND gate 26 indicated at a line 28 is applied to a data clock input of a second test SRL labelled STUCK AT 1 and designated by the reference numeral 30. Each of the STUCK AT 0 and STUCK AT 1 test SRLs 20 and 30 are implemented by a typical shift register latch used as a single storage element with the integrated circuit LSSD chip including the testing logic system 10. Each SRL 20 and 30 consists of a pair of polarity hold latches L1 and L2 (type D) with the output of the first L1 latch applied to an input of the second L2 latch. Typically the L1 latch is used as a functional storage element, while the L2 latch is used to improve the effectiveness of chip testing. LSSD requires that all of the SRLs on the entire chip are connected together into a shift register or scan ring by connecting a scan data output (SDO) of each L2 latch to another scan data input (SDI) of a L1 latch to allow patterns to be shifted or scanned into and out of all latches in the design. An A clock input is used to clock data from the SDI into the L1 latch. Functional data at an input DATA is the normal functional data input with a data clock used to load data from this input. A B clock input is used to clock data from the L1 latch into the L2 latch of the LSSD scan ring. The LSSD A scan clock is illustrated and the LSSD B scan clock is not shown in FIG. 2. During LSSD scan functions first the B clock is activated to copy the L1 latch data to the L2 latch, then the A clock is activated to load the previous L2 latch data at the L1 latch. During an initial LSSD scan function, logical zeroes are scanned into all the SRLs on the integrated circuit LSSD chip including the SRLs 20 and 30 of the testing logic system 10 before the chip is placed in functional mode. As shown in FIGS. 1 and 2, a logical zero is applied to the SDI and a logical one is applied to the L1 latch data input of the test SRLs 20 and 30. The oscillator input signal 12 and the inverted oscillator input signal 22 is ANDed with the -ENABLE DIAGNOSTICS signal 16 by gates 14 and 26, respectively, to isolate the oscillator and the inverted oscillator input signals 12 and 22 from the data clock of the SRLs 20 and 30 during the LSSD scan functions. The -ENABLE DIAGNOSTICS signal 16 is low or logical zero during the initial scan in function so that the data clock signals 18 and 28 are logical zero. The SDO of the test SRLs 20 and 30 indicated respectively at a line 20A and 30A is set at logical zero. FIG. 2 illustrates timing waveforms corresponding to a normal oscillator input signal 12 provided by the oscillator being tested. After the initial scan in function the -ENABLE DIAGNOSTICS signal 16 is activated high or to logical one so that the data clock signals 18 and 28 applied to the SRLs 20 and 30 correspond to the oscillator and the inverted oscillator input signals 12 and 22, respectively. Unless the oscillator under test has either a stuck at zero fault or stuck at one fault, the logical one SDI is loaded to the L1 latch of the test SRLs 20 and 30 responsive to an active high data clock signal 18, 28, respectively. Otherwise with a stuck at zero oscillator input signal 12, The L1 latch of the STUCK AT 1 SRL 30 is loaded with a logical one responsive to the resulting active high data clock signal 28 while the L1 latch of the STUCK AT 0 SRL 20 is maintained at a logical zero. With a stuck at one oscillator input signal 12, the STUCK AT 1 SRL 30 L1 latch data is maintained at a logical zero and the L1 latch of the STUCK AT 0 SRL 20 is loaded at a logical one responsive to the resulting active high data clock signal 18. The LSSD scan function is used for reporting oscillator stuck faults. As shown in FIG. 2, the -ENABLE DIAGNOSTICS signal 16 returns low or logical zero so that the resulting deactivated low data clock signal 18, 28 is applied to the SRLs 20, 30, respectively. Scanning begins as indicated at scan out. In response to a LSSD B scan clock pulse the L1 latch data that was loaded responsive to the previous data clock signals 18 and 28 is copied to the L2 latch for the test SRLs 20 and 30. When the oscillator is providing the normal oscillator input signal 12, a logical one is copied to the L2 latch of both test SRLs 20 and 30. Otherwise with either a stuck at one or a stuck at zero fault, a logical zero is copied to the the L2 latch of one of the test SRLs 20 or 30. The L2 latch data is scanned from the STUCK AT 0 and STUCK AT 1 test SRLs 20, 30 via a chip SDO. Each of the test SRLs 20, 30 are provided at a predefined position relative to the chip SDO in order to locate the stuck fault data. Fault testing logic system 10 can be implemented with logic circuitry as illustrated in FIG. 1 for carrying out the testing method of the invention; however, it should be understood that various other logic circuitry could be used.

Claims: A method for identifying stuck faults in an oscillator used for providing an oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system (10) and testing technique, said integrated circuit chip including a pair of test Shift Register Latches (SRLs, 20, 30); said method comprising the steps of: initially scanning logical zeros into both said test SRLs (20, 30); applying a logical one to the data inputs of both test SRLs (20, 30); applying the oscillator input signal to a data clock input of the first one of said test SRLs and applying the inverted oscillator input signal (22) to a data clock input of the second one of said test SRLs (20, 30) and detecting the scan data output (SDO) of said test SRLs in response to said applied oscillator input signal and said inverted oscillator input signal to identify a stuck fault in the oscillator. A method as recited in claim 1 wherein each said test SRLs (20, 30) are located at a predefined position relative to a SDO of the integrated circuit chip. A method as recited in claim 1 wherein said step of detecting the scan data output (SDO) of said SRLs responsive to said applied oscillator input signal (12) and said inverted oscillator input signal (22) to identify a stuck fault in the oscillator involves the steps of: isolating said oscillator input signal (23) from said data clock input (18) of said first one of said test SRLs (20, 30) and said inverted oscillator input signal (22) from said data clock input (28) of said second one of said test SRLs (20, 30); and sequentially applying a first LSSD B scan clock signal and a second LSSD A scan clock signal to said test SRLs (20, 30). A method as recited in claim 3 further involving the step of: sequentially sampling a SDO of the integrated circuit chip for detecting the scan data output (SDO) of said test SRLs. A method as recited in claim 3 wherein said step of - isolating said oscillator input signal (12) from said data clock input (18) of said first one of said test SRLs (20, 30) and said inverted oscillator input signal (22) from said data clock input (28) of said second one of said test SRLs (20, 30) involves the steps of: applying said oscillator input signal (12) to an input of a first AND gate (14); applying said inverted oscillator input signal (22) to an input of a second AND gate (26); applying an active low LSSD scan enable signal to the other inputs of said first and second AND gates (14, 26); applying the output of said first AND gate (14) to said data clock input of first one (20) of said test SRLs (20, 30); and applying the output of said second AND gate (26) to said data clock input of said second one (30) of said test SRLs (20, 30). A method as recited in claim 1 wherein a detected logical one value for the scan data output (SDO) of both said test SRLs (20, 30) indicates no stuck fault in the oscillator. A method as recited in claim 1 wherein a detected logical zero value for the scan data output (SDO) of said first test SRL (20) indicates a stuck at one fault in the oscillator. A method as recited in claim 1 wherein a detected logical zero value for the scan data output (SDO) of said second test SRL (30) indicates a stuck at zero fault in the oscillator. Apparatus for identifying stuck faults in an oscillator used for providing an oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique, said apparatus comprising: a pair of test shift register latches (SRLs) (20, 30) included in the integrated circuit chip; means for initially scanning logical zeros in both said test SRLs; means for applying a logical one to the data inputs of both said test SRLs (20, 30); means (14) for applying the oscillator input signal (12) to a data clock input of the first one (20) of said test SRLs (20, 30); means (26) for applying the inverted oscillator input signal (22) to a data clock input of the second one (30) of said SRLs (20, 30); and means for detecting the scan data output (SDO) of said test SRLs (20, 30) in response to said applied oscillator input signal (12) and said inverted oscillator input signal (22) to identify a stuck fault in the oscillator. Apparatus as recited in claim 9 wherein said means for applying the oscillator input signal (12) to a data clock input of the first one (20) of said test SRLs (20, 30) and said means (26) for applying the inverted oscillator input signal (22) to said data clock input of the second one (30) of said test SRLs (20, 30) includes: a first AND gate (14), said oscillator input signal (12) coupled to an input of said first AND gate (14); a second AND gate (26), said inverted oscillator input signal (22) coupled to an input of said second AND gate (26); means for coupling an active low LSSD scan enable signal to another input of said first (14) and second (26) AND gates; means for coupling an output of said first AND gate (14) to said data clock input of said first one (20) of said test SRLs (20, 30); and means for coupling an output of said second AND gate to said data clock input of said second one (30) of said test SRLs (20, 30). Apparatus as recited in claim 10 wherein said means for detecting the scan data output (SDO) of said test SRLs (20, 30) comprise LSSD scanning means responsive to said active low LSSD scan enable signal for sequentially sampling a SDO of the integrated circuit chip.

Inventors: BORKENHAGEN JOHN MICHAEL, DOUSKEY STEVEN MICHAEL, MEYER JEROME MARTIN, BORKENHAGEN, JOHN MICHAEL, DOUSKEY, STEVEN MICHAEL, MEYER, JEROME MARTIN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: G01R31
IPC codes: G01R31, G06F11