Parallel to serial converter

Abstract: A parallel to serial converter for converting n (n being an integer) bit parallel data streams into a serial data stream including first latch means responsive to a first timing pulse for latching the n bit parallel data streams to produce first n bit parallel data streams, m (m being an integer) second latch means responsive to m second timing pulses for latching the n bit parallel data streams to produce m sets of second n bit parallel data streams, third latch means responsive to the first timing pulse for latching the m sets of second n bit parallel data streams to produce m sets of third n bit parallel data streams, shift register means coupled to the first and third latch means and responsive to the first n bit parallel data streams and the m sets of third n bit parallel data streams and a load pulse for registering (m+1) x n bit data from the first n and m sets of third n parallel data streams and for shifting the (m+1) x n bit data in response to a shift pulse and timing generating means for generating the first timing pulse, m second timing pulses, the load pulse, and the shift pulse, the first timing pulse having one-((m+1) x n)th of the clock rate of the shift clock pulse, each of the m second timing pulses being delayed by one-mth of a period of the first timing pulse, and the load pulse being timed with the first timing pulse.

Description: BACKGROUND OF THE INVENTION This invention relates to an improvement for a parallel/serial converter which converts parallel signal sequence into a serial signal sequence. The parallel/serial converter of this type has been used for an interface which converts parallel data from a computer or a communication system to serial data and a multiplexer which multiplexes a plurality of data sequences from plural channels. A prior art parallel/serial converter comprises a parallel input/serial output shift register and a holding register connected to the parallel input side of the shift register as a buffer store means. (See, for example, pages 4-9 of "Technical Aspects of Data Communication" (in Japanese) published by CQ Publishing Company, on April 20, 1980). The holding register loads and stores n -bit ( n is an integer) parallel input digital data with a load input, and then the shift register receives the stored data in parallel from the holding register to shift n -bit serial signal on a bit by bit basis with a shift clock signal which has a higher rate than the input digital data. When the shift register has shifted out the n -bit serial data, it receive the next n -bit parallel outputs from the holding register and then converts them to serial data. If the signal rate of the parallel input signal sequence increases, the store means should receive and store each of the parallel input signals at a rate proportionally higher. Therefore, the prior art parallel/serial converter can not operate at the signal rate beyond the capacity of the operational frequency of the holding register and latch circuit. In "Integrated Circuits Applications Handbook" edited by Arthur H. Seidman and published by John Wiley and Sons, New York in 1983, there is described at pages 442 to 444 a circuit for interfacing a 12 bit DAC with an 8-bit µP in which a data bus is time shared by using two output ports; one for the first 8 bits and the other for the remaining 4 bits. In the circuit shown there is one output port for the least significant 8 data bits which are sent by a first instruction to the one output port and they are latched by a first converter, the four most significant bits being sent by the next instruction to another output port. It is an object of this invention to provide a parallel/serial converter which permits operation at a higher bit rate despite the use of components usable at a reduced bit rate. The parallel/serial converter according to this invention converts n (n being an integer) bit parallel data streams into a serial data stream. A parallel/serial converter to be described has first latch means responsive to a first timing pulse for latching the n bit parallel data streams to produce first n bit parallel data streams; m (m being equal to 2) second latch means responsive to m second timing pulses for latching the n bit parallel data streams to produce m sets of second n bit parallel data streams; third latch means responsive to the first timing pulse for latching the m sets of second n bit parallel data streams to produce m sets of third n bit parallel data streams; shift register means coupled to the first and third latch means and responsive to the first n bit parallel data steams and the m sets of third n bit parallel data streams and a load pulse for registering (m+1) x n bit data from the first n and m sets of third n parallel data streams and for shifting the (m+1) x n bit data in response to a shift pulse; and timing generating means for generating the first timing pulse, m second timing pulses, the load pulse, and the shift pulse. The first timing pulse have one-((m+1) x n)th of the clock rate of the shift clock pulse, and each of the m second timing pulses is delayed by one-m th of a period of the first timing pulse. The load pulse is timed with said first timing pulse. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a block diagram to show the first embodiment of the parallel/serial converter according to this invention; FIG. 2 is a timing chart to show the operation of the parallel/serial converter shown in FIG. 1; FIG. 3 is a block diagram to show the second embodiment of this invention; and FIG. 4 is a timing chart to show the operation of the parallel/serial converter shown in FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a parallel/series converter of this invention comprises a first main latch circuit 10 and a sub-latch circuit 30 which alternately latch 4-bit parallel input digital data streams applied at input terminals 1, 2, 3 and 4 at a constant interval, a second latch circuit 20 which latches the parallel output from the sub-latch circuit 30 simultaneously with the first latch circuit 10, and a parallel input/serial output shift register 40 which converts 8-bit parallel outputs from the first and second latch circuits 10, 20 into a serial data stream. The 4-bit parallel input signal applied to the input terminals 1, 2, 3 and 4 may be parallel data such as characters or mutually different data streams for each of the input terminals. As shown in FIG. 2, 4-bit parallel input signals A1 - A4, B1 - B4, C1 - C4, D1 - D4, and E1 - E4 (Each of Ai, Bi, Ci, Di, Ei (i = 1 ∼ 4) indicates a 1-bit signal in 4-bit parallel data) are continuously supplied at input terminals 1, 2, 3 and 4 at every 4 µs, and stored alternately in the main latch circuit 10 and the sub-latch circuit 30. The main latch circuit 10 and the sub-latch circuit 30 latch parallel inputs repeatedly at the period (8 µs) two times longer than that of the parallel input signals, respectively. The main latch circuit 10 latches and stores the parallel input signals A1 - A4, C1 - C4 and E1 - E4 in every 8 µs while the sub-latch circuit 30 latches and stores the parallel input signals B1 - B4 and D1 - D4 in the period of 8 µs but with the delay of 4 µs from the main latch circuit 10. The parallel input signals which are stored in the sub-latch circuit 30 are further latched by the main latch circuit 20 simultaneously with the main latch circuit 10. The latching operation of the main latch circuits 10 and 20 and sub-latch circuit 30 is controlled by an oscillator 50, a 1/8 frequency divider 60 and a delay circuit 70. The oscillator 50 generates a clock signal of the frequency of 1 MHz which is divided in frequency by the 1/8 frequency divider 60 to become a main latch signal a of 125 KHz (with the period of 8 µs). The main latch signal a is supplied to the main latch circuits 10 and 20 simultaneously. As shown in FIG. 2, the main latch signal a is pre-set to rise when the parallel input signal level is stable. The main latch signal a is delayed by 4 µs by the delay circuit 70 and supplied to the sub-latch circuit 30 as a sub-latch signal b . The delay circuit 70 comprises a delay line 72 which is serially connected between NOT gates 71 and 73 which shape the waveform of the signal. The main latch circuits 10 and 20 and the sub-latch circuit 30 are made to latch parallel input signals at the rising edges of the main latch signal a and the sub-latch signal b , respectively, and output them to the output terminals Q0 - Q4 until the next latch time. After the parallel signals A1 - A4 are latched and stored by the main latch circuit 10, the main latch circuits 10 and 20 latch parallel signals C1 - C4 and B1 - B4, and further 8 µs later, latch parallel signals E1 - E4 and D1 - D4. the 8-bit parallel outputs from the main latch circuits 10 and 20 are respectively applied to the input terminals A - H of the parallel input/serial output shift register 40 and loaded at the shift register 40 with a load signal c which is generated immediately after the rise of the main latch signal a . The load signal c is the pulse signal of negative logic supplied from a load signal generator 80, and turns to low level in synchronization with the rise of the main latch signal a and to high level after the time (1 µm) equivalent to one period of the clock signal from the oscillator 50. The shift register 40 loads the parallel output from the main latch circuits 10 and 20 with the rise of load signal c , and shifts out the loaded 8-bit parallel signal bit by bit basis with the clock signal from the oscillator 50, in the order of the parallel inputs at the input terminals H, G, F, E, D, C, B, and A. Therefore, the parallel signals A1 - A4, B1- B4 and C1 - C4 are converted into serial signal sequence A4, A3, A2, A1, B4, B3, B2, B1, C4, C3, C2, C1. As the latching period at the latch circuits 10, 20 and 30 in the aforementioned embodiment is two times higher than the input period of the parallel input signal sequence at the input terminals 1, 2, 3 and 4, the latch circuits 10, 20 and 30 can use ICs of the operational rate of one half of the prior art ICs. FIG. 3 shows another embodiment of this invention converter in block diagram. In FIG. 3, the parallel/serial converter comprises the first, second and third main latch circuits 11, 12 and 13 and the first and second sub-latch circuits 14, 15 which can use ICs operating at the rate lower than the latch circuits 10, 20 and 30 of the first embodiment, and a parallel input/serial output shift register 41 shifts the 12-bit parallel data fed from the main latch circuits 11, 12 and 13 and converts them to a serial data sequence. Similarly to the parallel input signals shown in FIG. 2, 4-bit parallel input digital signals A1 - A4, B1 - B4, ... are continuously supplied to input terminals 1, 2, 3 and 4 in every 4 µs as shown in FIG. 4. The first latch circuit 11 and the first and second sub-latch circuits 14, 15 are connected to the input terminals 1, 2, 3 and 4. The first main latch circuit 11 latches the first parallel input signals A1 - A4 at the rise of the main latch signal a 1 of the period of 12 µs. The main latch signal a 1 is a clock signal of the period of 12 µs which is obtained by dividing the frequency of the clock signal of 1 MHz from the oscillator 50 by 12. Then, the first sub-latch circuit 14 latches parallel input signals B1 - B4 at the rise of a first sub-latch signal b 1 which is obtained by delaying the main latch signal a 1 by 4 µs at the delay circuit 70 a . The second sub-latch circuit 15 latches parallel input signals C1 - C4 at the rise of a second sub-latch signal b 2 obtained by delaying the first sub-latch signal b 1 by 4 µs at the delay circuit 70 b . The parallel input signals which have been latched at the main latch circuit 11 and sub-latch circuits 14, 15 are stored and outputted until next rises of respective latch signals a1, b1, b2. The 4-bit parallel outputs from the first sub-latch circuit 14 are latched by the third main latch circuit 13 at the rise of the main latch signal a 1 while the 4-bit parallel outputs from the second sub-latch circuit 15 are latched by the second latch circuit 12 at the rise of the main latch signal a 1. When the main latch circuit 11 latches parallel input signals A 1 - A 4, the main latch circuits 12, 13 do not latch any signals because the sub-latch circuits 14, 15 have not stored the parallel signal respectively. But when the main latch circuit 11 latches parallel input signals D1 - D4, the main latch circuits 12, 13 latch respectively the parallel inputs C1 - C4 and B1 - B4 which have been stored by the sub-latch circuits 15 and 14. Therefore, the main latch circuits 11, 12 and 13 output parallel input signals D1 - D4, C1 - C4, and B1 - B4 to the shift register 41 for the period of 12 µs after the main latch circuit 11 has outputted parallel signals A1 - A4. The shift register 41 loads 12-bit parallel signals from the main latch circuits 11, 12 and 13 at the rise of load signal c 1 which is generated immediately after the rise of the main latch signal a 1, and shifts them out bit by bit with the clock of 1 MHz from the oscillator. The shift register 41 converts the 12-bit parallel signals into a serial signal in every 12 µs. The load signal c 1 is a pulse signal of negative logic generated from a load signal generator 81 which is shifted to low level at the rise of the main latch signal a 1 and shifted to high level after one period of clocks from the oscillator. The parallel/serial converter shown in FIG. 3, can use a latch circuit of the lower rate than those used for the converter shown in FIG. 1. For permitting the use of latches operable at a further reduce of bit rate, additional sub-latch circuit and main latch circuit may be connected in parallel between input terminals and a shift register to increase the number of parallel inputs of the shift register as well as to increase the latch period proportionally to the number of the main latch circuits. Although two to three 4-bit latch circuits are connected in parallel to the main latch circuit in the parallel/serial converters shown in FIGs. 1 and 3, only one latch circuit of 8-bit or 12-bit may be used instead. As described in detail in the foregoing statement, there has been disclosed a sub-latch means which latches parallel input signals different from those in the first latch means, and a second main latch which latches the parallel inputs stored in the sub-latch means simultaneously with the first main latch means, and the first and second main latch means supply plural parallel outputs of the rate lower than the original parallel input signals to a parallel input/serial output shift register. Therefore, the operational frequencies of respective latch means are reduced in proportion to the number of the parallel inputs to the shift register, and the main and sub-latch means can use low rate ICs even if the parallel input signals have a higher rate. It will be understood that, although the invention has been described, by way of example, with reference to particular embodiments, variations and modifications thereof, as well as other embodiments, may be made within the scope of protection sought in the appended claims.

Claims: A parallel to serial converter for converting n bit parallel input data, n being an integer on n bit data lines (1-4) into a serial data stream, the parallel to serial converter including a first main latch circuit (11) connected to the n bit data lines (1-4), a sub-latch circuit (14) connected to the n bit data lines (1-4) and a shift register (41) coupled to the output of the first main latch circuit (11) and responsive to first n bit parallel data, the first main latch circuit (11) being responsive to first timing pulses for latching the n bit parallel input data to produce the said first n bit parallel data, characterised in that there are provided second and third main latch circuits (12) (13), and a second sub-latch circuit (15), the second sub-latch circuit (15) being connected to the n bit data lines (1-4), the first and second sub-latch circuits (14) (15) constituting m latch circuits where m equals two for parallel latching the n bit parallel input data one after another in response to m sets of timing pulses, the second and third main latch circuits (12) (13) being responsive to the first timing pulses for latching the m sets of second n bit parallel data to produce third bit parallel data, the outputs of the first and second sub-latch circuits (14) (15) being applied respectively to the inputs of second and third main latch circuits (13) (12), and the shift register (41) being responsive to the third bit parallel data for registering the first and the third bit parallel data and for shifting the first and the third bit parallel data in response to shift pulses, and in that timing generating means (50, 61, 70a, 70b) are provided for generating the first timing pulses, m sets of second timing pulses and the shift pulses, the m sets of second timing pulses having a frequency of one-(m+1)th of the clock rate of the n bit parallel input data and being delayed in order every one clock period of n bit input parallel data to produce m sets of second n bit parallel data, the first timing pulse and the m sets of second timing pulses being alternately supplied to the first and the second latch means, the third latch means producing third n x m bit parallel data whereby the shift register registers the first and third parallel data n x (m + 1) and shifts the first and third data in response to shift pulses, and the shift pulses having a pulse rate which permits serial shifting of the first and third data from the shift register (41) within a period corresponding to a repetition rate of the first timing pulses. A parallel to serial converter for converting n bit parallel input data, n being an integer on n bit data lines (1-4) into a serial data stream including a first main latch circuit (10) connected to the n bit data lines (1-4), the first main latch circuit (10) being responsive to first timing pulses for latching the n bit parallel input data to produce first n bit parallel data, a sub-latch circuit (30) connected to the n bit data lines (1-4) and a shift register (40) coupled to the output from the first main latch circuit (10) and responsive to the first n bit parallel data, characterised in that there is provided a second main latch circuit (20) connected at its input to latch the parallel output from the sub-latch circuit (30) and at its output to the shift register (40), the sub-latch circuit (30) being responsive to second timing pulses for latching the n bit parallel data to produce second n bit parallel data, the first and second timing pulses being generated alternately, and the second main latch circuit (20) being responsive to the first timing pulses for latching the second n bit parallel data to produce third n bit parallel data, in that the shift register (40) is responsive to the third n bit parallel data, in that timing generating means (50, 60, 70) are provided for generating the first and second timing pulses and shift pulses, the shift register (40) being arranged to register 2 x n bit data of the first n and third n bit parallel data and to shift the 2 x n bit data in response to the shift pulses; the first and second timing pulses having a half clock rate of the n bit parallel input data, and in that the shift pulses have a pulse rate which permits the first and third data to be shifted serially from the shift register within a period corresponding to the repetition rate of the first timing pulses.

Inventors: UDA YOSHIHIRO, UDA, YOSHIHIRO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: H03M9
IPC codes: G06F5, H03M9