DIGITAL TO ANALOG CONVERTERS

Abstract: A multiplying digital to analog converter comprises shunt legs wherein a switch (15) has a common terminal connected to a respective node (12) in the series path and two switchable terminals each connected to a respective resistor. Each series branch consists of a dummy switch (28) in series with a series resistor (13) having half the resistance value of each of the shunt resistors (14', 14''). The switches, which are preferably implemented in CMOS technology, are physically matched and the switches in the series arms are configured to be closed so that the resistance of each dummy switch is half that of the switch in the respective shunt leg. The arrangement enables the preservation of the R-2R relationship between the series and shunt resistances and thereby substantially improves the linearity of the converter.

Description: DIGITAL TO ANALOG CONVERTERS Field of the Invention The present invention relates to digital to analog converters and particularly to multiplying digital to analog converters which are realised as R-2R ladder networks each with a switch in a respective shunt branch controlled by a respective digit of a digital signal. The invention more particularly relates to such a converter which is realised as an integrated circuit or part thereof and in particular with the use of complementary metal oxide semiconductor (CMOS) fabrication techniques. Such multiplying digital to analog converters are potentially attractive for use in a variety of systems, they are essentially simple in arrangement and employ relatively few types of component. They have inherent current switching, which may be readily adapted for voltage switching, and can readily be made bi-directional in operation so as to permit two or four quadrant operation. In the usual form of em R-2R converter, as described by, for example, Sevastopoulos et al., EDN March 1979, pages 77 to 81, the ladder network is arranged so that, ignoring the resistance of the switches in the shunt branches, the series resistance presented to each node is exactly equal to the shunt resistance connected to that node. If this theoretical condition is met, there is an exact current division at each node (considering current flow in the forward direction) so that the current flowing in each shunt branch, irrespective of the position of the controlling SUBSTITUTE SHEET switch, is proportioned according to a respective power of two. The appropriate switches are operated in accordance with the binary signal. For example, all stages representing a "1" are switched so that the respective currents are fed from a common reference to a common output; this provides the required conversion of the digital signal into its corresponding analog form. However, as may be noted from the foregoing, the accuracy with which the digital to analog conversion can be performed is fundamentally dependent upon the accuracy with which the ratio of the resistances in the series of shunt branches is realised. Each shunt branch normally consists of a resistor of which one end is connected to the node and the other end is connected by a two way switch to one or other of two outputs or reference voltages, depending upon the configuration of the converter. The switches should have zero resistance when closed and infinite resistance when open. The switches are semiconductor switches and accordingly the resistance is not negligible in the on condition of the switch. This is particularly true for CMOS switches. Moreover, the resistance of the switches depends upon their terminal voltages in a non-linear manner. The practical effect of the non-negligible resistance of the switches when they are conductive is non-linearity of the digital to analog conversion. Such non-linearity renders the multiplying digital to analog converter unsatisfactory for the conversion of digital words having more than about five or six bits. SUBSTITUTE SHEET Summary of the Invention One object of the invention is to provide an improved multiplying digital to analog converter and in particular a converter having improved linearity. Another object of the invention is to provide a multiplying digital to analog converter employing CMOS technology and in which the inaccuracies arising from the use of CMOS switches are substantially reduced. In a preferred form of the invention a switch means in each shunt arm is coupled to a respective node in the series path and is adapted to connect the node to one or other of two common lines, the resistances of the two alternative paths being equal. Preferably this switch means is realised as two pairs of CMOS switches. The series arms are each constituted by the required series resistor and a switch means which physically matches the switch means in the shunt arm. Preferably the series switch means comprises a pair of dummy switches in parallel, and in particular two parallel pairs of closed CMOS switches. By this means the contribution of the series switch means to the series resistance can be made half that of the contribution of the shunt switch means to the shunt resistances and a substantially exact match can be obtained. It is furthermore possible using complementary switches to reduce the voltage dependence of each switch and the variation of switch resistance between the most significant bit section and the least significant bit section can be kept below a few ohms. Since typical series and shunt resistances are of the order of ten or twenty kilohms, the SUBSTITUTE SHEET converter can readily be made to provide sufficient accuracy for eight bit operation and accuracy sufficient for operation with a greater number of bits is feasible. It is known from ϋS-A-4381499 (Struthoff) to provide in an integrated circuit an R to 2R digital to analog converter having a multiplicity of sections each including a series arm and a shunt leg wherein said shunt leg includes a semiconductive switch means for providing two alternative shunt paths of similar resistance, the semiconductive switch means having a substantial switch resistance when conductive and wherein the series arm has a resistance corresponding to half the resistance of one of the said alternative shunt paths, and dummy switch means in each series arm, each said dummy switch means being configured to have half the said switch resistance. The document proposes that the resistance of each dummy switch be made approximately half the shunt switch resistance by making the active power ratio of the series dummy switch twice that of a shunt switch. The present invention has the advantages that the manufacturing process is simpler and more accurate, the circuit does not require regulated voltage control of the gates of the switches and the resistance matching is inherently more accurate. Other objects and advantages of the present invention will be apparent from the detailed description which follows. SUBSTITUTESHEET Brief Description of the Drawings Figure 1A, Figure IB and Figure 1C illustrate known configurations of an R-2R multiplying digital to analog converter to which the present invention can be applied; Figure 2 illustrates a particular embodiment of the invention; Figure 3 illustrates a pair of dummy CMOS switches suitable for use in the embodiment shown in Figure 2; and Figure 4 shows a realization of a pair of shunt switches suitable for the embodiment shown in Figure 2 and an associated control circuit. Detailed Description of the Preferred Embodiment Figures 1A, IB and 1C show various typical configurations of a multiplying digital to analog converter. The converter in Figure 1A has a terminal 10 connected to a ladder network 11 which has nodes 12 separated by series resistors 13. From each node extends a respective shunt resistor 14. For reasons which will become apparent, the series resistors 13 are half the resistance value of the shunt resistors 14. All the shunt resistors except the last, terminating resistor 14a, are connected by way of a two-way switch 15 to one or other of two common lines. Each switch 15 has, as shown diagrammatically in Figure 1A, a common terminal 16 and two switched terminals 17 and 18. The terminal 17 is connected by way of a first common line 19 to a terminal 20 and the terminal 18 is connected by way of a SUBSTITUTE SHEET second common line 21 to an external terminal 22. Each switch has also an enabling input 23 which is controlled by a respective one of a mul ibit digital signal appearing on a line (diagrammatically represented) 24. The converters shown in Figure IB and Figure IC have been represented in simplified form for the sake of ease of explanation. Several stages and the digit lines have been omitted. However in reality these converters differ from the converter shown in Figure 1A by the use of different ones of the external terminals 10, 20 and 22 and by the addition of an output operational amplifier which converts the current output of the converter into a voltage output. For example, in Figure IB there is interposed between the terminal 10 and the node 12 for the most significant digit an operational amplifier 25; the node 12 is coupled to the non-inverting input of the operational amplifier 25 and a feedback line 26 extends from the output of the converter back to the inverting input thereof. In the configuration shown in Figure IB the terminal 20 is earthed and the terminal 22 is connected to an appropriate reference voltage. The converter shown in Figure IC is similar to that shown in Figure IB but has the inputs and outputs interchanged so that the terminal 10 -is coupled to a reference voltage and the common line 21 is coupled to the inverting input of a operational amplifier 25 of which the non-inverting input is earthed. A feedback resistor 27 is coupled from the output terminal 22 to the inverting input of the amplifier. SUBSTITUTE SHEET All these forms of R-2R digital to analog converter operate in a similar manner. The easiest to understand is that shown in Figure IC, wherein a reference voltage is applied to the terminal 10. If one considers first the node 12a at the right hand end of the network, the series impedance presented to this node by the terminating resistor 14a is 2R where R is some suitable value such as 10 kilohms and the shunt impedance presented to this node is likewise 2R, irrespective , of the position of the respective switch 15a, on the assumption that the switch has zero resistance when conductive and infinite resistance when it is non-conductive and also on the assumption (which is easy to realise) that the input impedance of the operational amplifier is zero. The effective impedance at that node 12a is that of the two resistors in parallel; the effective impedance is accordingly R. At the next node 12b to the left, the series impedance presented to the node is the resistance of the resistor 13a in series with the effective impedance of the resistors 14a and 14b; thus this series resistance is equal to 2R. Accordingly, the network is iterative, wherein at each node the series resistance and the shunt resistance are equal irrespective of the number of stages, again on the assumption that each switch 15 has in its conductive branch zero impedance and in its non-conductive branch infinite impedance. Under these conditions, a current entering the first node 12' from the reference terminal 10 divides equally between the shunt and series branches irrespective of the position of the switch 15 in the respective shunt branch. This process is repeated at each node. The switches divert "the currents in the shunt branches to one or other of the lines 19 and 21 and the contribution to each output current is SUBSTITUTE SHEET proportional to the binary power of the digit controlling the respective switch: this achieves the required digital to analog conversion. Since the network is theoretically linear, the reciprocity theorem applies, and Figure IB is merely the converter as shown in Figure IC, the source and load being interchanged. Figure 1A shows a more usual arrangement in which the reference terminals 20 and 22 are coupled to respective reference voltages but the operation is still essentially the same as before. The accuracy of the converter in any of its forms clearly therefore depends upon the resistances of each series branch or arm being exactly half that of the respective shunt branch or leg. Since the switches 15 are semiconductive switches and, preferably, complementary metal oxide semiconductor switches, this provision does not hold true and, as mentioned hitherto, the non-linearity arising from the non-zero resistance of the switch in the conductive state renders the converters unusable for digital words having more than five or six bits. Figure 2 illustrates one form of the present invention. In the configuration shown in Figure 2, each switch 15 is now directly connected to the respective node 12 and the terminals 17 and 18 are connected by way of respective resistors (14' and 14"), each of 2R ohms to the respective one of the common lines 19 and 21. In this embodiment the line 21 is earthed and the line 19 is connected to a reference voltage terminal. Although this modification involves a doubling of the number of shunt resistors (with SUBSTITUTE SHEET the exception of the terminating resistor) it does not represent an increase in current consumption because current flowing through a shunt branch or leg will flow through only one of these resistors at a time. Further according to the embodiment shown in Figure 2, interposed in each series branch or arm is a switch device 28. This switch device preferably physically matches the switch device 15. In particular, each switch device 15 preferably comprises two CMOS switches connecting the terminal 16 to the terminals 17 and 18 respectively. An initial assumption may be made that the conducting resistance of each of these two switches is of the same order of magnitude. Preferably therefore the switch device 28 comprises two CMOS switches in parallel and configured (or alternatively controlled) so that they are dummy switches, that is to say always closed during operation of the converter. This means that the effective resistance of the dummy switch arrangement is, since it consists of two switches in parallel, half that of the . resistance of a switch 15. Thus if the resistance of each shunt leg is 2R + r, where r is the resistance of a conductive CMOS switch, the resistance of the series arm will be (R + r/2) and the theoretical relationship required for the accurate operation of the converter is closely approached even though r may be substantial. The terminating resistor does not require a dummy switch like the device 28. Instead, a switch 15d is provided, the common terminal thereof being connected to the node 12a and the terminating resistor 14a being connected to the terminal 18d (corresponding to terminal 18) of switch 15d. The enable input of the switch is connected to the (earthed) SUBSTITUTE SHEET reference line 21 so that the switch 15d is rendered as a dummy switch having the same resistance as the other switches 15. Of course, the switch 15d is disposed so that the terminating resistor 14a is always in circuit and the terminal 17d is left open-circuited. The dummy switch means in the embodiment shown in Figure 3 comprises two complementary switches 31 and 32 which are adapted to be permanently closed and in parallel between a first terminal 29, to be connected to the adjacent upstream node 12, and a second terminal 30, to be connected to one end of the respective series resistor 13. The complementary (CMOS) switch 31 comprises an n-type transistor 31n and a p-type transistor 31p and the complementary (CMOS) switch 32 comprises an n-type transistor 32n and a p-type transistor 32p. Reference voltage AVD is applied to the gates of the n-type devices and to the substrate contacts 33 of the p-type devices and reference voltage AVS is applied to the gates of the p-type devices and the substrate contacts 34 of the n-type devices. The sources of the transistors are all connected to the terminal 29 and the drains of the transistors are all connected to the terminal 30. Thus the arrangement constitutes two closed CMOS switches 31 and 32 which are in parallel. Figure 4 illustrates a preferred form for the switch means 15. The switch means has a common terminal 16 and two switched termiiials 17 and 18, each of which will be connected to one of the respective 2R resistors 14' and 14" . A first CMOS switch 41, comprising an n-type transistor 41n and a p-type transistor 41p is connected between terminals 16 and 17 and a second CMOS switch 42, comprising an n-type transistor 42n and a p-type transistor 42p, is connected SUBSTITUTE SHEET between terminals 16 and 18. The gates of the transistors 41n and 42p are connected together and the gates of the transistors 41p and 42n are connected together. Reference voltages AVS and AVD are applied to the substrate contacts of the n-type devices and p-type devices respectively. An operating switch network 43 is coupled to the respective digit line 24 so as to render one or other of the complementary switches 41 and 42 conductive according as the voltage on the digit line is 'high' or 'low' . The network 43 comprises three complementary switches 44, 45 and 46. The digit line 24 is connected to the gates of both transistors 44n and 44p. The source of the n-type device 44n is connected to the drain of the p-type device and to the gates of the devices in the next CMOS switch 45. The drain of the n-type device 44n is connected by line 47 to the reference voltage AVD and the source of the p-type device 44p is connected by line 48 to the reference voltage AVS. The succeeding devices are correspondingly connected. The node 49 common to the gates of the switch 46 is connected to the gates of the device 41n and 42p and the node 50 common to the source of device 46n and the drain of the device 46ρ is connected to the gates of the devices 41p and 42n. This (known) form of network will render either the transistors 41n and 41p conductive (when line 24 is 'high') or the transistors 42n and 42p conductive (when line 24 is • low'). It will be readily understood that the dummy switches 28 should be physically matched to the shunt switches 15. This is achieved during fabrication of the integrated circuit which includes the converter by matching the complementary switches; this may be achieved by making the n-type devices SUBSTITUTE SHEET in switches 31, 32 41 and 42 all the same size and the p-type devices in the same switches all the same size. An advantage of using complementary devices is that whereas the switch resistances in the conductive states of p-devices and n-devices vary conversely with terminal voltage, there is a substantial range (typically 1 to 4 volts) of terminal voltage for which the resistance of a conductive complementary switch is substantially constant (typically about 80 ohms). In the embodiment of Figure 2 each switch 15 and the respective dummy switches are connected directly to the respective node 12. The advantage of this is that each switch 15 and the respective dummy switches 28 have the same terminal voltage and accordingly variation due to dependency of the switches' resistances on terminal voltage is reduced. However, the invention includes within its broadest scope other arrangements. For example, a resistor of R' ohms may be inserted between terminal 16 and the respective node 12 provided that the resistors 14' and 14" are each reduced to (2R-R' ) ohms, though this is less preferred. Other modifications will readily be apparent to those skilled in the art, and it is not desired to limit the invention to the foregoing details. SUBSTITUTESHEE'

Claims: - 13 - CLAIMS 1. A multiplying digital to analog converter comprising: an iterative ladder network (11) having series branches and shunt branches, each series branch including a first resistor means (13) , said series branches defining nodes (12) between successive series branches, said shunt branches comprising a respective switch (15) having a common terminal coupled to the respective node and two switchable terminals; a pair of second resistors (14',14' ') for each shunt branch, each second resistor having a resistance twice that of the said first resistor means and each second resistor being connected to a respective one of the said switchable terminals; means (14a, 15d) for terminating said network; a first line (19) connected to a first one of each pair of the shunt resistors; a second line (21) connected to a second one of each pair of shunt resistors; means (24) for operating each of said switches in accordance with a respective digit of a digital signal; and dummy switch means (28) in each series branch, characterised in that each dummy switch means consists of a pair of parallel substantially identical switches (31,32) each SUBSTITUTESHEE having a conductive resistance equal to that of a said respective switch. 2. A converter according to claim 1, in which the said common terminal of each said respective switch (15) is directly connected to the respective one of said nodes (12) and the dummy switches (31,32) of the respective series branch are connected directly to the respective one of the nodes. 3. A converter according to claim 1 in which each of said respective switches and each of the said dummy switch means comprises two CMOS switches. 4. A converter according to claim 3 in which each of said CMOS switches comprises an n-type transistor in parallel with a p-type transistor. 5. A multiplying digital to analog converter comprising: an iterative ladder network (11) having series branches and shunt branches, each series branch including a first resistor means (13), said series branches defining nodes (12) between successive series branches, said shunt branches comprising a respective shunt switch means (15) having a common terminal coupled to the respective node and two switchable terminals, said respective shunt switch means providing a respective pair of two selectable shunt paths each including a respective shunt switch (41,42) in series with a respective resistive means (14' ,14' ' ) each having twice the resistance of said first resistor means; SUBSTITUTE SHEET a first line (19) connected to a first one of each pair of the shunt paths; a second line (21) connected to a second one of each pair of shunt paths; means (14a,15d) for terminating said network; means (24) for operating each of said shunt switch means in accordance with a respective digit of a digital signal; and respective dummy switch means (28) in each series branch, characterised in that each said respective dummy switch means essentially consists of two parallel switches (31,32) each physically corresponding to a said shunt switch (41,42). 6. A converter according to claim 5 in which each of said shunt switches and each of the switches in the dummy switch means comprises a respective CMOS switch comprising an n-type transistor in parallel with a p-type transistor. 7. A converter according to claim 5 in which said means for terminating comprises one of said shunt switches in series with a terminating resistor means having the same resistance as one of said resistive means. 8. A multiplying digital to analog converter comprising: an iterative ladder network (11) having series branches and shunt branches, each series branch including a first resistor means (13), said series branches defining nodes SUBSTITUTESHEET (12) between successive series branches, said shunt branches coiivprising a respective switch (15) having a common terminal, connected to the respective node, and two switchable terminals; a pair of similar second resistors (14',14' ') for each shunt branch, each second resistor having a resistance twice that of the said resistor means and each second resistor being connected to a respective one of the said switchable terminals; means (14a,15d) for terminating said network; a first line (19) connected to a first one of each pair of the shunt resistors; a second line (21) connected to a second one of each pair of shunt resistors; means (24) for operating each of said switches in accordance with a respective digit of a digital signal; and dummy switch means (28) in each series branch, characterised in that the said switches and the said dummy switch means are physically substantially identical and in that each dummy switch means is configured to correspond to a said switch in which the said switchable terminals are connected together. 9. A converter according to claim 8 in which each of said switches (15) and each of the dummy switch means (28) comprises two CMOS switches, each CMOS switch being S UBS TITUTE SHEET constituted by a p-type transistor in parallel with an n-type transistor. 10. An integrated circuit including an R to 2R digital to analog converter having a multiplicity of sections each including a series arm (13) and a shunt leg (14) wherein said shunt leg includes a semiconductive switch means (15) for providing two alternative shunt paths of similar resistance, the semiconductive switch means having a substantial switch resistance when conductive and comprising two alternatively operable substantially identical switches (41,42) and wherein the series arm has a resistance corresponding to half the resistance of one of the said alternative shunt paths, and dummy switch means (28) in each series arm; characterised in that each said dummy switch means (28) physically corresponds to the said semiconductive switch means (15) and comprises two substantially identical switches (31,32) which are disposed in parallel. SUBSTITUTE SHEET

Inventors: MORLON PATRICE PIERRE, MORLON, PATRICE, PIERRE
Applicants: VLSI TECHNOLOGY INC
Application year: 1990
Main classification: H03M1
IPC codes: H03M1