Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit includes a first FET (Q1) serving as a transfer gate for controlling transfer of a high frequency signal, a first and a second capacitors (C1, C2) connected to a gate of the first FET (Q1) directly or through a resistor (R) or a 1/4 wavelength line, a second FET (Q2) having its drain connected to the first capacitor (C1) and its source grounded at a high frequency band, and a third FET (Q3) having its drain connected to said second capacitor (C2) and its source grounded at a high frequency band. The semiconductor integrated circuit may further comprise a second resistor (R2) connected to the first capacitor (C1) in parallel, a third resistor (R3) connected to the second capacitor (C2) in parallel and a fourth resistor (R4) having one end connected to a connecting point (S3) between the second resistor (R2) and the third resistor (R3) and the other end fixed to a certain potential.

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit for a high frequency band such as a microwave band. BACKGROUND OF THE INVENTION Figure 4 shows a conventional semiconductor integrated circuit. In figure 4, reference numeral Q1 designates a field effect transistor (referred to as an FET hereinafter) and reference numerals T1 and T2 designate microwave lines connected to a source and a drain of the FETQ1, respectively. Reference numerals C5 and C6 designate capacitors connected to the microwave lines T1 and T2, respectively. Reference numeral R1 designates a resistor connected to a gate of the FETQ1, reference numeral C8 designates a capacitor connected to the resistor R1, reference numeral T3 designates a 1/4 wavelength line connected to the microwave line T1 and the capacitor C5, and reference numeral C7 designates a capacitor connected to the microwave line T3. Next, operation thereof will be described. A drive signal input terminal S3 connected to a connecting point between the resistor R1 and the capacitor C8 is used to perform switching operation of the FETQ1. In addition, the 1/4 wavelength line T3 and the capacitor C7 serve as a circuit for source voltage bias of the FETQ1, which source voltage bias of the FETQ1 is applied from a power supply terminal V3 connected to a connecting point between the 1/4 wavelength line T3 and the capacitor C7. A high frequency signal is input from Rin and output to Rout. When the drive signal input terminal S3 becomes high, the FETQ1 is turned ON and the high frequency signal input from the Rin is output to the Rout. When the drive signal input terminal S3 becomes low, the FETQ1 is turned OFF and the high frequency signal input from the Rin is not output to the Rout. The resistor R1 is generally set sufficiently higher than line impedance of the microwave lines T1 and T2. Therefore, when the FETQ1 is ON, the high frequency signal is prevented from being leaked to the gate side of the FETQ1 by capacitance Cgs between the gate and source of the FETQ1. In addition, when mutual conductance Gm of the FETQ1 is fairly high, oscillation can be prevented. Furthermore, electrostatic destruction of the gate of the FETQ1 can be prevented. The capacitor C8 and the resistor R1 serve as a RC low-pass filter circuit in which capacitance of the capacitor C8 is set at a large value so as to be sufficiently low impedance to the high frequency signal so that the high frequency signal may not be leaked from the input terminal S3. In addition, although the resistor R1 is used in the example shown in figure 4, a 1/4 wavelength line is sometimes used instead of the resistor R1. Since the conventional semiconductor integrated circuit is structured as described above, a considerably large drive circuit such as a TTL circuit is required in order to control a potential of the drive signal input terminal S3, to drive the capacitor C8 and the gate of the FETQ1, with the result that power consumption is increased and a switching speed of the FETQ1 is slow because it is necessary to charge and discharge the capacitor C8. SUMMARY OF THE INVENTION The present invention was made to solve the above problem and it is an object of the present invention to provide a semiconductor integrated circuit in which power consumption is reduced and a gate of an FETQ1 can be driven at high speed because charging and discharging of a capacitor C8 is dispensed with. It is another object of the present invention to provide a semiconductor integrated circuit in which a signal for gate driving can be easily obtained by generating the same inside the integrated circuit. Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications will become apparent to those skilled in the art from this detailed description. A semiconductor integrated circuit in accordance with the present invention comprises a first FET serving as a transfer gate controlling transfer of a high frequency signal, a first and a second capacitors connected to a gate of the first FET directly or through a resistor or a 1/4 wavelength line, a second FET having its drain connected to the first capacitor and its source grounded at a high frequency band, and a third FET having its drain connected to the second capacitor and its source grounded at a high frequency band. A semiconductor integrated circuit in accordance with the present invention further comprises a second resistor connected to the first capacitor in parallel, a third resistor connected to the second capacitor in parallel and a fourth resistor having one end connected to a connecting point between the second resistor and the third resistor and the other end fixed to a certain potential. According to the present invention, the first capacitor transfers the high frequency signal by the second FET when the first FET is ON and the second capacitor transfers the high frequency signal by the third FET when the first FET is OFF, so that the high frequency signal is grounded at a high frequency band through the first capacitor or the second capacitor in both cases where the first FET is ON and OFF. Therefore, the first and second capacitors play the same role as the capacitor C8 in the prior art. However, this invention is different from the prior art in that the first and second capacitors are electrically made to be a floating state by the second and third FET's in accordance with the ON or OFF state of the first FET, so that charging and discharging of the capacitor is dispensed with. As a result, power consumption is reduced and the gate of the first FET can be driven at a high speed because there is no delay due to charging and discharging of the capacitor. In addition, according to the present invention, since the second, third and fourth resistors are further provided, a potential necessary for the gate of the first FET to be driven can be generated by those resistors. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram showing a semiconductor integrated circuit in accordance with a first embodiment of the present invention; Figure 2 is a diagram showing an input voltage waveform to each terminal of the semiconductor integrated circuit shown in figure 1; Figure 3 is a diagram showing a semiconductor integrated circuit in accordance with a second embodiment of the present invention; and Figure 4 is a diagram showing a conventional semiconductor integrated circuit. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail in reference to drawings. Figure 1 shows a semiconductor integrated circuit in accordance with a first embodiment of the present invention. In figure 1, reference numeral Q1 designates a first FET serving as a transfer gate controlling transfer of a high frequency signal, and reference numerals T1 and T2 designate microwave lines connected to a source and a drain of the FETQ1, respectively. Reference numerals C5 and C6 designate DC cutting capacitors, references Rin and Rout designate microwave input/output terminals through which a high frequency signal such as a microwave signal is input or output, and reference numeral T3 designates a 1/4 wavelength line serving as a part of a source bias circuit of the FETQ1. Reference numeral C7 designates a capacitor for grounding the high frequency signal, which also serves as a part of the source bias circuit of the FETQ1 together with the microwave line T1, reference numeral V3 designates a power supply terminal for source bias of the FETQ1, and reference numerals C1 and C2 designate a first and a second capacitors connected to a gate of the FETQ1 through a resistor R1, respectively. Reference numeral Q2 designates a second FET having its drain connected to the capacitor C1 and its source grounded through the capacitor C3, reference numeral Q3 designates a third FET having its drain connected to the capacitor C2 and its source grounded through the capacitor C4, and reference numerals S1 and S2 designate drive signal input terminals connected to the gates of the second and third FET's Q2 and Q3, respectively. Reference numeral S3 designates a drive signal input terminal connected to a connecting point between the first and second capacitors C1 and C2 and the resistor R1, reference numerals V1 and V2 designate power supply terminals for source bias of the second and third FET's Q2 and Q3, respectively. Then, operation thereof will be described. Figure 2 shows an example of an input waveform of a drive signal in each of the drive signal input terminals S1 to S3 with time shown by the abscissa. It is assumed that a power supply terminal V3 is grounded (0V) in a DC manner, a source potential of the FETQ1 is 0V and a pinch off (cut-off) voltage of the FETQ1 is Vp. In addition, it is assumed that the FET is a normally ON type and when a voltage of -Vp is applied between the gate and source thereof, the FET is turned OFF. At this time, as shown in figure 2, if the drive signal input to the terminal S3 is set at 0v at high level and -Vp at low level, the FETQ1 performs ON/OFF switching operation and then an output waveform shown in figure 2 is obtained from the microwave output terminal Rout corresponding to the switching operation of the FETQ1. Then, a potential of the power supply terminal V1 is set at 0V and a signal is input from the terminal S1, which signal rises, reaches 0v and falls while an input voltage of the terminal S3 is 0v, and it is at -Vp while the input voltage of the terminal S3 is -Vp as shown in figure 2. At this time, only when 0V is input to the terminal S1 and the terminal S3 and the terminal V1 become the same potential of 0v, the FETQ2 is turned ON. In this ON state, an electric charge amount Q c1 , which corresponds to a potential difference V c1 between the terminals S3 and V1, is stored in the capacitor C1. More specifically, if capacitance of the capacitor C1 is C c1 , the electric charge amount Q c1 is as follows: V c1 X C c1 = Q c1 In this embodiment, if there is no voltage fall at the FETQ2, the voltage V c1 across the capacitor C1 can be always 0V. In addition, when the input voltage of the terminal S1 becomes -V p , the FETQ2 is turned OFF, so that the electric charge amount Q c1 is stored in the capacitor C1 as it is. As a result, a potential across the capacitor C1 is always kept at a constant value. When the input voltages of the terminal S1 and the terminal S3 become 0V again, the FETQ2 is turned ON as described above, but storage of an electric charge does not happen because the electric charge amount Q c1 is already stored in the capacitor C1 and both ends of the capacitor C1 are at the same potential. Then, a potential of the power supply terminal V2 is set at -Vp and a signal is input from the terminal S2, which signal rises, reaches -Vp and falls while the input voltage of the terminal S3 is -Vp and it is at -2Vp while the input voltage of the terminal S3 is 0V as shown in figure 2. Thus, only when the terminal S3 and the terminal V2 are at the same potential of -Vp, the FETQ3 is turned ON. Therefore, at this time, the electric charge amount Q c2 , which corresponds to a potential difference between the terminals S3 and V2, is stored in the capacitor C2. In this embodiment, if there is no voltage fall at the FETQ3, a voltage across the capacitor is 0V. When the input voltage of the terminal S2 becomes -2Vp, the FETQ3 is turned OFF, so that the electric charge amount Q c2 is stored in the capacitor C2 as it is. As a result, both ends of the capacitor C2 are always kept at a constant value. Then, when the input potential of the terminal S2 becomes -Vp again, the FETQ3 is turned ON. However, since the electric charge amount Q c2 is already stored in the capacitor C2, both ends of the capacitor C2 become the same potential, so that store of an electric charge into the capacitor C2 does not arise. Therefore, since either FETQ2 or FETQ3 can be turned ON except when the input voltage of the terminal S3 rises or falls in this construction, the gate of the FETQ1 can be always grounded (except when it rises or falls) at a high frequency band by the capacitor C1 or C2 through the resistor R1. As a result, the same effect as in the conventional circuit shown in figure 4 can be obtained. In addition, as described above, the capacitors C1 and C2 are made to electrically be in a floating state by the FET's Q2 and Q3, respectively in accordance with ON or OFF state of the FETQ1 in which they are electrically insulated from the outside so that an electric charge may not flow into them. Therefore, voltages across the capacitors C1 and C2 can be always constant (0V in this embodiment). As a result, power consumption can be reduced because charging or discharging of the capacitor can be dispensed with. In addition, there is no delay of time due to charging or discharging of the capacitor, thereby the FETQ1 can be driven at high speed. As described above, a switching circuit with high performance for a high frequency band can be implemented by using the thus constructed semiconductor integrated circuit. In addition, the FETQ1 can be used as an attenuator or an amplifier when it is turned ON or OFF in a halfway manner. Furthermore, it can be used as a gate grounded type impedance converter by applying a bias circuit to the drain of the FETQ1. Figure 3 shows a semiconductor integrated circuit in accordance with a second embodiment of the present invention. In figure 3, the same references as in figure 1 designate the same part. Reference numerals R2 and R3 designate a second and a third resistors connected to the first capacitor C1 and the second capacitor C2 in parallel, respectively. Reference numeral R4 designates a fourth resistor for grounding a connecting point between the first and second capacitors C1 and C2 and the resistor R1. Then, operation thereof will be described. When a signal voltage shown in figure 2 is input to the drive signal input terminals S1 and S2, a potential of a node S3 is determined by values of the resistors R2 and R4 when the FETQ2 is ON. When a potential of the power supply terminal V1 is 0V, a potential of the terminal S3 is 0V. When the FETQ2 is OFF, a potential of the node S3 is determined by values of the resistors R3 and R4. For example, when a potential of the power supply terminal V2 is -Vp, a potential of the terminal S3 is as follows; -Vp · R4 / ( R3 + R4) If the value of the resistor R4 is set so as to be considerably larger than that of the resistor R3, a potential of the terminal S3 can be almost equal to -Vp. Therefore, an input signal necessary for the node S3 can be composed from the input signal to the drive signal input terminals S1 and S2. Although the connecting point between the capacitors C1 and C2 and the resistor R1 is grounded through the resistor R4 in the above embodiment, this is not necessarily a grounding potential and may be a fixed potential determined by correlation between the input voltages to the terminals S1, S2, V1, V2 and V3. In addition, although the resistor R1 is provided so that impedance may be considerably higher than the line impedance of the microwave lines T1 and T2 in the above embodiment, the resistor R1 can be dispensed with and they may be directly connected if considerably high impedance can be obtained. In addition, instead of the resistor, the 1/4 wavelength line, or the resistor and the 1/4 wavelength line which are connected in series, may be provided. Although the normally ON type FET is used in the above embodiment, the same effect can be obtained even when a normally OFF type FET is used. In addition, in the above embodiment, as shown in figure 2, the input signal to the terminal S1 is set such that it rises, reaches 0V and falls while the input voltage of the terminal S3 is 0V and it is -Vp while the input voltage of the terminal S3 is -Vp. Furthermore, the input signal to the terminal S2 is set such that it rises, reaches -Vp and falls while the input voltage of the terminal S3 is -Vp and it is -2Vp while the input voltage of the terminal S3 is 0V. However, the input signal to the terminal S1 may be set such that it is 0v while the input voltage of the terminal S3 is 0V and it is -Vp while the input voltage of the terminal S3 is Vp and the input signal to the terminal S2 may be set such that it is -Vp while the input voltage of the terminal S3 is -Vp and it is -2Vp while the input voltage of the terminal S3 is 0V. In this case, the gate of the FETQ1 can be always grounded by either capacitor C1 or C2 at a high frequency band through the resistor R1 even when the input voltage rises or falls. In addition, although potentials of the power supply terminals V1, V2 and V3 are set at 0V, -Vp and 0V, respectively in the above embodiments, these can be set at any value if the FET's Q1, Q2 and Q3 operate. Although a description is given of the microwave circuit using the microwave line in the above embodiments, it is needless to say that the same effect can be obtained if the FETQ1 serves as a transfer gate for controlling transfer of a high frequency signal even without the microwave lines T1 to T3 and capacitors C5 to C7. As described above, a semiconductor integrated circuit in accordance with the present invention comprises a first FET serving as a transfer gate controlling transfer of a high frequency signal, a first and a second capacitors connected to a gate of the first FET directly or through a resistor or a 1/4 wavelength line, a second FET having its drain connected to the first capacitor and its source grounded at a high frequency band and a third FET having its drain connected to the second capacitor and its source grounded at a high frequency band. Therefore, the first and second capacitors can be electrically in a floating state by the second and third FET's, respectively in accordance with ON or OFF state of the first FET. As a result, power consumption is reduced and there is no delay of time because charging or discharging of the capacitor can be dispensed with, whereby the first FET can be driven at high speed. Furthermore, a semiconductor integrated circuit in accordance with the present invention comprises a second resistor connected to the first capacitor in parallel, a third resistor connected to the second capacitor in parallel, a fourth resistor having one end connected to a connecting point between the second resistor and the third resistor and the other end fixed to a certain potential. Therefore, in addition to the above effect, there can be provided a high frequency semiconductor integrated circuit with high performance in which a potential required when the first FET is driven can be provided by these resistors and a signal necessary for gate driving can be easily provided.

Claims: A semiconductor integrated circuit, with a first FET (Q1) serving as a transfer gate controlling transfer of a high frequency signal applied at its source terminal, under control of a drive input signal obtained at a node (S3), characterised by a first and a second capacitor (C1,C2) having first ends connected to said node (S3) and also connected to a gate of said first FET (Q1) directly or through a resistor (R1) or a 1/4 wavelength line; a second FET (Q2) having its drain connected to a second end of said first capacitor (C1), and its source grounded at high frequency and its gate controlled by a first input signal; and a third FET (Q3) having its drain connected to a second end of said second capacitor (C2), its source grounded at high frequency and its gate controlled by a second input signal. A semiconductor integrated circuit as claimed in claim 1, further characterized by a second resistor (R2) connected to said first capacitor (C1) in parallel; a third resistor (R3) connected to said second capacitor (C2) in parallel; and a fourth resistor (R4) having one end connected to said node (S3) between said second and third resistors (R2, R3) and the other end fixed to a certain potential. A semiconductor integrated circuit as claimed in claims 1 or 2, characterized in that said first FET (Q1) comprises a normally ON type FET or normally OFF type FET. A semiconductor integrated circuit as claimed in one of the claims 1 to 3, characterized in that a drain terminal of said first FET (Q1) is connected to a microwave output terminal (Rout) through a microwave line (T2) and said source terminal of said first FET (Q1) is connected to a microwave input terminal (Rin) through a further microwave line (T1). A semiconductor integrated circuit as claimed in claim 4, characterized by DC cutting capacitors (C6, C5) between said microwave line (T2) and said microwave output terminal (Rout) and between said further microwave line (T1) and the microwave input terminal (Rin). A semiconductor integrated circuit as claimed in claims 4 or 5, characterized in that a source terminal of said first FET (Q1) is connected to a source bias circuit (T3, C7).

Inventors: TANINO NORIYUKI, TANINO, NORIYUKI, TANINO, NORIYUKI, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H03K17
IPC codes: H01P1, H03K17