Superconducting interconnection apparatus

Abstract: A structure connecting superconductor transmission lines to integrated circuits comprises a plurality of interconnection substrates having superconducting transmission path deposited thereon in contact with metallic contact areas, and integrated circuit chip carrier substrates for mounting integrated circuits and having metallic contact areas. The substrates are mounted in a retainer structure and are separated by spacers which have apertures in registration with the contact areas. Contact devices are selectively inserted in the apertures to establish an interconnection pattern between the substrates. The retainer structure applies force to the substrates to assure physical contact between the substrates and the contact device. The structure may be assembled and disassembled for replacement of parts or reconfiguration of interconnections, without the application of heat or other processes which are incompatible with relatively brittle and heat sensitive superconducting materials. The complete structure may be submerged in a bath of liquid nitrogen for cooling. The space provided by the spacers allows for access by the cooling liquid to the superconducing material on the substrates.

Description: This invention relates to electrical interconnection apparatus, and to apparatus for interconnecting superconducting transmission paths to integrated circuit chips. A problem of the prior art in highly integrated electronic circuitry is the physical design to physically support the integrated circuit chip, to make connections to the chip and provide transmission paths for high-frequency electronic signals transmitted by the integrated circuit. In the prior art, thin lines of metallic conductors, such as copper, have been deposited on substrates and connected by solder connection to the integrated circuits. Typically, conductors are deposited on both sides of a substrate and feed through holes are provided through the board to allow solder connections to be made to the conductors on either side. Furthermore, complex cross-over arrangements of plated metallic conductors are used in the prior art in order to support more transmission lines in a small area on a substrate in close proximity to the integrated circuit chip. The recent discovery of ceramic materials which have superconducting properties at higher temperatures has stirred a renewed interest in practical application for superconductor materials. Ceramics, such as the commercially available material sometimes referred to as 1-2-3 ceramic material (Y₁Ba₂Cu₃O 7) which is superconducting at the temperature of liquid nitrogen (N₂), e.g., approximately 77 degrees Kelvin, can be deposited in thin layers and have desirable properties for the transmission of high-frequency signals. A problem is the construction of a carrier by which the superconducting lines can be brought into contact with the integrated circuit chips, since the techniques for fabricating and intercontacting the metallic striplines such as soldering and cross-over structures are incompatible with superconductor materials which are more brittle and more sensitive to the application of heat required. IBM Journal of Research and Development, Vol. 24, No. 2, March 1980, pages 167-171, describes an arrangement for interconnecting circuit boards and chips for use at cryogenic temperatures using superconducting strip lines and balls of mercury entrapped by surface tension in a matrix of cavities to provide pin-to-pin electrical contact. According to one aspect of this invention there is provided electrical interconnection apparatus as claimed in claim 1. According to another aspect of this invention there is provided apparatus as claimed in claim 11. In one embodiment of the invention, an assembly of substrates comprises an interconnection substrate and an integrated circuit carrier substrate, with the substrates each having metallic conductor contact areas which are forced in contact with each other by mechanical pressure. In another embodiment of the invention, the carrier substrate may be provided with metallic conductors on opposing surfaces and brought in contact with metallic conductors on a pair of substrates to increase the number of paths available to the a chip carrier substrate. The contact may be made between substrates by providing matching lands on the metallic conducting material where the contact is made between substrates. Alternatively, a spacer having a plurality of openings may be inserted between the metallic surfaces of the substrates to be brought in contact, and spherical or the like shaped contact devices consisting of conducting material may be selectively inserted in openings in the spacer material to selectively establish a pattern of interconnections between substrates. Advantageously, the interconnection substrates, the chip carriers and spacers may be formed into a multiple layer stack structure with electrical contact established between layers by the pieces of.conducting material inserted in apertures of the spacers. Furthermore, carrier substrates and interconnection substrates may be independently manufactured, and the substrates may be assembled into a circuit structure without soldering or other manufacturing techniques which may be incompatible with superconducting materials. Advantageously, a repairable and reconfigurable integrated circuit structure is provided since individual layers may be removed and replaced without affecting other layers of the structure. In one embodiment of the invention, a structure for connecting to a plurality of integrated circuits is made up of a plurality of layers of interconnection ubstrates having superconductive materials deposited thereon and carrier substrates having integrated circuit chips attached thereto, all connections to the integrated circuits being made via metallic conductors on the edges of the integrated circuit carrier which are selectively brought into contact with metallic conductors on the edges of interconnection substrates at opposing surfaces of the carrier substrate, and the interconnecting substrates carrying superconducting transmission paths are selectively brought in contact with each other by means of metallic edge conductors, in order to provide a completed circuit structure. Superconducting stripline transmission paths, comprising superconducting signal paths and ground planes, may be deposited on interconnection substrates. In one specific embodiment, an integrated circuit device mounted on the carrier substrate is comprised of optical receivers and transmitters, and fiber optic conductors are brought into proximity with the integrated circuits through apertures provided in the interconnection carriers. Brief Description of the Drawing The invention may be better understood from the following detailed description when read with reference to the drawing in which: FIG. 1 is a representation of a multi-layered structure of substrates including interconnection substrates for supporting superconducting transmission lines and integrated circuit carrier substrates, FIG. 2 is a cross section of the structure of FIG. 1 along line 2-2. FIG. 3 and 4 represent top views of exemplary interconnection substrates; and FIG. 5 is a top view of an exemplary intersubstrate spacer. Detailed Description FIG. 1 is a representation of an integrated circuit carrier structure including a plurality of interconnection substrates 10 separated by spacers 15. FIG. 1 shows optical cables 20 and 22 which provide access to integrated circuit chips on carrier substrates disposed internal to the structure of FIG. 1 and accessible via aperture 30 which extends through various layers of the structure of FIG. 1. Apparatus for applying vertical pressure to keep the layers of the sandwich structure in tight contact comprises horizontally extending bars 35 and vertically extending rods 37 provided with threaded ends and hold down nuts, for forming a clamp. Cover plates 40 may be made of any substantially rigid material for distributing the pressure across the upper and lower surface of the structure. Other arrangements for keeping the layers of the structure in tight contact may be readily devised. The structure of FIG. 1 may be submerged in a bath of liquid nitrogen to keep the superconducting material deposited on the interconnecting substrates at the desired temperature. The space between layers formed by the spacers 15 and the aperture 30, provide access for the cryogenic fluid to the superconducting material and also for the cooling of integrated circuits in the sandwich. FIG. 2 shows a cross section along the line 2-2 of FIG. 1. FIG. 2 shows a plurality of interconnection substrates 10 each of which have deposited thereon strips 112 of superconducting ceramic material and metallic conductive plating 114 in electrical contact with the superconducting strips which may be provided with solder connections (not shown) for external access to the substrates. The plating may, for example, be silver or other metallic electrically conductive material which will not attack the ceramic superconducting material. The ceramic material may be, for example, commercially available 1-2-3 material (Y₁Ba₂Cu₃O₇) which may be deposited on substrates, made for example of strontium titanate (S r T i O₃) material, in a well-known fashion. In the manufacture of the interconnection substrates, the metallic conductors are plated on to the substrate before the superconducting material is deposited in contact with the metallic conductors to avoid heat damage to the superconducting material. Similarly, solder connections to the plated edge conductors to provide external access to the substrates are made before the superconducting material is deposited on the substrate. The substrates 10 are separated by spacers 15 which may be made of a phenolic or other suitable insulating material. Each of the spacers 15 is provided with a plurality of apertures 125, shown in greater detail in FIG. 5, in registration with plated metallic edge conductors 114 on substrates above and below the spacer. Contact devices 120 which may be, for example, a spherically shaped mallable conductive material such as indium, may be selectively inserted in the apertures 125 to selectively establish electrical contact between edge conductors on adjacent substrates, as shown in FIG. 2. An integrated circuit chip 132, 134, shown in FIG. 2, may be mounted on a carrier substrate 135, 136 in a standard fashion, e.g., via connector 133, and standard metallic plated connections 137 may be made from the circuit chip to a plated edge conductor, e.g., 138. By means of an indium contact device 120, contact is made between the plated edge conductor 138 of the substrate 135 and the plated edge 114 of an interconnection substrate 10A, which is in electrical contact with a strip of superconducting material 112. Other connections from the carrier chip 135 to an interconnection substrate 10C can be made with the insertion of a contact device 120 in one of the spacer apertures 125. In this configuration, substrates 10B and 10D may serve to provide a connecting path between their adjacent substrates (e.g., 10A and 10C or 10C and 10E), but they also provide additional signal paths 112 to connection to the chips. Each of the interconnection substrates 10A through 10F in the illustrative embodiment are a form of a stripline transmission line with ceramic superconducting signal conductors on one surface of the substrate and a ceramic superconducting ground plane on the opposing surface of the substrate. By way of example, each of substrates 10A through 10F has superconducting signal path conductors 112 connected to the plated edge conductors 114 at the edge adjacent to aperture 30 and superconducting ground plane conductors 113 connected to plated edge conductors 115 at the external edge. The ground plane conductors 113 of the several interconnecting substrates are interconnected by means of edge conductors 115 and contact device 120 inserted in spacer apertures between edge conductors 115. Numerous other connections can be made between substrates by selective insertion of contact devices 120 in appropriate spacer apertures 125. By way of example, in the arrangement shown in FIG. 2, a connection is established between superconductive signal path 112 of interconnecting carrier 10B and integrated circuit chip 134 via edge conductors 114 of substrates 10B and 10C and edge conductor 139 of carrier substrate 136. The carrier substrates 135 and 136 are provided with flow through holes 150 to allow cryogenic fluid to enter the space between the carriers and to allow fluid in liquid or gaseous form to escape when the temperature of the structure is raised above that of liquid nitrogen. Optical fiber cables are shown at 20 and 22, which may contain a plurality of fibers individually communicating with electro-optical devices on the integrated circuit chips. Electrical wires, for example, to supply power to the integrated circuits may also enter the structure via aperture 30, reserving the superconducting paths on the interconnect substrates for high frequency signals. The arrangement of FIG. 2 is shown with two integrated circuit chips facing opposite directions to be accessible to optical fiber cables or the like. When no external access such as fiber optic cables 20 and 22 is needed, integrated circuits may be mounted on both surfaces of chip carrier substrates 135 and 136 and a number of additional chip carriers may be added in the stack structure. Additional apertures such as aperture 30 may be provided in the interconnection substrates 10A through 10D for supporting additional circuit carriers such as carriers 135 and 136. As shown in FIG. 2, certain of the interconnection substrates, for example substrates 10B and 10D have larger central apertures than other substrates, to allow overlapping of the edge conductors 138 and 139 of carrier substrates 135 and 136 with edge conductors 114 of adjacent interconnection substrates (e.g. 10C). This is shown further in FIGS. 3 and 4. FIG. 3 is a top view of an interconnection substrate such as substrate 10A with a central aperture 310, a plurality of superconducting signal paths 312 and aperture edge plated metallic conductors, e.g., 314, in contact with the superconducting strips. Further shown in FIG. 3 are outside edge plated metallic conductors for example 316. External edge conductor 317 is provided to connect to a ground plane on the opposite surface (not shown) of the substrate. FIG. 4 is a top view of an interconnection substrate, e.g., 10B having a larger central aperture 410. FIG. 4 incorporates a similar configuration of superconducting signal paths 412, aperture edge plated metallic conductors 414 and external edge plated metallic conductors 416. External edge conductor 417 is provided to connect to a ground plane on the opposite surface (not shown) of the substrate. Shown in FIG. 5 is a top view of a spacer assembly such as shown in FIG. 2. The assembly of FIG. 5 is constructed of separated sections 510 and 512 to provide an opening between adjacent layers of interconnection substrates allowing for the flow of cryogenic fluid to enhance cooling. The external sections 510 are each provided with a plurality of apertures 511 to be aligned with, for example, corresponding external edge plated conductors 316 of the structure of FIG. 3 or external edge plated conductors 416 of the structure of FIG. 4. Aperture 517 is positioned to be aligned with edge conductors 317 and 417 of FIGS. 3 and 4, respectively. The center section 512 is provided with an aperture 514 to be aligned with aperture 310 of FIG. 3 and in aperture 410 of FIG. 4. Spacer 512 is provided with apertures 516 which will be placed in alignment with external edge plated conductors 318 and 418 of FIGS. 3 and 4, respectively. The center section 512 is further provided with apertures 518 which are positioned to be placed in registration with the plated aperture edge conductors 314 of the substrate of FIG. 3, and apertures 520 positioned to be placed in registration with plated aperture edge conductors 315 of the substrate of FIG. 3. The center spacer section 512 is further provided with apertures S24 positioned to be placed in registration with both plated edge conductors 314 of FIG. 3 and 414 of FIG. 4. Similarly, apertures 522 of section 512 are positioned to be placed in registration with both plated edge conductors 315 of FIG. 3 and 415 of FIG. 4. It will be apparent that by insertion of a set of spacers as shown in FIG. 5 between a substrate of FIG. 3 and a substrate of FIG. 4 and inserting, for example, spheres of electrically conducting indium, connection may be selectively established between the plated conductors and hence the superconducting signaling paths of the subsrates of FIG. 3 and 4, as shown in FIG. 2. The plated conductors along the edges of the aperture 310 of the substrate of FIG. 3 are designed to extend further on the surface of the substrate to assure alignment with the double row of apertures e.g. 518, 520, 522, 524 around the center aperture, thereby allowing for electrical connection to a chip carrier as shown in FIG. 2.

Claims: Electrical interconnection apparatus comprising a plurality of substrates (10A) each with a plurality of contact areas (114,115) of metallic conductive material, and retaining means (37) for applying mechanical force to the substrates to urge them together, wherein superconducting material (112) is deposited on each substrate to form a signal transmission path and to make electrical contacts with respective contact areas, and spacer means (15) of electrically insulating material is disposed between adjacent substrates and has apertures (125) therein in registration with contact areas of adjacent substrates, CHARACTERISED IN THAT conductive contact devices (120) are provided for insertion in certain of said apertures for making selective electrical contacts between contact areas of adjacent substrates. Apparatus according to claim 1, wherein certain of said contact areas of one substrate are disposed on one surface of said one substrate and certain of said contact areas of another substrate are disposed on a surface of said other substrate positioned in opposing relationship to said one surface of said one substrate; said apparatus comprises a circuit chip carrier substrate (135) having first and second surfaces, circuit chip connector means on one of said surfaces of said carrier substrate, metallic electrically conducting contact areas on said first and said second surfaces, and electrical conductor means for interconnecting said circuit chip connector means and said contact areas on said first and second surfaces; and said carrier substrate is positioned in a space between the opposing surfaces of said one and said other substrate, certain of said contact areas of said carrier substrate being positioned substantially in alignment with at least one of said contact areas of each of said one and said other substrates, whereby electrical contact is made between said one and said other substrates and said circuit chip carrier substrate to provide the carrier substrate with access to superconducting transmission paths on said substrates when said apparatus is submerged in cryogenic fluid. Apparatus according to claim 2, comprising an additional substrate (10B) having two surfaces, at least one electrical contact area on each of said two surfaces of said additional substrate, superconductive material deposited on at least one of said surfaces of said additional substrate for forming a signal transmission path connected to certain of said contact areas of said additional substrate and a portion of said carrier substrate being positioned to occupy a first portion of said space between said one and said other substrates, said additional substrate being positioned between said one and said other substrates to occupy a second portion of said space, and at least one of said certain contact areas of said additional substrate being aligned with at least one contact area of said contact areas on said two opposing surfaces of the substrates, to provide additional signal path access to said carrier chip via one of said one and said other substrates. Apparatus according to claim 2, comprising electrically insulating spacer means disposed between said carrier substrate and said one and said other substrates and disposed between said additional substrate in said one and said other substrates, said spacer means comprising apertures in registration with contact areas of said one and said other substrate, said carrier substrate and said additional substrate; and electrical contact devices selectively inserted in certain of said apertures to selectively establish electrical contact paths between said carrier substrate and said one and said other substrates and between said additional substrate and said one and said other substrates. Apparatus according to claim 2, when used for connecting the superconducting transmission paths to the integrated circuit chip, wherein the carrier substrate and the interconnection substrates are positioned adjacent to one another with contact areas on each of said substrates aligned with a contact area of at least one other substrate; and the spacer means permits the flow of cryogenic fluid between said substrates for the cooling of said superconducting material. Apparatus according to claim 5, wherein superconducting material on one surface of each substrate acts as a ground plane to form stripline transmission lines on the interconnecting substrate, the spacer means are disposed between said substrates in locations other than said contact areas to allow for the flow of cryogenic fluid between said substrates for the cooling of said superconducting material, and said spacer means and said contact devices are removable from said retainer means to allow for replacement of substrates and rearrangement of interconnections, or the contact devices comprise indium. Apparatus according to claim 2, wherein each of the interconnection substrates is provided with an aperture in registration with a corresponding aperture in another interconnection substrate; said carrier substrate is disposed between said interconnection substrates and said connection means of said carrier substrate is positioned in alignment with said aperture in said interconnection substrates and edges of said carrier substrate are overlapping with edges of said apertures in said interconnection substrates; and said carrier substrate and said interconnection substrates each comprise contact areas on said overlapping edges for establishing electrical contact between said carrier substrate and both of said interconnection substrates. A pparatus according to claim 7, wherein an electro-optical circuit device is positioned on said integrated circuit carrier substrate in alignment with said apertures in said interconnection substrates and an optical signal transmission device is positioned in alignment with said apertures in said interconnection substrates for optical communication with said electro-optical circuit device. Apparatus according to claim 2, wherein each of said interconnection substrates comprises an aperture and said integrated circuit carrier substrate is positioned between two of said interconnection substrates, and has surfaces overlapping surfaces of said interconnection substrates; an integrated circuit chip is positioned on said integrated circuit chip carrier substrate in alignment with said apertures in said two interconnection substrates; metallic contact areas on said interconnection substrates and superconducting signal paths on said interconnecting substrates are in electrical contact with said contact areas; contact areas on said carrier substrate are in electrical contact with said integrated circuit chip, certain of said contact areas of said interconnecting substrates and said carrier substrate being located on said overlapping surfaces; the additional substrate has an aperture larger than said aperture of said two interconnection substrates and larger than the outside dimension of said integrated circuit carrier substrate, and disposed between said two interconnection carriers; said additional substrate having two surfaces and contact areas on both of said surfaces in alignment with contact areas on said two interconnection substrates; the spacer means is disposed between said carrier substrate and said two interconnection substrates and disposed between said additional substrate and said two interconnection substrates, said spacer means comprising apertures in registration with contact areas on said carrier substrate aligned with contact areas on said two interconnection substrates and apertures in registration with contact areas on said additional substrate in alignment with contact areas on said two interconnection substrates, said spacer means providing space between substrates to allow for the flow of cryogenic fluid for the cooling of superconducting materials; the contact devices are selectively inserted in said apertures of said spacer means to provide electrical connecting paths between aligned contact areas on adjacent surfaces; and the retainer means retains said substrates and said spacer means in alignment and to apply force to said substrates to maintain physical contact between said contact areas and said contact devices. Apparatus according to claim 9 wherein the apertures in each interconnection substrate are in registration, said carrier substrate is disposed between said interconnection substrates and said connection means of said carrier substrate is positioned in alignment with said aperture in said interconnection substrates and edges of said carrier substrate are overlapping with edges of said apertures in said interconnection substrates; and said carrier substrate and said interconnection substrates each comprise contact areas on said overlapping edges for establishing electrical contact between said carrier substrate and both of said interconnection substrates. Apparatus for interconnecting superconducting transmission paths to integrated circuit chips comprising: a plurality of interconnection substrates and at least one integrated circuit carrier substrate of predetermined external dimension; each of said interconnection substrates comprising an aperture and said integrated circuit carrier substrate positioned between two of said interconnection substrates, and having surfaces overlapping surfaces of said interconnection substrates; an integrated circuit chip positioned on said integrated circuit chip carrier substrate in alignment with said apertures in said two interconnection substrates; metallic contact areas on said interconnection substrates and superconducting signal paths on said interconnecting substrates in electrical contact with said contact areas; contact areas on said carrier substrate in electrical contact with said integrated circuit chip, certain of said contact areas of said interconnecting substrates and said carrier substrate located on said overlapping surfaces; spacer means disposed between said carrier substrate and said two interconnection substrates and disposed between said additional substrate and said two interconnection substrates, said spacer means comprising apertures in registration with contact areas on said carrier substrate aligned with contact areas on said two interconnection substrates; said spacer means providing space between substrates to allow for the flow of cryogenic fluid for the cooling of superconducting materials; contact devices selectively inserted in said apertures of said spacer means to provide electrical connecting paths between aligned contact areas on adjacent surfaces; and retainer means to retain said substrates and said spacer means in alignment and to apply force to said substrates to maintain physical contact between said contact areas and said contact devices.

Inventors: BRILEY BRUCE EDWIN, LARSON MIKIEL LOYAL, MONTSMA JOHN, BRILEY, BRUCE EDWIN, LARSON, MIKIEL LOYAL, MONTSMA, JOHN
Applicants: AT & T CORP, AT&T CORP.
Application year: 1990
Main classification: H01L39
IPC codes: H01L23, H01L39