NON-INTERLACED INTERLINE TRANSFER CCD IMAGE SENSING DEVICE WITH SIMPLIFIED ELECTRODE STRUCTURE FOR EACH PIXEL

Abstract: An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptors in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implant barrier region is formed under an edge of each electrode.

Description: NON-INTERLACED INTERLINE TRANSFER CCD IMAGE SENSING DEVICE WITH SIMPLIFIED ELECTRODE STRUCTURE FOR EACH PIXEL Reference to Co— ending Patent Application Reference is made to commonly assigned U.S. Patent Application Serial No. 309,646 entitled Interline Transfer CCD Image Sensing Device With Electrode Structure for Each Pixel to Losee et al, filed February 10, 1989. Technical Field This invention relates to image sensing devices and, more particularly, to interline transfer type charge coupled imagers with non-interlaced read—out. Background Art In interline transfer type imaging devices, photogenerated charge is collected on a photo charge collection site or photoreceptor, such as in a photodiode pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit. In an area array of such photocharge collection sites it is necessary to transfer the collected photocharge, first into a vertical shift register and then to a horizontal shift register, finally, reaching a charge sensitive detector or amplifier. In prior art interlaced devices and indicated schematically in FIGS. 1 and 2, alternate rows of photoreceptors are read out in sequence, odd numbered rows being associated with one, so called, field, and even numbered rows associated with a second field. More particularly, a given row of pixels 10 is addressed by application of a voltage to electrodes 20 and 30 which are both connected to the same vertical clock, Φ, . Upon application of this voltage, photocharge is transferred to the buried channel 40 of a vertical CCD shift register. This vertical shift register is composed of buried channel 40, electrodes 20 and 30, which are connected to vertical clock ,, and electrodes 50 and 60 which are connected to vertical clock Φ 2 - These electrodes are separated from the substrate semiconductor 70 by an insulating layer 80. The regions 65 beneath electrodes 30 and 60 are ion implanted to provide a potential energy difference between regions 25 and 26, controlled by the Φ-, clock, and between regions 55 and 56, controlled by the Φ 2 clock. To read out image information on, say, odd numbered rows of photosites, Φ, is pulsed in a manner to effect transfer of the photocharge from the photodiodes to the buried channel region under electrode 20. This photocharge is then transferred via the vertical and horizontal CCD shift registers to a charge detection amplifier. Subsequently, sites on even numbered rows are read out as a second field in a similar manner by transferring photocharge from even numbered rows of photodiodes to the buried channel region beneath electrodes 50. However, with such a device architecture, it is not possible to read out each row of photodiodes sequentially, i.e., in what would be called a non-interlaced mode, since only one half of a vertical shift register cell is provided for each row. Such a non-interlaced read—out is desirable if the device is to be used in an electronically shuttered mode for still photography. For a non-interlaced read—out to be achieved a complete vertical CCD shift register cell is required for each row of photodiodes since photocharge from all photodiodes must be transferred into the vertical shift register simultaneously and maintained as separate charge packets throughout transfer to the output amplifier. In order to provide for such a non-interlaced read-out sequence each pixel would need to contain at least four separate CCD electrodes if a similar manufacturing process is to be used and the same number of clocking voltages maintained. Alternatively, if three levels of overlapping electrodes are employed with a three—phase clocking sequence, such as disclosed by Tsaur et al in IEEE Electron Device Letters, 10_, 361-363, 1989, a non-interlaced read-out may be achieved but at the expense of additional process and system complexity and a sacrifice of available photosensitive area. In U.S. Patent 4,330,796, Anognostopoulos et al disclose a non-interlaced interline transfer type CCD image sensor which employs three electrodes per pixel and a "meander channel" CCD which occupies a large fraction of the total picture element, or pixel, area. However, as discussed in Losee et al, U.S. Patent 4,613,402, if the barrier region implants in the meander channel CCD are not precisely aligned, parasitic potential wells or barriers will be present in the CCD, thus leading to transfer inefficiency and poor performance. Disclosure of the Invention It is the object of this invention to provide an image sensor with simplified pixel design which may be operated in a non-interlaced mode. It is a further object of this invention to provide such an image sensor with reduced pixel dimensions. It is a further object of this invention to provide a non-interlaced image sensor with a more efficient use of pixel area. The above objects are achieved in an interline transfer type area image sensor having an array of columns and rows of separate pixels and wherein charge collected in the pixels of each column is transferred into a vertical two-phase CCD, such CCD shift register comprising a series of overlapping electrodes, with each electrode being formed from a single level of conductor, separate voltage clocks connected to alternate electrodes, adjacent pairs of said electrodes constituting one complete stage of a CCD shift register, each column pixel being associated with one pair of a vertical CCD's electrodes, an ion implanted barrier region being formed under an edge of each electrode, and means for transferring charge from each pixel into a region under one of the corresponding electrodes . The present invention employs a two-phase CCD shift register which utilizes only one electrode for each clock phase, thus realizing a simplified non-interlaced read—out type device with improved ratio of photosensitive area to total pixel area. This is accomplished by providing a vertical CCD shift register with ion implanted transfer barrier regions such that only one layer of gate electrode is required by each phase of the vertical shift register. The design requires only two electrodes for each row of imaging sites and such a structure is not as subject to yield limitations due to intralevel short circuits, such as those caused by photomasking imperfections. The self-alignment of the transfer barrier region implants assure excellent transfer efficiency in the CCD shift register. Brief Description of the Drawings FIG. 1 is a plan view of a typical prior art interlaced read—out type imaging device; FIG. 2 is a fragmentary, partially schematic vertical section view through a semiconductor device, taken along the lines A-A of FIG. 1, illustrating a prior art construction; FIG. 3a through FIG. 3c are partial plan views of various stages during the making of an interline transfer type area image sensor in accordance with the present invention; FIG. 4a, FIG. 4b and FIG. 4c are fragmentary, partially schematic cross-sectional views taken along the lines A 1 —A 1 , B—B and C—C of FIG. 3c, respectively; and FIG. 5 is a fragmentary, partially schematic cross-section view of an alternative embodiment of the present invention. Mode of Carrying Out the Invention With reference to FIGS. 3a-c and 4a-c, an interline transfer type area image sensor has semiconductor substrate 100 provided with channel stop regions 110 and buried channel regions 120 as shown in plan view in FIG. 3a and in cross-sectional views in FIG. 4. The substrate 100 may be a p—well diffused into an n-type silicon wafer. An insulating oxide 125 is grown over the semiconductor surface and a single level layer of polysilicon conductor 130 is deposited. Barrier regions are provided in regions 140 by methods such as described by Losee et al in u.S. Patent 4,613,402, and illustrated in FIG. 3b. Turning now to FIG. 3c and FIG. 4b, an insulating layer of oxide 135 is grown over the polysilicon conductor 130 and a second barrier region 160 is provided by ion implantation of appropriate dopant atoms. A second single level layer of polysilicon conductor is deposited and patterned to form CCD electrodes 170 (see FIG. 4b). Regions 180, which are not covered with the polysilicon conductors, are then implanted with appropriate impurities to form rows and columns of charge collection sites photoreceptors for collection of photogenerated charge. FIG. 4a shows a cross section of a row of the interline area image sensor having pixels 180. FIG. 4c shows in cross section a column of the interline area image sensor having pixels 180. In this position the layers 170 are directly above layers 130. FIG. 4b is a cross section of one of the two-phase vertical CCD shift registers. Separate voltage clocks Φ, and 2 are respectively connected to alternating electrodes 130 and 170. As shown, the electrodes 170 overlap electrodes 130. To operate this device a positive going voltage pulse is applied to electrodes 130 which permits photogenerated charge from pixels 180 to transfer to the buried channel 120 beneath electrode 130 via the surface channel gap 191 (see FIG. 3a and FIG. 3b). After this transfer of charge into the vertical CCD shift register, clock voltages Φ, and Φ~ are applied to transfer the photocharges to an appropriate charge detection circuit in a well known manner. In this way a non-interlaced read-out of the photogenerated charges is accomplished and each row of pixels 180 is associated with one pair of electrodes 170 and 130. In order to operate such a device in an electronically shuttered mode a voltage pulse is applied to simultaneously deplete all of the photoreceptor sites of any accumulated signal charge. For example, if substrate 100 is a p-well diffused into an n—type wafer, a voltage pulse applied beweeen the p—well and the n—type wafer may be used to deplete the photoreceptor sites. After application of such a depleting pulse, photocharges are generated by absorption of incident light. Thereafter a suitable period of such light exposure, all accumulated photoreceptor photocharges are transferred simultaneously into the vertical CCD shift register and read out as described above. An alternative embodiment of this invention is shown schematically in FIG. 5. In this alternative embodiment the charge collection regions of the device, 180 are connected to capacitor plates 200 through a conducting pillar 210. Such a conducting pillar may be fabricated as described by -1- Raley et al, J. Electrochemical Soc. 135. 2640 (1988). The capacitor plates are covered with a photoconducting layer 220 and top electrode layer 230. Photogenerated charge is transferred across the photoconductive layer and transferred to the charge collecting regions 180. This photocharge is then further transferred from regions 180 to the vertical shift register and read out as described in the preceeding paragraph. A third embodiment of the present invention is one where the conductive electrodes 130 and 170 of the figures are composed of composite layers of polysilicon and one or more material selected from the group consisting of WSi , MoSi , TaSi , TiSi , W, Mo, or Ta. Example: The following description gives an example of a device constructed according to this invention. An n—type semiconductor doped to approximately 30 ohm-cm resistivity was provided with a p-type region by implantation of boron atoms with a dose of 1.0E+12 cm*''-2 and diffused to a depth of thickness of approximately 3.5 μm. Channel stop barrier regions are formed by implantation of boron with a dose of 1.0E+13 cm**-2, and subsequently growing an oxide of thickness approximately 4000 A. An additional oxidation and subsequent etch—back reduces this oxide to a thickness of approximately 2500 A. A buried channel region is formed by ion implantation of arsenic atoms, with a total dose 6.0E+12 cm**-2, and transfer gate oxide approximately 500 A thick, is grown in the charge transfer region and over the photodiode regions. Polysilicon electrodes and edge aligned boron implanted barrier regions were then formed according to procedures described by Losee et al, U.S. Patent 4,613,402, and phosphorus was implanted into the photodiode region with a dose of 4.0E+12 cm**—2. A thin oxide layer was grown at a temperature of 950 β C, in a wet ambient, for approximately 8 minutes. An insulating layer was deposited by chemical vapor deposition, consisting of approximately 1000 A undoped oxide covered by 5000 A of oxide doped with approximately 4 wt% boron and 4 wt% phosphorus. The device was subsequently annealed in an inert ambient for 30 minutes at a temperature of 900°C, contact openings were etched and an aluminum interconnect pattern was fabricated. The pixel dimensions of this device were 9.0 μm, horizontally, by 9.0 μm vertically. Industrial Appplicability For applications in electronic photography, image sensors of the interline transfer type with non-interlaced read-out sequence may be required. In interline transfer type image sensing devices, photogenerated charge is transferred from a pixel into a vertical CCD shift register. In the so-called interlaced read—out sequence alternate rows of pixels comprising one field are read out, one row at a time. Then, the second field, consisting of the remaining alternate rows of pixels, is read out. The vertical shift CCD register structure in such a device is composed of two or more overlapping levels of polysilicon electrodes associated with each row of pixels. For electronic photography, however, this interlaced read-out is frequently not desirable and a non-interlaced read-out, wherein photogenerated charge from each row is transferred in sequence, is preferred. In this disclosure, a non-interlaced interline transfer imaging device with simplified structure, and, hence improved manufacturability is described. The device utilizes two— hase vertical CCD shift registers with ion implanted barrier regions, which may be self—aligned, such as described by Losee et al U.S. Patent 4,613,402, to produce a device with the minimum number of two polysilicon electrodes associated with each pixel. In addition to structural simplifications, the device also provides improved topography for application of integral color filter arrays and maximizes the photosensitive area. The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.

Claims: CLAIMS : 1. An interline transfer type area image sensor having an array of columns and rows of separate pixels characterized in that charge collected in the pixels of each column is transferred into a vertical two—phase CCD shift register, such CCD shift register comprising a series of overlapping electrodes, with each electrode being formed from a single level of conductor, separate voltage clocks connected to alternate electrodes, adjacent pairs of said electrodes constituting one complete stage of a vertical CCD shift register, each column pixel being associated with one pair of a vertical CCD's electrodes, an ion implanted barrier region being formed under an edge of each electrode, and means for transferring charge from each photoreceptor into a region under one of its corresponding electrodes. 2. An image sensor device as in claim 1 wherein photogenerated charge in each photoreceptor is substantially simultaneously transferred to the CCD shift register and read out in a non-interlaced fashion. 3. An image sensor device as in claim 1 wherein a voltage is applied to the sensor to deplete charge collected in all the photoreceptors which then collect charge as a function of incident light, and means for transferring simultaneously the charge from each photoreceptor into a region under one of its corresponding electrodes. 4. An image sensor device as in claim 1 wherein said electrodes are comprised of doped polysilicon. 5. An image sensor device as in claim 1 wherein one or both of said electrodes of a pair are comprised of composite layers of polysilicon and one or more of a material selected from the group consisting of WSi , MoSi , TaSi v , TiSi , W, Mo, or Ta. 6. An image sensor device as in claim 1 wherein each photoreceptor includes a photodiode. 7. An image sensor device as in claim 1 wherein each photoreceptor comprises a photoconducting layer, a capacitor plate connected to such photoconducting layer, a charge collecting region, and a conducting pillar coupling the capacitor to the charge collecting region such that photogenerated charge produced in the photoconducting layer is transferred to the charge collecting region, whereby such charge is subsequently transferred to the vertical CCD shift register.

Inventors: LOSEE DAVID L, NELSON EDWARD T, STEVENS ERIC G, TREDWELL TIMOTHY JOHN, LOSEE, DAVID, L., NELSON, EDWARD, T., STEVENS, ERIC, G., TREDWELL, TIMOTHY, JOHN
Applicants: EASTMAN KODAK CO, EASTMAN KODAK COMPANY
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, H04N5