Adaptive array processor

Abstract: An off-line processor arrangement for a broadband accelerated convergence adaptive antenna array wherein signals from a plurality of antenna elements are applied to respective identical tapped delay lines (T) the outputs of which are fed through individual signal weighting means to a beamforming network (BFN), the arrangement including one or more lattice filter means (LF) to which the auxiliary antenna element signals are applied together with the output response of the beamforming network to compute sets of weight correction vectors (* W) with which to update weight coefficients and means for storing said updated coefficients, said stored coefficients being applied to the individual signal weighting means to weight the outputs of the tapped delay lines.

Description: This invention relates to an off-line processor for a broadband accelerated convergence adaptive antenna array. The objective of an adaptive antenna is to combine the signals received by the elements in an array to produce a far-field pattern that, in some sense, optimises the reception of a desired signal in the presence of jamming and noise. The substantial improvements in anti-jam performance offered by this form of array signal processing have meant that it is now becoming an essential requirement for many military radar, communication and navigation systems. A known type of combining circuit for a broadband adaptive array is shown in Fig. 1. Signals from the antenna array elements are received on individual channels which are identified as 'PRIMARY CHANNEL' and 'AUX CHANNELS'. The primary channel is applied via a time delay T D to a beamforming network BFN. The auxiliary channels 1 to N-1 are applied to respective tapped delay lines T, the outputs of which are fed through respective weighting networks to the beamforming network. Time delay T D in the PRIMARY channel compensates for the associated signal delay through the tapped delay line auxiliary weighting. Weights W 1,1 W 1,2 W 1,3 ...W n-1,1 W n-1,2 ....W n-1,m-1 W n-1,m are applied to the weighting networks. The weighted outputs of the tapped delay lines are combined in the beamforming network BFN together with the primary channel signal to form the output response of the array. Normally, to reduce or eliminate the effect of a jamming signal the weights are calculated (by a signal processor not shown in Fig. 1) to form a beam pattern with broadband spatial nulls in the directions of the jammer sources. To avoid the array nulling towards the desired signal source it can be arranged for the array to adapt to null the jamming signal(s) during intervals when the desired signal is absent. The weights are then frozen while the desired signal is present and then recalculated during any pauses in the desired signal. Other schemes can be devised which prevent cancellation of the wanted signal. Known forms of signal processing to calculate the required weights include the Widrow Least Mean Squares (LMS) algorithm or the least squares algorithm to minimise the output power of the beamformer. See for example, B Widrow et al, "Comparison of Adaptive Algorithms Based on the Methods of Steepest Descent and Random Search", IEEE Trans., 1976, AP-24, pp 615-637, and the time shared arrangement described in British patent GB 2 188 782 B. Dixieme Colloque sur le Traitement du Signal et ses Applications, Nice20-24.05.1985, FR; pages 391-396; G. Favier et al.: "Etude Comparative de Filtres Adaptifs en Treillis (Application au Traitement d'Antenne)" descibes a cascaded lattice filter arrangement essentially used as a method of providing an improved convergence rate performance compared with standard least mean squares (LMS) arrangements. "A Novel Algorithm and Architecture for Adaptive Digital Beamforming", C.R. Ward et al, IEEE Transactions on Antennas and Propagation, vol. AP-34, no. 3, March 1986, pages 338-346, New York, U.S.A., discloses an arrangement having specific application to high performance adaptive digital beamforming. It is shown how a simple, linearly constrained adaptive combiner forms the basis for a wide range of adaptive antenna subsystems. The function of such an adaptive combiner is formulated as a recursive least squares minimization operation and the corresponding weight vector is obtained by means of the Q-R weight decomposition algorithm using Givens rotations. An efficient pipelined architecture to implement this algorithm is also described. It takes the form of a triangular systolic/wavefront array suitable for very large scale integration (VSLI) system design. This arrangement, however, is concerned with a specific narrowband adaptive antenna processing problem not relevant to the present invention. According to the present invention there is provided an off-line processor arrangement for a broadband accelerated convergence adaptive antenna array wherein signals from a plurality of auxiliary antenna elements are applied to respective identical tapped delay lines (T) the outputs of which are fed through respective individual signal weighting means (W 1,1 - W n-1,m ) to a beamforming network (BFN) and then combined with the signal from a primary antenna element which is delayed via a delay line (TD) whereby the auxiliary signals from the tapped delay lines are applied together with the output response of the beamforming network to compute sets of weight correction vectors, characterised in that the arrangement includes one or more least squares lattice filter means (LF) together with an associated weight impulse response calculation means (PC) with which to update the weight coefficients and means for storing (WS) said updated coefficients, said stored coefficients being applied to the individual signal weighting means to weight the outputs of the tapped delay lines. In one embodiment of the invention separate identical lattice filter means are provided for each of the antenna element signal to compute weight vectors for updating the weight coefficients for the outputs of the respective tapped delay line. In an alternative embodiment of the invention there is provided a single lattice filter means and means for time multiplexing the antenna element signals to the filter means whereby the filter means is operated in a time shared mode. Embodiments of the invention will now be described with reference to the accompanying drawings, in which:- Fig. 1 illustrates a prior art beamforming arrangement for a broadband adaptive array (already referred to), Fig. 2 illustrates a partitioned off-line processor for a broad band accelerated convergence adaptive array, Fig. 3 illustrates a time-multiplexed off-line processor for a broadband accelerated convergence adaptive array, and Figs. 4 & 5 illustrate implementation and operation of a simple two-channel system using a lattice filter. In the arrangement shown in Fig. 2 the weights to be applied to the outputs of the tapped delay lines are updated by weight correction vectors derived from m-stage lattice filters LF₁...LF n-1 . Each lattice filter is constructed of a number of identical stages or sections LS (Fig.4) in cascade. The signal from the appropriate antenna element, i.e. auxiliary channel, is fed to the two inputs X, Y of the basic lattice structure. A typical lattice section LS is shown in Fig. 5. Input X is applied via a time delay T and then the X and Y signals are applied to the appropriate cross multiplier structure. After processing each section provides two outputs, X¹ and Y¹. For the adaptive antenna application the X¹ outputs of each lattice section are subjected to a scaling factor and then combined with the output response from the beamformer BFN. The operation of the lattice filters and lattice sections presented here is well known. Appropriate algorithms for least squares lattices are readily discussed in "Adaptive Filters" by C.F.N. Conan and P.M Grant (Prentice Hall Signal Processing Series, 1985) and "Adaptive Filter Theory" by S. Haykim (Prentice Hall Information and System Sciences Series, 1986). Returning now to Fig. 2, the operation of the m-stage lattice filters is controlled by a process controller PC which produces, for example, weight flush control signals to cause the weight correction vectors to be flushed out of the filters at the correct time intervals. The weight flush control calculates impulse response of the lattice filter. The flushed out impulse coefficients from the filters (represented in vector notation by * W i (P) for the i th lattice filter at the p th recursion) are applied to update the weights in respective stores WS₁...WS n-1 where the weights to be applied to the tapped delay line outputs are held. In the arrangement shown in Fig. 3 instead of using a number of lattice filters, one for each tapped delay line, a single lattice filter LF is used in a time-shared mode. The auxiliary channel signals from the antenna elements are applied to a time division multiplexer MUX from which the multiplexed signals are fed to the filter LF. The weight correction vectors * W i are supplied to the weight update-and-store circuit WS for all the tapped delay lines. The use of off-line lattice filters to produce weight correction vectors offers various levels of reduced circuit complexity while retaining a significant improvement in convergence compared with more conventional adaptive weight control techniques e.g. the Widrow LMS technique.

Claims: An off-line processor arrangement for a broadband accelerated convergence adaptive antenna array wherein signals from a plurality of auxiliary antenna elements are applied to respective identical tapped delay lines (T) the outputs of which are fed through respective individual signal weighting means (W 1,1 - W n- 1,m ) to a beamforming network (BFN) and then combined with the signal from a primary antenna element which is delayed via a delay line (TD) whereby the auxiliary signals from the tapped delay lines are applied together with the output response of the beamforming network to compute sets of weight correction vectors, characterised in that the arrangement includes one or more least squares lattice filter means (LF) together with an associated weight impulse response calculation means (PC) with which to update the weight coefficients and means for storing (WS) said updated coefficients, said stored coefficients being applied to the individual signal weighting means to weight the outputs of the tapped delay lines. An arrangement according to claim 1 wherein separate identical lattice filter means (LF₁ - LF n-1 ) are provided for each of the auxiliary antenna element signals to compute weight vectors for updating the weight coefficients for the outputs of the respective tapped delay line. An arrangement according to claim 1 wherein there is provided a single lattice filter means (LF) and means for time multiplexing (MUX) the antenna element signals to the filter means whereby the filter means is operated in a time shared mode.

Inventors: WARD CHRISTOPHER ROBERT, WARD, CHRISTOPHER ROBERT
Applicants: NORTHERN TELECOM LTD, NORTHERN TELECOM LIMITED
Application year: 1990
Main classification: H01Q3
IPC codes: H01Q3