Method of forming compound semiconductor layer

Abstract: A method of forming a compound semiconductor (GaAs) layer hetero-epitaxially grown on a silicon single crystal substrate(1) comprises the consecutive steps of: growing a first (e.g., III-V group) compound semiconductor (GaAs) layer(3) on the silicon substrate(1); heat treating the substrate and the layer to reduce a dislocation density thereof; doping the first compound semiconductor (GaAs) layer(3) with p-type impurities by feeding the impurities together with a volatile group element (V group) source gas (AsH₃ gas) into a reactor during the heat treating step; and growing a second compound semiconductor (GaAs) layer(4) on the first compound semiconductor (GaAs) layer(3). It is possible to adopt an ion-implantation method instead of the thermal diffusion method. A GaAs/Si substrate in which an increase of electron carriers is prevented by a compensation with the doped p-type impurities is obtained and is used for a production of a GaAs device (FET).

Description: The present invention relates to a hetero-epitaxial growth of a compound semiconductor layer on a silicon (Si) single crystalline substrate, and more particularly, to a method of forming a gallium arsenide (GaAs) thin layer on the Si substrate. The present invention is applied to a compound semiconductor/Si (e.g., GaAs/Si) substrate for compound semiconductor (GaAs) devices. A compound semiconductor substrate, for example, a GaAs substrate is produced by growing a single crystal (GaAs) lump (ingot) by a pulling method (Czochralski method) or the like, and then cutting (slicing) the lump into substrates (wafers). Such a GaAs substrate is expensive, easily broken, and has a relatively small size. Recently, the degree of integration of a GaAs IC (integrated circuit) and a chip size (area) thereof have been increased, leading to a demand for a larger size and a strong, not easily broken GaAs substrate. As such a large wafer size GaAs substrate, a GaAs/Si substrate produced by a hetero-epitaxial growth of a GaAs thin layer on a Si substrate has been proposed, and during this growth, GaAs layer GaAs devices such as high-speed transistors and photo-emitting elements (e.g., lasers, LED's) are formed (see, for example, Kaminishi and Akiyama: "GaAs layer is directly grown on a Si wafer and devices are formed on the layer", Nikkei-Microdevices, No. 7, January, 1986, pp. 113-127). A metalorganic chemical vapor deposition (MOCVD) method and a molecular beam epitaxy (MBE) method have been used for growing a hetero-epitaxil GaAs layer on a Si substrate. Further, for the growth (formation) of the GaAs layer, a two step growth method consisting of a first step of growing a noncrystalline (amorphous or partially crystallized) GaAs thin layer on a Si substrate at a relatively low temperature, and a second step of epitaxially growing GaAs thereon at a high temperature to obtain a predetermined layer thickness, has been proposed. Such a formed GaAs layer has crystal defects such as dislocation, and therefore, the substrate with the GaAs layer must be subjected to a heat treatment (annealing), to reduce the dislocations, under an atmosphere comprising hydrogen (H₂) gas and arsenic (As) gas (or arsine (AsH₃) gas). Such a process is described in the description with respect to Figure 1 below. Conventionally when the heat treatment for reducing the dislocation density is performed, however, the (exposed) surface layer portion of the grown GaAs layer becomes n-type, due to an unintentional n-type impurity (e.g., Si) doping to that portion, and accordingly, a leakage current is liable to flow through the n-type portion of the GaAs layer (GaAs/Si substrate) to the silicon substrate and the doping control can not be satisfactorily performed. To prevent or reduce the leakage current, there is an attempt to additionally form a high (electric) resistance layer within the epitaxial GaAs layer. In this case, the high resistance layer is formed by epitaxially growing GaAs with doping an impurity (Cr, Fe or V). However, such impurities contaminate a reactor (growing furnace) and remain therein to have an undesirable influence on the GaAs layer portion grown at a later stage. According to the present invention there is provided a method of forming a compound semiconductor layer hetero-epitaxially grown on a silicon single crystal substrate comprising the steps of: growing a first compound semiconductor layer on said silicon substrate; heat treating said substrate; and growing a second compound semiconductor layer on said first compound semiconductor layer characterised by doping the interface between the first compound semiconductor layer and the second compound semiconductor layer with a p-type impurity prior to or during the step of growing the second compound layer. The present invention provides a method of preventing an increase of the electron carrier concentration of the portion of the grown GaAs layer, caused by the heat treatment for reducing the dislocation density, to thereby reduce the leakage current and enable a desired doping control during the fabrication of the device. The method is suitable for producing a compound semiconductor device or element by using the compound semiconductor layer formed on a Si substrate without generating the increased electron carrier concentration portion. Preferably the p-type impurities (Zn, Be, C, or Mg) are doped (thermally diffused) into the first (III-V group compound semiconductor layer during the heat treatment for reducing the dislocation density, to compensate for the increase of the electron carriers. Namely, the doping amount is corresponded to the amount of electron carriers, to make the carrier concentration at an interface between the first and second compound semiconductor layers 10⁻⁶ cm⁻³ or less. The impurity-doping by can be carried out by an ion-implantation method instead of the thermal diffusion method, before or after the heat treatment for reducing the dislocation density. In this case, an annealing treatment must be carried out, to recover the ion-implanted portion and activated the p-type impurities, at a suitable stage. Preferably the III-V group compound semiconductor layer is GaAs, AlAs, GaP, InAs, and a mixture thereof (in particular, GaAs). It is possible to use II-VI group compound (ZnSe, ZnS, and HgCdTe), and IV-VI group compound (SnTe, PbS, and PbSe), as the compound semiconductor layer other than the III-V group compound. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more apparent from the description of the preferred embodiments set forth below, with reference to the accompanying drawings, in which: Figs. 1A to 1D are graphs of temperature profiles during the formation of the GaAs layer on a Si substrate; Fig. 2 is a schematic sectional view of a GaAs/Si substrate; Fig. 3 is a graph, similar to Fig. 1A, of a temperature profile for the growth of the GaAs layer of a GaAs/Si substrate according to the present invention; Fig. 4 is a graph showing a carrier concentration distribution in a GaAs/Si substrate having the GaAs layer in accordance with the temperature profile of Fig. 2, in a thickness direction; and Figs 5a to 5d are schematic sectional views of a GaAs device in various stages of the production thereof, using the GaAs/Si substrate. Conventionally heat treatment is performed in accordance with one of the temperature profiles shown in Fig. 1A to 1D. As shown in these drawings, first a Si substrate is preheated at step A, is heated at a high temperature for surface-cleaning at step B, is covered with a noncrystalline (amorphous) GaAs thin layer grown thereon at a relatively low temperature (e.g., 450°C) at step C, and is further covered with an epitaxial GaAs layer grown on the amorphous layer at a high temperature (e.g., 700°C). in Figs. 1A and 1B, the growth of the epitaxial GaAs layer is performed twice at steps G₁ and G₂ , and between the steps G₁ and G₂ the heat treatment for reducing the dislocation density is carried out by a thermal cycle treatment (at step D in Fig. 1A, at least one cycle of heating the substrate to a temperature higher than a growth temperature of the GaAs layer and cooling the substrate to a temperature lower than the growth temperature is carried out) or by a high temperature annealing treatment (at step E in Fig. 1B, wherein the substrate is held at a temperature higher than the growth temperature). In Figs. 1C and 1D, after the growth of the GaAs layer (at step G) the heat treatment for reducing the dislocation density is carried out by the thermal cycle treatment (at step D in Fig. 1C) or by the high temperature annealing treatment(at step E in Fig. 1D). Referring to Figs. 2 and 3, compound semiconductor (for example, GaAs) layer is formed (hetero-epitaxially grown) on a Si substrate, i.e., a GaAs/Si substrate is produced in accordance with a first embodiment of the present invention. First, a Si substrate (single crystal wafer) 1 is set in a conventional growing reactor or furnace (not shown). The furnace is evacuated, to obtain a high vacuum pressure, and the Si substrate is preheated at 450°C (step A). Then an H₂ gas (12 SLM) and an AsH₃ gas (100 sccm) are fed into the furnace to bring the inside pressure to 76 Torr (10kPa), and the substrate temperature is raised to 1000°C and held thereat for 10 minutes, to clean the surface of the Si substrate (step B). Next, the substrate temperature is lowered to 450°C, and a Ga(CH₃)₃ gas (24 sccm) is additionally fed into the furnace, and the H₂ gas (at 12 SLM) and AsH₃ gas (increased to 200 sccm) are continuously fed into the furnace, thereby grow (deposit) a noncrystalline (amorphous) GaAs thin layer 2 having a thickness of about 10 nm on the Si substrate 1 (step C), as shown in Fig. 2. Thereafter, the substrate temperature is raised to 700°C, and the H₂ gas (constant at 12 SLM), the AsH₃ gas (increased to 200 sccm), and the Ga(CH₃)₃ gas (increased to 29 sccm) are continuously fed into the furnace, to epitaxially grow a first GaAs layer 3 having a thickness of from 1 to 3 µm (e.g., about 1.3 µm) on the amorphous GaAs layer 2 (step G₁). The GaAs growth is interrupted by a heat treatment for reducing the dislocation density. This thermal cycle treatment and consists of one to 20 cycles (in this case, 5 cycles) of cooling to 200°C and heating to 800°C (step D), as shown in Fig. 3. During the heat treatment in a conventional case, the atmosphere is composed of the H₂ gas (constant at 12 SLM) and the AsH₃ gas (reduced to 120 sccm), by stopping the feed of the Ga(CH₃)₃ gas. According to the present invention, a p-type impurity containing gas, e.g., Zn(C₂H₅)₂ gas (0.5 to 30 sccm) is additionally fed, together with the H₂ gas and the AsH₃ gas, into the reactor to form an atmosphere, and accordingly, when the Si substrate 1 with the GaAs layer 3 is heated at 800°C, Zn (p-type impurity) is thermally diffused into the GaAs layer 3, i.e., the GaAs layer 3 is doped with the Zn. The AsH₃ gas, as a V group source gas, is continuously fed for a period other than the GaAs growth time, whereby a vaporization of As, which has a high vapor pressure and is easily vaporized, is prevented. It is possible to adopt an As(CH₃)₃ gas for carbon (C) impurities or an Mg(C₅H₅)₂ or for Mg(C₅H₃C₅H₄)₂ gas for Mg impurities, instead of the Zn(C₂H₅)₂ gas. After the heat treatment, the substrate temperature is raised to 700°C and the epitaxial growth of GaAs is repeated by feeding the H₂ gas (12 SLM), the AsH₃ gas (200 sccm), and Ga(CH₃)₃ gas (29 sccm, in the same way as in step G₁ , into the growing reactor to form a second GaAs layer 4 having a thickness of from 1 to 10 µm (e.g., about 1.9 µm) on the first GaAs layer 3 (step G₂). Accordingly, a GaAs/Si substrate is produced, and the obtained GaAs epitaxial layer of the substrate consists essentially of the first and second GaAs layers 3 and 4 having an interface 5 therebetween, and has thickness of, e.g., about 3.2 µm. The (electron) carrier concentration of the obtained GsAs/Si substrate, from the top surface thereof in a layer thickness direction, is determined and the result shown in Fig. 4 obtained. As shown in Fig. 4, where a conventional heat treatment for reducing the dislocation density is performed in a thermal cycle treatment mode, the electron carrier concentration is increased at the interface 5 between the first and second epitaxial layer 3 and 4 (indicated with a broken line) at which the heat treatment is carried out, to form an n-type portion. On the other hand, in accordance with the present invention, the p-type impurity (such as Zn) doping is carried out during the heat treatment, and thus the carrier concentration becomes lower than the measuring range of the measuring equipment employed, as indicated by a solid line. Namely, the electron carriers in the portions of the first and second GaAs layers 3 and 4 near the interface 5 are compensated by the p-type dopants (impurities), and thus the carrier concentration at and near the interface 5 is lowered to 4.5 x 10¹⁵ cm⁻³ or less (lower than the carrier concentration in the second epitaxial GaAs layer 4). The desired doping control can be carried out when the carrier concentration becomes 1 x 10¹⁶ cm⁻³. Therefore, according to the present invention, it is possible to prevent the increase of the electron carrier concentration caused by a conventional heat treatment for reducing the dislocation density, at and near the interface in the GaAs layer formed on the Si substrate, to thereby obtain a GaAs/Si substrate having a leakage current lower than that of conventional GaAs/Si substrates. The heat treatment for reducing the dislocation density can be performed by holding the Si substrate with the first epitaxial GaAs layer 3 at a constant high temperature, e.g., 800°C, instead of the thermal cycle treatment, and in this case, the temperature profile is similar to that of Fig. 1B. The atmosphere of the heat treatment is composed of the H₂ gas, the AsH₃ gas, and the Zn(C₂H₅)₂ gas (the p-type impurity containing gas) added in accordance with the present invention, and during the heat treatment the Zn (p-type impurity) is thermally diffused into the first epitaxial GaAs layer 3, to prevent the formation of the n-type portion as explained above. It is possible to adopt other III-V group compound semiconductor materials, such as AlAs, GaP and InAs, for the first epitaxial GaAs layer 3, instead of the above-mentioned GaAs. It is also possible to adopt other III-V group compound semiconductor materials (such as AlAs, GaP and InAs), II-VI group compound materials (such as ZnSe, ZnS and HgCdTe), or IV-VI group compound materials (SnTe, Pbs, and PbSe) for the second epitaxial GaAs layer 4 instead of the above-mentioned GaAs. An ion-implantation method can be used for doping the first epitaxial GaAs layer 3 with the p-type impurities, instead of the above-mentioned thermal diffusion method, but in this case, after the ion-implantation treatment, the ion-implanted GaAs layer 3 (i.e., the Si substrate) must be subjected to an annealing process (additional heat treatment), to recover the ion-implanted portion and activate the implanted p-type impurities. The following ion-implantation conditions are preferable: The ion-implantation can be performed before or after the heat treatment for reducing the dislocation density. In the former case, after the epitaxial growth of the first GaAs layer 3, the p-type impurities are ion-implanted into the whole layer 3 under the above-mentioned conditions, and then the above-mentioned thermal cycle treatment is performed. Since the thermal cycle treatment includes the high temperature heating of 800°C, this treatment serves as the heat treatment for reducing the dislocation density and as the annealing process for recovering the ion-implanted portion and activating the implanted p-type impurities. In the latter case (after the heat treatment for reducing the dislocation density and the ion-implantation treatment), the annealing is performed in the following three ways. First, a SiO₂ cap layer is formed on the whole surface of the first GaAs layer 3, to prevent an evaporation of the V group element (As), the Si substrate temperature is raised to 800°C for, e.g., 90 minutes, under a H₂ atmosphere in the growing reactor, to carry out the annealing, and then the SiO₂ cap layer is removed by a suitable etching method. Thereafter, the second epitaxial GaAs layer 4 is grown on the first GaAs layer 3 in the above-mentioned manner. Next, the Si substrate with the ion-implanted GaAs layer 3 is reset in the reactor and is heated at 800°C in an AsH₃ gas atmosphere for, e.g., 90 minutes, to carry out the annealing process, and thereafter, the second epitaxial GaAs layer 4 is the first GaAs layer 3 in the above-mentioned manner. Finally, the Si substrate with the ion-implanted GaAs layer 3 is reset in the growing furnace and the second epitaxial GaAs layer 4 is grown on the first GaAs layer 3 in the above-mentioned manner, except that the growing temperature is 800°C or more, to carry out the annealing process. Using the obtained gaAs/Si substrate, a GaAs FET (field effect transistor) is produced in the following manner, as shown in Figs. 5a to 5d. First, as shown in Fig. 5a, the second epitaxial GaAs layer 4 is covered with a pattern masking layer 8 and is ion-implanted with n-type impurities (e.g., Si) with an energy of 50 keV at a dose of 2 x 10¹² cm⁻², to form an n⁻ -type region 9. Then, as shown in Fig. 5b, the same portion of the second epitaxial GaAs layer 4 is also ion-implanted with p-type impurities (e.g., Mg) with an energy of 80 keV at a dose of 10¹³ cm⁻², to form a p⁺-type region 10 under the region 9, and after the masking layer 8 is removed, a gate electrode 11 made of WSi is formed on the region 9 of the layer 4. Next, as shown in Fig. 5c, the second epitaxial GaAs layer 4 is covered with another pattern masking layer 12 and is further ion-implanted with n-type impurities (e.g., Si), with an energy of 150 keV at a dose of 2 x 10¹³ cm⁻², to form n⁺-type source and drain regions 14 and 15, and after the masking layer 12 is removed, the GaAs/Si substrate is annealed at a temperature of 800°C or more to recover the ion-implanted portion of the layer 4 and to activated the implanted impurities. Finally, as shown in Fig. 5d, a source electrode 16 and a drain electrode 17, made of AuGe/Au, are formed on the regions 14 and 15, respectively, to obtain the GaAs FET. Instead of the GaAs FET, a GaAs laser can be produced by using the GaAs/Si substrate according to the present invention.

Claims: A method of forming a compound semiconductor layer hetero-epitaxially grown on a silicon single crystal substrate comprising the steps of: growing a first compound semiconductor layer (3) on said silicon substrate (1); heat treating said substrate (1); and growing a second compound semiconductor layer (4) on said first compound semiconductor layer characterised by doping the interface between the first compound semiconductor layer (3) and second compound semiconductor layer (4) with a p-type impurity prior to or during the step of growing the second compound layer (4). A method according to claim 1, further comprising a step of growing an amorphous compound semiconductor layer (2) prior to said step of growing the first compound semiconductor layer (3). A method according to claim 2, wherein said heat treatment step is performed by at least one cycle of heating said substrate (1) to a temperature higher than a temperature used in said step for growing the first compound semiconductor layer (3) and cooling said substrate to a temperature lower than said temperature used in said growing step. A method according to claim 1, wherein said heat treatment step is performed by heating said substrate (1) at a constant temperature higher than temperature used in said step for growing the first compound semiconductor layer (3). A method according to any one of the preceding claims, wherein said compound semiconductor layer (3,4) is a compound selected from the group consisting of a III-V group compound, a II-VI group compound, and a IV-VI group compound. A method according to claim 5, wherein said III-V group compound semiconductor layer is a compound selected from the group consisting of GaAs, AlAs, GaP, and InAs. A method according to claim 6, wherein said III-V group compound semiconductor layer is GaAs. A method according to any one of the preceding claims, wherein said p-type impurities are an element selected from the group consisting of Zn, Be, C, and Mg. A method according to any one of the preceding claims, wherein in said second compound semiconductor layer (4) an electronic device is formed. A method according to any one of the preceding claims, wherein said p-type impurities are doped, to thereby compensate for electron carriers by carrying out the step of heat treating in an atmosphere including a volatile group element of said compound semiconductor and a p-type impurity. A method according to any one of claims 1 to 9, in which the p-type impurities are doped by ion-implanting p-type impurities into said first compound semiconductor layer (3). A method according to claim 11, wherein said ion-implanting step is performed, and then said heat treating step is performed for reducing a dislocation density. A method according to claim 11, wherein said heat treating step is performed for reducing a dislocation density, and then said ion-implanting step is performed. A method according to claim 13, wherein said annealing step is performed by forming a SiO₂ cap layer on said first compound semiconductor layer, holding said substrate at a temperature higher than a temperature used in said step for growing the first compound semiconductor layer, and removing said cap layer. A method according to claim 13, wherein said annealing step is performed by holding said substrate at a temperature of 800°C or more under an atmosphere containing a volatile group element of said compound semiconductor. A method according to claim 13, wherein said annealing step is performed during said step for growing the second compound semiconductor layer, at a temperature of 800°C or more. A method of producing a semiconductor device in a compound semiconductor layer hetero-epitaxially grown on a silicon single crystal substrate, comprising the steps of: growing a first compound semiconductor layer(3) on said silicon substrate (1); heat treating said substrate and said layer(3) to reduce a dislocation density thereof; growing a second compound semiconductor layer (4) on said first compound semiconductor layer(3); doping the interface between said first compound semiconductor layer (3) and said second compound semiconductor layer with p-type impurities prior to or during the step of growing the second compound layer (4) to thereby compensate for electron carriers; doping said second compound semiconductor layer (4) with impurities to form at least one impurity-introduced region (9, 10, 14, 15); forming an electrode (11, 16, 17) on said impurity-introduced region of said second compound semiconductor layer (4).

Inventors: ESHITA TAKASHI, INOUE TOSHIKAZU, ESHITA, TAKASHI, INOUE, TOSHIKAZU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01L21
IPC codes: H01L21