BCH code decoder and method for decoding a BCH code

Abstract: There is disclosed a BCH code decoder for correcting a natural number N of error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, and a method therefor. In the BCH code decoder and the BCH decoding method, first to N-th syndromes are generated from an inputted code sequence encoded by the BCH encoding method, respectively, and first to N-th check codes are generated by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first to N-th syndromes, respectively. Thereafter, error correction information is generated when a number of error bits represented by said first to N-th syndromes is equal to the sum of one and a number of error bits represented by said first to N-th check codes, and one or more error bits of said inputted code sequence are corrected according to said error correction information, thereby outputting the decoded code sequence.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a Bose-Chaudhuri-Hocquenghem code (referred to as a BCH code hereinafter) decoder and a method for decoding a BCH code, and more particularly, to a BCH code decoder for correcting a natural number N or less of error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, and a method for decoding a BCH code so as to correct a natural number N or less of error bits occurring in a code sequence composed of bits encoded by a BCH encoding method. DESCRIPTION OF THE RELATED ART Conventionally, in order to correct one or more bit errors occurring in digital data upon transmitting the digital data, there has been used such a method that digital data composed of information sequence to which check sequence is added on a transmission side are transmitted, and bit errors occurring in digital data upon transmitting them are corrected by a error correction unit on a reception side. As one of error correction codes for obtaining the above-mentioned check sequence, the BCH code has been used. Fig. 1 shows a conventional BCH code decoder which is well known to those in the art (For example, see Toshihide HABUTSU, "Error correction by the BCH code", Hohsoh gijutsu, November 1983, pp 1111). The composition of the conventional BCH decoder will be described below with reference to Fig. 1. Referring to Fig. 1, a code sequence composed of an information sequence and a check sequence which is coded by the BCH code is inputted in a serial form through an input terminal 111 to a syndrome generator 101 and a delay circuit 108. The syndrome generator 101 generates a syndrome based on a check matrix of the BCH code from the code sequence inputted through the input terminal 111, and outputs the generated syndrome to a syndrome memory 102. The syndrome memory 102 temporarily stores the generated syndrome at a timing when the generation of the syndrome performed by the syndrome generator 101 has been completed, and outputs the stored syndrome to a code converter 103. The code converter 103 of a read only memory (referred to as a ROM hereinafter) converts the syndrome inputted from the syndrome memory 102 into signals for representing different error bit positions of one or two bit errors to coincidence judgment circuits 105 and 106, respectively. Data of bit error positions corresponding to all the syndromes previously obtained in respective error patterns with respect to all the bit errors of two bits or less are stored at the addresses which are respectively the same as the above syndromes in the ROM of the code converter 103. When the syndrome temporarily stored in the syndrome memory 102 is inputted to an address terminal of the ROM of the code converter 103, data of the bit error positions corresponding to the inputted syndrome are outputted from a data terminal thereof. The delay circuit 108 delays the code sequence inputted through the input terminal 111 by a predetermined delay time, and sequentially outputs them to a first input terminal of an exclusive OR gate 109, which is provided for inverting a bit inputted from the delay circuit 108 only when the inputted bit is an error bit. A counter 107 generates a signal for representing a bit position of the delayed code sequence which is outputted from the delay circuit 108 in synchronization with the delayed code sequence by counting a clock of the code sequence, and outputs the generated signal to both the coincidence judgment circuits 105 and 106. The coincidence judgment circuit 105 compares the error bit position outputted from the code converter 103 with the signal for representing the bit position of the code sequence which is outputted from the counter 107. Then, when the error bit position coincides with the bit position of the code sequence, the coincidence judgment circuit 105 outputs an error correction signal having a high level to a first input terminal of an OR gate 110. On the other hand, when the error bit position does not coincide with the bit position of the code sequence, the coincidence judgment circuit 105 outputs the error correction signal having a low level to the first input terminal of the OR gate 110. The coincidence judgment circuit 106 generates an error correction signal by comparing the error bit position outputted from the code converter 103 with the signal for representing the bit position of the code sequence which is outputted from the counter 107 in a manner similar to that of the coincidence judgment circuit 105, and then, outputs the generated error correction signal to the second input terminal of the OR gate 110. The OR gate 110 calculates the logical sum of the error correction signal inputted from the coincidence judgment circuit 105 and the error correction signal inputted from the coincidence judgment circuit 106, and outputs a signal of the logical sum to the second input terminal of the exclusive OR gate 109. The exclusive OR gate 109 calculates the exclusive logical sum of the signals inputted from the delay circuit 108 and the OR gate 110, namely inverts a bit inputted from the delay circuit 108 only when the inputted bit is an error bit, and outputs the signal of the exclusive logical sum to an output terminal 112. The action of the conventional BCH decoder shown in Fig. 1 will be described below. When a transmitted code sequence is inputted in a serial form through the input terminal 111, a syndrome is generated from the inputted code sequence by the syndrome generator 101, and then, the generated syndrome is temporarily stored in the syndrome memory 102. Thereafter, the syndrome stored in the syndrome memory 102 is converted into signals of the error bit positions of the error bits occurring in the code sequence by the code converter 103. Simultaneously, the code sequence is inputted to the delay circuit 108, and then, the delay circuit 108 delays the inputted code sequence by the predetermined delay time and outputs the delayed code sequence to the exclusive OR gate 109. At that time, the counter 107 is started, and then, the counter 107 generates a signal for representing a bit position of the delayed code sequence which is outputted from the delay circuit 108 in synchronization with the delayed code sequence by counting a clock of the code sequence, and outputs the signal to both the coincidence judgment circuits 105 and 106. The coincidence judgment circuits 105 and 106 compare the different error bit positions outputted from the code converter 103 with the bit position of the code sequence represented by the signal which is generated by the counter 107, respectively. When either one of the coincidence judgment circuits 105 and 106 judges that the error bit position outputted from the code converter 103 coincides with the bit position of the code sequence represented by the above-mentioned signal, the error correction signal having the high level is outputted from the OR gate 110 to the exclusive OR gate 109. The exclusive OR gate 109 inverts the bit of the code sequence outputted from the delay circuit 108 if the error correction signal becomes the high level. Therefore, one or two error bits included the code sequence are corrected, and then, the code sequence composed of only the correct bits when the number of the error bits is two or less is outputted as the decoded code sequence from the exclusive OR gate 109 to the output terminal 112. However, in the BCH decoder having the composition constructed as described above, it is necessary for the ROM of the code converter 103 to have the addresses of a bit number which is the same as the number of all the syndrome, and also it is necessary for data of a bit number for representing all the error bit positions, to be stored at these addresses in the ROM of the code converter 103. Therefore, the memory capacity of the ROM of the code converter 103 becomes extremely large, and then, there is such a problem that the circuit size of the BCH decoder is enlarged. Further, as the code length of the code used for the error correction becomes longer, the necessary memory capacity of the ROM of the code converter 103 exponential-functionally increases depending on the code length, and then, the circuit size of the decoder is extremely enlarged, resulting in difficulty of realizing the decoder. For example, in the case of a BCH (15, 7) code having a code length of 15 bits and a length of a information code of 7 bits, the bit number of the syndrome is eight, and the number of the addresses of the ROM is eight. Further, it is necessary to store data of eight bits at one address of the ROM in order to represent information of two positions in the code having a code length of 15. As a result, it is necessary to provide a ROM having a memory capacity of 2048 (= 8 x 2 8 ) bits. Furthermore, in the case of a BCH (255, 239) code, it is necessary to provide a ROM having a memory capacity of 1048576 bits. Since it is necessary to provide storage means such as a ROM, there is such a problem that it is difficult to construct the whole composition of the BCH decoder using an LSI. A similar decoder as described above is disclosed in GB-A-2 093 238 which defines the closest prior art from which the invention proceeds. This document describes a BCH code decoder comprising i.a. a first and a second syndrome generator, a correction inhibit circuit, a comparator and an error correction circuit. SUMMARY OF THE INVENTION An essential object of the present invention is to provide a BCH code decoder capable of correcting N or less error bits occurring in a code sequence encoded by a BCH encoding method, which can be miniaturized as compared with the conventional BCH code decoder. It is to be noted that N is a natural number, hereinafter. Another object of the present invention is to provide a method for decoding a BCH code capable of correcting N or less error bits occurring in a code sequence encoded by a BCH encoding method, in a manner more simple than that of the conventional method for decoding the BCH code. A further object of the present invention is to provide a BCH code decoder capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method, which can be constructed using logical operation circuits and also can be miniaturized as compared with the conventional BCH code decoder. A still further object of the present invention is to provide a method for decoding a BCH code capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method, in a manner more simple than that of the conventional method for decoding the BCH code. In order to accomplish the above objects, according to one aspect of the present invention, there is provided a BCH code decoder for correcting a natural number N or less of error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, comprising: first to N-th syndrome generating means for generating first to N-th syndromes from an inputted code sequence encoded by the BCH encoding method, respectively; first to N-th subtracting means for generating first to N-th check codes by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first to N-th syndromes generated by said first to N-th syndrome generating means, respectively; first error number judging means for judging a number of error bits represented by said first to N-th syndromes generated by said first to N-th syndrome generating means, respectively, and outputting a signal for representing the judged number thereof; second error number judging means for judging a number of error bits represented by said first to N-th check codes generated by said first to N-th subtracting means, respectively, and outputting a signal for representing the judged number thereof; error number comparing means for generating an error correction signal when the judged number of said signal outputted from said first error number judging means is equal to the sum of one and the judged number of said signal outputted from said second error number judging means by comparing the judged number of said signal outputted from said first error number judging means with the judged number of said signal outputted from said second error number judging means; delay means for delaying said inputted code sequence by a predetermined delay time and outputting said delayed code sequence, sequentially; and error bit correcting means for inverting each bit of said delayed code sequence outputted from said delay means and outputting it when said error correction signal is inputted from said error number comparing means and for outputting each bit of said delayed code sequence outputted from said delay means as it is without inverting it when said error correction signal is not inputted from said error number comparing means, thereby outputting the decoded and corrected code sequence. According to another aspect of the present invention, there is provided a BCH code decoder for correcting two or less error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, comprising: first and second syndrome generating means for generating first and second syndromes from an inputted code sequence encoded by the BCH encoding method, respectively; first and second subtracting means for generating first and second subtraction codes by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first and second syndromes generated by said first and second syndrome generating means, respectively; non-zero detecting means for outputting a first judgment signal when at least one bit of said first syndrome generated by said first syndrome generating means is not zero in response to said first syndrome; cube calculating means for calculating the cube of said first subtraction code generated by said first subtracting means and outputting a code of the calculated value; coincidence judgment means for outputting a second judgment signal when said code outputted from said cube calculating means coincides with said second subtraction code outputted from said second subtracting means by comparing said code outputted from said cube calculating means with said second subtraction code outputted from said second subtracting means; gate means for outputting an error correcting signal when said first judgment signal is outputted from said non-zero detecting means and said second judgment signal is outputted from said coincidence judgment means; delay means for delaying said inputted code sequence by a predetermined delay time and outputting said delayed code sequence, sequentially; and error bit correcting means for inverting each bit of said delayed code sequence outputted from said delay means and outputting it when said error correction signal is inputted from said gate means and for outputting each bit of said delayed code sequence outputted from said delay means as it is without inverting it when said error correction signal is not inputted from said gate, thereby outputting the decoded and corrected code sequence. According to a further aspect of the present invention, there is provided a BCH code decoder for correcting two or less error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, comprising: first and second syndrome generating means for generating first and second syndromes from an inputted code sequence encoded by the BCH encoding method, respectively; first subtracting means for generating a first subtraction code by subtracting a predetermined syndrome to be calculated when an error occurs at a predetermined bit of said code sequence from said first syndrome generated by said first syndrome generating means; non-zero detecting means for outputting a first judgment signal when at least one bit of said first syndrome generated by said first syndrome generating means is not zero in response to said first syndrome; cube calculating means for calculating the cube of said first subtraction code generated by said first subtracting means and outputting a code of the calculated value; adding means for adding a predetermined syndrome to be outputted from said second syndrome generating means when an error occurs at a predetermined bit of said code sequence, to said code outputted from said cube calculating means, and outputting a code of the added value; coincidence judgment means for outputting a second judgment signal when said code outputted from said adding means coincides with said second subtraction code outputted from said second subtracting means by comparing said code outputted from said adding means with said second syndrome outputted from said second syndrome generating means; gate means for outputting an error correcting signal when said first judgment signal is outputted from said non-zero detecting means and said second judgment signal is outputted from said coincidence judgment means; delay means for delaying said inputted code sequence by a predetermined delay time and outputting said delayed code sequence, sequentially; and error bit correcting means for inverting each bit of said delayed code sequence outputted from said delay means and outputting it when said error correction signal is inputted from said gate means and for outputting each bit of said delayed code sequence outputted from said delay means as it is without inverting it when said error correction signal is not inputted from said gate means, thereby outputting the decoded and corrected code sequence. According to a still further aspect of the present invention, there is provided a method for decoding a BCH code so as to correct a natural number N or less of error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, including steps of: generating first to N-th syndromes from an inputted code sequence encoded by the BCH encoding method, respectively; generating first to N-th check codes by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first to N-th syndromes, respectively; generating error correction information when a number of error bits represented by said first to N-th syndromes is equal to the sum of one and a number of error bits represented by said first to N-th check codes; and correcting one or more error bits of said inputted code sequence according to said error correction information. According to a still more further aspect of the present invention, there is provided a method for decoding a BCH code so as to correct two or less error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, including the steps of: generating first and second syndromes from an inputted code sequence encoded by the BCH encoding method, respectively; generating first and second subtraction codes by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first and second syndromes, respectively; generating error correction information when at least one bit of said first syndrome is not zero and the cube of said first subtraction code coincides with said second subtraction code; and correcting one or more error bits of said inputted code sequence according to said error correction information. According to a more still further aspect of the present invention, there is provided a method for decoding a BCH code so as to correct two or less error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, including the steps of: generating first and second syndromes from an inputted code sequence encoded by the BCH encoding method, respectively; generating a first subtraction code by subtracting a predetermined syndrome to be calculated when an error occurs at a predetermined bit of said code sequence from said first syndrome; adding a predetermined second syndrome to be calculated when an error occurs at a predetermined bit of said code sequence, to the cube of said first subtraction code and obtaining the sum thereof; generating error correction information, when at least one bit of said first syndrome is not zero and said sum coincides with said second syndrome; and correcting one or more error bits of said inputted code sequence according to said error correction information. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing a composition of a conventional BCH code decoder capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method; Fig. 2 is a block diagram showing a composition of a BCH code decoder of the first preferred embodiment according to the present invention, which is capable of correcting N or less error bits occurring in a code sequence encoded by a BCH encoding method; Fig. 3 is a block diagram showing a composition of a BCH code decoder of the second preferred embodiment according to the present invention, which is capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method; Fig. 4 is a block diagram showing a composition of a BCH code decoder of the third preferred embodiment according to the present invention, which is capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method; Fig. 5 is a block diagram showing a composition of a BCH code decoder of the fourth preferred embodiment according to the present invention, which is capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method; Fig. 6 is a block diagram showing a composition of a syndrome generator for generating first syndromes S 1 , k shown in Figs. 4 and 5, which is provided in the BCH code decoder for decoding the BCH (15, 7) code; Fig. 7 is a block diagram showing a composition of a syndrome generator for generating a second syndromes S 3 , k shown in Figs. 4 and 5, which is provided in the BCH code decoder for decoding the BCH (15, 7) code; Fig. 8 is a block diagram showing a composition of a subtracter shown in Figs. 4 and 5, which is provided in the BCH code decoder for decoding the BCH (15, 7) code; and Fig. 9 is a block diagram showing a composition of each of another subtracter shown in Fig. 4 and an adder shown in Fig. 5, which are provided in the BCH code decoder for decoding the BCH (15, 7) code. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the attached drawings. (1) BCH Code First of all, a BCH code capable of correcting N or less error bits will be described below, wherein N is a natural number. The BCH code capable of correcting N or less error bits is composed of code bits of roots which are elements of α, α 3 ..., α 2N-1 of the Galois field GF (2 m ), and has a code length of n (= 2 m - 1) bits, wherein m and n are natural numbers, respectively. In the present specification, respective calculations described hereinafter are performed over the Galois field GF (2 m ). Namely, in the case of the following code sequence R: R = [a 1 , a 2 , ..., a n-1 , a n ] the above code sequence R including the following N check matrixes: H 1 = [α n-1 , α n-2 , ..., α 1 , a 0 ] H 3 = [α 3(n-1) , α 3(n-2) , ..., α 3 , α 0 ] ...... H 2N-1 = [α (2N-1)(n-1) , α (2N-1)(n-2) , ..., α (2N-1) , α 0 ] is encoded so as to establish the following equations: H 1 R T = 0 H 3 R T = 0 ..... H 2N-1 R T = 0 If a code sequence R' when one or more error bits occur therein is represented as follows: R' = [a 1 ', a 2 ', ..., a n-1 ' a n '] the above code sequence R' is represented by the following equation: R' = R + E where an error sequence E is represented by the following equation: E = [e 1 , e 2 , ..., e n-1 , e n ] a k ' = a k + e k , for 1 ≤ a natural number k ≤ n e k = 1, for an error bit = 0, for a correct bit or non-error bit It is to be noted that the error code sequence R' includes the non-error code sequence R when E = [0, 0, ..., 0], hereinafter, as is apparent from the equations (5) to (7), (8a) and (8b). Further, N syndromes S 1 , S 3 , S 2N-1 are obtained based on the N check matrixes H 1 , H 3 , ..., H 2N-1 from the error code sequence R' as follows: S 1 = H 1 R' T = H 1 R T + H 1 E T = H 1 E T S 3 = H 3 E T ..... S 2N-1 = H 2N-1 E T In the first to the fourth preferred embodiments, a syndrome S K α k-1 (K = 1, 3, ..., 2N-1 and k = 1, 2, ..., n) is referred as a syndrome S K,k generated in a k-th bit timing upon processing the code sequence, as described in detail later. Further, a group of syndromes S 1 , S 1 α, ..., S 1 α n-1 is referred to as first syndromes, a group of syndromes S 3 , S 3 α, ..., S 3 α n-1 is referred to as second syndromes, ..., and a group of syndromes S 2N-1 , S 2N-1 α, ..., S 2N-1 α n-1 is referred to as N-th syndromes. (2) First Preferred Embodiment Fig. 2 is a block diagram showing a composition of a BCH code decoder of the first preferred embodiment according to the present invention, which is capable of correcting N or less error bits occurring in a code sequence encoded by a BCH encoding method. Referring to Fig. 2, a code sequence R' of the BCH code having a code length of n is inputted in a serial form through an input terminal 91 to a delay circuit 88 and syndrome generators 81a to 81c. The syndrome generators 81a, 81b, ... , and 81c generate the syndromes S 1,k , S 2,k , ..., S 2N-1,k , in a k-th bit timing among the code sequence based on the check matrixes H 1 , H3, ..., H 2N-1 in response to the code sequence R' and outputs them to subtracters 83a to 83c and an error number judgment circuit 87, respectively. The subtracters 83a to 83c subtracts α (n-1) , α 3(n-1) , ..., α (2N-1)(n-1) from the inputted syndromes S 1,k , S 2 ,k, ..., S 2N-1,k , respectively, and outputs the first and the second to the n-th check codes CC 1 , CC 2 , ..., CC N of the subtraction results to the error number judgment circuit 85, respectively. The above values α (n-1) , α 3(n-1) , ..., α (2n-1)(n-1) to be subtracted in the subtracters 83a to 83c respectively correspond to syndromes generated when e 1 = 1, and in this case, they are the values of the first row of the check matrixes H 1 , H 3 , ..., H 2N-1 when e 1 = 1. It is to be noted that the values to be subtracted therein are changed depending on the BCH code to be used in a manner well known to those skilled in the art. The error number judgment circuit 85 judges the number of error bits (referred to as an error number hereinafter) represented by the first and the second to the N-th check codes CC 1 , CC 2 , ..., CC N in a manner well known to those skilled in the art, and outputs a signal for representing the error number EN 1 thereof to an error number comparator 90. On the other hand, the error number judgment circuit 87 judges the error number represented by the first and the second to the N-th syndromes S 1,k , S 3 ,k, ..., S 2N-1,k in a manner well known to those skilled in the art, and outputs a signal for representing the error number EN 2 thereof to the error number comparator 90. The error number comparator 90 compares the error number EN 1 with the error number EN 2 in response to the signals inputted from the error number judgment circuits 85 and 87. If EN 2 = EN 1 + 1, the error number comparator 90 outputs an error correction signal having a high level to the second input terminal of an exclusive OR gate 89. Otherwise, the error number comparator 90 outputs the error correction signal having a low signal thereto. On the other hand, the delay circuit 88 delays the code sequence R' inputted through the input terminal 91 by a predetermined delay time of one BCH code, and outputs it to the first input terminal of the exclusive OR gate 89, sequentially. The exclusive OR gate 89 calculates the exclusive logical sum of the signals inputted from the delay circuit 88 and the error number comparator 90, namely inverts a bit inputted from the delay circuit 88 only when the inputted bit is an error bit, namely the error correction signal becomes the high level, and then, outputs the signal of the exclusive logical sum thereof to an output terminal 92. Therefore, one or more error bits up to the N bit error bits included the error code sequence R' are corrected, and then, the decoded code sequence composed of only the corrected bits when the number of the error bits is N or less is outputted from the exclusive OR gate 89 to the output terminal 92. (3) Second Preferred Embodiment Fig. 3 is a block diagram showing a composition of a BCH code decoder of the second preferred embodiment according to the present invention, which is capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method. In Fig. 3, the components which are the same as those shown in Fig. 2 are denoted by the numerals which are the same as those shown in Fig. 2. In the case of the BCH decoder of the second preferred embodiment, the error number judgment circuit 85 judges the error number represented by the first and the second check codes CC 1 and CC 2 , and outputs a signal for representing the error number EN 1 thereof to the error number comparator 90. On the other hand, the error number judgment circuit 87 judges the error number represented by the first and the second syndromes S 1 and S 3 , and outputs a signal for representing the error number EN 2 thereof to the error number comparator 90. Thereafter, the error number comparator 90 outputs the error correction signal having the high level to the exclusive OR gate 89, if the error number EN 2 of the signal outputted from the error number judgment circuit 87 is one and the error number EN 1 of the signal outputted from the error number judgment circuit 85 is zero, or the error number EN 2 is two and the error number EN 1 is one. Otherwise, the error number comparator 90 outputs the error correction signal having the low level thereto. Therefore, one or two error bits included the error code sequence R' are corrected, and then, the decoded code sequence composed of only the corrected bits when the number of the error bits is two or less is outputted from the exclusive OR gate 89 to the output terminal 92. (4) Third Preferred Embodiment Fig. 4 is a block diagram showing a composition of a BCH code decoder of the third preferred embodiment according to the present invention, which is capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method. The composition of the BCH decoder of the third preferred embodiment and the action thereof when errors occur in the i-th and j-th bits among the code sequence R, namely e i = 1, e j = 1 and e k = 0 (1 ≤ k ≤ n and k ≠ i, k ≠ j) will be described below with reference to Fig. 4. Referring to Fig. 4, a code sequence R' of the BCH code is inputted in a serial form through an input terminal 11 to a delay circuit 8 and syndrome generators 1 and 2. In response to the code sequence R', the syndrome generator 1 generates the first syndrome S 1,k in a k-th bits timing among the code sequence R' based on the check matrix H 1 . For example, in response to the first bit a 1 ' of the code sequence R', the syndrome generator 1 generates the following syndrome S 1 : S 1 = H 1 R' T = α n-i + α n-j which is outputted to a subtracter 3 and a non-zero detector 7. Further, in response to the code sequence R', the syndrome generator 2 generates the second syndrome S 3,k in a k-th bit timing based on the check matrix H 3 . For example, in response to the first bit a 1 ' of the code sequence R', the syndrome generator 2 generates the following syndrome S 3 : S 3 = H 3 R' T = α 3(n-i) + α 3(n-j) which is outputted to a subtracter 4. On the other hand, the delay circuit 8 delays the code sequence R' inputted through the input terminal 11 by a predetermined delay time of one BCH code, and outputs it to the first input terminal of an exclusive OR gate 9. At a timing when the whole code sequence R' has been completely inputted to the delay circuit 8, the first bit a 1 ' of the code sequence R' is outputted from the delay circuit 8, and then, the syndromes S 1 and S 3 are outputted from the syndrome generators 1 and 2. Thereafter, the BCH code decoder starts in an error correction process. In the time interval while performing the error correction process, data of zero are always inputted in a serial form through the input terminal 11 to the delay circuit 8 and the syndrome generators 1 and 2, and the syndrome generators 1 and 2 and delay circuit 8 are operated, sequentially, in synchronization to a clock (not shown) of the code sequence R'. As described above, the timing when the syndromes S 1 and S 3 are outputted from the syndrome generators 1 and 2 is referred to as the first bit timing, and thereafter, a timing when a time interval of one clock has been passed from the first bit timing is referred to as the second bit timing. Similarly, a timing when a time interval of (n-1) clocks has been passed from the first bit timing is referred to as the n-th bit timing. It is to be noted that the syndrome generators 1 and 2, the delay circuit 8 and the other circuits 3 to 10 which are provided in the BCH code decoder shown in Fig. 4 operate in synchronization to the clock (not shown) of the code sequence R'. When data of zero are inputted to the syndrome generator 1 at the second bit timing, the syndrome generator 1 generates the syndrome S 1 α and outputs it. Thereafter, the syndrome generator 1 operates similarly, and then, generates at a k-th bit timing the following syndrome: s 1 α k-1 = (α n-i + α n-j )·α k-1 = α n-1 ·(α k-i + α k-j ) and outputs it to the subtracter 3 and the non-zero detector 7. On the other hand, when data of zero are inputted to the syndrome generator 2 at the second bit timing, the syndrome generator 2 generates the syndrome S 2 α 3 and outputs it. Thereafter, the syndrome generator 2 operates similarly, and then, generates at a k-th bit timing the following syndrome: S 3 α 3(k-1) = (α 3(n-i) + α 3(n-j) )·α 3(k-1) = α 3(n-1) ·(α 3(k-i) + α 3(k-j) ) and outputs it to the subtracter 4. Further, the subtracter 3 subtracts α n-1 from the syndrome S 1,k outputted from the syndrome generator 1, and then, outputs data SS 1 of the subtraction result thereof to a cube calculator 5. The cube calculator 5 calculates data SS1 cubed and outputs to a coincidence judgment circuit 6 the following code P 1 of the calculation result thereof: P 1 = (S 1 α k-1 - α n-1 ) 3 = α 3(n-1) ·(α k-i + α k-j - 1) 3 = α 3(n-1) ·{α 3(k-i) + α 3(k-j) - 1 + (α k-i + α k-j )(α k-i - 1)(α k-j - 1)} The subtracter 4 subtracts α 3(n-1) from the syndrome S 3,k outputted from the syndrome generator 2, and outputs to the coincidence judgment circuit 6 the following code P 3 of the subtraction result thereof: P 3 = S 3 α 3(k-1) - α 3(n-1) = α 3(n-1) ·{α 3(k-i) + α 3(k-j) - 1} Further, the coincidence circuit 6 compares the code P 1 with the code P 3 , and then, if the code P 1 coincides with the code P 3 , the coincidence judgment circuit 6 outputs a judgment signal D 2 having the high level to the second input terminal of an AND gate 10. Otherwise, the coincidence judgment circuit 6 outputs the judgment signal D 2 having the low level thereto. In this case, when k = i and k = j, the code P 1 coincides with the code P3. Namely, at each of the i-th and j-th bit timings, the judgment signal D 2 having the high level is outputted. The non-zero detector 7 is provided for judging whether or not the first syndrome S 1,k is zero. At each of the first to the n-th bit timings, since the first syndrome S 1,k is not zero, the non-zero detector 7 outputs a judgment signal D 1 having the high level to the first input terminal of the AND gate 10. If the judgment signal D 2 having the high level is outputted from the coincidence judgment circuit 6 and the judgment signal D 1 having the high level is outputted from the non-zero detector 7, the AND gate 10 outputs an error correction signal having the high level to the second input terminal of the exclusive OR gate 9. Namely, at each of the i-th and j-th bit timings, the error correction signal having the high level is outputted from the AND gate 10 to the exclusive OR gate 9. Otherwise, the AND gate 10 outputs the error correction signal having the low level. Further, the exclusive OR gate 9 calculates the exclusive logical sum of the signals inputted from the delay circuit 8 and the AND gate 10, namely inverts a bit inputted from the delay circuit 8 when the error correction signal becomes the high level. Accordingly, at the i-th and j-th bit timings, the i-th bit ai' and the j-th bit aj' of the code sequence R' outputted from the delay circuit 8 are respectively inverted by the exclusive OR gate 9 in responsive to the error correction signal having the high level. As a result, bit errors of the i-th bit ai' and the j-th bit aj' are corrected, and then, the corrected i-th and j-th bits are outputted from the exclusive OR gate 9 to an output terminal 12. On the other hand, the bits other than the i-th and j-th bits are outputted without processing them thereto. Accordingly, the corrected code sequence R without the error code E is outputted from the exclusive OR gate 9 to the output terminal 12. In the above description, the action of the BCH code decoder shown in Fig. 4 when errors occur in the i-th and j-th bits among the code sequence R is described. However, when an error occurs in the i-th bit among the code sequence R', the syndromes S 1 and S 3 and the codes P 1 and P 3 are represented as follows: S 1 = α n-i S 3 = α 3(n-i) P 1 = α 3(n-1) ·{α 3(k-i) - 1 - α k-i (α k-i - 1)} P 3 = α 3(n-1) ·{α 3(k-i) - 1} Only at the i-th bit timing, the error correction signal having the high level is outputted from the AND gate 10 to the exclusive OR gate 9. Then, an error in the i-th bit among the code sequence R' is corrected. Furthermore, in the case of no error among the code sequence R', the syndromes S 1 and S 3 and the codes P 1 and P 3 are as follows: S 1 = 0 S 3 = 0 P 1 = -α 3(n-1) P 3 = -α 3(n-1) While the BCH code decoder shown in Fig. 4 performs the above-mentioned decoding process, since the code P 1 always coincides with the code P 3 , the judgment signal D 2 having the high level is outputted from the coincidence judgment circuit 6 to the AND gate 10, however, the judgment signal D 1 having the low level is outputted from the non-zero detector 7 to the AND gate 10. Therefore, in this case, the AND gate 10 outputs the error correction signal having the low level. As described above, the BCH code decoder of the third preferred embodiment according to the present invention can correct bit errors of two bits or less which may occur in the code sequence R' of the BCH code. Respective concrete compositions of the syndrome generators 1 and 2, the subtracters 3 and 4 and the cube calculator 5 which are provided in the BCH code decoder for decoding the BCH (15, 7) code will be described below. Fig. 6 is a block diagram showing a composition of the syndrome generator 1 shown in Fig. 4, which is provided for generating the first syndrome S 1,k based on the check matrixes H 1 from serial data a t + e t of the error code sequence R'. Referring to Fig. 6, the syndrome generator 1 comprises two exclusive OR gates 42a and 42b and four delay type flip flops 41a to 41d, wherein each of the exclusive OR gates 42a to 42b is an adder of modulo 2 as well known in those skilled in the art. The serial data are inputted to the first input terminal of the exclusive OR gate 42a. The output terminal of the exclusive OR gate 42a is connected to the input terminal of the flip flop 41a, and the output terminal of the flip flop 41a is connected to the first input terminal of the exclusive OR gate 42b. The output terminal of the exclusive OR gate 42b is connected to the input terminal of the flip flop 41b. The flip flops 41b to 41d are connected in series. The output terminal of the flip flop 41d is connected to respective second input terminals of the exclusive OR gates 42a and 42b. In the syndrome generator 1 constructed as described above, the first to the fourth bits b 0 to b 3 of the first syndrome S 1,k in a k-th bit timing are outputted from respective output terminals of the flip flops 41a to 41d to the subtracter 3 and the non-zero detector 7. Fig. 7 is a block diagram showing a composition of the syndrome generator 2 shown in Fig. 4, which is provided for generating the second syndrome S 3,k based on the check matrixes H 3 from the inputted serial data a t + e t of the error code sequence R'. Referring to Fig. 7, the syndrome generator 2 comprises four exclusive OR gates 52a and 52d and four delay type flip flops 51a to 51d. The serial data are inputted to the first input terminal of the exclusive OR gate 52a, and the output terminal of the exclusive OR gate 52a is connected to the input terminal of the flip flop 51a. The output terminal of the flip flop 51a is connected to the first input terminal of the exclusive OR gate 52d. The output terminal of the exclusive OR gate 52d is connected to the input terminal of the flip flop 51d, and the output terminal of the flip flop 51d is connected to respective second input terminals of the exclusive OR gates 52c and 52d. The output terminal of the exclusive OR gate 52c is connected to the input terminal of the flip flop 51c, and the output terminal of the flip flop 51c is connected to " respective first input terminals of the exclusive OR gates 52b and 52c. The output terminal of the exclusive OR gate 52b is connected to the input terminal of the flip flop 51b, and the output terminal of the flip flop 51b is connected to respective second input terminals of the exclusive OR gates 52a and 52b. In the syndrome generator 2 constructed as described above, the first to the fourth bits b 0 ' to b 3 ' of the second syndrome S 3,k in a k-th bit timing are outputted from respective output terminals of the flip flops 51a to 51d to the subtracter 4. Fig. 8 is a block diagram showing a composition of the subtracter 3 shown in Fig. 4, which is provided for subtracting·α 14 from the first syndrome S 1,k inputted from the syndrome generator 1 shown in Fig. 4. Referring to Fig. 8, the subtracter 3 comprises two inverters 61a and 61b. The bit b 3 of the first syndrome S 1,k is inverted by the inverter 61a, and then, the inverted bit thereof is outputted as a bit c 3 of the data SS1 to the cube calculator 5. The bits b 2 and b 1 of the first syndrome S 1,k are outputted as they are as bits c 2 and c 1 of the data SS1 thereto, respectively. The bit b 0 of the first syndrome S 1,k is inverted by the inverter 61b, and then, the inverted bit thereof is outputted as a bit c 0 of the data SS1 thereto. Fig. 9 is a block diagram showing a composition of the subtracter 4 shown in Fig. 4, which is provided for subtracting α 3x14 (= α 42 = α 12 ) from the second syndrome S 3,k inputted from the syndrome generator 2 shown in Fig. 4. Referring to Fig. 9, the subtracter 4 comprises four inverters 61c to 61f. The bits b 3 ' to b 0 ' of the second syndrome S 3,k are respectively inverted by the inverters 61c to 61f, and then, the inverted bits thereof are outputted as bits c 3 ' to c 0 ' of of the code P 3 to the coincidence judgment circuit 6. Furthermore, the cube calculator 5 calculates the results of the following logical operations: d 3 = c 3 + c 3 ·c 2 + c 3 ·c 1 + c 2 + c 1 d 2 = c 3 ·c 2 + c 3 ·c 1 + c 3 ·c 0 + c 2 + c 2 ·c 1 + c 2 ·c 0 + c 1 ·c 0 d 1 = c 3 + c 3 ·c 2 + c 2 ·c 0 + c 1 ·c 0 d 0 = c 3 ·c 1 + c 2 ·c 1 + c 2 ·c 0 + c 0 from a matrix [c 3 , c 2 , c 1 , c 0 ] of the data SS 1 inputted from the subtracter 3, and outputs a matrix [d 3 , d 2 , d 1 , d 0 ] of the results thereof as the code P 1 to the coincidence judgment circuit 6. In the above logical equations (24a) to (24d), X · Y means the logical product of X and Y, and X + Y means the exclusive logical sum of X and Y. Further, the logical operations are performed with giving the priority to the operation of the logical product as compared with that of the exclusive logical sum. In the BCH code decoder comprising the syndrome generators 1 and 2 respectively shown in Figs. 6 and 7, the subtracters 3 and 4 respectively shown in Fig. 8 and 9, and the cube calculator 7 as described above, the shape of the BCH code decoder can be miniaturized, and the BCH code decoder capable of correcting two or less error bits can be constituted by using only the logical operation circuits. (5) Fourth Preferred Embodiment Fig. 5 is a block diagram showing a composition of a BCH code decoder of the fourth preferred embodiment according to the present invention, which is capable of correcting two or less error bits occurring in a code sequence encoded by a BCH encoding method. In Fig. 5, the components which are the same as those shown in Fig. 4 are denoted by the numerals which are the same as those shown in Fig. 4. The differences between the BCH code decoder of the third and fourth preferred embodiments respectively shown in Figs. 4 and 5 are that an adder 24 is provided between the cube calculator 5 and the coincidence judgment circuit 6 instead of the subtracter 4. The adder 24 is provided for adding α 3(n-1) to the data of the code P 1 , and outputting the following code P 1 ' of the addition result thereof to the coincidence judgment circuit 6: P 1 ' = {S 1 α k-1 - α n-1 } 3 + α 3(n-1) = α 3(n-1) ·{(α k-i + α k-j - 1) 3 + 1} =α 3(n-1) · {α 3(k-i) + α 3(k-j) + (α k-i + α k-j )(α k-i - 1)(α k-j - 1)} It is to be noted that α 3(n-1) to be added in the adder 24 corresponds to the second syndrome S 3,k outputted when e 1 = 1, and the above value to be added is changed depending on the BCH code to be used. It is to be noted that the following second syndrome S 3,k which is outputted from the syndrome generator 2 is directly inputted to the coincidence judgment circuit 6: S 3 =α 3(n-1) ·{α 3(k-i) + α 3(k-j) } When errors occur respectively in the i-th and j-th bits among the code sequence R, namely e i = 1, e j = 1 and e k = 0 (1 ≤ k ≤ n, k ≠ i and k ≠ j), the code P 1 ' coincides with the second syndrome S 3,k when k = i and k = j, the BCH code decoder of the fourth preferred embodiment shown in Fig. 5 can correct the error bits in a manner similar to that of the BCH code decoder of the third preferred embodiment shown in Fig. 4. In the BCH code decoder of the fourth preferred embodiment for decoding the BCH (15, 7) code, since the addition operation over the Galois field GF (2 4 ) is the same as the subtraction operation thereover, the adder 24 has a composition which is the same as that of the subtracter 3. In the BCH code decoder of the fourth preferred embodiment as described above, the shape of the BCH code decoder can be miniaturized, and the BCH code decoder capable of correcting two or less error bits can be constituted by using only the logical operation circuits. It is to be noted that the BCH code decoders of the first to the fourth preferred embodiments according to the present invention can be constructed using a microprocessor unit and software.

Claims: A BCH code decoder for correcting a natural number N or less of error bits occurring in a code sequence composed bits encoded by a BCH encoding method, comprising: first to N-th syndrome generating means (81a, 81b, 81c; 1, 2) for respectively generating first to N-th syndromes from an inputted code sequence encoded by the BCH encoding method; delay means (88) for delaying said inputted code sequence by a predetermined delay time and for sequentially outputting a delayed code sequence; first error number judging means (87) for judging a number of error bits represented by said first to N-th syndromes respectively generated by said first to N-th syndrome generating means (81a, 81b, 81c; 1, 2), and for outputting a signal representing the judged number thereof; error number comparing means (90) for generating an error correction signal; and error bit correcting means (89) for inverting each bit of said delayed code sequence outputted from said delay means (88) and for outputting each inverted bit when said error correction signal is inputted from said error number comparing means (90) and for outputting each bit of said delayed code sequence outputted from said delay means (88) as it is without inverting it when said error correction signal is not inputted from said error number comparing means (90), thereby outputting the decoded and corrected code sequence; characterized by first to N-th subtracting means (83a, 83b, 83c; 3, 4) for respectively generating first to N-th check codes by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first to N-th syndromes generated by said first to N-th syndrome generating means (81a, 81b, 81c; 1, 2); and second error number judging means (85) for judging a number of error bits represented by said first to N-th check codes respectively, generated by said first to N-th subtracting means (83a, 83b, 83c; 3, 4), and for outputting a signal representing the judged number thereof; wherein said error number comparing means (90) generates an error correction signal when the judged number of said signal outputted from said first error number judging means (87) is equal to the sum of one and the judged number of said signal outputted from said second error number judging means (85) by comparing the judged number of said signal outputted from said first error number judging means (87) with the judged number of said signal outputted from said second error number judging means (85). The BCH decoder as claimed in Claim 1, wherein the natural number N is equal to 2; wherein said first error number judging means includes non-zero detecting means (7) for outputting a first judgment signal when at least one bit of said first syndrome generated by said first syndrome generating means (81a) is not zero in response to said first syndrome; wherein said second error number judging means includes cube calculating means (5) for calculating the cube of said first subtraction code generated by said first subtraction means (3) and for outputting a cubic code of the calculated cube of said first subtraction code, and coindidence judgment means (6) for outputting a second judgment signal when said cubic code outputted from said cube calculating means (5) coincides with said second subtraction code outputted from said second subtraction means (4); wherein said error number comparing means includes gate means (10) for outputting an error correcting signal when said first judgment signal is outputted from said non-zero detecting means (7) and said second judgment signal is outputted from said coincidence judgment means (6); wherein said first syndrome generating means (1) is a multiplier for multiplying the inputted code sequence by a primitive element α, and said first syndrome generating means (1) sequentially multiplies said first syndrome by the primitive element α in an error bit correction process performed by said error bit correction means (9) after calculating said first syndrome; and wherein said second syndrome generating means (2) is a multiplier for multiplying the inputted code sequence by α 3 , and said second syndrome generating means (2) sequentially multiplies said second syndrome by α 3 in the error bit correction process performed by said error bit correction means (9) after calculating said second syndrome, thereby outputting the decoded and corrected code sequence. The BCH code decoder as claimed in Claim 1, wherein the natural number N is equal to 2; wherein said first error number judging means includes non-zero detecting means (7) for outputting a first judgment signal when at least one bit of said first syndrome generated by said first syndrome generating means (1) is not zero in response to said first syndrome; wherein said second subtracting means and said second error number judging means include cube calculation means (5) for calculating the cube of said first subtraction code generated by said first subtracting means (3) and for outputting a cubic code of the calculated cube of said first subtraction code, adding means (24) for adding a predetermined syndrome to be outputted from said second syndrome generating means (2) when an error occurs at a predetermined bit of said code sequence, to said cubic code outputted from said cube calculating means (5), and for outputting an addition code of the addition result, and coincidence judgment means (6) for outputting a second judgment signal when said addition code outputted from said adding means (24) coincides with said second syndrome outputted from said second syndrome generating means (2) by comparing said addition code outputted from said adding means (24) with said second syndrome outputted from said second syndrome generating means (2); and wherein said error number comparing means (90) includes gate means (10) for outputting an error correcting signal when said first judgment signal is outputted from said non-zero detecting means (7) and said second judgment signal is outputted from said coincidence judgment means (6). A method of decoding a BCH code so as to correct a natural number N or less of error bits occurring in a code sequence composed of bits encoded by a BCH encoding method, comprising the steps of: respectively generating first to N-th syndromes from an inputted code sequence encoded by the BCH encoding method; generating error correction information; and correcting one or more error bits of said inputted code sequence according to said error correction information; characterized by the further steps of: respectively generating first to N-th check codes by subtracting predetermined syndromes to be calculated when an error occurs at a predetermined bit of said code sequence from said first to N-th syndromes; wherein said error correction information is generated when a number of error bits represented by said first to N-th syndromes is equal to a sum obtained by adding one to a number of error bits represented by said first to N-th check codes. The method as claimed in Claim 4, wherein the natural number N is equal to 2; wherein the step of generating the first to second check codes includes a step of respectively generating first and second subtraction codes by subtracting syndromes which are constants calculated when an error occurs at a predetermined bit of said code sequence from said first and second syndromes, wherein the step of generating error correction information includes a step of generating error correction information when at least one bit of said first syndrome is not zero and a cube of said first subtraction code coincides with said second subtraction code, wherein said method further includes: generating a new first syndrome by multiplying said first syndrome by a primitive element α; generating a new second syndrome by multiplying said second syndrome by α 3 ; and repeating the processes of the step of generating the first and second subtraction codes, the step of generating error correction information, the step of correcting, the step of generating the new first syndrome and the step of generating the new second syndrome. The method as claimed in Claim 4, wherein the natural number N is equal to 2; wherein the step of generating first to N-th check codes includes a step of generating a first subtraction code by subtracting a predetermined syndrome to be calculated when an error occurs at a predetermined bit of said code sequence from said first syndrome, wherein the step of generating error correction information includes: generating a cubic code by cubing said first subtraction code; generating an addition code by adding a predetermined second syndrome to be calculated when an error occurs at a predetermined bit of said code sequence to said cubic code; and generating error correction information, when at least one bit of said first syndrome is not zero and said addition code coincides with said second syndrome.

Inventors: KIMURA TOMOHIRO, KIMURA, TOMOHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1990
Main classification: H03M13
IPC codes: H03M13