Vertical thin film transistor and optical sensor having leakage current suppression elements

Abstract: A thin film transistor/optical sensor including a substrate (10) upon which are supported a gate electrode layer (12), a gate dielectric layer (14), a source electrode comprising finger elements (16), a semiconductor layer (24) overlying the gate dielectric layer and at least partially surrounding the source electrode, a drain electrode layer (26) contiguous with the semiconductor layer, barrier elements (22) for inhibiting a drain field from reaching the source electrode, and a transparent, electrically conductive drain contact member (28) contiguous with said drain electrode layer, through which optical energy may pass to the semiconductor layer.

Description: This invention relates to a thin film device which may be used interchangeably as either a transistor or as an optical sensor. Because of their relative ease of fabrication on large area substrates thin film transistors (TFTs) have been actively studied for use in driving individual pixels in large area displays, such as liquid crystal displays. The TFTs generally comprise laterally spaced apart source and drain electrodes, held at different potentials, and electrically interconnected by a semiconductor material which forms a channel therebetween. Current flow between these electrodes, is controlled by the application of a voltage to a gate electrode, which is adjacent a portion of the semiconductor channel and is insulated therefrom. The gate field acts to invert or accumulate a portion of the semiconductor material, thereby conductively coupling the source and drain electrodes. Amorphous silicon technology was initially developed primarily for photovoltaics but recently the microelectronic applications therefor have become more and more important. This material is ideally suited for use in large area arrays because of the low deposition temperatures involved in its fabrication and the availability of large area deposition and lithographic equipment. A shortcoming of amorphous silicon is its relatively low electron mobility which limits the operating speed of these transistors. The operating speed may be improved and the output current may be increased by reducing the channel length L, because the transit time of electrons across the channel is proportional to L² and the output current is inversely proportional to the channel length (1/L). Typically, lithographically produced amorphous silicon TFTs have channel lengths of about 10 µm. Of course, the channel length could possibly be decreased substantially by using critical lithographic techniques developed for VLSI fabrication, but this solution is very costly and is impractical over the large areas contemplated (e.g. one foot square and larger). In fact, it is likely that a one micrometer feature size cannot be accurately maintained over very large areas. Another consideration to be borne in mind with respect to amorphous silicon devices is that these TFTs operate with a field effect mobility of around 1 cm²/volt-sec despite the fact that the amorphous silicon electron band mobility is 10 to 20 cm²/volt-sec. This is due to traps in the material, in the form of localized tail states, which allow only a small fraction (about 10 to 20%) of the charge induced into the channel of these TFTs to become mobile carriers. For a 10 µm feature size and gate width-to-length ratio of 10, one may expect output currents on the order of 10 to 50 µamp and a transit time of approximately 100 nsec for drive voltages (V DS ) in the range of 10 to 20 volts. In practice, switching speeds also will be reduced by circuit capacitances. Improved current drive capabilities necessitate shorter channel lengths. Although amorphous silicon has been the most promising semiconductor material for TFTs, silicon in its polycrystalline or microcrystalline states may be fabricated over large areas and yield attractive results, and other semiconductor materials, such as Ge, GaAs and CdS, in these three states also have been found to be satisfactory. A vertical, short channel thin film transistor, whose effective channel length is much less than any minimum lithographic feature size used in its fabrication, is disclosed in EP-A-0 335 632. Thin film amorphous silicon sensors and phototransistors are well known. In large area applications, where transistors and sensors are fabricated upon the same substrate, such as, for example, in an optical scanning array, it would be convenient to configure these devices so as to have compatible fabrication techniques. It is an object of the present invention to provide a thin film structure which will operate as either a transistor (more specifically, a short channel, high current, thin film transistor) or an optical sensor (more specifically, a high gain optical sensor). The present invention provides a thin film transistor/sensor device as defined in the accompanying claim 1. By way of example, embodiments of the invention will now be described with reference to the accompanying drawings, wherein: Figure 1 is a side sectional view of a vertical thin film transistor/sensor, Figure 2 is a plan view of the source electrode array of the transistor/sensor of Figure 1, Figure 3 is a side sectional view similar to Figure 1 showing the movement of photogenerated electron/hole pairs, Figure 4 is a side sectional view similar to Figure 3 showing a trapped hole centrally located between two source electrode fingers, Figure 5a is a graphical representation of light intensity during a single pulse of illumination, Figure 5b is a graphical representation of current flow through the sensor in response to the single pulse of illumination, Figure 6 is a plan view of a pair of interdigitated source electrode arrays for use in a transistor/sensor according to the present invention, Figure 7 is a side sectional view of a thin film transistor similar to that of Figure 1 including proximity current barrier means, Figure 8 is a side sectional view of a thin film transistor similar to that of Figure 1 showing another form of proximity current barrier means, Figure 9 illustrates light and dark output characteristics for the device of Figure 7, and Figure 10 is an enlarged side sectional view, similar to Figure 7, showing an additional blocking layer. Turning now to Figure 1 there is illustrated a vertical, bottom gate, short channel, thin film transistor/sensor. By vertical we mean that the primary path of the majority charge carrier movement is through the thickness of the semiconductor layer in the direction parallel to the direction of the gate field, as opposed to movement within a narrow channel of the semiconductor layer extending in the direction perpendicular to the gate field. We have found this vertical orientation to be desirable because the current path between source and drain electrodes is established primarily by the deposited thickness of a semiconductor layer and not by lithography, and as this is short, it enables more current to flow. Since it is well known that the art of thin film layer deposition allows accurate conformal formation of layers on the order of tens of Angstroms, this transistor configuration allows one to obtain the performance of 1 micron, and shorter, channel lengths while using 5 to 10 µm lithography or larger. Furthermore, this design separates the gate and drain electrodes by the channel length, thereby preventing breakdown between these electrodes. Upon a suitable substrate 10, such as glass, there is deposited a conducting gate electrode layer 12 (about 500 to 1000Å thick), preferably metallic, such as chromium, over which lies a gate dielectric layer 14 (about 100 to 5000Å thick), such as silicon nitride, silicon oxide or other thin film insulating material. Source electrode fingers 16 overlie the gate dielectric layer 14. Each finger comprises an n⁺ doped semiconductor stripe 18 (about 100 to 500Å thick), adjacent layer 14, an overlying source metal stripe 20 (about 1000 to 10,000Å thick), such as a titanium/tungsten alloy, and barrier elements 22, in the form of lightly p-doped (p⁻) semiconductor sidewall members (about 1000 to 5000Å wide). Typically, the fingers would be about 3 to 5µm wide on 3 to 5µm centers, thus posing no problem for standard lithographic patterning. The source fingers may be arranged in an array A which is patterned, as illustrated in Figure 2, so that the semiconductor stripes 18 and metal stripes 20 are in electrically parallel configuration. In a transistor/sensor in accordance with the present invention, however, the source fingers are arranged in two interdigitated arrays, for example as described below with reference to Figure 6. A semiconductor charge transport layer 24 (about 2000 to 40,000Å thick), such as intrinsic or lightly doped amorphous silicon surrounds the source electrode fingers 16 on three sides. A drain electrode layer 26, made of an n⁺ doped semiconductor (about 1000 to 20,000Å thick) in turn overlies the charge transport layer 24, and a transparent, conductive, drain metal layer 28, such as ITO (about 500 to 2000Å thick), or a thin semitransparent metal layer, such as evaporated chromium (about 50 to 100Å thick) overlies the drain electrode layer. Alternatively, the drain metal layer such as would be used in a transistor (e.g. aluminum or chrome/aluminum about 1000 to 10,000Å thick) could be patterned with fine perforations therethrough (e.g. a grid or stripes) between the source fingers for allowing light to pass to the semiconductor charge transport layer. Dimensions set forth are representative of typical ranges which we contemplate or have used in our experimentation and/or modeling, but are not intended to limit the size of these elements in future devices. In operation of the Figure 1 device as a transistor, the source and drain electrodes would have a drive potential maintained therebetween. For example, the source electrode fingers 16 may be at 0 volts and the drain electrode may be at about 10 volts. The gate potential would be switched from a low, OFF state, potential of, for example, -5 to 0 volts, to a high, ON state, potential of, for example, 0 to 10 volts. In the OFF state, the p⁻ sidewalls 22 prevent current leakage by providing effective barriers to the movement of charge carriers from the source electrode semiconductor stripes 18 into the semiconductor charge transport layer 24. A Schottky barrier, between the metal stripes 20 and the semiconductor charge transport layer 24, prevents current flow directly between the metal stripes and the drain electrode 26. When the gate electrode potential is switched to the ON state, channel portions 30 (indicated by hatched lines) through the sidewall barrier elements 22, lying adjacent to the gate dielectric 14, are inverted so that current may flow therethrough. Current flow follows the paths indicated by the arrows, namely, initially laterally from the n⁺ stripes 18 through the channel portions 30 of the sidewall barrier elements 22, and then vertically through the semiconductor charge transport layer 24 to the drain electrode 26. It shouid be noted that when the semiconductor charge transport layer is intrinsic, or lightly doped, amorphous silicon, vertical current flow through charge transport layer 24 is space charge limited. While this form of our device has an excellent ON/OFF ratio, the ON state current will be less than optimum because electrons moving through the p⁻ doped semiconductor, in the channel portions 30, have a lower mobility than in undoped material. In operation of the Figure 1 device as a sensor, both the source and drain electrodes would have applied thereto a drive potential similar to that applied to the transistor, described above. The gate electrode, however, would have a fixed potential applied thereto which would be comparable to the low, OFF state, potential of the transistor, e.g. about -5 volts to 0 volts. In the dark (OFF), current flow is suppressed by the p-type barrier side walls 22 as in the transistor OFF state. When illuminated (ON), as shown in Figure 3, electron-hole (e and h) pairs are generated within the semiconductor layer 24 by the optical energy radiated thereon (indicated by arrows B). The photogenerated electrons move to the drain electrode 26, while the photogenerated holes move through the p⁻ sidewall barrier elements 22 to the n⁺ source electrodes 18 and are trapped therein. When holes move through the p⁻ elements they create a low resistance path therein for electrons to move out of the source electrode. Since the electrons have a longer lifetime than their transit time through the internal drain-source-drain circuit, they will effectively continue to move around this internal circuit many times (as illustrated), giving rise to the high photoconductive gain of the sensor. For example, if each photogenerated electron moves, or causes another electron to move, through the internal circuit 10 times, the gain will be 10. As in the transistor form of this device, the ON state current flow will not be optimum because the electrons moving through the p⁻ doped semiconductor, in the channel portions 30, have a lower mobility than in undoped material . However, it should be understood that this sensor device will have a gain and dynamic range sufficient for may applications. The identical structure may be used for both transistor and sensor devices. By simply providing an opaque mask over those areas of an array containing these devices, the transistors and sensors will be defined. On the other hand, it should be well understood that during fabrication it is possible to deposit an opaque metal layer over the transistors and an ITO layer over the sensors. In Figure 4 there is shown an isolated photogenerated hole centrally positioned between two source electrode fingers 16. If the source electrode fingers are constructed as shown in Figure 2, all of them will be at the same potential and there will be no lateral electric field to drive the hole to either finger. A hole entering this central, low field region will slowly diffuse into a high field region before it is collected, resulting in a relatively slow transient response time as is illustrated by comparing Figures 5a, which shows an optical energy pulse, with Figure 5b, which shows the photogenerated current response. Moreover, by remaining in the material for a sufficiently long time it is likely to be trapped and, as the release time can be quite long, this will further increase the response time. Current continues to flow after the optical energy pulse has terminated on the order of milliseconds, as indicated by the signal tail, caused by the moving holes. Although such a device may have utility in some applications, a transient response time on the order of microseconds would be more desirable. We are able to substantially shorten the transient response time by providing a pair of interdigitated source electrode array structures as shown in Figure 6. Array structure C will have a first potential applied to it and array structure D will have a second potential applied to it, the potential differential being sufficiently small so as not to adversely affect the operation of the device. For example, a potential differential on the order of 1 or 2 volts is believed to be satisfactory. The two source electrode array structures should be nearly at the same voltage but equal to or greater than the voltage on the gate electrode. By decreasing the lateral distance between the source electrode fingers, it is possible to further lower the potential differential. When used in the transistor mode, it would be possible to electrically tie the two array structures together so that they perform exactly as does the Figure 2 source electrode array. In the Figure 1 vertical device structure, described above, the p⁻ doped sidewall barrier elements will reduce the ON current in both the transistor and sensor devices. Blocking configurations which do not significantly reduce the ON current are shown in Figures 7 and 8 in which similar elements have been identified by similar numerals with a prime (′) added. The Figure 7 device further includes a thin semiconductor layer 32 (about 100 to 2000Å thick), such as intrinsic or lightly doped amorphous silicon, overlying the gate dielectric layer 14′, and heavily p-doped (p⁺) sidewall barrier elements 34 are in contact with this layer. The drain field is prevented from reaching the n⁺ source electrodes 18′ and drawing out charge carriers by the proximity blocking effect of the p⁺ barrier elements 34 which pinch off the leakage channel through the thin semiconductor layer 32 due to the spillover of holes into, or depletion of electrons from, the thin semiconductor layer. A p-type proximity barrier region, induced in this layer in the vicinity of the sidewall barrier elements, inhibits electron movement therethrough and suppresses OFF state current leakage in the device. Another factor in suppressing the OFF state leakage current is the field plate effect of the p⁺ barrier elements, maintained at the source electrode potential, which prevent the drain field from reaching the source electrode. When this form of the transistor device is turned ON, by applying a positive potential to the gate electrode 12′, an accumulation channel region 36 (shown by hatch lines) will be formed as the gate field overcomes hole spillover at the silicon/silicon nitride interface, allowing free movement of electrons therethrough. Similarly, when the sensor device is turned ON by subjecting it to illumination, the semiconductor layer 24′ becomes conductive by generating electron/hole pairs. The photogenerated electrons move to the drain electrode 26′, and the photogenerated holes move through the p-type proximity barrier region to the n⁺ source electrodes 18′ and are trapped therein. As holes move through the proximity barrier region they create a low resistance path therein for electrons to move out of the source electrode and through the internal circuit. In Figure 8 there is shown a shield plate or field plate embodiment of the present invention, in which the OFF state leakage current is inhibited without introducing defects into the thin semiconductor layer 32′. Each sidewall barrier element is in the form of a metal cladding layer (such as chromium) having a sidewall 38 and an outboard flange 40. The sidewall 38 blocks charge carrier movement through the sides of the n⁺ source electrode fingers 18″ and the flange defines a blocking tunnel, or gauntlet, 42 in the thin semiconductor layer 32′. Masking members 44, which may be made of silicon nitride or p-type semiconductor, are positioned outboard of the metal cladding layer and serve only to aid in fabrication, by defining the flange length and, thereby, the length of tunnel 42. The desired blocking effect is provided, in the OFF state, by the tunnel, or gauntlet region, in the thin semiconductor layer 32′, lying between the gate electrode layer 12″ (usually maintained at -5 volts to 0 volts) and the metal flange 40 (maintained at source electrode potential, usually 0 volts). The metal flange acts as a field plate by shielding the source from the drain potential. In the ON state of the transistor form of the device, when a switching potential is applied to the gate electrode, the interface region between the thin semiconductor layer 32′ and the gate dielectric layer 14″ is accumulated and a conductive channel 46 is formed, through which charge carriers may move. In the ON state of the sensor form of the device, when the device is illuminated, the charge transport layer 24″ becomes conductive by generating electron/hole pairs. The photogenerated electrons move to the drain electrode 26″, and the photogenerated holes move through the tunnel 42 to the n⁺ source electrodes 18″ and are trapped therein. As holes move through the tunnel they create a low resistance path therein for electrons to move out of the source electrode and through the internal circuit. Charge from the holes also screens this region from the gate potential. In Figure 9 the ON/OFF ratios of a Figure 8 sensor device are illustrated. Characteristic curves of the ON state and OFF state currents are plotted for different gate voltages. We used a monochromatic red LED light source having an intensity of about 10¹⁴ photons/cm²/sec, which is comparable to about 1/1000 AM 1 (average ambient room light). At a gate voltage of about -4 volts the ON/OFF ratio is somewhat greater than three orders of magnitude and the measured optical gain was about 5. An additional blocking layer may be provided, as illustrated in Figure 10, in order to further suppress the sensor dark current. Although this embodiment is shown as a modification of the Figure 7 device, it has applicability in any of the devices described. A lightly doped p-type blocking layer 50 (about 200Å thick) overlies the semiconductor charge transport layer 24′′′ and is shown separated from the n⁺ drain electrode layer 26′′′ by a thin layer 48 of intrinsic or lightly doped semiconductor (about 500Å thick). This blocking layer may, however, be located anywhere within the semiconductor charge transport layer 24‴. While this device construction will improve the optical sensor performance it will slightly impair the transistor performance.

Claims: A thin film transistor/sensor device comprising a substrate (10) upon which is supported a gate electrode (12), a gate dielectric (14) overlying said gate electrode, a source electrode comprising source electrode fingers (16) overlying said gate dielectric, barrier sidewalls (22) on said source electrode fingers for inhibiting a drain field from reaching said source electrode a semiconductor layer (24) covering said gate dielectric and said source electrode fingers including said sidewalls, and a drain electrode (26) on said semiconductor layer, characterized in that the source electrode fingers are arranged in two interdigitated array structures (C,D) and in that the device further comprises an electrically conductive drain contact (28), on said drain electrode, through which optical energy is able to pass to said semiconductor means, so that said device selectively may be operated as a transistor or as a sensor. A device as defined in claim 1, including means for establishing an electric field between the two array structures of source electrode fingers. A device as defined in claim 2, wherein said means for establishing an electric field comprises means for maintaining one array structure at a first potential, and means for maintaining the other array structure at a second potential. A device as defined in claim 1, wherein the two arrays of source electrode fingers are electrically tied together. A device as defined in any one of the preceding claims, wherein said barrier means is located adjacent the side walls of said source electrode means. A device as defined in any one of the preceding claims, wherein said barrier sidewalls are spaced from said gate dielectric by semiconductor layer (32) through which a channel region (36) is defined. A device as defined in claim 6, wherein said barrier sidewalls establishe a proximity barrier to current flow through said channel region in the absence of a gate field, and wherein said proximity barrier is abated in the presence of a gate field. A device as defined in claim 7, wherein said barrier sidewalls depletes majority carriers from said channel region. A device as defined in claim 7, wherein said barrier sidewalls comprise a semiconductor material heavily doped so as to spill charge carriers, of a sign opposite to the sign of the current carrying charge carriers of the transistor, into said channel region. A device as defined in claim 9 wherein said semiconductor layer comprises intrinsic amorphous silicon and said barrier sidewalls comprise heavily p-doped amorphous silicon. A device as defined in any one of claim 1 to 5, wherein said barrier sidewalls comprises a field plate maintained at the same potential as that applied to said source electrode and which, together with said gate electrode, prevents said drain field from reaching said source electrode. A device as defined in anyone of the preceding claims, further comprising a blocking layer (50) for suppressing sensor dark current located within said semiconductor layer adjacent to and parallel with said drain electrode. A device as defined in claim 12, wherein said blocking layer is lightly p doped.

Inventors: HACK MICHAEL, SHAW JOHN GARY, SHUR MICHAEL, HACK, MICHAEL, SHAW, JOHN GARY, SHUR, MICHAEL
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1990
Main classification: H01L31
IPC codes: H01L27, H01L29, H01L31