DRAM cell array layout

Abstract: The semiconductor memory device comprises a plurality of word lines (WL) and a plurality of bit lines (BL) intersected by the plurality of word lines, and a plurality of memory cells located at intersections of the word lines and the bit lines. Each of the memory cells comprises a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of the transfer transistor being connected to a word line, the source of the transfer transistor being connected through a bit line contact (C b ) to a bit line, the drain of the transfer transistor being connected through a storage capacitor contact (C s ) to the storage electrode of the capacitor. A memory cell pair is formed by two nearby memory cells having a common bit line contact, and a unit memory cell array has a configuration in which the word lines are not arranged orthogonally with respect to the bit lines. The direction of the word lines or the bit lines is parallel with one side of a semi-conductor chip on which the semiconductor memory device is arranged. The unit memory cell array is divided by a straight line parallel with one side of the unit memory cell array into portions the number of which is an integer multiple of two, and the divided memory cell array constitutes two identical halves which are mirror images of each other.

Description: The present invention relates to a semiconductor memory device. The semiconductor memory device according to the present invention is applicable to a storage capacitance type dynamic random access memory (dynamic RAM) in which information is stored in a storage capacitor. A memory call of a storage capacitance type dynamic RAM, is constituted by a storage capacitor for storing information and a transfer transistor for reading and writing information. The gate of the transfer transistor is connected to a word line, the source of the transfer transistor is connected to a bit line, and the drain of the transfer transistor is connected to the storage electrode of the storage capacitor. In a memory cell array of the storage capacitance type dynamic RAM, a plurality of bit lines is arranged in a longitudinal direction and a plurality of word lines is arranged in a lateral direction. The two adjacent bit lines connected to the same sense amplifier at one end of each the two bit lines constitute a folded bit line type arrangement. A transfer transistor is connected to a bit line through a bit line contact area. In the spaces defined by a sequence of bit lines and a sequence of word lines, the drain of a transfer transistor is connected to a storage capacitor electrode through a storage capacitor contact area. Between two adjacent word lines, the bit line contact areas are arranged for every other bit line. Between two adjacent word lines, the storage capacitor contact areas are arranged in sequence. Two adjacent memory cells constitute a memory cell pair which has a single common bit line contact area. One side transfer transistor is connected between one side storage capacitor contact area and the bit line contact area, and the other side transfer transistor is connected between the other side storage capacitor contact area and the bit line contact area. In a prior art arrangement of an array of memory cells of a storage capacitance type dynamic RAM, the storage capacitor contact areas are arranged closely in sequence in a lateral direction, but the bit line contact areas are arranged only for every other bit line in a longitudinal direction. Accordingly, the portion where the bit line contact area does not exist constitutes an unused wasteful space. This is not advantageous for realizing a highly integrated storage capacitance type dynamic RAM. EP-A-0 031 490 discloses a semiconductor memory device according to the preamble of accompanying claim 1. In this device, the column arrangement of memory cells is interdigitated, such that the memory cells associated with a given bit line are arranged in two parallel lines along left and right sides of the bit line, which zig-zags alternately between memory cells on the left and right sides. However, the bit lines are arranged in a general direction orthogonal to the word lines; more particularly, three consecutive bit line contacts belonging to a given bit line are arranged along direction orthogonal to a direction defined by the channel regions of transfer transistors along a given word line. IBM Technical Disclosure Bulletin, vol. 24, no. 7B, pages 3815-3816 discloses a design for a semiconductor memory device in which three memory cells are provided per bit line contact. Repeating units of the three memory cells form a T-shaped pattern with the bit line contact made at the centre of the head of the T. This necessitates arranging the bit lines non-orthogonally to the word lines. It is an object of the present invention to provide an improved semiconductor memory device in which the degree of utilization of the space for the arrangement of the bit line contact areas and the storage capacitor contact areas is enhanced, and the amount of unused wasteful space is reduced, so that a high integration of the semiconductor memory device can be realized. According to the present invention, there is provided a semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing electric charge representing information and a transfer transistor for reading electric charge from and writing electric charge into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells having a common bit line contact; at least three consecutive bit line contacts belonging to the same bit line being arranged along a first direction; wherein a second direction from a channel region of a first transfer transistor to the channel region of the nearest transfer transistor belonging to the same word line as the first transfer transistor is not orthogonal to the first direction; the first direction or the second direction is parallel with one side of a semiconductor chip on which the semiconductor memory device is arranged; and a unit memory cell array is a divided memory cell array which is divided by a straight line parallel with one side of the unit memory cell array into portions the number of which is an integer multiple of two, adjacent two portions constituting two identical halves which are mirror images of each other. For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which: Fig.1 shows the arrangement of a storage capacitance and a transfer transistor in relation with a folded type bit line connected to a sense amplifier to which the present invention is to be applied; Fig. 2 shows a prior art memory device with bit line contact areas and storage capacitor contact areas; Fig. 3 shows the pattern of the memory device of Fig. 2; Fig. 4 is a cross-sectional view along line IV-IV of the memory device of Fig. 3; Fig. 5 shows another prior art memory device with bit line contact areas and storage capacitor contact areas; Fig. 6 shows the pattern of the memory device of Fig. 5; Fig. 7 shows still another prior art memory device with bit line contact areas and storage capacitor contact areas; Fig. 8 shows a storage capacitance type dynamic RAM useful for understanding the present invention; Fig. 9 shows the pattern of the memory device of Fig. 8; Fig. 10 is a cross-sectional view along lines X-X of the memory device of Fig. 9; Figs 11 to 14 illustrate the dimensions and spatial arrangement of the bit line contact areas and the storage capacitor contact areas of the memory device of Fig. 8; Fig. 15 and 16 illustrate the dimensions and spatial arrangement of the patterns of the memory device of Fig. 8; Fig. 17 and 18 illustrate the arrangement of memory cell arrays in a semiconductor chip for the memory device of Fig. 8; Fig. 19 shows the arrangement of memory cell arrays in an embodiment of the present invention; Fig. 20 shows the pattern of the memory cell arrays in the embodiment of Fig. 19; Figs. 21A and 21B illustrate the dimensions of the bit line contact area, the storage capacitor contact area, and the bit line in the prior art memory device; Fig. 22 illustrates the dimensions of the bit line contact area, the storage capacitor contact area, and the bit line in a memory device ; and Figs. 23A and 23B illustrate arrangements of the bit line contact area and the storage capacitor contact area. Before describing the preferred embodiment of the present invention, some of the prior art semiconductor memory devices with bit line contact areas and storage capacitor contact areas are described with reference to Figs. 1 to 7. In general, a memory cell array of the storage capacitance type dynamic RAM is constituted by word lines (WL), bit lines (BL, BL ), sense amplifiers (A s ), storage capacitors for storing information, and transfer transistors for reading and writing information from and to the storage capacitors, as shown in Fig. 1. The gate of the transfer transistor is connected to a word line, the source is connected to a bit line, and the drain is connected to a storage electrode of a storage capacitor. In the schematic planar pattern of a prior art memory cell array of the storage capacitance type dynamic RAM shown in Fig. 2, a plurality of bit lines BL (1a), BL (1b), ... are arranged in the longitudinal direction, and a plurality of word lines WL (1), WL (2), ... are arranged in the lateral direction. The adjacent bit lines BL (1a) and BL (1b), BL (2a) and BL (2b), ... are connected to sense amplifiers A s (1), A s (2), ... to form bit line pairs of the folded bit line type. In the spaces defined by the longitudinal bit lines BL (1a), BL (1b), ..., and the lateral word lines WL (1), WL (2), ..., drains of the transfer transistors make contact with electrodes of the storage capacitors to form storage capacitor contact areas C s . On the longitudinal bit lines BL (1a), BL (1b), ..., connections between adjacent transfer transistors make contact with a bit line to form bit line contact areas C b . A sequence of storage capacitor contact areas C s are located in the spaces between word lines WL (1) and WL (2). Bit line contact areas C b are located on every other bit line between word lines WL (2) and WL (3). The two adjacent memory cells which constitute a memory cell pair have in common a bit line contact area C b . A bit line contact area C b is located on the line connecting storage capacitor contact areas C s and C s . The top view of the storage capacitance type dynamic RAM of Fig. 2 is shown in Fig. 3, and the cross-sectional view along line IV - IV of Fig. 3 is shown in Fig. 4. The source region 14 and the drain region 16 of the transfer transistor are formed in the active region 13 along the surface of the semiconductor substrate 10 separated by field oxide coating 12. The word line WL (5) is arranged via gate oxide coating 18 between the source region 14 and the drain region 16. The word line WL (4) is arranged via gate oxide coating 18 between the source region 14 and a drain region which is to be provided to the left. The word line (6) is arranged over the field oxide coating 12. The oxide coating 20 is arranged over the word lines WL (4), WL (5), and WL (6). The bit line BL (1b) contacts the source region 14 through a contact hole formed in the oxide coating 20 to form the bit line contact area C b . The storage capacitor is formed over the bit line BL (1b) via the oxide coating 22. One electrode 24 of the storage capacitor contacts the drain region 16 to form a storage capacitor contact area C s , while the opposite electrode 26 as the other electrode is formed around the electrode 24 via a thin oxide coating 25. The electrode 24 is of a rectangular shape having the storage capacitor contact area C s at the center thereof. Another prior art storage capacitance type dynamic RAM is shown in Figs. 5 and 6. In the device of Figs. 2 and 3, the active region 13 is arranged in the oblique direction with regard to the word line. In the device of Figs. 5 and 6, the active region 13 has a T shape which is parallel with the bit line and the word line, and the transfer transistor in the active region 13 is perpendicular to the word line. Also, another prior art storage capacitance type dynamic RAM is shown in Fig. 7. The bit line contact areas C b and the storage capacitor contact areas C s are arranged along a bit line in a manner overlapping the bit line. The active region 13 corresponding to the bit line contact area and the storage capacitor contact areas is arranged along a bit line in a manner overlapping the bit line. A storage capacitance type dynamic RAM is shown in Figs. 8, 9, and 10. The schematic planar pattern is shown in Fig. 8, the top view of the device in Fig. 9, and the cross-sectional view along line X - X in Fig. 10. In the device of Fig. 8, the first bit line BL (1a) and the third bit line BL (1b) are connected to the sense amplifier A s (1) to constitute a bit line pair, and the second bit line BL (2a) and the fourth bit line BL (2b) are connected to the sense amplifier A s (2) to constitute a bit line pair. Between word lines WL (1) and WL (2), bit line contact area C b on bit line BL (1a), storage capacitor contact area C s between bit lines BL (2a) and BL (1b), storage capacitor contact area C s between bit lines BL (1b) and BL (2b), and bit line contact area C b on bit line BL (3a) are arranged in sequence. Between word lines WL (2) and WL (3), a sequence of bit line contact area C b and storage capacitor contact area C s similar to the case between word lines WL (1) and WL (2), is arranged. In the device of Fig. 8, the bit line contact area between word lines WL (1) and WL (2) on bit line BL (1a) and the bit line contact area between word lines WL (2) and WL (3) on bit line BL (2a) are located on the opposite sides of word line WL (2). Also, each of the memory cell pairs having a common bit line contact area has the same direction, that is the direction from lower left to upper right. In the device of Fig. 8, in a unit region defined by word lines Nos. "i" and "i + 1", for example WL (2) and WL (3), and bit line Nos. "j" and "j + 4", for example BL (1a) and BL (3a), there are provided bit line contact areas and storage capacitor contact areas with a ratio of 1:2 between the number of the bit line contact areas and the storage capacitor contact areas. As shown in Fig. 9 as a top view and in Fig. 10 as a cross-sectional view, the source region 14 and the drain region 16 of a transfer transistor are formed in the active region 13 separated by the field oxide coating 12 along the surface of the semiconductor substrate 10. The word line WL (3) is arranged between the source region 14 and the drain region 16 via the gate oxide coating 18. The word line WL (2) is arranged between the source region 14 and the drain region to be provided to the left thereof via the gate oxide layer 18. The word line WL (4) is arranged over the oxide coating 12. The oxide coating 20 is arranged over the word lines WL (2), WL (3), and WL (4). The bit line BL (2a) contacts the source region 14 through the bit line contact area C b . A storage capacitor is constituted over bit line BL (2a) via oxide coating 22. One electrode 24 as a storage electrode of a storage capacitor contacts the drain region 16 through the storage capacitor contact area C s , while the opposite electrode 26 as the other electrode is formed around the electrode 14 via thin oxide coating 25. In a modified device, the cross-sectional configuration of the electrode 24 of the storage capacitor can be a multiple layer configuration, i.e., a fin-like configuration. An analysis of the arrangement of the storage capacitance type dynamic RAM of Fig. 8 will be described with reference to Figs. 11, 12, 13, and 14 as follows. The X-directional distance x and Y-directional distance y between a bit line contact area C b and a storage capacitor contact area C s are determined in accordance with a first condition that a word line WL passes between the bit line contact area C b and the storage capacitor contact area C s (Fig. 11), and a second condition that the storage capacitor contact area C s is apart from the bit line BL with which the bit line contact area C b is formed (Fig. 12). It is assumed that the radius of the bit line contact area C b is "a", its width allowance is "b", the width of the word line WL is "c", the radius of the storage capacitor contact area is "e", and its width allowance is "d". Then, the distance between the bit line contact area C b and the storage capacitor contact area C s is given from the first condition to be "a + b + c + d + e" (Fig. 11). It is assumed that the width of the bit line BL is "2f". Then, the Y-directional distance y between the bit line contact area C b and the storage capacitor contact area C s is given from the second condition to be "e + d + f". The X-directional distance x' and the Y-directional distance y' between the nearest bit line contact areas are determined in accordance with a third condition that a word line WL passes between the bit line contact areas and a fourth condition that each of the bit line contact areas contacts a different bit line. From the third condition the distance between the bit line contact areas is given to be "a + b + c + b + a" (Fig. 13). It is assumed that the allowance of width of the bit line contact area is "h". Then, the Y-directional distance y' between the bit line contact areas is given from the fourth condition to be "f + g + h + a" (Fig. 13). The X-directional distance x" and the Y-directional distance y" between the nearest storage capacitor contact areas are determined in a similar manner. From the above, the arrangement of the bit line contact areas C b and the storage capacitor contact areas C s is given as shown in Fig. 14. A calculation of the area of the memory cell will be carried out, for example, as follows. It is assumed that the diameter of the contact hole is 0.6 µm, the width of the wiring conductor is 0.5 µm, the allowance of the contact hole and the external wiring conductor is 0.3 µm, the allowance of the contact hole and the wiring conductor contacting the contact hole is 0.2 µm, and the gap between the wiring conductors is 0.5 µm. The dimensions are given as follows, a = e = 0.3 µm b = d = 0.3 µm c = 0.5 µm f = 0.25 µm g = 0.5 µm h = 0.2 µm Then, the calculations are carried out as follows, x = [(a + b + c + d + e) 2 - (e + d + f) 2 ] ½ = [(0.3 + 0.3 + 0.5 + 0.3 + 0.3) 2 - (0.3 + 0.3 + 0.25) 2 ] ½ = 1.472 µm = 1.5 µm y = e + d + f = 0.3 + 0.3 + 0.25 = 0.85 µm x' = [(a + b + c + b + a) 2 - (f + g + h + a) 2 ] ½ = [(0.3 + 0.3 + 0.5 + 0.3 +0.3) 2 - (0.25 + 0.5 + 0.2 + 0.3) 2 ] ½ = 1.152 µm ≒ 1.2 µm y' = f + g + h + a = 0.25 + 0.5 + 0.2 + 0.3 = 1.25 µm An arrangement of the memory cell array based on the values obtained by the above described calculations is shown in Fig. 15. Four memory cell pairs, i.e., eight memory cells, constitute a unit pattern defined by a parallelogram ABCD. In the planar pattern of the device, this unit pattern is repetitively arranged. The configuration of the parallelogram ABCD is illustrated in Fig. 16. The X-directional dimension between apexes A and B is " 2x - 3x' + x" ", and that between apexes A and D is " 2x + x' + x" ". The Y-directional dimension between apexes A and B is " 2y + 3y' + y" ", and that between appexes A and D is " 2y - y' + y" ". Accordingly, the X-directional shift of the laterally running word line WL is " 2x - 3x' + x" ", and the Y-directional shift of the longitudinally running bit line BL is " 2y - y' + y" ". Then, the area of the unit pattern ABCD is calculated as follows. (2x + x' + x")(2y + 3y' + y") - (2x - 3x' + x")(2y - y' + y") Since eight memory cells constitute a unit pattern ABCD, the area S of a memory cell is one eighth of the area of the unit pattern ABCD. For the convenience of calculation, it is assumed that there is no shift of a word line WL. In this case, it is required that 2x - 3x' + x" = 0, and hence the values of x" and y" are as follows. x" = -2x + 3x' = (-2)(1.5) + (3)(1.2) = 0.6 µm y" = [(2e + 2d + c) 2 - (x") 2 ] ½ = 1.59 µm Accordingly, the area of a memory cell is as follows. S = 4.224 µm 2 In order to eliminate a shift of word line WL, it is possible to assume that x = x' = x". In this case, the maximum value between x, x', and x" is used as follows x = x' = x" = 1.5 µm y = y" = 0.85 µm y' = 1.25 µm Accordingly, the area of a memory cell is as follows. S = 4.725 µm 2 In the arrangement of the prior art memory cell, the area of a memory cell is calculated to be 5.1 µm 2 . As a result of the comparison based on the above-described calculation, the area of a memory cell according to the device of Fig. can be more than 10% less than that according to other prior art devices. Possible arrangements of the memory cell array of the device of Fig. 8 in a semiconductor chip (not in accordance with the invention) are shown in Figs. 17 and 18. In the arrangement shown in Fig. 17 where the X-axis and Y-axis of the memory cell array 30 are in parallel with the two sides of the semiconductor chip 32, respectively, unused,spaces 301 and 302 are formed around the memory cell array unit 30, and thus this arrangement is not considered to be advantageous. In another arrangement shown in Fig. 18, the longer side of the parallelogram of the memory cell array unit 30 is set to be parallel with one side of the semiconductor chip 32. The arrangement shown in Fig. 18 is better than that in Fig. 17, since the area of the unused spaces 303 and 304 is less than in the case of Fig. 17. Fig. 19 shows an embodiment of the invention. Here, the memory cell array unit 30 is divided into two parts 30A and 30B by the central division line 31 to constitute a mirror image symmetry of the parts 30A and 30B, and the central division line 31 is made parallel with one side of the semiconductor chip 32. The arrangement shown in Fig. 19 is better than that in Fig. 18, since the area of the unused spaces 305, 306, and 307 is less than in the case of Fig. 18. The details of the arrangement of the memory cell array shown in Fig. 19 in the vicinity of the division line 31 are shown in Fig. 20. In the arrangement shown in Fig. 20, there exists a common memory cell which is to be owned by both the divisional memory cell arrays 30A and 30B. In this case, the word line BL (B1) in the divisional memory cell array 30B is maintained always in an OFF state so that the common memory cell is treated as belonging to the divisional memory cell array 30A. In a modified embodiment, the number of divisions of the memory cell array 30 can be more than two, for example, integer multiples of two. Based on the above described device shown in Fig. 8, and by way of background explanation, the analysis of the increase of degree of integration caused by the reduction of pitch of the sense amplifiers, and the general rule for determining the pattern of the device having the minimum sense amplifier pitch are described as follows with reference to Figs. 21A, 21B, 22, 23A and 23B. First, the increase of degree of integration caused by the reduction of pitch of the sense amplifiers is described with reference to Figs. 21A, 21B, and 22. Figures 21A and 21B correspond to the prior art device, and Fig. 22 corresponds to the device of Fig. 8, L is the width of the bit line BL, S is the gap between the adjacent bit lines, H is the diameter of the contact hole (i.e., the diameter of the contact area) for the bit line contact area or the storage capacitor contact area, M i is the inner allowance of the contact hole, and M 0 is the outer allowance of the contact hole. The pitches P (Fig. 21A ) and P (Fig. 21B) of the sense amplifiers in the cases of Fig. 21A and 21B are calculated as follows, P (Fig. 21A) = 1 2 H + M i + S + L + S + M i + 1 2 H P (Fig. 21B) = 1 2 L + M 0 + H + M 0 + L + M 0 + H + M 0 + 1 2 L If it is assumed that L, S, and H are equally the same as F, and that M i and M 0 are equally the same as M, the calculation is as follows, P (Fig. 21A ) = 4F + 2M P (Fig. 21B ) = 4F + 4M From this calculation, it is acknowledged that the pitch in the case of Fig. 21B is greater by 2M than the pitch in the case of Fig. 21A. Thus, the pattern must be determined not by Fig. 21A but by Fig. 21B, and accordingly the unused wasteful space is caused. In the case of Fig. 22 , the pitch P (Fig. 22) of the sense amplifiers is calculated as follows. P (Fig. 22 ) = 1 2 L + M 0 + H + M 0 + L + S + M i + 1 2 H = 4F + 3M Thus, the pitch in the case of Fig.22 is less by 1M than the pitch in the case of Figs. 21A and 21B. This constitutes the main reason for the increase in degree of integration in the device of Fig. 8. Second, the general rule for determining the pattern of the device having the minimum sense amplifier pitch is described with reference to Figs. 23A and 23B. Figure 23A shows an arrangement according to the general rule, and Fig. 23B shows an imaginary arrangement which is impossible to realize. In the device of Fig . 8, since two storage capacitor contact areas are provided for each bit line contact area, the ratio between the number of the bit line contact areas C b and the number of the storage capacitor contact areas C s in the entire memory cell array is as follows. N(C b ):N(C s ) = 1:2 If there are excessive numbers of bit line contact areas between a first space between two adjacent word lines to give the relationship 2N(C b ) > N(C s ), in the second space between two adjacent word lines next to the first space, the number of storage capacitor contact areas must be excessive to give the relationship 2N(C b ) < N(C s ) to maintain the above-mentioned ratio. If the number of the storage capacitor contact areas becomes excessive, the pitch of the sense amplifiers for such storage capacitor contact areas becomes maximum, and the size of the memory cell array is determined by such maximum pitch of the sense amplifiers so that a reduction in size is prevented. Thus, it is concluded that the pitch of the sense amplifiers becomes minimum in the case where the ratio of N(C b ) and N(C s ) is "1:2" in each of the spaces between two adjacent word lines. The analysis of the repetitive basic unit of the pattern of the arrangement of the bit line contact areas and the storage capacitor contact areas is described as follows. In the minimum basic unit of the pattern of the arrangement of the bit line contact areas and the storage capacitor contact areas which is defined by the pitch of the word lines and the pitch of the sense amplifiers (which is twice the pitch of the bit lines), there is on average one storage capacitor contact area. Also, the ratio between the number of the bit line contact areas and the number of the storage capacitor contact areas is required to be 1:2. Thus, the pitch of the sense amplifiers becomes minimum when the average number of the bit line contact areas is ½ and the number of the storage capacitor contact areas is 1 in each of the minimum basic units. Both the number of the bit line contact areas and the number of the storage capacitor contact areas in the repetitive basic unit should be integers. Hence, the number of the repetitive basic units must be 2n times the number of the minimum basic unit, where n is an integer. Accordingly, a unit defined by one pitch of the word lines WL and the 2n times the pitch of the sense amplifiers A s is the repetitive basic unit. The general rule of the pattern of the device for attaining the minimum pitch of the sense amplifiers is described with reference to Figs. 23A and 23B as follows. Since the pattern of the repetitive basic unit is of the translational symmetry, the pattern of the repetitive basic unit according to the general rule is as shown in Fig. 23A. After the patterns of the bit line contact areas C b and the storage capacitor contact area C s are determined, the location of a bit line contact area on a bit line is determined, and thus the entire arrangement of the device is determined. There are rules for determining the location of the bit line contact area such that: between two adjacent word lines, bit line contact areas should not be located on the same bit line; in the spaces between the sequence of the word line WL, the sequence in the manner that C b on BL (a), C b on BL (b), and C b on BL (a) as imaginarily shown in Fig. 23B is impossible to realize; and the like. In consequence, in the design of the arrangement of the device, after the repetitive basic unit is determined, the locations of the bit line contact areas are determined according to the above-described rules, and after that the locations of the storage capacitor contact areas are determined.

Claims: A semiconductor memory device comprising: a plurality of word lines (WL) and a plurality of bit lines (BL) intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing electric charge representing information and a transfer transistor for reading electric charge from and writing electric charge into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact (Cb) to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact (Cs) to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells having a common bit line contact (Cb); at least three consecutive bit line contacts (Cb) belonging to the same bit line (BL) being arranged along a first direction; said plurality of memory cells, word lines, and bit lines forming at least one unit memory cell array (30); characterized in that : a second direction from a channel region of a first transfer transistor to the channel region of the nearest transfer transistor belonging to the same word line as the first transfer transistor is not orthogonal to the first direction; the first direction or the second direction is parallel with one side of a semiconductor chip (32) on which the semiconductor memory device is arranged; said unit memory cell array (30) is a divided memory cell array which is divided by a straight line (31) parallel with one side of the unit memory cell array into portions the number of which is an integer multiple of two, adjacent two portions being two identical halves (30A, 30B) which are mirror images of each other, such that either the respective first directions, or the respective second directions within adjacent portions of said unit memory cell array are mutually different.

Inventors: EMA TAIJI, HASHIMOTO KOICHI, EMA, TAIJI, HASHIMOTO, KOICHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01L27
IPC codes: H01L27