Bipolar transistor and method of manufacturing the same

Abstract: In a semiconductor device including a bipolar transistor having a base region (4) formed in a collector region (3), and an emitter region (5) formed in the base region (4), the emitter region (5) comprises a high concentration region (5a) in contact with the base region (4), and a low concentration region (5b) provided between the base region (4) and the high concentration region (5a). The low concentration region (5b) is formed by introducing an impurity with a mask including a large opening. In addition, the high concentration region (5a) is formed by introducing an impurity with a mask including a small opening.

Description: FIELD OF THE INVENTION This invention relates to a semiconductor device including a bipolar transistor and a method of manufacturing the same. BACKGROUND OF THE INVENTION FIGS. 9A and 9B are a plan view and a cross sectional view of an NPN type bipolar transistor (Bi-Tr) as a portion of a conventional semiconductor device, e.g., Bi-CMOS, respectively. This Bi-Tr is manufactured as follows. Namely, an N + type buried layer 2 is formed on a P-type Si substrate 1 and an N-type collector region 3 is grown thereon. A P-type impurity (B or BF 2 , etc.) is ion-implanted into a region where the base is to be formed of the collector region 3. Thereafter, using a resist mark, an N-type impurity (e.g., As) is ion-implanted only into a region where the emitter is to be formed in the region where the base is to be formed. Heat treatment is then conducted. As a result, a P-type base region 4 is formed within the N-type collector region 3, and an N-type emitter region 5 is formed within the P-type base region 4. Thus, Bi-Tr is provided. There are instances where a reverse bias may be applied to the junction portion between the emitter region 5 and the base region 4 of the Bi-Tr. Application of such a reverse bias leads to the difficulty that the emitter-base junction breakdown voltage is lowered and the current gain h FE is also lowered, resulting in considerably deteriorated device characteristics. A known device is shown in EP-A-0 241 699. It includes an emitter region with a high concentration region and a low concentration region. The high concentration region is surrounded by the low concentration region, but penetrates through the low concentration region to contact a base region. SUMMARY OF THE INVENTION This invention has been made in view of the above, and its object is to provide a semiconductor device constructed so that the device characteristic is not lowered even when a reverse bias is applied to the junction portion between the emitter region and the base region, and a method of manufacturing such a semiconductor device. According to a first aspect of the present invention, there is provided a semiconductor device as set out in claim 1. Since such a structure is employed, an electric field at the edge portion of the emitter region is relaxed. Thus, even when a reverse bias is applied to the base-emitter junction portion, there is no possibility that the junction breakdown voltage and the current gain are lowered. A further aspect of the present invention is set out in claim 6. In accordance with this invention, even when a reverse bias is applied to the portion across the emitter region and the base region of the bipolar transistor, lowering of the device characteristic can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIGS. 1A and 1B are a plan view and a cross sectional view of an embodiment according to this invention, respectively; FIG. 1C is a cross sectional view of other embodiment according to this invention; FIG. 2 and FIGS. 3A to 3D are cross sectional views showing an example of manufacturing process steps; FIGS. 4A to 4D, FIG. 5, FIGS 6A to 6E, and FIGS. 7A to 7C, show different examples of manufacturing process steps, respectively without showing all the steps of the invention; FIGS 8A to 8E show the method of the present invention; and FIGS. 9A and 9B are a plan view and a cross sectional view of a background art. FIG. 10 shows the emitter-base junction initial characteristics of the semiconductor devices according to the present invention and the background art. FIG. 11A shows changes of the emitter-base junction characteristics of the semiconductor devices according to the present invention and the background art after putting the devices into reverse bias stress conditions. FIG. 11B shows changes of the current gain characteristics of the semiconductor devices according to the present invention and the background art after putting them into reverse bias stress conditions. DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A and 1B are a plan view and a cross sectional view of an NPN type Bi-Tr of a semiconductor device according to this invention, respectively. In this Bi-Tr, an N-type collector region 3 is formed on the side of the surface of an N + buried layer 2 formed on a P-type semiconductor substrate 1. A P-type base region 4 is formed on the side of the surface of the collector region 3. Furthermore, an N-type emitter region 5 is formed on the side of the surface of the base region 4. This emitter region 5 is composed of two sections. One is a high concentration region (N + )5a having a small lateral cross section and a deep depth, and the other is a low concentration region (N - )5b having a large lateral cross section and a shallow depth. In the Bi-Tr of such a structure, an N-type impurity diffused region (5b) having a low concentration is formed at the edge portion of a so-called conventional emitter region (5a) formed by N-type impurity having a high concentration. Thus, an electric field at the edge portion is relaxed. Even when a reverse bias is applied to the junction portion between the base and the emitter, the junction breakdown voltage and the current gain are not lowered. Thus, a high reliability device is provided. The semiconductor device shown in FIGS. 1A and 1B can be manufactured as follows. Namely, as shown in FIG. 2, e.g., Sb is ion-implanted into a P-type Si substrate 1 (e.g., 2Ω·cm) under the condition of 100 KeV, 1 x 10 15 cm -2 . A thermal process step under the condition of 1100°C, 60 minutes is implemented. An N + buried layer 2 is thus formed. Thereafter, the surface of the Si substrate 1 is epitaxially grown in the atmosphere including SiH 2 Cl 2 . An N-type collector region 3 is thus formed. Then, device isolation regions 7, 7 are formed by LOCOS process. Thereafter, a silicon oxide film 8 having a thickness of approximately several ten to several hundred Å is formed by an argon diluted oxidation process. Thereafter, a P-type impurity (e.g., boron or BF 2 ) 6 is ion-implanted into a region where the base is to be formed under the condition of 25 KeV, 5 x 10 13 cm -2 . Subsequently, process steps shown in FIGS. 3A to 3D are implemented in succession. These figures show only the surface portion of the substrate shown in FIG. 2. As seen from FIG. 3A, a silicon oxide film 9 is deposited on the oxide film 8 in a manner in close contact therewith by a CVD process so that its thickness is equal to, e.g., 100nm (1000 Å). Then, a resist (not shown) is coated on the silicon oxide film 9 in a manner in close contact therewith. By removing the portion of the resist, above a region where the emitter is to be formed, an opening is provided. Using this resist as a mask, by CDE (Chemical Dry Etching), openings 9a, 8a are provided in the silicon oxide films 9, 8, respectively. Then, that resist is exfoliated. Thus, the state shown in FIG. 3A results. Thereafter, using the silicon oxide films 9, 8 as a mask, an N-type impurity (e.g., As) 11 is densely ion-implanted through the openings 9a, 8a under the condition of 40 KeV, 5 × 10 15 cm -2 so as to result in the state of high concentration. Then, as seen from FIG. 3B, the openings 9a, 8a of the silicon oxide films 9, 8 are widened, e.g., by 1000 Å by wet etching process. Thus, larger openings 9b, 8b are newly provided. Then, as seen from FIG. 3C, an N-type impurity (e.g., P) 12 is sparsely ion-implanted under the condition of 20 KeV, 3 × 10 13 cm -2 so as to result in the state of low concentration. Subsequently, as seen from FIG. 3D, a thermal diffusion process, e.g., a process having a temperature of 900°C and N 2 annealing time of 60 minutes is implemented. Thus, an emitter region 5 including an N-type high concentration region 5a and an N-type low concentration region 5b is formed within the P-type base region 4. At times subsequent thereto, in the same manner as in widely used semiconductor devices, metallization process and passivation process are implemented in succession. Thus, a semiconductor device is provided. A semiconductor device according to this invention may be manufactured by various methods described below in addition to the above-described method. Namely, a first modification will be first described. After undergoing the process shown in FIG. 2, as seen from FIG. 4A, a resist film 21 is coated on the upper surface of the oxide film 8 in a manner in close contact therewith. The portion, above the region where the emitter is to be formed, of the resist film 21 is removed. An opening 21a is thus provided. Then, an N-type (e.g., As) is densely ion-implanted under the condition of 40 KeV, 5 × 10 15 cm -2 so as to result in a state of high concentration. Then, as seen from FIG. 4B, the resist film 21 is etched by a wet etching process to further widen the opening 21a by 100nm (1000 Å) to newly form a larger opening 21b. Then, as seen from FIG. 4C, an N-type impurity (e.g., P) 12 is sparsely ion-implanted under the condition of 20 KeV, 3 × 10 13 cm -2 so as to result in the state of low concentration. Subsequently, as seen from FIG. 4D, the entirety of the resist film 21 is exfoliated. A thermal process similar to the thermal process in FIG. 3D is implemented. Thus, an N-type emitter region 5 including a high concentration region 5a and a low concentration region 5b is formed within the P-type base region 4. Thereafter, a metallization process and a passivation process are implemented. Thus, a semiconductor device is provided. A second modified example will now be described. After the process step in FIG. 2 and the process in FIG. 4A, the entirety of the resist film 21 is exfoliated. Then, as shown in FIG. 5, a resist film 24 is coated on the oxide film 8. An opening 24a having substantially the same dimension as that of the opening 21b shown in FIG. 4B is provided in the resist film 24. Thereaftrer, an N-type impurity (e.g., P) 12 is sparsely ion-implanted under the condition of 20 KeV, 3 × 10 13 cm -2 so as to result in a state of low concentration. At times subsequent thereto, a semiconductor device is provided by executing the same process as that in FIG. 4D, the metallization process and the passivation process. A third modified embodiment will now be described. After the process step in FIG. 2, as seen from FIG. 6A, large openings 8b, 9b are provided in the oxide films 8, 9, respectively, and an N-type impurity 12 is introduced sparsely through these openings 8b, 9b so as to result in a state of low concentration. Thereafter, as seen from FIG. 6B, a polycrystalline silicon oxide film 27 is deposited on the oxide films 8, 9 in a manner in close contact therewith so that its thickness is equal to, e.g., 100nm (1000 Å). Then, as seen from FIG. 6C, a polycrystalline silicon oxide film 27a is left only within the openings 8b, 9b by anisotropic etching to form an opening 27b. Thereby, an opening 27b is formed. Then, as seen from FIG. 6D, using the polycrystalline silicon oxide film 27a as a mask, an N-type impurity (e.g., P) 11 is densely ion-implanted under the condition of 40 KeV, 5 × 10 15 cm -2 so as to result in the state of high concentration. Then, as seen from FIG. 6E, the remaining polycrystalline silicon oxide film 27a is removed by a dry etching process. Subsequently, process steps similar to those shown in FIG. 3D, i.e., the thermal process step, the metallization process step, and the passivation process step will be carried out. In the abovementioned third modified embodiment, a SiO 2 film can be used instead of the polycrystalline silicon film 27. In this case, it is free that the remaining SiO 2 film in the openings 8b, 9b may be either removed or left as it is. A fourth modified example will now be described. After the process step shown in FIG. 2, as seen from FIG. 7A, a resist film 29 is coated on the oxide film 8 in a manner in close contact therewith. Only the portion, above the region where the emitter is to be formed, of the resist film 29 is removed to provide a large opening 29a. Thereafter, an N-type impurity (e.g., P) 12 is sparsely ion-implanted through the opening 29a under the condition of 20 KeV, 3 × 10 13 cm -2 so as to result in a state of low concentration. Then, as seen from FIG. 7B, after the entirety of the resist film 29 is exfoliated, a resist film 30 is coated. The portion, above the region where the high concentration region is to be formed, of the resist film 30 is removed to provide a small opening 30a. Thereafter, an N-type impurity (e.g., As) 11 is densely ion-implanted under the condition of 40 KeV, 5 × 10 15 cm -2 so as to result in a state of high concentration. Then, as seen from FIG. 7C, the entirety of the resist film 30 is exfoliated. Thereafter, the thermal process, the metallization process and the passivation process are implemented. Finally, the method according to the present invention will be described. After the process step shown in FIG. 2, as seen from FIG. 8A, a silicon oxide film 32 is deposited on the oxide film 8 in a manner in close contact therewith by a CVD process so that its thickness is equal to, e.g., 100nm (1000 Å). A resist (not shown) is coated on the oxide film 32 in a manner in close contact therewith. Thereafter, only the portion, above the region where the emitter is to be formed, of the resist is removed to provide an opening. Then, using this opening as a mask, large openings 32a, 8a are provided in the silicon oxide film 32, 8 by CDE process, respectively. Thereafter, an N-type impurity (e.g., P) 12 is sparsely ion-implanted through these openings 32a, 8a under the condition of 20 KeV, 3 × 10 13 cm -2 so as to result in a state of low concentration. Then, as seen from FIG. 8B, after the oxide films 32, 8 are removed by wet etching process, another oxide film 34 is deposited by a CVD process so that its thickness is equal to 300 nm (3000 Å). Thereafter, a second resist film 35 is coated on the oxide film 34. An exposure process is implemented thereto to form an opening 35a. Then, as seen from FIG. 8C, an opening 34a is provided in the oxide film 34 by CDE process. Thereafter, the entirety of the resist 35 is exfoliated. Then, as seen from FIG. 8D, a polycrystalline silicon film 37 including an N-type impurity (e.g., P) is deposited on the silicon oxide film 34 in a manner in contact therewith so that its thickness is equal to, e.g., 100nm (2000 Å). Then, as seen from FIG. 8E, the heat treatment process, the metallization process and the passivation process are implemented. In the above-mentioned heat treatment process, the N-type impurity in the polycrystalline silicon film 37 is diffused. A high concentration region 5a is thus formed. As a mask in ion-implanting the N-type impurity, a nitride film may be used instead of the above-mentioned silicon oxide film and resist film. As the N-type impurity, Sb may be used instead of the above-mentioned P and As. While a Bi-Tr including NPN transistor has been described above, Bi-Tr including PNP transistor may be obtained in the same manner as stated above by allowing the conductivity to be opposite to the above. Another embodiment of the present invention is shown in FIG. 1C. FIGS. 10 to 11b show the advantageous effects of the present invention. Especially, it will be understood from FIG. 11A that the emitter-base junction characteristics of the semiconductor device according to the present invention does not practically change even if the device is put into reverse bias stress conditions (V EBO = 5V, 1000 sec), while the characteristics of the device according to the background art change widely. Furthermore, it will be understood from FIG. 11b that the current gain characteristics of the device according to the present invention changes only slightly if the device is put into the aforementioned conditions, while the characteristics of the device according to the background art changes greatly. Reference signs in the claims are intended for better understanding and shall not limit the claims.

Claims: A semiconductor device including a semiconductor substrate (1), and a bipolar transistor formed in said semiconductor substrate, said bipolar transistor comprising: a collector region (3) comprising a first conductivity type impurity; a base region (4) comprising a second conductivity type impurity and formed in the vicinity of the surface of said collector region, and an emitter region (5) comprising said first conductivity type impurity and formed in the vicinity of the surface of said base region, said emitter region comprising a high concentration region (5a) having a high impurity concentration and a low concentration region (5b) having an impurity concentration considerably lower than that of said high concentration region, said high and low concentration regions being in columnar form, said columnar low concentration region having a lateral cross-section considerably larger than that of said high concentration region and a depth considerably smaller than that of said high concentration region, said high and low concentration regions being superimposed so that said low concentration region comprises a central columnar portion superimposed on a surface portion of said high concentration region and a peripheral annular portion surrounding said central columnar portion and said surface portion of said high concentration region, whereby said emitter region essentially comprises high concentration impurities, the volume of said low concentration region being smaller than that of said high concentration impurity region. A device as set forth in claim 1, wherein said high concentration region is formed as a quadrangular column, and said low concentration region is formed as a quadrangular frame. A device as set forth in claim 1 or 2, wherein said semiconductor substrate is a substrate comprised of said second conductivity type impurity, and said collector region is a well region formed in said substrate. A device as set forth in one of claims 1-3, wherein said first conductivity type impurity is an N-type impurity, and said second conductivity type impurity is a P-type impurity. A device as set forth in one of claims 1-4, wherein said first conductivity type impurity is a P-type impurity, and said second conductivity type impurity is an N-type impurity. A method of manufacturing a semiconductor device as set out in claims 1 - 5, having at least one bipolar transistor constructed by forming a second-conductivity type impurity base region on a surface of a first-conductivity type impurity collector region; and forming a bipolar transistor by forming a first-conductivity impurity emitter region on a surface of the base region, characterised by the following steps of: forming a first mask layer (32,8) formed with a first aperture (32a,8a) in the surface of the base region; ion-implanting first-conductivity type impurities (12) into the base region through the first aperture to form a low concentration region (5b) of the emitter; forming a second mask layer (35) formed with a second aperture (35a) smaller than the first aperture on the surface of the low concentration region (5b) of the emitter; depositing a diffusing film (35A) containing first-conductivity type impurities in the second aperture formed on the surface of the base region; and diffusing by heat treatment the first-conductivity impurities from the diffusing film (35A) into the base region to form a high concentration region (5a) of the emitter. The method of manufacturing a semiconductor device of claim 6, wherein the first mask layer (32,8) formed on a semiconductor substrate (1) is a first oxide film, the first aperture (32a, 8a) being formed by etching the first oxide film. The method of manufacturing a semiconductor device of claim 6 or 7, wherein the second mask layer (34) is a second oxide film, the second aperture (35a) being formed by etching the second oxide film with a resist as a mask. The method of manufacturing a semiconductor device of claim 6, 7 or 8, wherein the diffusion layer (35A) is a polycrystal silicon film formed by deposition. A method as set forth in claim 6 which further comprises a step of introducing a first conductivity type impurity into a semiconductor substrate (1) comprised of a second conductivity type impurity thereafter to apply heat treatment thereto to form a first conductivity type buried layer (2) to form, by epitaxial growth, said collector region (3) of said first conductivity type on the surface of said buried layer (2). A method as set forth in claim 6, wherein said heat treatment process is implemented in a manner that heating is applied for 60 minutes in an atmosphere of N 2 at a temperature of 900°C. A method as set forth in claim 6, wherein said process of introducing the impurity for forming said base region (4) is ion-implantation under the condition of 25 KeV, 5 x 10 13 cm -2 , and wherein said process of introducing the impurity (12) for forming said low concentration emitter region (5b) is an ion-implantation under the condition of 20 KeV, 3 x 10 13 cm- 2 . A method as set forth in claim 6, wherein said first opening (32a) is formed, using a resist (35) as a mask, by etching said first silicon oxide film (32) deposited by CVD process on an oxide film (8) forme on said base region (4) so that its thickness is equal to 100nm (1000 Å), and wherein said second opening (34a) is formed by removing said first silicon oxide film (32), thereafter to deposit another oxide film (34) with a thickness of 300nm (3000 Å) on said base region (4) by CVD process thereafter to etch said another oxide film (34) using said resist (35) as a mask.

Inventors: MOMOSE HISAYO, MOMOSE, HISAYO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L29
IPC codes: H01L21, H01L29