Matrix circuit of FM stereo multiplex demodulation circuit

Abstract: A matrix circuit includes a first resistor (R A ) having one end connected to receive a current signal and another end connected to a first output node (51), a second resistor (R B ) having one end connected to the one end of said first resistor (R A ), a first bipolar tran­ sistor (Q3) having a first collector connected to the another end of said second resistor (R B ), a first emit­ ter connected to a circuit ground (GND) and a first base connected to said first collector, and a second bipolar transistor (Q4) having a second collector connected to a second output node (52), a second emitter connected to said circuit ground (GND) and a second base connected to said first base.

Description: This invention relates to an input (matrix) circuit of an FM stereo multiplex demodulation circuit which is formed in an integrated circuit configuration and is used in a device capable of receiving FM stereo broadcast, and more particularly to a circuit for shunting a demodulated composite signal current in the preset ratio. An input (matrix) circuit of an FM stereo multiplex demodulation circuit to which this invention is not applied is constructed as shown in Fig. 5. The block diagram thereof is shown in Fig. 7. That is, in the input (matrix circuit of Fig. 5, Q51 and Q52 denote NPN transistors whose emitters are connected together via respective matrix resistors R₁ and the connection node therebetween is connected to a ground terminal via a matrix resistor R₂. The bases of the NPN transistors Q51 and Q52 are connected to an input node 50 and a bias voltage (V₁) source, respectively. When an FM-demodulated composite signal voltage Δvi is input to the input signal node 50, the input signal Δvi is divided into shunt currents Δi₁ and Δi₂ which flow as collector currents of the NPN transistors Q51 and Q52 in the preset ratio. A similar circuit to that shown in figure 5 is known from US-A-3947645. In Fig. 7, 11 denotes a buffer circuit, 12 a V/I converter, 13 a tone controller, 14 an I/V converter, 15 a matrix (input) circuit, and 16 a switching decoder. Shunt currents i₁ and i₂ output from the input (matrix) circuit are supplied to a switching decoder SD, switching-controlled by complementary switching pulse signals of 38 KHz and output as a left-channel signal Lout and a right-channel signal Rout. In the above operation, the input signal Δvi, shunt currents Δi₁ and Δi₂, matrix resistances R₁ and R₂ have the following relations: Δi 1 = Δvi R 1 1 + R 2 R 1 + R 2 Δi 2 = Δvi R 1 1 + R 1 + R 2 R 2 Δi 2 Δi 1 = R 2 R 1 + R 2 In order to set the separation between the left-channel signal Lout and the right-channel signal Rout to a maximum value, the resistances R₁ and R₂ are determined to satisfy the following expression: R 2 R 1 + R 2 = π - 2 π + 2 As shown in Fig. 7, since the input (matrix) circuit to which this invention is not applied receives a voltage signal Δvi as an input, an FM-demodulated composite signal cannot be directly input in a case where the FM-demodulated composite signal is a current output, and in this case, the FM-demodulated composite signal can be input only after the composite signal is converted into a voltage signal Δvi by means of a current-voltage (I/V) converting circuit (14 in Fig. 7). As described above, the input (matrix) circuit to which this invention is not applied cannot directly receive an FM-demodulated composite signal as an input in a case where the FM-demodulated composite signal is a current output, and can receive the same only after it is converted into a voltage signal Δvi by use of the I/V converting circuit. Therefore, it tends to be restricted by the internal dynamic range, the operation efficiency of the power source is lowered and the number of elements used becomes larger. An object of this invention is to provide an input (matrix) circuit of an FM-stereo multiplex demodulation circuit in which an FM-demodulated composite signal can be supplied to a switching decoder by shunting an input current corresponding to the FM-demodulated composite signal in a preset ratio even when the FM-demodulated composite signal is a current output and input in the form of current. The object of the invention is solved by an input circuit for a multiplex demodulation circuit which derives first and second signals from a composite input current signal, the input circuit including: a first resistor; a second resistor; and wherein the composite input current signal is applied to said input circuit; characterized by : said first resistor being connected to a first output node of said input circuit; a current mirror circuit; including a plurality of bipolar transistors being connected to said second resistor and to a second output node of said input circuit; said first and second resistors shunting the composite input current signal to the first and second output nodes, respectively, in a preset current ratio dependent upon the ratio of the resistances of the first and second resistors; and a first bipolar transistor connected with its emitter to said first resistor, and connected with its collector to said first output node. The first and second shunting means can include one of a plurality of bipolar transistors of the NPN or PNP type. With the above construction, the other end of each of the resistors (R A ) and R B ) as viewed from a current signal supplied from a tone controller is a low impedance. Therefore, an input current is divided into shunt currents Δi A and Δi B depending on the resistance ratio of the first resistor (R A ) and the second resistor (R B ). At this time, the shunt current Δi B flowing in the second resistor (R B ) is derived with a phase opposite to that of the collector current Δi A of the first bipolar transistor (Q1). Therefore, it becomes possible to derive shunt currents with opposite phases from the input (matrix) circuit and to supply the same to the switching decoder. As a result, it becomes possible to supply the current signal from the tone controller directly to the input (matrix) circuit without passing the same through the I/V converter. Thus, there can be provided an input (matrix) circuit of an FM stereo multiplex demodulation circuit which can supply an FM-demodulated composite signal to the switching decoder by shunting the input current with a preset ratio even if the FM-demodulated composite signal is a current output and is input as it is. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing one embodiment of a matrix circuit of an FM stereo multiplex demodulation circuit according to this invention; Figs. 2, 3 and 4 are circuit diagrams showing other embodiments of this invention; Fig. 5 is a circuit diagram showing an FM stereo multiplex circuit to which this invention is not applied; Fig. 6 is a circuit diagram showing an embodiment of a switching decoder; Fig. 7 is a block diagram showing a multiplex stereo demodulation section to which this invention is not applied; Fig. 8 is a block diagram showing an embodiment of this invention; and Fig. 9 is a circuit diagram showing an embodiment of this invention having a plurality of switching decoders. There will now be described an embodiment of this invention in detail with reference to the accompanying drawings. Fig. 1 shows a matrix circuit of an FM stereo multiplex demodulation circuit formed in an IC. 1 denotes a current source supplying an FM-demodulated composite signal current output, and the emitter of an NPN transistor Q1 is connected to the output terminal of the current source 1 via a first matrix resistor R A . Further, the emitter of a PNP transistor Q2 is connected to the output terminal of the current source 1 via a second matrix resistor R B . The collector-emitter path of an NPN transistor Q3 whose base and collector are connected together is connected between the collector of the PNP transistor Q2 and a ground potential terminal. The base of the NPN transistor Q3 is connected to the base of an NPN transistor Q4 which has an emitter connected to the ground potential terminal. The NPN transistors Q3 and Q4 are combined to constitute a current mirror circuit CM1. The base of the NPN transistor Q1 is applied with a bias power source voltage V₂ and the base of the PNP transistor Q2 is applied with a bias power source voltage V₃ (< V₂). The collector currents of the NPN transistors Q1 and Q4 are supplied to a switching decoder SD. In the above matrix circuit, the other end of each of the matrix resistors R A and R B as viewed from the current source 1 is a low impedance, and an input current Δiin from the current source 1 is divided by the matrix resistors R A and R B in the ratio only depending on the resistance ratio of the matrix resistors R A and R B . The shunt current Δi A flowing in the matrix resistor R A is derived out via the NPN transistor Q1, and the shunt current Δi B flowing in the matrix resistor R B is derived out with a phase opposite to that of the collector current of the NPN transistor Q4 via the PNP transistor Q2 and the current mirror circuit CM1. In this way, the shunt currents Δi A and Δi B with opposite phases output from the matrix circuit are supplied to the switching decoder SD and switching-controlled by complementary switching pulse signals, thereby causing a left-channel signal Lout and a right-channel signal Rout to be derived out. In this case, the resistances of the matrix resistors R A and R B are so determined that the separation between the left-channel signal Lout and the right-channel signal Rout can be set to the largest value. Next, the operation of the above matrix circuit is explained. The emitters of the NPN transistor Q1 and PNP transistor Q2 are low impedance and variation in the emitter resistances re of the respective transistors is neglected for simplifying the explanation, then the following equations can be obtained: Δi A - Δi B - Δi IN = 0 R A · Δi A + R B · Δi B = 0 The following equation can be obtained by substituting the equation (3) into the equation (2) to eliminate Δi B : Δi A = Δi IN · R B R A + R B Then, Δi B = Δi IN · R A R A + R B and therefore the following equation can be obtained: Δi B /Δi A = - R A /R B In this way, the ratio of the output currents Δi A and Δi B is determined by the ratio of R A and R B and currents with opposite phases can be derived. The currents are supplied to the switching decoder SD and switching-controlled by complementary switching pulse signals, thus deriving a left-channel signal Lout and a right-channel signal Rout. In this case, the condition for setting the separation between the left-channel signal Lout and the right-channel signal Rout to maximum is expressed as follows: R A /R B = (π-2)/(π+2) According to the above-described matrix circuit, an FM-demodulated composite signal output current can be directly input, and the input current can be shunt in the ratio only depending on the resistance ratio of the matrix resistors and then supplied to the switching decoder. In a case where a filtering process or tone control operation is required to reduce stereo noise in the matrix circuit of the FM stereo multiplex demodulation circuit when an weak input is supplied, two processing circuits may be necessary and the number of elements used increases if the above process is effected after the separation between the left-channel signal Lout and the right-channel signal Rout is effected. Therefore, increase in the number of elements used can be reduced if the above process is effected at a stage before the switching decoder and the matrix circuit. In this case, if the filtering process or the like is effected with the current mode kept unchanged, it is less restricted by the internal dynamic range and the operation efficiency of the power source can be raised. At this time, since the output attained in the filtering process or the like is set in the current mode, it is preferable to directly input the current to the matrix circuit as in this invention. Figs. 2 to 4 show other embodiments of the matrix circuit of this invention. That is, the matrix circuit of Fig. 2 is similar to the matrix circuit of Fig. 1 except that the PNP transistor Q2 is omitted. Parts used in Fig. 2 and corresponding to those used in Fig. 1 are denoted by the same reference numerals. The matrix circuit of Fig. 3 is similar to the matrix circuit of Fig. 1 except that the PNP transistor Q2 is omitted, and resistors R B , R B-2 are respectively connected to the emitters of NPN transistors Q3 and Q4 of the current mirror circuit CM1. Parts used in Fig. 3 and corresponding to those used in Fig. 1 are denoted by the same reference numerals. Also, in the matrix circuits of Figs. 2 and 3, the other end of each of the matrix resistors R A and R B , R B-2 as viewed from the current source 1 is a low impedance. Therefore, in the matrix circuits of Figs. 2 and 3, the same effect as in the matrix circuit of Fig. 1 can be obtained. The matrix circuit of Fig. 4 is similar to the matrix circuit of Fig. 1 except the following three points: (1) a resistor R₃ is connected to the collector of the NPN transistor Q1, the emitter-base path of a PNP transistor Q5 is connected across the resistor R₃, and the collector of the PNP transistor Q5 is connected to the emitter of the NPN transistor Q1; (2) the other end of the matrix resistor R B is connected to the ground potential terminal and the PNP transistor Q2 and the current mirror circuit CM1 are omitted; and (3) a current mirror circuit CM2 formed of an NPN transistor Q6 whose collector and base are connected together and an NPN transistor Q7, constant current sources I respectively connected to the collectors of the NPN transistors Q6 and Q7, a resistor R B-2 connected between the emitter of the NPN transistor Q6 and the ground potential terminal, and an NPN transistor Q8 whose base-emitter path is connected between the collector of the NPN transistor Q7 and the emitter of the NPN transistor Q6 are further provided and one of the shunt currents, that is, the shunt current Δi B is output from the collector of the NPN transistor Q8. Other portions used in Fig. 4 and corresponding to those used in Fig. 1 are denoted by the same reference numerals. In the matrix circuit of Fig. 4, since a negative feedback operation is effected with respect to the emitter of the NPN transistor Q1 by means of the resistor R₃ and the PNP transistor Q5, the impedance of the other end of the resistor R A is further lowered, and the other end of the resistor R B is grounded so that the impedance thereof is further lowered. As a result, the precision of the current shunting or dividing ratio is further enhanced, and a non-linear element caused by the emitter resistor re is removed from the shunting path, thereby suppressing occurrence of distortion. That is, since only constant currents may flow in the NPN transistors Q6 and Q7 of the current mirror circuit CM2, a voltage occurring in the emitter of the NPN transistor Q7 (or a voltage drop of Δi B ΔR B caused by the shunt current Δi B ) is projected onto the emitter of the NPN transistor Q6 and a current expressed by the following equation is output via the NPN transistor Q8: Δi B · R B R B-2 = Δi B R B = R B-2 Further, a negative feedback operation is effected with respect to the emitter of the NPN transistor Q1 by means of the resistor R₃ and the PNP transistor Q5, and the impedance of the emitter of the NPN transistor Q1 becomes extremely low. As a result, the shunt path from the emitter of the NPN transistor Q1 to the ground potential terminal includes only resistors R A and R B and does not include a non-linear element. Further, only constant currents are permitted to flow in the NPN transistors Q6 and Q7 of the current mirror circuit CM2, no shunting current flows therethrough, and no non-linear element is included in the signal transmission path so that occurrence of distortion can be suppressed to a minimum. Fig. 6 is a circuit diagram showing one embodiment of a switching decoder. In Fig. 6, a circuit formed of bipolar transistors Q₆₁, Q₆₂, Q₆₃ and Q₆₄ is shown as an example of the switching decoder. In this case, Q₆₁ is a bipolar transistor having a collector connected to a left-output terminal Lout, and a base supplied with a switching signal of 38 KHz and an emitter connected to first input terminal 51. Q₆₂ is a bipolar transistor having a collector connected to a right-output terminal Rout, a base supplied with a switching signal of 38 KHz and an emitter connected to a first input terminal 51. Q₆₃ is a bipolar transistor having a collector connected to the left-output terminal Lout, a base connected to the base of the bipolar transistor Q₆₂ and an emitter connected to a second input terminal 52. Q₆₄ is a bipolar transistor having a collector connected to the right-output terminal Rout and the collector of the bipolar transistor Q₆₂, a base connected to the base of the bipolar transistor Q₆₁ and an emitter connected to the second input terminal 52. Since a circuit described below has substantially the same construction as the circuit of Fig. 3, portions shown in Fig. 6 and corresponding to those in Fig. 3 are denoted by the same reference numerals and the explanation thereof is omitted. Fig. 8 is a block diagram showing an embodiment of this invention. In Fig. 8, 11 denotes a buffer circuit, 12 a V/I converter, 13 a tone controller, 15-2 a matrix circuit of this invention, and 16 a switching decoder. With this construction, the L OUTPUT and R OUTPUT can be derived without using the I/V converter 14 shown in the blockdiagram of Fig. 7 to which this invention is not applied. Further, Fig. 9 is a circuit diagram showing still another embodiment according to this invention and having a plurality of switching decoders. SD1 and SD2 denote switching decoders, Q1, Q5, Q6, Q7, Q8, Q9, Q10 and Q11 bipolar transistors, R A , R B , R B-2 , R C , R D , R E , R3 and R4 resistors, I₁ and I₂ constant current sources, and 1 a signal current source. The circuit with the above construction includes a plurality of switching decoders supplied with switching signals of odd-multiple frequency ratio so as to constitute an anti-birdy system. Therefore, with this circuit, odd higher harmonic noise of the switching signal can be reduced. As described above, according to the matrix circuit of the FM stereo multiplex demodulation circuit of this invention, the FM-demodulated composite signal current output can be directly input with the current mode kept unchanged, and the input current is shunted in the ratio depending only on the resistance ratio of the matrix resistors and can be supplied to the switching decoder. Therefore, it becomes unnecessary to convert the FM-demodulated composite signal current output into a voltage signal by means of the I/V converter, and the matrix circuit may be less influenced by the limitation of the internal dynamic range in comparison with the matrix circuit to which this invention is not applied, the operation efficiency of the power source can be enhanced and the number of elements used can be reduced. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: An input circuit for a multiplex demodulation circuit which derives first and second signals (L out , R out ) from a composite input current signal (Δi in ), the input circuit including: a first resistor (RA); a second resistor (RB); and wherein the composite input current signal (Δi in ) is applied to said input circuit; said first resistor (RA) being connected to a first output node (51) of said input circuit; a current mirror circuit (CM₁; CM₂) including a plurality of bipolar transistors (Q3, Q4; Q6, Q7) being connected to said second resistor (RB) and to a second output node (52) of said input circuit; said first and second resistors (RA, RB) shunting the composite input current signal (Δi in ) to the first and second output nodes, respectively, in a preset current ratio dependent upon the ratio of the resistances of the first and second resistors (RA, RB); and a first bipolar transistor (Q1) connected with its emitter to said first resistor (R A ), and connected with its collector to said first output node (51). An input circuit according to claim 1, having a second bipolar transistor (Q2) between said second resistor (R B ) and said current mirror circuit (CM₁). An input circuit according to claim 1, having a third bipolar transistor (Q5) connected to said first resistor (R A ), and a third resistor (R₃) connected to said third bipolar transistor (Q5). An input circuit according to claim 1, wherein said current mirror circuit (CM₁) is connected to a fourth resistor (R B-2 ) connected to ground potential (GND). An input circuit according to claim 1, having constant current sources (I₁, I₂) respectively connected to collectors of said bipolar transistors (Q6, Q7) of said current mirror circuit (CM₂) and a fourth bipolar transistor (Q8) connected with its base to that bipolar transistor (Q7) of said current mirror circuit (CM₂) which is connected with said second resistor (R B ), said fourth bipolar transistor being connected with its collector to said second output node (52). An input circuit according to any of the preceding claims, having switching decoder means (SD) connected between first and second output nodes (51, 52), for decoding a signal from said first and second output nodes (51, 52). An input circuit according to claim 6, wherein said switching decoder means (SD) includes: a fifth bipolar transistor (Q₆₁) having a collector connected to a left signal output (L out ), a base connected to a first signal input (SI₁) and an emitter connected to said first output node (51); a sixth bipolar transistor (Q₆₂) having a collector connected to a right signal output (R out ), a base connected to a second signal input (SI₂) and an emitter connected to the emitter of said fifth bipolar transistor (Q₆₁); a seventh bipolar transistor (Q₆₃) having a collector connected to said left signal output (L out ), a base connected to the base of said sixth bipolar transistor (Q₆₂) and an emitter connected to said second output node (52); and an eighth bipolar transistor (Q₆₄) having a collector connected to the collector of said sixth bipolar transistor (Q₆₂), a base connected to said first signal input (SI₁) and an emitter connected to the emitter of said seventh bipolar transistor (Q₆₃). An input input circuit according to claim 5, having a plurality of switching decoder means (SD1, SD2) supplied with switching signals of odd-multiple frequency ratio.

Inventors: ITOH MASASHI C O INTELLECTUAL, ITOH, MASASHI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H04B1
IPC codes: H04B1, H04S1, H04H40, H04H1