Method and apparatus for detecting alignment mark of semiconductor device

Abstract: In a semiconductor device having a leveling metal layer (3, 15) for forming a flat surface on an alignment mark (M2) of a level-difference, charged particles (EB) are irradiated and scanned onto a region of the alignment mark (M2), and information generated from the region of the alignment mark (M2) in accordance with a thickness of a metal in the level-difference of the alignment mark is detected. Therefore, even when the alignment mark formed by the level-difference in the semiconductor device is buried under the leveling metal layer (3, 15), the alignment mark (M2) can be detected exactly without adding excessive processes.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for detecting an alignment mark of a semiconductor device having a leveling metal layer for forming a flat surface on said alignment mark of a level-difference. 2. Description of the Related Art Such a method and apparatus for detecting an alignment mark of a semiconductor device is known from US-A-4,008,402. With this known method and apparatus an electron beam is irradiated onto marks and x-rays are generated therefrom and then the x-rays are detected by corresponding detectors. These detectors are provided each in a fixed position adjacent to one or more marks. Recently, in the art of producing semiconductor devices using an electron beam exposure system, hyper-fine patterns will be required in accordance with an improvement of a large scale integration in the semiconductor device. Therefore, the patterns should be exactly formed on a semiconductor wafer and a correction process (alignment process) becomes important. Namely, in the electron beam exposure system, in order to irradiate an electron beam and form patterns on the semiconductor wafer exactly, a coordinate of a control unit of the electron beam exposure system should be made to agree with a practical position on the semiconductor wafer by using the alignment mark. Note, this alignment process is also used for compensating a distortion of a deflection unit in the electron beam exposure system, so that the electron beam is exactly irradiated on the semiconductor wafer and specific patterns are exactly formed thereon. In a conventional alignment process used in an electron beam exposure system for forming specific patterns by an electron beam, an alignment mark is formed on a semiconductor wafer (substrate), and an alignment process is carried out by detecting positional information of the alignment mark. Namely, the alignment mark is generally formed on the substrate as a level-difference (irregularity) using an RIE method and the like, and then an insulation layer and the like is formed on the substrate. Note, the alignment mark is also formed on the insulation layer as a level-difference. In both cases, the alignment process is carried out by the steps of: scanning an electron beam to cross over the level-differences of the alignment mark, determining a center position of the alignment mark by detecting reflected electrons (secondary electrons) from the level-differences, calculating a correction coefficient by detecting a difference of the center position of the alignment mark, and carrying out an alignment, for example, compensating a distortion of a deflection unit in the electron beam exposure system (with reference to Japanese Unexamined Patent Publication No. 54-81782). However, in a manufacturing process of a semiconductor device, a new layer is formed as a flat surface to increase the reliability of the semiconductor device and make a formation process of the next layer easy. Namely, when a metal layer is formed as a flat surface on the insulation layer having an alignment mark formed by a level-difference, the level-difference alignment mark is buried under the metal layer (leveling metal layer), and thus a detection process of detecting the level-difference alignment mark cannot be carried out. In this case, according to the prior art, an area of the alignment mark or close to the level-difference is gouged out for detection. In this manner, there is a problem that a process for gouging out the level-difference alignment mark must be carried out. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and an apparatus for detecting an alignment mark which can be realized without application of exzessive processes so that a manufacturing time of the semiconductor device can be shortened. For solving this object, the present invention provides a method of detecting an alignment mark of a semiconductor device which is characterized by the features of the characterizing part of claim 1. Furthermore the present invention also provides an apparatus for detecting an alignment mark of a semiconductor device having a leveling metal layer for forming a flat surface on said alignment mark of a lever-difference. The above-mentioned object is also solved by the features of the characterizing part of claim 4. Improved embodiments of features of the inventive method and also of the inventive apparatus result from the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: Figure 1 is a cross sectional diagram for explaining a level-difference alignment mark; Figure 2 is a cross sectional diagram for explaining a flat surface alignment mark; Figure 3 is a diagram for explaining a basic configuration of the present invention; Figure 4 is a cross sectional diagram indicating a general semiconductor device having a leveling metal layer; Figure 5 is a diagram indicating a wafer having a plurality of alignment marks; Figures 6A and 6B are diagrams indicating an alignment mark shown in Fig. 5; Figure 7 is a block diagram indicating an electron exposure system applying the present invention; Figure 8 is a block diagram indicating a first example of an apparatus for detecting an alignment mark of a semiconductor device according to the present invention; Figure 9 is a block diagram indicating a second example of the apparatus according to the present invention; Figures 10 and 11 are diagrams indicating examples of arrangements of detectors shown in Figs. 8 and 9; and Figures 12 and 13 are diagrams indicating configurations of the detectors shown in Figs. 8 and 9. DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an alignment mark of a semiconductor device will be explained, with reference to Figs. 1 and 2. Figure 1 is a cross sectional diagram for explaining a level-difference alignment mark. As shown in Fig. 1, a level-difference alignment mark (M1), which is an alignment mark indicating a level-difference, is generally formed on a semiconductor wafer or a substrate 1 as a level-difference (irregularity) using an RIE method and the like. In Fig. 1, an insulation layer 12 is formed on the substrate 1, and the level-difference alignment mark is formed on the insulation layer 12. Note, a width W 1 of the level-difference alignment mark of the substrate 1 is different from a width W 2 of the level-difference alignment mark of the insulation layer 2, but the center positions of these alignment marks are the same. In both cases, the alignment process is carried out by the steps of, scanning an electron beam to cross over the level-differences of the alignment mark, determining a center position of the alignment mark by detecting reflected electrons (secondary electrons) from the level-differences, calculating a correction coefficient by detecting a difference of the center position of the alignment mark, and carrying out an alignment of the electron beam exposure system. The alignment of the electron beam exposure system is, for example, to make a coordinate of a control unit of the electron beam exposure system with a practical position on the substrate 1 or the insulation layer 2, or to compensate a distortion of a deflection unit in the electron beam exposure system. Figure 2 is a cross sectional diagram for explaining a flat surface alignment mark. As shown in Fig. 2, a flat surface alignment mark (M2), which is an alignment mark having a flat surface, is formed as a results of a new metal layer 3 being formed on the level-difference alignment mark as a flat surface for increasing a reliability of the semiconductor device and for making a formation process of the next layer easy. Namely, the flat surface alignment mark is formed by a metal 3a in the irregularity (level-difference) of the level-difference alignment mark and a surface thereof is flattened. This flat surface alignment mark cannot be detected by using reflected electrons the same as detecting the level-difference alignment mark, as the level-difference is buried under the metal layer 3. In this case, according to the prior art, an area of the alignment mark or close to the level-difference is gouged out for detection. In this manner, there is a problem that a process for gouging out the alignment mark of the level-difference must be added. However, according to the present invention, this flat surface alignment mark can be detected exactly without adding extraneous processes. Furthermore, according to the present invention, the level-difference alignment mark can be also detected by the same method as the above description with reference to Fig. 1. Next, a principle of the present invention will be explained. Figure 3 is a diagram for explaining a basic configuration of the present invention. As shown in Fig. 3, in a semiconductor device having a leveling metal layer 3, charged particles, for example, an electron beam EB, is scanned at a flat surface alignment mark (M2), and information, for example, an X-ray generated from the region of the flat surface alignment mark in accordance with a thickness of a metal layer in the level-difference (irregurality) of the alignment mark, is detected so that a position of the alignment mark can be detected. Note, in this detection method, when scanning the electron beam EB at a region of the alignment mark, electrons reflected by the surface of the metal layer are also generated accompanying the generated X-ray. Therefore, a detector 4 may be constituted by an intercept (includes absorption) means for intercepting (or absorbing) the reflected electrons and PIN-diodes for detecting the X-ray passing through the electron intercept means, and the flat surface alignment mark can be efficiently detected, which will be explained in detail with reference to Figs. 12 and 13. In the above descriptions, when irradiating an electron beam EB on a metal layer, for example, an aluminium layer, the electron beam EB can get into the aluminium layer to a depth of about 2 or 3 µ m, this depth being varied by an accelerating voltage of the electron and a material of the metal layer. Note, the intensity of an X-ray generated from the metal (aluminium) layer is determined by the thickness of the metal layer where the electrons are passing. Namely, when the thickness of the metal layer is two times, an intensity of the generated X-ray (K alpha-ray) becomes two times, as the number of electrons colliding with metal atoms is increased by two times. However, in plactice, when the thickness of the metal layer is two times, the intensity of the generated X-ray is smaller than two times, as some of the X-rays generated by the collision of electrons and metal atoms are absorbed by the metal layer. In the present invention, the X-ray generated from the metal layer or a thickness of a metal in a level-difference of an alignment mark (a metal thickness of a flat surface alignment mark), which has an intensity in accordance with the thickness of the metal layer, is used for detecting the alignment mark, when the level-difference is buried under the metal layer or detecting the flat surface alignment mark. Note, the irradiation processes of the electron beam EB and the detection processes of the alignment mark are carried out several times in order to obtain high accuracy without introducing a detection noise. Furthermore, the scanning processes of the electron beam EB and detection processes of the alignment mark are not only carried out in an X-direction, but also in a Y-direction. Figure 4 is a cross sectional diagram indicating a general semiconductor device having a leveling metal layer. In Fig. 4, a reference numeral 11 denotes a silicon substrate of a single crystal having an alignment mark (level-different alignment mark) M1 formed using an RIE method. Next, an insulation layer (for example, an SiO 2 layer) 12 is formed on the substrate 11 by thermal oxidation, and then a wiring layer (for example, a polysilicon layer) 13 is formed on the insulation layer 12. Furthermore, an insulation layer (for example, a SiO 2 layer) 14 is formed on the wiring layer 13 using a CVD (Chemical Vapor Deposition) method, and then a leveling metal layer 15 is formed on the insulation layer 14 using a spattering method. Therefore, the upper part of contact portions and an alignment mark become flattened. Note, a reference numeral 16 denotes a resist. In Fig. 4, the alignment marks (M1, M2) can be detected by detecting the reflected electrons in the electron beam exposure system before forming a leveling metal layer 15. However, as the alignment mark cannot be detected by detecting the reflected electrons after forming the leveling metal layer 15, in such a case, the alignment mark (flat surface alignment mark) M2 is detected by detecting the generated X-ray. Figure 5 is a diagram indicating a wafer having a plurality of alignment marks. As shown in Fig. 5, a plurality of chips 18 are formed on a semiconductor wafer 17, and alignment marks 19 (M1, M2) are formed at all corners of the chips 18. Namely, one of the four alignment marks 19 is provided at each of the four corners of each of the chips 18. Figures 6A and 6B are diagrams indicating an alignment mark shown in Fig. 5. A shape of the alignment mark 19 is, for example, formed as a square of several tens of µ m as shown in Fig. 6A, and a depth of the alignment mark 19 is, for example, about several µ m. Note, the level-difference alignment mark M1 shown in Fig. 1 is obtained when no material layer is formed on the alignment mark 19, and the flat surface alignment mark shown in Fig. 2 is obtained when a leveling metal layer 3 is formed on the alignment mark 19. Below, the preferred embodiments of an apparatus for detecting an alignment mark of a semiconductor device according to the present invention will be explained. Figure 7 is a block diagram indicating an electron exposure system applying the present invention. As shown in Fig. 7, in a body tube 20, a semiconductor wafer 17 is moved in accordance with a movement of a stage 26 which is controlled by a CPU 8 through a stage control unit 25. A present position of the stage 26 is measured and compared with a reference position 26a by a position measurement unit 24, and an output of the position measurement unit 24 is supplied to a pattern correction circuit 22. The electron beam EB is irradiated and scanned onto the alignment mark (flat surface alignment mark M2). Note, the flat surface alignment mark is defined by a different thickness of the leveling metal layer 15 in the alignment mark 19 having a level-difference. An X-ray, which is generated from a region of the flat surface alignment mark in accordance with a metal thickness of the flat surface alignment mark, is detected by a detector 4. An output of the detector 4 is supplied to a detection circuit 6 through an amplifier 5, and an output of the detection circuit 6 is processed and supplied to the pattern correction circuit 22 through a pattern generator 29. The direction of electron beam EB irradiation or an electron beam pattern is corrected by the pattern correction circuit 22 through a deflection control unit 30 and a deflector 23 in accordance with data from the position measurement unit 24 and the detection circuit 6, and specific patterns are exposed on the semiconductor wafer 17 by the electron beam EB by using the pattern generator 29, a blanking amplifier 31, the deflector 23, and the like. Note, a shot counter 27 is used to count the output of the blanking amplifier 31, a control circuit 28 is used to control function interruption patterns, and a control circuit 21 is used to control defective recognition pattens. Figure 8 is a block diagram indicating a first example of an apparatus for detecting an alignment mark of a semiconductor device according to the present invention. As shown in Fig. 8, this embodiment comprises detectors 4, an amplifier 5, a detection unit 6, a control unit 7, and a CPU 8. In Fig. 8, a leveling metal layer 15 is formed on the alignment mark 19 of a level-difference, and an electron beam EB is irradiated and scanned onto a region of the alignment mark 19, or a flat surface alignment mark. The detector 4, which is provided over the semiconductor wafer (semiconductor device) 7, is used to detect information generated from the region of the alignment mark. If the alignment mark of the semiconductor device is a flat surface alignment mark as shown in Fig. 2, the detected information is an X-ray whose intensity is determined in accordance with a thickness of a metal 15 in the level-difference of the alignment mark, so that a position of the flat surface alignment mark can be detected. In Fig. 8, when scanning and exposing an electron beam, a detector 4 only detects an existing X-ray and reflected electrons which are generated by the leveling metal layer 15. An output of the detector 4 is amplified by an amplifier 5, and is filtered by a detection circuit 6 and supplied to a control system 7. In the control system 7, the alignment mark is exactly detected by an intensity of the X-ray corresponding to thickness-differences of the leveling metal layer 15. Further, a CPU 8 control carrys out various controls in accordance with the detection of the alignment mark. Note, the control unit 7 corresponds to the stage control unit 25 and the deflection control unit 30 in Fig. 7. Figure 9 is a block diagram indicating a second example of the apparatus according to the present invention. As shown in Fig. 9, this embodiment comprises an X-ray detection means and a reflected electron detection means. Namely, this embodiment comprises an X-ray detector 4a, an amplifier 5a, an X-ray detection unit 6a, a reflected electron detector 4b, an amplifier 5b, a reflected electron detection unit 6b, a switching means SW, a control unit 7, and a CPU 8. In this embodiment, an electron beam EB is irradiated and scanned onto a region of the alignment mark 19, or a flat surface alignment mark, an X-ray generated by a flat surface alignment mark only is detected by the X-ray detector 4a, and electrons reflected by the level-difference alignment mark only are detected by the reflected electron detector 4b. The X-ray detector 4a, which is provided over the semiconductor wafer 7, is used to only detect an X-ray generated from the region of the flat surface alignment mark. The reflected electron detector 4b, which is provided over the semiconductor wafer 7, is used to only detect electrons reflected by a surface of the level-difference alignment mark. If the alignment mark of the semiconductor device is a flat surface alignment mark as shown in Fig. 2, an intensity of the detected X-ray is determined in accordance with a thickness of a metal 15 in the level-difference of the alignment mark, so that a position of the flat surface alignment mark can be detected. If the alignment mark of the semiconductor device is a level-difference alignment mark shown in Fig. 1, an intensity of the detected electron is determined in accordance with a surface shape of the level-difference of the alignment mark, so that a position of the level-difference alignment mark can be detected. The switching means SW, which is connected to the X-ray detection unit 6a and the reflected electron detection unit 6b, is used to switch in accordance with the type of the alignment mark. Namely, when the alignment mark is determined to be a flat surface alignment mark, the output of the X-ray detection unit 6a is supplied to the control unit 7 through the switching means SW. Conversely, when the alignment mark is determined to be a level-difference alignment mark, the output of the reflected electron detection unit 6b is supplied to the control unit 7 through the switching means SW. The control unit 7, which is connected to the switching means SW, is used to detect a position of the flat surface alignment mark or the level-difference alignment mark by the detected X-ray intensity or the detected electron intensity. The CPU 8, which is connected to the control unit 7, is used to carry out various controls in accordance with the detected position of the flat surface alignment mark or the level-difference alignment mark. Note, the control unit 7 corresponds to the stage control unit 25 and the deflection control unit 30 in Fig. 7. Figures 10 and 11 are diagrams indicating examples of arrangements of detectors shown in Fig. 9. As shown in Fig. 10, the X-ray detector 4a and the reflected electron detector 4b are provided as four units, respectively. Note, the number of the X-ray detectors 4a and the reflected electron detectors 4b are not limited to four, but can be increased in number. Furthermore, the number of the X-ray detectors 4a can be greater than the number of the reflected electron detectors 4b, as the sensitivity of the X-ray detector 4a is lower than that of the reflected electron detector 4b. As shown in Fig. 11, the X-ray detector 4a can be made larger than the reflected electron detector 4b, as the sensitivity of the X-ray detector 4a is lower than that of the reflected electron detector 4b. Figures 12 and 13 are diagrams indicating configurations of the detectors shown in Fig. 9. As shown in Fig. 12, the detector 4 comprises an electron intercept portion 60 and PIN-diodes 61, 62, 63, and 64. The electron intercept portion 60, which is provided at the side of the semiconductor wafer in the detector 4, is used to intercept electrons reflected by a surface of the semiconductor wafer or the level-difference alignment mark. The PIN-diodes, which are contacted to the electron intercept portion 60 and constituted by a substrate 61, a P-layer 62, an I-layer 63, and an N-layer 64, are used to detect an X-ray passing through the electron intercept portion 60. Note, the electron intercept portion 60 is constituted by two electrode panels to which can be applied a high voltage (for example, -10K Volts), and when the high voltage is applied between the two electrode panels, the reflected electrons are intercepted. Namely, the electrons reflected by the surface of the semiconductor wafer are intercepted when the high voltage is applied to the electron intercept portion 60, and the electrons reflected by the surface of the semiconductor wafer are passed through when the high voltage is not applied to the electron intercept portion 60. In this case, the detector 4 is also used to detect the electrons reflected by the semiconductor wafer in accordance with a surface shape thereof. Furthermore, in the embodiment shown in Fig. 9, the X-ray detector 4a is constructed to apply the high voltage to the electron intercept portion 60, and the reflected electron detector 4b is constructed not to apply the high voltage to the electron intercept portion 60. As shown in Fig. 13, the detector 4 comprises an electron intercept portion 65 and PIN-diodes 61, 62, 63, and 64. The electron intercept portion 65, which is provided at the side of the semiconductor wafer in the detector 4, is used to intercept electrons reflected by a surface of the semiconductor wafer or the level-difference alignment mark. The PIN-diodes have the same configuration as the above PIN-diodes 61, 62, 63, and 64. Note, the electron intercept portion 65 is constituted by a light metal layer, for example, a berylium layer. In this case, a thickness of the berylium layer 65 is about 10 µ m. This berylium layer 65 has a function of intercepting electrons at its surface. Consequently, the detector in Fig. 13 functions only as an X-ray detector. Note, this detector shown in Fig. 13 can be used as the X-ray detector 4a in the embodiment shown in Fig. 9. In accordance with the present invention as described above, even when an alignment mark formed by a level-difference of a semiconductor device is buried under a leveling metal layer, an alignment mark formed by the thickness of the leveling metal layer corresponding to the level-difference can be detected, that is a level-difference alignment mark and a flat surface alignment mark can be detected without adding excessive processes, and thus a manufacturing time of the semiconductor device can be shortened by usign the level-difference alignment mark and the flat surface alignment mark.

Claims: A method of detecting an alignment mark of a semiconductor device having a leveling metal layer for forming a flat surface on said alignment mark of a level-difference, characterized in that said method comprises the steps of: irradiating and scanning charged particles onto a region of said alignment mark; and detecting by a detector means not being fixed in relation to the position of the alignment mark, information generated from the region of said alignment mark in accordance with a thickness of a metal in said level difference in said alignment mark, so that a position of said alignment mark is detected. A method of detecting an alignment mark of a semiconductor device as claimed in claim 1, wherein said charged particles are constituted by an electron beam, and said information generated from the region of said alignment mark is an X-ray intensity. A method of detecting an alignment mark of a semiconductor device as claimed in claim 1 or 2, wherein said method comprise a step of defining a flat surface alignment mark by a different thickness of said leveling metal layer in said level-difference alignment mark. An apparatus for detecting an alignment mark of a semiconductor device having a leveling metal layer for forming a flat surface on said alignment mark of a level-difference, characterized in that said apparatus comprises: a means (20) for irradiating and scanning charged particles onto a region of said alignment mark (M1,M2) and a detection means (4), provided over said semiconductor device (11), for detecting information generated from the region of said alignment mark (M1, M2) in accordance with a thickness of a metal in said level-difference of said alignment mark, so that a position of said alignment mark is detected. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 4, wherein said charged particles are constituted by an electron beam, and said information generated from the region of said alignment mark (M1, M2) is an X-ray intensity. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 4 or 5, wherein said detection means (4) comprises: an electron intercept means (60, 65), provided at the side of said semiconductor device in said detection means (4), for intercepting electrons reflected by a surface of said semiconductor device; and PIN-diodes (61 to 64), contacted to said electron intercept means (60, 65), for detecting an X-ray passing through said electron intercept means (60, 65). An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 6, wherein said electron intercept means comprises a voltage applying means (60), so that the electrons reflected by said semiconductor device are intercepted when said voltage applying means (60) is switched ON, and the electrons reflected by said semiconductor device are passed through when said voltage applying means (60) is switched OFF, and said detection means (4) is also used for detecting the electrons reflected by said semiconductor device in accordance with a surface shape thereof. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 6 or 7, wherein said electron intercept means comprises a light metal layer (64). An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 8, wherein said light metal layer (64) is a berylium layer. An apparatus for detecting an alignment mark of a semiconductor device as claimed in any of claims 4 to 9, wherein said apparatus is used for an electron beam exposure system. An apparatus for detecting an alignment mark of a semiconductor device according to one of the claims 4 to 10 wherein said semiconductor device has a flat surface alignment mark and a level-difference alignment mark and comprises: a means (20) for irradiating and scanning an electron beam onto a region of said level-difference alignment mark and said surface alignment mark; a first detection means (4a), provided over said semiconductor device, for detecting an X-ray generated from the region of said flat surface alignment mark in accordance with a metal thickness in said flat surface alignment mark; a second detection means (4b), provided over said semiconductor device, for detecting an electron reflected from the region of said level-difference alignment mark in accordance with a surface shape of said level-difference alignment mark; and a switching means (SW), connected to said first detection means (4a) and said second detection means (4b), for switching said first detection means (4a) and said second detection means (4b) in accordance with the type of said flat surface alignment mark and said level-difference alignment mark. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 11, wherein said apparatus further comprises: a control unit (7), connected to said switching means (SW), for detecting a position of said flat surface alignment mark or said level-difference alignment mark by said detected X-ray intensity or said detected electron intensity; and a CPU (8), connected to said control unit (7), for carrying out various controls in accordance with the detected position of said flat surface alignment mark or said level-difference alignment mark. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 11, wherein said first detection means (4a) and said second detection means (4b) are provided in plural. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 11, wherein said first detection means (4a) are formed larger than said second detection means (4b). An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 11, wherein said first detection means (4a) comprises: an electron intercept means (60, 65) for intercepting electrons reflected by a surface of said semiconductor device; and PIN-diodes (61 to 64) for detecting an X-ray passing through said electron intercept means. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 15, wherein said electron intercept means comprises a voltage applying means (60). An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 15, wherein said electron intercept means comprises a light metal layer (65). An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 17, wherein said light metal layer (65) is a berylium layer. An apparatus for detecting an alignment mark of a semiconductor device as claimed in claim 11, wherein said apparatus is used in an electron beam exposure system.

Inventors: TAKAHASHI YASUSHI, YASUDA HIROSHI, TAKAHASHI, YASUSHI, YASUDA, HIROSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01J37
IPC codes: H01J37, H01L21