Memory devices

Abstract: A semiconductor memory device includes bit lines (12, 13) and common data lines (14, 15) for writing data to or reading of data from plural memory cells (11). The bit lines (12, 13) and common data lines (14, 15) are provided with equalising circuits (21, 23) and/or precharging circuits (22, 24) which operate during address transition. Transition from writing to read-out is detected and used to actuate the equalising and/or precharging circuits more promptly than usual during such a transition in order to shorten the write recovery time to realise high speed operation. An output circuit (5) of the semiconductor memory device is provided with a precharging circuit (53, 54; 73, 74) for sensing and precharging the level on an output terminal (55; 75) to an intermediate level, thereby allowing a reduction in power consumption and ensuring a high speed outputting operation.

Description: This invention relates to memory devices. In general, in a static random access memory (SRAM), which is a type of semiconductor memory device, a signal potential difference is produced across a pair of bit lines or a pair of common data lines in order to effect data readout or data writing. For high speed readout or writing operations, it is necessary to change the logic level quickly. Thus, a known technique provides for shorting a pair of bit lines or a pair of common data lines, across which the signal potential difference is produced, for equalising the logic level for the next data. When bit lines having a logic level opposite to that of a memory cell of the SRAM are connected to the cell at the time of row selection, the data on the cell occasionally may be reversed. Thus, there is also known a precharging technique of transiently raising the bit line voltage towards the source voltage prior to row selection (word line selection) of the bit lines. Such equalising or precharging is usually performed at the time of the writing or reading and before row selection. The timing is produced by an address transition detection circuit (ATD) operative to generate pulses upon address changes. For example, according to Japanese Patent Application Publication no. JP-A-57 74 884 or US Patent No. US-A-4 355 377, pulses are generated in the address transition detection circuit in response to address changes and are transmitted to a clock generator. The signals for controlling the equalising or precharging are outputted from the clock generator to actuate the equalising or precharging circuits provided on the bit line pairs to shorten the access time. However, in general, during transition from the write operation to the readout operation, the bit lines or the common data lines are substantially in what is referred to as a fully swung state. For this reason, such an amount of time is needed for equalising or precharging that, when the speed is to be increased, it becomes difficult to terminate the equalising or precharging operation before word line selection. If pulses are produced more promptly from the address transition detection circuit, the equalising or precharging operation can be terminated more promptly. However, as shown diagrammatically in Figure 1 of the accompanying drawings, the address transition detection (ATD) circuit 101 collects the data at address inputs 100a to 100g, detects address data transitions and transmits a signal ATD comprising pulses to a clock generator (CG) 102. The address inputs 100a to 100g are widely distributed on a chip 103, so that it is extremely difficult to detect a data transition of each address at high speed. The greater the number of addresses, the larger is the scale of the address transition detection circuit 101 and the longer is the time involved until pulse generation. The above-described problem arises during transition from writing to readout of the SRAM data. US Patent US-A-4 712 194 discloses a memory device comprising: a plurality of memory cells arranged in a matrix configuration and composed of flip-flop circuits for data storage; a plurality of pairs of bit lines, each coupled to a column of the memory cells, for handling complementary read-out data or write data; a plurality of word lines, one for each row of the memory cells, for selecting rows of the memory cells; a sense amplifier connectable to a pair of bit lines for amplifying the voltage across the pair of bit lines; bit line equalising means (referred to as "first precharging means") operative transiently prior to memory cell selection by a word line to equalise a pair of the bit lines by setting the lines to the same potential; equalising control means for setting the operating time interval for the bit line equalising means; first signal generating means responsive to an address signal supplied for selection of the word lines and the bit lines to generate a signal for actuating the equalising control means; bit line precharging means (referred to as "second precharging means") operative transiently prior to memory cell selection by a word line to precharge a pair of the bit lines by connecting the lines to a potential source; precharging control means for setting the operating time interval of the bit line precharging means; and second signal generating means operative to detect a transition from writing to read-out and to actuate the precharing control means at the time said transition is detected. Thus, while US-A-4 712 194 contemplates precharging of the bit lines on transition from writing to read-out, like the above-cited prior art it equalises the bit lines in response to the address signals. In US-A-4 355 377 (cited above), both precharging and equalising (referred to as "equilibrating") of the bit lines is carried out in response to transitions in the address signals. US-A-4 355 377 also discloses the possibility of equilibrating data line pairs connected to respective bit line pairs. Respective different aspects of the invention are set out in claims 1 and 3, the first or pre-characterising parts of both of which are based upon US-A-4 712 194. According to an aspect of the invention there is provided a memory device which includes a signal generator operative to detect a transition from writing to readout (for example a pulse generator operative to produce a pulse on detection of such a transition), the common data lines being equalised and/or precharged when such a transition is detected (for example when a pulse is produced). A write enable signal may be used as a signal enabling detection of a transition from writing to readout. Thus, a high-speed common data line equalising and/or precharging operation can be performed at the time of transition from a writing operation to a read-out operation. According to an embodiment of the invention, a pulse signal from the above-mentioned pulse generator is transmitted to a bit line equalising control circuit, a bit line precharging control circuit, a common data line equalising control circuit, and a common data line precharging control circuit. Control signals for equalising and/or precharging circuits are transmitted from each of the foregoing control circuits. For operations other than those during transition from writing to readout, each control circuit receives not only the pulse signal from the pulse generator but also a signal from an address transition detection circuit. Embodiments of the invention described in detail hereinbelow provide a semiconductor memory device that can be arranged for use as a static random access memory (SRAM), and which has a large capacity and can operate at high speed. The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Figure 1 is a diagrammatic view of a chip of a previously proposed semiconductor memory device; Figure 2 is a block diagram showing the arrangement of a typical semiconductor memory device embodying the invention; Figure 3 is a circuit diagram showing parts of the device of Figure 2; Figure 4 is a timing chart showing the operation of a EQW generating circuit of the device of Figure 2; Figure 5 is a circuit diagram showing an example of the EQW generating circuit; and Figure 6 is a timing chart for illustrating the operation of the device of Figure 2. A SRAM forming a preferred illustrative embodiment of the invention will now be described in detail with reference to the drawings. Figure 2 shows schematically the overall construction of the SRAM, which is of complementary metal oxide semiconductor (CMOS) structure. The circuitry of the SRAM is constituted by MOS transistors formed on a major surface of a semiconductor substrate and includes an address buffer-address transition detection (ATD) circuit 4 to which address signals AO to An are inputted and from which address data are transmitted to a decoder 2. Memory cell selection signals are transmitted from the decoder 2 to a memory cell array 1 where a desired memory cell is selected and corresponding data are read out. The data from the memory cell array 1 are amplified by a sense amplifier 3 from which data output signals Dout are transmitted to an output circuit 5. An address transition detection signal ATD, which is a pulse signal comprising pulses generated by transitions of the address signals A0 to An, is outputted from the address buffer-ATD circuit 4 and transmitted to a clock generator 6, in which an equalising pulse signal EQ is generated on the basis of the pulses of the address transition detection signal ATD. An output enable signal OE is inputted from outside to the clock generator 6 so as to be supplied to the output circuit 5 as a signal  OE . The equalising signal EQ is also transmitted to the output circuit 5. Thus, the data signal Dout, the equalising signal EQ and the signal  OE are transmitted to the output circuit 5, where outputting and precharging operations are performed as will be described subsequently. The equalising signal EQ is transmitted to a bit line equalising precharging control circuit 8 and is simultaneously transmitted to a common data line equalising and precharging control circuit 9. A signal which undergoes transition from the time of writing until reading is transmitted to a EQW generator 7. A signal EQW from the generator 7 is transmitted to the bit line equalising and precharging control circuit 8 and to the common data line equalising and precharging control circuit 9. Thus, the control circuits 8 and 9 are controlled not only by the equalising signal EQ, but also by the signal EQW. The memory cell array 1 and peripheral circuitry are shown in Figure 3. A number of memory cells (MC) 11 are arrayed in a matrix configuration with each cell 11 being connected to a pair of bit lines 12, 13. The memory cells 11 comprise flip-flops for data storage. A potential difference is produced across the bit lines 12, 13 at the time of reading and writing. Word lines Xi, Xi+1, ... , arranged at right angles to the bit lines 12, 13, are connected to the memory cells 11. Signals from a row decoder bring the word lines Xi, Xi+1, ... to a high level at the time of row selection to turn on word transistors (not shown) of the memory cells 11. A source or a drain of a pMos transistor 21 is connected to each pair of bit lines 12, 13. Each pMOS transistor 21 constitutes a bit line equalising circuit and can short-circuit the associated bit line pair 12, 13. A signal B from the bit line equalising and precharging control circuit 8 is supplied to the gate of each pMOS transistor 21. Between each bit line of each bit line pair 12, 13 and the high level source voltage there is connected a pMOS transistor 22 which constitutes a bit line precharging circuit and which has its source and drain connected to a source voltage and to the bit line 12 or 13, respectively. The signal B from the bit line equalising and precharging control circuit 8 is supplied to the gate of each pMOS transistor 22, similarly to the pMOS transistors 21. A bit line load transistor 31 is provided for terminating each of the bit lines 12, 13. Each bit line load transistor 31 has its source and gate connected to the source potential and to ground potential GND, respectively. A pair of nMOS transistors 18, 18, functioning as a column select switch, are connected across each bit line pair 12, 13. The bit lines 12 are connected via the nMOS transistors 18 to a common data line 14 of a common data line pair 14, 15 while the bit lines 13 are connected to the common data line 15 via the nMOS transistors 18. Common column select lines Yi, Yi+1, ... , which are selectively brought to a high level by signals from a column decoder (not shown), are connected to the gates of the nMOS transistors 18, 18 associated with the bit line pairs 12, 13. The signals from the column decoder are based on the address signals and function to select a specified one of the memory cells 11 in association with the word lines Xi, Xi+1, ... . The common data line pair 14, 15 functions to select a specified number of bit line pairs 12, 13 in common to associated sense amplifiers 3. Each sense amplifier 3 is connected to the terminals of the common data lines 14, 15 for amplifying the signal potential difference across the lines 14, 15. A main data line 17 is taken out from the sense amplifier 3 for input/output and is used for data outputting. A pair of pMOS transistors 32, 32 functioning as a common data line load are connected across the common data lines 14, 15. The source and the drain of a pMos transistor 23 are connected to the common data lines 14, 15. The pMOS transistor 23 constitutes a common data line equalising circuit and can short-circuit the common data line pair 14, 15. A signal C from the common data line equalising and precharging control circuit 9 is supplied to the gate of the pMOS transistor 23. Between the common data line pair 14, 15 and the source voltage there are connected a pair of pMOS transistors 24, 24 constituting a common data line precharging circuit, with the source and the drain of each of the pMOS transistors 24, 24 being connected to the source potential and to a respective one of the common data lines 14, 15, respectively. The signal C from the common data line equalising and precharging control circuit 9 is also transmitted to the gate of each of the pMOS transistors 24. The circuitry for actuating the equalising and precharging circuitry will now be described. The equalising and the precharging operations for the bit lines 12, 13 are performed by the signal B from the bit line equalising and precharging control circuit 8, while the equalising and the precharging operations for the common data lines 14, 15 are performed by the signal C from the common data line equalising and precharging control circuit 9. In the case of transition from writing to reading, the bit line equalising and precharging control circuit 8 and the common data line equalising and precharging control circuit 9 perform a control operation in accordance with the pulse signal EQW from the EQW generator 7. Thus, in case of transition from writing to reading, as later described, a high speed equalising and precharging operation may be performed. In the case of other address transitions, the control circuits 8, 9 perform necessary control operations in accordance with the pulse signal EQ generated by the clock generator 6 on the basis of the signal ATD from the address buffer-ATD circuit 4 (Figure 2). The EQW generator 7 will now be described with reference to Figures 4 and 5. As shown in Figure 4, the EQW generator 7 generates a pulse of the pulse signal EQW when the write enable signal rises from low level to high level. When the write enable signal is at the low level or at the high level, the chip is set to the write state or to the reading state, respectively. Hence, the rising of the signal corresponds to the transition from writing to reading and this timing of transition may be used to achieve high speed equalising and precharging. The circuit construction of the EQW generator is shown in Figure 5. A pad 41, to which the signal is inputted, is connected to an input terminal of a two-input NOR circuit 42, which has its other input terminal grounded, while an output of the NOR circuit 42 is inputted to one input terminal of a two-input NAND circuit 44 by way of an inverter 43. An output of the inverter 43 is connected to the other input terminal of the NAND circuit 44 by way of a delay circuit 45 consisting of plural stages of inverters. The delay circuit 45 determines the pulse width of the signal EQW. An output of the NAND circuit 44 is transmitted as the pulse signal EQW to the bit line equalising and precharging control circuit 8 and to the common data line equalising and precharging control circuit 9 by way of an inverter 46. In this manner, the EQW generator 7 directly generates pulses from the signal and collection of plural stages of address transitions is unnecessary so that the pulses of the signal EQW may be transmitted at elevated speeds to the control circuits 8, 9 to shorten the write recovery time. The operation of the above-described SRAM of the illustrative embodiment will now be explained with reference to Figures 3 and 6. The address signal shown at (a) in Figure 6 is changed at a time t0, at the same time that the write enable signal shown at (c) in Figure 6 is changed from the low level to the high level. With the write enable signal thus changed, the chip is switched from writing operation to reading operation. The write enable signal is transmitted immediately to the EQW generator 7 shown in Figure 3 and, at a time t1 after an extremely short time has elapsed, a pulse of the signal EWQ is produced, as shown at (d) in Figure 6. This is because the pulse of the signal EQW is generated with high response from the write enable signal by the EQW generator 7. The thus-produced pulse of the signal EQW is transmitted to the bit line equalising and precharging control circuit 8 and to the common data line equalising and precharging control circuit 9. The bit line equalising, bit line precharging, common data line equalising and common data line precharging operations are performed by the control signals B, C from the control circuits 8, 9. That is, at the bit lines 12, 13, the pMOS transistors 21 forming the bit line equalising circuits are turned on, while the pMOS transistors 22 forming the bit line precharging circuits are turned on. The result is that the level - shown at (e) in Figure 6 - at the bit line pair, which has been swung almost fully, is raised towards the source voltage when the current flows from the high level bit line to the low level bit line by equalising, with the precharging pMOS transistors 22 turned on, until the potentials at the bit lines 12, 13 become equal to each other at a time t2. At the time t2, or at a time t3, the pulse of the signal EQW ends, that is the signal EQW goes low, to terminate the equalising and precharging operation. Similarly, on the common data lines 14 and 15, the pMOS transistor 23 forming the common data line equalising circuit is turned on and the pMOS transistors 24 forming the common data line precharging circuit are turned on. The result is that the level - as shown at (f) in Figure 6 - at the common data line pair, which has been swung almost fully, is raised to the source voltage by the pMOS transistors 24, with the current flowing from the high level common data line to the low level common data line by equalisation, until the potentials at the common data lines 14, 15 become equal to each other at a time t4. In this manner, the equalising and precharging operations are performed at the bit lines 12, 13 and the common data lines 14, 15 on the basis of the signal EQW and, towards the close of these operations, the potential - shown at (b) in Figure 6 - of the word line to be selected is raised at a time t5 to effect the row selecting operation. In the word line selecting operation, the word transistors of the memory cells 11 of a given column are turned on to turn on the drive transistor to cause the signal potential difference to appear across the bit lines 12, 13. Such signal potential difference is also caused to appear on the common data lines 14, 15 by way of the pMOS transistors 18 forming the column select switch. The data are outputted and read out by way of the sense amplifiers 3. For comparison, the operation of the equalising pulse signal EQ based on the address buffer-ATD circuit 4 will now be explained with reference to signals shown by broken lines at (g) to (i) in Figure 6. After the change in the address signal at the time t0 and at the time of using the address buffer ATD circuit 4, a delay is caused and, at a time t11, a pulse of the signal EQ - as shown at (g) in Figure 6 - is generated by the clock generator 6. As a result, the equalising and precharging operation for the level on the bit line - see (h) in Figure 6 - and the level on the common data line - see (i) in Figure 6 - is performed with a delay as compared to the case of the EQW pulse signal. At a time t12 the levels of the bit line pair become equal, and, at a time t13, the levels of the common data line pair become equal. With a time difference of approximately ΔT at the bit lines as compared to the case of the pulse signal EQW, it can be seen that a higher speed may be realised when the equalising and precharging operation is carried out by generating the pulses of the EQW signal by the EQW pulse generator 7 on the basis of the write enable signal With the SRAM of the present embodiment, a pulse of the EQW signal is generated at an elevated speed by the EQW pulse generator 7 from the write enable signal at the time of transition from the write operation to the readout operation, despite the fully swung state of the bit lines and the common data lines, to perform the equalising and precharging operation, so that high speed access can be realised, while the word line can be selected at a high speed to prevent data destruction in the memory cell. Although both the bit lines and the common data lines are both equalised and precharged in the above embodiment, it is possible for only the common data lines to be equalised and/or precharged. Although the precharging and equalising circuits are each formed by pMOS transistors, other transistor types may also be used in combination. Similarly, for selecting the impedance, the threshold voltage Vth, the signal level supplied to the base or the gate, or the element size can be selected. The bit line load or the common data line load can be formed as variable load means. Ways in which the output circuit 5 used as an output buffer on the SRAM of the present illustrative embodiment can be constructed are described in the specification of this application as published under the number EP-A-0 384 673 and in the specification of European Patent Application No. 94200916.8 which has been divided from this application.

Claims: A memory device comprising: a plurality of memory cells (11) arranged in a matrix configuration and composed of flip-flop circuits for data storage; a plurality of pairs of bit lines (12, 13), each coupled to a column of the memory cells (11), for handling complementary read-out data or write data; a plurality of word lines (Xi etc), one for each row of the memory cells (11), for selecting rows of the memory cells; a sense amplifier (3) connectable to a pair of bit lines (12, 13) for amplifying the voltage across the pair of bit lines; equalising means (23) operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of lines by setting the lines to the same potential; equalising control means (9) for setting the operating time interval for the equalising means (23); first signal generating means (4, 6) responsive to an address signal supplied for selection of the word lines (Xi etc) and the bit lines (12, 13) to generate a signal for actuating the equalising control means (9); and second signal generating means (7) operative to detect a transition from writing to read-out; characterised in that: the memory cells (11), the bit lines (12, 13), the word lines (Xi etc), the sense amplifier (3), the equalising means (23), the equalising control means (9), the first signal generating means (4, 6) and the second signal generating means (7) are all formed on a major surface of a semiconductor substrate; a plurality of pairs of common data lines (14, 15) are formed on said major surface and each pair is connected in common by column select switches (18) to a plural number of bit line pairs (12, 13) for handling complementary read-out data or write data; the sense amplifier (3) is connected to a pair of common data lines (14, 15); the equalising means (23) acts as common data line equalising means in that it is operative to equalise a pair of common data lines (14, 15); and the second signal generating means (7) is operative to actuate the equalising control means (9) at the time said transition is detected. A memory device according to claim 1, comprising bit line equalising means (21) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of the bit lines (12, 13), the equalising control means (8, 9) being operative to control the bit line equalising means (21) and the common data line equalising means (23). A memory device comprising: a plurality of memory cells (11) arranged in a matrix configuration and composed of flip-flop circuits for data storage; a plurality of pairs of bit lines (12, 13), each coupled to a column of the memory cells (11), for handling complementary read-out data or write data; a plurality of word lines (Xi etc), one for each row of the memory cells (11), for selecting rows of the memory cells; a sense amplifier (3) connectable to a pair of bit lines (12, 13) for amplifying the voltage across the pair of bit lines; precharging means (24) operative transiently prior to memory cell selection by a word line (Xi etc) to precharge a pair of lines by connecting the lines to a potential source; precharging control means (9) for setting the operating time interval for the precharging means (24); first signal generating means (4, 6) responsive to an address signal supplied for selection of the bit lines (12, 13); and second signal generating means (7) operative to detect a transition from writing to read-out and to actuate the precharging control means (9) at the time said transition is detected; characterised in that: the memory cells (11), the bit lines (12, 13), the word lines (Xi etc), the sense amplifier (3), the precharging means (24), the precharging control means (9), the first signal generating means (4, 6) and the second signal generating means (7) are all formed on a major surface of a semiconductor substrate; a plurality of pairs of common data lines (14, 15) are formed on said major surface and each pair is connected in common by column select switches (18) to a plural number of bit line pairs (12, 13) for handling complementary read-out data or write data; the sense amplifier (3) is connected to a pair of common data lines (14, 15); the first signal generating means (4, 6) is responsive to the address signal supplied for selection of the bit lines (12, 13) to generate a signal for activating the precharging control means (9); and the precharging means (24) acts as common data line precharging means in that it is operative to precharge a pair of common data lines (14, 15). A memory device according to claim 3, comprising bit line precharging means (22) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to precharge a pair of the bit lines (12, 13) the precharging control means (8, 9) being operative to control the bit line precharging means (22) and the common data line precharging means (24). A memory device according to claim 4, comprising first equalising means (23) operative transiently prior to memory cell selection by a word line (Xi etc) to equalise each of a pair of the common data lines (14, 15), second equalising means (21) operative transiently prior to selection of a memory cell (11) by a word line (Xi etc) to equalise each of a pair of the bit lines (12, 13), and equalising control means (8, 9) formed on said major surface for controlling each of the first and second equalising means (23, 21), both the equalising control means (8, 9) and the precharging control means (8, 9) being arranged to be controlled by a signal from each of the first signal generating means (4, 6) and the second signal generating means (7). A memory device according to claim 3, comprising equalising means (23) formed on said major surface and operative transiently prior to memory cell selection by a word line (Xi etc) to equalise a pair of the common data lines (14, 15), and equalising control means (8, 9) formed on said major surface for setting the operating time interval for the equalising means (23), both the equalising control means (8, 9) and the precharging control means (8, 9) being arranged to be actuated by a signal from each of the first signal generating means (4, 6) and the second signal generating means (7). A memory device according to any one of the preceding claims, wherein the second signal generating means (7) is operative to detect a transition from writing to read-out on the basis of a write enable signal.

Inventors: ARAKI SHIGEO C O PATENTS DIVIS, SUZUKI HIROYUKI C O PATENTS DI, ARAKI, SHIGEO, C/O PATENTS DIVISION, SUZUKI, HIROYUKI, C/O PATENTS DIVISION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: G11C7
IPC codes: G11C11, G11C7