Memory access control circuit for graphic controller

Abstract: A memory access control circuit (52) includes an access mode determining information generator (2,38,39) receiving an access request from a data processing unit and generating information for determining an access mode to be performed by judging access information of the access request. The memory access control circuit (52) further includes an access sequence control circuit (4) having a function of performing memory access operations in accordance with not only an access mode designated by the access information of the access request but also other access modes and selecting one of the access modes in response to the access mode determining information from the generator to perform the memory access operation in accordance with the selected access mode. Thus, the access sequence control circuit manages a plurality of access modes by itself and performs a memory access operation by selecting an adequate one of the access modes. The data processing unit such as a drawing control unit is thereby free from the management of all the access modes. In a graphics display system, the access mode determining information can be derived from an access address, mask data and so forth.

Description: BACKGROUND OF THE INVENTION The present invention relates to a memory access control circuit for performing an access operation to a memory in response to a request from a data processing unit and, more particularly, to such a control circuit for a graphic controller in a graphic display system for displaying characters, figures and so forth by means of a printer and/or a raster scan type cathode ray tube (called hereinafter "CRT"). A memory access control circuit intervenes between a data processing unit and a memory and responds to an access request from the data processing unit to perform a data read/write operation on the memory in accordance with a designated one of various access modes. Also in a graphics display system, a memory access control circuit intervenes between a drawing control unit, which performs a drawing data processing operation on characters, figures and so forth to be displayed, and a frame buffer memory, which temporarily stores character and figure data being currently displayed. The display of characters and figures on CRT is performed by the drawing control unit generating character and figure data to be displayed and writing them into the frame buffer memory through the memory access control circuit. While the access to the frame buffer memory is performed in word units, the actual drawing process is frequently performed only on one of few bits within the accessed word. This is because one pixel (picture element), which represents a unit of processing in the graphics display system, consists of one to four bits in general and thus one word includes a plurality of pixels. For instance, in drawing of a line such as a straight line, a circle, an arch or the like, the number of pixels to be processed in one word is one (two or more in some cases). Therefore, only the data of a pixel or pixels to be processed within one word read out from the frame buffer memory are modified or updated in accordance with line type data and/or color data to be displayed and the word containing the modified or updated data bits is then written back to the same address of the buffer memory. In this case, three successive steps are required, the first step being of reading one word data from the frame buffer memory, the second step being of modifying certain pixel data, and the third step being of writing the word including modified data bits back to the memory. An operation for performing those three steps is hereinafter called "read-modify-write (or RMW) access". On the other hand, such a memory has been developed and put into practical use, that has improved access modes for shortening an access time. One of them is a write-per-bit (WPB) access mode. According to this access mode, only by supplying the memory with modifying data together with mask data for designating a bit or bits to be modified within one word, the data of the bit or bits designated by the mask data are automatically modified inside the memory in accordance with the modifying data. If the memory having WPB access is employed, therefore, the operation required to the graphic controller is reduced to only one step of supplying the modifying data and the mask data to the memory. The graphic controller is free from the data read access operation and the data modifying operation. In other words, WPB access causes the same operation as RMW access with the same access speed as a random write access. WPB access is effective in drawing process of a line above, in which the original data of the pixel or pixels to be processed are not required. Another of the high-speed access modes is a page-mode access, in which a memory address is divided into a row address defined as a page address and a column address defined as a word address within one page so that in case of accessing successive words within one page, the row address for the second and later words is not required. The graphics display system also has a bit-block-transfer (BitBlt) function of transferring data stored in a certain area (i.e., a source area) to another area (i.e., a destination area), and thus the page-mode access is effective in this function. Thus, by selecting the optimum one of the access modes of the memories employed in the graphics display system in accordance with the drawing operation to be performed, the memory access speed and efficiency are improved extremely. The selection of the access mode to be used can be carried out by the drawing algorisms of the drawing control unit responsive to the required drawing operations. However, the kind of memories (and thus the access modes thereof) actually employed in a system depends on a spec of the system to be structured. That is, it is impossible for the drawing control unit to predict the kind of memories, which will be employed in the system, at the moment of determining the drawing algorisms thereof. Moreover, in a recent system, the memory, which is an object of the drawing operation by the drawing control unit, is not restricted to the frame buffer memory, but is spread over a so-called system memory which is used by CPU operating as a host processor of the system. Since the access frequency to the system memory by CPU is considerably higher than that by the graphic controller, an ordinal dynamic memory (DRAM) not having WPB access mode is used as the system memory in view of the costs. Further, a system bus coupled with the system memory cannot meet the page-mode access in general. Thus, there are a case where ordinal DRAMs are employed as both of the frame buffer memory and the system memory and another case where a memory having WPB access mode and/or the page-mode access is employed as the frame buffer memory and ordinal DRAM is employed as the system memory. It is therefore considered to prepare a plurality of drawing algorisms corresponding respectively to the memory access modes for each one of the drawing operations. However, the preparation of a plurality of drawing algorisms causes he expansion of firmwares for performing the respective algorisms, so that the cost of the drawing control unit is i creased. Moreover, it is required to detect conditions and circumstances for selecting optimum one of the drawin algorisms, so that the burden of application software is increased. Furthermore, if a new memory having a higher access speed mode would be provided in further, the development of the drawing control unit will have to start all over again. EP-A-0 228 136 discloses a generalized operation-signalling logic for a raster scan video controller which, in accessing the memory of a computer system, can indicate what type of operation is to be performed at each memory address to be accessed. The signalling scheme provides a rich set of functions, logic to generate this signalling and an external PLA-type device which interprets this signalling for a wide variety of memory types. GB-A-2 210 239 discloses an apparatus for controlling the access of a video memory comprising a group of registers in which various kinds of control data are set to access a video memory. The group of the registers are set to store data for detecting scanning rasters, incrementing or decrementing an address of the video memory which is accessed, and starting a DMA transfer of image data. Therefore, various kinds of accessing modes can be performed without the necessity of a complicated software. SUMMARY OF THE INVENTION Therefore, a object of the present invention is to provide a memory access control circuit which determines an optimum memory access mode and performs the determined memory access mode without requiring various memory access mode designation data from a data processing unit. Another object of the present invention is to provide a graphic controller having an improved memory access control circuit which performs an adequate memory access for a drawing operation to be performed in accordance with a memory employed in a system. Still another object of the present invention is to provide a memory access control circuit which can perform a plurality of memory access operations, the number of which is larger than the number of access modes designated by a drawing control unit, and which judges automatically which memory access is to be performed and executes the judged memory access. A memory access control circuit according to the present invention is claimed in claims 1, 3 and 5. Thus, the access sequence control circuit manages a plurality of access modes by itself and performs a memory access operation by selecting an adequate one of the access models. The data processing unit such as a drawing control unit is thereby free from the management of all the access modes. In a graphics display system, the access mode determining information can be derived from an access address, mask data and so forth. BRIEF DESCRIPTION OF THE DRAWINGS The above an other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram representative of a graphic controller including a memory access control unit according to a first embodiment of the present invention; Fig. 2 is a diagram representative of a kind of operations performed by RMW operator shown in Fig. 1; Fig. 3 is a memory map representative of address spaces allocated to a frame buffer memory and a system memory shown in Fig. 1; Fig. 4 is a block diagram representative of a second embodiment of the present invention; Fig. 5 is a diagram representative of access modes performed by an access sequence control circuit shown in Fig. 4; Fig. 6 is a block diagram representative of a third embodiment of the present invention; Fig. 7 is a diagram representative of access modes performed by an access sequence control circuit shown in Fig. 6; Fig. 8 is a diagram representative of some access modes in drawing of a straight line; Fig. 9 is a diagram representative of some access modes in BitBlt drawing operation; Fig. 10 is a timing chart representative of RMW access; Fig. 11 is a timing chart representative of WPB access; Fig. 12 is a timing chart representative of a random read (R) access; Fig. 13 is a timing chart representative of a random write (W) access; Fig. 14 is a timing chart of a no-access operation (NOP); Fig. 15 is a timing chart representative of a page-mode read-modify-write (PRW) access; Fig. 16 is a timing chart representative of a page-mode read (PR) access; and Fig. 17 is a timing chart representative of a page-mode write (PW) access. DETAILED DESCRIPTION OF THE EMBODIMENTS Referring now to Fig. 1, a memory access control circuit 52 intervenes between a drawing control unit 51 and each of frame buffer memory 53 and a system memory 54 to perform an access operation on the memory 53 and/or 54 in response to an access request from the unit 51. The drawing control unit 51 and memory access control circuit 52 are integrated on a single semiconductor chip as a graphic controller 50. If desired, the unit 51 and circuit 52 may be fabricated on separate semiconductor chips, respectively. The drawing control unit 51 responds to commands from CPU (not shown) and executes drawing operations in accordance with drawing algorisms prepared therein. In order to initiate the drawing operation, CPU sets a drawing mode data into a drawing mode register 46 and further issues a drawing parameter and a drawing command to a drawing sequence control circuit 40. The drawing command instructs a drawing operation to be executed such as a line drawing, a painting of a polygon, BitBlt operation and so forth. The drawing parameter includes drawing start and/or end addresses, a line type pattern data, color data and the like required for performing the instructed drawing operation. The drawing mode data designates a kind of operation on write-data (S) 31 from a write-data generator 42 and original data (D) 33 of a pixel or pixels to be processed. Seven kinds of operations are shown in Fig. 2, as typical examples. The operation designated by the drawing mode data is performed by a RMW operator 47. It should be noted that the RMW operator 5 is further supplied mask data (M) 32 from a mask data generator 43. Thus, RMW operator 47 performs the following operation on the write-date 31, "S", the original data 33, "D", and the mask data 32, "M", and produces the resultant data 48, "W": W = ( M ∧ D) ∨ (M ∧ (S OP D)) wherein "∧" represents a logic AND operation; "∨" represents a logic OR operation; and "OP" represents the operation designated by the drawing mode data (see Fig. 2) The original data (D) 33 is read out from the memory 53 or 54 and supplied to RMW operator 47. The drawing sequence control circuit 40, when receiving the drawing command and parameter, controls an address generator 41, write-data generator 42 and mask data generator 43 to generate a drawing (access) address 30, write-data 31 and mask data 32 corresponding to the pixel or pixels to be processed in accordance with the drawing algorisms realized by firmwares provided therein. Since the construction and operation of the drawing control unit 51 is well known in the art and is not related directly to the feature of the present invention, further detailed description will be omitted. The memory access control circuit 52 makes access to the memories 53 and 54 in response to the data and control signals from the drawing control unit 51. Included in the circuit 52 is an access sequence control circuit 4 which receives a read/write signal (RW) 26 from a read/write flag 45 of the control unit 51. RW signal 26 designates an access mode. In the present embodiment, the low level of RW signal 26 designates a random read access (R access), whereas the high level thereof designates RMW (read-modify-write) access. The drawing algorisms of the drawing sequence control circuit 40 are thus determined such that the drawing operations responsive to the drawing commands are performed by use of R access and RMW access. The actual access operation is performed in synchronism with an access request signal (AREQ) 27, and the drawing sequence control circuit 40 is informed of the completion of one access operation by an access end signal (AEND) 28 returned from the access sequence control circuit 4. The access sequence control circuit 4 further receives the output of an AND gate 39 and determines an access mode to be performed actually in response to the level of RW signal 26 and the output level of the AND gate 39 to shorten an access time by effective use of access modes built in the frame buffer memory 53. One input end of the AND gate 39 is supplied with the output of an address comparator 2 which in turn detects that the output 30 of the address generator 41, i.e. a memory address to be accessed, is within an address range preset in an address range register 7. In this embodiment, the frame buffer memory 53 is allocated in an address range from "040000H" to "090000H", as shown in Fig. 3. The mark "H" represents a hexadecimal notation. When a memory having WPB access mode is employed as the frame buffer memory 53, the register 7 is set with numbers of "04H" and "09H" as most significant eight bits of address information at an initial setting state by CPU. If an ordinal DRAM, which does not have a WPB access mode, is employed as the frame buffer memory 53, the register 7 is set with a default number. Accordingly, in case of the memory address 30 to be accessed being the frame buffer memory 53 having WPB access mode, the comparator 2 outputs the high level which is in turn supplied to one input end of the AND gate 39. On the other hand, when a memory not having WPB access mode is employed as the frame buffer memory 53 or when the memory address 30 belongs to the system memory 54, the output of the comparator 2 takes the low level. The other input of the AND gate 39 is supplied with an output signal (RM) 23 of a drawing mode detector 38. RM signal 23 takes the high level only when the operation performed by RMW operator 47 does not require the data of the pixels to be processed, as shown in Fig. 2 by "replace" and "inverted-replace" operations. Thus, when the pixels to be process are contained in the frame buffer memory 53 having WPB access mode and the designated drawing mode is replace or inverted-replace operation, the output of the AND gate 39 is changed to the high level. Even when the drawing control unit 51 designates RMW access by the high level of RW signal 28, if the output of the AND gate 39 is the high level, the access sequence control circuit 4 changes a set of access control signals 141 at its output from RMW access mode to WPB access mode. The set of access control signals 141 includes a latch-enable signal 111 for a latch circuit 11 which temporarily stores the memory address 30, a data output-enable signal 121 for a tristate output buffer 12 which transfers the output 48 of RMW operator 47, a data input-enable signal 131 for a tristate input buffer 13 which fetches read data from the memories 53 and 54, a latch-enable signal 151 for a latch circuit 15 which temporarily stores the mask data 32, an address / mask switching signal 191 for a multiplexer (MPX) 19 which outputs either one of the memory address and mask data, and an operation timing control signal 471 for controlling an operation timing of RMW operator 47. The set of access control signals 141 further includes a chip select signal for the memories 53 and 54 and an R/ W signal indicating data read or write operation, which are supplied via a control bus 57 to the memories 53 and 54. The address / mask signal is also supplied to the memories 53 and 54 via the bus 57. Buses 55 and 56 are address and data buses, respectively. The address bus 55 is used as a multiplex bus for a memory address and mask data in case of employing a memory having WPB access mode. Assume now that the drawing control unit 51 request RMW access to the memory access control circuit 52. At this time, if the AND gate 39 is in the low level, the access sequence control circuit 4 performs RMW access operation in accordance with a timing chart shown in Fig. 10. Specifically, an access to be actually performed is determined against an access request from the control unit 51 in T1 state, and the determined access in then initiated at T2 state. In this description, since RMW access mode is determined as an access mode to be actually determined, the data read out from the accessed word is transferred to RMW operator 47 in T4 state, and RMW operator 47 performs in T5 state the operation designated by the drawing mode data on the data of the pixel or pixels within the accessed word, followed by the operation resultant data 48 being written back to the same address in T6 state. This T6 state corresponds to T1 state for a next memory access. On the other hand, if AND gate 39 changes its output to the high level in response to an access request from the control unit 51, the access sequence control circuit 4 performs WPB access operation against RMW access request, in accordance with a timing chart shown in Fig. 11. Specifically, in T2 state, the address / mask switching signal is changed to the low level to allow the mask data 32 to be transferred onto the bus 55. At an intermediate time point in T3 state, the switching signal is returned to the high level, so that the memory address 30 is transferred onto the bus 55. During T3 state, RMW operator 47 performs the replace operation and the output data 48 thereof is transferred onto the bus 56 in T4 state. In WPB access, T4 state corresponds to T1 state of a next memory access. Thus, RMW access requires 6 states, whereas WPB access is completed for 4 states. When the control unit 51 request R access by the low level of RW signal 26, the access sequence control unit 4 performs R access in accordance with a timing chart shown in Fig. 12, irrespective of the output level of the AND gate 39. The data read out of the accessed word is stored into the register 44. R access requires 4 states, similarly to WPB access. Turning to Fig. 4, there is shown a block diagram of a memory access control unit according to a second embodiment of the present invention, wherein the same constituents as those shown in Fig. 1 are denoted by the same reference numerals to omit further description thereof. The control circuit 52 according to this embodiment further includes a mask comparator 1 and a memory type register 8. The mask comparator 1 detects or compares the content of the mask data 32 and outputs MO signal 21 when all the bits of the mask data 32 are "0" and M1 signal 22 when they are all "1". The memory type register 8 stores codes representing the kinds of memories employed as the frame buffer memory 53 and system memory 54. In this embodiment, the codes to be stored in the register 8 are determined as follows: 0: DRAM not having WPB access mode 2: DRAM having WPB access mode when the output of the comparator 2 is at the high level, the code "2" is supplied from the register 8 to the circuit 4. On the other hand, the low level output of the comparator 2 causes the register 8 to supply the code "0" to the circuit 4. In operation, at an initial state, CPU writes upper and lower addresses of the frame buffer memory 53 into the register 7 and the memory type codes into the register 8. When CPU encounters a drawing instruction, it writes the drawing mode data into the register 46 and issued the drawing command and drawing parameters to the drawing control unit 51. In response thereto, the drawing control unit 51 starts the execution of the drawing operation, as mentioned above. Specifically, the address generator 41 generates a memory address 30 designating a word containing a pixel or pixels to be processed and the mask generator 43 generates mask data 32 representative of the pixel or pixels to be processed. In case of R access, the flag 45 is set with "0" to change RW signal 26 to the low level. On the other hand, in case of RMW access, the flag 45 is set with "1" to produce the high level RW signal 26. Also in RMW access, the write-data generator 42 generates write-data 31 for drawing. The above data and signal 30, 48, 32 and 26 are supplied to the memory access control circuit 52 together with AREA signal 27. In response to AREQ signal 27, the control circuit 52 initiates the access mode determination operation and the access performing operation with reference to the supplied data and signal. More specifically, the mask comparator 1 detects that the contents of the mask data 32 are all "0" or all "1" and supplies MO signal 21 and M1 signal 22 to the access sequence control circuit 4. The address comparator 2 detects whether or not the memory address 30 is within the address region allocated to the frame buffer memory 53 and supplies the detection output to the register 8. The code "0" or "2" are thus supplied from the register 8 to the access sequence control circuit 4 as MT signal 20. The drawing mode detector 38 detects the content of the drawing mode data 49 from the register 46 and supplies RM signal 23 to the access sequence control circuit 4. RM signal 23 takes the high level when replace or inverted-replace operation is designated and takes the low level when other operation is designated, as shown in Fig. 2. These MO signal 21, M1 signal 22, MT signal 20 and RM signal 23 are used as access mode determination (or selection) information for determining an optimum and adequate memory access mode. In response to the access mode determination information, the access sequence control circuit 4 selects and determines one of a plurality of access modes provided therein in accordance with the relationship shown in Fig. 5 and described in detail in the following: I. RMW access request (RW = H) Unless the conditions (1), (2) and (3) below are satisfied, RMW access mode is selected as an access mode to be performed. (1) MO = H (all the bits of mask date 32 are "0") This condition represents that all the bit data of a word to be accessed are not required to be updated or modefied. Therefore, the memory access that itself can be omitted. Namely, RMW access request is changed to no-access-operation (NOP). (2) M1 = H and RM = H (all the bits of mask data 32 are "1" and replace or inverted-replace operation is designated). This condition represents that all the bit data of a word to be accessed are replaced by the write-data 31 or inverted one thereof. Accordingly, a random write (W) access can be used. RMW access request is thus changed to W access. (3) RM = H and MT = 2 (replace or inverted-replace operation is designated and the frame buffer memory 53 has WPB access mode). RMW access request is thus changed to WPB access. II. Read access request (RW = L) A random read access (R) is required in all the cases. When the access mode to be used is determined, the access sequence control circuit 4 generates and supplies appropriate access control signals described above to the control bus 57, tristate buffers 12 to 14, latch circuits 11 and 15, MPX 19 and the operator 47 in order to performed a memory access of the selected access mode. The timing charts of RMW access, WPB access and R access are shown in Figs. 10, 11 and 12, respectively. W access and NOP timings are shown in Figs. 13 and 14, respectively. In response to the access control signals on the bus 57, a timing controller (not shown) provided in the memories 53 and 54 generates RAS , CAS , WB / WE and DT / OE signals for VRAM which has WPB access mode and is used as the frame buffer memory 53, and also generates RAS , CAS , WE and OE signals for ordinal DRAM which does not have WPB access mode and is used as the system memory 54, as well known in the art. Referring to Figs. 8 and 9, there are shown comparisons in a drawing time between a case of employing a memory not having WPB access mode and a case of employing a memory having WPB access mode. Fig. 8 shows a straight line drawing operation, in which pixels 1 to 6 denoted by slant lines becomes objects of this drawing operations. One word consists of four pixels, in this description. The line drawing operation is performed in pixel unit, and therefore both of MO and M1 signals 21 and 22 take the low level. In case of employing DRAM not having WPB access mode as the frame buffer memory 53, MT signal 20 is held at the code "0". As a result, the memory access control circuit 52 selects and performs RMW access to each of the pixels 1 to 6 (see Example 1 in Fig. 8). On the other hand, in case of employing DRAM having WPB access mode as the memory 53, MT signal 20 is changed to the code "2". Therefore, the access sequence control circuit 4 selects and performs WPB access (see Example 2 in Fig. 8) in place of RMW access request from the drawing control unit 51. Fig. 9 shows a destination area in BitBlt operation. This destination area consists of four successive words i, i+1, i+2 and i+3, but excludes respective one portions of the word i and i+3. Example 1 in Fig. 9 indicates that RMW access operation is performed for all of the words i to i+3. Since the mask data for the words i+1 and i+2 are all "1", however, the access sequence control circuit 4 performs W access operation on these words i+1 and i+2 (see Example 3 in Fig. 3). Further, in case of MT signal 20 indicating the code "2", the access sequence control circuit 4 performs WPB access operation on the words i and i+3. The access times of W, WPB and RMW accesses are as follows: W access: 150 nsec WPB access: 150 nsec RMW access: 250 nsec Thus, the access sequence control circuit 4 automatically selects an optimum access mode and then performs a memory access in accordance with the selected access mode. The access speed thereby becomes minimum. Turning to Fig. 6, there is shown as a third embodiment of the present invention a memory access control circuit for a memory to which a page-mode access can be made, wherein the same constituents as those shown in Figs. 1 and 4 are denoted by the same reference numerals. The memory access control circuit 52 according to this embodiment includes a last address register 9 for storing a memory address which was used in the latest memory access operation, a last data register 10 for storing data of a word accessed by the address stored in the last address register 9, and an address comparator 3 comparing the memory address 30 from the address generator 41 with the address stored in the register 9. When the memory address 30 is coincident with the address stored in the register 9, i.e. when both of page and word addresses of the memory address 30 are coincident with those of the address from the register 9, the comparator 3 changes SA signal output 24 to the high level. The comparator 3 further has SP signal output 25, the level of which is controlled by the comparison between only the page addresses of the memory address 30 and the address from the register 9 and is changed to the high level when both the page addresses thereof are coincident with each other. The codes to be set to the memory type register 8 are designed in this embodiment as follows: 0: DRAM to which a page-mode access cannot be made 1: DRAM to which a page-mode access can be made The MT signal 20, SA signal 24 and SP signal are used as access mode determination (and selection) information. In response to this information, the access sequence control circuit 4 selects and determines one of a plurality of access modes provided therein in accordance with the relationship shown in Fig. 7 and described in detail in the following: I. RMW access request (RW = H) Unless the conditions (1), (2) and (3) below are satisfied, RMW access mode is selected as an access mode to be used. RMW access operation is performed in the timing shown in Fig. 10 with replacing the address / mask switching signal by a page-mode signal for indicating a page-mode access to the memory 53. (1) SA = 1 and MT = 0 In this case, the data of the latest memory access is copied in the register 10, and hence RMW access request can be changed to W access mode. W access operation is performed by the timing shown in Fig. 13 with replacing the address / mask switching signal by the page-mode signal. (2) SA = H and MT = 1 Since the page-mode access can be used and the data of a word to be accessed is stored in the register 10, a page-mode write (PW) access is selected and performed in accordance with the timing shown in Fig. 17. (3) SA = L, SP = H and MT = 1 Although the page-mode access can be utilized, the data stored in the register 10 is not equal to the data of a word to be accessed. Therefore, a page-mode read-modify-write (PRW) access is selected and performed in accordance with the timing shown in Fig. 15. II. Read access request (RW = L) Unless the following conditions (1) and (2) are satisfied, R access is performed by the timing shown in Fig. 12. The address / mask signal is replaced by the page-mode signal. (1) SA = H Since the data stored in the register 10 is equal to the data of a word to be access, the read access that itself is omitted and becomes NOP. (2) SA = L, SP = H and MT = 1 Since page-mode access can be utilized, a page-mode read (PR) access is selected and performed in accordance with the timing shown in Fig. 16. Thus, an access mode is determined and a memory access according to the selected access mode is performed by the access sequence controller. For preparation of a next memory access, the memory address 30 and data in the current memory access operation are stored in the registers 9 and 10, respectively. The data to be stored in the register 10 is read-data from the access word in case of read memory access or write-data into the accessed word in case of write memory access. Referring again to Figs. 8 and 9, there are further shown memory access modes utilizing page-mode accesses. The page-mode access is most effective in BitBlt operation. Specifically, as shown in Fig. 9 as Example 2, although RMW access has to be used for the word i, PW access operation is performed on the words i+1 and i+2. The word i+3 is within the same page as the words i, i+1 and i+2. However, only one portion of the word i+3 has to be processed. Therefore, PRW access operation is performed on the word i+3. It is noted that in BitBlt operation, the drawing control unit 51 preliminarily stores word data of a source area into the register 44 by use of R access and/or PR access. On the other hand, a line drawing operation is represented in Fig. 8 by Example 3 and Example 4. Specifically, the page and word addresses of the pixels 2 and 3 are equal to those of the pixel 1 and the page and word addresses of the pixel 5 are equal to those of the pixel 5. Therefore, W access operation is performed on the pixels 2, 3 and 6 in case of employing a memory to which a page-mode access can be made (see Example 3). On the other hand, when a memory to which a page-mode access can be made is employed, PW access operation is performed on pixels 2, 3 and 6. Further, if the page address of the pixel 4 is equal to that of the pixel 4, PRW access operation is performed on the pixel 5. As a result, the respective access operations on the pixels 1 to 6 are shown as Example 4. The access times of the respective access operation are as follows: PW access: 50 nsec W access: 150 nsec PRW access: 150 nsec RMW access: 250 nsec Thus, an adequate access mode is automatically selected to enhance the processing speed and efficiency. It is apparent that the present invention is not limited to the above embodiments but may be modified and changed. For example, the memory access control circuit 52 can be constructed to meet a memory to which both of WPB access and a page-mode access can be made, by combining the structures shown in Figs. 4 and 6 and expanding the access selection modes shown in Figs. 5 and 7. A memory other than three kinds of memories describe above, for example a static random memory, can be also controlled only by adding required access timing control circuit to the access sequence control circuit 4 and expanding the access mode selection sequence. The kinds of operations of RMW operator 47 may changed and expanded, if desired. The address space of the frame buffer memory 53 can be changed and further devided into a plurality regions. In this case, the address region register 7 has a plurality of storage areas for storing upper and lower addresses of the respectife address areas.

Claims: A memory access control circuit (52) inserted between a data processing unit (CPU) and a memory (53, 54) having a plurality of storage areas, said memory access control circuit comprising: receiving means (4, 51) operatively coupled to said data processing unit (CPU) for receiving an access request (27) from said data processing unit (CPU), said access request (27) including access information (26, 30) containing a memory address (30) which selects one of said storage areas of said memory (53, 54) and access mode designation information (26) which specifies a first memory access operation to be performed on said selected storage area to perform a predetermined data processing operation on said selected storage area, storing means (7) for temporarily storing address information which corresponds to a part of said storage areas of said memory (53, 54), each storage area contained in said part being accessible by said first memory access operation and further by a second memory access operation which performs a data processing operation equivalent to said predetermined data processing operation performed by said first memory access operation and at a faster speed than said first memory access operation, generation means (2, 38, 39) operatively coupled to said receiving means (4, 51) and said storing means (7) for generating, in response to said access information (26, 30) and said address information, an access change command signal taking a first state when said selected storage area is outside of said part of storage areas and a second state when said selected storage area is within said part of storage areas, and access sequence control means (4) operatively coupled to said memory (53, 54) and said generation means (2, 38, 39) for performing said first memory access operation on said selected storage area when said access change command signal is in said first state and performing said second memory access operation on said selected storage area irrespective of said access mode designation information (26) specifying said first memory access operation when said access change command signal is in said second state. The memory access control circuit (52) as claimed in claim 1, characterized in that each of said storage areas includes a plurality of bits and said access request (27) further includes mask data (32) which specifies one or more bits of said plurality of bits of said selected storage area and modifying data (48) by which bit data (33) of one or more bits specified by said mask data (32) are replaced; said first memory access operation being a read-modify-write (RMW) operation in which data is read out from said selected storage area, said data is modified by use of said modifying data (48) to produce modified data and said modified data is written back to said selected storage area (53, 54); each storage area of said part of said storage areas of said memory (53, 54) having a write-per-bit access mode (WPB) in which, in response to mask information and replacement information supplied thereto, bit data (33) of one or more bits specified by mask information are replaced by said replacement information; and said access sequence control means performing said second memory access operation to supply said mask data (32) and said modifying data (48) to said memory (53, 54) as said mask information and said replacement information when said access change command signal is in said second state. A memory access control circuit (52) inserted between a data processing unit (CPU) and a memory (53, 54) having a plurality of storage areas, each of said storage areas having a plurality of bits, said memory access control unit (52) comprising: receiving means (4, 51) operatively coupled to said data processing unit (CPU) for receiving an access request (27) from said data processing unit (CPU), said access request (27) including (1) a memory address (30) which selects one of said storage areas of said memory (53, 54), (2) mask data (32) specifying one or more bits of said selected storage area, (3) modifying data (48) by which bit data (33) of said specified bits of said selected storage area are replaced, and (4) access mode designation information (26) which specifies a read-modify-write (RMW) access operation in which data is read out from said selected storage area, and in which the bit data (33) of the bits specified by said mask data (32) are replaced by said modifying data (48) to produce modified data, and said modified data is written back to said selected storage area; generation means (1) operatively coupled to said receiving means (4, 51) for generating control information (21, 22) which takes a first state when said mask data (32) does not specify at least one of the bits of said selected storage area and a second state when said mask data (32) specifies all the bits of said selected storage area of said memory (53, 54), and access sequence control means (4) operatively coupled to said receiving means (4, 51), said generation means (1) and said memory (53, 54) for performing said read-modify-write (RMW) access operation when said control information (21, 22) is in said first state and for performing, in place of said read-modify-write (RMW) access operation, a data write access operation to write said modifying data (48) directly into said selected storage area when said control information (21, 22) is in said second state. The memory access control circuit as claimed in claim 3, characterized in that control information (21, 22) generated by said generation means (1) further takes a third state when said mask data (32) specifies no bit of said selected storage area and said access sequence control means further performs no access to said selected storage area irrespective of said read-modify-write (RMW) access operation specified by said access mode designation information (26). A memory access control circuit (52) inserted between a data processing unit (CPU) and a memory (53, 54) having a plurality of storage areas, each of said storage areas having a plurality of bits, said memory access control circuit comprising; receiving means (4, 51) operatively coupled to said data processing unit (CPU) for receiving an access request (27) from said data processing unit (CPU), said access request (27) including a memory address (30) selecting one of said storage areas of said memory (53, 54), mask data (32) specifying one or more bits of said selected storage area of said memory (53, 54) for modifying data (48) by which said specified bits of said selected storage area are replaced, and a read-modify-write (RMW) access operation in which data is read out from said selected storage area and in which bit data (33) of said specified bits are replaced by said modifying data (48) to produce modified data, and said modified data is written back to said selected storage area; generation means (3, 9, 10) operatively coupled to said receiving means (4, 51) for generating control information (24, 25) which takes a first state when said memory address (30) selecting said storage area of said memory (53, 54) is not identical with a preceding memory address used in a preceding memory access operation and a second state when said memory address (30) selecting said storage area is identical with said preceding memory address, said generation means (3, 9, 10) including a data register (10) for temporarily storing data used in said preceding memory access operation; and access sequence control means (4) operatively coupled to said receiving means (4, 51), said generation means (3, 9, 10) and said memory (53, 54) for performing said read-modify-write (RMW) access operation where said control information ( 24, 25) is in said first state and for performing, irrespective of said read-modify-write (RMW) access operation being specified by said access request (27), a data write operation by use of said data stored in said data register (10) when said control information is in said second state.

Inventors: OHUCHI MITSUROU C O NEC CORPOR, OHUCHI, MITSUROU C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G06F13
IPC codes: G06T11, G06F12, G06T1, G09G5