Dynamic type random-access memory

Abstract: A dynamic type random-access memory includes a bit line pair constituted by first and second bit lines (BL, BL ), a memory cell array constituted by a plurality of memory cells (MC i : i = 0 to 255) connected to the bit line pair, a precharge circuit (PR) for precharging the bit line pair to a predetermined potential at a predetermined timing, a bit line sense amplifier (NA, PA) to be enabled after data written in one of the plurality of memory cells (MC i : i = 0 to 255) is read out to the bit line pair, and a charge transfer circuit (NT₁, NT₂) connected between the bit line pair and first and second sense nodes (SN, SN ) of the bit line sense amplifier (NA, PA), turned off upon reception of a charge transfer drive signal which is decreased from a power source potential to a medium potential between the power source potential and a ground potential when a small potential difference is produced between bit lines of the bit line pair, and having an impedance decreased as a potential difference between the bit line pair and the first and second sense nodes (SN, SN ) of the bit line sense amplifier (NA, PA) is increased when a potential difference between a control terminal and the first and second sense nodes (SN, SN ) exceeds a threshold value.

Description: The present invention relates to a dynamic type random-access memory having a charge transfer circuit between a bit line pair and a bit line sense amplifier. In a conventional large-capacity dynamic random-access memory (to be referred to as a DRAM hereinafter), as shown in Fig. 1, charge transfer transistors NT 1 and NT 2 comprising insulating gate type field effect transistors (MOS transistors) are connected between a pair of bit lines BL and BL and a bit line sense amplifier NA of each column so that the bit line sense amplifier can rapidly sense-amplify a potential difference produced in the bit line pair upon reading out of memory cell data. That is, referring to Fig. 1, reference symbols BL and BL denote first and second bit lines constituting a bit line pair of each column in a memory cell array of the DRAM; MC i (i = 0 to 255), a plurality of dynamic memory cells connected to each of the bit lines BL and BL ; DC 0 and DC 1 , dummy cells connected to the first and second bit lines BL and BL , respectively; WL i (i = 0 to 255), a word line connected to the gate of a charge transfer transistor TM of the memory cell MC i ; DWL 0 and DWL 1 , dummy word lines connected to the gates of charge transfer transistors TD of the dummy cells DC 0 and DC 1 , respectively; and TW 0 and TW 1 , dummy cell write transistors for writing dummy cell write voltage V DC in the dummy cells DC 0 and DC 1 , respectively. The transistors TW 0 and TW 1 are enabled by an equalize signal EQL . Reference symbol PR denotes a precharge/equalize circuit for precharging and equalizing the bit lines BL and BL to a precharge voltage V BL (set to be, e.g., 1/2 a power source voltage V CC ). The circuit PR is enabled by an equalize signal EQL (bit line precharge dummy cell write signal). Reference symbol PA denotes a bit line restore p-channel sense amplifier in which the drains of two p-channel transistors P 1 and P 2 having cross-connected gates and drains are connected to the bit lines BL and BL , respectively, and which is enabled by a p-channel sense amplifier enable signal SAP; and NA, an n-channel sense amplifier in which the drains (a pair of sense nodes SN and SN ) of two n-channel transistors N 1 and N 2 having cross-connected gates and drains are connected to the other terminals of the charge transfer transistors NT 1 and NT 2 , respectively, and which is enabled by an n-channel sense amplifier enable signal SAN . The charge transfer transistors NT 1 and NT 2 are so controlled as to be kept OFF for a predetermined time period immediately before the n-channel sense amplifier NA is enabled when the gates of the transistors NT 1 and NT 2 receive a drive signal  T from a charge transfer transistor driver (not shown). The pair of sense nodes SN and SN of the n-channel sense amplifier NA are connected to a pair of column selection transistors CT 1 and CT 2 , respectively. The pair of column selection transistors CT 1 and CT 2 are connected to a pair of data buses DL 1 and DL 2 via a pair of data lines DQ 1 and DQ 2 connected in common to a plurality of columns, respectively, and a data buffer DQB. A conventional operation of the DRAM having the above arrangement will be described below with reference to waveforms shown in Fig. 2. Assuming that data indicating a potential of 0 V ("L" level) is written in a memory cell MC 1 connected to one bit line of the bit line pair, e.g., the bit line BL, read and rewrite operations performed for the memory cell MC 1 will be described. Since this DRAM has a V CC potential of, e.g., 5 V and adopts a driving system for precharging the bit line pair to a voltage of V BL = V CC /2, the first and second bit lines BL and BL are equally kept at V CC /2 before a word line is selected. Row and column addresses are sequentially input as address inputs, and a row address strobe signal RAS is enabled after the row address is input, thereby decoding the row address. A word line WL 1 at the bit line BL side is selected to turn on the charge transfer transistor TM of the selected memory cell MC 1 , and the data of 0 V ("L" level) is read out from a capacitor C 1 of the memory cell MC 1 . Therefore, a potential of the first bit line BL is slightly reduced from V CC /2. At the same time the word line WL 1 at the first bit line BL side is selected, the dummy word line DWL 0 at the second bit line BL side is selected to turn on the charge transfer transistor TD of the dummy cell DC 0 . In this case, a potential of V DC (e.g., V CC /2) is prewritten in the dummy cell DC 0 . Therefore, even if the charge transfer transistor TD is turned on to short-circuit a capacitor C 0 and the second bit line BL , a potential of the second bit line BL is kept at V CC /2 because the capacitor C 0 and the second bit line BL are at the same potential. Thereafter, when a small potential difference is produced between the potentials of the first and second bit lines BL and BL , the signal T goes to a potential V SS , the charge transfer transistors NT 1 and NT 2 are turned off, and the bit lines BL and BL are disconnected from the bit line sense amplifier NA. A signal SAN goes to the ground potential V SS to enable the n-channel sense amplifier NA, and a signal SAP goes to the potential V CC to enable the p-channel sense amplifier PA. As a result, a small potential difference between the pair of sense nodes SN and SN of the sense amplifier NA is sense-amplified, and a potential of the sense node SN is reduced to 0 V. In addition, the potential of the bit line BL is increased to the potential V CC by the p-channel sense amplifier PA. Thereafter, a column address strobe signal CAS is enabled to decode the column address, and the pair of column selection transistors CT 1 and CT 2 are turned on by a column decode signal CSL i . When the transistors CT 1 and CT 2 are turned on, the potentials of the sense nodes SN and SN of the sense amplifier NA are reamplified by the data buffer DQB and output to the pair of data buses DL 1 and DL 2 via the pair of data lines DQ 1 and DQ 2 , respectively. When the signal  T returns to the potential V CC to turn on the charge transfer transistors NT 1 and NT 2 , the bit lines BL and BL are connected to the sense nodes SN and SN of the bit line sense amplifier NA. The potential of the first bit line BL is reduced to 0 V, and that of the second sense node SN is increased to the potential V CC (e.g., 5 V). Therefore, data of "L" level and that of "H" level are rewritten in the selection memory cell MC 1 and the dummy cell DC 0 , respectively. Thereafter, the word line WL 1 and the dummy word line DWL 0 return to a nonselection state. After the above rewrite operation is completed, the bit line precharge dummy cell write signal EQL goes to the potential V CC , the bit line BL and BL are precharged to the voltage V BL , and the dummy cells DC 0 and DC 1 are precharged to the voltage V DC . In the above DRAM, since the capacitances of the bit lines BL and BL are completely disconnected from the pair of sense nodes SN and SN during an operation of the sense amplifier NA, loads on the sense nodes SN and SN are reduced to increase a speed of sense amplification. Therefore, an access time t ACC from a fall timing of the signal RAS to an output timing of readout data can be shortened. In the above operation of the DRAM, however, when the charge transfer transistors NT 1 and NT 2 return from an OFF to ON state, a large amount of charges simultaneously flow from the first bit line BL to be reduced to the "L" level side to the sense node SN of the sense amplifier NA, and the potential of the sense node SN is abruptly increased. In this state, a current driving power of the sense amplifier NA is reduced. Therefore, if the column selection transistors CT 1 and CT 2 are turned on in this state, a speed of extracting charges from the data line DQ 1 (precharged to, e.g., the potential V CC ) connected to the sense node SN may be decreased to disable reamplification in the data buffer DQB. That is, if a time t RAD from an enable timing (in this case, a fall timing) of the signal RAS to an input timing of a column address is shorter or longer than a predetermined range, the potential of the sense node SN of the sense amplifier NA has almost no increase when the column selection transistors CT 1 and CT 2 are turned on after the column address is input. Therefore, reamplification can be correctly performed in the data buffer DQB. If, however, the time t RAD from the enable timing of the signal RAS to the input timing of the column address falls within the predetermined range, the potential of the sense node SN of the sense amplifier is increased as described above when the column selection transistors CT 1 and CT 2 are turned on after the column address is input. Therefore, reamplification cannot be correctly performed in the data buffer DQB to cause a read error. In the DRAM having the above arrangement, therefore, a read error is caused when the time t RAD from the enable timing of the signal RAS to the input timing of the column address falls within a predetermined range. IEE Journal of Solid-state circuits Vo. SC-13 No. 5, October 1978 p607-610, Wada et al shows a DRAM with a charge transfer circuit with a charge transfer drive signal activated in response to a sense activation signal. When activated, a bit line with a higher potential is disconnected from sense nodes on the device. US-A-4 112 512 shows a DRAM with bit line switches, one of which will become conductive according to storage cell content. US-A-4 061 954 shows another DRAM with bit line switches driven to have variable impedance to the sense nodes. EP-A-0 187 246 shows the features of the preamble of claim 1. It is an object of the present invention to provide a dynamic type random-access memory in which a short access time t ACC is maintained and no read error is caused even when the time t RAD from an enable timing of the signal RAS to an input timing of a column address is shorter or longer than or falls within a predetermined range. According to the present invention, there is provided a dynamic type random-access memory as set out in claim 1. When read and rewrite operations are to be performed for a memory cell which is connected to the first bit line and in which a potential or 0 V is written, for example, both the first and second bit lines are equally kept at a bit line precharge voltage from an enable timing of a signal RAS to a selection timing of a specific word line. When the word line is selected, 0 V of the selected memory cell is read out, and the potential of the first bit line is slightly decreased from the precharge voltage. When a small potential difference is produced between the potentials of the first and second lines in this manner, the charge transfer circuit is turned off, and the bit line pair is disconnected from the bit line sense amplifier. The bit line sense amplifier is enabled to sense-amplify the small potential difference between the potentials of the first and second bit lines, and the potential of the first sense node is decreased to 0 V. In this case, if a potential difference between the first sense node and the third node of the charge transfer circuit becomes larger than a threshold value of the charge transfer circuit, an impedance of the charge transfer circuit is gradually decreased in accordance with the potential difference between the two terminals, and the potential of the first bit line is gradually decreased to 0 V. Therefore, a large amount of charges do not simultaneously flow from the first bit line to the first sense node, and the potential of the first sense node is not abruptly increased. After the potential of the first bit line is rewritten in the selected memory cell, the word line is returned to a nonselection state. Note that the charge transfer circuit is returned to an ON state before or after the rewrite operation is finished. In addition, a bit line precharge signal is enabled to precharge the bit line pair. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram for explaining operations of a conventional dynamic type random-access memory and a dynamic type random-access memory according to the present invention; Fig. 2 is a timing chart showing waveforms for explaining an operation of the conventional dynamic type random-access memory shown in Fig. 1; Figs. 3 and 4 are circuit diagrams showing a circuit for generating an n-channel sense amplifier enable signal SAN ; Fig. 5 is a circuit diagram showing a circuit for receiving a signal PHI generated by the circuit shown in Figs. 3 and 4 and generating a charge transfer transistor drive signal  T ; Figs. 6 to 9 are circuit diagrams showing modifications of an output portion A shown in Fig. 5, respectively; Fig. 10 is a timing chart showing waveforms for explaining an operation of a dynamic type random-access memory according to the present invention; Fig. 11 is a circuit diagram showing a modification of the dynamic type random-access memory according to the present invention; Fig. 12 is a timing charge showing waveforms for explaining an operation of the random-access memory shown in Fig. 11; and Figs. 13A and 13B are circuit diagrams showing modifications of a charge transfer circuit. An embodiment of the present invention will be described below with reference to the accompanying drawings. Fig. 1 shows an embodiment of a DRAM of the present invention. A circuit arrangement of the DRAM of this embodiment is the same as that of the conventional DRAM of a charge transfer transistor driving system as described above with reference to Fig. 2 except that a driving potential level of a charge transfer transistor drive signal  T of this DRAM is different from that of the conventional DRAM, and a detailed description thereof will be omitted. Figs. 3 and 4 are circuit diagrams showing a circuit for generating an n-channel sense amplifier enable signal SAN , and Fig. 5 is a circuit diagram showing a circuit for receiving a signal PHI generated by the circuit shown in Figs. 3 and 4 and generating a charge transfer transistor drive signal  T . Figs. 6 to 9 show modifications of an output portion A shown in Fig. 5. That is, the level of the charge transfer transistor drive signal  T is decreased not to a V SS potential (0 V) but to a medium potential VM when charge transfer transistors NT 1 and NT 2 are to be turned off and is increased to a potential V CC when the transistors NT 1 and NT 2 are to be turned on. Assuming that a bit line precharge potential is V BL and a threshold potential of the transistors NT 1 and NT 2 is V TN , the medium potential V M satisfies V TM ≦ V M ≦ V BL + V TN and is set to be, e.g., V CC /2 = 2.5 V. An operation of the above DRAM will be described below with reference to waveforms shown in Fig. 10. Assuming that data indicating a potential of 0 V ("L" level) is written in a memory cell MC 1 connected to one of bit lines, e.g., a first bit line BL, read and rewrite operations performed for the memory cell MC 1 will be described. Since this DRAM adopts a system of precharging the bit line pair to a voltage represented by V BL = V CC /2 = 2.5 V, both of the first and second bit lines BL and BL are equally kept at 2.5 V before a word line is selected. Row and column addresses are sequentially input as address inputs, and a row address strobe signal RAS is enabled after the row address is input, thereby decoding the row address. A word line WL 1 at the bit line BL side is selected to turn on the charge transfer transistor TM of the selected memory cell MC 1 , and the data of 0 V ("L" level) is read out from a capacitor C 1 of the memory cell MC 1 . Therefore, a potential of the first bit line BL is slightly reduced from V CC /2. At the same time the word line WL 1 at the first bit line BL side is selected, the dummy word line DWL 0 at the second bit line BL side is selected to turn on the charge transfer transistor TD of the dummy cell DC 0 . In this case, a potential of V DC (e.g., V CC /2) is prewritten in the dummy cell DC 0 . Therefore, even if the charge transfer transistor TD is turned on to short-circuit a capacitor C 0 and the second bit line BL , a potential of the second bit line BL is kept at V CC /2 because the capacitor C 0 and the second bit line BL are at the same potential. Thereafter, when a small potential difference is produced between the potentials of the first and second bit lines BL and BL , the signal  T goes to the medium potential V M , the charge transfer transistors NT 1 and NT 2 are turned off, and the bit lines BL and BL are disconnected from the bit line sense amplifier NA. A signal SAN goes to the ground potential V SS to enable the n-channel sense amplifier NA, and a signal SAP goes to the potential V CC to enable the p-channel sense amplifier PA. As a result, a small potential difference between the pair of sense nodes SN and SN of the sense amplifier NA is sense-amplified, and a potential of the sense node SN is reduced to 0 V. In addition, the potential of the bit line BL is increased to the potential V CC side by the p-channel sense amplifier PA. When the potential of the first sense node SN is decreased to be smaller than (V CC /2) - V TN (i.e., the potential difference between the potential of the first sense node SN and the level of the signal  T is increased to be larger than V TN ), an impedance of the charge transfer transistor NT 1 is gradually decreased in accordance with the potential difference between the two terminals. Therefore, the n-channel sense amplifier NA starts reducing the charge of the first bit line BL, and the potential of the first bit line BL is decreased. As a result, the charge of the first bit line BL starts flowing into the first sense node SN to abruptly reduce a potential decrease speed of the first sense node SN. After a time ta, the potentials of the first sense node SN and the first bit line BL are gradually reduced to be close to each other and finally reach 0 V. Therefore, the potential of the first bit line is rewritten in the selected memory cell MC 1 , and the potential of the second bit line BL is rewritten in the dummy cell DC 0 . After the time ta, a signal CAS is enabled to decode the column address, and the column selection transistors CT 1 and CT 2 are turned by a column decode signal CSL i . As a result, the potentials of the pair of sense nodes SN and SN of the n-channel sense amplifier NA are reamplified by the data buffer DQB via the data lines DQ 1 and DQ 2 and output from a pair of data buses DL 1 and DL 2 , respectively. Before (or after) the above rewrite operation is finished, the signal  T is returned to the potential V CC to turn on the charge transfer transistors NT 1 and NT 2 . When the transistor NT 1 is turned on, potential redistribution is abruptly performed between the first sense node SN and the first bit line BL, and the potential of the first sense node SN having a smaller capacitance is slightly increased. Since, however, the potentials of the first sense node SN and the first bit line BL are already close to each other, the potential of the first sense node SN is not so abruptly, largely increased. After the rewrite operation is finished as described above, the word line WL 1 and the dummy word line DWL 0 return to a nonselection state. Thereafter, a bit line precharge dummy cell write signal EQL goes to the potential V CC to precharge the bit lines BL and BL to V BL and dummy cells DC 0 and DC 1 to a potential V DC . In the above read operation of the DRAM, the capacitances of the bit lines BL and BL are completely disconnected upon the sense operation performed by the n-channel sense amplifier NA. Therefore, loads on the sense nodes SN and SN are reduced to increase a speed of sense amplification. In addition, at the time ta at which the charge of the first bit line BL starts flowing into the first sense node SN to rapidly reduce the potential decrease speed of the first sense node SN, the potential difference between the pair of sense nodes SN and SN is larger than V TN . Therefore, even if the column selection transistors CT 1 and CT 2 are turned on in this state, the potential difference between the sense nodes SN and SN is large enough to be reamplified by the data buffer DQB via the data lines DQ and DQ , respectively, thereby realizing high-speed access. Even if the column selection transistors CT 1 and CT 2 are turned on at a time tb at which the potential of the first sense node SN is slightly increased, the power of the n-channel sense amplifier NA is not reduced. Therefore, the charge of the data line DQ 1 can be extracted at a satisfactorily high speed to eliminate an erroneous operation caused by the data buffer DQB. According to the above DRAM, therefore, even if a time t RAD from an enable timing of the signal RAS to an input timing of a column address is shorter or longer than or falls within a predetermined range, the potentials of the sense nodes SN and SN of the n-channel sense amplifier NA have almost no increase when the signal CAS is enabled after the column address is input. Therefore, the data buffer DQB can correctly perform reamplification. In the above embodiment, the potentials are set to satisfy the relation of V TN ≦ V M ≦ V BL + V TN . The same effects as those of the above embodiment, however, can be obtained by turning off the charge transfer transistors NT 1 and NT 2 in an initial stage of the sense operation by the sense amplifier NA and turning on the transistors NT 1 and NT 2 before the sense amplifier NA completes the sense operation. Therefore, assuming that a voltage required to turn on the column selection transistors CT 1 and CT 2 to allow the data buffer DQB to perform the sense operation is α and a potential at which the sense node SN or SN starts decreasing the charge of the bit line BL or BL , respectively, is β, a relation of V TN + β ≦ V M ≦ V BL + V TN - α need only be set. Fig. 11 shows a part of a DRAM according to another embodiment of the present invention. This embodiment is the same as the above embodiment except that the positions of an n-channel sense amplifier NA and a p-channel sense amplifier PA are switched, p-channel charge transfer transistors PT 1 and PT 2 are used in place of the n-channel charge transfer transistors NT 1 and NT 2 , and a logic level of a charge transfer transistor drive signal  T is inverted. Therefore, in Fig. 11, the same reference numerals as in Fig. 1 denote the same parts. The level of the charge transfer transistor drive signal  T is increased not to a potential V CC but to a medium potential V M when the charge transfer transistors PT 1 and PT 2 are to be turned off and is decreased to a potential V SS when the transistors PT 1 and PT 2 are to be turned on. Assuming that a bit line precharge potential is V BL and a threshold voltage of the p-channel charge transfer transistors PT 1 and PT 2 is V TP , the medium potential V M satisfies a relation of V BL - |V TP | ≦ V M ≦ V CC - |V TP |. An operation of the DRAM shown in Fig. 11 is similar to that of the above embodiment and performed as shown in the timing chart of Fig. 12 to obtain the same effects as those of the above embodiment. That is, at a time ta at which a charge starts flowing from the second sense node SN to the second bit line BL to abruptly reduce a potential increase speed of the second sense node SN, a potential difference between a pair of sense nodes SN and SN is larger than |VTP|. Therefore, even if column selection transistors CT 1 and CT 2 are turned on in this state, the potential difference between the sense nodes SN and SN is large enough to be reamplified by a data buffer DQB via data lines DQ 1 and DQ 2 , respectively, thereby realizing high-speed access. When the charge transfer transistor PT 2 is turned on, charge redistribution is abruptly performed between the second sense node SN and the second bit line BL , and the potential of the second sense node SN having a smaller capacitance is slightly decreased. Even if the column selection transistors CT 1 and CT 2 are turned on at a time tb at which the potential of the node SN is decreased, a decrease in amplification power of the p-channel sense amplifier PA is small enough to eliminate an erroneous operation caused by the data buffer DQB. In the above embodiment shown in Fig. 11, the potentials satisfy the relation of V BL - |V T p| ≦ V M ≦ V CC - |V T p|. The same effects as those of the above embodiment, however, can be obtained by turning off the charge transfer transistors PT 1 and PT 2 in an initial stage of the sense operation performed by the sense amplifier PA and turning on the transistors PT 1 and PT 2 before the sense amplifier PA completes the sense operation. Therefore, assuming that a voltage required to turn on the column selection transistors CT 1 and CT 2 to allow the data buffer DQB to perform the sense operation is α and a charge at which the sense node SN or SN starts decreasing the charge of the bit line BL or BL , respectively, is β, a relation of V BL - |V TP | + α ≦ V M ≦ V CC - |V TP | - β need only be set. In the above embodiment shown in Fig. 1 or 11, not only the charge transfer transistors NT 1 and NT 2 or PT 1 and PT 2 but also another charge transfer circuit having characteristics equal to those of the charge transfer transistor can be connected between the pair of bit lines BL and BL and the pair of sense nodes SN and SN . That is, in this charge transfer circuit, similar to the above charge transfer transistor, an element, having an impedance which changes in accordance with a potential difference between two terminals and being turned off in accordance with a potential difference between a third terminal and one of the two terminals, is connected between a terminal at a bit line side and a terminal at a bit line sense amplifier side, and is temporarily turned off when a small potential difference is produced between the bit lines BL and BL . This element is turned off in an initial stage of enabling of the bit line sense amplifier to disconnect the sense nodes SN and SN from the bit lines BL and BL . When a potential difference of a predetermined value or more is obtained between the sense nodes SN and SN , the impedance of the element is gradually decreased to slowly, naturally connect the sense nodes to the bit lines. Therefore, the speed of the sense operation can be increased, and a temporary reduction in potential difference between the sense nodes SN and SN caused when the charge transfer circuit is turned on can be prevented. Figs. 13A and 13B show modifications of the above charge transfer circuit. Referring to Figs. 13A and 13B, a diode D consisting of a bipolar npn transistor in which a collector and a base are connected is connected between two terminals. This diode D is connected in parallel with a switch circuit S, and the switch circuit S is switching-controlled. In this charge transfer circuit, when the switch circuit S is turned off in an initial stage of enabling of the bit line sense amplifier, the diode D is turned off. When a potential difference of a predetermined value or more is produced between the sense nodes SN and SN , an impedance of the diode D is gradually decreased, and the switch circuit S is turned on when the bit lines BL and BL are connected to the sense nodes SN and SN , respectively. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A dynamic type random-access memory comprising: a bit line pair constituted by first and second bit lines (BL, BL ); a memory cell array constituted by a plurality of memory cells (HCi: i = 0 to 255), each being connected to said bit line pair; a precharge circuit (PR) for precharging said bit line pair to a predetermined potential, which is a half of said power source voltage (Vcc) wherein said precharge circuit (PR) precharges said bit line pair to said predetermined potential, upon receipt of an equalise signal (EQL) prior to a selection of a word line (WL); a first sense amplifier circuit (NA) having a sense node pair constituted by first and second sense nodes (SN, SN ), which amplifies a potential difference at said sense node pair; a pair of first and second charge transfer transistors (NT1, NT2), said first charge transfer transistor (NT1) being located between said first bit line (BL) and said first sense node (SN) of said first sense amplifier circuit (NA) and said second charge transfer transistor (NT2) being located between said second bit line ( BL ) and said second sense node ( SN ) of said sense amplifier circuit (NA); and a pair of first and second data lines (DQ1, DQ2) connected to a data buffer circuit (DQB); and characterised by a pair of first and second column selector transistors (CT1, C12), said first column selector transistor (CT1) located between said first sense node (SN) of said first sense amplifier circuit (NA) and said data line (DQ1) and said second column selector transistor (CT2) being located between said second sense node (SN) of said first sense amplifier circuit (NA) and said second data line (DQ2), said column selector transistors (CT1, CT2) being controlled by a column decode signal (CSL1); wherein said first and second charge transfer transistors (NT1, NT2) are controlled by a charge transfer transistor drive signal  T in a following manner, which has first, second and third potentials; a) said first potential is applied to gate electrodes of said first and second charge transfer transistors (NT1, NT2) at a first stage of a sense operation of said first sense amplifier circuit (NA) so as to make said charge transfer transistors (NT1, NT2) conductive until an initial difference between the potentials of the bit lines is detected, then the charge transfer transistors are turned off; b) said second potential (VM), having an intermediate level between a power source voltage (Vcc) and a ground source voltage (Vss), is applied to said gates of first and second charge transfer transistors (NT1, NT2) at a second stage of said sense operation of said first sense amplifier circuit (NA) so as to decrease impedances of said first and second charge transfer transistors (NT1, NT2); and c) said third potential having the same level as that of said first potential is applied to said gates of said first and second charge transfer transistors (NT1, NT2) at a third stage of said sense operation of said first sense amplifier circuit (NA) so as to make said first and second charge transfer transistors (NT1, NT2) conductive, when the potentials of the bit line with the lower potential and the corresponding sense node are substantial equal. The memory according to claim 1 further comprising: a second sense amplifier circuit (PA) having and second sense nodes the first sense node of which is connected to said first bit line (BL) and the second sense node of which is connected to said second bit line (BL). The memory according to claim 1 wherein said second potential (VH) having the intermediate level is a half of said power source voltage (Vcc). The memory according to claim 3, wherein said second potential (VH) having the intermediate level satisfies a following inequality: V BL - V TH ≤ Vcc - V TH where V BL is a bit line precharge potential, V TH is a threshold voltage of said charge transfer transistors (KT1, KT2), and Vcc is said power source voltage. The memory according to claim 1, wherein said first sense amplifier circuit (NA) comprises first and second n-channel MOS transistors (N1, N2) having gates cross-coupled to said first ad second bit lines (BL, BL). The memory according to claim 2, wherein said second sense amplifier circuit (PA) comprises first and second p-channel MOS transistors (P1, P2) having gates cross-coupled to said first and second bit lines (BL, BL). The memory according to claim 1, wherein said precharge circuit (PR) comprises three MOS transistors, two of them being connected in series between said bit line pair, the remaining one being located between said bit line pair, and the gates of them being commonly connected to receive said equalise signal. The memory according to claim 1, wherein said charge transistor drive signal  T is generated by a circuit which comprises: an input terminal for receiving a first signal outputted after a word line drive signal is outputted; a first inverter for receiving said first signal and outputting said signal in an inverted form; an NOR circuit having two input terminals, one inputting said inverted signal and the other thereof inputting said signal in a non-inverted form with delay; and a second inverter for receiving a second signal and outputting the second signal in an inverted form to said charge transfer transistors (NT1, NT2). The memory according to claim 1, characterised in that each of said first and second charge transfer transistors comprises a bipolar transistor having a collector and a base which are connected to each other to form a diode (D), and a switch circuit (S) is connected in parallel to said diode (D). The memory according to claim 9, characterised in that said bipolar transistor is a pnp transistor. The memory according to claim 9, characterised in that said bipolar transistor is an npn transistor.

Inventors: OHSAWA TAKASHI, OHSAWA, TAKASHI, OHSAWA, TAKASHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G11C11
IPC codes: G11C11