High efficiency coding apparatus

Abstract: A highly efficient coding apparatus, for coding digital video data in a block format allowing video data compression for transmission using a data transmitter having a predetermined transmission capacity, includes a first detector for detecting a maximum value of the digital video data of plural picture elements in a block; a second detector for detecting a minimum value of the digital video data of plural picture elements in the same block; a first averaging circuit (12) for averaging the digital video data having a value between the maximum value and a first value which is a first predetermined level lower than the maximum value, and for generating a modified maximum value; a second averaging circuit (13) for averaging the digital video data having a value between the minimum value and a second value which is a second predetermined level higher than the minimum value, and for generating a modified minimum value; a subtracter (16) for subtracting the modified minimum value from the digital video data for each of the picture elements to generate modified digital video data; a circuit (15) for generating modified dynamic range information from the modified maximum and minimum values; a bit number deciding circuit (19) for determining an encoding bit number for each block during a predetermined period from the predetermined transmission capacity of the data transmitter; an edge-match encoder for encoding the modified digital video data with the encoding bit number; and a transmission circuit for transmitting an output of the encoder, a first additional code for each block formed of at least two of the modified maximum and minimum values and a signal based on the modified dynamic range information and a second additional code for each predetermined period referred to above.

Description: This invention relates to a highly efficient coding apparatus and, more particularly, relates to a highly efficient coding apparatus for compressing the number of bits required to represent each picture element of picture data of a digital television signal or the like. Among various types of video signal coding methods, there are known some highly efficient coding methods which adapted to diminish the average bit number or sampling frequency of each picture element for the purposes of narrowing the required transmission bandwidth. The present applicant has proposed a highly efficient coding apparatus for obtaining dynamic range determined by maximum and minimum values of plural picture elements contained in a two-dimentional block and for performing a coding adaptive to the dynamic range, as described in Japanese Patent Laid Open Publication JP-A-61144989. Further, Japanese Patent Laid Open Publication JP-A-6292620 discloses a highly efficient coding apparatus for a coding technique which is adaptive to a dynamic range with respect to a three-dimensional block formed of picture elements of areas respectively contained in plural frames has been proposed. Moreover, Japanese patent laid open publication JP-A-62128621 discloses a variable-length coding method for varying the bit number depending on dynamic range so as to keep the maximum distortion occurring at the time of quantisation constant. Figure 1 of the accompanying drawings illustrates a coding method adaptive to the dynamic range of the video signal which has already been proposed and is known as ADRC. The dynamic range DR (difference between a maximum value MAX and a minimum value MIN) is calculated for every two-dimensional block formed of, for example, (8 lines x 8 pixels = 64 pixels). The minimum level (minimum value) is removed by subtraction from input pixel data in the block. The pixel data after removal of the minimum value is converted into a representative level. This quantization is a processing for dividing the detected dynamic range DR into four level ranges A0 to A3 corresponding to e.g. two bits which is a bit number less than the original quantization bit number, for subsequently detecting a level range encompassing each of pixel data in the block, and for generating a code signal indicative of the level range. In Fig. 1, the dynamic range DR of' the block is divided into four level ranges A0 to A3. Pixel data contained in the minimum level range A0 are coded into (00), the pixel data contained in the level range A1 is coded into (01), the pixel data contained in the level range A2 is coded into (10), the pixel data contained in the maximum level range A3 is coded into (11). Therefore, data of 8 bits of each picture element is transmitted in a form in which it is compressed into 2 bits. In the receiver, a received code signal is decoded into representative levels L0 to L3 which are center levels of the level ranges A0 to A3, respectively. The coding method adaptive to the dynamic range, referred to above, involves a problem that block distortion can arise because of a ringing or an impulsive noise. Figure 2 illustrates the occurrence of block distortion. In Fig. 2, for purposes of simplifying the explanation, variation in data in respect of a one-dimensional block, i.e., a block formed of a predetermined number of samples in a horizontal direction, is shown as an analog waveform, and decoded values on the part of the receiver are shown by a broken line. A low-level ringing is often produced in a picture output of a video camera near an edge where the level is changed abruptly, as shown in Fig. 2. In a block including such ringing, a peak value of the ringing is detected as a maximum value MAX1, and coding is carried out adaptively to a dynamic range DR1 determined by the maximum value MAX1, and a minimum value MIN1. In a subsequent block, occurring after the ringing has died down, the maximum value is decreased as shown at MAX2, the coding is effected adaptively to a dynamic range DR2 determined by a minimum value MIN2 and the maximum value MAX2. Therefore, a difference in luminance level is produced between these two blocks and this causes block distortion. Also in the case of an impulsive noise, block distortion occurs for the same reason. The difference in luminance level causing the block distortion is small but occupies a certain area of the image which is visually noticeable. In order to overcome the problem of a block distortion caused by ringing or impulsive noise, the present applicant has proposed a system for performing preliminary processing of input data converted into a block structure, as described in the Japanese Patent Laid Open Publication JP-A-6359187. More specifically, by detecting an average value MAX′ of values of input data contained in a maximum level range (A3 in Fig. 1) at the time of equally dividing a dynamic range by a quantizing bit number of the ADRC and also detecting an average value MIN′ of input data contained in a minimum level range (A0 in Fig. 1), quantization is carried out so as to convert the average value MAX' and the minimum value MIN′ into detected levels L3 and L0, respectively, as shown in Fig. 3. The quantization shown in Fig. 1 in which the represetative levels L0 to L3 do not include the maximum value MAX and the minimum value MIN but indicate center values in respective level ranges, is called a non-edge matching. In contrast, the quantization shown in Fig. 3 in which they include the average values MAX′ and MIN′, is called an edge matching. According to the ADRC for first performing the preliminary non-edge matching processing and for subsequently performing the edge matching quantization, the maximum value is converted into the average value MAX′ and not into the peak of a ringing signal either in a block including the ringing shown in Fig. 2. Similarly, the minimum value is converted into MIN′. Since the edge matching quantization is carried out in the concealed dynamic range DR′ determined by the values MAX′ and MIN′, the difference between a decoded level of a specific block and a decoded level of an adjacent block is reduced, and generation of a block distortion is prevented. Since the above-described ADRC coding adaptive to dynamic range can significantly compress the amount of data to be transmitted, it is suitable for use in a digital VTR. In particular, variable-length ADRC can increase the compression rate. However, since the variable-length ADRC produces an amount of data to be transmitted which varies with the contents of the picture, buffering processing is required when using a transmission path of a fixed rate such as digital VTR configured to record a predetermined amount of data as one track. As a buffering system of a variable-length ADRC, the present applicant has proposed a system disclosed in Japanese Patent Laid Open Publication JP-A-63111781. In this system, an integrating type frequency distribution table of dynamic ranges is formed and by using for the frequency distribution table a threshold value preliminarily prepared for determining an assigned bit number, the generated information amount in a predetermined period such as one frame period is obtained, so that the generated information amount does not exceed a target value. When using a variable-length ADRC in the above-mentioned ADRC for performing the preliminary processing using the non-edge matching quantization and subsequently performing the edge matching quantization, a problem is caused by mismatching between the encoder and the decoder because, while the assigned bit number is established based on an original dynamic range DR, a different dynamic range DR′ is transmitted to the receiver side. More specifically, in order to control the generated information amount, a frequency distribution table of a predetermined period, e.g., one frame period, of dynamic ranges DR is made, and the frequency distribution table is converted into an integrating type frequency distribution table to which threshold values T1, T2, T3 and T4 (T1 < T2 < T3 < T4) are adapted. In case of (DR < T1), the assigned bit number n is set at 0 (this means that no code signal is transmitted). In case of (T1 ≦ DR < T2), it is set at (n = 1). In case of (T2 ≦ DR < T3), it is set at (n = 2). In case of (T3 ≦ DR < T4), it is set at (n = 3). In case of (T4 ≦ DR), it is set at (n = 4). As described above, under the relationship of (MAX′ - MIN′ = DR′), quantization is performed based on the concealed dynamic range DR′, and the dynamic range DR′ is transmitted. If the relationships (T2 ≦ DR < T3) and (T2 ≦ DR′ < T3) are established regarding the dynamic range of a certain block, the bit number (n = 2) set on the part of the encoder also exhibits (n = 2) on the part of the decoder, and no problem occurs. However, since the relationship of (DR > DR′ ) exists, the decoder may erroneously regard it as being (n = 1) in case of (T1 ≤ DR' < T2), and this causes a problem that a proper decoding operation is not effected. It is, therefore, an object of the invention to provide a highly efficient coding apparatus which reduces or avoids mismatching between encoder and decoder sides caused by a difference between an original dynamic range DR and a conceals dynamic range DR'. According to the present invention, there is provided a coding apparatus for coding digital video data in a block format allowing video data compression for transmission by data transmission means having a predetermined transmission capacity, comprising: detecting means for detecting a maximum and a minimum value of the digital video data of plural picture elements in a block; first averaging means for averaging the digital video data having a value between said maximum value and a first value which is a first predetermined level lower than said maximum value, said first averaging means generating a modified maximum value; second averaging means for averaging the digital video data having a value between said minimum value and a second value which is a second predetermined level higher than said minimum value said second averaging means generating a modified minimum value; means for subtracting said modified minimum value from the digital video data for each of said picture elements to generate modified digital video data; means for generating modified dynamic range information from said modified maximum and minimum values; edge-match encoding means for encoding said modified digital video data with an encoding bit number; and means for transmitting an output of said encoding means and a first additional code for each block, formed of at least two of said modified maximum and minimum values and a signal based on said modified dynamic range information; characterised by: means for determining, with reference to said predetermined transmission capacity of said data transmission means, said encoding bit number for each block during a predetermined period said means for determining including means for generating original dynamic range information from said maximum and minimum values, and setting means for setting a threshold value for determining a boundary of plural bit numbers; and in that said means for transmitting includes comparator means (23) for comparing said original and modified dynamic range informations (DR, DR') and said threshold value (Ti) and for generating a flag code (F) for each block and means for transmitting said flag. The invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which:- Figs. 1, 2 and 3 are schematic diagrams for describing example of quantization for explaining prior art highly efficient coding apparatus, respectively; Fig. 4 is a block diagram of one embodiment of this invention; Fig. 5 is a schematic diagram for describing a block used as a unit of process for encoding; Fig. 6 is a block diagram showing a structure on the reception side corresponding to the transmitter shown in Fig. 4; Fig. 7 is a block diagram showing buffering circuit 21 of Fig. 4; Fig. 8 is a flow chart for use in explaining the operation of the buffering circuit 21 of Fig. 4; Figs. 9A and 9B are schematic diagrams showing distribution tables of dynamic range information; Fig. 10 is a block diagram of a second embodiment of the invention; Fig. 11 is a block diagram showing a construction on a reception side corresponding to the transmitter shown in Fig. 10; Figs. 12 and 13 are block diagrams of third and fourth embodiments of this invention, respectively; Fig. 14 is a block diagram of a fifth embodiment of this invention; Figs. 15A, 15B, 15C and 15D are schematic diagrams for describing examples of quantization used in the embodiment of Fig. 14; and Figs. 16A, 16B, 16C, 16D and 16E are shcematic diagrams showing distribution tables of dynamic range information. Some preferred embodiments are described below, referring to the drawings. Fig. 4 shows a general structure on the part of the transmitter (recording side) in a first embodiment of the invention. A digital video signal (digital luminance signal) in which one sample is quantized with eight bits, for example, is entered in an input terminal shown at 1. The digital video signal is given to a block segmentation circuit 2. In the block segmentation circuit 2, the input digital video signal is converted into successive signals for each two-dimentional block which is the unit of coding. In this embodiment, one block is as large as (8 lines × 8 pixels = 64 pixels) as shown in Fig. 5. An output signal of the block segmentation circuit 2 is supplied to a maximum/minimum value detector circuit 3 and a delay circuit 4. The maximum/minimum value detector 3 detects a minimum value MIN and a maximum value MAX of each block. The delay circuit 4 delays the input data by a time required for detecting the maximum value and the minimum value. Pixel data from the delay circuit 4 are supplied to a comparator circuits 5 and 6. The maximum value MAX from the maximum/minimum value detector 3 is fed to a subtracter circuit 7, and the minimum value MIN is supplied to an adder circuit 8. A value Δ of one quantization step width at the time of variable-length non-edge matching quantization is supplied from a bit shift circuit 9 to the subtracter 7 and the adder 8. The bit shift circuit 9 is configured to shift a dynamic range DR by n bits so as to perform subtraction of (DR/2 n ) when the assigned bit number is n. From the subtracter 7 is obtained a threshold value of (MAX - Δ ), and from the adder 8 is obtained a threshold value of (MIN + Δ ) These threshold values from the subtracter 7 and the adder 8 are fed to the comparators 5 and 6, respectively. An output signal of the comparator 5 is supplied to an AND gate 10, and an output signal of the comparator 6 is fed to an AND gate 11. The input data from the delay circuit 4 is given to the AND gates 10 and 11. The output signal of the comparator 5 represents a high level when the input data is larger than the threshold level. Therefore, at the output terminal of the AND gate 10 is extracted a pixel data of the input data contained in the maximum level range of (MAX to MAX - Δ ). The output signal of the comparator 6 represents a high level when the input data is smaller than the threshold level. Therefore, at the output terminal of the AND gate 11 is extracted a pixel data of the input data contained in the minimum level range of (MIN to MIN + Δ ). An output signal of the AND gate 10 is supplied to an averaging circuit 12, and an output signal of the AND gate 11 is fed to an averaging circuit 13. These averaging circuits 12 and 13 each calculate an average value of each block, and a reset signal of block intervals is supplied to the averaging circuits 12 and 13 from a terminal 14. From the averaging circuit 12 is obtained an average value MAX′ of the pixel data belonging to the maximum level range of (MAX to MAX - Δ ), and from the averaging circuit 13 is obtained an average value MIN′ of the pixel data belonging to the minimum level range of (MIN to MIN + Δ ) The average value MIN′ is subtracted from the average value MAX′ by a subtracter circuit 15, and a concealed dynamic range DR′ is obtained from the subtracter 15. Further, the average value MIN′ is supplied to a subtracter circuit 16, and the average value MIN′ is subtracted in the subtracter 16 from the input data coming through a delay circuit 17, thereby forming data PD1 after removal of the minimum value. The data PD1 and the concealed dynamic range DR′ are supplied to a quantizer circuit 18. This embodiment performs edge-match quantization which is a variable-length ADRC in which the bit number n assigned to the quantization is one of 0 bit (no code signal is transmitted), 1 bit, 2 bits, 3 bits and 4 bits. The assigned bit number n is determined for each block by a bit number deciding circuit 19, and data of the bit number n are supplied to the quantizer 18. To the bit number deciding circuit 19 is supplied an output signal of a comparator circuit 22. The comparator 22 is supplied with the original dynamic range DR (= MAX - MIN) from a subtracter circuit 20 and threshold values T1 to T4 (T1 < T2 < T3 < T4) from a buffering circuit 21. The assigned bit number n is determined based on the magnitude relationship between the dynamic range DR and the threshold values T1 to T4. The variable-length ADRC can perform an efficient coding by decreasing the assigned bit number n in a block where the dynamic range DR is smaller and by increasing the assigned bit number n in blocks where the dynamic range DR is larger. More specifically, in a block of (DR < T1), no code signal is transmitted, and the dynamic range DR′ and the average value MIN′ alone are transmitted. In blocks of (T1 ≦ DR < T2), the bit number is set as (n = 1). In blocks of (T2 ≦ DR < T3), it is set as (n = 2). In blocks of (T3 ≦ DR < T4), it is set as (n = 3). In blocks of (DR ≧ T4), it is set as (n = 4). The assigned bit number n determined in this manner and the concealed dynamic range DR′ are supplied to the quantizer 18, and edge-match quantization is carried out. In such variable-length ADRC, the generated information amount can be controlled (so-called buffering) by varying the threshold values T1 to T4. Therefore, variable-length ADRC may be adapted to a transmission path, e.g. a digital VTR, which requires the generated information amount of each field or each frame being a predetermined value. In Fig. 4, reference numeral 21 designates a buffering circuit which determines the threshold values T1 to T4 for limiting the generated information amount to a predetermined value. In the buffering circuit 21, a plurality of, for example, 32 sets of threshold values (T1, T2, T3 and T4) are prepared as will be referred to later, and these sets of threshold values are discriminated by a parameter code Pi (i = 0, 1, 2, ..., 31). As the number i of the parameter code Pi increases, the generated information amount monotonely decreases. However, as the generated information amount decreases, the decoded picture quality is deteriorated. In the comparator 22 to which the threshold values T1 to T4 from the buffering circuit 21 and the dynamic range DR from the subtracter circuit 20 are applied, respective threshold values are compared with the dynamic range DR, and comparison outputs are supplied to the bit number deciding circuit 19 to have it determine the assigned bit number n of the block. In the quantizer 18, the data PD1 after removal of the minimum value is converted into a code signal DT by edge-match quantization using the dynamic range DR′ and the assigned bit number n. The quantizer 18 is formed of, for example, a ROM. A flag F is formed in a comparator circuit 23 in order for the receiver side to properly set the assigned bit number n. The comparator circuit 23 is supplied with the original dynamic range DR, the concealed dynamic range DR′ and a threshold value Ti selected by a selector 24. The selector 24 is supplied with the threshold values T1 to T4 formed in the buffering circuit 21 and information of the assigned bit number n from the bit number deciding circuit 19. A lower threshold value Ti for deciding the assigned bit number n of the block is selected by the selector 24. For example, in case of (n = 2), the threshold value T2 is selected by the selector 24. Under the relationship of (DR ≧ Ti > DR′) which causes such a mismatching that the assigned bit number on the part of the encoder is regarded as (n - 1) with respect to the assigned bit number n on the part of the decoder, the comparator circuit 23 generates a flag F indicating "1", and when the aforegoing relationship is not established, it generates a flag F indicating "0". In order to ensure 1 bit as the variation of the assigned bit number caused by a difference between the original dynamic range DR and the concealed dynamic range DR′ (that is, in order to prevent variation of 2 bits), the threshold values T1 to T4 are set to satisfy the following relationship. T2 ≧ 2T1, T3 ≧ 6/8 × T2, T4 ≧ 16/14 × T3 The concealed dynamic range DR′, the average value MIN′ and the code signal DT are supplied to a frame segmentation circuit 25, and the parameter code Pi indicative of a specific set of threshold values and the flag F are also supplied to the frame segmentation circuit 25. Data to be transmitted which have been converted into serial data are taken out at an output terminal 26 of the frame segmentation circuit 25. In the frame segmentation circuit 25, a coding of an error correction code is carried out, if necessary, and a synchronizing signal is added. Fig. 6 shows a construction on the part of a receiver (or reproducer). Received data from an input terminal 31 are fed to a frame separation circuit 32. The code signal DT and the added codes DR′, MIN′, Pi and F are separated and undergo an error correction processing in the frame separation circuit 32. The code signal DT is fed to a decoder circuit 33, and the parameter code Pi is applied to a ROM 34. The ROM 34 generates a set of threshold values indicated by the parameter code Pi, and the set of threshold values is supplied to a comparator circuit 35. The dynamic range DR′ is fed to the comparator circuit 35, and an output signal of the comparator circuit 35 is applied to a bit number deciding circuit 36. The bit number deciding circuit 36 decides an assigned bit number for the block based on the relationship between the dynamic range DR′ and the threshold values, and generates data corresponding to the bit number. An output of the bit number deciding circuit 36 is fed to an adder circuit 37 and added to the flag F. As described above, since the flag F represents "1" when the assigned bit number decided by the bit number deciding circuit 36 is less by 1 bit than that on the part of the encoder, a proper assigned bit number is obtained at the output of the adder circuit 37. The assigned bit number from the adder circuit 37 and the dynamic range DR′ are fed to the decoder 33. The average value MIN′ is applied to an adder circuit 38. The adder 38 is supplied with an output signal of the decoder 33, and an output signal of the adder 38 is applied to a block separation circuit 39. The decoder 33 carries out a processing opposite to the processing of the quantizer 18 on the part of the transmitter. More specifically, the code signal DT is decoded into a plurality of representative levels each including MAX′ and MIN′, and the data and the average value MIN′ of 8 bits are added by the adder 38, thereby to decode the original pixel data. The output signal of the adder 38 is fed to the block separation circuit 39. The block separation circuit 39 is a circuit for, in contrast to the block segmentation circuit 2 on the part of the transmitter, converting the decoded data in the order of blocks into a different order which is the same as the television signal scanning order. At an output terminal 40 of the block separation circuit 39 is obtained a decoded video signal. Fig. 7 shows an example of the buffering circuit 21. In order to form a frequency distribution table and an integrating type frequency distribution table, a memory (RAM) shown at 41 is provided in the buffering circuit 21, and an address is supplied to the memory 41 via a multiplexer 42. An one of inputs of the multiplexer 42, the dynamic range DR is supplied from an input terminal 43, and an address from an address circuit 50 is fed as the other input of the multiplexer 42. To the memory 41 is entered an output signal of an adder circuit 44, and output data of the memory 41 and an output of a multiplexer 45 are added in the adder circuit 44. The output of the adder circuit 44 is fed to a register 46, and an output of the register 46 is supplied to the multiplexer 45 and a comparator circuit 47. The multiplexer 45 is supplied with 0 and +1 in addition to the output of the register 46. When a computing operation of the generated information amount is carried out, an information amount Ai generated in one frame period, for example, is obtained at the output of the register 46. The generated information amount Ai and a target value Q from a terminal 48 are compared in the comparator 47, and an output signal of the comparator 47 is fed to a parameter code generator circuit 49 and a register 51. The parameter code Pi from the parameter code generator 49 is applied to an address generator 50 and the register 51. The parameter code Pi taken in the register 51 is fed not only to the frame segmentation circuit 25, as described before, but also to a ROM 52. The ROM 52 generates a set of threshold values (T1i, T2i, T3i and T4i) corresponding to the parameter code Pi entered as an address. The threshold values are fed to the comparator 22 as described before. Fig. 8 is a flow chart which shows an operation of the buffering circuit 21. In the first step shown at 61, the memory 41 and the register 46 are cleared into zero. Because of the zero clearance of the memory 41, the multiplexer 42 selects an address generated in the address generator 50, and the output of the adder circuit 44 is continuously held in zero. The address varies in the order of (0, 1, 2, ..., 255), and zero (0) data is written into all addresses of the memory 41. In the next step shown at 62, a frequency distribution table of dynamic ranges DR in one frame, which is a unit period for buffering, is formed in the memory 41. The multiplexer 42 selects the dynamic ranges DR from the terminal 43, and the multiplexer 45 selects +1. Therefore, when the one-frame period expires, occurrence frequencies of respective dynamic ranges DR are stored in respective addresses of the memory 41 corresponding to the dynamic ranges DR. The frequency distribution table of the memory 41 is as shown in Fig. 9A, taking the DR in the abscissa and the frequency in the ordinate. Subsequently, the frequency distribution table is converted into an integrating type frequency distribution table (step 63). Upon forming the integrating type frequency distribution table, the multiplexer 42 selects an address from the address generator 50, and the multiplexer 45 selects the output of the register 46. The address sequentially decrements from 255 toward 0. The read-out output of the memory 41 is fed to the adder 44, and it is added to the contents of the register 46 in the adder 44. An output of the adder 44 is written into the same address as the read-out address of the memory 41, and the contents of the register 46 are renewed into the output of the adder 44. In the initial condition where the address of the memory 41 is 255, the register 46 is cleared into zero (0). A integrating frequency distribution table shown in Fig. 9B is formed in the memory 41 when occurrences are accumulated for all the addresses of the memory 41. The amount of generated information Ai at the time when the set of threshold values (T1i, T2i, T3i and T4i) is adapted to the integrating type frequency distribution table is computed (step 64). Upon the computation of the generated information amount Ai, the multiplexer 42 selects the output of the address generator 50, and the multiplexer 45 selects the output of the register 46. The parameter code generator 49 generates a parameter code which sequentially varies from P0 to P31. The parameter code Pi is fed to the address generator 50, and addresses corresponding to the respective threshold values (T1i, T2i, T3i and T4i) are successively generated. values read out of the addresses corresponding to the respective threshold values are accumulated in the adder 44 and the register 46. This integrated value corresponds to the generated information amount Ai at the time when the set of threshold values indicated by the parameter code Pi is adapted. More specifically, in the integrating type frequency distribution table of Fig. 9B, the value which is obtained by multiplying the total value (A1 + A2 + A3 + A4) of the respective values A1, A2, A3 and A4 read out of the addresses corresponding to the threshold values T1, T2, T3 and T4 by the number of picture elements (64) in the block is the generated information amount (bit number). However, since the number of picture elements is constant, the processing of multiplying them by 64 is omitted in the buffering circuit 21 of Fig. 7. The generated information amount Ai is compared to the target value Q (step 65), An output of the comparator circuit 47 generated under a relationship of (Ai ≦ Q) is fed to the parameter code generator 49 and the register 51. As a result, increment of the parameter code Pi is stopped, and the parameter code Pi is taken in the register 51. The parameter code Pi from the register 51 and a set of threshold values generated in the ROM 52 are exerted (step 66). If the relationship of (Ai ≦ Q) is not established in the judging step 65 in the comparator 47, the parameter code Pi is changed into a subsequent code Pi+1, and an address corresponding to Pi+1 is generated from the address generator 50. In the same manner as described above, a generated information amount Ai+1 is computed, and it is compared to the target value Q in the comparator 47. This operation is repeated until the relationship of (Ai ≦ Q) is established. In the aforegoing explanation, the code signal DT, the dynamic range DR′ and average value MIN′ are transmitted. In lieu of the dynamic range, the average value MAX′ and a quantization step width may be transmitted as additional codes. A second embodiment of the invention is described below, referring to Fig. 10 in which some elements equivalent to those of the first embodiment of Fig. 4 are denoted by the same reference numerals. Their detailed explanation is omitted in the following description, accordingly. In the embodiment of Fig. 4, the data PDI is quantized adaptively to the concealed dynamic range DR′ according to the bit number decided in the bit number deciding to the bit number decided in the bit number deciding circuit 19. Therefore, under the above-indicated relationship between the original dynamic range DR and the concealed dynamic range DR′, since mismatching occurs between the bit number n on the part of the transmitter and the bit number obtain on the part of the receiver by comparing the transmitted dynamic range DR′ with the threshold value Ti generated on the basis of the transmitted parameter code Pi, a flag F is also transmitted to insure proper decoding. In the second embodiment shown in Fig. 10, in order to omit transmission of the flag F, information on threshold values T1 to T4 obtained by the buffering circuit 21 is compared with the concealed dynamic range DR′ in a comparator circuit 28 so that a bit number deciding circuit 27 decides a bit number n′ for quantization, based on a comparison output of the comparator 28, and the data PDI are quantized by the quantizer 18 according to the bit number n′. Under this arrangement, quantizing bit numbers on both parts of the transmitter and the receiver never fail to coincide, and transmission of the flag F is not necessary. An arrangement on the part of the receiver for receiving data transmitted from the part of the transmitter of Fig. 10 is explained below, referring to Fig. 11 in which some elements equivalent to those in the arrangement of the receiver shown in Fig. 6 are designated by the same reference numerals. As described above, since the transmitter shown in Fig. 10 performs quantization using the bit number n′ which is obtained by comparing the concealed dynamic range DR′ with the threshold value information T1 to T4 obtained in the buffering circuit 21, the receiver can readily decode the quantizing bit number n′ from the transmitted parameter code Pi and dynamic range DR′. Decoding of the quantizing bit number n' is done in a decoder circuit 33 in the arrangement of Fig. 11. Its detail, however, is omitted. Data DT are decoded based on the decoder bit number information n' and the dynamic range DR′. Other operations of the arrangement of Fig. 11 are equal to those of the arrangement of Fig. 6, and their detailed explanation is omitted. A third embodiment of the invention is explained below, referring to Fig. 12 in which some elements equivalent to those of Figs. 4 and 10 are designated by the same reference numerals. Their detailed explanation is omitted in the following description, accordingly. In the third embodiment of Fig. 12, edge-match quantization using a fixed bit number is first performed as a preliminary processing. After this, by averaging data belonging to the maximum and minimum bit planes, new values MAX′ and MIN′ are obtained. The quantizing bit number is decided by effecting a buffering based on a concealed dynamic range DR′ obtained from the values MAX′ and MIN′. Therefore, by performing fixed-bit shifting of a dynamic range DR of an output of the maximum/minimum detector 3 in the bit shift circuit 9, a value of one quantizing step width (Δ = 1/16 DR) is obtained. Subsequent processings are the same as those of the first and second embodiments. The concealed dynamic range DR′ obtained in the subtracter 15 is supplied to the buffering circuit 21. Arrangement of the buffering circuit 21 is the same as the arrangement of the buffering circuit shown in Fig. 7 and, its operation is the same as the operation explained with reference to the flow chart shown in Fig. 8. The threshold values T1 to T4 obtained in the buffering circuit 21 are supplied to the comparator 22 for comparison with the concealed dynamic range DR′ and, based on an output of the comparator 22, the bit number deciding 19 decides the quantizing bit number n. The quantizer 18 is responsive to the quantizing bit number n to quantize the output data DT of a delay circuit 123 adaptively to the dynamic range DR′. As a result, quantized data DT are obtained. Delay circuits 122, 123 and 124 are used to delay respective signals by a time required for processing in the buffering circuit. The same arrangement as that of the receiver apparatus shown in Fig. 11 may be employed for receiving data transmitted from the transmitter apparatus in the form of the third embodiment of Fig. 12. Fig. 13 shows a fourth embodiment which is basically analogous to the third embodiment of Fig. 12 except that, while the embodiment of Fig. 12 obtains the one quantizing step width Δ by fixed-bit shifting of the original dynamic range DR, the embodiment of Fig. 13 is configured to enter a fixed value Δ from a terminal 9 and to compute it with the maximum values Max and Min. The fixed value Δ preferably corresponds to the noise level. Other arrangements and operations of the embodiment of Fig. 13 are the same as those of the third embodiment of Fig. 12. In the first embodiment of Fig. 4 heretofore referred to, flag information is required as additional information. In the second embodiment of Fig. 10, since the buffering itself is based on the original dynamic range and, from the resulting threshold value information and the concealed dynamic range DR′, the quantizing bit number is decided so that the quantization is performed accordingly, there is a problem of such a low efficiency that the actual information amount is less than the allowable maximum information amount. In the third embodiment of Fig. 12 and in the fourth embodiment of Fig. 13, since non-edge matching quantization using the fixed bit number is performed as a preliminary processing regardless of any value of the original dynamic range DR, they are also not optimum from the viewpoint of efficiency. A fifth embodiment removing these drawbacks is explained below, referring to Fig. 14A et seq. Figs. 14A and 14B, although connected actually, are drawn separately on account of the limited area of each drawing sheet. In Fig. 14A, a digital video signal (video luminance signal) in which one sample is quantized with eight bits, for example, is entered in an input terminal shown at 1. The digital video signal is given to a block segmentation circuit 2. In the block segmentation circuit 2, the input digital video signal is converted into successive signals for each two-dimensional block which is the unit of coding. In this embodiment, one block is as large as (8 lines × 8 pixels = 64 pixels) as shown in Fig. 5. An output signal of the block segmentation circuit 2 is supplied to a maximum/minimum value detector circuit 3 and a delay circuit 4. The maximum/minimum value detector 3 detects a minimum value MIN and a maximum value MAX of each block. The delay circuit 4 delays the input data by a time required for detecting the maximum value and the minimum value. Pixel data from the delay circuit 4 are supplied to a comparator circuits 5A, 5B, 5C and 5D and to comparator circuits 6A, 6B, 6C and 6D. The maximum value MAX from the maximum/minimum value detector 3 is fed to a subtractor circuits 7A, 7B, 7C and 7D and to adder circuits 8A, 8B, 8C and 8D. The subtractor circuits 7A, 7B, 7C and 7D and the adders 8A, 8B, 8C and 8D are supplied from a bit shift circuits 9A, 9B, 9C and 9D with values (Δ4 = 1/16DR, Δ 3 = 1/8DR, Δ 2 = 1/4DR and Δ 1 = 1/2DR) of one quantization step width at the time of non-edge matching quantization using respective bit numbers: 4 bits, 3 bits, 2 bits and 1 bit. The bit shift circuits 9A, 9B, 9C and 9D are configured to shift a dynamic range DR by 4 bits, 3 bits, 2 bits and 1 bits, respectively, so as to perform these subtractions. From the subtractors 7A, 7B, 7C and 7D are obtained threshold values of (MAX - Δ 4, MAX - Δ 3, MAX - Δ 2 and MAX - Δ 1), and from the adders 8A, 8B, 8C and 8D, threshold values of (MIN + Δ 4, MIN + Δ 3, MIN + Δ 2 and MIN + Δ 1) are obtained. These threshold values from the subtractors 7A, 7B, 7C and 7D and from the adders 8A, 8B, 8C and 8D are fed to the comparators 5A, 5B, 5C and 5D and to comparator circuits 6A, 6B, 6C and 6D, respectively. Output signal of the comparators 5A, 5B, 5C and 5D are supplied to AND gates 10A, 10B, 10C and 10D, and a output signals of the comparators 6A, 6B, 6C and 6D are fed to AND gates 11A, 11B, 11C and 11D, respectively. The input data from the delay circuit 4 is given to the AND gates 10A, 10B, 10C and 10D and to the AND gates 11A, 11B, 11C and 11D. The output signal of the comparators 5A, 5B, 5C and 5D represent high levels when the input data is larger than the threshold level. Therefore, at the output terminal of the AND gates 10A, 10B, 10C and 10D are extracted pixel data of the input data contained in the maximum levels ranges of (MAX to MAX - Δ 4, MAX to MAX - Δ 3, MAX to MAX - Δ 2, and MAX to MAX - Δ 1). The output signals of the comparators 6A, 6B, 6C and 6D represent low levels when the input data is smaller than the threshold level. Therefore, at the output terminals of the AND gates 11A, 11B, 11C and 11D are extracted a pixel data of the input data contained in the minimum level ranges of (MIN to MIN + Δ 4, MIN to MIN + Δ 3, MIN to MIN + Δ 2, and MIN to MIN + Δ 1). Output signals of the AND gates 10A, 10B, 10C and 10D are supplied to an averaging circuits 12A, 12B, 12C and 12D, and output signals of the AND gates 11A, 11B, 11C and 11D are fed to an averaging circuits 13A, 13B, 13C and 13D. These averaging circuits 12A, 12B, 12C, 12D 13A, 13B, 13C and 13D each calculate an average value of each block, and a reset signals of block intervals are supplied to the averaging circuits 12A, 12B, 12C, 12D 13A, 13B, 13C and 13D from a terminal 14. From the averaging circuit 12A is obtained an average value MAX4 of the pixel data belonging to the maximum level range of (MAX to MAX - Δ 4) and, from the averaging circuits 12B, 12C and 12D, average values MAX3, MAX2, and MAX1 of the pixel data belonging to the maximum level ranges of (MAX to MAX - Δ 3, MAX to MAX - Δ 2, and MAX to MAX - Δ 1) are obtained, respectively. From the averaging circuits 13A, 13B, 13C and 13D are obtained average values MIN4, MIN3, MIN2 and MIN1 of the pixel data belonging to the minimum level ranges of (MIN to MIN + Δ 4, MIN to MIN + Δ 3, MIN to MIN + Δ 2 and MIN to MIN + Δ 1), respectively. Representative sets of corresponding average values undergo subtraction in subtracter circuits 15A, 15B, 15C and 15D, respectively, and concealed dynamic ranges DR4, DR3, DR2 and DR1 are obtained from the subtracters 15A, 15B, 15C and 15D. Figs. 15A to 15D are diagrams for explaining formation of the dynamic range DR4, DR3, DR2 and DR1. As shown in Fig. 15A, a bit shift circuit 9A divides the original dynamic range DR into 16 equal parts and forms the quantizing step width Δ 4. Averaging values of pixel data present in the maximum level range (MAX - Δ 4) and in the minimum level range (MIN + Δ 4) are used as the maximum value MAX4 and the minimum value MIN4. As shown in Fig. 15B, a bit shift circuit 9B divides the original dynamic range DR into 8 equal parts and forms the quantizing step width Δ 3. Averaging values of pixel data present in the maximum level range (MAX - Δ 3) and in the minimum level range (MIN + Δ 3) are used as the maximum value MAX3 and the minimum value MIN3. Using the quantizing step width Δ 2 which is formed in a bit shift circuit 9C, the maximum value MAX2 and the minimum value MIN2 are formed as shown in Fig. 15C. Using the quantizing step width Δ 1 which is formed in a bit shift circuit 9D, the maximum value MAX1 and the minimum value MIN1 are formed as shown in Fig. 15D. As shown in Fig. 14B, the average values MIN4, MIN3, MIN2, and MIN1 are supplied to a subtracter circuits 216A, 216B, 216C and 216D, and the subtracters 216A to 216D subtract the average values MIN4, MIN3, MIN2, and MIN1, respectively, from the input data PD coming through a delay circuit 17 to form data PD1 after removal of the minimum values. These data and the concealed dynamic ranges DR4 to DR1 are supplied to a quantizer circuits 218A, 218B, 218C and 218D, respectively. This embodiment performs edge-match quantization which is a variable-length ADRC in which the bit number n assigned to the quantization is one of 0 bit (no code signal is transmitted), 1 bit, 2 bits, 3 bits and 4 bits. The quantizers 218A, 218B, 218C and 218D each consist of, for example, a ROM, and their output signals are supplied to a selector 219. A code signal selected by the selector 219 is transmitted as a coding output DT. There is provided a further selector 220 which is supplied with the dynamic ranges DR4 to DR1 and the minimum values MIN4 to MIN1. The selectors 219 and 220 are controlled by a bit number code Bn which is read out of a ROM 221. The assigned bit number n indicated by the bit number code Bn is decided for each block by the ROM 221, and the bit number code Bn is supplied to the quantizers 218A, 218B, 218C and 218D. Variable-length ADRC performs efficient coding by decreasing the assigned bit number n in a block where the dynamic range DR is smaller and by increasing the assigned bit number n in a block where the dynamic range DR is larger. More specifically, assuming that the threshold values upon deciding the bit number n are T1 to T4 (T1 < T2 < T3 < T4), no code signal is transmitted in blocks of (DR < T1), and information on the dynamic range DRI alone is transmitted. In blocks of (T1 ≦ DR2 < T2), it is set as (n = 1). In blocks of (T2 ≦ DR3 < T3), it is set as (n = 2). In blocks of (T3 ≦ DR4 < T4), it is set as (n = 3). In blocks of (DR4 ≧ T4), it is set as (n = 4). The ROM 221 is supplied with comparison output signals from comparator circuits 222A, 222B, 222C and 222D as addresses. The comparator 222A compares the dynamic range DR4 with the threshold value T4, the comparator 222B compares the dynamic range DR3 with the threshold value T3, the comparator 222C compares the dynamic range DR2 with the threshold value T2, and the comparator 222D compares the dynamic range DRI with the threshold value T1. These comparators supply output signals of "1" (high level) under the condition of (DRn > Tn) (n = 0, 1, 2, 3 or 4). When indicating comparison output signals of the comparators 222A, 222B, 222C and 222D by a, b, c and d, respectively, the ROM 221 produces the output signal Bn of 3 bits according to the following table. a 1 0 0 0 0 b 1 1 0 0 0 c 1 1 1 0 0 d 1 1 1 1 0 Bn 4 3 2 1 0 When (Bn = 4) is established, the selector 219 selects the output signal of the quantizer 218A, and the selector 220 selects DR4 and MIN4. In case of (Bn = 3), the selector 219 selects the output signal of the quantizer 218B, the selector 220 selects DR3 and MIN3. In case of (Bn = 2), the selector 219 selects the output signal of the quantizer 218C, and the selector 220 selects DR2 and MIN2. In case of (Bn = 1), the selector 219 selects the output signal of the quantizer 218D, and the selector 220 selects DR2 and MIN2. In case of (Bn = 0), the selector 219 dose not supply any code signal, and the selector 220 selectively supplies DR1 and MIN1. The code signal DT selected by the selector 219, the dynamic range DRn and the average value MINn both selects by the selector 20, and the parameter code Pi indicative of a specific set of threshold values are supplied to a frame segmentation circuit (not shown). The frame segmentation circuit performs a coding of an error correcting code, if necessary, and adds a synchronizing signal. At an output terminal of the frame segmentation circuit, transmitted data converted into serial data is taken out. Variable-length ADRC can control (so-called buffering) the generated information amount by varying the threshold values T1 to T4. Therefore, variable-length ADRC is useful in a transmission path, e.g., a digital VTR, which requires the generated information amount of each field or each frame being a predetermined value. This embodiment uses distribution table generator circuits 223A, 223B, 223C and 223D as shown in Fig. 14A in order to compute generated information amounts. The distribution table generator 223A is supplied with the dynamic range DR4 from the subtracter 15A. The distribution table generators 223B, 223C and 223D are supplied with the dynamic ranges DR3, DR2 and DR1 from the subtracters 15B, 15C and 15D, respectively. The distribution table generator 223A makes in a memory a table corresponding to an occurrence frequency distribution graph as shown in Fig. 16A which indicates the dynamic range DR4 in the abscissa and the occurrence frequencies in the ordinate. The distribution table generators 223B, 223C and 223D make, in memories, tables corresponding to occurrence frequency distribution graphs shown in Figs. 16B, 16C and 16D, respectively. The occurrence frequency table is formed for each predetermined period, e.g., every frame period or every two frame periods. After the tables are formed, the distribution table generators 223A, 223B, 223C and 223D are supplied with the threshold values T4, T3, T2 and T1, respectively, from a threshold value table 224 which may be formed of a ROM. In the threshold value table 224, plural sets e.g., 32 sets, of threshold values (T1, T2, T3 and T4) are prepared and these sets of threshold values discriminated by a parameter code Pi (i = 0, 1, 2, ..., 31). As the number i of the parameter code Pi increases, the generated information amount monotonely decreases. However, as the generated information amount decreases, the decoded picture quality is deteriorated. When the threshold value T4 is given to the distribution table generator 223A, it aggregates the number of blocks including dynamic ranges DR4 larger than the threshold value T4 as shown by hatched lines in Fig. 16A, and supplied an aggregated value S4. The aggregated value S4 is the total number of blocks to which the bit number of 4 bits is assigned. When the threshold value T3 is given to the distribution table generator 223B, it aggregates the number of blocks including dynamic ranges DR3 larger than the threshold value T3 as shown by hatched lines in Fig. 16B, and supplies an aggregated value S3. The distribution table generators 223C and 223D supply aggregated values S2 and S1 of blocks including dynamic ranges larger than the threshold values T2 and T1, respectively, as shown by hatched lines in Figs. 16C and 16D. In Figs. 16B, 16C and 16D, different regions discriminated by other threshold values are shown by different shadow lines or marks. The aggregated value S4 is the total number of blocks whose assigned bit number is 4 bits. The aggregated value S3 is the total number of blocks whose assigned bit number is 3 bits or more. The aggregated value S2 is the total number of blocks whose assigned bit number is 2 bits or more. The aggregated value S1 is the total number of blocks whose assigned bit number is 1 bit or more. Therefore, a value obtained by multiplying the sum of the aggregated values obtained from an adder circuit 226 by the number of picture elements in one block (64 in this embodiment) is the total of the bit numbers in a predetermined period. However, since the number of picture elements is constant, multiplication by 64 is omitted in this embodiment. An output signal of the adder circuit 226 is supplied to a comparator circuit 227, and it is compared with a target value from a terminal 228. When the generated information amount is equal to or less than the target value, the transmitted data amount in a predetermined period is deemed to be within the capacity of the transmission path. An output signal of the comparator 227 is supplied to a read-out control circuit 225. The read-out control circuit 225 controls the reading of the threshold values T4 to T1 from the threshold value table 224. 32 sets, for example, of threshold values T4 to T1 are stored in the threshold value table 224, and they are selectively read out of the threshold value table 224 in response to the parameter code Pi. In this case, the sets of threshold values are sequentially read out, starting from a set with which the generated information is increased. A set of threshold values at the time when the generated information amount generated from the adder circuit 226 comes under the target value is decided to be the optimum set. This set of threshold values is supplied to the comparators 222A to 222D (Fig. 14B). Additionally, the parameter code Pi indicative of the set of threshold values is supplied to the frame segmentation circuit (not shown) and transmitted to the receiver. Referring to Figs. 16A to 16D, in respect of obtaining aggregated values S4 to S1 of the number of blocks larger than the threshold values T4 to T1, the distribution table is preferably converted into an integrating type in order to ensure quick generation of the aggregated values when the threshold value is changed. Taking the distribution table of Fig. 16A as an example, an integrating type distribution table shown in Fig. 16E is obtained by sequentially integrating occurrence frequencies from the maximum value of the dynamic range DR4 toward the minimum value thereof. In the integrating type distribution table, the integrating type occurrence frequency, at the time when the threshold value T4 is given, is just the aggregated value S4. The other aggregated values S3, S2 and S1 can readily be obtained from integrating type distribution tables in the same manner. The embodiment of Fig. 14A et seq. may be used in combination with a receiver having the same arrangement as that of Fig. 11. According to the invention, it is possible to prevent block distortion in a block including ringing, impulsive noise, or the like. The invention can perform effective coding using a variable-length ADRC, and can prevent mismatching between the assigned bit number n in the encoder and decoder because of a difference in dynamic ranges used for control of the generated information amount and quantization. Further, upon obtaining a new dynamic range DRn, the maximum levels MAXn and the minimum levels MINn are in the form of average values of pixel data present in the maximum level range and in the minimum level range corresponding to a specific bit number. Therefore, as compared to other system in which the maximum level range and the minimum level range are fixed at constant values regardless of the assigned bit number, the invention can effectively prevent block distortion.

Claims: A coding apparatus for coding digital video data in a block format allowing video data compression for transmission by data transmission means having a predetermined transmission capacity, comprising: detecting means (3) for detecting a maximum (MAX) and a minimum (MIN) value of the digital video data of plural picture elements in a block; first averaging means (5, 10, 12) for averaging the digital video data having a value between said maximum value (MAX) and a first value (MAX-Δ) which is a first predetermined level lower than said maximum value, said first averaging means generating a modified maximum value (MAX'); second averaging means (6, 11, 13) for averaging the digital video data having a value between said minimum value (MIN) and a second value (MIN + Δ) which is a second predetermined level higher than said minimum value said second averaging means generating a modified minimum value (MIN'); means for subtracting (16) said modified minimum value from the digital video data for each of said picture elements to generate modified digital video data (PDI); means for generating modified dynamic range information from said modified maximum and minimum values; edge-match encoding means for encoding said modified digital video data with an encoding bit number (n); and means (25) for transmitting an output of said encoding means and a first additional code for each block, formed of at least two of said modified maximum and minimum values and a signal based on said modified dynamic range information; characterised by: means (19-22) for determining, with reference to said predetermined transmission capacity of said data transmission means, said encoding bit number (n) for each block during a predetermined period said means for determining including means (20) for generating original dynamic range information from said maximum and minimum values, and setting means (21) for setting a threshold value for determining a boundary of plural bit numbers (T1-T4); and in that said means for transmitting includes comparator means (23) for comparing said original and modified dynamic range informations (DR, DR') and said threshold value (Ti) and for generating a flag code (F) for each block and means for transmitting said flag. A coding apparatus according to claim 1, wherein said means for determining further includes means (21) for generating a distribution table of said original dynamic range information during said predetermined period, and second comparator means (22) for comparing the original dynamic range information (DR) and said threshold value. A coding apparatus according to claim 1 wherein said means for determining further includes means (Fig. 13B, 21) for generating a distribution table of said modified dynamic range information during said predetermined period, and comparator means (22) for comparing the modified dynamic range information (DRI) and said threshold value (T1-T4). A coding apparatus according to claim 1, 2 or 3, wherein said first and second predetermined levels (Δ) are obtained by bit shifting said original dynamic range information (DR) by the bit number (n) determined by said threshold value and said original dynamic range information. A coding apparatus according to claim 1 or 2, wherein said first and second predetermined levels are fixed levels. A coding apparatus according to any one of claims 1 to 4, wherein said first averaging means includes n averaging means (12A-12D) each of which averages the digital video data having a value between said maximum value and a value lower than said maximum value by original dynamic range information generated from said maximum and minimum values divided by 2 i (i = 1, 2, ... n), said first averaging means generating n modified maximum values, said second averaging means includes n averaging means (13A - 13D) each of which averages the digital video data having a value between said minimum value and a value higher than said minimum value by the original dynamic range information divided by 2 i (i = 1, 2, ... n), said second averaging means generating n modified minimum values, said means (15A- 15D) for generating modified dynamic range information generates n modified dynamic range informations, and said means for determining includes means for generating n distribution tables (223A-D) from said n of modified dynamic range information, setting means (224) for setting a threshold value of the modified dynamic range information for determining a boundary of plural bit numbers, and comparator means (227) for comparing said n of modified dynamic range information and said threshold value.

Inventors: KONDO TETSUJIRO, YADA ATSUO, KONDO, TETSUJIRO, YADA, ATSUO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H04N7
IPC codes: H04N1, H04N7