Display system

Abstract: A display system wherein, in a normal mode, foreground pels are displayed with low luminance and wherein, in a high intensity mode, foreground pels are displayed with zero luminance and background pels with high luminance.

Description: The invention relates to a display system wherein foreground dots of image are displayed by dark level and background dots are displayed by white level. Display devices are known wherein characters, cursor, lines, etc. are displayed by illuminated dots on a black or non-illuminated background of a display screen. The display operations for displaying the characters, cursor, etc. by illuminated dots on a black background will be referred to as a negative display mode or a white on black mode. The negative display mode includes a normal mode wherein the characters, cursor, etc. of low luminance are displayed on a black or nonilluminated background; and a high intensity mode wherein the characters, cursor, etc. of high luminance are displayed on a black or non-illuminated background. To control the luminance of the dot or picture element, two binary bits are assigned for each dot, and represent the luminance of one dot, as follows. 0 0 ... Zero luminance (Black) 0 1 ... Low luminance (Gray) 1 0 ... High luminance (White) 1 1 ... Not used Dot patterns generated from a font memory include foreground dots representing the characters to be displayed on the display screen and background dots. With reference to a Fig. 6 which shows a merge circuit and a prior art mode switching circuit, the dot patterns generated from the font memory are merged with a trim line, a ruler or a cursor by OR gate 61 in a merge circuit. It is assumed that a character T is displayed in the normal mode of the negative display mode; no additional functions, i.e., trim, ruler and cursor, are reguired; and one character is represented by 5 dots x 7 dots. In the negative display mode, a positive mode signal to an exclusive OR (XOR) gate 62 is low level, a normal mode signal to the AND gate 63 is high level, and a high intensity mode signal to the AND gate 64 is low level. The output dot patterns at the outputs A, A′, B and C in this mode are shown in Fig. 7. The two bits on the output lines C and B are used as the two binary bits for controlling luminance of each dot of the foreground and background. The bit on the line C is a high order bit and the bit on the line B is a low order bit of the two bits. Referring to the dot patterns 71C and 71B generated in this mode, the high order bit for each dot of the foreground image portion or the character T is 0 and the low order bit for each dot of the foreground portion is 1; and the high order bit of each dot of the background portion is 0 and the low order bit for each dot of the background portion is 0. In the normal mode of the negative display mode, therefore, the two bit combination (0 1) is assigned to each dot of the foreground character image and the two bit combination (0 0) is assigned to each dot of the background, so that the foreground image is displayed by the dots of the low luminance or gray level, and the background is not illuminated. That is, the background is black. In the negative display mode, it is reguired to display the foreground image with the high intensity in addition to the normal mode. In this mode, the positive mode signal is low level, the normal mode signal is low level and the high intensity mode signal is high level, and the dot patterns 72A, 72A′, 72B and 72C in the Fig. 7 show the dot patterns at the outputs A, A′, B and C in the Fig. 6. In the high intensity mode of the negative display mode, two bit combination (1 0) is assigned to each dot of the foreground character image, and the two bit combination (0 0) is assigned to each dot of the background, so that the foreground image is displayed by the dots of the high luminance or white level, and the background is not illuminated. It has recently become necessary to display characters, cursors, etc. in a positive display mode or black on white mode wherein the characters or the foreground image are represented by the non-illuminated background color and the background is displayed by the illuminated dots. According to the prior art, to perform the positive display mode, the Exclusive OR gate 62 is added into the mode switching circuit and the positive mode signal is applied to the Exclusive OR gate 62. The positive display mode also includes the normal mode and the high intensity mode. In the normal mode of the positive display mode, the positive mode signal and the normal mode signal are high level, and the high intensity mode signal is low level in Fig. 6. The dot patterns 73A, 73A′, 73B and 73C in Fig. 7 shows the patterns at the outputs A, A′, B and C in the Fig. 6. In this mode, the two bit combination (0 0) is assigned to each dot of the foreground character image, and the two bit combination (0 1) is assigned to each dot of the background, so that the foreground character image T is represented by the non-illuminated black level, and the background is represented by the illuminated dots of the low luminance or gray level. The high intensity mode is also reguired in the positive display mode. In this mode, the positive mode signal and the high intensity mode signal are high level and the normal mode signal is low level, and the dot patterns 74A, 74A′, 74B and 74C in the Fig. 7 show the dot patterns at the outputs A, A′, B and C in the Fig. 6. In this high intensity mode of the positive display mode, the two bit combination (0 0) from the patterns 74C and 74B is assigned to each dot of the foreground character image, and the two bit combination (1 0) from the pattern 74C and 74B is assigned to each dot of the background, so that the foreground image is represented by the non-illuminated black level and the background is represented by the illuminated dots of the high luminance or white level. The problem in the positive display mode is that the luminance of the background in the normal mode is the low luminance or gray level specified by the two bit combination (0 1), while the luminance of the background in the high intensity mode is the high luminance or white level specified by the two bit combination (1 0). Thus, in the case that both the normal mode and high intensity mode are mixedly displayed on a display screen 81, as shown in Fig. 8, the background is displayed by the two kinds of luminance, i.e., the low luminance or gray level and the high luminance or white level. More particularly, the areas 82 and 83 which are the background of the high intensity mode have the high luminance, while the areas 84, 85 and 86 of the normal mode have the low luminance. The mixed display of these areas on the display screen is illegible, and causes an asthenopia or fatigue of the eyes of the operator. The mark # shown in the Fig. 8 is a field attribute representing the normal mode, and the mark @ shown in the Fig. 8 is a field attribute representing the high intensity mode. It is noted that both the marks # and @ actually are not displayed on the display screen. The field attribute is placed at the top of a field including plural character boxes, and defines the attribute characteristics of the field. The reasons for changing the luminance of the background in the prior positive display mode are that the basic concept of the negative display mode wherein the luminance of the dots represented by the binary number 1 of the dot pattern of the output A′ in the Fig. 6 is changed between the two luminance levels has been introduced into the positive display mode. That is, the dots represented by the binary number 1 in the positive display mode are the background dots as shown in the dot patterns 73A′ and 74A′ in the Fig. 7, and the luminance of the background dots represented by the binary number 1 is switched between the low luminance (0 1) in the normal mode and the high luminance (1 0) in the high intensity mode and the luminance of the foreground is not changed, in accordance with the concept of the negative display mode, stated above. Japanese patent application 47-98526 (Published examined patent application No. 54-3581) shows a CRT display system wherein the background is displayed by the low luminance, negative value is displayed by the zero luminance, and positive value is displayed by the high luminance, whereby the negative and positive values in an equation are distinguishably displayed on the display screen. The application JP-A-47-98526, however, does not disclose the concept of the invention; see also EP-A-0 175 499. Therefore, in accordance with the present invention, there is provided a display system for displaying an image comprising a plurality of pels, the system comprising: means for displaying, in a normal mode, foreground pels of low luminance and background pels of high luminance and, in a high intensity mode, foreground pels of zero luminance and background pels of high luminance. The display system preferably comprises a signal generating means for responding to a normal mode signal to generate control signals for displaying foreground dots by low luminance and background dots by high luminance and for responding to a high intensity mode signal to generate control signals for displaying foreground dots by zero luminance and background dots by the high luminance. The signal generating means receives a dot pattern signal wherein the foreground dots are represented by one binary number, and the background dots are represented by another binary number, responds to a normal mode signal to generate control signals for displaying the foreground dots by the low luminance or gray level or intermediate level and the background dots by the high luminance or white level, and responds to a high intensity mode signal to modify the received dot pattern to generate control signals for displaying the foreground dots by zero luminance or black level and the background dots by the high luminance or white level. The signal generating means responds to a normal mode signal to modify the received dot pattern to generate first dot pattern wherein the foreground dots are represented by the other binary numbers respectively and the background dots are represented by one binary numbers, respectively, and second dot pattern wherein the foreground dots are represented by one binary numbers, respectively and the background dots are represented by the other binary numbers, respectively. The control signal for controlling the luminance of each dot position on a display screen in the normal mode of the positive display mode is formed by two binary numbers at each dot position of the first and second dot patterns generated in this mode. The signal generating means responds to the high intensity mode signal to generate first dot pattern wherein the foreground dots are represented by the other binary numbers, respectively and the background dots are represented by one binary numbers, respectively, and second dot pattern wherein the foreground and background dots are represented by the other binary numbers, respectively. The control signal for controlling the luminance of each dot position on the display screen in the high intensity mode of the positive display mode is formed by two binary numbers at each dot position of the first and second dot patterns generated in this mode. The characters of the normal mode of the positive display mode and the characters of the high intensity mode of the positive display mode are mixedly displayed on the display screen. The display system can be a data processing system which may include other components such as data storage devices, user input devices such as a keyboard or a mouse, communications links and the like. The invention will be better understood with reference to the following description of a particular embodiment and the accompanying drawings wherein: Fig. 1 is a block diagram of the display terminal device into which the mode switching function of the present invention is incorporated; Fig. 2 is a block diagram of the mode switching circuit of the present invention; Fig. 3 shows various dot patterns at various points of the circuit of Fig. 2; Fig. 4 shows the image on the screen displayed in accordance with the present invention; Fig. 5 shows a second embodiment of the present invention. Fig. 6 shows a prior art mode switching circuit; Fig. 7 shows various dot patterns at various points of the prior art circuit of Fig. 6. and Fig. 8 shows displayed images according to the prior art. Fig. 1 is a block diagram of a display terminal device into which a mode switching function in accordance with the present invention is incorporated. A control device 1, such as a microprocessor, controls the operations of the blocks in Fig. 1. Actually, a large number of control lines for controlling the operations of the blocks are connected between the control device 1 and the blocks. For clarity, however, the control lines are not shown. The circuit includes a column, line, row counter 2, an address generator 3, a character code buffer 4, an attribute buffer 5, a character code register (C/C) 6, a font memory 7, a parallel/serial converter 8, a merge circuit 9, a signal generating circuit or a mode switching circuit 10, a video circuit 11, and CRT display system 12. The operation of each of these blocks is well known in the art. The character codes and the attributes of the characters displayed on the CRT display system 12 are stored in the character code buffer 4 and the attribute buffer 5, respectively, under the control of the control device 1. The display screen of the CRT display system 12 is divided into a plurality of character boxes, such as 80 (horizontal) x 32 (vertical). That is, the 32 character rows, each of which includes the 80 character boxes or columns, are displayed on the display screen. For example, each character box includes 9 x 19 dots or picture elements (pels), and one character in the box is represented by 5 x 7 dots or pels. The positions of the character boxes in the horizontal and vertical directions are represented by columns and rows. One row includes 19 scan lines in this example. The scan lines are traced in accordance with a raster scan scheme. The column, line, row counter 2 counts the number of columns, lines, rows to control the display of the characters on the display system 12. The count values from the column, line, row counters 2 are supplied to the address generator 3, which generates addresses for sequentially accessing both the character code and attribute buffers 4 and 5. The character codes of the characters of one row are stored in the character code register 6 for repeatedly accessing the character dot patterns in the font memory 7, whereby the dot patterns on one scan line of the character patterns in one row are supplied, in parallel, to the parallel/serial converter 8. The converter 8 serially supplies the dot patterns of plural characters on one scan line to the merge circuit 9. In this circuit 9, a trim line, a ruler line or a cursor is added to the dot pattern of selected character boxes by the operation. The dot patterns from the merge circuit 9 are supplied to the signal generating circuit or mode switching circuit 10 of the present invention. The attribute representing the normal mode or the high intensity mode is supplied to the mode switching circuit 10. The details of the merge circuit 9 and the mode switching circuit 10 are shown in Fig. 2. The merge circuit 9 includes OR gate 21. The dot patterns generated from the font memory 7 are merged with a trim line, a ruler line or a cursor by the OR gate 21. It is assumed that the character T is displayed, the trim, ruler and cursor are not merged. The mode switching circuit 10 includes AND gates 22, 23, 25 and 26, NOR gate 24, an inverter 27 and OR gate 28. The character dot patterns on one scan line of one row are sequentially supplied to the OR gate 21. The output line of the OR gate 21 is connected to one input of the AND gates 22 and 23. The normal mode signal is applied to the other input of the AND gate 22, the high intensity mode signal is supplied to the other input of the AND gate 23, and the positive display mode signal is supplied to the input of the inverter 27. The two bits are used to control the luminance of each dot or pel of the character box on the display screen, in the same manner as the prior technology described hereinbefore. The luminance assigned to the two bit combination is, as follows. 0 0 ... Zero luminance (Black level) 0 1 ... Low luminance (Gray level) 1 0 ... High luminance (White level) 1 1 ... Not used The assignment is the same as that in the prior art. The output B of the AND gate 22 is used as the low order bit of the two bit combination. The output B of the AND gate 22 is also supplied to the one input of the NOR gate 24. The output C of the AND gate 23 is supplied to one input of the AND gate 26 and the other input of the NOR gate 24. The output D of the NOR gate 24 is supplied to one input of the AND gate 25. The positive display mode signal is also supplied to the other input of the AND gate 25. The output of the inverter 27 is supplied to the other input of the AND gate 26. The outputs of the AND gates 25 and 26 are supplied to the OR gate 28. The output E of the OR gate 28 is used as the high order bit of the two bit combination. Fig. 3 shows the bit patterns of the character T at the outputs A, B, C, D and E in the various modes in the circuit of the Fig. 2. Dot patterns 31A, 32A, 33A and 34A represent dot pattern at the output A of the merge circuit 9 in the Fig. 2, which are supplied to the mode switching circuit 10 as the input dot pattern in the respective operational mode. In the input dot pattern received by the mode switching circuit 10, the foreground dots, i.e. image dots of the character T are represented by one of the binary numbers, i.e. the binary number 1, respectively, and the background dots of the character T are represented by the other of the binary numbers, i.e. the binary number 0, respectively. In the normal mode of the negative display mode, the normal mode signal is the high level, and both the high intensity mode signal and positive mode signal are the low level. As shown by the dot pattern 31E, the high order bit of the foreground portion of the image is 0, and the low order bit of the foreground portion of the image is 1, thus the foreground image is displayed by the low luminance specified by the two bit combination (0 1). And, the background is displayed by the zero luminance specified by the two bit combination (0 0), wherein the high order bit 0 is picked up from the background portion of the dot pattern 31E and the low order bit 0 is picked up from the background portion of the dot pattern 31B. In the high intensity mode of the negative display mode, the high intensity mode signal is the high level, and both the normal mode signal and positive display mode signal are the low level. The foreground image is displayed by the high luminance specified by the two bit combination (1 0), wherein the high order bit 1 is picked up from the foreground portion of the dot pattern 32E at the output E, and the low order bit 0 is picked up from the foreground portion of the dot pattern 32B. And, the background is displayed by the zero luminance specified by the two bit combination (0 0), wherein the high order bit 0 is picked up from the background portion of the dot pattern 32E, and the low order bit 0 is picked up from the background portion of the dot pattern 32B. Thus, the same luminance as that of the prior art described hereinbefore with respect to the dot patterns 71B, 71c, 72B and 72C in the Fig. 7 is selected in this mode. Describing the positive display mode in accordance with the present invention, in the normal mode, the normal mode signal and the positive display mode signals are the high level, and the high intensity mode signal is the low level in the Fig. 2. The dot patterns at the outputs A, B, C, D and E in this mode are shown by the dot patterns 33A, 33B, 33C, 33D and 33E in the Fig. 3. The two bit combination for controlling the luminance of each dot of the foreground image, i.e. the character T is picked up from the foreground portions of the first dot pattern 33E at the output E and second dot pattern 33B at the output B. In this case, the high order bit 0 is picked up from each dot of the foreground portion of the first dot pattern 33E, and the low order bit 1 is picked up from each dot of the foreground portion of the second dot pattern 33B. Thus, each dot of the foreground image is displayed by the low luminance or gray level specified by the two bit combination (0 1). To control the luminance of each dot of the background, the bit 1 of each dot of the background portion of the first dot pattern 33E is used as the high order bit, and the bit 0 of each dot of the background portion of the second dot pattern 33B is used as the low order bit. Thus, the first and second dots, i.e. background dots of the second scan line L2 are displayed by the high luminance specified by the two bit combination (1 0), the third dot i.e. the image dot of the second scan line L2 is displayed by the low luminance specified by the two dot combination (0 1), and so on. The two bit combination for each dot is supplied to the video circuit 11 which controls the intensity of the scanning beam of the CRT display system 12. In the high intensity mode of the positive display mode, the normal mode signal is the low level, and both the high intensity mode signal and positive display mode signal are the high level in the Fig. 2. The dot patterns at the outputs A, B, C, D and E are shown by the dot patterns 34A, 34B, 34C, 34D and 34E in the Fig. 3. The two bit combination for controlling the luminance of each dot of the foreground image, i.e. the character T, is picked up from each dot of the foreground portions of the first dot pattern 34E and the second dot pattern 34B. In this case, the high order bit 0 is picked up from each dot of the foreground portion of the first dot pattern 34E, and the low order bit 0 is picked up from each dot of the foreground portion of the second dot pattern 34B. Thus, each dot of the foreground image is displayed by the zero luminance or black level specified by the two dot combination (0 0). To control the luminance of each dot of the background, the bit 1 of each dot of the background portion of the first dot pattern 34E is used as the high order bit, and the bit 0 of each dot of the background portion of the second dot pattern 34B is used as the low order bit. Thus, the first and second dots, i.e. background dots of the second scan line L2 are displayed by the high luminance specified by the two bit combination (1 0), the third dot, i.e. foreground dot of the second scan line L2 is displayed by the zero luminance specified by the two dot combination (0 0), and so on. The two bit combination for each dot is supplied to the video circuit 11 which controls the intensity of the scanning beam of the CRT display system 12. It is noted that the background in both the normal and high intensity modes of the positive display mode is displayed by the high luminance, and the luminance of the foreground image is switched between the low luminance in the normal mode and the zero luminance in the high intensity mode. The Fig. 4 shows the example of the display on the screen of the CRT display system 12 in accordance with the present invention. For comparing with the example of the prior display shown in the Fig. 8, the same mixed display as that shown in the Fig. 8 is shown in the Fig. 4. That is, the mark @ in the Fig. 4 is the field attribute representing the high intensity mode, and the mark @ in the Fig. 4 is the field attribute representing the normal mode. It is noted that both the marks @ and @ are actually not displayed on the display screen. In the Fig. 4, although both the normal and high intensity modes are mixedly displayed, the luminance of the entire background is the high intensity, while, in the prior technology, the background areas 82 and 83 are displayed by the high luminance and the background areas 84, 85 and 86 are displayed by the low luminance. The invention solves the illegibility of the screen and the asthenopia or the fatigue of the eyes of the operator caused by the prior technology. The Fig. 5 shows the second embodiment wherein the concept of the present invention is used in a liquid crystal display (LCD). The reference numeral 52 shows one dot which corresponds to one dot shown in the Fig. 3. The one dot 52 includes plural LCD cells, such as LCD cells 52A, 52B, 52C and 52D. Each LCD cell is switched between the first state wherein the liquid crystal material is in an opaque state, and the second state wherein the liquid crystal material is in a transparent state. The liquid crystal material is sandwitched between electrodes on glass plates. The state of liquid crystal material is switched by controlling the voltage levels applied to the electrodes. The two bit combination for each dot is applied to a LCD control circuit 51. When the two bit combination (1 0) is applied, the LCD control circuit 51 controls the voltage levels of the four cells to switch the liquid crystal material of all the cells to the second state, whereby the light from the back side light source is transmitted through the four cells, thus the dot 52A is displayed by the high luminance. When the two bit combination (0 1) is applied, the LCD control circuit 51 controls the voltage levels to switch the liquid crystal material of the two cells to the second state and the liquid crystal material of the remaining cells to the first state, whereby the dot 52B is displayed by the low luminance. When the two bit combination (0 0) is applied to the LCD control circuit 51, the LCD control circuit 51 controls the voltage levels to switch the liquid crystal material of all the cells to the first state, whereby the dot 52C is displayed by the zero luminance. The mode switching circuit 10 of the Fig. 2 in accordance with the present invention receives the negative video signals or the negative dot patterns wherein the foreground dots are represented by the binary number 1 and the background dots are represented by the binary number 0, and responds to the positive display mode signal and one of the normal mode signal and high intensity mode signal to modify the negative dot pattern to generate the two bit combinations which are the control signals for displaying (a), in the normal mode, the foreground dots by the low luminance or the gray level and the background dots by the high luminance or the white level, and (b) in the high intensity mode, the foreground dots by the zero luminance or the black level and the background dots by the high luminance or the white level. The invention is also used to control a plasma display system, an electroluminescence display system, a LED display system, etc. The luminance of the foreground and background dots of a color display system is also controlled in accordance with the invention. The invention solves the problem in the prior display system, i.e., the illegibility of the screen, and the fatigue of the eyes of the operator when both the normal and high intensity modes of the positive display mode are displayed on the screen.

Claims: Display system for displaying an image comprising a plurality of pels, the system comprising: means for displaying, in a normal mode, foreground pels of low luminance and background pels of high luminance and, in a high intensity mode, foreground pels of zero luminance and background pels of high luminance. Display system as claimed in claim 1 wherein the displaying means comprises a signal generating means for generating control signals for controlling a display device, the signal generating means responding to an input signal indicative of the normal mode by generating control signals for displaying foreground pels of low luminance and background pels of high luminance and the signal generating means responding to an input signal indicative of a high intensity mode by generating control signals for displaying foreground pels of high luminance. Display system as claimed in claim 2 wherein the signal generating means generates the control signals in response to an input signal indicative of a positive display mode. Display system as claimed in claim 2 or claim 3 wherein the signal generating means receiveds a pel pattern signal wherein the foreground pels are represented by a 1st binary number and the background pels are represented by a 2nd binary number, the signal generating means generating the control signals by logically combining the pel pattern signal with the input signals indicative of either the normal mode or high intensity mode. Display system as claimed in any of claims 2 to 4 wherein the control signals comprise pairs of binary numbers, a first pair of binary numbers indicating high luminance, a second pair of binary numbers indicating low luminance and a third pair of binary numbers indicating zero luminance. Display system as claimed in any preceding claim wherein the image is made up of a set of characters, groups of pels comprising foreground pels and background pels, forming the characters and wherein each character may be displayed in either high intensity mode or normal mode. Display system as claimed in any preceding claim comprising a cathode ray tube display device. Display system as claimed in any of claims 1 to 6 comprising a liquid crystal display device. Display system as claimed in claim 8 wherein the liquid crystal display device comprises a plurality of liquid crystal cells for each pel and wherein the control signals control the state of the cells of each pel. Display system as claimed in any preceding claim wherein the display system is a data processing system.

Inventors: MINAMI TOSHIYA, SATOH HIROSHI, SATOH TAKANOBU, MINAMI, TOSHIYA, SATOH, HIROSHI, SATOH, TAKANOBU
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: G09G5
IPC codes: G09G5, G09G3