Method and device for switching fixed-length packets such as ATM cells

Abstract: In a packet communication network, a packet switch is designed to process an input transmission frame (A) at V (b/sec) consisting of a transmission overhead (10B) at V OH (b/sec) containing control information for transmission and a payload cells (260B) at V p (b/sec) of c (= a+b) bytes, the cells consisting of a b byte information field containing transmission data and an a byte header field containing a first control information for transmitting the information field. The transmission overhead is removed and a second control information is added to the input transmission frame. The input transmission frame with the second control information and without the transmission overhead is converted to a plurality of inner cell trains (g cells/s) (54) of f (= b+j) bytes length, the inner cell trains consisting of a b byte information field containing the transmission data and a second header field of j (= a+d) bytes consisting of the first control information and the second control information (where f x g = h x V, h is an integer or a fraction of an integer). Packet switching is performed on each inner cell. A plurality of inner cells are converted to an output transmission frame at V (b/sec) having the same format as the input transmission frame.

Description: BACKGROUND OF THE INVENTION The present invention relates to a communication processing device such as a switcher for switching fixed-length packets or a multiplexing device, and in particular to the communication processing device which is capable of supporting an ATM (Asynchronous Transfer Mode) indicated in the CCITT recommendation I.121. Such a digital communication network designed to support the switching of fixed-length packets includes a transmission-line I/O interface, which may be defined so that a cell with a length c (= a+b) consisting of a header field of an a-byte length and an information field of a b-byte length is located on a pay load of a transmission frame consisting of an overhead of V OH (b/s) and the pay load of V P (b/s). For example, the switcher serves to switch only each cell portion of the interface and the multiplexing device also serves to multiplex only each cell portion. If the communication processing device has the foregoing I/O interface, it mainly treats only each cell portion. In this instance, therefore, the communication processing device generally has the main function of: (1) Switching a rate for picking up only a pay load portion from the transmission frame and treating each cell as a train of successive cells, or (2) Entering the I/O interface format to a switch, controlling the action and stop of the switch portion for treating a transmission overhead portion, discontinuously picking up cell portions only by discontinuously operating the switch, and treating them. The foregoing prior art employing the function (1) requires a plurality of clock generation sources since it operates on respective rate sequences for the internal portion and the I/O portion of the switching device. It results in disadvantageously raising the cost. The foregoing prior art employing the function (2) also has a disadvantage that a complicated control system is required for controlling the action and stop of the switch and matching the phase of an input interface to another. In particular, in several places such as the CCITT, the ATM has been under study as a transfer system realizing a wide-band ISDN. The communication processing device such as the switcher designed to support the ATM (referred to as an ATM switcher) or the multiplexing device, in general, includes an I/O interface of a transmission line, which may be defined so that a cell with a length c (= a+b) consisting of a header field of an a-byte length and an information field of a b-byte length is located on a pay load of a transmission frame consisting of an overhead of V OH (b/s) and the pay load of V P (b/s), as indicated in Fig. 7/1.121(C) of the reference document I.121. The communication processing device supporting the ATM, hence, has the foregoing problems. European Patent Application No. EP-A-0 219 049 describes a packet switched communication system with end to end flow control and retransmission in which a plurality of switching nodes serve a plurality of terminals through transmission links. United States Patent No. US 4,782,478 describes a time division circuit switch in which incoming slots are converted into fixed length packets which can be routed through a self-routing switching network in a synchronous manner. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a packet communication method and a packet communication device which are allowed to operate on a single clock rate sequence without having to perform the switching control in a complicated manner. In order to achieve the foregoing object, the present invention provides a packet communication device according to claim 1. Further aspects of the device of the invention are provided according to dependent claims 2 to 6. Further, in order to achieve the foregoing object, the present invention provides a packet communication method according to claim 7. Further aspects of the method of the invention are provided according to dependent claims 8 to 11. In the communication processing device, b, c, f, h and V preferably have the relations of: h x V x 125 x 10 -6 /f = k (k is integer) and b x h x V/f>v x V/x Further, the I/O transmission frame may include a frame format designed according to the CCITT recommendation G.707 to 709 and assume a as five bytes, b as 48 bytes, c as 53 bytes and f as 54 bytes. The switcher is preferably designed so that the header field contained in the inner cell includes information about an output port at which the inner cell is switched, that is, a highway and the switching section serves to switch each inner cell based on the information. According to an aspect of the invention, the packet processing device is designed to convert an I/O transmission frame of totally V(b-sec) consisting of a transmission overhead of V OH (b/sec) and a pay load of V P (b-sec) having a packet of a totally c-byte (c=a+b) fixed length consisting of a header field of an a-byte length and an information field of a b-byte length located on the pay load into an f-byte inner cell train (g cell/sec) containing a b-byte information field (wherein f x g = h x V, h is an integer or a fraction of an integer whereby is meant a value of one divided by an integer), and treating each inner cell. The communication processing device is designed to perform terminal processing such as frame synchronization, detection of a parity check alarm and notification, said terminal processing containing deletion of the transmission overhead contained in the input transmission frame, convert each outer cell into an inner cell of totally f bytes consisting of a header length of j bytes and an information field length of b bytes, assemble an inner cell train (g cell/sec, where f x g = h x V, h is an integer or a fraction of an integer), and treat each inner cell contained in the inner cell train. Assuming that the communication processing device offers the relation of h x V x 125 x 10 -6 /f = k (k is an integer), by counting the inner cells, it is possible to obtain timing information of 8 kHz which is the basic timing of a digital network. Assuming it offers the relation of b x h x V/ f≥b x V/c, it is possible to enhance a utilization rate of the outer cell. Further, assuming that the I/O transmission frame has a frame format designed according to the CCITT recommendation G.707 to 709, a is five bytes, b is 48 bytes, c is 53 bytes, and f is 54 bytes, the communication processing device operates similarly. According to an aspect of the invention, the packet switcher is designed to perform terminal processing such as frame synchronization, detection of a parity check alarm and notification, said terminal processing containing deletion of the transmission overhead contained in the input transmission frame, convert each outer cell into an inner cell of totally f bytes consisting of a header length of j bytes and an information field length of b bytes, assemble an inner cell train (g cell/sec, where f x g = h x V, h is an integer or a fraction of an integer). It includes a switching section, which serves to switch the inner cell contained in the inner cell train. Assuming that the header field of the inner cell contains information about an output port at which the inner cell is switched, the switching section serves to switch each inner cell based on the information. This assumption makes it possible to reduce the number of interface lines in the switcher. As set forth above, the present invention can realize a communication processing device such as a packet switcher which is capable of operating on a single clock rate sequence without having to perform the switching control in a complicated manner. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing arrangement of an ATM switcher according to an embodiment of the invention; Fig. 2 is a view illustrating cell structures provided on a transmission line and inside of the switcher; Fig. 3 is a view detailing the cell structure provided inside of the switcher; Fig. 4 is a block diagram showing arrangement of a transmission line interface on a receiving side; Fig. 5 is a block diagram showing arrangement of a transmission line interface on a transmitting side; and Fig. 6 is a view illustrating a frame format of SDH (Synchronous Digital Hierarchy). DESCRIPTION OF THE PREFERRED EMBODIMENT A description will be directed to an ATM switcher designed according to an embodiment of the present invention. Fig. 1 shows arrangement of an essential portion of the ATM switcher designed according to the embodiment. Herein, for convenience's sake, assume that the ATM switcher is designed to accommodate 256 I/O interface lines of 155.52Mb/s. As shown in Fig. 1, 3 denotes a switching section for switching cells, 2 denotes a receiving-side transmission-line interface section, and 4 denotes a transmitting-side transmission-line interface section for matching a transmitting interface with the transmission line. The receiving-side transmission-line interface section 2 provides a received cell buffer 21 and the transmitting-side transmission-line interface section 4 provides a transmitted cell buffer 41. 111 and 112 denote I/O transmission line interfaces and 121 and 122 denote internal highways. Next, with reference to Fig. 2, the operation of the ATM switcher will be described. The I/O transmission line interfaces 111, 112 are designed so that the transmission format complies with the G.707 to 709 and the cell structure is 53B consisting of a header length of 5B and an information field length of 48B (see Fig. 2A). The ATM switcher serves to switch a cell train located on the I/O transmission lines into an inner cell train (see Fig. 2B) located on inner highways 121, 122 of totally 54B consisting of a header length of 6B and an information field length of 48B and switch the inner cells with each other on the switching section 3 as the switcher is controlling the write and read of the received cell buffer 21 and the transmitted cell buffer 41. The buffer 21 is located in the receiving-side transmission interface section 2 and the buffer 41 is located in the transmitting-side transmission interface section 4. Fig. 3 shows the arrangement of the inner cell in detail. As shown in Fig. 3, the inner cell contains an additional one-byte (d-byte) header and an outer cell. The additional one-byte header has an output port number indicating an inner highway 122 to which the switching section 3 outputs the inner cell. The switching section 3 serves to route the inner cell to the output port indicated by the output port number. A frame format of SDH (Synchronous Digital Hierarchy) will be shown in Fig. 6. Next, Fig. 4 shows arrangement of the receiving-side transmission-line interface 2. The receiving-side transmission-line interface section 2 provides the received cell buffer 21, a header conversion table 23, a fixed delay section 24, and a header/information selector 25. The outer cell train transmitted on the input transmission line 111 is written in the received cell buffer 21 in synchronization to a write enable signal 201 and a write head signal 202. In the received cell buffer 21, only the cell portion is written. The write enable signal 201 indicates a pay load portion located on the input transmission line and the write cell head signal 202 indicates a head position of each outer cell located on the input transmission line 111. Both signals are extracted on a timing from the input signal on the receiving-side transmission line by a transmission frame terminal section (not shown) for performing some kinds of processing such as frame synchronization, detection of a parity check alarm and notification. The header portion and the information field portion are read from the received cell buffer 21 in synchronization to a readout cell head signal 203. The readout cell head signal 203 is generated on each inner-cell-delimiting timing placed on the inner highway 112 by a switcher timing generating section (not shown). The header portion is transmitted to the header conversion table 23 and the information field portion is transmitted to the fixed delay section 24. The header conversion table 23 serves to retrieve a header value to be updated and an additional header to be added from the header portion and then to transmit the information about the inner header used for the switcher to the header/information selector 25. Herein, the header value indicates a channel to which each cell belongs and the update of the header value indicates the conversion of a channel identification code, for example, on the input transmission line into a channel identification code, for example, used in the switcher. The information field portion transmitted to the fixed delay section 24 waits for a time required for accessing the header conversion table and a time corresponding to the additional header and then is sent to the header/information selector 25. The header/information selector 25 serves to merge the inner header portion with the information field portion and then send out the result as an inner cell train to the receiving-side inner highway 121. When the outer cell is converted into the inner cell as mentioned above, the input transmission line 111 has a different cell rate than the inner highway 121. It is thus necessary to insert an empty cell as an inner cell. That is, if no cell to be read exists in the buffer when reading the received cell buffer 21, the reading is controlled so that an empty cell is inserted to the inner cell train. The empty cell is discarded in the switching section 3. As is understood from the fact that the inner cell structure and the inner highway structure are referenced by 121 and 122 in Fig. 1, a clock 200 used in the series of operations such as writing and reading can be assumed as a single cell rate sequence. Then, Fig. 5 shows the arrangement of the transmitting-side transmission-line interface section 4. As shown, the transmitting-side transmitting-line interface section 4 provides the transmitted cell buffer 41. When the inner cell train is written from the transmitting-side inner highway 122 to the transmitted cell buffer 41 based on a written cell head signal 204, only the portion 53B is written therein, that is, the additional header is excluded. The written cell head signal 204 is generated on each inner-cell-delimiting timing placed on the inner highway 112 by the switcher timing generating section. The outer cell train is read out of the transmitted cell buffer 41 in synchronization to a readout enable signal 205 and a readout cell head signal 206 and then is sent to the pay load portion of the output transmission frame. The readout enable signal 205 indicates the pay load portion located on the output transmission path 112 and the readout cell head signal 206 indicates the head position of each outer cell located on the output transmission line 112 and both signals are generated in the transmission frame terminal section. As is understood from the fact that the inner cell structure and the inner highway structure are referenced by 121 and 122 in Fig. 1, a clock 200 used in the series of operations such as writing and reading can be assumed as a single cell rate sequence (the same cell rate sequence as the receiving side). The cell rate given on the transmitting-side inner highway 122 is 45 cell/125µs and the cell rate given on the output transmission line 112 is about 44.15 cell/125µs or a bit more. For preventing instant overflow of the transmitted cell buffer 41, it is necessary to provide a mechanism for giving back a buffer busy signal 207 to the switching section 3 and temporarily stopping the transmission of the inner cell from the switching section 3 when the transmitted cell buffer- 41 is busy. In general, however, the switcher itself and the I/O transmission line are subject to at most 70 to 80% utilization rate. The mechanism is thus effected only when failure takes place. The switcher whose utilization rate is limited may reduce this mechanism. According to the present embodiment, as described above, the ATM switcher can have the same cell rate sequence on both the I/O transmission line and the inner highways so that the cell rates are allowed to be same on the transmission line and the inner highways. If a simple buffer is provided, it is possible to switch the outer cell train located on the I/O transmission line to the inner cell train located on the inner highways or vice versa. It results in arranging the ATM switcher without having to provide a mechanism for complicated controls such as multiple-clocks control or intermittent control of the switching. Moreover, by inserting routing control information such as an output port number to an additional area of the inner header, the number of interface lines can be made smaller than the system for passing the routing control information on another line. And, since the inner cell length is assumed to be a fraction of an integer of bytes within the I/O transmission line of 125µs, inside of the switcher, the timing information of 8 kHz, which is a basic timing of a digital network included in the transmission line frame, can be easily referenced by counting a cell-delimiting timing. It results in offering an effect that it allows a band to be easily assigned to a switch output port if the existing digital communication (e.g. a voice of 64 Kb/s) is provided on the ATM switcher for switching the line (The voice of 64 Kb/s is controlled to be output at each 2160 cells). In the foregoing description of the embodiment, assuming that the transfer rate of the I/O transmission frame is V (b/sec), the outer cell length is c bytes, the information field of the inner or outer cell is b bytes, the inner cell length is f bytes, and the transfer rate of the inner cell is g cell/sec, the embodiment has met the relations (1) f x g - h x V (h is an integer or a fraction of an integer), (2) h x V x 125 x 10 -6 (k is an integer), and (3) b x h x V/f≥v x V/c. Yet, it may be designed to meet the relation (1) only, in which case the clock rate given on the I/O transmission line and the clock rate given on the inner highway can be placed on the same rate sequence. Further, it may be designed to meet the relations (1) and (2) only, in which case the timing information, that is, a basic timing of 8 kHz of a digital network included in the transmission line frame can be easily referenced by counting the cell-delimiting timing even within the switcher. And, if it meets the relations (1), (2) and (3) like the foregoing embodiment, it results in enhancing a utilization rate of the outer cell. As has been understood from the above description, the communication processing device related to the invention has been described with reference to the ATM switcher. It goes without saying that the invention may be applied to a multiplexing device and a general packet switcher in addition to the ATM switcher. In the applications, the processing of the inner cell makes it possible to provide the similar effect. As described above, the present invention can offer a communication processing device such as a packet switcher which is capable of operating on a single clock rate sequence without having to perform the switching control in a complicated manner.

Claims: A packet communication device (1) comprising: transmission frame receiving means (2) for receiving a transmission frame with a first speed comprising a transmission overhead and a payload containing a plurality of fixed length packets of a first byte length including a header of a second byte length and an information field of a third byte length, and packet processing means (3) for processing said plurality of fixed length packets, characterized in that said packet communication device further comprises: removing means (21, 200-202) for removing said transmission overhead from said transmission frame input thereto, fixed length packet conversion means (23-25, 200, 203) for converting said plurality of fixed length packets into inner cells of a fourth byte length by adding an additional byte of a fifth byte length to said header and for outputting a train of said inner cells with a second speed such that a value of said fourth byte length multiplied by said second speed is equal to a value of said first speed multiplied either by an integer or by a value of one divided by an integer. A packet communication device according to claim 1, characterized in that said processing means (3) comprises switching means for switching said plurality of packets, the transmission frame receiving means (2) receives said transmission frame at a speed V byte/sec, said payload contains a plurality of c-byte, fixed length packets, each including a header of an a-byte length and an information field of a b-byte length, said fixed length packet conversion means (23-25, 200, 203) provides means for converting each of said plurality of fixed length packets into an inner cell of an f-byte length comprising a header of a j-byte length formed by adding an additional byte of a d-byte length to said header of an a-byte length and said information field of a b-byte length and for outputting a train of the inner cells of a speed g cell/sec such that said inputted transmission frame is converted into said train of inner cells so as to satisfy the relationship f x g = h x V where h is an integer or a value of one divided by an integer, said switching means being means for receiving said train of inner cells, for performing a switching processing of said inner cells, and for outputting the processed train of inner cells, and the device comprises transmitting means for transmitting a transmission frame at said speed V, said transmission means comprising output means (4) including reverse-converting means (41) for converting said train of inner cells to said transmission frame. A packet communication device according to claim 2, characterized in that said additional byte of a d-byte length contains information indicating an address to which the inner cell is switched in said switching means (3). A packet communication device according to claim 2 or claim 3, characterized in that the values of h, c, f, h, and V meet at least one of the relations of h x V x 125 x 10 -6 /f = k, where k is an integer, and b x h x V/f ≥ b x V/c. A packet communication device according to any one of claims 2 to 4, characterized in that said transmission frame includes a frame format designed according to the CCITT recommendation G.707 to 709, and the value of said a-byte length is 5 bytes, said b-byte length is 48 bytes, said c-byte length is 53 bytes, and said f-byte length is 54 bytes. A packet communication device according to claim 1, characterized in that the transmission frame receiving means (2) receives said transmission frame at a speed V byte/sec comprising said transmission overhead of a speed V OH byte/sec, and said payload at a speed V P byte/sec, said payload contains a plurality of c-byte, fixed length packets, each including a header of an a-byte length and an information field of a b-byte length, said fixed length packet conversion means provides means for converting each of said plurality of fixed length packets into an inner cell of an f-byte length comprising a header of a j-byte length formed by adding an additional byte of a d-byte length to said header of an a-byte length and said information field of a b-byte length and for outputting a train of the inner cells of a speed g cell/sec such that said inputted transmission frame is converted into said train of inner cells so as to satisfy the relationship f x g = h x V where h is an integer or a value of one divided by an integer, and said fixed length packet conversion means (23-25, 200, 203) outputs said train of inner cells to said packet processing means (3). A packet communication method comprising the steps of: receiving a transmission frame of a first speed, said transmission frame comprising a transmission overhead and a payload comprising a plurality of fixed length packets of a first byte length including a header of a second byte length and an information field of a third byte length, removing said transmission overhead, converting said plurality of fixed length packets into inner cells of a fourth byte length by adding an additional byte of a fifth byte length to said header, outputting a train of said inner cells with a second speed such that a value of said fourth byte length multiplied by said second speed is equal to a value of said first speed multiplied by either an integer value or a value of one divided by an integer value, and processing said plurality of fixed length packets. A packet communication method according to claim 7, characterized in that said transmission frames are received at a speed V byte/sec, said payload contains a plurality of c-byte fixed length packets, each including a header of an a-byte length and an information field of a b-byte length and said method further comprises the steps of: converting each of said plurality of fixed length packets into an inner cell of an f-byte length comprising a header of a j-byte length formed by adding an additional byte of a d-byte length to said header of an a-byte length and said information field of a b-byte length, outputting a train of inner cells of a speed g cell/sec such that said inputted transmission frame is converted into said train of inner cells so as to satisfy the relationship f x g = h x V where h is an integer or a value of one divided by an integer, performing a switching processing of the train of inner cells, and converting the train of inner cells to a transmission frame and transmitting said transmission frame at said speed V. A packet communication method according to claim 8, characterized in that said additional byte of a d-byte length contains information indicating an address to which the inner cell is switched in said switching processing. A packet communication method according to claim 8 or claim 9, characterized in that the values of h, c, f, h, and V meet at least one of the relations of h x V x 125 x 10 -6 /f = k, where k is an integer, and b x h x V/f ≥ b x V/c. A packet communication method according to any one of claims 8 to 10, characterized in that the transmission frame includes a frame format designed according to CCITT G.707 to 709, and said a-byte length is 48 bytes, said b-byte length is 48 bytes, said c-byte length is 53 bytes and said f-byte length is 54 bytes.

Inventors: GOHARA SHINOBU, TORII YUTAKA, GOHARA, SHINOBU, TORII, YUTAKA, GOHARA, SHINOBU, HITACHI MAIOKA DAIICHI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1990
Main classification: H04L12
IPC codes: H04Q3, H04L12