Apparatus and a method for automatically centering a video zoom and pan display

Abstract: A video zoom and pan system is disclosed in which a viewer may specify a portion of a source image to be magnified by incrementally changing a center point (51,52, 55,56)- relative to the source image - for the magnified image, and a magnification factor (58,59). The viewer may pan around the source image, by changing the center point, to select the portion to be magnified. The system monitors (241,242,243,244,248) the relative values of the center point coordinates (HC,VC) and the magnification factor (ZR) and adjusts (218,223) the center point coordinates to prevent blanking intervals of the source image from being displayed as part of the magnified image. The invention is described in terms of three embodiments, two hardware embodiments, which use sub-pixel resolution in specifying the center point, and a combined hardware-software embodiment in which the center point is specified with multi-pixel resolution.

Description: The invention concerns a video signal processing apparatus including the means recited in the preamble of claim 1. From US-A-4,725,960 a method of sizing an image on a graphic display for a numerical controller is known whereby a microcomputer obtains a magnification for image drawing and center coordinates of an image drawing space such that maximum and minimum coordinate values entered through a key input means will be put in the display screen. Based upon such a magnification and center coordinates, the locus of a tool or the like is drawn on the display screen. In parallel with the above drawing process, the microcomputer obtains maximum and minimum coordinate values of the NC command program. When a predetermined command is entered through the key input means after completion of the above drawing process, the microcomputer obtains such a magnification for image drawing and center coordinates of the image drawing space that the maximum and minimum coordinate values of the NC command program obtained in parallel with the above drawing process will be contained in the display screen. Based upon the thus obtained magnification and center coordinates, the locus of a tool or the like is drawn on the display screen. Further, from US-A-4,774,581 a television picture Zoom system is known relating to a circuitry that produces a magnificant image representing a portion of a video frame from a conventional television signal. The portion of the field which is magnified, hereinafter referred to as the source portion, is determined by signals provided via viewer controls. These controls define the upper left corner of the image, in terms of horizontal and vertical pixel positions in the unmagnified field, and a magnification factor to be used to produce the magnified display. In this referenced patent, the upper left corner of the source portion is used as a reference point when the magnification factor is changed or when the source portion is panned around the unmagnified field. However, this may not be the best reference point. Intuitively, a viewer manipulating the controls would expect the center of the image to be the reference point since this is the reference used by mechanical zoom apparatus such as photographic zoom lenses. If, for example, the upper left corner of a source portion were used as the reference point, an object of interest in the center of the picture may be moved out of the display when the magnification factor is increased. From the point of view of the circuit designer, it is more convenient to provide the pixel positions of the upper left corner of the portion of the image to be magnified to the zoom and pan system. If, for example, the portion of the image being magnified were near an edge of the frame and the magnification factor were reduced, maintaining a constant center position would cause portions of the video signal outside of the active video region (i.e. the horizontal or vertical blanking intervals) to be included in the magnified display. Moreover, it is easier to determine the allowable limits of the source portion during a pan operation when the upper left corner is used as the reference point than when the image center is used as the reference point. The object of the invention is to provide for means allowing a viewer of a television apparatus to more convenient make use of the magnification feature thereof. Starting from the above mentioned US-A-4,774,581 to which the preamble of claim 1 refers, this object is being solved by the characterizing features of that claim. Particular improvements and embodiments of the invention are being characterized in the subclaims. The present invention is embodied in apparatus and a method for selecting a part of a field of an input video signal to be used to produce a magnified image. This apparatus includes control circuitry which allows a viewer to select the center position of the selected part, and the magnification factor to be used to produce the magnified image. Monitoring circuitry is included in the apparatus to limit the boundaries of the selected part to be within the active video portion of the input signal. This monitoring circuitry is responsive to the horizontal and vertical coordinates of the selected center position as well as to the selected magnification factor. FIGURE 1 is a block diagram of a television receiver which includes an image zoom feature. FIGURE 1a is a diagram of a zoom system control suitable for use with the television receiver shown in FIGURE 1. FIGURE 2 is a block diagram of an output controller suitable for use in the television receiver shown in FIGURE 1. FIGURE 3 is a block diagram of a portion of an alternative output controller which limits the magnification factor selected by the viewer. FIGURES 4, 5A and 5B are block diagrams of other portions of the alternative controller which limit the horizontal and vertical starting positions selected by the viewer. FIGURE 6 is a block diagram of circuitry which augments the controller shown in FIGURES 3, 4, 5A and 5B. FIGURE 7 is a block diagram of a second alternative output controller which limits the magnification factor and vertical and horizontal starting positions selected by the viewer. FIGURES 8, 9 and 10 are flow chart diagrams useful for explaining the operation of the controller shown in FIGURE 7. The following is a brief description of the zoom system described in the above referenced U.S. Patent US-A-4,774,581 which provides a context for the present invention. In FIGURE 1, a composite video signal, provided by a source 10 which, may include a conventional television tuner, provides a composite video signal to an analog to digital converter (ADC) 14. The ADC 14 digitizes this signal and applies it to a field memory 16. The memory 16 is responsive to signals provided by a memory sequencer 18 and by a write address generator 20 to write samples representing image pixels into the field memory 16. These samples are read from the memory 16, after a suitable delay, responsive to address values provided by a read address generator 22. The sampled data composite video signal provided by the memory 16 is separated into luminance (Y) and chrominance (C) signal components by Y/C separation circuitry 27. The luminance and chrominance components are applied to respective vertical interpolator circuits 28 and 32. The interpolators 28 and 32 insert additional lines between the lines of the respective video signals provided by the circuitry 27 to effect the requested vertical magnification. The chrominance vertical interpolator 32 also separates the chrominance signal into in-phase (I′) and quadrature-phase (Q′) color difference signal components. The vertically interpolated luminance signal is applied to hanging dot correction circuitry 29 which removes distorting signal artifacts, introduced in the Y/C separation process, to produce an output signal Y′. The signal Y′ is applied to a luminance signal horizontal interpolator 30 and the signals I′ and Q′ are applied to a color difference signal horizontal interpolator 34. The interpolators 30 and 34 insert interpolated samples between the samples of the respective signals Y′ and I′, Q′ to effect the horizontal magnification requested by the viewer. In the above-referenced patent, the portion of the video signal provided by the source 10 which is to be used to produce the magnified image is defined by three signals provided via viewer controls 24, indicated in phantom. These signals are a vertical position value, VPOS, a horizontal position value, HPOS and a zoom ratio value, ZR. The signals VPOS and HPOS respectively define a line interval of the video field held in the memory 16 and a sample in that line interval which are at the upper left corner of the image to be magnified. The signal ZR defines the magnification factor to be used. This value is not, itself a magnification factor but the denominator of a fraction 256/ZR which is the magnification factor. The signal VPOS and ZR are used by the read address generator 22 while the signals HPOS and ZR are used by the horizontal interpolators 30 and 34 to produce the magnified image. Those persons skilled in the art of digital video signal processing will readily appreciate that in the more general case both starting addresses HPOS and VPOS will be applied to the read address circuitry. In addition a signal ZR or a signal representing the desired magnification will be coupled to the read address circuitry to establish the rate at which read addresses are generated. Nominally only the signal ZR or signals representing ZR will be coupled to the vertical and horizontal interpolators. Note signals representing ZR may be, for example, interpolator coefficients which may be provided by preprogrammed read only memories addressed by the values ZR. In the present embodiments of the invention, the viewer controls 24 are replaced by an output controller 25. The controller 25 is responsive to viewer controls 23 which allow a user to specify the center of the source portion of an image and a magnification factor to be used to produce an output image. The controller 25 converts signals provided by these controls into the signals HPOS, VPOS and ZR. The controller 25 ensures that the magnified image includes only active video information, and the signals it produces properly track viewer commands to change the center of the source portion as the source portion is panned around the input field. FIGURE 1A is a diagram of an exemplary viewer control 23. These controls include vertical up and down center position controls, 51 and 52, respectively, horizontal left and right center position controls, 55 and 56, respectively, and zoom-in and zoom-out step controls 58 and 59, respectively. A reset button 57 may also be provided. By pressing one of the control buttons 51, 52, 55, and 56, the viewer incrementally changes the horizontal and vertical center positions of the target image. By pressing one of the control buttons 58 and 59, the viewer incrementally increases and decreases the applied magnification factor. A constant center position is maintained while the magnification factor is changed. However, this center position may be adjusted if a decrease in magnification would cause a portion of the image beyond the raster boundaries to be displayed. By pressing the reset button, 57, the viewer may return the displayed image to a preset center position and magnification factor, for example, one to one magnification and centered in the center of the input field. Two different hardware implementations and one combined hardware and software implementation of the output controller 25 are described below. To understand the operation of these controllers, it is helpful to first understand some mathematics used by the controllers. The zoom system shown in FIGURE 1 is designed for an exemplary video image having 768 active pixels per horizontal line interval, and 256 active line intervals per field. It is understood that the methodology employed may be used for displays with different numbers of pixels per line interval and different numbers of line intervals per field. Ten-bit data values are used to identify a horizontal pixel position. Similarly, eight-bit data values are used to identify the line interval in which a pixel resides. During the zooming process, when the magnification factor is changing, it is desirable to maintain the appearance of a smooth, continuous transition, although the displayed image is changing in discrete steps. As the number of intermediate steps grows larger, the change appears smoother. Moreover, it is desirable to create a relatively large number of virtual positions located between the actual pixels, in order to identify a unique value for each pixel in the magnified display. To these ends, 256 virtual positions are defined between each pair of pixels in a scan line and between each pair of scan lines. These virtual positions are used to define the relative positions of the pixels and lines which constitute the magnified display. However, these virtual positions are grouped into a smaller number of interstitial positions for interpolation. In the embodiments of the invention described below, 15 interstitial pixel values may be interpolated between each pair of contiguous pixels, with a sixteenth position located at the pixel center. Likewise, each pair of horizontal scan lines has 16 interstitial line positions. Four additional bits are used to specify the interstitial pixel or line location with the required precision. Output controller 25, therefore, specifies HPOS as a 14-bit signal and VPOS as a 12-bit signal. The maximum magnification is attained when each virtual pixel position in the zoom region is mapped to one pixel in the displayed image. This corresponds to 1/65,536th [i.e. 1/(256 * 256)] of the original picture being displayed. The magnification factor is an eight-bit value, thus, 256 different magnification steps are allowed. Since the most of the steps correspond to non-integer magnification levels, it is convenient to define a zoom ratio signal, ZR, related to the magnification in which each value of the signal ZR corresponds to a unique magnification value and the values of ZR are integers ranging from one to 256. To determine the unique zoom ratio value for any magnification level, it is only necessary to determine the fraction of the image, along a linear dimension, which is displayed and multiply by the maximum magnification value (in this case 256). In order to store the information in eight bits, rather than nine, one is subtracted from each value of the signal ZR as per the above computation, making the range of the signal ZR between zero and 255. The magnification factor, MF, is defined in terms of the signal ZR by equation (1). MF = 256 / (ZR+1) (1) Since this magnification factor is applied uniformly across the displayed region, a pair of center point coordinates and a ZR value will uniquely define the horizontal and vertical pixel positions, HPOS and VPOS, of the upper left corner of the image. The general relationship is defined by equations (2) and (3), and the specific relationship for a 768 x 256 display is defined by equations (4) and (5). HPOS = HC - (NHP * NIP) / (2 * MF) (2) VPOS = VC - (NVL * NIP) / (2 * MF) (3) HPOS = HC - (24) (ZR+1) (4) VPOS = VC - (8) (ZR+1) (5) In these equations, HPOS is the starting horizontal position, VPOS is the starting vertical position HC is the horizontal center, VC is the vertical center, ZR is the selected zoom ratio, NHP is the number of pixels in a horizontal scan line. NVL is the number of vertical lines in the display and NIP is the number of interstitial positions between any two lines or any two pixels, plus one. In addition to allowing the user to specify a center point and a zoom factor, the output controller 25 includes circuitry which automatically corrects the center point of the viewed region so that raster boundaries are not crossed and only active video is displayed. If the magnification factor, MF, is increased while the center point of the magnified image is held at the center of the source image, only active video information will be displayed. However, once the center point of the generated image is moved away from the center of the source image, demagnification may eventually result in the display of non-active video information, i.e. the horizontal and vertical blanking intervals. The general relationship defining the valid horizontal and vertical center positions is given by the inequalities (6) and (7) while the specific relationship for a 768 pixel by 256 line display is given by the inequalities (8) and (9). (NHP*NIP)/(2*MF) ≦ HC ≦ NHP*NIP*(1 - 1/(2*MF)) (6) (NVL*NIP)/(2*MF) ≦ VC ≦ NVL*NIP*(1 - 1/(2*MF)) (7) 24 * (ZR+1) ≦ HC ≦ 12288 - 24 * (ZR+1) (8) 8 * (ZR+1) ≦ VC ≦ 4096 - 8 * (ZR+1) (9 ) FIGURE 2 is a block diagram showing components of an output controller 25 suitable for use in a first embodiment of the invention. This controller accepts the incremental signals provided by the viewer controls 23 and produces signals ZR, HPOS and VPOS for application to the zoom system as shown in FIGURE 1. To change the magnification factor, the output controller 25 accepts up and down incremental zoom control signals from the viewer controls 58 and 59, respectively. These control signals are applied to a zoom controller 212 which converts the signals into pulses that respectively decrement and increment the value held in an 8 bit up-down counter 213. The output signal of the counter 213 is the signal ZR. The horizontal center controller 216 accepts left and right control signals provided by the viewer controls 55 and 56. These signals are converted into pulse signals which respectively decrement and increment a horizontal center counter 217. The output signal provided by the counter 217 is the horizontal center signal, HC. In the same way, a vertical center controller 221 receives up and down control signals from the viewer controls 51 and 52. The controller 221 converts these signals into pulse signals which respectively decrement and increment a vertical center counter 222. The output signal of the counter 222 is the vertical center signal, VC. Circuitry which includes an adder 241, multipliers 242 and 243, digital value sources 241a, 242a and 243a and a subtracter 244 produce the signal HPOS at the output port of the subtracter 244 according to the equation (4) set forth above. Similarly, the adder 241, the multiplier 242, digital value sources 241a and 242a and a subtracter 248 produce the signal VPOS at the output port of the subtracter 248 according to the equation (5) set forth above. The signal HPOS is compared, in a comparator 218, to a signal HL which is defined by equation (10). HL = 48 * (255 - ZR) (10) The signal HL is generated by a subtracter 245, multipliers 246 and 247 and digital value sources 245a, 246a, and 247a. The signal HL defines the right pixel limiting value for the image. If HPOS is greater than HL, a portion of the horizontal blanking interval will be displayed on the right side of the reproduced image. The left pixel limiting value for the image is zero. The comparator 218 performs the validity check set forth above in reference to equation (8) when equation (2) is used to convert the signal HC to the signal HPOS. When the comparator 218 detects that the signal HPOS is greater than HL or less than zero, it applies a logic-one signal to the horizontal center controller 216. The controller 216 is also coupled to receive a signal, 225, provided by the counter 217. The signal 225 indicates whether the value of the signal HC is on the left or right of horizontal center of the source image, that is to say, whether the value of the signal HC is respectively less than or not less than 6144 (1800 hexadecimal). There are 12288 (768 * 16) pixels and interstitial pixels on each line of the source image. The signal 225 may be generated as the logical OR of the most significant bit (MSB) of the 14-bit signal HC with the logical AND of the next two less significant bits of the signal HC. Responsive to these two signals, the horizontal center controller 216 conditions the counter 217 to increment its value if HPOS is invalid and HC is in the left half of the source image and to decrement its value if HPOS is invalid and HC is in the if the right half of the source image. Otherwise, the controller 216 increments or decrements the counter 217 as requested by the viewer. The subtracter 245, multiplier 246 and digital value sources 245a and 246a are used to generate a vertical limiting signal, VL, which is defined by equation (11). VL = 16 * (255 - ZR) (11) The signal VL represents the largest line number or interpolated line number which can be at the top of an image for a given zoom ratio. The vertical position signal VPOS is compared to the signal VL by a comparator 223. The comparator 223 provides a logic-one output signal when the signal VPOS is greater than VL or when it is less than zero. the output signal of the comparator 223 is a logic-zero otherwise. The output signal of the comparator 223 is coupled to the vertical center controller 221. The controller 221 is also coupled to receive a signal 226 from the counter 222 which indicates that the signal VC represents a line in the upper or lower half of the source image. This signal has a logic-one value, for example, when the signal VC is greater than 2048 (800 hexadecimal) and a logic-zero value when the signal VC is less than or equal to 2048. There are 4096 (256 * 16) lines and interstitial lines in a field of the source image. The signal 226 may be, for example, the most MSB of the signal VC. When the comparator 223 indicates that VPOS is invalid and the signal 226 indicates that the current vertical center is in the upper half or the lower half of the source image, the vertical center controller 221 conditions the counter 222 to respectively increment or decrement its value. When the comparator 223 indicates that VPOS is valid, the controller 221 conditions the counter 222 to increment or decrement its value as requested by the viewer. FIGURE 3 shows the details of a portion of an alternative output controller 23 which may be used to replace step control 212 and 8-bit counter 213, shown in FIGURE 2. In the discussion of the previous embodiment of the invention, the only zoom control option for the viewer was to request an increase or a decrease in the value of ZR. FIGURE 3 shows a circuit which will allow a user to change ZR or to reset ZR to a predetermined value. Switching to an absolute ZR value allows an instantaneous transition from one magnification factor to another without stepping through the intermediate magnification factors. A typical use for such a feature would be to implement a reset feature as discussed above in reference to the reset button 57 of the viewer controls 23. In these embodiments of the invention, a reset may be achieved by setting the signal ZR to 255. This reset button may also be coupled to condition the horizontal and vertical control circuitry to set HPOS and VPOS to zero, as shown below in reference to FIGURES 5A and 5B. FIGURE 3 shows a circuit which receives a signal DZ indicating a requested change in the magnification factor. This signal is generated, for example, by viewer manipulation of the magnification step controls 58 and 59. A value of -1 is provided when the control button 58 is pressed to increase the magnification factor and a value of +1 is provided when the control button 59 is pressed to decrease the magnification factor. The signal DZ is added to the zoom ratio signal ZR by an adder 310. The sum provided by the adder 310 is a user requested zoom ratio, Z2. The signal Z2 is applied to a Limiter 311 which ensures that the requested value of ZR is within range and corrects the value as necessary. For the range of the signal ZR set forth above (0 to 255), the limiter may be eliminated since the signal ZR is kept within these limits by virtue of it being an eight-bit signal. It may be desirable to limit the lower value of the signal ZR to a value such as 51, to limit the maximum magnification factor to five. In this instance, the limiter 311 would establish a lower limit of 51 for the signal provided by the adder 310. The signal Z3, provided by the limiter 311, is applied to one input port of a multiplexor 312. An absolute value, A1, for the signal ZR is applied to another input port of the multiplexor 312. The control input terminal of the multiplexor is coupled to receive an absolute/differential mode signal ADM1. The signal ADM1 may be provided, for example, by the reset control button 57 of the viewer controls 23, shown in FIGURE 1A. Responsive to the signal ADM1, the multiplexor 312 passes either the signal Z3 or the value A1. The multiplexor 312 applies its output signal Z4 to a synchronizing latch 313. The latch 313 synchronizes the signal Z4 to the system clock signal (not shown). The output signal of the latch 313 is the zoom ratio signal, ZR, which is provided by the output controller 25 as shown in FIGURE 1. The signal ZR is also applied to the adder 310, for use in processing further zoom changes, and it is passed on to latch 314 and to one input port of a subtractor 315. In this embodiment of the invention, the latch 314 is a delay element which provides a delay of one cycle of the viewer control update clock. Typically, this clock is relatively slow, having a period on the order of a centisecond to allow the viewer to stop the zoom at any level. By subtracting the signal Z5 from the signal ZR, the zoom differential, Z6, between the current and previous values of the signal ZR may be determined. The signal Z6 may differ from the user requested zoom differential signal Z1 if the limiter 311 has made adjustments or if the system has been reset. The zoom differential signal, Z6, is used in the circuit shown in FIGURE 4 to adjust the values of the signals HPOS and VPOS. FIGURE 4 shows a circuit which corrects user requested changes to the signals HPOS and VPOS to account for changes in the zoom ratio signal ZR. The signal Z6 is stored in a synchronizing latch 415. The output signal, Z7, of latch 415 is applied to two parallel circuits which determine the adjustments to the signals HPOS and VPOS, respectively. This circuitry maintains a substantially constant image center position when the magnification factor is changed. The signal Z7 is multiplied by 24 by a shift-and-add circuitry which includes bit-shifters 416 and 418 and an adder 417. The signal provided by the shifter 418 is subtracted, by a subtractor 419, from a requested horizontal differential signal, DX, to produce a corrected horizontal differential value DX′. In the same manner, a subtractor 421 subtracts a signal representing eight times the signal Z7 from a requested vertical differential circuit DY to produce a corrected differential circuit DY′. The resulting differential horizontal and vertical signals are applied to circuitry such as that shown in FIGURES 5A and 5B which generates the respective signals HPOS and VPOS for the zoom system shown in FIGURE 1. FIGURE 5A shows the details of a viewer control interface which may be used to replace the horizontal center controller 216 and the horizontal center counter 217, described above in reference to FIGURE 2. This circuit allows a user either to increment or decrement the signal HC or to substitute an absolute HC value for the current HC signal. FIGURE 5B shows circuitry of the same type which performs the same functions for the vertical center signal VC. In the circuitry shown in FIGURE 5A, the signal DX′, provided by the adder 419 of FIGURE 4 is applied to one input port of an adder 512. Another input port of the adder 512 is coupled to receive the signal HPOS. The output signal of the adder 512 is a user requested horizontal position signal, X3. The signal X3 is range checked in a limiter 513. The limiter 513 ensures that the new sum is non-negative and no greater than the total number of pixels and interstitial pixels in a scan line (i.e. 12288). The output signal, X4, of limiter 513 is applied to one input port of a multiplexor 514. Another input port of the multiplexor 514 is coupled to receive an absolute horizontal position value, A2. The multiplexor 514 is conditioned by a control signal ADM2, which may be the same as the signal ADM1, to pass either the signal X4 or a preset absolute value, A2. The output signal, X5, of the multiplexor 514 is stored in a synchronizing latch 515. The output signal of the latch 515 is the signal HPOS which is applied to the zoom circuitry by the output controller 25 as shown in FIGURE 1. The signal HPOS is also applied to the adder 512, as set forth above. The circuit in FIGURE 5B is substantially the same as the circuit shown in FIGURE 5A. The two circuits differ only in the maximum values used by respective limiters 513 and 517. The limiter 517 will allow VPOS values as large as the total number of scan lines and interstitial scan lines (i.e. 4096). FIGURE 6 shows the details of circuitry which will limit the user requested HPOS and VPOS values, provided by the circuitry shown in FIGURES 5A and 5B, to prevent the display of video information outside of the active video region. This circuitry receives, as inputs, the signals ZR, HPOS and VPOS provided by the circuitry shown in FIGURES 3, 4, 5A and 5B. The output signals provided by the circuitry shown in FIGURE 6 are corrected signals HPOS′ and VPOS′. These signals are applied to the zoom system shown in FIGURE 1 as the starting horizontal and vertical position signals. This circuitry uses substantially the same algorithm as is used by the circuitry shown in FIGURE 2: it limits HPOS to be greater than zero and less than 48 * (256 - ZR). It also limits VPOS to be greater than zero and less than 16 * (256 - ZR). In FIGURE 6, a zero is concatenated onto the signal ZR in the MSB position to add a ninth bit. This new MSB is inverted in inverter 611, and then concatenated to the eight least significant bits (LSB's) of the signal ZR, which have not been inverted. This operation is equivalent to a twos complement subtraction of 256 from ZR. The difference value produced by this operation is applied to a conventional shift and add multiplier 612 which multiplies the difference value by three. The multiplier 612 includes a synchronizing latch (not shown). The output signal of the multiplier 612 is a ten-bit signal. Four zero bits are concatenated to this value in the LSB positions to provide a 14 bit value, P5, which represents the signal provided by the multiplier 612 multiplied by 16. The signal P5 is extended to 15 bits by sign extending circuitry 613 which adds a fifteenth most significant bit with the same value as the fourteenth (previously the most significant) bit. This 15-bit signal, P6, is applied to an input port of an adder 614. Another input port of the adder 614 is coupled to receive a signal S5 which is the signal HPOS extended to 15 bits and delayed by a synchronizing latch 619 to be properly timed with respect to the signal P6. The signals S5 and P6 are summed by adder 614, yielding a signal, S6. The signal S6 has a value of [HPOS + 48 * (ZR - 256)] which is equivalent to -[48 * (256 - ZR) - HPOS]. The product in the square brackets is essentially the same limiting signal that is applied to the comparator 218 in FIGURE 2. The 15 bits of the signal S6 are applied to respective first input terminals of a 15 two-input NAND gates 615. An inverted version of the MSB of the signal S6 is applied to the second input terminal of each of the gates 615. If the MSB is logic-zero (a positive S6), each of the 15 bits will be inverted so that the signal S7 provided by the NAND gates 615 is the ones complement representation of the signal S6. If, however, the MSB of the signal S6 is logic-one (a negative S6), the NAND gates 615 are all disabled and provide an output value having 15 ones (the ones complement of zero). The signal S7 is applied, through a synchronizing latch 619, to one input port of an adder 616. The other input port of the adder 616 is coupled to receive the signal S5 via a synchronizing latch 620. The adder 616 has a carry-in input terminal, CI, which is coupled to receive a logic-one value. In this configuration, the adder 616 effectively converts the ones complement values provided by the latch 619 into twos complement negative values which are added to the twos complement positive values provided by the latch 620. This operation subtracts the signal S6 from the signal S5. If S6 is negative or zero then the signal HPOS is within its valid range and a value of zero is subtracted from HPOS by the adder 616. If S6 is positive, its value is the amount by which the signal HPOS exceeds its upper limit. This value is subtracted by the adder 616 to produce a signal HPOS that is within its upper limit. However, the signal HPOS may still be less than the lower limit of zero. HPOS is limited to be within its lower limit (i.e. to be greater than or equal to zero) by a bank of 14 AND gates, 617. First input terminals of the gates 617 are coupled to receive the 14 LSB's, respectively, of the signal provided by the adder 616. Second input terminals of each of the AND gates 617 are coupled to receive an inverted version of the MSB (i.e. the sign bit) of the signal provided by the adder 616. When the signal provided by the adder 616 is negative, the AND gates 617 are disabled and provide a zero value. Otherwise, the gates 617 pass the value applied to their first input terminals. The output signal provided by the AND gates 617 is passed through a synchronizing latch 618 to produce a signal HPOS′. This signal is the horizontal position signal that is provided to the zoom circuitry shown in FIGURE 1. A similar correction is applied to the signal VPOS. The signal S4 (i.e.the signal (ZR - 256) is multiplied by 16 by the concatenation of four logic-zero valued LSBs from a digital value source 630a. This product, the signal P7, is applied to a synchronizing latch 630. The user requested vertical center value, VPOS, is applied to a synchronizing latch 641. The 12-bit output signal of the latch 641 is extended to 13 bits by concatenating a logic-zero in the thirteenth most significant bit position. This 13 bit version of the signal VPOS is designated S10. The signal S10 is added to the signal provided by the latch 630 by an adder 632. The output signal, S11, of the adder 632 has a value represented by the expression [VPOS + 16 * (ZR - 256)]. If S11 is positive, its value represents an error in the upper bound of the signal VPOS. If S11 is negative or zero there is no error. Accordingly, the signal S11 is limited to be zero or positive by a bank of 13 NAND gates 633 and subtracted from the signal VPOS by an adder 635. The adder 635 is configured in the same way as the adder 616 described above. The output signal S13 provided by the adder 635 is a VPOS signal that is limited to be within its upper bound. The signal VPOS is limited to be within its lower bound (i.e. greater than zero) by a bank of 12 AND gates 636. The output signal provided by the AND gates 636 is applied to a synchronizing latch 637 which provides the fully limited signal VPOS′. This signal is the vertical position signal that is applied to the zoom system shown in FIGURE 1. The signals HPOS′ and VPOS′, provided by the circuitry shown in FIGURE 6, are limited to produce a magnified image that is always entirely within the active video region. FIGURES 7 through 10 illustrate a third embodiment of the present invention. In this system, the horizontal and vertical center positions are adjusted by a microprocessor 712 as incremental changes are requested using the viewer controls 23. The horizontal and vertical center positions are stored and manipulated as eight-bit values. These values are converted into respective 14 and 12 bit starting pixel values, HPOS and VPOS, respectively, which are applied to the zoom system shown in FIGURE 1. Using this method, the value of HPOS is adjusted in increments of three pixels of the source image and the value of VPOS is adjusted in increments of one scan line of the source image. The microprocessor 712 also adjusts the magnification factor by incrementing or decrementing the zoom ratio signal, ZR. The magnification factor is limited to a range between one-to-one and five-to-one. When the signal ZR is adjusted, the horizontal and vertical center positions are reevaluated to determine if further adjustment of these signals is desirable to prevent the display of the blanking intervals. An assembly language listing of the program which controls the microprocessor 712 is included as an appendix to this specification. The program is written in assembly language for a HD63B01Y0 microprocessor manufactured by Hitachi, Inc. In FIGURE 7, the viewer control buttons, 51, 52, 55, 56, 58 and 59 are coupled to interface circuitry 710. This circuitry translates the action of the viewer pressing one or more of the buttons into a sequence of commands for a microprocessor 712. In the present embodiment of the invention, the operator control 23 is a remote control transmitter and The interface 710 is circuitry internal to the remote control transmitter, which generates a sequence of infra-red signals, and circuitry internal to the television receiver, which translates these signals into commands for the microprocessor 712. The microprocessor 712 interprets these incremental commands to produce signals ZR, HPOS and VPOS for application to the zoom system shown in FIGURE 1. The signals ZR, HPOS and VPOS are stored, by the microprocessor 712, in respective latches 714, 716 and 718 as they are calculated. FIGURE 8 is a flow-chart diagram of an exemplary main program which is executed by the microprocessor 712 to generate the signals ZR, HPOS and VPOS. In FIGURE 8, commands are received from the interface 710 at step 810. Step 812 determines if the command is an adjustment of the signal ZR. If so, it invokes a zoom routine at step 818. If the command is not a zoom adjustment, step 812 transfers control to step 814 which invokes a horizontal position routine, at step 820, if the command is for a horizontal center position adjustment. If so, the command is neither a zoom change nor a horizontal position change step, control passes to step 816 which determines if the command is a vertical center adjustment. If so, the command 816 invokes a vertical position routine at step 822. If the command was not a vertical center adjustment command, control is transferred to the step 810 to await the next command. After the routines invoked at the steps 818, 820 and 822 have returned control to the main program, the step 810 is executed to await the next command. FIGURE 9 is a flow-chart diagram of an exemplary horizontal position routine. This routine begins at step 900 which receives the command from the main program. Step 910 tests the type of the received command to determine if it is an increment command or a decrement command. If it is an increment command, step 912 is executed which adds a value of one to an eight-bit horizontal center position variable HC. If the command is a decrement command, step 914 is executed which subtracts a value of one from the variable HC. The steps 912 and 914 both transfer control to a step 916. The step 916 determines if the value held by the variable HC is less than the quantity ZR/2. If it is, then the left side of the magnified image may include portions of the horizontal blanking interval. To prevent this, step 918 is executed which assigns the value ZR/2 to the variable HC. The next step executed, 920, determines if the value held in the variable HC is greater than 256- ZR/2. If so, the right side of the image may include portions of the horizontal blanking interval. To prevent this, the step 922 is executed which assigns the value 256 - ZR/2 to the variable HC. The next step, 924, multiplies the value held in HC by 64 and stores the result in a variable HC1. This operation converts the eight-bit HC value into an equivalent 14-bit value. Step 924 also generates a horizontal starting position value from the value HC1 and stores the generated value in a variable HPOS. The algorithm for this conversion is given in the equation (4) set forth above. At step 926, the value HPOS is applied by the microprocessor 712 to the latch 716. The final step, 928, of the routine returns control to the program which invoked the horizontal position routine. The vertical position routine is the same as the horizontal position routine shown in FIGURE 9 except that the variables VC, VC1 and VPOS replace the variables HC, HC1 and HPOS, the step 924 multiplies VC by 16 instead of 64, and equation (5) is used instead of equation (4) to convert the value held in VC1 to a value to be stored in VPOS. FIGURE 10 is a flow-chart diagram of a zoom routine suitable for use in this embodiment of the invention. The zoom routine starts at step 1000 which accepts the command from the interface 710. Step 1010 determines if the command requests that the signal ZR be incremented (to reduce the magnification factor) or be decremented (to increase the magnification factor). If ZR is to be incremented, step 1012 is executed, otherwise step 1014 is executed. The next step in the routine, 1016 determines if the value held in the variable ZR is less than 51. This value corresponds to a magnification factor of five-to-one, an arbitrarily established maximum for this embodiment of the invention. If ZR is less than 51, a step 1018 sets ZR to 51. Step 1020 determines if the incremented value held in the variable ZR is greater than 256. This value corresponds to the minimum magnification factor, one-to-one. Step 1022 limits the value held in ZR to 256. After the value held in ZR has been updated, the horizontal position routine is invoked at step 1024 and the vertical position routine is invoked at step 1026 to recalculate the current values of HC and VC using the new value of ZR. These recalculated values for HC and VC ensure that image blanking intervals are not displayed as part of the magnified image. Step 1028 writes the calculated values of ZR, HPOS and VPOS into the registers 714, 716 and 718 and step 1030 returns control to the main program.

Claims: A video signal processing apparatus having means for producing a magnified image representing a portion of an active video part of a source image, and including means for selecting the portion of the source image to be magnified comprising: first viewer control means (51-56) for establishing a center point of the selected portion in at least a first coordinate direction; second viewer control means (58,59) for adjusting a magnification factor for scaling the selected portion to produce said magnified images, characterized by; means responsive to adjusted magnification factors for generating limit values; and means (218,223,241-248) responsive to said limit values for adjusting the position of said center point in response to an adjustment of said magnification factor to prevent display of portions of said source image outside of said active video part. The video signal processing apparatus set forth in Claim 1, characterized by, memory means for storing the image from which the magnified portion is selected, memory address means responsive to starting addresses for providing memory addresses for reading the portion of the stored image to be magnified from said memory means, and means for generating horizontal starting addresses comprising; first means responsive to a user control, for generating a first value representing a magnification factor; second means responsive to a user control, for generating a second value representing a center coordinate of the selected portion; means responsive to said first and second values, for generating a third value corresponding to an adjusted center coordinate; means responsive to said third value, for generating a fourth value corresponding to said horizontal starting address; means responsive to said first value for generating a horizontal limit value representing maximum horizontal address that may be utilized for the generated magnification factor; and means responsive to the horizontal limit value and said fourth value, for decreasing said fourth value when said fourth value exceeds said horizontal limit value. The apparatus set forth in Claim 2, characterized in that said second means includes means responsive to the user control for incrementing or decrementing a count value and responsive to a further signal for decrementing said count value, and wherein said means for decreasing said fourth value includes a comparing means, responsive to said fourth value and said horizontal limit value for generating said further signal when said fourth value exceeds said horizontal limit value. The apparatus set forth in Claim 2, characterized in that the means for decreasing the fourth value includes means for adjusting the second and third values. The apparatus set forth in Claim 2, characterized in that the means for decreasing the fourth value includes: means for generating the difference between the first value and a predetermined constant; means for generating a product equal to said difference multiplied by a second predetermined constant; means for combining said product with said fourth value to form a combined value; means for subtracting said combined value from said fourth value to produce a further difference; and means for providing as said horizontal starting address a zero value if said further difference has a first predetermined polarity and providing said further difference if said further difference has a polarity opposite said first predetermined polarity.

Inventors: CANFIELD BARTH ALAN, DUFFIELD DAVID JAY, MCNEELY DAVID LOWELL, CANFIELD, BARTH ALAN, DUFFIELD, DAVID JAY, MCNEELY, DAVID LOWELL
Applicants: RCA THOMSON LICENSING CORP, RCA THOMSON LICENSING CORPORATION
Application year: 1990
Main classification: H04N5
IPC codes: G09G5, H04N5, H04N1