TEST PATTERN GENERATOR

Abstract: A test pattern generator that generates test patterns used for testing semiconductor ICs. So far, test patterns are stored in an SRAM and are sucessively read out therefrom. Generally, an SRAM has a memory device integration density which is smaller than that of a DRAM. When a DRAM having a large memory element density is used instead of an SRAM, it is necessary to refresh the stored content of the DRAM at a constant period. Consequently, it is impossible to read test patterns during the refreshing, and test patterns are not continuously generated. According to this invention, a DRAM is used as a test pattern memory (32). A control circuit (21) generates address generation clock pulses (ACK), a read control signal (RC), a refresh control signal (REF) and write clock pulses (WCK). In response to the address generation clock pulses (ACK), an address generating circuit (31) generates addresses for reading the DRAM (32). In response to one of the address and read control signal (RC), a test pattern is read out from the DRAM (32) and is written onto a FiFo memory (22) in synchronism with the write clock pulses (WCK). The test patterns are continuously read out from the FiFo memory (22) in synchronism with the pattern generation clock pulses (PCK). The average reading speed at which the test patterns are read out from the DRAM (32) inclusive of the refresh time is determined to be greater than the reading speed from the FiFo memory (22). When filled with test patterns, the FiFo memory outputs a full flag (FF). In response to the full flag (FF), the control circuit (21) no more generates the address generation clock pulses (ACK), read control signal (RC) and write clock pulses (WCK). These signals are generated again when the full flag is cancelled. Thus, the test patterns are continuously read out from the FiFo memory (22) even when the DRAM (32) is refreshed at a constant period.

Description: TECHNICAL FIELD The present invention relates to a test pattern generator which generates test patterns for testing semiconductor integrated circuits. BACKGROUND ART A test pattern generator forms a part of an IC tester for testing semiconductor ICs and generates a test pattern to be applied to the IC under test and an expected value pattern for comparison with a response from the IC under test. These two patterns are commonly referred to simply as a test pattern. A conventional test pattern generator is shown in Fig. 1. A clock PCK for pattern generating use and a start signal S are applied to an address generating circuit 11 and an address provided therefrom is used to read out a test pattern memory 12 in which a test pattern has been stored. The test pattern memory 12 is usually constituted by an SRAM (i.e. a static RAM). A large-capacity test pattern memory is needed to cope with extended test patterns which result from an increased degree of integration of circuits to be tested and an automatic generation of test patterns by a computer. Conventionally, such a large-capacity test pattern memory employs the SRAM, and hence is expensive. The number of transistors necessary for forming one memory cell is four to six in the case of the SRAM but only one in the case of a DRAM (i.e. a dynamic RAM). In the case of fabricating IC memories of the same chip area through a patterning process under the same rule, the IC memory using the DRAM is larger in capacity and lower in the unit cost per bit than the IC memory using the SRAM. Hence, the use of the DRAM will cut the manufacturing cost of the test pattern memory. However, stored contents of the DRAM will disappear unless refreshed at regular time intervals, and during the refresh the readout of a test pattern is suspended, making high-speed pattern generation impossible. On this account, the prior art does not employ the DRAM for the test pattern memory. The document GB-A-2 108 278 discloses a test pattern generator designed to provide a continuous sequence of test patterns to a device under test. The test pattern generator employs a plurality of DRAMs as high capacity and low speed storage elements and a buffer memory arrangement interposed between the DRAMs and a test pattern output. The buffer memory arrangement includes two SRAMs. While test patterns are written from the DRAMs into one of the SRAMs, test patterns previously written into the other SRAM are read out for application to the device under test. The two SRAMs are used to avoid a pause that would otherwise occur if only one SRAM were used which had to be repeatedly written and read. To cope with the problem of the low speed of the DRAMs, when the test patterns are written into one of the SRAMs these test patterns are cyclically read from the plurality of DRAMs at a rate higher than that at which data could be read from a single DRAM. The document US-A-4 727 312 discloses a test pattern generator employing FIFO memories between an advance-time machine and a real-time machine. The time between successive test patterns from the advance-time machine is sometimes greater and sometimes less than the time between changes of the test patterns which the real-time machine applies to a device under test. On the average the rate at which the advance-time machine produces test pattern signals is usually the same as that at which the real-time machine uses them, because it pauses when the FIFO memories get full. In this prior art the advance-time machine includes a plurality of state-code generators, each connected via a respective FIFO memory to a respective formatter in the real-time machine. Each state-code generator includes a memory and a data engine receiving data from the memory and generating codes for storage in the FIFO memory. The present invention is to provide a test pattern generator which can be fabricated at low cost through use of the DRAM and is capable of generating test patterns at high speed. DISCLOSURE OF THE INVENTION According to the present invention, a control circuit, which operates on a system clock, is controlled by a start signal and a full flag to generate an address generating clock, a readout control signal and a write clock and, at the same time, a refresh control signal is periodically provided from the control circuit. An address generating circuit is controlled by the address generating clock from the control circuit to generate an address. A test pattern memory formed by the DRAM and having stored therein test patterns is read out, based on the address from the address generating circuit and the readout control signal from the control circuit, and at the same time, the test pattern memory performs a refreshing operation based on the refresh control signal provided from the control circuit. The test pattern read out from the test pattern memory is written into a FiFo memory by the write clock from the control circuit. When filled with test patterns, the FiFo memory provides a full flag to the control circuit and the test patterns are read out from the FiFo memory in synchronism with the pattern generating clock. The address generating clock is made higher in rate than the pattern generating clock. When the FiFo memory becomes full, the readout of the test pattern is started, and when the full flag falls, the address generating clock, the readout control signal and the write clock are produced and then the test pattern memory is read out. The test pattern thus read out is written into the FiFo memory and the refresh control signal is produced. Even while the test pattern memory performs the refreshing operation based on the refresh control signal, the readout of the test pattern from the FiFo memory is continued. Upon completion of the refreshing operation, the readout of the test pattern memory is resumed and the test pattern read out therefrom is written into the FiFo memory. Consequently, test patterns can be read out of the FiFo memory continuously and hence at high speed without being affected by the refreshing operation of the test pattern memory. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a conventional test pattern generator; Fig. 2 is a block diagram illustrating an embodiment of the present invention; Fig. 3 is a circuit diagram showing a specific operative example of a control circuit 21; Fig. 4 is a timing chart showing an example of operation of the present invention; Fig. 5 is a block diagram illustrating a modified form of the present invention; Fig. 6 is a block diagram illustrating another modified form of the present invention; and Fig. 7 is a circuit diagram showing a specific operative example of a control circuit 21-2 used in the embodiment of Fig. 6. BEST MODE FOR CARRYING OUT THE INVENTION Fig. 2 illustrates an embodiment of the test pattern generator according to the present invention. The test pattern generator of the present invention comprises a control circuit 21, a FiFo memory 22, an address generating circuit 31 and a DRAM 32 serving as a test pattern memory. The test pattern generator responds to a system clock SCK, a pattern generating clock PCK and a start signal S supplied from a control section of an IC tester (not shown) to perform a test pattern generating operation. The control circuit 21 is synchronized with the system clock to generate a refresh control signal REF, an address generating clock ACK, a readout control signal RC and a write clock WCK with predetermined periods, respectively, but during its generation of the refresh control signal REF and during the input thereinto of a full flag FF from the FiFo memory 22, the control circuit does not generate the address generating clock, the readout control signal and the write clock. The control circuit 21 is made up of a timing generating circuit 23, a full flag rise detector circuit 24R, a full flag fall detector circuit 24F, a flip-flop 25 and AND gates 26 to 29, as depicted in Fig. 3. The timing generator 23 generates the address generating clock ACK, the readout control signal RC, the write clock WCK and the refresh control signal REF with predetermined periods, respectively, and in synchronism with the system clock SCK and applies the first three signals to the AND gates 27 to 29 at one input thereof and provides the refresh control signal REF, as an inhibit signal, to the AND gate 26 and, at the same time, applies it to the test pattern memory 32. The flip-flop 25 is set by the start signal S and its Q output goes high and is provided, as an enable signal EN, via the AND gate 26 to the other inputs of the AND gates 27 to 29 to enable these gates, through which the address generating clock ACK, the readout control signal RC and the write clock WCK are output. When the full flag FF is applied from the FiFo memory 22, its leading edge is detected by the full flag rise detector 24R and its detected output is used to reset the flip-flop 25; so that the enable signal EN goes low and the gates 27 to 29 are disabled, stopping the outputting of the address generating clock ACK, the readout control signal RC and the write clock WCK. When the full flag FF falls, its trailing edge is detected by the fall detector 24F and, by its detected output, the flip-flop 25 is set; so that the enable signal EN goes high again and the afore-mentioned three signals are output again. When the refresh control signal REF is yielded during the high-level period of the Q output of the flip-flop 25, the gate 26 is disabled; so that during the high-level period of the signal REF the enable signal EN is held low, disabling the gates 27 through 29. Referring back to Fig. 2, the address generating clock ACK from the control circuit 21 is applied to the address generator 31, which, in turn, generates addresses A 0 , A 1 , A 2 , ... one by one upon each application of the address generating clock ACK. The addresses thus obtained and the readout control signal RC from the control circuit 21 are used to read out test patterns P 0 , P 1 , P 2 , ... from the test pattern memory 32. The test pattern memory 32 is formed by a DRAM, which has stored therein test patterns and performs the refresh operation when supplied with the refresh control signal REF from the control circuit 21. The test patterns P 0 , P 1 , P 2 , ... read out of the test pattern memory 32 are written into the FiFo memory 22 by the write clock WCK provided from the control circuit. When fully filled with the test patterns, the FiFo memory 22 provides the full flag FF to the control circuit 21. Ordinary FiFo memories have a full flag generating function. The FiFo memory 22 is read out in synchronism with the pattern generating clock PCK. The readout of the FiFo memory 22 starts with old data. The rate of the address generating clock ACK is made higher than the rate of the pattern generating clock PCK. More specifically, letting the period of the pattern generating clock PCK, the readout period of the test pattern memory 32 (i.e. the period of the address generating clock ACK) and the time for refreshing the test pattern memory 32 be represented by T 1 , T 2 and T r , respectively, and assuming that the test pattern memory 32 is refreshed every m-th readout therefrom, the period T 2 is chosen so that the following relationship holds: m x T 1 > m x T 2 + T r When the start signal S is applied to the control circuit 21 as shown in Fig. 4, the flip-flop 25 is set to make the enable signal EN high, by which the gates 27 to 29 are enabled, starting the output of the address generating clock ACK. By this, the addresses A 0 , A 1 , A 2 , ... are produced one after another by the address generator 31, and at the same time, the control circuit 21 starts to generate the readout control signal RC, and the test patterns P 0 , P 1 , P 2 , are sequentially read out of the test pattern memory 32 and then written into the FiFo memory 22 by the write clock WCK. When the FiFo memory 22 becomes full, the full flag FF rises, by which the flip-flop 25 is reset and the enable signal EN goes low. Consequently, the gates 27, 28 and 29 inhibit the passage therethrough of the address generating clock ACK, the readout control signal RC and the write clock WCK, respectively, and the readout of the test pattern memory 32 is stopped. At the same time, the write into the FiFo memory 22 is also stopped. Hence, the readout of the test pattern memory 32 by an address A h being generated by the address generator 31 at that time is not performed and the address A h is retained. On the other hand, the pattern generating clock PCK is input in this state and the FiFo memory 22 is read out in synchronism with the clock PCK, providing the test patterns P 0 , P 1 , P 2 , ... Upon initiation of the readout of the FiFo memory 22, the full flag FF falls, by which the flip-flop 25 is set. As a result of this, the enable signal EN goes high again and the readout of the test pattern memory 32 by the retained address A h is resumed and the write into the FiFo memory 22 is also resumed. When supplied with the refresh control signal REF from the control circuit 21, the test pattern memory 32 performs the refresh operation. Since the gate 26 is kept disabled during the refresh of the test pattern memory 32, the enable signal EN goes low and the gates 27, 28 and 29 inhibit the passage therethrough of the address generating clock ACK, the readout control signal RC and the write clock WCK, respectively. The address generator 31 retains an address A j that it is generating at that time, and the write into the FiFo memory 22 is also stopped, but the readout of the FiFo memory 22 by the pattern generating clock PCK is continued; so that output test patterns are continuously obtained. Upon completion of the refresh operation of the test pattern memory 32, the gate 26 is enabled and the readout of the test pattern memory 32 is resumed by the address A j and the write into the FiFo memory 22 is also resumed. Since the average readout rate of the test pattern memory 32, including the refresh period, is higher than the readout rate of the FiFo memory 22, the memory 22 becomes full until the refresh control signal REF is generated next. Thus, the test patterns can be continuously read out from the FiFo memory 22. In the case where the readout rate (1/T 2 ) of the test pattern memory 32 cannot be made higher than a desired readout rate (1/T 1 ) of the FiFo memory 22 so that the condition of Eq. (1) is fulfilled, it is possible to employ such an arrangement as shown in Fig. 5, in which N (where N is an integer equal to or greater than 2) test pattern memories 32-1 to 32-N are provided for one FiFo memory 22 and are simultaneously operated by the addresses A 0 , A 1 , ..., the readout control signal RC and the refresh control signal REF common to them and test patterns thus read out of the N test pattern memories are taken out by a multiplexer 33 sequentially and cyclically and written into the FiFo memory 22. In this instance, the control circuit 21 needs only to have an arrangement in which the system clock SCK of the period T 2 is repeatedly counted from 0 to N-1 by an N-ary counter in the timing generator 23 in Fig. 3 and the count values are sequentially output as a select signal SEL and a signal of a period N x T 2 and a desired phase, obtained by detecting a desired count value of the N-ary counter through use of a decoder, is output as the address generating clock ACK, the readout control signal RC and the write clock WCK. The period T 2 of the system clock SCK is so selected as to satisfy Eq. (1). It is also possible to obtain test patterns at high speed by using such an arrangement as shown in Fig. 6, in which N test pattern memories 32-1 to 32-N and N FiFo memories 22-1 to 22-N are provided in combination and are concurrently operated by the addresses, the readout control signal RC, the refresh control signal REF and the write clock WCK common to them and test patterns thus read out of the N FiFo memories by readout clocks RCK-1 to RCK-N are taken out by the multiplexer 33 sequentially and cyclically. In this instance, a control circuit 21-1 may be the same as that shown in Fig. 3. A control circuit 21-2 is composed of an N-ary counter 21A, a decoder 21B and N flip-flops 21C-1 to 21C-N, as depicted in Fig. 7. The N-ary counter 21A and the flip-flops 21C-1 to 21C-N are reset by the start signal S. The N-ary counter 21A repeatedly counts the pattern generating clock PCK from 0 to N-1. The decoder has N output terminals and provides high-level outputs to its output terminals 1 to N one after another as the count value of the counter 21A varies from 0 to N-1 in a sequential order. The outputs of the decoder 21B are respectively taken into the flip-flops 21C-1 to 21C-N in synchronism with the pattern generating clock PCK and their Q outputs sequentially go high for one cycle period of the clock PCK. Such Q outputs of the flip-flops are used as readout clocks RCK-1 to RCK-N of the FiFo memories 22-1 to 22-N. On the other hand, the count value of the counter 21A is provided as the select signal SEL to the multiplexer 33. INDUSTRIAL APPLICABILITY As described above, according to the present invention, test patterns can continuously be obtained from the FiFo memory even during the refresh of the DRAM, since the test pattern generator has an arrangement in which test patterns read out of the test pattern memory formed by the DRAM are written into the FiFo memory which is read out by the pattern generating clock. Since the test pattern memory is formed by the DRAM, even an extended pattern can be produced by a low-cost device.

Claims: A test pattern generator in an integrated circuit tester for testing semiconductor integrated circuits comprising: control means (21) which starts to operate in response to a start signal (S) supplied thereto and generates an address generating clock (ACK), a readout control signal (RC), and a refresh control signal (REF) with respective predetermined periods in response to a system clock (SCK) supplied thereto; an address generating circuit (31) for sequentially generating addresses (A 0 , A 1 , A 2 , ...) in response to the address generating clock (ACK) supplied thereto from said control means; test pattern memory means (32) having at least one DRAM in which test patterns (P 0 , P 1 , P 2 , ...) have been stored, said test patterns being read out sequentially from said test pattern memory means in response to both the readout control signal (RC) supplied to said test pattern memory means from said control means and each address (A 0 , A 1 , A 2 , ...) supplied to said test pattern memory means from said address generating circuit, said test pattern memory means performing a refresh operation in response to the refresh control signal (REF) supplied thereto from said control means, said test pattern generator being characterized in that: said control means (21) further generates a write clock (WCK) with a predetermined period in response to the system clock (SCK) supplied thereto; FiFo memory means (22) is provided into which the test patterns read out from said test pattern memory means are sequentially written in response to the write clock (WCK) supplied thereto from said control means, said FiFo memory means outputting a full flag (FF) to said control means when it has been fully filled with the test patterns, the test patterns stored in said FiFo memory means being read out in synchronism with a pattern generating clock (PCK) with a period T 1 supplied thereto; said control means is arranged to stop the generation of the address generating clock, the readout control signal and the write clock during generation of the refresh control signal and during the time interval that the full flag is being supplied from said FiFo memory means, and comprises: timing generating means (23) which responds to the system clock supplied thereto to generate the address generating clock, the readout control signal and the write clock with the same period T 2 respectively and the refresh control signal with a period mxT 2 +T r , in synchronism with the system clock where m is the number of the test patterns read out from said test pattern memory means between two adjoining refresh operations thereof and T r is the time interval required for the refresh operation; gate means (27, 28, 29) which controls the passage therethrough of the address generating clock, the readout control signal and the write clock; enable signal generating means (25) which responds to the start signal supplied thereto to generate an enable signal (EN) for enabling said gate means; full flag rise detecting means (24R) which responds to the full flag supplied thereto from said FiFo memory means to detect the leading edge thereof thereby causing said enable signal generating means to stop the generation of the enable signal; full flag fall detecting means (24F) which responds to the full flag supplied thereto from said FiFo memory means to detect the trailing edge thereof thereby causing said enable signal generating means to generate the enable signal; and enable inhibit means (26) which responds to the refresh control signal supplied thereto from said timing generating means to inhibit the enable signal from being supplied to said gate means, and the periods T 1 and T 2 are selected so that the following expression is satisfied: m x T 1 > m x T 2 + T r . The test pattern generator according to claim 1, wherein the test pattern memory means includes: N DRAMs which are supplied with the address, the readout control signal and the refresh control signal in common to them, N being an integer equal to our greater than 2; and multiplexer means which sequentially outputs test patterns read out of the N DRAMs for supply to the FiFo memory means. The test pattern generator according to claim 1, wherein the test pattern memory means includes N DRAMs which are supplied with the address, the readout control signal and the refresh control signal in common to them, N being an integer equal to or greater than 2; and the FiFo memory means includes: N FiFo memories into which test patterns read out of the N DRAMs are written by the write clock applied to the memories in common to them, and multiplexer means which sequentially outputs the test patterns read out of the FiFo memories. The test pattern generator according to claim 3, wherein the control means includes clock generating means which generates N readout clocks for sequentially and cyclically reading out the N FiFo memories in synchronism with the pattern generating clock, and select signal generating means which generates a select signal for sequentially and cyclically switching the multiplexer means in synchronism with the pattern generating clock.

Inventors: SAITO ATSUSHI, SAITO, ATSUSHI
Applicants: ADVANTEST CORP, ADVANTEST CORPORATION
Application year: 1990
Main classification: G06F11
IPC codes: G11C29, G01R31