Non-volatile split gate EPROM memory cell and self-aligned field insulation process for obtaining the above cell

Abstract: The cell comprises a substrate (20) with diffusions of source (11) and drain (12) separated by a channel area (7, 8), a floating gate (4) superimposed over a first part of said channel area (8) and a control gate (10) formed by a first and a second polysilicon strip (4, 10), respectively, a cell gate oxide (3) between said floating gate (4) and said first part of the channel area (8), a transistor gate oxide (9') between said control gate (10) and a second part of the channel area (7), an interpoly oxide (9) between said floating gate (4) and said control gate (10) and a layer of dielectric filler (14). By means of a process which provides for self-aligned etchings of layers of polysilicon (4, 10, 15) and of oxides (3, 9, 9') there is obtained a floating gate (4) and a control gate (10) self-aligned with one another and with the diffusions of source (11) and drain (12), as well as with the first oxide (1).

Description: The present invention relates to a non-volatile split gate EPROM memory cell device and self-aligned field insulation process for obtaining the above cell device. The use is known of non-volatile split gate EPROM memory cells. In such cells the floating gate does not extend along the entire channel of the cell, but only covers a part of it to form the actual memory cell. The second part of the channel is governed directly by the control gate which thus goes to form a small transistor in series with the cell itself. A first advantage deriving from the use of the split gate memory cell consists in the fact that with such a structure the problem is highlighted of the partial raising of the floating gate voltage (with consequent current in the channel) due to the capacitive coupling between floating gate and drain (a problem known as «drain turn-on»), when the drain is biased at a high voltage and the control gate is grounded. In fact in a split gate cell, even in the case when the capacitive coupling between the floating gate and the drain is large, the opening of the channel is completely prevented by the presence of the transistor in series with the cell itself. A second advantage deriving from the use of the above memory cell consists in the fact that, thanks to its asymmetry, it can be programmed starting from only one of the two diffusions (the one known as the drain, that is, that facing the floating gate). If the cell is read from the source side (that is, by raising above ground the diffusion from which writing is impossible), it is then possible to abolish completely the so-called «soft-writing» problem, that is, of the slow and undesired programming of the cell during its reading step. As a result of this advantage the voltage at which the bit-line diffusion is polarised during the reading step of the cell itself can be raised with respect to the typical value used (about 1 volt), thus obtaining both an increase in the cell's reading current and a drop in the capacity of the bit-line itself. Several types of split gate EPROM memory cells are known in the literature. A first example of a cell of this type is described in the US patent 4,328,565 and consists of a non self-aligned structure, in which the source and drain diffusions are implanted before the definition of the superimposed floating and control gates. It follows that, for the drain diffusion to be coupled to the floating gate (that is, sufficiently superimposed over it) independently of the mis-alignments between the different masks, it is necessary to maintain a large superimposiiton between the floating gate itself and the drain, from which there derives a large and highly variable capacitive coupling between the latter. During the cell's programming step this is reflected in a wide variability of the value of the voltage transferred to the floating gate and thus in a threshold jump, after the writing step, whose value is predictable with difficulty and a function of the process misalignments. A second problem related to this cell is connected with the fact of executing the diffusion implant before growing the subsequent oxide layers of gate and interpoles. The diffusions are subjected in this way to all the heat treatments connected with these oxidation steps and they are thus deper and more diffuse. This is the opposite of the current tendency towards new generations of processes characterised by an increasingly higher density. A last problem related to this type of cell is connected with the fact that the control gate passes over the gate and drain diffusions, it being insulated from them only by a thin layer of thermal oxide. It follows that the word-line capacity is raised with a corresponding reduction in the speed of the device. A second example of cell of this type is described in US patent 4,639,893. In this cell the drain diffusion is self-aligned with the floating gate; the source and drain implant is executed after defining the floating gate itself and, on the drain, it is self-aligned with it. The capacitive coupling of the floating gate with the drain thus becomes independent from the process misalignments. The distance between source and drain, on the other hand, is subject to the misalignment between the mask which defines the floating gate and that used for the source and drain implant. As in the cell of the first example, the control gate passes completely over the source and drain diffusion and it is insulated from it only by a thin oxide thermally grown simultaneously with the gate oxide and with the interpoly one. The greatest problem of this type of structure is precisely in this oxidation step; to lower the word-line's capacity (and thus to raise the access speed of the device) it is in fact necessary for the thin oxide to be as thick as possible, but this is not reconcilable with a good quality of the other two oxides. To obtain an appreciable difference between the thicknesses of these oxides it is in actual fact necessary to execute oxidation at low temperatures, but the oxides so obtained are of poor quality. JP-A-58-209164 and EP-A-0 052 982 disclose the subject matter of the preamble of claim 1. In view of this state of the art, the main object of the present invention is to provide a split gate EPROM memory cell device that does not have the above drawbacks. A further object of the present invention is to provide a process for obtaining the above cell device. According to the invention such object is attained with a non-volatile split gate EPROM memory cell, device as defined in claim 1. Again according to the invention such further object is attained through a process as defined in claim 3. In this way there is obtained an EPROM memory cell device in which the drain diffusion is self-aligned with the floating gate and with the control gate, in turn self-aligned with one another, and the source diffusion is self-aligned with the control gate, and wherein the distance between the source and drain diffusions is determined by the width of the mask defining the control gate and is thus independent of the misalignment between the masks. In addition the source and drain junctions are not very diffused as they are not subjected to any of the oxidation heat treatments for the formation of the gate oxide and of the interpoly oxide. Moreover, in this cell device, the presence of a thick dielectric allows the word-line, constituted by a third series of polysilicon or silicide strips perpendicular to those defining the control and floating gates, to be arranged very high up, thus avoiding the problem of the triple oxidation and of the high coupling capacity between the gates and the source and drain diffusions. Finally the self-alignment of the field insulation with the control gate allows the cells to be packed into a matrix in a periodic structure having a so-called «tablecloth» pattern in which it is not necessary to have a drain contact for each pair of cells. The features of the present invention shall be made more evident by the following detailed description of an embodiment illustrated as a non-limiting example in the enclosed drawings, wherein: Fig. 1 shows a vertical sectional view of a pair of cells according to the invention; Fig.s 2-4 show a top plan view and two sectional views, taken along the lines III-III and IV-IV of Fig. 2, respectively, of the initial step of the process for manufacturing the cells of Fig. 1; Fig.s 5-7, 8-10, 11-13, 14-17, 18-21, 22-25, 26-29, 30-33 show in turn subsequent steps of the above process. With reference to Fig. 1, each cell 30 comprises a semiconductor substrate 20 in which there are obtained diffusions of source 11 and drain 12 essentially of the type n+, between which there is a channel formed by adjacent portions 7, 8, preferably doped in a different way. Over the portions 8 and 7 there are superimposed a layer of cell gate oxide 3 and a transistor oxide layer 9′, respectively. Over oxide 3 there is in turn superimposed a first polysilicon strip (perpendicular to the plane of the drawing) constituting a floating gate 4, over which there is an interpoly oxide 9 similar to the transistor oxide 9′. Over oxides 9 and 9′ there is arranged a second polysilicon strip constituting a control gate 10. As shown, the floating gate 4 is aligned with the drain diffusion 12 and the control gate 10 is aligned with one edge of the floating gate 4 and with the source and drain diffusions 11 and 12. A dielectric 14 is used for sealing the spaces present between one cell and the other and lastly a further polysilicon or silicide strip 15, constituting a connection word-line between cells, extends perpendicularly to the gate strips 4 and 10. With reference to Fig.s 2-28, the process according to the invention for the accomplishment of the pair of cells 30 of Fig. 1 comprises a first step in which on the silicon substrate 20 there are defined parallel insulations strips of field 1 and of active area 2 (Fig.s 2-4). During such step there is also executed the channel implant of the cell (portions 8 and 7 of Fig. 1), necessary for defining the threshold voltage. With reference to Fig.s 5-7, there is then executed a growth of cell gate oxide 3 and the subsequent deposition of a layer of polysilicon 4. The layer of polysilicon 4 is made conductive (doped) using conventional techniques. With reference to Fig.s 8-10, the double layer of cell gate oxide 3 and polysilicon 4 is defined in strips perpendicular to the field oxide strips 1. After etching the polysilicon layer 4 and of the cell gate oxide 3, there may be executed, if necessary, an implant of transistor channel (portion 7 of Fig. 1), whose object is to define the threshold of the transistor in series with the cell; in this way, as shown in Fig. 1, the channel doping in the portion of channel 7 directly controlled by the control gate 10 is differentiated with respect to that in the portion of channel 8 under the floating gate 4. With reference to Fig.s 11-13, the growth is executed of transistor gate oxide 9′ and of interpoly oxide 9, over which there is deposited and made conductive a second layer of polysilicon 10 which shall constitute the control gate. With reference to Fig.s 14-17, there is first accomplished the definition of a second layer of polysilicon 10 in strips that are parallel and partially superimposed over those of the first layer 4 and then the self-aligned etching of the multilayer constituted by the first and second layer of polysilicon 4, 10, by the interpoly oxide 9 and by the gate oxides 9′ and 3 according to strips parallel to one another and perpendicular to the strips related to the field oxide 1 and to the active regions 2. With subsequent etching of the field oxide 1 there are uncovered side-by-side regions of source 11 and drain 12, constituting the bit-lines, aligned with the control gate 10 and with the floating gate 14, respectively. During the etching of the first layer of polysilicon 4 the cell's asymmetry (Fig. 15) determines the creation of small excavations 30 in the silicon substrate 20 in the source areas 11. With reference to Fig.s 18-21, there is executed an n+ implant in the regions of source 11 and of drain 12, after which a lateral sealing takes place with oxide 13 of the multistrate 3, 4, 9, 10. With reference to Fig.s 22-25, the planarisation is executed, that is, the filling with dielectric 14 of the spaces between the cells 30. Typically, planarisation is executed by depositing a layer of deposed oxide and subsequently a layer of «spin-on-glass» (or resit) whose object is to make the surface planar. Planarisation is completed by partially removing the dielectric 14 and the covering oxide 13 over the second layer of polysilicon 10, so that the polysilicon surfaces 10 are not covered with oxide and may thus be contacted. With reference to Fig.s 26-29, there is executed the deposition of a conductive layer 15, typically polysilicon or silicide, which shall constitute the word-lines. With reference to Fig.s 30-33, the self-aligned etching is executed of the multistrate 3, 4, 9, 10, 15 up to the field oxide 1, according to strips which are parallel to, but wider than, the active area strips 2, so as to obtain cells with lateral fins superimposed over the field oxide 1 (Fig. 32). In this way the fins of one cell are separated from those of the contiguous cell. The steps of the standard process which follow, in particular the sealing reoxidation, the deposition of intermediate dielectric, the opening of the contacts and the metallisation, are not described here.

Claims: Non-volatile split-gate EPROM memory cell device, in which each cell (30) comprises a substrate (20) with source and drain diffusions (11, 12) separated by a channel area (7, 8), a floating gate (4) superimposed over a first part (8) of said channel area and a control gate (10) formed by first and second polysilicon layers (4, 10), respectively, a cell gate oxide (3) between said floating gate (4) and said first part (8) of channel area, a transistor gate oxide (9′) between said control gate (10) and a second part (7) of the channel area, and an interpoly oxide (9) between said floating gate (4) and said control gate (10), said floating gate (4) being aligned with said drain diffusion (12) and said control gate (10) being aligned with said floating gate (4) and with said source and drain diffusions (11, 12), a dielectric layer (14) being arranged over said source and drain diffusions (11, 12) and field oxide (1) being interposed between adjacent rows of cells (30), characterised in that the cells (30) are electrically connected within said rows by parallel polysilicon strips (15) which are superimposed over and in contact with the control gate (10) of said cells (30) and are isolated from each other by etchings extending down to the field oxide (1). Device according to claim 1, characterised in that the cells (30) have lateral fins of the floating gate (4) and the control gate (10) superimposed over the field oxide (1). Process for manufacturing a non-volatile split-gate EPROM memory cell device according to anyone of the preceding claims, characterised in that it comprises the following steps: definition of parallel strips of field oxide (1) and of active area (2) and execution of a cell channel implant on a semiconductor substrate (20); growth of cell gate oxide (3), deposition and doping of a first polysilicon layer (4) and definition of both in first strips perpendicular to those of the field oxide (1); growth of transistor gate oxide (9′) and of interpoly oxide (9), deposition and doping of a second polysilicon layer (10); definition of said second polysilicon layer (10) in second strips parallel and partially superimposed over those of the first polysilicon layer (4); self-aligned etching of the second polysilicon layer (10), the transistor gate oxide (9′), the interpoly oxide (9), the first polysilicon layer (4) and the cell gate oxide (3) up to the field oxide (1) and subsequent etching of said field oxide (1) with uncovering of substrate strips (20); execution of implants of source (11) and drain (12) in said uncovered strips of the substrate and subsequent formation of thick dielectric (14) over said implants of source (11) and drain (12); partial removal of the dielectric (14) and of the covering oxide (13) until said second polysilicon strips (10) are uncovered; deposition of a conductive layer (15) suitable for constituting word-lines; and etching of said conductive and polysilicon layers (15, 10, 4) and said interpoly and gate oxide (9′, 9, 3) up to the field oxide (1) to define etchings which are interposed between and parallel to the active area strips (2). Process according to claim 3, characterised in that said etchings are narrower than the field oxide (1) so as to obtain cells with lateral fins on the field oxide. Process according to claim 3, characterised in that after definition of the first polysilicon layer (4) a transistor channel implant is executed to form a transistor channel (7) having a doping profile different from that of the channel area (8).

Inventors: CAMERLENGHI EMILIO, CAMERLENGHI, EMILIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L27