Dynamic random access memory

Abstract: A dynamic random access memory includes a semiconductor substrate (1) having an active region (AR) including first and second diffusion regions (D, S) of a transfer transistor, an insulating layer (2, 3) formed on the semiconductor substrate and having first and second contact holes (SH, BH), and a stacked capacitor (SC) having a storage electrode (SE) which is electrically coupled to the first diffusion region through the first contact hole formed in the insulating layer and an opposed electrode (CP). The DRAM also includes a word line (WL) electrically isolated from the semiconductor substrate, and a bit line (BL) electrically isolated from the semiconductor substrate and electrically coupled to the second diffusion region through the second contact hole formed in the insulating layer. The second contact hole is substantially positioned at a center (CL) of the bit line. The word line has a bent portion (Z, Z') located between the first and second contact holes so that the word line is separated from the second contact hole at a predetermined distance.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to a dynamic random access memory, and more particularly to a dynamic random access memory having an improved layout. Further, the present invention is concerned with a method of arranging a memory cell pattern of the dynamic random access memory. Recently, the layout of structural elements of a dynamic random access memory (hereinafter simply referred to as a DRAM) has been designed by using a computer. In order to reduce the amount of data to be processed, the layout is designed by using straight lines extending in two orthogonal directions and straight lines extending at an angle of 45° with respect to each of the orthogonal directions. However, advanced computers have an ability to process an extremely large amount of data at high speeds and thus make it possible to design the layout by using oblique lines which extend at angles other than 45° with respect to the aforementioned orthogonal directions. Referring to FIG.1, there is illustrated a layout of a DRAM of a stacked capacitor type. In FIG.1, AR indicates an active (diffusion) region including a drain region and a source region, a word line and S indicates a source area. D indicates a drain area. WL indicates a word line and WL' denotes the distance between the adjacent word lines WL. BL indicates a bit line and BL' indicates an extension portion of the bit line BL. BH indicates a bit line contact hole and SE indicates a storage electrode. SH indicates a storage electrode contact hole. GP is the space between the extension portion BL' of the bit line BL and the adjacent bit line BL. FIG.2 is a sectional view taken along line II-II shown in FIG.1. A P-type silicon semiconductor substrate 1 has a source region S and drain region D of a transfer transistor, both of which are active regions (impurity diffused regions) buried in the Si substrate 1. A field insulating layer 2 and a gate insulating layer 3 are formed on the Si substrate 1. CP indicates an opposed electrode (cell plate) of a storage capacitor. The bit line BL is formed at a layer level lower than that of the opposed electrode CP. The word line WL, the bit line BL, the storage electrode SE and the opposed electrode CP are stacked in this order. A stacked capacitor is composed of the storage electrode SE, a dielectric film DE and the cell plate CP. This arrangement would become popular as the size of memory cells is further reduced. In the arrangement shown in FIGS.1 and 2, each bit line contact hole BH used for electrically coupling the bit line BL and the source region S of the transfer transistor must be positioned so that it keeps away from the word line WL. The storage electrode contact hole SH used for electrically coupling the storage electrode SE and the drain region D of the transfer transistor must be positioned so that it keeps away from both the word line WL and the bit line BL. Each bit line BL must be provided with the extension portion BL' which is formed so that it surrounds the contact hole BH. The presence of the extension portion BL' increases the surface area of the bit line BL so that a parasitic capacitance is increased. In addition, the arrangement shown in FIGS.1 and 2 causes short circuiting in the vicinity of the bit line extension portion BL', since the distance GP between the bit line extension portion BL' and the adjacent bit line BL is smaller than the distance between the adjacent bit lines BL. Length DM of each memory cell measured in the direction in which each bit line BL extends is described as follows. DM = a + e + d + e + 2c + e + d + 1/2WL' = A + c + e + d + 1/2WL' where a: half the width of the bit line contact hole BH e: alignment margin of each of the contact holes d: the width of the word line WL c: half the width of the storage electrode contact hole SH WL': the distance between the adjacent word lines W1 It can be seen from FIG.1 that A = a + e + d + e + c = a + c + d + 2e. The bit line contact hole BL and the storage electrode contact hole SH are arranged approximately in a line so that the length DM of each memory cell is great. Patent Abstracts of Japan, vol. 13, no. 594, 27.12.89 & JP-A-1 248 556 and Patent Abstracts of Japan, vol 14, no. 273, 13.6.90 & JP-A-2 86164 each describe a memory device having a bent portion in the word line between a storage capacitor contact and a corresponding bit line contact. Patent Abstracts of Japan, vol. 13, no. 459, 17.10.89 & JP-A-1 179 449 discloses that the active area has an inclination equal to 45° with respect to the bit line in order to most finely arrange the active areas and that the active areas with which the bit lines make contact are needed to extend in parallel with the bit lines. EP-A 0 399 531 and EP-A-0 428 247, cited pursuant to Art. 54(3) EPC, each show a memory device having bent word line portions and obliquely arranged active regions. SUMMARY OF THE INVENTION It is general object of the present invention to provide a DRAM having an improved layout in which the aforementioned disadvantages are eliminated. A more specific object of the present invention is to provide a DRAM having an improved layout which has no bit line extension portion for forming a bit line contact hole and which is directed to preventing the occurence of short circuiting between the adjacent bit lines. The above-mentioned objects of the present invention are achieved by a dynamic random access memory as defined in claim 1. Further embodiments of the invention are set out in the dependent claims. Another object of the present invention is to provide a method of arranging a memory cell pattern of the above-mentioned dynamic random access memory. This object of the present invention is achieved by a method according to attached claims 23 and 25. BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG.1 is a diagram illustrating a conventional layout of a DRAM of a stacked capacitor type; FIG.2 is a cross sectional view taken along line II-II shown in FIG.1; FIG.3 is a diagram illustrating a principle of the present invention; FIG.4 is a diagram illustrating a pattern according to a preferred embodiment of the present invention; FIGS.5A and 5B are diagrams illustrating the influence of a bird's beak; FIG.6 is a diagram of a pattern according to the embodiment of the present invention in which four memory cells are illustrated; FIGS.7A, 7B and 7C are diagrams illustrating how the present invention was made; and FIG.8 is a block diagram of a folded bit line type DRAM. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is based on the following considerations. First, in order to eliminate the aforemetioned extension portion BL' which projects from the bit line BL and which surrounds the bit line contact hole BH, it is the best way to arrange the bit line contact hole BL so that the center thereof is positioned on the center line of the bit line BL. Second, it is advantageous to arrange the storage electrode contact hole SH so that the center thereof is positioned at an equal distance from the adjacent bit lines BL and at an equal distance from the adjacent word lines WL. Third, an imaginary line which connects the bit line contact hole BH and the corresponding storage electrode contact hole SH crosses the bit line BL at an angle with respect to the direction in which the bit line BL extends, that is, the center line thereof. Active regions such as source and drain regions are arranged on the basis of the imaginary line. In addition, the shape of each word line WL is determined, taking into consideration the pattern of the active regions. Referring to FIG.3, there is illustrated a principle of the present invention based on the above-mentioned first to third considerations. In FIG.3, those parts which have the same names of structural elements as those shown in FIG.1 are given the same reference characters. CL indicates a center line of the bit line BL, and C BH indicates the center of the bit line contact hole BH. C SH indicates the center of the storage electrode contact hole SH, and  indicates an angle formed between the center line CL and an imaginary line which connects the center C BH and C SH . A distance A between the center C BH of the bit line contact hole BH and the center C SH of the storage electrode contact hole SH, that is, the length A of the imaginary line therebetween is described as follows. A = a + c + d + 2e The distance between the center line CL of the bit line BL and the center C SH of the storage electrode contact hole BH is written as follows. 1/2b + c + e It can be seen from FIG.3 that two right-angled isosceles triangles TA are formed. Thus, the able e is written as follows.  = sin -1 [(1/2b + e + c) / (a + c + d + 2e)] The memory cell pattern is determined so that formula (1) is satisfied. It is possible to determine the memory cell pattern so that the angle  is nearly equal to the right term of formula (1). Referring to FIG.4, there is illustrated a layout of a DRAM according to a preferred embodiment of the present invention. In FIG.4, those parts which have the same names as those shown in the previous figures are given the same reference characters. In FIG.4, a letter b denotes the width of the bit line BL, and AR' indicates a bent portion of the active region AR. Z is a bent portion of the word line WL. Z1, Z2 and Z3 indicate areas of the word line WL which form the bent portion Z of the word line WL. The center C BH of the bit line contact hole BH is positioned on the center line CL of the bit line BL. Although the bit line BL shown in FIG.4 has an extension portion for forming the bit line contact hole BH, it is very smaller than that shown in FIG.1. Thus, the distance between the extension portion of the bit line BL and the adjacent bit line BL is increased so that the occurrence of short circuiting therebetween can be reduced. The length A of the imaginary line which connects the center C BH of the bit line contact hole BH and the center C SH of the storage electrode contact hole SH is equal to a + c + d +2e, as described previously. The angle  of the line with respect to the center line CL of the bit line BL is selected, as defined by formula (1). The minimum distance between the center C SH of the storage electrode contact hole SH and the center line CL of the bit line BL is equal to 1/2b + c + e. The active area AR extends along the imaginary line which connects the center C BH of the bit line contact hole BH and the center C SH of the storage electrode contact hole SH. That is, the active area AR is arranged obliquely with respect to the bit line BL. The active area AR has a bent portion AR' which is symmetrically bent or curved with respect to a line which passes through the center C SH of the storage electrode contact hole SH and which is perpendicular to the center line CL of the bit line BL. The bent portion AR' of the active area AR reduces the influence of bird's beaks. Referring to FIG.5A, there is illustrated a silicon nitride (Si 3 N 4 ) film used for selectively oxidizing the Si substrate to thereby produce an oxide layer (field insulating layer) for element-to-element isolation. Oxygen is supplied with a short end of the Si 3 N 4 film along various directions, as shown by arrows in FIG.5A. Thus, the bird's beak occurs at the short end of the Si 3 N 4 film and an Si substrate surface portion in the vicinity of the short end is oxidized, as indicated by arrow OX shown in FIG.5B. Although an Si substrate surface portion in the vicinity of a long end of the Si 3 N 4 is also oxidized, as indicated by arrow OY shown in FIG.5B, it is smaller than that indicated by the arrow OX. The bent portion AR' of the active region AR is provided for taking into account the occurrence of the above-mentioned bird's beak. It should be noted that it is impossible to provide a bent portion which straight extends from the active area AR because of the presence of the bit line contact hole BH. The direction in which each word line WL extends is perpendicular to the direction in which each bit line BL extends. Each word line WL has the bent portion Z, which is composed of the areas Z1, Z2 and Z3. The area Z1 is orthogonal to the center line CL of the bit line CL. The areas Z2 and Z3 are located on both sides of the area Z1. Each of the areas Z2 and Z3 is orthogonal to the corresponding line which connects the center C BH of the bit line contact hole BH and the center C SH of the storage electrode contact hole SH. The areas Z2 and Z3 are arranged symmetically with the area Z1. According to the layout shown in FIG.4, the length L of each memory cell measured in the direction in which the bit line BL extends is as follows. L = 2 x (a + c + d + 2e) 2 - (1/2b + c + e) 2 It can be seen from the above formula that the length L of memory cell is not based on the distance WL' between the adjacent word lines. As a result, it is possible to increase the distance WL' and reduce the possibility of the occurrence of short circuiting. When the minimum distance between the adjacent lines is 0.5 [µm], the parameters are selected as follows. a = c = 0.3 [µm] b = d = 0.5 [µm] e = 0.4 [µm] WL' = 0.5 [µm] In this case, the length of each memory cell in the direction in which the bit line BL extends is 3.29 [µm]. On the other hand, the length of each memory in the same direction according to the aforementioned prior arrangement shown in FIG.1 is 3.35 [µm] when the distance between the adjacent word lines is set equal to 0.5 [µm]. The distance between the adjacent word lines according to the arrangement shown in FIG.4 is 0.8 [µm]. On the other hand, the distance between the adjacent word lines according to the prior arrangement shown in FIG.1 is 0.5 [µm]. The distance between the adjacent bit lines according to the arrangement shown in FIG.4 is 1.0 [µm]. On the other hand, the distance between the adjacent bit lines according to the prior arrangement shown in FIG.4 is 0.5 [µm]. The area of each memory cell according to the arrangement shown in FIG.4 is slightly less than that shown in FIG.1. The distance between the adjacent bit lines BL and the word lines WL in the memory cells is 1.6 - 2 times that of the prior arrangement. The cross section taken along line II'-II' is almost the same as that shown in FIG.2. The stacked capacitor is not limited to the structure shown in FIG.2. For example, it is possible to form the stacked capacitor so that the storage electrode SE has a single fin. It is also possible to form the stacked capacitor so that the single fin or the lowermost fin from among a plurality of fins is separated from the insulating layer and the opposed electrode is also provided between the single fin or the lowermost fin and the insulating layer. FIG.6 is a diagram showing the layout of four memory cells. In FIG.6, those parts which are the same as those in the previous figures are given the same reference numerals. It will be noted that the bent portion AR' of each active area AR shown in FIG.6 is greater than that shown in FIG.4. That is, the bent portion AR' of each active area AR is located under the corresponding word line WL. It will also be noted that a curved part Z' of each word line WL which crosses the bit line BL is curved without having the areas Z1, Z2 and Z3. Even in the arrangement shown in FIG.6, the imaginary line connecting the center C BH of the bit line contact hole BH and the center C SH of the storage electrode contact hole C SH is perpendicular to the curved part Z' of the word line WL. All of memory cell patterns can be formed by repeatedly arranging the layout shown in FIG.6. FIGS.7A, 7B and 7C are diagrams illustrating how the present invention was made. In FIGS.7A through 7C, those parts which have the same names as those described previously are given the same reference letters. Referring to FIG.7A, the dotted line illustrates the pattern of the conventional word line WL as shown in FIG.1. A contact hole formed in a fine pattern is approximately of a circle shape due to the intensity distribution of light. Thus, it is possible to consider each contact hole as a circle on the pattern layout drawing. The word lines are required to be separated from the bit line contact holes BH at a predetermined distance. Thus, it is possible to partially shape each word line WL into a circular arc in order to keep away from the bit line contact holes BH at the predetermined distance. As a result, dotted areas between the adjacent word lines WL become available. Thus, as shown in FIG.7B, it becomes possible to obliquely shift the positions of the storage electrode contact holes SH. Due to the positional change in the storage electrode contact holes SH, it becomes possible to shift the positions of the bit lines BL so that the bit line contact holes BH are located at the center thereof, as shown in FIG.7B. Thereby, it is possible to substantially eliminate the bit line extension portions as shown in FIG.1 or FIG.7A so that each bit line BL is substantially straight. In addition, it is possible to increase the distance between the adjacent bit lines BL from GP (FIG.7A) to GP' (FIG.7B). Further, due to this positional change of the storage electrode contact holes SH, it becomes possible to shift the positions of the word lines WL, as illustrated in FIG.7C. As a result, it becomes possible to increase the distance between the opposite edges of the adjacent word lines WL from W1 to W1', as shown in FIG.7C. On the other hand, the distance between the other opposite ends of the adjacent word lines WL is decreased, as shown in FIG.7C. It is possible to arbitrarily determine the distances W1' and W2' on the basis of various requirements. Moreover, FIG.8 is a block diagram of a folded bit line type DRAM. A plurality of pairs of bit lines, such as BL1 and BL1 , extend from corresponding sense amplifiers S/A. A plurality of word lines extend so as to cross the bit lines, as described previously. A memory cell MC is coupled between one of the bit lines and one of the word lines. The pattern arrangements according to the present invention are suitable for the folded bit line type DRAM as shown in FIG.8. However, the arrangements are also applicable to an open bit line type DRAM.

Claims: A dynamic random access memory comprising: a semiconductor substrate (1) having an active region (AR) including first and second diffusion regions (D, S) of a transfer transistor, an insulating layer (2, 3) formed on said semiconductor substrate and having first and second contact holes (SH, BH), a stacked capacitor (SC) having a storage electrode (SE) which is electrically connected to said first diffusion region through said first contact hole formed in said insulating layer and an opposed electrode (CP), a word line (WL) electrically isolated from said semiconductor substrate, and a bit line (BL) electrically isolated from said semiconductor substrate and electrically connected to said second diffusion region through said second contact hole formed in said insulating layer, a conductive layer forming the bit lines (BL) is located at a level lower than that of a conductive layer forming the opposed electrode (CP), said second contact hole being positioned at a center of said bit line, said active region (AR) being obliquely arranged with respect to said bit line (BL) and said word line (WL) such that the first contact hole (SH) does not overlap the bit line (BL), and the second diffusion region being disposed so as to cross the bit line, characterized in that said contact holes have an approximately circular shape, said word line has a bent portion (Z, Z', Z1, Z2, Z3) located between said first (SH) and second (BH) contact holes, said bent portion being substantially concentric with the centre of said second contact hole (BH) and comprising a plurality of straight segments separated from said second contact hole (BH) by a distance being equal to or larger than a predetermined minimum distance, and in that the active region (AR) comprises a bent active portion (AR') which is bent at the centre of said first contact hole (SH) and which extends towards said bit line (BL). A dynamic random access memory as claimed in claim 1, characterized in that said bent portion (Z, Z') of the word line is arranged so that said bent portion is orthogonal to an imaginary line which connects a center (C SH ) of said first contact hole (SH) and a center (C BH ) of said second contact hole (BH). A dynamic random access memory as claimed in claim 1, wherein said active region (AR) is arranged along an imaginary line which connects a center (C SH ) of said first contact hole (SH) and a center (C BH ) of said second contact hole (BH). A dynamic random access memory as claimed in any of claims 1 to 3, characterized in that said bent portion (Z') of the word line has an arc-shaped pattern. A dynamic random access memory as claimed in any of claims 1 to 3, characterized in that: said bent portion (Z) of the word line has a first area (Z1), a second area (Z2) and a third area (Z3) which are integrally formed in this order; said second area is orthogonal to said bit line; and one of said first and second areas is orthogonal to an imaginary line which connects a center (C SH ) of said first contact hole (SH) and a center (C BH ) of said second contact hole (BH). A dynamic random access memory as claimed in claim 5, characterized in that said first and third areas (Z1, Z3) are arranged in symmetry with each other about said second area. A danymic random access memory as claimed in claim 1, characterized in that: said active region (AR) comprises a straight portion integrally formed with said bent active portion (AR') thereof; and said bent active portion of the active region is partially in symmetry with said straight portion about said center (C SH ) of the first contact hole (SH). A dynamic random access memory as claimed in claim 1, characterized in that said bent active portion (AR') of the active region (AR) has an end which is located below said bit line (BL). A dynamic random access memory as claimed in claim 1, characterized in that said bent active portion (AR') of the active region (AR) is obliquely arranged with respect to said bit line (BL). A dynamic random access memory as claimed in any of claims 1 to 9, characterized in that: an imaginary line which connects a center (C SH ) of said first contact hole (SH) and a center (C BH ) of said second contact hole (BH) is inclined at an angle  with respect to a direction in which said bit line (BL) extends; and said angle  is defined substantially as follows:  = sin -1 [(1/2b + e + c) / (a + c + d + 2e)] where a: half a width of the second contact hole, e: an alignment margin of each of said first and second contact holes, d: a width of the word line, c: half a width of said second contact hole, and b: a width of said bit line. A dynamic random access memory as claimed in any of claims 1 to 10, characterized in that said first diffusion region is a drain region (D) and said second diffusion region is a source region (S). A dynamic random access memory according to claim 1, comprising on said semiconductor substrate (1): a plurality of said active regions (AR) each including first and second diffusion regions (D, S) of a respective transfer transistor, said insulating layer (2, 3) having a plurality of first contact holes (SH) and a plurality of second contact holes (BH), a plurality of said stacked capacitors (SC) each having a storage electrode (SE) which is electrically connected to a corresponding one of said first diffusion regions through a corresponding one of said first contact holes formed in said insulating layer, and an opposed electrode (CP), a plurality of said word lines (WL) electrically isolated from said semiconductors substrate, and a plurality of said bit lines (BL) electrically isolated from said semiconductor substrate, each of said bit lines being electrically connected to a corresponding one of said second diffusion regions through a corresponding one of the second contact holes formed in said insulating layer, each of said second contact holes being positioned at a center (CL) of said bit lines, each of said active regions (AR) being obliquely arranged with respect to said bit lines (BL) and said word lines (WL), the second diffusion region being disposed so as to cross the bit line, wherein each of said word lines has a plurality of said bent portions (Z, Z') located between corresponding first and second contact holes each bent portion being separated from a corresponding one of said second contact holes by said predetermined distance, and each of said active regions (AR) comprises a bent active portion (AR') which is bent at a center of a corresponding one of the first contact holes (SH) and which extends toward a corresponding one of the bit lines (BL). A dynamic random access memory as claimed in claim 12, characterized in that: each of said first contact holes (SH) is located at an almost equal distance from two adjacent word lines from among said plurality of word lines (WL); each of said first contact holes is located at an almost equal distance from two adjacent bit lines from among said plurality of bit lines (BL). A dynamic random access memory as claimed in claim 12 or claim 13, characterized in that each bent portion (Z, Z') of each of the word lines (WL) is arranged so that each bent portion is orthogonal to an imaginary line which connects a center (C SH ) of said corresponding one of the first contact holes (SH) and a center (C BH ) of said corresponding one of the second contact holes (BH). A dynamic random access memory as claimed in claim 12, characterized in that each of said active regions (AR) is arranged along an imaginary line which connects a center (C SH ) of a corresponding one of said first contact holes (SH) and a center (C BH ) of a corresponding one of said second contact holes (BH). A dynamic random access memory as claimed in any of claims 12 to 15, characterized in that each bent portion of each of the word lines (WL) has an arc-shaped pattern (Z'). A dynamic random access memory as claimed in any of claims 12 to 15, characterized in that each of said active regions (AR) comprises a bent active portion (AR') extending toward a corresponding one of the bit lines (BL). A dynamic random access memory as claimed in claim 17, characterized in that: each of said active regions (AR) comprises a straight portion integrally formed with said bent active portion (AR') thereof; and said bent active portion of each of the active regions is partially in symmetry with said straight portion about said center (C SH ) of said corresponding one of the first contact holes (SH). A dynamic random access memory as claimed in claim 17, characterized in that said bent active portion (AR') of each of said active regions (AR) has an end which is located below a corresponding one of the bit lines (BL). A dynamic random access memory as claimed in claim 17, characterized in that said bent active portion (AR') of each of said active regions (AR) is obliquely arranged with respect to a corresponding one of the bit lines (BL). A dynamic random access memory as claimed in any of claims 12 to 20, characterized in that: an imaginary line which connects the center of one of said first contact holes (SH) and a center of a corresponding one of said second contact holes (BH) is inclined at an angle  with respect to a direction in which said bit lines (BL) extend; and said angle  is defined as follows:  = sin -1 [(1/2b + e + c) / (a + c + d + 2e)] where a: half a width of each of the second contact holes, e: an alignment margin of each of said first and second contact holes d: a width of each of the word lines, half a width of each of said second contact holes, and b: a width of said bit lines. A dynamic random access memory as claimed in any of claims 12 to 21, wherein said bit lines are of a folded-bit line type. A method of arranging structural elements of a dynamic random access memory according to claim 1 or 12 comprising the steps of: determining a first position (C SH ) which is separated from a center (CL) of said bit line at a first predetermined distance; determining a second position (C BH ) which is located at the center of said bit line and which is separated from said first position at a second predetermined distance; and determining a position of said word line (WL) so that said word line is located between said first and second contact holes, wherein: said first position corresponds to a center (C SH ) of said first contact hole (SH); and said second position corresponds to a center (C BH ) of said second contact hole (BH). A method as claimed in claim 23, characterized in that: said first predetermined distance is approximately equal to b/2 + c + e where b is a width of said bit line, c is half a width of said first contact hole, and e is an alignment margin of each of said first contact holes; said second predetermined distance is approximately equal to a + c + d + 2e where a is half a width of said second contact hole. A method of arranging structural elements of a dynamic random access memory according to claim 1 or 12 comprising the steps of: determining a first position (C BH ) which is located at a center (CL) of said bit line; determining a second position (C SH ) which is located on an imaginary line extending from said first position at a predetermined angle () with respect to said bit line and which is separated from the center of said bit line at a predetermined distance; and determining a position of said word line (WL) so that said word line is positioned between said first and second contact holes, wherein: said first position corresponds to a center (C BH ) of said second contact hole (BH); and said second position corresponds to a center (C SH ) of said first contact hole (SH). A method as claimed in claim 25, characterized in that: said predetermined angle  is defined substantially as follows:  = sin -1 [(1/2b + e + c) / (a + c + d + 2e)] where a: half a width of said second contact hole, e: an alignment margin of each of said first and second contact holes, d: a width of said word line, c: half a width of said second contact hole, and b: a width of said bit line; and said predetermined distance is approximately equal to b/2 + c + e.

Inventors: EMA TAIJI, EMA, TAIJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01L27
IPC codes: H01L27