Method for producing a semiconductor device comprising a conductive layer

Abstract: An element which includes a first film containing no impurity particles due to spontaneous oxidization or residual resist at its surface, and an electrically conductive material layer formed on a surface in contact with the surface of said first film. On the surface of the electrically conductive material layer is formed an insulating compound film as a result of surface reaction with the electrically conductive material layer, and on the surface of said first film is formed a desired second film that is necessary for constituting the element.

Description: Technical Field The present invention relates to a method for producing a semiconductor device. Background Art Problems of conventional semiconductor integrated circuits will be described below by taking the following three arrangements as examples. The first example is a bipolar transistor. An ECL (Emitter Coupled Logic) circuit is available as the most typical circuit using a bipolar transistor, and its switching time t pd is represented by the following relation: t pd ∝ r bb' [AC TCl + C dl ] + V S •(C TSl + C del )/I CS where r bb' : the base resistance of an input transistor A : the voltage amplification factor of a current switching circuit V S : the logic amplitude voltage C TCl : the base-collector junction capacitance of the input transistor C dl : the diffusion capacitance and the emitter-base junction capacitance of the input transistor I CS : the current amount of the input transistor C TSl : the collector-side parasitic capacitance of the input transistor C del : the diffusion capacitance of an output emitter-follower transistor. As is apparent from the above relation, in case of a low-current region, i.e., a region of small I CS for the ECL circuit, a delay time is determined by a collector response time in the second term of relation (1). On the other hand, a base response time in the first term in the relation becomes dominant in a region where I CS is large. That is, reduction in r bb' and C TC and that in the diffusion capacitance, i.e., an improvement in an f T value is an important factor of increasing an operation speed. To realize a high operation speed, a transistor using an SST (Super-Self-aligned process Technology) as shown in Fig. 15 is currently proposed. Referring to Fig. 15, reference numeral 201 denotes a p-type semiconductor substrate; 202, a p + -type semiconductor isolation region for isolating adjacent elements; 203, an n + -type buried layer (n + -BL); 204, an n-type epitaxial layer; 205, a field oxide layer; 206, an Si 3 N 4 film; 207, a p-type base region; 208, a p + -type polycrystalline Si base electrode; 209, an n + -type emitter region; 210, an n + -type polycrystalline Si emitter electrode; and 211, 212, and 213, base, emitter, and collector electrodes, respectively, each consisting of a metal. Fig. 16 shows the emitter and base regions of this conventional example in an enlarged scale. As is apparent from Fig. 16, since the p + -type polycrystalline Si base electrode 208 for a base contact is formed close to the emitter region 209, an external base current is reduced. The above conventional example, however, has the following problems. (1-1) A natural oxide film 214 is present in the interface between the n + -type polycrystalline Si layer 210 and the p-type base region 207 of the single-crystal epitaxial layer 204 to cause a variation in bipolar characteristics (especially, an emitter ground current amplification factor). The emitter region 209 in this structure is normally called a DOPOS (Doped Poly Silicon) emitter which is formed by doping an impurity in the n + -type poly silicon layer 210 into the portion 209 of the epitaxial layer by thermal diffusion. However, since a wafer must be temporarily exposed to the outer air before formation of the n + -type poly Si layer 210 on the p-type base region 207, the natural oxide film 214 is formed on the p-type base region 207. The natural oxide film 214 is nonuniform because the process control is impossible. As a result, the diffusion of the impurity into the p-type base region 207 becomes nonuniform.To settle the matter radically, therefore, a process not forming any natural oxide film must be adopted. In the current circumstances, however, since a contact hole patterning step for the emitter region 209 is necessary before formation of the n + -type poly Si layer 210, the upper surface of the p-type base region 207 of the epitaxial layer 204 is inevitably exposed to the outer air and a natural oxide film is formed on the surface.. (1-2) When the contact hole formation step (hole formation) for forming the emitter region 209 is performed by dry etching, the base region 207 present below the emitter region 209 is damaged. Although wet etching may be performed as etching free from a damage, since the size of a contact hole is inevitably increased when the wet etching is used, no micropatterned emitter region can be formed. Although a dry etching method causing no damage has been developed, the method is currently still unsatisfactory. (1-3) A base resistance is still high to interfere with a high-speed operation. That is, although an external base resistance is reduced in the bipolar transistor using the SST described above as compared with conventional transistors, it is still high because poly Si is used as the material of the base electrode 208. Problems of a MOSFET will be described below. (2-1) Degradation in a drain current I P and g m (≡ ∂I P /∂I G ) becomes significant due to a parasitic resistance as the degree of micropatterning is increased. Fig. 17 shows calculated values and measured values in a relationship between an effective channel length (abscissa) and a drain current (ordinate) obtained in an LDD (Lightly Doped Drain) structure which is used most often among conventional micropatterned MOSFETs. The calculation is performed using an equivalent circuit model formed in consideration of a parasitic resistance and speed saturation. As is apparent from Fig. 17, as the effective channel length approaches 0.2 µm, the parasitic resistance is increased, and current reduction in a nonsaturated region becomes significant. (2-2) In a conventional MOSFET structure in which a source·drain region is formed by a diffusion layer, a channel length is significantly decreased in a micropatterned region. Fig. 18 shows a change in threshold voltage (ordinate) as a function of a channel length L (abscissa) using a depth X j of a source•drain diffusion layer as a parameter. As shown in Fig. 18, in an ordinary MOSFET, reduction in threshold value becomes significant because the channel length is decreased when the depth X j is large. However, since a source•drain diffusion layer of a conventional MOSFET is formed by ion implantation using a gate as a mask, the minimum value of X j is at most about 0.1 µm, and it is difficult to form a source·drain portion having a depth smaller than this value. (2-3) Selection of a gate material is considerably limited. In a conventional MOSFET, a source•drain diffusion layer is formed by ion implantation using a gate as a mask. Therefore, a gate material is required to satisfy the following conditions. (1) The gate material must have an ion-implantation resistance. (2) Since a heat treatment is performed at a temperature of 550°C or more to activate the source·drain formed by ion implantation, the material must withstand a temperature of 550°C or more. (3) The gate material must allow formation of an insulating layer around the gate portion in order to prevent a leakage current between the gate and the source•drain. (4) The gate material must have a low resistance to realize a high-speed operation. (5) The gate material must have a predetermined work function to suppress reduction in threshold value caused by a short channel length. If Al, for example, is used as the gate material to achieve a low resistance, the problem of heat resistance described in item (2) above is satisfied. Lastly, problems in conventional wiring will be described below. Fig. 19 is a view showing conventional wiring steps, in which reference numeral 215 denotes a substrate or a wafer layer, e.g., a p-type semiconductor layer. Reference numeral 216 denotes a field oxide film; 217, a diffusion layer for contact with respect to wiring, which is an n + -type semiconductor layer in this example; 218, an insulating layer such as SiO 2 formed by a CVD apparatus; 219, a wiring metal; and 220, a resist for patterning the wiring metal 219. Fig. 19(a) is a view showing a step in which resist patterning is finished. The resultant wafer is conveyed into an RIE (Reactive Ion Etching) apparatus, and its metal wiring is etched as shown in Fig. 19(b). Referring to Fig. 19(b), reference numeral 222 denotes an etching residue of the wiring metal. The etching residues 222 are produced because a metal enters microspaces on the surface of the insulating layer 218 or the resist 220 is scattered in an RIE atmosphere when the wafer is exposed to the atmosphere and the scattered resist components adhere on the metal surface to form masks. These residual metal components cause a leakage current. Fig. 19(c) shows a step of removing the resist obtained by patterning the wiring metal after the etching. As shown in Fig. 19(c), removal of the resist and washing are generally performed using an organic substance such as trichloroethylene. However, residues 223 of the resist are produced in such a method. Although a method (so-called O 2 ashing) of leaving a wafer to stand in an oxygen plasma to remove a resist may be used, a damage is produced because the wafer is left to stand in the plasma. As described above, the conventional wiring steps have the following problems. (3-1) A wiring metal remains at a microlevel on the surface of an insulating layer, and a leakage current is flowed through this residual metal. (3-2) A resist used in patterning of wiring is not perfectly removed, and an organic impurity remains on a wafer. (3-3) When O 2 ashing is performed in resist removal, a damage caused by a plasma is produced inside a wafer. As a result, in conventional techniques, even if attempts are made to keep clean surface conditions on various film surfaces (e.g., a semiconductor surface and an insulating layer surface) having important effects on device characteristics, mixing of an impurity caused by a natural oxide film or a resist residue cannot be prevented. Therefore, there exists no device in which neither a natural oxide film nor an impurity remains on the surface of each film surface. The article "Modern Bipolar Technology For Gate Array And Memory Applications" by W. M. Werner et al., published in Siemens Research and Development Reports, Vol. 17 (1988), No. 5, p. 221-226, discloses a prior art method of making a bipolar transistor having a self-aligned emitter-base structure. Furthermore, a method of manufacturing a bipolar transistor wherein a conductive material is formed on a portion of a doped semiconductor layer not covered by an insulating film and an side surfaces of said insulating film is disclosed in JP-A-64 002362 and the corresponding abstract. It is an object of the present invention to provide a method for producing a semiconductor device which is free from the drawbacks as discussed above. This object is achieved by a method for producing a semiconductor device according to claim 1. Advantageous further developments of the invention are as defined in the dependent claims. Operation The present invention will be described with reference to the accompanying drawings. In an arrangement shown in Fig. 1, a device is a bipolar transistor in which a first film is a base layer 7. In Fig. 9 showing an arrangement in which a device is a MOSFET, a first film is a gate insulating film 59. In Fig. 13 showing a semiconductor device as an example of a device having wiring, a first film is an insulating interlayer 86. In the present invention, an insulating film (31, 66, and 90 shown in Figs. 4, 10, and 14, respectively) is formed on the surface of the first film. This insulating film consists of an insulating material which can be selectively dry-etched with respect to an insulating compound to be formed later. For example, SiO 2 formed by a chemical vapor deposition method or a material obtained by doping an impurity in this SiO 2 may be used. Subsequently, in the present invention, a conductive material layer of metal or silicide is formed on a surface adjacent to the surface of the first film. In the arrangement shown in Fig. 4, the surface adjacent to the surface of the first film is a surface except for the surface of a source layer 7 on which an insulating film 31 is formed. In the arrangement shown in Fig. 10, the surface is the surfaces of source and drain regions 55 and 56. In the arrangement shown in Fig. 13, the surface extends from the surface of an n + -type layer 85 to the exposed surface of the insulating interlayer 86. The type of the metal or silicide conductive material is not particularly limited as long as the material has conductivity and can form an insulating compound on the surface by a surface reaction. For example, a metal or silicide capable of reacting with O 2 or F 2 gas to form an insulating compound on the surface can be used. The present invention has one feature in the formation of this conductive material layer. That is, the feature of the present invention is that the side surfaces of the insulating film are not covered by the conductive material layer of metal or silicide. To form the conductive material layer in this manner, the insulating film may be formed to have an inversely tapered shape. Alternatively, the film formation conditions during the formation of the insulating film, particularly, the wafer temperature and the bias voltage may be controlled to decrease the migration of conductive material grains. In this case, the "migration" means surface diffusion of the conductive material grains. That is, the migration is the degree of diffusion of the conductive material grains on the surface. After the formation of the conductive material layer, an arbitrary gas is used to form an insulative compound film of the conductive material on the surface of the conductive material layer. Examples of the gas are O 2 and F 2 gases. After the formation of the insulating compound film, an arbitrary dry gas is used to perform dry etching for the insulating film. Examples of the dry gas are HF gas and HF gas diluted by N 2 gas. The gas does not etch the insulating compound film formed on the conductive material layer surface but selectively etches only the insulating film. Since the side surfaces of the insulating film are exposed, the insulating film and the conductive material deposited on the insulating film are removed, and the surface of the first film is exposed because, e.g., a contact hole is formed on the surface of the first film. That is, since the conductive material and the insulating compound film formed on the surfaces of the conductive material play a role as a mask, the second film necessary for a device configuration can be formed on only the surface of the first film. Since the present invention adopts the above arrangement, a surface on which the second film is to be formed is covered until the second film is formed. Therefore, no natural oxide film or the like is formed on the prospective formation surface of the second film. In addition, since the contact hole can be formed without using any resist, mixing of an impurity caused by a resist residue can be prevented. Furthermore, since the formation of the contact hole can be performed without using, e.g., the RIE method, a damage to the prospective formation surface of the second film caused by the RIE can be prevented. Moreover, since the conductive material layer plays a role as a mask in the formation of the second film, a self-alignment is enabled to realize formation of a micropatterned device. Brief Description of Drawings Fig. 1 is a sectional view showing a bipolar transistor produced according to the first embodiment of the present invention, Fig. 2 is a plan view showing the bipolar transistor produced according to the first embodiment of the present invention, Fig. 3 is a sectional view showing a connection portion between a base electrode and wiring of the bipolar transistor produced according to the first embodiment of the present invention, Fig. 4 is a view showing manufacturing steps of the method for producing a bipolar transistor according to the first embodiment of the present invention, Fig. 5 is a sectional view showing a bipolar transistor produced according to the second embodiment of the present invention, Fig. 6 is a sectional view showing a bipolar transistor produced according to the third embodiment of the present invention, Fig. 7 is a sectional view showing a bipolar transistor produced according to the fourth embodiment of the present invention, Fig. 8 is a view showing manufacturing steps of the method for producing a bipolar transistor according to the fourth embodiment of the present invention, Fig. 9 is a sectional view showing a MOSFET produced according to the fifth embodiment of the present invention, Fig. 10 is a view showing manufacturing steps of the method for producing a MOSFET according to the fifth embodiment of the present invention, Fig. 11 is a sectional view showing a MOSFET produced according to the sixth embodiment of the present invention, Fig. 12 is a sectional view showing a MOSFET produced according to the seventh embodiment of the present invention, Fig. 13 is a view showing a wiring structure produced according to the eighth embodiment of the present invention, Fig. 14 is a view showing manufacturing steps of the method for producing a wiring structure according to the eighth embodiment of the present invention, Fig. 15 is a view showing a structure of a conventional high-speed bipolar transistor, Fig. 16 is an enlarged view showing an emitter portion of the structure of the conventional high-speed bipolar transistor, Fig. 17 is a graph showing a change in drain current upon a decrease in channel length of a conventional MOSFET, Fig. 18 is a graph showing a change in threshold value upon a decrease in a channel length of the conventional MOSFET, and Fig. 19 is a view showing conventional wiring steps. 1 denotes substrate; 2 denotes element isolation diffusion layer; 3 denotes buried layer; 4 denotes epitaxial layer; 5, 54, 84 denote field oxide films; 7 denotes base thin film; 8 denotes buried base electrode; 14, 88, 60 denote insulating layers; 15 denotes n-type semiconductor; 16 denotes wide-gap n + -type semiconductor; 11 denotes emitter electrode; 12 denotes collector electrode; 13, 89 denote passivation films; 51 denotes buried layer; 52 denotes channel stopper layer; 53, 83 denote well layer; 55 denotes source layer; 56 denotes drain layer; 59 denotes gate oxide film; 62 denotes source electrode; 63 denotes drain electrode: and 64 denotes gate electrode. Embodiments of the present invention will be described in detail below. (1st Embodiment) Fig. 1 shows a sectional structure of a bipolar transistor produced according to the first embodiment of the present invention. Referring to Fig. 1, reference numeral 1 denotes a p-type Si substrate; 2, an element isolation p + -type semiconductor layer; 3, an n + -type semiconductor buried layer for obtaining a collector potential; 8, a conductive material (a buried metal for a base electrode) such as Al or Cu; 5, a field oxide film; 4, an n-type epitaxial layer; 7, a base layer consisting of a p + -type semiconductor; 14, an insulating layer formed on the surface of the base electrode buried metal 8; 6, an n + -type semiconductor layer for connecting a collector electrode 12 and the n + -type semiconductor buried layer 3; 15, an n - -type Si layer for forming an emitter region; 16, an n + -type semiconductor thin film having a band gap wider than that of Si and consisting of, e.g., a single-crystal material or a polycrystalline material of Si x C 1-x Ge y (0 < x < 1 and 0 < y < 1), a polycrystalline Si x C 1-x : H material, a micro-crystal Si x C 1-x : H material, and a micro-crystal Si : H material; 11 and 12, emitter and collector wiring metals; and 13, a passivation film consisting of, e.g., Si 3 N 4 . Although the base electrode 8 is kept buried in Fig. 1, it can be caused to contact the wiring metal on the insulating interlayer in a region separated from the peripheral portion of the emitter region 15, as shown in Fig. 2. Referring to Fig. 2, reference numeral 17 denotes an emitter contact hole; 18, a collector contact hole; 19, a through hole for connecting the base buried metal 8 with the wiring metal on the insulating interlayer; and 20, base electrode wiring on the insulating interlayer. Fig. 3 is a sectional view showing a portion around the through hole 19. As is apparent from Fig. 3, since the upper surface (a surface opposite to the base region 7, i.e., a surface on the opposite side) of the base buried electrode 8 is covered with the insulating layer 14, the electrode 8 is in contact with the upper electrode 20 through the semiconductor heavily doped impurity diffusion layer (n + -type diffusion layer) 9. The base buried electrode 8 is formed on the field oxide film 5 and therefore does not particularly lead to an increase in parasitic capacitance in a base-to-collector path. The characteristics of the above bipolar transistor are as follows. (1) Since the base wiring consists of a conductive material and the emitter region is formed through a thin insulating layer formed on the surface of the base wiring, an external base resistance is reduced to its limit to improve frequency characteristics. (2) As shown in Fig. 2, since no contact hole for a base electrode need be formed around the emitter, the device size can be decreased. (3) An emitter·base junction has a flat surface, and a junction capacitance in an emitter-to-base path is small. (4) Since the transistor is manufactured by a manufacturing method (to be described below) on the interface on which an emitter thin film is formed, no natural oxide film is present. A method for producing the bipolar transistor according to the first embodiment of the present invention will be described below with reference to Fig. 4. A p-type high-resistance substrate is used as an Si substrate 1 shown in Fig. 4(a). First, the surface of the Si substrate 1 is oxidized to form an SiO 2 film 22, and a photoresist process is performed. Subsequently, as shown in Fig. 4(a), the SiO 2 film 22 is selectively etched, and an n-type impurity is diffused at a high concentration into a predetermined position of the Si substrate 1 to form a collector buried layer (n + -BL) 3. Sb or the like having a small diffusion constant can be preferably used as the impurity to be doped in the collector buried layer 3 in order to minimize spreading of the impurity caused when a heat-treatment (to be described later) is performed. Alternatively, since Sb has a low solid solubility, As may be used as the impurity to be doped in order to decrease the resistance of the collector buried layer 3. In this case, to prevent re-distribution of As, the temperature of a heat treatment may be decreased or auto doping may be prevented in epitaxial growth. Subsequently, epitaxial growth is performed on the collector buried layer 3 to form an n-type single-crystal layer 4 (Fig. 4(b)) to have a thickness of about 1.0 to 0.8 µm. The impurity concentration of the single-crystal layer 4 is 10 15 to 10 17 /cm 3 . After the epitaxial growth, as shown in Fig. 4(b), the surface of the single-crystal layer 4 is oxidized to form a thin oxide film (oxide SiO 2 film) 25, and an Si 3 N 4 film 26 serving as a mask for selective oxidation is formed by a CVD method. Subsequently, a photoresist process for forming an isolation pattern (an isolation oxide film 5 shown in Fig. 4(d)) is performed to etch the Si 3 N 4 film 26 and the SiO 2 film 25, and etching of the n-type single-crystal layer (epitaxial growth layer 4) is performed. As indicated by reference numeral 27 in Fig. 4(c), the etching of the n-type single-crystal layer 4 is performed to the middle portion of the epitaxial layer 4 so that the bottom surface (5a in Fig. 4(d)) of the isolation oxide film 5 (to be formed later) is formed to be in contact with the collector buried layer 3. Thereafter, B + ion implantation is performed in a region indicated by reference numeral 2 in Fig. 4(d) to form an element isolation region 2 for ensuring isolation. After the ion implantation, an annealing is performed to prevent production of defects, and selective oxidation is performed at a temperature of 900°C to 1050°C to form the isolation oxide film 5, as shown in Fig. 4(d). Since the temperature of the selective oxidation is as high as 900°C to 1050°C, it is preferred to shorten the oxidation time using a high-pressure oxidation method so that the impurity doped in the collector buried layer 3 does not cause re-distribution. Subsequently, the Si 3 N 4 film 26 used as a mask for the selective oxidation is removed, and phosphorus is diffused in a collector extraction region as indicated by reference numeral 6 in Fig. 4(e). After a heat treatment is performed to activate the phosphorus-diffused layer, the SiO 2 layer 25 is etched until the Si surface of the epitaxial layer 4 is exposed. A material such as HF : H 2 O = 1 : 100 may be used as an etchant. The resultant wafer is conveyed into an RF-DC coupled bias sputtering apparatus, and a 10 nm (100-Å) thick p + -type Si film is formed on the wafer. Subsequently, patterning is performed as shown in Fig. 4 (e) by a photoresist process. The p + -type Si film 7 thus formed serves as a base layer. Note that the film formation conditions of the p + -type Si film 7 are, for example, as follows. That is, polycrystalline Si doped with 1 x 10 19 to 1 x 10 20 cm -3 of B (boron) is used as a target, and the wafer is conveyed into a chamber. A DC bias of -25 V and RF power of 5 W having a frequency of 100 MHz are applied to the target side, and a DC bias of +7 V is applied to the wafer side. As a result, the wafer surface is cleaned, i.e., an impurity on the wafer surface is removed without causing any damage to the wafer itself. Ar gas, for example, is used as a plasma generation gas, and the Ar pressure is set at, e.g., 1,066 Pa (8 m Torr). After the cleaning, the DC bias and the RF power on the target side, for example, are increased to -200 V and 40 W, respectively, and the surface voltage on the wafer side is set at 5 to 10 V. The wafer temperature may be set at 300°C to 400°C. Subsequently, the wafer having the patterned base thin film 7 is conveyed into an atmospheric CVD apparatus, and a nondoped SiO 2 layer is formed. A resist mask is used to perform patterning by the RIE to obtain an inversely tapered shape as indicated by reference numeral 31 in Fig. 4(f). The inversely tapered SiO 2 layer 31 is caused to remain on a prospective formation portion of the emitter, on the field oxide film 5, and on the collector extraction region 6. The film formation temperature of SiO 2 in the atmospheric CVD may be set at, e.g., 300°C to 400°C. The resist used in the patterning of the SiO 2 layer 31 is removed by H 2 SO 4 : H 2 O 2 = 4 : 1, and the wafer is washed with water. Thereafter, the natural oxide film formed on the base thin film surface is removed by an etchant HF : H 2 O = 1 : 100, and the resultant wafer is subjected to washing with water and N 2 blow-drying. Subsequently, formation of a metal or silicide conductive material is performed. That is, the wafer is conveyed into the RF-CD coupled bias sputtering apparatus. The target is changed to a metal or silicide conductive material such as Al, and a conductive material (Al film) 8 is formed to have a thickness of 200 nm to 400 nm (2000 Å to 4000 Å), as shown in Fig. 4(g). The film formation conditions are, for example, as follows. That is, after Ar gas at 0.399 Pa (3 mm Torr) is supplied into the chamber, a DC bias of -25 V and RF power of 5 W having a frequency of 100 MHz are applied to the Al target side, and a DC bias of +7 V is applied to the wafer side. The wafer is left to stand for five minutes to clean its surface. Thereafter, the bias and the RF power on the target side are increased to -200 V and 80 W, respectively, and the surface potential on the wafer side is set at 0 to -20 V. The substrate temperature is set at, e.g., room temperature. When film formation is performed under the above conditions, conductive material grains (Al grains) sputtered from the target do not adhere on side wall portions of the CVD SiO 2 film 31 but form a film on only the base thin film 7, the field oxide film 5, and the CVD SiO 2 film 31. This film formation is achieved by 1 ○ setting film formation conditions such that the degree of migration (surface diffusion) on the wafer surface is reduced or 2 ○ forming the CVD SiO 2 film 31 into an inversely tapered shape. The film formation conditions of reducing the migration degree described in item 1 ○ above are achieved by decreasing the wafer temperature and the energy of Al grains bombarded on the wafer (more specifically, decreasing the DC bias voltage applied on the wafer). To reduce a variation in energy of the bombarded Al grains, the frequency is preferably set at 100 MHz or more. Note that since practical conditions change in accordance with individual situations, film formation conditions under which the migration degree is decreased may be predetermined by an experiment or the like. After the formation of the CVD SiO 2 film 31, in order to form an insulating layer on the surface of the Al film 8, the wafer is conveyed in a vacuum into a chamber, and F 2 gas, for example, is supplied into the chamber to form an insulating layer (AlF film) 14 having a thickness of about 100 nm (1000 Å) on the surface of the Al layer 8. In the formation of the insulating layer 14, O 2 gas may be used to form Al 2 O 3 (alumina) on the Al surface in place of fluoridization caused by F 2 gas. Subsequently, when HF gas is supplied into the chamber, the CVD SiO 2 film 31 is selectively removed by this HF gas. In this case, if the wafer is set to face downward, the Al film 8 formed on the surface of the CVD SiO 2 film 31 and the insulating layer 14 formed on the surface of the Al film 8 automatically fall by gravity upon removal of the CVD SiO 2 film 31. As a result, a structure as shown in Fig. 4(h) is obtained. A space for recovering the falling object consisting of the Al film 8 and the insulating layer 14 formed on the surface of the Al film 8 may be provided on the bottom surface of the chamber via a gate valve. In this case, the gate valve is kept open when the falling object is present. After the HF gas treatment is performed, the gate valve is closed to leak the recovery space to discharge the falling object consisting of the Al film 8 and the insulating layer 14 on the surface of the Al film 8 out of the chamber. The interior of the chamber is always kept clean by this manipulation. Since the field oxide film 5 consists of SiO 2 formed by thermal oxidation, the field oxide film 5 is not etched at all by diluting HF gas by N 2 gas to be about 0.1 to several vol%. With this process, patterning can be performed by a so-called lift-off in the chamber. At the same time as or after the HF gas etching is performed, an Xe lamp or a UV lamp is preferably turned on to illuminate the wafer surface for the following reason. That is, when the HF gas treatment is performed, although F may partially remain on the wafer surface to produce defects in an emitter thin film formed in the subsequent step, the illumination of the Xe or UV lamp can prevent the production of defects. If the CVD SiO 2 31 consists of PSG, a residue of a compound P 2 F 5 is produced on the Si surface (the surface of the base thin film 30) when the HF etching is performed. However, when several % of Cl 2 gas are mixed in HF gas diluted by N 2 gas described above, it is possible to remove P in the form of PCl 3 . In the above embodiment, the removal of SiO 2 formed by a CVD apparatus of HF-N 2 -Cl 2 gas type is described. However, the above selectivity can be obtained by supplying ClF 2 gas upon radiation of UV light. Subsequently, the resultant wafer is conveyed to the DC coupled bias sputtering apparatus through an N 2 tunnel or a vacuum tunnel. The target of the RF-DC coupled bias sputtering apparatus is changed to n-type Si, and a 10 nm (100 Å) thick n-type Si thin film 15 is formed. Note that cleaning may be performed using an H plasma upon film formation. An impurity concentration in the n-type Si thin film 15 may be set at 10 16 to 10 18 cm -3 . As the film formation conditions, the same bias and RF power as those of the base thin film formation are set. In this embodiment, the target material is further changed to n + -type Si x C y Ge z (preferably, x = 0.475, y = 0.475, and z = 0.05), and an n + -type semiconductor material having a wide band gap is formed to have a film thickness of 200 nm (2000 Å), as indicated by reference numeral 16 in Fig. 4(i). This thin film 16 serves as a hetero emitter. When the values of the above x , y , and z are set at predetermined values, a good single-crystal Si x C y Ge z thin film can be formed since matching in lattice constant with respect to Si of the n-type Si thin film 15 is obtained. After the formation of the emitter thin films 15 and 16, the emitter thin films 15 and 16 are patterned as shown in Fig. 4(h), and a resist used in the patterning is removed. Thereafter, the resultant wafer is conveyed to the atmospheric CVD apparatus to form an insulating interlayer 21. After formation of the insulating interlayer 21, a contact hole is formed, and a film of a wiring material is formed by the RF-DC coupled bias sputtering and patterned. Finally, a passivation Si 3 N 4 film is formed on the resultant structure by a plasma CVD apparatus. As is apparent from the above description, (1) A wafer is not exposed to the outer air from the base electrode metal formation step to the emitter thin film formation step, and a base surface is cleaned by light radiation and a predetermined gas. Therefore, neither a natural oxide film nor other impurities are present on an emitter•base interface. (2) Since an Si surface of a prospective emitter formation portion is protected by SiO 2 before formation of an emitter and is not exposed to a dry etching atmosphere, no damage is caused in the portion. (3) In the above process, micropatterning of an emitter can be performed because an emitter size is determined by the edge of a base electrode metal. Although element isolation is performed by the LOCOS in the above embodiment, various types of methods such as trench type element isolation and V-trench type element isolation can be performed as well as the above isolation technique. The above embodiment is described by taking a method for producing a hetero bipolar transistor using a material having a large band width as an example, but the present invention is not limited to this embodiment. For example, the present invention may be applied to an arrangement in which an Si x Ge 1-x (0 < x < 1) thin film is used as the base layer 7 and n-type and n + -type Si thin films are used as the emitter thin films 15 and 16, respectively, or an arrangement in which a superlattice thin film of Si and Si x Ge 1-x (0 < x < 1) is used as the base layer. (2nd Embodiment) The second embodiment of the present invention will be described below with reference to Fig. 5. In Fig. 5, the same reference numerals as in the first embodiment denote the same parts and a detailed description thereof will be omitted. The second embodiment differs from the first embodiment in that the metal or silicide conductive material for burying a base electrode consist of a plurality of conductive materials 36 and 37 and the conductive material 36 in contact with the base layer 7 has a low Schottky barrier with respect to a p-type Si layer. Preferable examples of the material 37 having a lower Schottky barrier height with respect to the p-type Si layer are Mo (molybdenum) and W (tungsten). The metal or silicide conductive material 37 may be a wiring metal such as Al. The method of the second embodiment can be easily realized by using the above metal target as a target of an RF-DC coupled bias sputtering apparatus of the second embodiment to continuously form films. With the method of the second embodiment, a contact resistance with respect to a base layer is further decreased to advantageously decrease an external base resistance. When the transistor produced by the method of this embodiment is of a pnp type, a metal having a low Schottky barrier height with respect to n-type Si or its silicide, e.g., Ti, Ni, TaSi 2 , or TiSi 2 can be used as the material of the metal 36. (3rd Embodiment) The third embodiment of the present invention will be described below with reference to Fig. 6. In Fig. 6, as is the case with the second embodiment, the same reference numerals as in the first embodiment denote the same parts and a detailed description thereof will be omitted. The third embodiment is identical to the second embodiment in that the metal or silicide conductive material for burying a base electrode consists of at least two types of materials 38 and 39 but differs therefrom in that a conductive material 38 in contact with a base layer consists of a metal which is nonreactive to a semiconductor while a metal or silicide conductive material 39 on the surface side allows easy formation of an insulating layer free from pin holes and having a small permittivity by a fluoridization or oxidation treatment. Preferable examples of the material 38 nonreactive to a semiconductor are W and Ti. Preferable examples of the material 39 capable of forming a good insulating layer on the surface in accordance with the type of gas atmosphere are Ni, Cr, and Fe, or a silicide capable of forming a good insulating layer in an oxygen atmosphere. The base of the transistor of this embodiment has a very small thickness of about 10 nm (100 Å). Therefore, when a metal in contact with a base layer contacts a collector layer upon punchthrough in a semiconductor layer, a base-collector leakage current is increased. In addition, if pin holes or the like are present in an insulating layer on the surface of a base buried electrode, an emitter-base leakage current is increased. The arrangement of the third embodiment completely solves the above problems and realizes a highly reliable transistor. The second and third embodiments are related to producing the structure of a buried base electrode, but an arrangement of a combination of the second and third embodiments is also possible. An example of the possible arrangement is a method in which a conductive material in contact with the surface of a base layer has a low Schottky barrier height with respect to a base layer semiconductor while a conductive material on the surface side allows formation of a good insulating layer in a gas atmosphere. (4th Embodiment) The fourth embodiment of the present invention will be described below with reference to Fig. 7. Fig. 7 is a sectional view showing a bipolar transistor produced according to the fourth embodiment, in which the same reference numerals as in the first embodiment denote the same parts and a detailed description thereof will be omitted. The fourth embodiment differs from the first embodiment in that base electrode wiring is extracted from a position close to an emitter. As shown in Fig. 7, therefore, a region 40 where no insulating layer 14 is formed is present on a base buried electrode 8, and a base contact electrode 41 is in contact with the buried electrode 8 via the region 40. In the method of the fourth embodiment, the base buried electrode 8 and the base electrode electrode 41 contact each other not through an impurity diffusion layer (corresponding to 9 in Fig. 3) formed on the surface of a semiconductor substrate but directly. Therefore, an external base resistance can be further reduced to improve frequency characteristics. A method for producing the bipolar transistor according to the fourth embodiment will be described below with reference to Fig. 8. Since the method steps of the fourth embodiment are identical to those of the first embodiment till the step shown in Fig. 4(e) of the first embodiment, only the subsequent steps will be described. In Fig. 8, the same reference numerals as in the first embodiment denote the same parts and a detailed description thereof will be omitted. As shown in Fig. 8(f'), a base thin film 7 is formed and patterned, and the resultant wafer is conveyed into an atmospheric CVD apparatus to form an impurity-doped SiO 2 film. Note that P (phosphorus), B (boron), or a mixture thereof can be used as the impurity. Subsequently, a resist mask is used to perform patterning by RIE so that an inversely tapered shape 42 is obtained, as shown in Fig. 8(f'). The impurity-doped SiO 2 pattern is the same as in the first embodiment. The resist used in the SiO 2 patterning is removed in an H 2 SO 4 : H 2 O 2 = 4 : 1 solution, and the resultant structure is washed with water. Thereafter, a natural oxide film formed on the surface of a base thin film is removed by an etchant of HF : H 2 O = 1 : 100, and the resultant wafer is washed with water, subjected to N 2 blow-drying, and conveyed to the RF-DC coupled bias sputtering apparatus. As in the first embodiment, a base electrode 8 to be buried is formed, as shown in Fig. 8(g'). In this film formation, formation of the metal film of the electrode 8 on the side walls of the impurity-doped SiO 2 42 can be prevented by setting the voltage of bias sputtering on the wafer side at a predetermined value. For example, when a target bias is -200 V, RF power having a frequency of 100 MHz to be applied to the target side is 80 W and an Ar gas pressure is 0.399 Pa (3 mm Torr), the voltage on the wafer side may be set at -20 to 0 V. The conditions are not limited to the above conditions but the energy of ions to be incident on the wafer need only be equal to that in the above conditions. After formation of the base electrode wafer buried layer 8, the wafer is conveyed from the RF-DC coupled bias sputtering apparatus into the atmospheric CVD apparatus to form a non-impurity-doped SiO 2 film. Subsequently, as indicated by reference numeral 43 in Fig. 8(g'), the non-impurity-doped SiO 2 is left on only the base electrode buried layer 8 as a prospective base wiring electrode formation region. After the patterning, the resultant wafer is conveyed into an insulating layer formation treatment apparatus, and an insulating layer 44 is formed on the surface of the base electrode buried layer 8, as in the first embodiment. In this insulation layer formation, no insulating layer 44 is formed on the prospective base wiring electrode formation region since the non-impurity-doped SiO 2 43 is formed thereon. Subsequently, Cl 2 gas-added HF gas diluted by N 2 gas is supplied into the apparatus. The dilution amount is set to obtain selectivity by which the impurity-doped SiO 2 is etched but the non-doped SiO 2 is not etched. With this etching gas, only the impurity-doped SiO 2 can be removed, as shown in Fig. 8(h'). Since the wafer is set to face downward as described in the above embodiment, the metal on the surface side is simultaneously removed. After the above step, as in the first embodiment, light is radiated or Cl gas is supplied to remove F or the like remaining on the wafer surface, thereby cleaning the wafer surface. The resultant wafer is conveyed to the RF-DC coupled bias sputtering apparatus through a vacuum tunnel. Thereafter, as shown in Fig. 8(i'), a 10 nm (100 Å) thick n-type Si thin film 15 and an n + -type wide band gap material having a thickness of 200 nm (2000 Å) are formed. After the above emitter thin film formation, the emitter thin films 15 and 16 are patterned as shown in Fig. 8(h') as in the first embodiment, and an insulating interlayer 21 is formed by the atmospheric CVD apparatus. It is assumed that this insulating interlayer has RIE characteristics equal to or close to those of the non-doped SiO 2 43. After formation of the insulating interlayer 21, emitter, base, and collector contact holes are formed by RIE. In this case, since the non-doped SiO 2 43 having the etching characteristics similar to those of the insulating interlayer is formed on the buried base electrode, a shape as indicated by reference numeral 45 in Fig. 8(h') is obtained. After formation of the contact holes, a wiring metal film is formed and patterned, and a passivation film is formed, thereby completing the transistor. The method of the fourth embodiment can use the selective etching characteristic difference between the non-doped SiO 2 and the doped SiO 2 in the HF gas etching. (5th Embodiment) The fifth embodiment of the present invention will be described below with reference to Fig. 9. Fig. 9 is a sectional view showing a MOSFET produced using the present invention. Referring to Fig. 9, reference numeral 51 denotes a p + -type semiconductor buried layer for obtaining a substrate potential; 52, a p + -type semiconductor layer for channel stop of an n-type MOSFET; 53, a p-type well layer; 54, a field oxide film; 55 and 56, source and drain regions consisting of n + -type semiconductor layers, respectively; 57 and 58, conductive material layers consisting of a metal or a silicide formed on upper portions of the source and drain regions, respectively; 59, a gate oxide film; 60, an insulating layer formed on the surfaces of the conductive materials 57 and 58; 61, an insulating interlayer which is formed by a CVD apparatus and may consist of, e.g., BPSG (Boron-doped Phospho Silicate Glass), PSG (Phospho Silicate Glass), or NSG (Non-doped Silicate Glass); 62 and 63, wiring electrodes for the source and drain regions 55 and 56, respectively; and 64, a gate electrode. The characteristics of the MOSFET having the above structure are as follows. (1) Since the interface between the semiconductor layers, i.e., the source and drain regions 55 and 56 and the underlying semiconductor 53 and that between the gate oxide film 59 and the underlying semiconductor 53 are on the same plane, a short channel effect caused by micropatterning can be suppressed. (2) The metal or silicide conductive material portions 57 and 58 are formed on the upper portions of the source and drain-regions, respectively. Therefore, a source-drain parasitic resistance can be largely reduced to suppress a reduction in drain current caused by micropatterning or degradation in gm. (3) Although the gate electrode is formed at the end of the process, it can be micropatterned since the gate electrode formation step is a self-align step. (4) Since the gate electrode formation step is performed in the final stage of the process, a degree of freedom in selection of the gate electrode material is increased. For example, a metal gate can be formed. Although the fifth embodiment is described above by taking an n-channel MOSFET as an example, the present invention can be similarly applied to a p-channel MOSFET. A method for producing the MOSFET in accordance with the fifth embodiment of the present invention will be described below with reference to Fig. 10. Fig. 10(a) shows a stage in which a field oxide film 54 is formed by a LOCOS technique, the surface of Si on an active region is exposed and sufficiently cleaned by RCA washing, and a 5 nm (50 Å) thick oxide film 59 is formed by thermal oxidation. Subsequently, the resultant wafer is conveyed into an atmospheric CVD apparatus, and impurity-doped SiO 2 , 66 is formed and etched by RIE using a resist 67 as a mask to have an inversely tapered shape 66, as shown in Fig. 10(b). The etching is performed until an underlying Si layer (p-type well layer) 53 is exposed. Since the upper surface of an oxide film 59a is covered with the SiO 2 layer 66, this surface is not contaminated with an impurity derived from a resist residue. After the etching, the resist is removed by an H 2 SO 4 : H 2 O 2 = 4 : 1 solution, and the resultant structure is washed with water. Subsequently, a natural oxide film formed on the surface of the p-type well layer 53 is removed by dilute fluoric acid, and the wafer is washed with water and dried by N 2 blow. As shown in Fig. 10(c), the resultant wafer is conveyed into an RF-DC coupled bias sputtering apparatus to form 200 nm (200 Å) thick n + -type Si layers 55,56 and 100 nm (1000 Å) thick Al layers (metal or silicide conductive material layer) 57,58. The film formation conditions of the two layers are the same as those in the first embodiment and therefore a detailed description thereof will be omitted. As in the first embodiment, since the impurity-doped SiO 2 layer 66 has an inversely tapered shape and the surface migration of the Si layer 53 and the Al layers 57,58 on the substrate surface is low due to a low film formation temperature, no films are formed on the side walls of the SiO 2 layer 66. The resultant wafer is removed from the sputtering apparatus, and non-doped SiO 2 is formed on a portion of the Al layers 57,58 formed on the surfaces of the source and drain portions, as indicated by reference numeral 70 in Fig. 10(d). Thereafter, the resultant wafer is conveyed into an insulating layer formation treatment apparatus to form an insulating layer 60 on the surface of the Al layers 57,58. The formation of the insulating layer 60 may be performed by using, e.g., F 2 gas or O 2 gas as in the first embodiment. Subsequently, HF gas diluted by N 2 gas is supplied into the chamber. As in the other embodiments, since the wafer is set to face downward, the metal or the like on the doped SiO 2 falls In this case, a dilution amount is set to obtain selectivity by which the impurity-doped SiO 2 is etched and the non-impurity-doped SiO 2 is not etched. As shown in Fig. 10(e), the impurity-doped SiO 2 portion is removed by this etching gas. Subsequently, an insulating interlayer 61 is formed by the atmospheric CVD apparatus, contact holes are formed in the source, gate, and drain portions, and a wiring electrode is formed as shown in Fig. 10(f). Although the most standard LOCOS (Local Oxidation of Silicon) technique is used in element isolation in the fifth embodiment, another method such as drain element isolation or V-trench element isolation may be performed. In the fifth embodiment, the metal formed on the upper portions of the source and drain portions consists of only one type of metal. As in the second and third embodiments, however, a metal having a low Schottky barrier height with respect to the lower semiconductor or nonreactive to the lower semiconductor can be effectively used as the underlying metal, and a metal free from pin holes and capable of forming an insulating layer having a low permittivity by an F 2 or O 2 gas treatment can be effectively used as the metal on the surface side. (6th Embodiment) The sixth embodiment of the present invention will be described below with reference to Fig. 11. In Fig. 11, the same reference numerals as in the fifth embodiment denote the same parts and a detailed description thereof will be omitted. Referring to Fig. 11, reference numeral 72 denotes a semiconductor, a silicide, or a metal having a work function capable of obtaining a predetermined threshold value. As is apparent from Fig. 11, in the sixth embodiment, a gate electrode material consists of at least a plurality of materials so that a work function of a material in contact with a gate oxide film can be set at a value capable of obtaining a predetermined threshold value. (7th Embodiment) The seventh embodiment of the present invention will be described below with reference to Fig. 12. In Fig. 12, the same reference numerals as in the fifth embodiment denote the same parts and a detailed description thereof will be omitted. Referring to Fig. 12, reference numerals 73 and 74 denote p - -type semiconductor layers present immediately below n + -type semiconductor layers 55 and 56 for forming source and drain regions, respectively. In a micro MOSFET, if the gate length is decreased to be on the submicron order or less, a short channel effect is caused even in a structure in which source and drain regions and a gate oxide film are formed on the same plane. As a result, a punchthrough current is undesirably flowed through a source-to-drain path. In the method of this embodiment, therefore, in order to solve the above problem, the gate oxide film 59 is located closer to the substrate than the source and drain regions 55 and 56. This is already reported in "Shigeru Nishimatsu et al. Japanese of Applied Phisics Vol. 16 (1977) Supplement 16-1 pp. 179-183". In the Nishimatsu et al. article, however, polycrystalline Si is formed on an n + -type layer for forming source and drain regions, and a gate portion is formed by etching an Si substrate to have a trench shape. Therefore, in the Nishimatsu et al. article, a parasitic resistance in the source and drain regions is high, and the depth of the trench must be controlled by etching, resulting in unsatisfactory manufacturing precision. In contrast to this, in the method of this embodiment, the method or silicide conductive material is formed immediately above the source and drain regions 55 and 56 to decrease the parasitic resistance, and the trench depth of the gate portion can be controlled by the thickness of the p - -type layer immediately below the source and drain regions. As described in the above embodiments, since this film formation is performed by an apparatus capable of performing control at the level of a monoatomic layer such as the RF-DC coupled bias sputtering apparatus, the depth of the trench can be controlled at a high precision. With this method, therefore, a micro MOSFET on the submicron order or less is produced. (8th Embodiment) The eighth embodiment of the present invention will be described below with reference to Fig. 13. The eighth embodiment relates to an application to a wiring step and, more particularly, to a method capable of producing wiring patterning in a vacuum chamber without using a resist step. Fig. 13 is a sectional view showing wiring produced by the method of the present invention. Referring to Fig. 13, reference numeral 81 denotes a p + -type buried layer or p-type semiconductor substrate; 82, an element isolation p + -type semiconductor layer; 83, a p-type well layer; 84, a field oxide film; 85, a semiconductor diffusion layer for obtaining a contact with wiring and consisting of an n + -type semiconductor layer in this embodiment; 86, an insulating interlayer; 87, a wiring metal; 88, an insulating layer formed on the surface of a wiring metal; and 89, a passivation film such as, preferably, an Si 3 N 4 film. This method is such that no wiring metal remains between the insulating interlayer 86 and the passivation film 89 except for a wiring portion because no wiring metal adheres on regions except for the wiring formation portion. Therefore, no leakage current flowing through the wiring metal is present in this embodiment of the present invention. Second, no resist residue caused by wiring metal patterning is present because no resist is used after film formation of the wiring metal as is the case with the first reason. Third, since the insulating layer is formed on the surface of the wiring metal before the wafer is removed from a chamber (for film formation of a wiring metal), the wiring is not changed but stable in quality. The method of the eighth embodiment of the present invention will be described below with reference to Fig. 14. In Fig. 14, the same reference numerals as in Fig. 13 denote the same parts and a detailed description thereof will be omitted. Fig. 14(a) is a sectional view showing a device in a stage in which an insulating interlayer 86 is formed and an impurity-doped SiO 2 layer 90 is subsequently formed. In this arrangement, when the insulating interlayer 86 and the SiO 2 layer 90 are subjected to etching using HF gas, only the SiO 2 layer 90 must be etched. Therefore, it is more preferable to form the insulating interlayer 86 by non-doped SiO 2 and perform a heat treatment to obtain dense SiO 2 after film formation of the insulating interlayer 86. Subsequently, a resist pattern having a wiring shape is used to etch only the impurity-doped SiO 2 layer 90 first using HF gas (diluted by N 2 gas). At this time, the shape of the SiO 2 layer 90 in which a contact portion is doped is as indicated by reference numeral 91 in Fig. 14 b1), and the shape of the SiO 2 layer 90 in which a wiring portion is doped is as indicated by reference numeral 91 in Fig. 14 b2). After the above selective etching, the wiring resist pattern is removed, and a resist pattern having a contact hole shape is patterned. The shapes of the resist pattern at the contact portion and the wiring portion are indicated by reference numerals 92 in Figs. 14 b1) and 14 b2), respectively. The wiring region is covered with the resist as shown Fig. 14 b2), and the contact hole region has an opening portion in the contact hole portion, as shown in Fig. 14 b1). Etching of the insulating interlayer 86 is performed by RIE, and the resist 92 is removed using an H 2 SO 4 : H 2 O 2 = 4 : 1 solution. The resultant wafer is washed with water, and a natural oxide film formed on the surface of the diffusion layer 85 is removed by dilute fluoric acid. The resultant wafer is washed with water, dried by N 2 blow, and conveyed into an RF-DC coupled bias sputtering apparatus to form an Al film 87 under the same conditions as described in the above embodiments. After the film formation, an insulating layer 88 is formed on the Al surface by an F 2 or O 2 treatment (Figs. 14 c1) and 14 c2)). Subsequently, the HF gas etching is performed again to completely remove the impurity-doped SiO 2 layer 90, thereby finishing the patterning of the wiring. In the eighth embodiment, the wiring metal consists of only one type of material. As in the above embodiments, however, the wiring metal may consist of two or more types of materials such that a metal having a low Schottky barrier height is used as a metal in contact with the semiconductor diffusion layer and a metal capable of forming a good insulating layer is used as a metal on the prospective insulating layer formation side. Industrial Applicability As has been described above, the method of the present invention can be widely applied to various steps in a semiconductor process to provide the following effects. (1) Since film formation of, e.g., a semiconductor and a metal and formation and patterning of an insulating film can all be performed in a vacuum chamber, no natural oxide film is formed on a junction portion, and a semiconductor device which positively uses an interface can be realized with high reliability. (2) Since a semiconductor region to be used is not exposed to a dry etching atmosphere, no damage is caused in the surface and the interior of the semiconductor. (3) A self-alignment process enables micropatterning and decreases the number of masks, thereby realizing a very economical device. (4) In a bipolar transistor, an external base resistance is minimized, and wiring in a base electrode portion need not be formed in a peripheral portion of an emitter, thereby achieving a high operation speed and a very high degree of integration. (5) In a MOSFET, a parasitic resistance and a parasitic capacitance are minimized to suppress a reduction in drain current or degradation in gm caused by a short channel. In addition, punchthrough caused by the short channel can also be prevented. (6) Since neither the problem of shallowness of a wiring metal nor that of a resist residue is posed, an insulating layer can be formed on the surface of the wiring metal after the wiring step, thereby improving the reliability of the wiring.

Claims: A method for producing a semiconductor device, comprising the successive steps of: step 1: providing an insulating film (31; 42; 66; 90) over a doped semiconductor layer (7; 53, 55, 56; 85) of a wafer, said insulating film having side surfaces; step 2: providing a conductive material (8; 36, 37; 38, 39; 57, 58; 87) of metal or silicide on a portion of said doped semiconductor layer (7; 55, 56; 85) not covered by said insulating film (31; 42; 66; 90) such that the side surfaces of the insulating film are not covered by the conductive material, said conductive material being such that an insulating compound can be formed on the conductive material by surface reaction with a gas, and said insulating film consisting of a material which can be selectively dry-etched with respect to said insulating compound; step 3: forming an insulating compound film (14; 44; 60; 71; 88 ) of a material different from that of said insulating film (31; 42; 66; 90) on said conductive material by subjecting said conductive material (8; 36, 37; 38, 39; 57, 58; 87) to a surface processing by surface reaction with gas; step 4: removing said insulating film (31; 42; 66; 90) by selective dry-etching with respect to said insulating compound; and step 5: forming, on a portion of said doped semiconductor layer (7; 53; 55; 56; 85) from which said insulating film (31; 42; 66; 90) is removed, a semiconductor layer, a conductive layer, or an insulating layer. A method according to claim 1, wherein step 1 contains the successive steps of: forming an insulating interlayer (86) on said doped semiconductor layer (85) and the surrounding regions (84); forming the insulating film as an impurity-doped SiO 2 film (90) formed on said insulating interlayer (86); forming a first resist pattern on said insulating film for a wiring; etching the insulating film (90) using said first resist pattern as a mask so as to form an opening in which the insulating interlayer (86) is exposed; and step 2 comprises the successive steps of: forming a second resist pattern (92) on the exposed insulating interlayer (86) and the insulating film (90) for contact holes; dry etching said insulating interlayer (86) using said second resist pattern (92) as a mask so as to expose the doped semiconductor layer (85) within the opening of the insulating film (90); forming the conductive material as a film of conductive material (87) formed on the exposed doped semiconductor layer (85) for constituting a wiring member. A method according to claim 1, wherein step 1 comprises the successive steps of: forming the insulating film as an impurity-doped SiO 2 film (42) formed on said doped semiconductor layer (7) and the surrounding regions; forming a resist pattern on said insulating film for a wiring; and etching the insulating film (42) using said resist pattern as a mask so as to form an opening in which the doped semiconductor layer (7) is exposed; after step 2 is provided a step 2' of forming an undoped SiO 2 layer (43) on a portion of said conductive material (8); and in step 5 an emitter thin film (15, 16) for a bipolar transistor is formed. A method according to claim 1, wherein step 1 comprises the successive steps of: forming the insulating film as an SiO 2 film (31) formed on said doped semiconductor layer (7) and the surrounding regions; forming a resist pattern on said insulating film for a wiring; and etching the insulating film (31) using said resist pattern as a mask so as to form an opening in which the doped semiconductor layer (7) is exposed; and in step 5 an emitter thin film (15, 16) for a bipolar transistor is formed. A method according to claim 1, wherein step 1 comprises the successive steps of: forming the insulating film as an impurity-doped SiO 2 film (66) formed on a gate oxide film (59a) forming a resist pattern (67) on said insulating film for a wiring; and etching said insulating film (66) using said resist pattern (67) as a mask so as to form an opening in which a portion (53) of the doped semiconductor layer (53, 55, 56) is exposed; after step 1 is provided a step 1' of forming a source and drain semiconductor layer (55, 56) on the exposed portion (53) of the doped semiconductor layer (53, 55, 56); after step 2 is provided a step 2' of forming an undoped SiO 2 layer (70) on a portion of said conductive material (57, 58); after step 4 is provided a step 4' of forming an insulating interlayer (61) and contact holes; and in step 5 source, gate and drain electrodes (62, 64, 63) for a MOSFET are formed. A method according to any one of the preceding claims, wherein a shape of said insulating film (31; 42; 66; 90) is an inversely tapered shape. A method according to any one of the preceding claims, wherein said insulating film (31; 42; 66; 90) is an SiO 2 film formed by a chemical vapor deposition method. A method according to any one of the preceding claims, wherein said step of forming said conductive material (8; 57, 58; 87) is performed under conditions in which a degree of migration of said conductive material (8; 36; 37; 38, 39; 57, 58; 87) on said side surfaces of the insulating film (31; 42; 66; 90) is reduced. A method according to any one of the preceeding claims, wherein said insulating compound film (14; 44; 60; 71; 88) is formed by surface reaction with fluorine gas. A method according to any one of claims 1 to 8, wherein said insulating compound film (14; 44; 60; 71; 88) is formed by surface reaction with oxygen gas. A method according to any one of the preceding claims, wherein said step of removing said insulating film (31; 42; 66; 90) is performed by HF gas diluted by N 2 gas. A method according to claim 11, wherein Cl 2 gas is mixed in the HF gas diluted by the N 2 gas. A method according to any one of the preceding claims, wherein said step of removing said insulating film (31; 42; 66; 90) is performed while the wafer is set so that the insulating film (31; 42; 66; 90) faces downward.

Inventors: MIYAWAKI MAMORU, OHMI TADAHIRO, MIYAWAKI, MAMORU, OHMI, TADAHIRO
Applicants: CANON KK, OHMI TADAHIRO, CANON KABUSHIKI KAISHA, OHMI, TADAHIRO
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, H01L21