Semi-custom integrated circuit device

Abstract: A semi-custom integrated circuit comprises a basic cell array comprising a plurality of basic cells aligned in a first direction, the basic cells comprising a transistor unit (1), a capacitor unit (3) and a resistor unit (2) arranged in a second direction perpendicular to the first direction. The transistor unit (1) is positioned between the capacitor unit (3) and the resistor unit (2). The transistor unit (1) has a terminal portion (21, 29) for connection of wiring, the capacitor unit (3) having a terminal portion (32) for connection of wiring, the resistor unit (1) having a terminal portion (12, 14) for connection of wiring. The terminal portions (12, 14, 21, 29, 32) of said transistor unit, capacitor unit and resistor unit are aligned along a line. Such an integrated circuit can be more readily designed and wired using computer-aided techniques.

Description: The present invention relates to a semi-custom integrated circuit apparatus capable of discretionally forming a gate array of a digital circuit (logic circuit), a gate array of an analog circuit, or a gate array on which a digital circuit and an analog circuit are mixed. Description of the Related Art In the present art, a gate array on which a logic circuit is provided forms the main current. Furthermore, in a recently developed device, a gate array on which an analog circuit is provided has both a digital circuit and an analog circuit formed on the gate array. Generally, it is necessary in an analog circuit to provide a resistor or a capacitor in addition to a transistor. The number of prior-art devices having the gate array in which a digital circuit and an analog circuit are mixed is very small. However, an example of this type of device is the invention disclosed in Japanese Patent Disclosure sho 59-1083228, which has a capacitor formed in a wire layer of the cell array. Figure 1 represents a plan view of a main part of a cell array in a semi-custom IC disclosed in this Japanese Patent Disclosure. In Figure 1, TR represents a transistor region, WR a wiring region, WP a wiring poly-silicon film and CE a capacitor poly-silicon film. One electrode of the capacitor is formed of the capacitor poly-silicon film CE of the other electrode of the capacitor is formed of an impurity diffusion region with a bulk form. A resistor can be formed by deriving two electrodes from the impurity diffusion region. In a semi-custom integrated circuit, respective cells must have a rectangular shape to enable the arrangement and wiring to be designed by a computer. Respective regions with a bulk form are fixed. Only the wiring is changed to enable the device to be provided with different functions. As described above, where a digital circuit is mixed with an analog circuit, the above condition which includes provision of a resistor and capacitor, which are essential for the construction of an analog circuit, should be maintained. For this purpose, it is important to provide a layout which includes a resistor and a capacitor. Needless to say, the prior art invention disclosed in the above patent disclosure is limited to the idea in which a digital circuit and an analog circuit are merely mixed. Therefore, in this prior art, the arrangement of the resistor and capacitor is not regular. Thus, it requires an unnecessarily large space, thereby drastically decreasing the number of cells with an analog function which can be provided in the cell. In particular, this prior art does not clearly specify the wiring and thus does not solve the wiring problem. Thus, as can be seen from the above, the prior art has serious problems which may make it impossible to realize a gate array on which a digital circuit and analog circuit can be mixedly mounted. JP-A-60 18932 by Suwa Seikosha K.K. discloses a gate array device in accordance with the preamble of each independent claim. In this device, two "cells" are separated by a single resistance element and a single capacitance element. According to a first aspect of the present invention, there is provided a semi-custom integrated circuit comprising an array of circuit elements arranged in a line, said elements comprising transistor units, capacitor units and resistor units, said transistor unit having a gate electrode, and each of said transistor unit, capacitor unit and resistor unit having one or more respective terminal portions for connection of wiring; wherein said transistor unit comprises a source region and a drain region arranged in said first direction, said gate electrode provided between said source region and drain region and extending in a second direction which is perpendicular to said first direction and said gate electrode having terminal portions in a terminal region; characterised in that:- said array is a basic cell array consisting of a plurality of basic cells aligned in a first direction, each basic cell having a said capacitor unit, a said resistor unit, and a said transistor unit positioned between the capacitor unit and resistor unit; wherein said terminal portions of said transistor unit, capacitor unit and said resistor unit are aligned along a straight line in said second direction. According to a second aspect of the present invention, there is provided a semi-custom integrated circuit comprising an array of circuit elements arranged in a line, said elements comprising transistor units, capacitor units and resistor units, wherein: said array is a basic cell array consisting of a plurality of first basic cells and a plurality of second basic cells aligned in a first direction, each first basic cell comprising a first resistor unit, a second resistor unit and a transistor unit positioned between said first resistor unit and said second resistor unit; wherein said transistor unit comprises a source region and a drain region arranged in said first direction, a gate electrode provided between said source region and drain region and extending in a second direction which is perpendicular to said first direction; each of said transistor unit, first resistor unit and second resistor unit having one or more respective terminal portions for connection of wiring; wherein said terminal portions of said transistor unit, first resistor unit and second resistor unit are aligned along a straight line in said second direction, and each second basic cell comprising a first capacitor unit, a second capacitor unit and a further transistor unit positioned between said first capacitor unit and said second capacitor unit; wherein said further transistor unit comprises a source region and a drain region arranged in said first direction, a gate electrode provided between said source region and drain region and extending in said second direction; each of said further transistor unit, first capacitor unit and second capacitor unit having one or more terminal portions for connection of wiring; wherein said terminal portions of said further transistor unit, first capacitor unit and second capacitor unit are aligned along a straight line in said second direction. Reference is made, by way of example, to the accompanying drawings in which: Figure 1 shows a plan view of the main part of a cell array in a semi-custom IC disclosed in the prior art, Figures 2A and 2B, respectively show a plan view of the main part of a basic cell for explaining the principle of the present invention and an equivalent circuit thereof, Figure 3 shows a plan view of the main part of an array for explaining one embodiment of an arrangement of a resistor unit and a capacitor unit and that of a basic cell, Figure 4 shows a plan view of the main part of an array for explaining another embodiment of an arrangement of a resistor unit and a capacitor unit and that of a basic cell, Figure 5 shows a plan view of the main part of an array for explaining a further embodiment of an arrangement of a resistor unit and a capacitor unit and that of a basic cell, Figure 6 shows a plan view of the main part of an array for explaining a still further embodiment of the arrangement of a resistor unit and a capacitor unit and that of a basic cell, Figure 7 shows a plan view of the main part of an array for explaining other embodiment of an arrangement of a resistor unit and a capacitor unit and that of a basic cell, Figure 8 shows a plan view of the main part of an array for explaining an embodiment in which the width of a transistor unit is different from that of the resistor unit or the capacitor unit, Figure 9 shows a plan view of the main part of an array for explaining another embodiment in which the width of the transistor unit is different from that of the resistor unit or capacitor unit, Figures 10A and 10B, respectively, show a plan view of the main part of the basic cell for explaining the embodiment of the present invention and an equivalent circuit thereof, Figure 11 is a sectional view of the main part of the embodiment along the line Y1-Y1 shown in Figure 10A, Figure 12 shows a sectional side view of the main part of the embodiment along the line X-X shown in Figure 10A, Figure 13 is a sectional view of the main part of the embodiment along the line Y2-Y2 shown in Figure 10A, Figure 14 shows a sectional view of the main part of the embodiment along the line Y3-Y3 shown in Figure 10A, Figures 15 shows a plan view of the main part of the embodiment for explaining a pattern layout of an operational amplifier to which the present invention is applied, Figure 16 shows an equivalent circuit of the operational amplifier shown in Figure 15 as the pattern layout and, Figure 17 shows a plan view of the main part of the whole bulk for explaining the gate array according to the present invention. Preferred Embodiment of the Present Invention Figures 2A and 2B, respectively, show a plan view of a main part of a basic cell for explaining the principle of the present invention and equivalent circuit thereof. In the drawing, 1 is a transistor unit, 1p a p-channel transistor portion, 1n an n-channel transistor portion, 2 a resistor unit, 3 a capacitor unit, ST the width of the transistor unit 1, SR the width of the resistor unit 2, and SC the width of the capacitor unit 3. As described above, in the present invention, transistor unit 1, resistor unit 2, and capacitor unit 3 are combined to form a single basic cell and the basic cell is arranged as an array. The basic cell shown in Figure 2A provides resistor unit 2 on the left side of transistor unit 1 and capacitor unit 3 on the right side thereof. The structure of the basic cell can be modified in various ways and the arrangement of the basic cell can be selected appropriately as necessary. The number of transistors may be one or more than one. Figures 3 to 7 represent explanatory plan views of the main part of an array for explaining the arrangement of the resistor 2 and the capacitor unit 3 and an array of the basic cell. The same reference numbers as used in Figure 2A represent the same portions or the same meanings. Figure 3 represents an array in which the basic cell shown in Figure 2A is sequentially arranged. Figure 4 represents an array of a basic cell in which the positions of the capacitor unit 3 and resistor unit 2 are exchanged with those of the resistor unit 2 and capacitor unit 3 of the basic cell shown in Figure 3, such array of the basic cell being provided in one column. The array of the basic cell shown in Figure 3 is provided in the adjacent column. Figure 5 represents an array in which the basic cell shown in Figure 3 and the basic cell shown in Figure 4 are provided in turn. Figure 6 shows an array in which a basic cell having resistor units 2 provided on both sides of the transistor unit 1 and a basic cell having capacitor units 3 provided on both sides of the transistor unit 1 are arranged in turn and the basic cell array on the left side is shifted from the basic cell array on the right side by one basic cell. Figure 7 represents an array in which the basic cell array on the left side becomes the same basic cell array on the right side in the array relationship shown in Figure 6. In the basic cell shown in Figures 2 to 7, the width ST of the transistor unit 1 is equal to the width SR of resistor unit 2 and the width SC of capacitor unit 3, but the widths ST, SR and SC can be properly selected within a scope facilitating a computer aided design. Figures 8 and 9 are an explanatory main part plan views relating to an array for explaining a case in which the width SR of resistor unit 2 and the width SC of capacitor unit 3 are not equal to the width ST of transistor unit 1. The reference numbers shown in Figures 8 and 9, which are the same as those shown in Figures 3 to 7, represent the same part or the same meaning. In Figure 8, the width SR of the resistor unit 2 and the width SC of the capacitor unit 3 are a positive natural number times the width ST the of transistor unit 1. Figure 9 represents an array in which the width SR of resistor unit 2 and the width SC of capacitor unit 3 are a positive natural number times half the width ST of the transistor unit 1. Where the gate array is of a channel type, the basic cell forms the transistor unit 1 in the transistor area TR and forms the resistor unit 2 and capacitor unit 3 so that they are buried in the wiring region WR. If the gate array is of a channelless type (i.e. a sea of gate: SOG), the basic cell is provided over the entire area. As is clear from the above description, in the semi-custom integrated circuit device according to a first embodiment of the present invention as viewed in the plan direction, a resistor unit (for example, the resistor unit 2) or capacitor unit (for example, the capacitor unit 3) is provided on both sides of a transistor unit (for example, the transistor unit 1). The vertical width of these units is either the same as the vertical width (for example, the width ST) of the transistor unit, a positive natural number times the vertical width of the transistor unit or positive natural number times half the vertical width of the transistor unit. This assembly forms a basic cell. In addition, a transistor unit may be provided in the transistor region and the resistor or capacitor units may be provided in the wiring region provided beside the transistor region. By this means, a semi-custom integrated circuit apparatus on which a digital circuit and an analog circuit can be independently or mixedly mounted is realized and the wire for completing an integrated circuit device which can be provided to a user can be dealt with by using the conventional technology. Figures 10A and 10B, respectively, represent a plan view and an equivalent circuit view of a main part of a basic cell for explaining an embodiment of the present invention and the same references used in Figures 2 to 9 represent the same parts or meanings. The present embodiment is basically the same as the basic cell explained by referring to Figure 2. Needless to say, the symbols in Figure 10A correspond to the symbols shown in Figure 10B. In Figures 10A and 10B, 11 to 32 indicate terminals, R1 and R2 resistors, QP1 and QP2 p-channel and QN2 n-channel transistors, QP3 and QP4 q-channel transistors, QN3 and QN4 n-channel transistors, C1 a capacitor, CP a contact pattern for connection to a p-type substrate and CN a contact pattern for connection to an n-type substrate. Respective transistors in Figures 10A and 10B are represented by their gates and symbols are given to their gates. An impurity diffused region R1 of the resistor unit 2 is to form a resistor R1. The regions 11 and 13 are to form terminals 11 and 13 of the resistor R1. Regions 16 and 21 are to form gate terminals 16 and 21 of the transistors QP1 and QP2. Regions 15 and 20 are to form source terminals 15 and 20. Region 18 is to form drain electrode 18. Regions 31 and 32 are to form terminals 31 and 32 of capacitor C1. The regions for terminals 11,13, 16 and 24 are aligned with each other. The regions for terminals 12,14, 21, 29 and 32 are aligned with each other. Therefore terminals of the resistor unit 2, transistor unit 1 and capacitor unit 3 are aligned with each other in a horizontal direction, for example, analog a line of a grid (not shown). Contact patterns CN and CP are also aligned in a horizontal direction. Some of the terminals or contact patterns may be aligned in a vertical direction. Therefore, the embodiment shown in Figure 10A facilitates computer aided design and wiring. Figure 11 is a sectional view of a main part along the line Y1-Y1 shown in Figure 10A and the same reference numbers as in Figures 2 and 10A represent the same parts as in Figures 2 to 10A. In Figure 11, 41 indicates an n type semiconductor substrate, 42 a field insulating film comprising a silicon dioxide (Sio₂), 43A and 43B are p-type resistor regions and 44 an insulating film formed simultaneously with a gate insulating film. Figure 12 is a sectional view of the main part along the line x-x shown in Figure 10A and the same references as used in Figure 2 to 11 represent the same parts or the same meanings. In Figure 12, 45 indicates a p⁺-type electrode contact region, 46 a phosphosilicate glass(PSG) film and 47 an electrode. Figure 13 is a sectional view of the main part along the line Y2-Y2 shown in Figure 10A. The same reference numbers as used Figures 2 to 12 represent the same parts or the same meanings. In Figure 13, 48 indicates a polisilicon gate electrode of transistor QP1, 49 a polisilicon gate electrode of transistor QP2, 50 a p-type source region of transistor QP1 and QP2, 51 a p-type drain region of transistors Q1, 52 a p-type drain region of transistor AP2, and 53 a between-layer insulating film comprising Sio₂. Figure 14 is a sectional view of the main part along the line Y-3 shown in Figure 10A. The same reference numbers as in Figures 2 to 13 represent the same parts or the same meanings. In Figure 14, 54 indicates a p-type region, 55 a capacitor electrode of polysilicon, 56 a capacitor dielectric film comprising Sio₂, 57 a capacitor electrode of a polysilicon and 58 an insulating film. As described above, when a capacitor is formed of a 2-layer configuration comprising polysilicon films, the accuracy of the capacitance is higher than that of a capacitor formed by bulk polysilicon and a single-layer polysilicon film. Where a high-precision capacitor or resistor is obtained, it becomes possible to form a D/A converter of the R-string type or an A/D converter of the sequential comparison type by using the cell of the present invention. Therefore, an integrated circuit unit device can be completed within a short period in the same manner as an ordinary gate array. Figures 15 and 16 represent a plan view of the main part for explaining the pattern layout of an operational amplifier formed by and the equivalent circuit diagram the basic cell of the present invention. The reference numbers as used in Figures 1 to 13 represent the same parts or the same meanings. In Figures 14 and 15, V DD represents a positive power source level, Vss a ground side power source level, IM a -difference input, IP a +difference input, VR a bias input and OT an output. The wire represented by a solid line is made of metal wire and it is in the first layer Aℓ. The wire represented by a dashed line is also made of metal and is in the second layer Aℓ. The x mark indicates the contact portion between the first-layer metal wire and the bulk, and the O mark designates the contact point between the first-layer metal wire and the second-layer metal wire. As is clear from the drawings, the basic cell in this embodiment is the same as that, used for the explanation in Figures 2 to 4. Transistor unit 1, resistor unit 2 and capacitor unit 3 can be wired by computer-aided automatic design. Figure 17 is an explanatory plan view of the main part representing the whole bulk for explaining a gate array embodying the present invention. The same reference numbers used in Figures 2 to 16 represent the same portions or the same meanings. In Figure 17, BR represents an input and output buffer and BP an input and output bonding pad. In Figure 17, when the gate array is used only for a logic circuit, resistor unit 2 and capacitor unit 3 in the basic cell need not be used. Further more, if the gate array is used only for an analog circuit, the whole basic cell can be used. If they are selectively embodied, a gate array in which a logic circuit and an analog circuit are mixed can be realized. When the gate array is formed only by the logic circuit, it does not cause any problem even if a metal wire passes over resistor unit 2 or capacitor unit 3. The basic cell of the present invention can also form A/D or D/A converter, analog switch, and comparator, for example. The basic cell of the present invention may be used for a full-custom integrated circuit device and a regular standard integrated circuit device. Digital and the analog circuits can be independently or mixedly mounted, thereby providing semiconductor integration. The wiring required to complete an integrated circuit device to be provided to a user, can be dealt with by automatic computer aided design using the conventional technology.

Claims: A semi-custom integrated circuit comprising an array of circuit elements arranged in a line, said elements comprising transistor units, capacitor units and resistor units, said transistor unit having a gate electrode, and each of said transistor unit, capacitor unit and resistor unit having one or more respective terminal portions for connection of wiring; characterised in that:- said array is a basic cell array consisting of a plurality of basic cells aligned in a first direction, each basic cell having a said capacitor unit, a said resistor unit, and a said transistor unit positioned between the capacitor unit and resistor unit; wherein said transistor unit comprises: a source region and a drain region arranged in said first direction, said gate electrode provided between said source region and drain region and extending in a second direction which is perpendicular to said first direction, and said gate electrode having terminal portions in a terminal region; wherein said terminal portions of said transistor unit, capacitor unit and said resistor unit are aligned along a straight line in said second direction. The semi-custom integrated circuit according to claim 1, wherein a plurality of said cell arrays are arranged in said second direction crossing a wiring region. The semi-custom integrated circuit according to claim 1, wherein an unused region of said capacitor unit or transistor unit is used for the arrangement of interconnection wiring between said basic cells. The semi-custom integrated circuit according to claim 1, wherein said resistor unit comprises a polysilicon layer formed on an insulating film covering a semiconductor substrate and extending in said second direction and having a terminal portion, and said capacitor unit comprises a first electrode formed on the insulating film for covering said semiconductor substrate, an insulating film for covering a first electrode and a second electrode formed on said insulating film, said first and second electrodes having respective terminal portions. The semi-custom integrated circuit according to claim 1, wherein said transistor unit comprises a p-channel MIS-transistor pair and an n-channel MIS transistor pair arranged in said second direction, said p-channel MIS transistor pair comprises a first p-type region, a second p-type region, and a third p-type region, which are arranged in said first direction, a first gate electrode arranged between said first p-type region and said second p-type region and extending in said second direction and a second gate electrode arranged between said second p-type region and said third p-type region and extending in said second direction, said n-channel MIS transistor pair comprises a first n-type region, a second n-type region, and a third n-type region, which are arranged in said first direction, a third gate electrode arranged between said first n-type region and said second n-type region and extending in said second direction, and a fourth gate electrode arranged in said second n-type region and said third n-type region and extending in said second direction, said resistor unit comprises a first resistor element and a second resistor element arranged in said first direction and extending in said second direction, said capacitor unit has a first capacitor electrode and a second capacitor electrode, terminal portions of the first and the third gate electrodes, said first p-type region, said first n-type region, said first resistor element, and said first capacitor electrode are aligned along a line in said second direction, and terminal portions of the second and fourth gate electrodes, said third p-type region, said third n-type region, said second resistor element, and said second capacitor electrode are aligned with each other, and the terminal portions of said second p-type region and said second n-type region are aligned along a line in said second direction. The semi-custom integrated circuit according to claim 5, wherein said first and third gate electrodes are formed of an integrated electrode and said second and fourth electrodes are formed of another integrated electrode. The semi-custom integrated circuit according to claim 1, wherein said transistor unit comprises first and second p-channel MIS transistor pairs and first and second n-channel MIS transistor pairs arranged in said second direction, said first and second p-channel MIS transistor pairs each comprise a first p-type region, a second p-type region and a third p-type region arranged in said first direction, a first gate electrode arranged between said first p-type region and said second p-type region and extending in said second direction, and a second gate electrode arranged between said second p-type region and said third p-type region and extending in said second direction, said first and second n-channel MIS transistor pair each has a first n-type region, a second n-type region and a third n-type region arranged in said first direction, a third gate electrode arranged between said first n-type region and said second n-type region and extending in said second direction, and a fourth gate electrode arranged between said second n-type region and said third n-type region and extending in said second direction, said resistor unit has a first resistor element and a second resistor element arranged in said first direction and extending in said second direction, said capacitor unit comprises a first capacitor electrode and a second capacitor electrode, terminal portions of said first and third gate electrodes, said first p-type region, and said first n-type region, said first resistor element and said first capacitor electrode of said first and second p-channel MIS transistor pair, and said first and second n-channel MIS transistor pair and said first resistor element and said first capacitor electrode are aligned along a straight line, terminal portions of said second and fourth gate electrodes, said third p-type region, and said third n-type region, said second resistor element and said second capacitor electrode of said first and second p-channel MIS transistor pair and said first and second n-channel MIS transistor pair and said second resistor element and said second capacitor electrode are aligned along a straight line, and terminal portions of said second p-type region and said second n-type regions of said first and second p-channel MIS transistor pair and said first and second n-channel MIS transistor pair are aligned along a straight line in said second direction. The semi-custom integrated circuit according to claim 7, wherein said first and second p-channel MIS transistor pair or said first and second n-channel MIS transistor pair are arranged adjacent to each other. The semi-custom integrated circuit according to any preceding claim, wherein a plurality of said transistor units forms a digital circuit through an interconnection and a plurality of resistor units and capacitor units forms an analog circuit through an internal connection. The semi-custom integrated circuit according to any preceding claim, wherein said resistor and capacitor units have the same maximum dimension in said first direction as a maximum dimension in said first direction of the transistor unit. The semi-custom integrated circuit according to claim 10, wherein the resistor unit is provided on the left side of the transistor unit, and the capacitor unit is provided on the right side of the transistor unit. The semi-custom integrated circuit according to claim 10, wherein said basic cells are arranged in columns extending along said first direction, corresponding basic cells in adjacent columns being aligned in said second direction. The semi-custom integrated circuit according to claim 10, wherein the resistor unit is provided on the right side of the transistor unit, and the capacitor unit is provided on the left side of the transistor unit. The semi-custom integrated circuit according to claim 10, wherein said basic cell array is made up of first basic cells and second basic cells, each first basic cell comprising a said transistor unit, a said resistor unit provided on the left side of the transistor unit, and a said capacitor unit provided on the right side of the transistor unit, and each second basic cell comprising a said transistor unit, a said resistor unit provided on the right side of the transistor unit, and a said capacitor unit provided on the left side of the transistor unit. The semi-custom integrated circuit according to claim 14, wherein the basic cell array has columns of basic cells wherein the cells are aligned in said first direction, including a column of first basic cells and an adjacent column of second basic cells. The semi-custom integrated circuit according to claim 14, wherein the basic cell array comprises a column made up of first and second basic cells arranged in turn along said first direction. A semi-custom integrated circuit comprising an array of circuit elements arranged in a line, said elements comprising transistor units, capacitor units and resistor units, wherein: said array is a basic cell array consisting of a plurality of first basic cells and a plurality of second basic cells aligned in a first direction, each first basic cell comprising a first resistor unit, a second resistor unit and a transistor unit positioned between said first resistor unit and said second resistor unit; wherein said transistor unit comprises a source region and a drain region arranged in said first direction, a gate electrode provided between said source region and drain region and extending in a second direction which is perpendicular to said first direction; each of said transistor unit, first resistor unit and second resistor unit having one or more respective terminal portions for connection of wiring; wherein said terminal portions of said transistor unit, first resistor unit and second resistor unit are aligned along a straight line in said second direction, and each second basic cell comprising a first capacitor unit, a second capacitor unit and a further transistor unit positioned between said first capacitor unit and said second capacitor unit; wherein said further transistor unit comprises a source region and a drain region arranged in said first direction, a gate electrode provided between said source region and drain region and extending in said second direction; each of said further transistor unit, first capacitor unit and second capacitor unit having one or more respective terminal portions for connection of wiring; wherein said terminal portions of said further transistor unit, first capacitor unit and second capacitor unit are aligned along a straight line in said second direction. The semi-custom integrated circuit according to claim 17, wherein said first resistor, second resistor, first capacitor and second capacitor units have the same maximum dimension in said first direction as a maximum dimension in said first direction of said transistor unit. The semi-custom integrated circuit according to claim 18, wherein the basic cell array comprises columns of basic cells, wherein said first and second basic cells are arranged by turns along said first direction, adjacent columns having different arrangements such that corresponding cells in adjacent columns are of different types. The semi-custom integrated circuit according to claim 18, wherein the basic cell array comprises columns made up of first and second basic cells arranged along said first direction, adjacent columns having the same arrangements such that corresponding cells in adjacent columns are of the same type. The semi-custom integrated circuit according to any of claims 10 to 20, wherein an array of said basic cells is connected to form an operational amplifier. The semi-custom integrated circuit according to any of claims 1 to 9, wherein said resistor and capacitor units have a maximum dimension in said first direction which is a natural number times a maximum dimension in said first direction of the transistor unit. The semi-custom integrated circuit according to any of claims 1 to 9, wherein said resistor and capacitor units have a maximum dimension in said first direction which is a natural number times half a maximum dimension in said first direction of the transistor unit. The semi-custom integrated circuit according to claim 23, wherein said transistor unit is formed in a transistor region, and said resistor and capacitor units are formed in a wiring region provided at the side of said transistor region. The semi-custom integrated circuit according to any preceding claim, wherein the terminal portions of at least one of said transistor, resistor and capacitor units are aligned along a line in said first direction.

Inventors: HASEGAWA KIYOKAZU, KOSUGI NOBORU, SAITOH TADAHIRO, TOMITA MASAYOSHI, HASEGAWA, KIYOKAZU, KOSUGI, NOBORU, SAITOH, TADAHIRO, TOMITA, MASAYOSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, H01L21