A transistor amplifier having variable bias circuits

Abstract: The invention relates to an improved electrical amplifier (22) including a circuit arrangement which biases the amplifier (22) so that current in an output stage of the amplifier (22) is constant even though its load current varies. The circuit arrangement is configured so that the biasing current in the output stage is varied dynamically, thus compensating for changes in the current of the load (18) which the amplifier (22) drives.

Description: The invention relates to amplifiers in general and more particularly to an amplifier having variable bias circuits. Transistor amplifiers are widely used in different types of electronic equipment. A fundamental tradeoff in the design of an amplifier is that of power consumption versus performance. A typical transistor amplifier has at least an input stage which accepts an input signal, one or more intermediate stages and an output stage which delivers the input signal to a load circuit. Power for the amplifier is supplied from a power source connected to the amplifier. The output stage of the amplifier frequently operates in what is known as the large signal region of operation. In this region of operation the signal or load current is the same order of magnitude as the quiescent or bias current. When an amplifier is operating in this large signal mode, many of its characteristics vary as a function of the signal level. For example, some of the critical performance characteristics which vary with operating current include and output impedance, bandwidth and linearity. Even though the above problem occurs in several types of amplifier topologies, its effect is noticeable in a common emitter follower configuration which is used to illustrate the problem. Fig. 1 shows an electrical schematic of a prior art emitter follower amplifier operating in a class A mode. When the output voltage (V o ) rises towards a maximum, the emitter current (I e ) of the transistor is I1max.+I Q . When the output voltage decreases towards 0 volts, I1 decreases and the emitter current of Q′1 approaches I Q . As the output voltage goes negative, the load current (I1) goes negative and the emitter current of Q′1 decreases towards 0. The result of this large signal operation is that Q′1 collector current could vary from I Q + I1max. to no current at all. Since many transistor parameters are function of the collector current, the performance of the amplifier can vary significantly with signal levels and is thus non-linear. The prior art has provided several techniques to compensate for the non-linearity in amplifiers. One obvious technique is to increase I Q in order to have it dominate over I1 variations. This technique would improve linearity at the expense of power consumption. Another prior art technique used for improving the nonlinear characteristics of amplifiers is negative feedback. Even though this technique works well for its intended purpose, it has drawbacks which adversely affect the operation of the amplifier. The ability of negative feedback to improve performance is limited by the amount of excess gain available as well as stability limitations. Feedback is also limited in its ability to improve large signal performance by the dynamic range of error correcting circuitry within the feedback loop. U.S. Patent 5 254 381 to Wheatley described a balanced-to-single-ended signal converter using the feedback technique improved by a circuit nulling the input offset error. Cascode topologies are another prior art technique used to improve the non-linear characteristics of amplifiers. Cascode circuit topologies are commonly used to improve amplifier performance by adding transistors which maintain a primary amplifying transistor at a constant operating voltage. This technique can be used to widen bandwidth and improve linearity in voltage gain amplifiers. However, Cascode techniques are limited in their application to current only gain amplifiers. In addition, Cascode circuitry also suffers from a reduction in signal swing due to voltage drops required for the additional Cascode devices. It is therefore the main objective of the present invention to provide an improved amplifier that functions in its linear operating range during large signal mode of operation. The performance of the amplifier, according to the teaching of the present invention, is improved by dynamically varying the bias current of a transistor which is used in a current gain configuration. This technique improves many characteristics such as input impedance, bandwidth and linearity. More importantly, these improvements are achieved without the limitations of negative feedback or Cascode configurations. Since these improvements are achieved without increasing supply current, the technique provides a significant improvement in performance versus power consumption tradeoffs. It should also be noted that the technique described in detail below is applicable to many different types of amplifier topologies and can also be used in addition to negative feedback and/or Cascode topologies for even greater performance enhancement. The improved amplifier includes a circuit arrangement that provides a bias current (I Q ) which is a function of an input signal (V IN ) and a load Z L . The mathematical expression for the relationship between IQ, V IN and Z L is I Q =f(V IN ,Z L ). Stated another way, I Q = Ie-AV IN /ZL; where I Q represents the biasing current, Ie represents the emitter current in a device configured in a voltage follower configuration, A represents the amplifier gain, V IN represents the input signal and Z L is a load impedance. In a specific configuration, the improved amplifier includes a differential stage formed from a pair of differential transistors. An emitter follower transistor is connected to the differential stage. A current source interconnects the emitter terminals of the differential pair transistors to a negative rail of a power supply. Another emitter follower transistor is connected to the differential stage. A load circuit with an impedance characteristic similar to that of the load which the amplifier drives is connected to the emitter electrode of said another emitter follower. As a result, a biasing current I Q is generated and is coupled into the emitter follower transistor by a current mirroring circuit. The foregoing features and advantages of the invention will be more fully described in the accompanying drawings. Fig. 1 shows a prior art emitter follower amplifier operated in Class A mode. The figure is helpful in understanding the problem which the present invention corrects. Fig. 2 shows an electrical schematic of a circuit which includes the teachings of the present invention. Fig. 3 shows an electrical circuit of an amplifier according to the teachings of the present invention. Fig. 2 shows an electrical schematic of a circuit according to the teachings of the present invention. The circuit comprises an amplifier 10 connected to current source 12 and load means 14. A power supply is connected to the amplifier and provides power thereto. The amplifier has an input terminal which accepts an input signal V IN and an output terminal for providing an output voltage V o . The amplifier 10 may include a plurality of input stages coupled to an output stage represented by device 20 which is arranged in an emitter follower configuration. In the preferred embodiment device 20 is a transistor. It should be noted that the present invention is applicable to amplifiers whose output stage is configured differently. Thus, the emitter follower configuration is only illustrative of applicant's invention and should not be construed as a limitation on the scope of the present invention. Still referring to Fig. 2, the key to the variable bias current is to make the bias current IQ a function of signal level in such a way that the transistor emitter current (I e ) and collector current remain constant or nearly constant as load current (I L ) varies. The mathematical expression for this relationship is I Q =f(V IN , Z L ) where I Q represents the bias current, V IN represents the input signal and Z L represents the load. The mathematical expression can be stated more precisely as I Q =I e -AV IN /Z L where I Q represents the bias current. Ie represents the emitter current. A represents the gain of the amplifier. V IN represents the input signal and Z₀ represents the load impedance. Fig. 3 shows a detailed circuit arrangement for an amplifier according to the teachings of the present invention. The circuit arrangement includes the last two stages of an amplifier which are identified by numeral 22, a circuit arrangement 24 which biases the amplifier and an output load circuit 18. As described previously, I Q is made to be a function of V IN and output load 18 so that the current through the amplifier is constant. The amplifier 22 includes a differential stage formed by circuit components 28, 30, R and R′. A constant current source 29 interconnects the differential stage to the negative rail of the power supply. The differential stage is coupled to the output stage which is formed by NPN transistor Q1. The transistor Q1 is configured in an emitter follower configuration. As stated previously, the emitter follower configuration is only illustrative, and other types of configurations may be used without departing from the spirit and scope of the present invention. Still referring to Fig. 3, values for R′ and R are selected based upon the type of amplifier that one is designing. Selection of appropriate values is well within the skill of the art and therefore no specific values will be given. In the preferred embodiment of this invention R′=R/2. Of course, it is within the skill of the art to change the ratio between R′ and R. As can be seen from Fig. 3, the differential amplifier receives the input signal V IN , amplifies it and delivers it as single-ended signal Vi on the base of device Q1. Simultaneously, one-half the negative phase of V i is provided at V′ i . A mathematical expression for this relationship may be stated as V′ i =V i /2. As will be explained subsequently, V i is buffered by Q1 and converted to a current used for driving load 18. Also, V ′i is processed by a circuit arrangement 24 and generates the current I Q which biases Q₁. Still referring to Fig. 3, circuit arrangement 24 includes a current mirror formed by devices Q3 and Q4, a device Q2 coupled in an emitter follower configuration and an RC circuit arrangement 32. The RC circuit arrangement 32 is approximately two times the impedance of the equivalent load circuit 18. The RC circuit arrangement 32 generates the current which is reflected as I Q in the emitter circuit of Q1. As can be seen from Fig. 3, the voltage V′i is provided at the base of Q2 and is converted into a current by the RC circuit configuration. This current is mirrored into the emitter terminal of Q1 by Q3 and Q4. Still referring to Fig. 3, the load circuit 18 which is driven by the improved amplifier includes a high current circuit formed from four parallel interconnected transistors 26′. The emitter terminal of the transistors is connected through a resistor Rout to a reference voltage level (not shown). It is connected to ground and the collector electrodes of the transistor 26′ are connected to the positive terminal of the power supply. As stated above, other types of load circuits can be designed. In operation, an input signal V IN is applied to the differential inputs of the differential amplifier. The differential amplifier generates opposite polarity voltages V i and V′ i . The V i and V′ i voltages are out of phase signal with V′ i =V i /2. The voltage V i drives Q₁ which generates current I1 for driving load 18. Similarly, the V′ i voltage drives emitter follower Q2 and RC circuit arrangement 32 provides current into current mirrors Q3 and Q4. The signal variable current sunk by Q4 is opposite in phase to I₁. This makes I Q the desired function of V IN . In this embodiment the quiescent current in Q1 is set by the difference between the quiescent voltage at V′ i and the ground supply (minus two times V be ) divided by Z L where 2V be represents the base emitter voltages of Q1 and Q3. The impedance of 32 is twice the value of circuit 18's load impedance. As can be seen from Fig. 3, the input impedance Z L of the compound output transistor is both resistive and capacitive. Thus, circuit arrangement 32 has both a resistive portion and a capacitive portion. It should be noted that the load 32 must have characteristics equivalent to that of the output load which the amplifier is driving. It should also be noted that the biasing current I Q has a static portion and a dynamic portion. For Fig. 3 the static portion of I Q was obtained by rationing or "selecting a ratio for the" collector resistors (R and R′) and the load which Q2 drives. While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims: A circuit arrangement for biaising an amplifier, said amplifier comprising an input stage for amplifying an input signal, an output stage coupled to the input stage and a load circuit connected to said output stage, said circuit arrangement being characterized in that it comprises : a circuit means (32, Q2) coupled to said input stage, said circuit means responsive to a reference signal and generating therefrom a bias current whose magnitude varies so that IQ=Ie-A*VIN/ZL with IQ represents the bias current, le represents a current flowing in the output stage of said amplifier, A represents the gain of said amplifier, ZI represents the impedance of said load circuit and VIN represents the input signal; and a current mirror circuit means (Q3,Q4) interconnecting the circuit means to said output stage, said current mirror circuit means mirroring the bias current to said output stage. The circuit arrangement of claim 1 wherein the reference signal includes a voltage having a value V′I =VI/2 wherein V′I represents the negative phase of an input voltage and VI represents the positive phase of said input voltage. The circuit arrangement of anyone of claims 1 or 2 wherein said circuit means includes a transistor (Q2) having an emitter electrode, a base electrode coupled to said reference signal and a collector electrode for coupling to a power supply; and a circuit connected to the emitter electrode of said transistor having characteristics equivalent to said load circuit. The circuit arrangement of anyone of claims 1 to 3 wherein said circuit connected to the emitter electrode comprises a RC circuit (32). The amplifier of anyone of claims 1 to 4 wherein said input stage includes a differential amplifier (28, 30) which receives said input signal (VIN) and generates a pair of differential voltages (VI,V′I) therefrom, and an emitter follower transistor (Q1) connected to the differential amplifier. The amplifier according to claim 5 comprising a current source (29) coupled to said differential amplifier (28,30).

Inventors: SUTTERLIN PHILIP HARVEY, SUTTERLIN, PHILIP HARVEY
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: H03F1
IPC codes: H03F1, H03F3