Method of forming stacked tungsten gate PFET devices and structures resulting therefrom

Abstract: A stacked semiconductor structure including: a base structure comprised of a semiconductor substrate (18/19) having active regions (21) of devices (N1, ...) formed therein and a plurality of polysilicon lines (23-1, ...) formed thereupon; a first thick passivating layer (26/27) formed onto said substrate having a set of first metal contact studs (30-1, ...) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, ...), the upper part of said first contact studs defining either gate electrodes of sPFET devices (P2) and/or interconnection conductors; the surface of said first metal contact studs is coplanar with the surface of said first thick passivating layer; a thin insulating layer (31) forming the gate dielectric layer of said PFET devices and provided with contact openings (32-1, ...) to expose desired portions of said first contact studs at desired locations; a plurality of polysilicon lands (33-1, ...) formed over said thin insulating layer (31), a certain portion thereof define the source, drain and channel region of the body of a determined PFET device (P2); at least one of said source and drain regions contacting a first metal contact stud (30-4) through a contact opening; a second thick passivating layer (35/36) having a set of second metal contact studs (38-1, ...) therein contacting at least one of said polysilicon lands (33-1, ...) and/or said first contact studs (30-1, ...); the surface of said second metal contact studs is coplanar with the surface of said second passivating layer. a first metal interconnection configuration having metal lands (39-1, ...) electrically contacting at least one of said second metal contact studs (38-1, ...); and a final insulating film (40). The structure of the present invention can be advantageously used in chips implementing 6D SRAM cells with stacked PFETs as load devices in CMOS FET technology.

Description: The present invention relates to the Integrated Circuit manufacturing and more specifically to a method of forming stacked tungsten gate PFET devices in semiconductor chips and to the structures resulting therefrom. In particular, the method has applicability in the forming of stacked tungsten gate PFETs to be used as load devices in six device (6D) SRAM cells. Polycrystalline silicon (polysilicon) resistors are commonly used as load devices in a variety of digital and analog applications, and in particular, in Static Random Access Memories (SRAMs). SRAM cells with resistive loads are thereafter referred to as the 4D/2R SRAM cells. Stacking polysilicon load resistors above the NFETs in 4D/2R SRAM cells is much appreciated in the design of the SRAM chip layout. This results in a significant reduction in the SRAM cell size because the cell area is then only determined by the area used by the NFETs. It is now a general practice in the industry to have the load resistors of 4D/2R SRAM cells formed by resistive polysilicon lands obtained from a very thin layer of either intrinsic or lightly doped polysilicon material. However, because these load resistors must be fairly high-valued, say in the tera-ohms (10¹²Ω) range or even above, in order to decrease the current drawn by the cell, capacity of 4D/2R SRAM cell chips appears to be limited to the 1 megabits. As a matter of fact, for increased capacities, the polysilicon layer should be so thin that the process tolerances would be too difficult to control. In addition, 4D/2R SRAM cells are also very sensitive to soft errors produced by alpha particles. Beyond the 1 megabits, stacked PFETs instead of polysilicon resistors have to be used as load devices although this is at the cost of a significantly more complicated manufacturing process. Fig. 1 shows a conventional 6D SRAM cell circuit referenced 1 with PFETs as load devices. Two cross-coupled NFETs N1 and N2, so-called the driver transistors, are connected between common node 2 tied to a first supply voltage Vs (usually the ground Gnd) and respective nodes 3 and 4, so-called charge storage nodes. These nodes 3 and 4 are connected to a common node 5 tied to a second supply voltage (usually a positive voltage Vc) respectively through PFETs P1 and P2. On the other hand, nodes 3 and 4 are also respectively connected to the bit lines BLT and BLC through NFETs N3 and N4, so-called the access transistors. The gate electrodes of NFETs N3 and N4 are connected to the word line WL for READ and WRITE operations. Fig. 2 is a partial cross-sectional view of the structure of the 6D SRAM cell circuit of Fig. 1 when integrated in a semiconductor substrate according to a conventional CMOS manufacturing process offering stacked polysilicon gate PFET devices (sPFETs). The structure referenced 6 is a good example of the advanced state of the art known to date and is extracted from an article entitled: "A .1 µA stand-by current ground-bounce-immune 1-M bit CMOS SRAM by M. Ando et al, published in the IEEE JSSC vol. 24, N° 6, Dec. 89, pp. 1708-1713. Reference numeral 7 indicates the P type silicon substrate. Numerals 8 indicate the different field recess oxide (ROX) regions that are used to isolate the different active regions of the structure. Numerals 9 are active N+ implanted source and drain regions of the NFETs. Numeral 10 indicates the gate dielectric layer, typically an SiO₂ layer. The highly doped N+ polysilicon gate electrodes of driver NFETs N1 and N2 are respectively referenced 11-1 and 11-2. Polysilicon gate electrode 11-2 forms a buried contact with region 9′ which is a protrusion of the drain region 9 of NFET N1. The gate electrodes 11-1 and 11-2 and the source and drain regions of NFETs N1 and N2 are covered by a thin insulating protective layer 12 of SiO₂. SiO₂layer 12 forms oxide sidewalls or spacers on the lateral sides of gate electrode 11-1 of NFET N1. A polysilicon land 13 surmounts gate electrodes 11-1 and 11-2 and is isolated therefrom by said SiO₂ layer 12. Polysilicon land 13 results from the patterning and selective doping of an intrinsic or lightly doped polysilicon layer that has been deposited to form the body of sPFETs. As apparent from Fig. 2, this polysilicon land 13 is highly doped with a P type dopant except just above gate electrode 11-1. The undoped region forms the channel region of the sPFET P1 while the adjacent P+ doped regions form the source and drain regions thereof. An extension of the drain region of sPFET P1 so-called the extended drain region contacts the small portion of gate electrode 11-2 which is exposed through an opening in oxide layer 12. N+ doped gate electrode 11-1 of NFET N1 plays also the role of gate electrode of sPFET P1, while layer 12 is the gate dielectric thereof. More generally, for each cell, oxide layer 12 is opened in all locations where it is necessary to make a contact between the N+ doped polysilicon gate electrode of a NFET and the adjacent P+ extended drain region of the corresponding sPFET. Note that region 9 and protrusion thereof 9′, gate electrode 11-2 and the extended drain region of sPFET P1 13 are at the potential of node 3, achieving thereby the desired cross-coupling of the devices as illustrated in the cell circuit of Fig. 1. At this stage of the process, the structure is said to have completed the Master Slice processing steps of a polysilicon gate CMOS FET technology. The structure is passivated by a relatively thick, insulating SiO₂ layer 14 of about 500 nm. As such, the structure results from the FEOL (Front End Of the Line) processing. Elements that will now be described are formed during the personalization steps or BEOL (Back End Of the Line) processing. Numeral 15 is a typical example of a polycide land or line used as a power bus. In Fig. 2, polycide land 15 which connects a N+ active region 9 (the source region of a NFET not illustrated in Fig. 2) to Gnd is so-called thereafter the Gnd bus. An additional insulating SiO₂ layer 16 terminates the structure. Layer 16 is provided with contact openings (not shown) to allow appropriate contacting with the metal bit lines BLT and BLC and power busses (e.g. the Vc power bus). As apparent from Fig. 2, all the succeeding layers, and in particular polysilicon layer 13, are conformally deposited which results in the typical "corrugated" relief aspect of the upper layers of structure 6. The cell construction of Fig. 2 wherein the PFETs used as load devices are stacked above the NFETs, is of great interest in terms of density, because the cell area is only determined by the area of NFETs. However, the disclosed semiconductor structure and its corresponding manufacturing process have some major inconveniences that are recited below. 1. The structure of Fig. 2 needs for its fabrication six more additional masks with respect to a conventional manufacturing process of 6D SRAM cell chips not offering sPFETs in the menu. The first mask is used to remove the gate oxide layer 10 above protruded source region 9′ of NFET N1 to allow the buried contact between gate electrode 11-2 and said region 9′. The second mask makes an opening above gate electrode 11-2. The third mask delineates the N type lightly doped polysilicon layer 13. The third mask is used to shape the desired polysilicon land wherein sPFET P1 and its related extended drain region (for connection with underlying gate electrode 11-2) are to be formed. The fourth mask is a block-out mask that is required to protect the channel region of sPFET P1 from the implantation of P type dopants while forming the highly doped P+ source and drain regions thereof, along with said extended drain region. The fifth mask defines contact openings where polycide lands conveying the Gnd potential contact source regions 9 of certain NFETs e.g. driver transistors (not referenced). An example of a Gnd bus is shown in Fig. 2. Finally, the sixth mask delineates said polycide lands: the word lines and some power busses. 2. sPFET P1 is very dependent upon the underlying NFET N1 size and lay-out which in turn, results in less flexibility in the design. Because the gate electrode 11-1 of NFET N1 is also the gate electrode of sPFET P1, the layout of the two devices are strongly coupled both in terms of device size and device lay-out. More generally, since the gate length of the NFET, e.g. N1, must be at the minimum allowed by the lithography for maximum performance, so must be the gate length of the corresponding sPFET e.g. P1. This constitutes a potential source of reliability hazards. Firstly, if the out-diffusion of the P+ dopants contained in the implanted source and drain regions of the sPFET P1 is not well controlled, said source and drain regions get too large, thereby reducing the effective channel length of sPFET P1. As a consequence, punch-through problems can occur. The channel length of sPFET P1 cannot be increased since this length is dictated by the performance requirements of NFET N1 as mentioned above. In addition, since the block-out mask defining the channel region of sPFET P1 is also at minimum image size, alignment tolerance between this block-out mask and the channel region can result in a channel region not correctly aligned with the gate electrode. Figs. 3A and 3B illustrates the effect of misalignment on sPFET P1 as to the introduction of parasitic devices to an ideal PFET P (that would be obtained, should misregistration not exist) that has inherently a poor performance. In the first case (positive misalignment) shown in Fig. 3A, diode D (forwardly-biased) and a high value resistor R are in series with the source region s of the ideal PFET P. These parasitic devices decrease the effective gate to source overdrive voltage (VGS-VT) of sPFET P1 (which has already a high threshold voltage VT) and hence will decrease the "ON" current of sPFET P1. In the second case (negative misalignment), shown in Fig. 3B, the parasitic devices: e.g. resistor R and diode D (now reversely-biased) are in series with the drain region d of the ideal PFET P and similarly decrease the current capability of sPFET P1, as a result, the latter is far from an ideal PFET P. 3. The gate electrode of the sPFET P1 has not an optimized work function. Since both NFET N1 and the corresponding sPFET P1 formed thereupon share the same N+ gate electrode 11-1, the gate electrode of the sPFET is therefore of the N+ type while P+ type would have been preferred. It is well recognized that this situation creates some problems from the punch-through point of view, because in this case, the channel region is buried instead of being in surface. Punch-through effects induce leakage currents which are critical for the SRAM cell stand-by power consumption. 4. As pointed out above in conjunction with Fig. 2, the conventional manufacturing process results in a non planarized structure 6. The gate oxide layer 12 and the polysilicon layer 13 forming sPFET P1 are deposited over the castellated topology of the NFET N1 gate electrode 11-1 although slightly smoothed by protective layer 12, thereby creating reliability problems, known under the brand name of "step coverage', since polysilicon layer 13 is much thinner than gate electrode 11-1. 5. A parasitic P+/N+ diode is formed between N+ gate electrode 11-2 of NFET N2 and the P+ extended drain region of sPFET P1. This diode deteriorates the contact quality which is no longer of the ohmic type thereby slowing down the SRAM cell performance. 6. The word lines WL, some power busses and possibly the local interconnect scheme that makes straps and short distance connections at the silicon wafer level, are made of polycide. Polycide is a quite good conductive material; however it is known to exhibit higher re-sistivities than metal. 7. Finally, the structure of Fig.2 has a poor design flexibility because of the difficult contacting of source region of sPFET P1 to Vc power bus because the presence of the polycide lands 15. According to FR-A-2 595 165 there is a three-dimensional type semiconductor device comprising a first semiconductor device comprising a first semiconductor integrated circuit layer including at least one first semiconductor elemental device having active regions, first insulating layers formed on the first semiconductor elemental device and first interconnection layers formed on the first insulating layers and connected to the active regions in the first semiconductor integrated circuit layer; a second semiconductor integrated circuit layer formed on the second insulating layer and including at least one second semiconductor elemental device having active regions, third insulating layers formed on the second semiconductor elemental device and second interconnection layers formed on the third insulating layers and connected to the active regions in the second semiconductor elemental device. It is of the essence of this disclosure that at lease one contact hole formed straight to directly reach the first semiconductor integrated circuit layer from one of the active regions in at least one second semiconductor device; and at least one interlayer interconnection directly connecting one of the active regions in the second semiconductor elemental device to the first semiconductor integrated circuit layer through the contact hole. It is therefore a primary object of the present invention to provide a method of forming stacked tungsten gate PFET devices that implies a reduced number of masking steps. It is another object of the present invention to provide a method of forming stacked tungsten gate PFET devices that is independent of NFET device size and lay out, avoiding therefore potential problems related to leakage and misregistration. It is another object of the present invention to provide a method of forming stacked tungsten gate PFET devices wherein the gate electrodes of said devices are made of P+ polysilicon for adequate work function. It is another object of the present invention to provide a method of forming stacked tungsten gate PFET devices wherein said devices are formed on planar surfaces for better reliability. It is another object of the present invention to provide a method of forming stacked tungsten gate PFET devices wherein no parasitic diodes are produced in the contacts for better performance. It is another a further object of the present invention to provide a method of forming stacked tungsten gate PFET devices wherein word lines, power busses and local inter-connect straps are formed of metal for improved conductivity. It is still a further object of the present invention to provide a method of forming stacked tungsten gate PFET devices offering quite good design flexibility for easy contacting of the source regions of PFET devices to the Vc power bus. The above objects are achieved by the integrated circuit structure according to claim 15 and the corresponding manufacturing method according to claim 1 of the present invention. A stacked semiconductor structure including a base structure comprised of a semiconductor substrate having active regions of devices formed therein and a plurality of polysilicon lines formed thereupon after completion of the Master Slice processing steps characterized in that it further includes: a first thick passivating layer formed onto said base structure having a set of first metal contact studs therein contacting at least one of said active regions and/or said polysilicon lines; the upper part of said first contact studs defining either gate electrodes of PFET devices and/or interconnection conductors; the surface of said first metal contact studs is coplanar with the surface of said first thick passivating layer; a thin insulating layer disposed over said first thick passivating layer forming the gate dielectric layer of PFET devices and provided with contact openings to expose desired portions of said first contact studs at desired locations; a plurality of polysilicon lands formed over said thin insulating layer, certain portion thereof defines the source, drain and channel region of the body of a PFET device; at least one of said source and drain regions contacting a first metal contact stud through a contact opening; a second thick passivating layer disposed onto the resulting structure having a set of second metal contact studs therein contacting at least one of said polysilicon lands and/or said first contact studs; the surface of said second metal contact studs is coplanar with the surface of said second passivating layer. The manufacturing method used to produce this stacked semiconductor structure includes the following sequence of steps: a) depositing a first thick passivating layer of a dielectric material that can be planarized onto the base structure; b) forming a set of first stud openings so-called first stud openings in said first thick passivating layer exposing at least one active region and/or one of said polysilicon lines; c) depositing a first layer of a conductive material to fill said first stud openings and define a set of first contact studs; the upper part of certain of said first contact studs are the gate electrodes of said PFET devices; d) planarizing the structure to make the top surface of said first contact studs coplanar with the surface of said first thick passivating layer; e) depositing a thin insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose certain first contact studs at desired locations; f) depositing a layer of polysilicon lightly doped with an impurity of a first type of conductivity; g) patterning said polysilicon layer to define a plurality of polysilicon lands contacting said first contact studs at said desired locations; h) selectively implanting ions of a second type of conductivity dopant in the structure to define the source and drain regions of the PFET devices and interconnection conductors in certain polysilicon lands or portions thereof; i) depositing a cap layer; j) depositing a second thick passivating layer of a dielectric material that can be planarized; k) forming a set of second stud openings in said second thick passivating layer to expose desired portions of said polysilicon lands and/or portions of said first contact studs; l) depositing a second layer of a conductive material to define a second set of second contact studs; m) planarizing the structure to make the top surface of said second contact studs coplanar with the surface of said second thick passivating layer. Preferably, said conductive material is a metal, typically tungsten and said ions of a second conductivity type are boron ions. Compared to the prior art approach described in conjunction with the structure of Fig.2, the method of forming stacked tungsten gate PFET devices sPFET and structures resulting therefrom of the present invention have definite advantages: 1. Only four extra masks are required, 2. The sPFET is independent of the underlying NFET size and lay-out. 3. the sPFET is controlled by a tungsten gate electrode. 4. the sPFET device is formed onto a planarized surface. 5. the N+/P+ diode contact structure is replaced by a tungsten contact stud forming an ohmic contact. 6. Word lines WL, Gnd and Vc power busses, and the local interconnect conductors are made of metal instead of polycide. 7. Very high design flexibility which allows easy contacting of the sPFET source regions to the Vc power bus. The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may best be understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings. In the drawings: Fig. 1 is a diagram showing a conventional 6D SRAM cell circuit including two PFETs as load devices. Fig. 2 is a cross-sectional view partially broken away of the structure of the 6D SRAM cell circuit of Fig. 1 when integrated in a silicon substrate according to a conventional CMOS FET manufacturing process offering stacked polysilicon gate PFET devices. Figs. 3A and 3B detail the PFET device structure of Fig. 2 depending positive or negative mask misregistration illustrating the parasitic devices introduced thereby. Fig. 4 shows a partial cross-sectional view of a conventional base structure of the 6D SRAM cell of Fig. 1 after having completed the Master Slice processing steps of a standard CMOS FET manufacturing process. Figs. 5 to 12 show the structure of Fig. 4 being processed through a sequence of processing steps in accordance with a preferred embodiment of the method of the present invention. Figs. 13 and 14 are plan views which show the typical lay-out of the 6D SRAM cell with stacked tungsten gate PFETs as load devices of the present invention at two different stages of the manufacturing. Fig. 4 shows a partial cross sectional view of a conventional base structure of the prior art after source/drain region and polysilicon gate electrode formation that results from a standard polysilicon gate CMOS FET process. The right hand part shows the driver NFETs N1 and N2 combination of the 6D SRAM cell circuit of Fig. 1 and is similar in some respect to the structure shown in Fig. 2. The left hand part shows three adjacent NFETs referenced N5, N6 and N7, such those that can be found in the I/O circuit portion of the chip, outside the memory array properly said. In Fig. 4 the whole structure is designated by reference 17 and is briefly described thereafter. The starting material consists of a conventional P⁺ silicon substrate 18 having a P⁻ epitaxial layer 19 thereon. ROX regions 20 are used as it is well known for the skilled man to isolate active regions one from the others at the surface of the wafer. N⁺ implanted active regions 21 have been formed in the epitaxial layer 19 to constitute the source and drain regions of the NFETs. Active regions 21 are generally provided with a thin TiSi₂ contact layer to reduce their sheet resistance thereby improving electrical contact quality with the contact studs to be formed subsequently. The gate dielectric layer, typically an SiO₂ layer, is referenced 22. Numerals 23 indicate the remaining portions of the N+ highly doped polysilicon layer 23 that has been patterned to create the polysilicon gate electrodes. Numerals 23-1 and 23-2 designate respectively the gate electrodes of NFETs N1 and N2. Oxide sidewalls or spacers 24 have been formed on the lateral sides of the polysilicon gate electrodes for a better definition of the channel length of NFETs. The above-described device structure of Fig. 4 is shown for the purpose of illustrating the present invention, and is a conventional structure in the art, amenable to fabrication by the use of many known semiconductor CMOS FET manufacturing processes, but is not limited to CMOS technology. Firstly, the said remaining polysilicon portions are not limited to gate electrodes, they could be lands used as conductors, as such forming the extrinsic base contact in a polysilicon self-aligned bipolar transistor manufacturing process. Consequently, said remaining polysilicon portions 23 will be referred to more generally as polysilicon lines. Secondly, active regions 21 are not limited to source and drain regions of FETs but also include emitter, base and collector regions of bipolar devices. To take into account that structure of Fig. 4 could be adapted to result either from a bipolar, CMOS or BiCMOS manufacturing process, any base structure, at the stage of Fig. 4, is said to have completed the Master Slice processing steps. In other words, this means that the forming of active regions 21 (irrespective the type of devices formed therein), and optionally, polysilicon lines 23-1,... has been accomplished. Detailed description of a preferred embodiment of the method of the present invention Now a preferred embodiment of the method of the present invention will be described with reference to Figs. 5 to 12. 1) First, a relatively thick layer of a passivation and planarization dielectric material is deposited onto the conventional base structure of Fig. 4. To that end, the wafer is cleaned by dipping in a tank containing an H₂SO₄/H₂O₂ (4:1) acidic solution. This cleaning step will be referred to below as the Piranha clean. A thin Si₃N₄ diffusion barrier layer (not shown) is blanket deposited over the wafer with a thickness of 50nm. The Si₃N₄ diffusion barrier layer avoids potential dissolution of the TiSi₂ layer in the upper layer to be subsequently formed. This step is completed in a standard LPCVD equipment at 785°C with a SiH₂Cl₂/NH₃ reative gas. An intrinsic polysilicon etch stop layer 25 is conformally deposited over the surface of the wafer using conventional CVD process to a thickness in the range of 50 nm. The etch stop layer is used to protect the bird's beak of the ROX regions should a contact stud overlying both silicon (e.g. at a source/drain region) and SiO₂ (e.g. at a ROX region) be required. The material forming this etch stop layer must have a good etching selectivity with the phosphosilicate glass (PSG) layer to be subsequently formed. Al₂O₃ is suitable but intrinsic polysilicon is preferred, because it has not only the desirable high etch ratio with PSG, say about 25:1, but it is easier to etch. The structure is cleaned again in two steps: first, using the Piranha clean as described above followed by a Huang B clean in an H₂O/HCl/H₂O₂ (5:1:1) acidic solution, then rinsed. The PSG layer 26 is now deposited conformally at 400°C, using a SiH₄ /PH3 gas with N₂ as the carrier gas in a APCVD reactor such as a WATKINS-JOHNSON to reach a thickness of 900 nm. Optionally, a 200 nm thick intermediate pyrolitic SiO₂ layer (not shown) can be inserted between intrinsic polysilicon layer 25 and PSG layer 26. It aims to protect the intrinsic polysilicon layer 25 from the phosphorous dopants contained in layer 26. The deposition is achieved in an AME-5000 at 440°C in an O₂/SiH₄/N₂ ambient. Next, the PSG layer 26 is chem-mech polished for fine planarization in a WESTECH or STRAUSBAUGH equipment using a solution of colloidal SiO₂ in water, e.g. the slurry referenced SC1 sold by SPEAR CARBO. After polishing, the remaining thickness is 600 nm. This step is followed by a post-clean in a SVG double-sided brush cleaner. After a new two-step cleaning as mentioned above, the process continues with the deposition of a PECVD SiO₂ oxide layer 27. The purpose of this layer is to act as a diffusion barrier layer in blocking the out-diffusion of the phosphorous dopants contained in the PSG layer into the upper layer of polysilicon to be subsequently formed. This step is completed in a standard PECVD equipment such as an AME-5000. The desired thickness of layer 27 is about 200 nm. Should a non contaminating passivating and planarizing dielectric material be used, e.g. quartz, the need of layer 27 could be eliminated. Quartz is appropriate, but results in an expensive process. Organic materials, such as polyimide, are also appropriate but behave badly in hot processing steps. Finally, phosphosilicate glass (PSG) is the preferred material although it necessitates an etch stop layer and at least two diffusion barrier layers. The wafer is then annealed in a furnace at 750°C during 1H in an N2 ambient. The resulting structure is shown in Fig. 5. This terminates the list of elements formed during the FEOL processing steps. 2) At this point of the process, the step of forming the set of first stud openings generically referenced 28 is now carried out. First stud openings are generally formed in two successive etching steps using two different masks: GS and CA. After a new two-step cleaning, a photoresist adhesion promoter such as HMDS is applied onto the structure (prebake time 7 mn), then a standard photoresist, e.g. the e-MERCK resin, is applied e.g. in a MTI MULTIFAB equipment, and baked. After alignment, the resist is exposed to UV light through a mask in a NIKON G6 stepper and developed to produce an in-situ GS resist mask (not shown) having the desired configuration. The first subset of openings is then formed by etching the PECVD SiO₂ diffusion barrier layer 27. Fig. 6 shows the structure after the only patterning of the LPCVD SiO₂ layer 27. However, during the formation of said first subset of openings, the PSG layer could also be partially etched. The situation shown in Fig. 6 is only for illustrating purposes. The first subset of openings consists of openings 28-10, 28-20 and 28-30. These openings correspond respectively to a top contact stud, a gate electrode and an overpass conductor to be subsequently formed. The first etching step is achieved in a AME 8300 equipment using a CHF₃/O₂ reactive gas to supply the reactive ions. The in-situ resist mask GS is stripped away and the structure is cleaned in a Piranha solution. 3) Next, the second subset of openings is formed by etching the thick PSG planarized layer 26 (and the optional pyrolitic layer mentioned above, if any), downwards to the etch stop layer 25. To that end, a second in-situ photoresist mask CA (not shown) is applied onto the structure in a quite identical manner than above. The second subset of openings is then created. The second step of etching can be achieved in the same AME 8300 equipment using CHF₃/O₂ reactive gas since PECVD SiO₂and PSG are quite similar materials. Finally, the exposed portions of the intrinsic polysilicon etch stop layer 25 are etched still in the same RIE equipment using a Cl₂/O₂/Ar or HCl/O₂/Ar plasma. The resist is stripped off and the structure cleaned again. Next, the structure is annealed in an ammonia (NH₃) ambient in a THERMCO equipment at 700°C during 55 mn with N2 as the carrier gas. The intrinsic polysilicon is oxidized through the thick dual passivating layer 26/27 to become fully neutral, from an electrical stand-point. This step is achieved in a THERMCO oxidation furnace model HiPOX at high pressure. Finally, the exposed portions of the underlying Si₃N₄ layer are etched in a SF₆ plasma. As shown in Fig. 7, different configurations are possible. First stud opening 28-1 comprises both upper and lower parts referenced 28-10 and 28-11 corresponding to said first and second etching steps respectively. These two etching steps allows the decoupling of the sizes of said first and second subsets of openings. For example, the size of the lower opening (e.g. 28-21) may be at the minimum size afforded by the lithography, while quite independently, the upper opening (e.g. 28-20) may be larger, to meet the size requiments for the gate electrode to be formed therein. A metal contact stud will be formed in opening 28-1, when filled with metal that will contact an active region 21. In a similar way, first stud opening 28-2 is also comprised of two parts 28-20 and 28-21. When filled with metal, the upper part will form the metal gate electrode of a sPFET device, while the lower part will be a pedestal stud, interconnecting said metal gate electrode with an active region 21 and polysilicon gate electrode 23-2 of NFET N2. First stud opening 28-3 consists of an upper part and two lower parts, which, when all be filled with metal, will respectively form an overpass conductor and two pedestal contact studs connected therewith, to provide a conductive strap. The strap will interconnect an active region 21 of NFET N5, an active region of NFET N6 and gate electrode 23-3 of NFET N7. Finally, first stud opening 28-4 is an example of an opening made in one step using the CA mask. When filled with metal, a metal contact stud will be formed to contact gate electrode 23-1. 4) Now, the steps of filling the first stud openings with a highly conductive material, typically a metal such as tungsten, and planarization are carried out. To that end, the structure of Fig. 7 is first cleaned in a 100: 1 diluted HF solution and rinsed. Prior to tungsten (W) filling, a titanium (Ti) layer is deposited with a thickness of about 40 nm in a VARIAN M2000 equipment to plate the bottom and side-walls of said first stud openings. This titanium layer prevents the diffusion of tungsten atoms in the active regions 21. Next, a thin titanium nitride (TiN) layer is formed over the titanium layer. This TiN layer aims to improve adhesion of the tungsten layer. This step is accomplished in the same VARIAN M2000 equipment but a flow of N2 is introduced in the Ar carrier gas until a thickness of 25 nm is obtained. A tungsten layer is then deposited in two steps to entirely fill the first stud openings. A CVD GENUS 8700 equipment is appropriate in that respect. Firstly, deposition is carried out at a high rate of 120 nm/min. at 450°C using a SiH₄/WF₆/H₂/He gas combination until a thickness of 240 nm is attained. Then, the deposition is continued at a lower rate of 40 nm/min. in the same equipment and with the same operating conditions, except in that, SiH₄ is no longer used, until the desired final thickness of about 550 nm is obtained. The deposited metal layers are now planarized using either a chem-mech technique, as described in EP-A-0223920 entitled: "Chem-mech polishing method for producing co-planar metal/insulator films on a substrate" assigned to the assignee of the present invention or plasma etching in an AME 8100 using a BCl₃/Cl₂/N₂ gas. This step is followed by a post-clean in a SVG double-sided brush cleaner. Planarization of the Ti-TiN and W composite layer produces first contact pads 29 and first contact studs 30 in first stud openings 28 that are referenced with corresponding references. Upper and lower parts thereof can be distinguished in Fig. 7. For example, first contact stud 30-1 is comprised of upper and lower parts respectively referenced 30-10 and 30-11. Similar reasoning applies to contact pad 29-1. This has to be generalized to all other first contact studs. Finally, as apparent from Fig. 8, the top surface of the first contact studs 30-x is now coplanar with the surface of the PECVD oxide layer 27. 5) Now, the gate dielectric of the PFET devices is formed. To that end, a first oxide layer 31 is deposited with a thickness of about 25 nm in a PECVD equipment such as an AME-5000. After cleaning in a Piranha solution, a new in-situ resist mask (OG mask) is formed over the structure and the oxide layer 31 is opened at desired locations. Contact openings 32 are formed in the oxide layer 31 by RIE in a AME 8300 reactor in a CHF₃/O₂ ambient. The structure is cleaned again. Contact openings 32, e.g. 32-1 are formed on the portions of the first contact studs where either a region of a sPFET device or an interconnect conductor (to be subsequently formed), have to contact a first contact stud. Next, a polysilicon layer is deposited that will provide the desired source, drain and channel regions of the body of PFET devices and interconnection conductors after patterning and adequate doping. To that end, a CVD intrinsic (non doped) polysilicon layer 33 is deposited in a LPCVD equipment such as ASM or TEMPRESS, at 615°C using SiH₄ to reach a thickness in the 10-100 nm range. However, because the sPFET device characteristics depend strongly on the grain size of polysilicon material of layer 33, it is recommended first to convert the polysilicon of layer 33 in an amorphous silicon layer and then, to recrystallize it at low temperature, in order to get grains as large as possible. Amorphization can be effected by ion implantation of Si atoms in an EXTRION CF5 implanter at an energy in the 25-50 KeV range and a dose of 1E15 at/cm2. The recrystallization anneal is completed in a THERMCO furnace at 625° in a N2 ambient and during 30H. Alternatively, an amorphous layer of the same thickness could have been directly formed as taught in the literature. In this case, polysilicon is deposited in a PECVD equipment or in the UHV chamber of an E-beam source evaporator and the recrystallization anneal still completed in a THERMCO furnace and a N2 atmosphere, but at 600°C and during 12 hours. A N type dopant is now blanket implanted in the polysilicon layer 33 to adjust the threshold voltage of the sPFET devices. The concentration in N type dopants needs to be accurately controlled in the channel region of sPFET devices. To that end, phosphorous atoms are implanted in polysilicon layer 33 to attain a concentration of 1E17 at/cm3 in the channel region of sPFETs. This step can be achieved in a EXTRION CF5 implanter and is followed by a standard implant anneal. Next, a photo-lithographic step (PR mask) is then performed, similar to the one previously mentioned in above point 2) to define the appropriate in-situ resist mask. This resist mask will be used to create the desired polysilicon land configuration in polysilicon layer 33. The structure is submitted to RIE in a TEGAL 1500 using a standard reactive gas composition such as CF₄/O₂/Cl₂/HCl that has a high polysilicon/ËCVD SiO₂ etch rate ratio. The resist mask is then stripped in an adequate stripper. As illustrated in Fig. 9, it remains three N- polysilicon lands 33-1, 33-2 and 33-3. Note that instead of performing the recrystallization anneal step mentioned above in point 5) before patterning the polysilicon layer 33, this step can be done after it, in order to have only a local recrystallization in the polysilicon lands. In this case, this step is followed by the above mentioned blanket implant. Alternatively, the recrystallization anneal could be replaced by a rapid thermal anneal (RTA) step at a temperature in the 600-700°C range, during 10-120s in a N2 ambient. A TEOS oxide layer 34 is now deposited over remaining polysilicon lands in a PECVD equipment such as an AME-5000. The desired thickness is about 100 nm. Layer 34 plays different roles. Layer 34 is used as a screen oxide layer for a subsequent ion implant step as it will be explained later. It also acts a diffusion barrier layer, and finally it encapsulates the body of the sPFET device, once formed, from the second PSG layer to be also subsequently formed. At this stage of the process, the resulting structure is shown in Fig. 9. 6) Next, a new photolithographic step (BG mask) is performed, in order to define the appropriate in-situ photoresist BG mask that will be used in particular to define the source/drain regions of the sPFET devices by an ion implantation step. The photolithographic step is identical to the one described above. A selective boron ion implant is then performed through screen oxide layer 34 for source/drain region definition of the sPFET devices and for doping of other polysilicon lands to define interconnection conductors. Only the channel region of sPFET devices is protected by the BG mask from ion implantation. The implantation of boron ions is performed in an EXTRION CF5 implanter at a dose of 1E16 at/cm2 and an energy of 30keV. The resulting structure is shown in Fig. 10. The photoresist in-situ BG mask is then stripped off. Finally, a low temperature (or rapid thermal anneal) is performed to reactivate the dopants in the source and drain regions of sPFETs. This step can be completed in a THERMCO furnace at a temperature ranging from 650 to 850°C in a N2 ambient and during 12 H. In Fig. 10, sPFET device P2 is clearly depicted. The body of sPFET device P2 comprises the source, drain, and channel regions respectively referenced SP2, DP2 and CP2. The gate electrode GP2 of sPFET device P2 is separated from the body by thin gate dielectric layer 31. Gate electrode GP2 is made of metal, therefore exhibiting a better work function than N+ polysilicon as it was the case with the structure of Fig. 2. Note also at this point, that contacts with the source and/or drain region of sPFET P2 can be made directly to active regions 21 and/or gate electrodes 23-x of devices underneath by first contact studs. For example, drain region DP2 is shorted to gate electrode 23-1 of NFET N1 by first contact stud 30-4, these elements are therefore at the potential of node 4 (see Fig. 1). Likewise, as apparent from Fig. 10, first contact stud 30-2 not only forms gate electrode GP2 of sPFET P2 but also interconnects gate electrode 23-1 of NFET N2, and source region 21 of NFET N1. As a result, first contact stud 30-2 is at the potential of node 3 (see Fig. 1). Should a specific source or drain region located above a first contact stud, a direct contact is therefore made without any additional lithography step. On the other hand, in the left part of Fig. 10, first contact stud 30-3 shorts polysilicon land 33-2, one active region 21 of NFETs N5 and N6, and gate electrode 23-3. Polysilicon land 33-3 is isolated since encapsulated by oxide layers 31 and 34. 7) A second thick PSG layer 35 is then deposited after Piranha/Huang B cleaning step. Layer 35 is submitted to a fine chem-mech planarization. After that, an additional thin PECVD oxide or preferably PSG layer 36 is deposited thereon, in order to eliminate pin holes. The steps of depositing and planarizing are completed in the same way as described in point 2). As a result, the top surface of structure 17 is quite flat. After a novel Piranha/Huang B cleaning step, the structure is ready again for stud opening. Second stud openings 28′ corresponding to the second contact studs are then opened, the etch stop layer being either the polysilicon layer 33 for the sPFET devices or tungsten for the first contact studs. The resulting structure provided with three second stud openings 28-1′, 28-2′ and 28-3′ is shown in Fig. 11. 8) Next, the second stud openings 28-x are filled by successive deposition of a Ti layer and a Ti-N layer that are blanket sputtered on the whole wafer to form a composite Ti-TiN layer 37. Second stud openings are then filled with a tungsten layer 38. The deposited metal layers are planarized with one technique described in point 3) above. Planarization of the Ti-TiN and W composite layer produces second contact pads 37 and second contact studs 38 in second stud openings 28′ that are referenced with corresponding references. Three second contact studs referenced 38-1, 38-2 and 38-3 are shown in Fig. 12. They respectively contact the source region SP2 of sPFET P2, first contact stud 30-3 and polysilicon land 33-3. A standard first metallization layer 39 is now deposited and patterned to leave metal lands 39-1, 39-2 and 39-3 at the M1 mask level. The metallization layer may be a Ti/Al-Cu/Si metallurgy. Metal land 39-3 is the word line WL, while metal lands 39-1 and 39-2 are power busses and are respectively connected to Vc and Gnd. Normal BEOL process can now continue. The structure is covered by an insulating film of PECVD oxide 40. The final structure is shown in Fig. 12. In order to increase the channel mobility and decrease the threshold voltage VT, hydrogen passivation of the dangling bonds can be done. It will help to minimize the effects of the grain boundary potential barriers on device performance. This step known in the art as the forming gas anneal step is completed in a furnace at 400°C during 30 mn in a N₂/H₂ forming gas. This step may be performed at different times during the BEOL processing and at any subsequent level, to improve the structure quality. The steps of depositing the dual PSG layer 35/36, of forming second contact studs 38-x,... and metal lands 39-x,... could be repeated again should the chip be of the multilevel type. Note that a planarization step is to be associated to each stud level. The structure fabrication is terminated by completing the terminal metallurgy steps including forming the contact pads of the Ball Limiting Metallurgy (BLM) and contact terminals (e.g. solder balls) as widely described in the literature. Other Considerations From this process description, it can be seen that, with only four more masks when compared with a conventional CMOS FET process, there is provided a tungsten gate sPFET device that has a high contact flexibility through the two sets of first and second contact studs. This means that the sPFET device can be connected to the active regions of devices (e.g. N1, N2, ...) through first contact studs while the connection to the M1 metal lands is made by the second contact studs. A planarization step is associated to each contact stud level and the proposed sPFET device is inserted therebetween. Polysilicon lands, are used to define the body of sPFETs, but they can also be used, if necessary, as interconnection lines or conductors. For better conduction, silicidation of said lines could be required, but at the cost of an extra mask. In addition, the upper parts of the first contact studs that are used as gate electrodes of sPFETs can also be used as interconnection conductors. As an example, the upper part of first contact stud 30-3 is used as an overpass conductor when combined with two lower parts to form a strap connecting two active regions and/or polysilicon gate electrodes at the silicon wafer level. The expected sPFET device characteristics are: Threshold voltage : 1.6 - 2.0V Oxide thickness : 20 - 30 nm Channel mobility : 10 cm2/V.s Subthreshold current: 2 pA ON/OFF current ratio: 10E6 Figs. 13 and 14 are typical views of the lay-out of the 6D SRAM cell when manufactured according to the method of the present invention at different stages of the manufacturing. Fig. 13 shows the lay-out at the stage of Fig. 5. Fig. 14 shows the lay-out corresponding to the structure at the stage of Fig. 12 when the metal lands defining the power busses (Vc, Gnd) and the word line (WL) have been delineated.

Claims: A method of forming stacked tungsten gate PFET devices on a semiconductor IC base structure having active regions (21) of devices (N1, ...) and/or a plurality of polysilicon lines (23-1,...) formed therein after completion of the Master Slice processing steps and the steps of: a) depositing a first thick passivating layer (26/27) of a dielectric material that can be planarized onto the base structure; b) forming a set of first stud openings (28-1, ...) so-called first stud openings in said first thick passivating layer (26/27) exposing at least one active region (21) and/or one of said polysilicon lines (23-1,...); c) depositing a first layer (30) of a conductive material to fill said first stud openings and define a set of first contact studs (30-1, ...); characterized in that the upper part of certain of said first contact studs are the gate electrodes of said PFET devices; and in that it further includes the following sequence of steps: d) planarizing the structure to make the top surface of said first contact studs (30-1, ...) coplanar with the surface of said first thick passivating layer (26/27); e) depositing a thin insulating layer (31) to form the gate dielectric of PFET devices and patterning it to define contact openings (32-1, ...) to expose certain first contact studs at desired locations; f) depositing a polysilicon layer (33) lightly doped with an impurity of a first type of conductivity; g)patterning said polysilicon layer (33) to define a plurality of polysilicon lands (33-1, ...) contacting certain of said first contact studs (30-1, ...) at said desired locations; h) selectively implanting ions of a second type of conductivity dopant in the structure to define the source and drain regions of the PFET devices and interconnection conductors in certain polysilicon lands or portions thereof; i) depositing a second thick passivating layer (35/36) of a dielectric material that can be planarized; j) forming a set of second stud openings (28-1′, ...) in said second thick passivating layer (35/36) to expose desired portions of said polysilicon lands (33-1, ...) and/or portions of said first contact studs (30-1, ...); k) depositing a second layer (38) of a conductive material to define a second set of second contact studs (38-1, ...); l) planarizing the structure to make the top surface of said second contact studs (38-1, ...) coplanar with the surface of said second thick passivating layer (35/36). The method of claim 1 further including the step of: m) depositing a cap layer (34) over said polysilicon lands (33-1, ...) prior to step h); The method of claim 1 or 2 further including the step of: n) depositing an etch stop layer (25) prior to step a) of depositing the said first thick passivating layer (26/27). The method of claim 3 further including the step of: o) depositing a barrier diffusion layer onto the said base structure prior to step a). The method of claim 4 wherein the material forming said etch stop layer (25) and said diffusion barrier layer is intrinsic polysilicon and Si₃N₄ respectively. The method of any above claim wherein step a) comprises the steps of: a1) depositing a thick layer (26) of PSG; a2) planarizing said thick layer of PSG; a3) depositing a thin layer (27) of LPCVD oxide over the PSG layer (26) to act as a diffusion barrier to the dopants contain therein. The method of any above claim wherein said step b) is achieved in two steps. The method of claim 7 wherein said two steps consists of: b1) forming a first subset of openings corresponding to conductors and/or gate electrodes of PFET devices extending partially through said first thick passivating layer; b2) forming a second subset of openings extending certain openings of said first subset to expose at least one of said active regions (21) and/or polysilicon lines (23-1, ...). The method of any above claim wherein step j) of selectively implanting ions is made through an in-situ photoresist mask (BG) masking the channel region of PFET devices. The method of any above claim wherein the polysilicon of step f) is of the P-type and the dopant of step h) is boron. The method of any above claims wherein step i) comprises the steps of: i1) depositing a thick layer (35) of PSG; i2) planarizing said thick layer of PSG; i3) depositing a thin layer (36) of either LPCVD oxide or PSG. The method of any above claim further including the steps of: p1) depositing a metal layer (39) onto the structure and patterning it to form metal lands (39-1, ...) in contact with certain of said second contact studs (38-1, ...); p2) depositing an insulating film (39) onto the structure. The method of any above claim wherein said steps d) and 1) of planarization are completed by chem-mech techniques. The method of any above claim wherein steps c) and k) comprises the steps of: c1) forming a composite Ti-TiN (29;36) on the bottom and side walls of said first/second stud openings (28; 28′); and, c2) filling the said openings with a tungsten layer (30;38). A stacked semiconductor structure including a base structure comprised of a semiconductor substrate (18/19) having active regions (21) of devices (N1, ...) formed therein and a plurality of polysilicon lines (23-1, ...) formed thereupon after completion of the Master Slice processing steps including a first thick passivating layer (26/27) formed onto said base structure having a set of first metal contact studs (30-1, ...) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, ...); characterized in that: the upper part of said first contact studs defining either gate electrodes of PFET devices and/or interconnection conductors; the surface of said first metal contact studs is coplanar with the surface of said first thick passivating layer; and in that said structure further includes: a thin insulating layer (31) forming the gate dielectric layer of PFET devices and provided with contact openings (32) to expose desired portions of said first contact studs at desired locations; a plurality of polysilicon lands (33-1, ...) formed over said thin insulating layer (31), certain portion thereof define the source, drain and channel region of the body of a PFET device; at least one of said source and drain regions contacting a first metal contact stud through a contact opening (32-1); a second thick passivating layer (35/36) disposed onto the resulting structure having a set of second metal contact studs (38-1, ...) therein contacting at least one of said polysilicon lands (33-1, ...) and/or said first contact studs (30-1, ...); the surface of said second metal contact studs is coplanar with the surface of said second passivating layer. The semiconductor structure of claim 15 further including: a first metal interconnection configuration having metal lands (39-1, ...) electrically contacting at least one of said second metal contact studs (38-1, ...); and a final insulating film (40). The semiconductor structure of claim 15 or 16 wherein certain of said first contact studs are U-shaped to provide strap-like conductors. The semiconductor structure of any above claim 15 to 17 wherein certain of said polysilicon lands or portions thereof are used as interconnection conductors. The semiconductor structure of any above claim wherein said devices (N1, ...) are FETs and said polysilicon lines (23-1, ...) are gate electrodes of said FETs.

Inventors: CEDERBAUM CARL, CHANCLOU ROLAND, COMBES MYRIAM, MONE PATRICK, VALLET VINCENT, CEDERBAUM, CARL, CHANCLOU, ROLAND, COMBES, MYRIAM, MONE, PATRICK, VALLET, VINCENT, Moné, Patrick
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L27, H01L21, H01L23