TRANSDUCER SIGNAL CONDITIONING CIRCUIT

Abstract: The invention provides a transducer signal conditioning circuit for amplifying a transducer output signal (V1, V2), deducting an offset voltage and further amplifying the remaining signal voltage, the circuit comprising a differential in, differential out first amplifying stage (2), a differential summing amplifier second amplifying stage (3), and an offset voltage (preferably a temperature-dependent offset voltage) generating circuit (4). Particularly where the output signal is to be supplied to an A/D converter, the signal conditioning circuit may incorporate or be combined with circuitry for providing the A/D converter with a full scale reference voltage and an offset reference voltage which are ratiometric with the signal voltage.

Description: TRANSDUCER SIGNAL CONDITIONING CIRCUIT This invention relates to transducer signal conditioning circuits which provide amplification of the signal component of the output of a transducer whilst eliminating an offset component. Many transducers including those of plezoreslstive and bridge types generate a small differential voltage output consisting of a signal component and an offset component. The signal component will vary from zero to full scale span with a measured physical variable. The offset component, which does not change with this variable, 1s an error component which 1t is desirable to eliminate. A typical example is a pressure sensor which has a 3v supply and has a small differential output resting upon a 1.5v common mode level. This differential output may, for example, consist of a 30mv offset plus a signal component which varies from 0 to 60mv as the measured pressure varies from 0 to 100 kPa. It is a function of the signal conditioning circuit to amplify the small differential output voltage of a transducer and deduct the offset component from 1t so that the remaining component is the signal component. Also, 1t 1s common to convert the differential output to a single ended output and eliminate any common mode level. A circuit which will amplify a small differential signal and give a single ended output is the well known instrumentation amplifier which is composed of a pair of operational amplifiers in a differential 1n, differential out gain stage with a third operational amplifier configured as a standard differential amplifier with a gain of 1 to convert the differential output to a single ended output. This circuit is ideal for amplifying small differential signals but provides no means of deducting a large offset voltage from the output. A known circuit which will allow an offset compensation voltage to be combined with another voltage 1s the summing amplifier. This circuit can have two or more input resistors at the summing junction and will sum the voltages on these resistors together. However, it will not provide a difference function. It has been found however, that a differential amplifier and a summing amplifier can be combined advantageously into one circuit to create a differential summing amplifier using only one operational amplifier. Moreover, this circuit can be used Instead of the differential amplifier in the second stage of an instrumentation amplifier where it will combine the amplified differential output from the first stage, deduct a voltage from the result, and give a single ended output. According to the present Invention there is provided a transducer signal conditioning circuit for amplifying a transducer output signal, deducting an offset voltage and further amplifying the remaining signal voltage, the circuit comprising a differential in, differential out first amplifying stage, a differential summing amplifier second amplifying stage and an offset compensation voltage generating circuit, the first amplifying stage being arranged to receive the transducer output signal as its differential input and having its differential output connected to the differential input of the second stage, and the offset compensation voltage generating circuit being connected to apply such offset compensation voltage to a summing junction at one side of the differential input of the second stage. Preferably the second amplifying stage comprises an operational amplifier having positive and negative input terminals each connected by a respective input resistor to a respective side of the differential output of the first amplifying stage, and an output terminal connected by a resistive feedback connection to the negative input terminal, the output of the offset compensation voltage generating circuit being connected by a further input resistor to the negative input terminal of the second amplifying stage and the positive input terminal thereof being connected to ground by a resistive connection; and preferably an adjustable gain boosting resistor is also provided. To that end, preferably, the resistive feedback connection of the second amplifying stage comprises two resistors in series with a first node between them and the resistive connection between the positive input terminal and ground also comprises two resistors, with a second node between them, and the gain boosting resistor is connected between the first and second nodes. It will often be required that the offset compensation voltage 1s temperature-dependent, and accordingly, preferably, the offset compensation voltage generating circuit comprises a first operational amplifier in inverting mode with resistive feedback from its output to Its negative input, means for applying a selected false ground voltage to the amplifier positive input, and means including the said temperature- sensitive device for applying a temperature-dependent voltage to the negative input of the operational amplifier through an input resistor. Also, preferably, the offset compensation voltage generating circuit comprises a further operational amplifier 1n inverting mode with resistive feedback from Its output to its negative input, the output of the first operational amplifier being applied through an Input resistor to the negative input of the further operational amplifier and there being connected between the negative input and the output of the further operational amplifier the said resistive divider to opposite ends of which, accordingly, temperature-dependent voltages of opposite slope are applied. Particularly when the output signal voltage from a signal conditioning circuit according to the invention 1s to be supplied to an A/D converter, the signal conditioning circuit may advantageously incorporate or be combined with circuitry for providing the A/D converter with a full-scale or half-full-scale reference voltage, and perhaps also an offset reference voltage, which is ratiometric with the signal voltage. The invention will be disclosed and described more fully below with reference to the accompanying drawings, in which:- Figure 1 is a circuit diagram of a first embodiment of a transducer signal conditioning circuit; Figure 2 is a circuit diagram showing a modification of the circuit shown in Figure 1; Figure 3 is a circuit diagram of a temperature-dependent offset compensation voltage generating circuit which may be incorporated in the circuit shown in Figure 1 or Figure 2; Figure 4 1s a circuit diagram of another temperature- dependent offset compensation voltage generating circuit which may be incorporated in the circuit shown in Figure 1 or Figure 2; Figure 5 is a circuit diagram of signal conditioning circuitry interposed between a transducer and an A/D converter; and Figure 6 is a circuit diagram similar to that of Figure 5 but incorporating additional circuitry. Referring to Figure 1, a transducer 1 is represented as four resistors (RG1 to RG4) in a heatstone bridge configuration. A signal conditioning circuit for the transducer 1 comprises a differential in, differential out amplifier gain stage 2 with a differential summing amplifier 3 to generate the output. Also provided is an offset compensation voltage generating circuit 4. The differential in, differential out gain stage 2 comprises operational amplifiers Ul and U2 whose non-inverting <+) inputs are connected to the positive and negative outputs respectively of the transducer 1. The outputs of amplifiers Ul and U2 are connected together via a resistive ladder comprising resistors Rl , R2 and R3 in series. The node between resistors Rl and R2 is connected to the inverting (-) input of amplifier Ul , and the node between resistors R2 and R3 is connected to the inverting (-) input of amplifier U2. The differential summing amplifier 3 comprises a resistive divider R4, R9 connecting the output of amplifier Ul to ground (GND) , and an operational amplifier U3 to the non-inverting (+) input of which the node between resistors R4 and R9 is connected. The output of amplifier U3 is connected via a feedback resistor R10 to its inverting (-) input, and input resistors R5 and R6 connect the output of amplifier U2 and the output of offset compensation voltage generating circuit 4, respectively, to the inverting (-) input of amplifier U3. The offset compensation voltage generating circuit 4 comprises, in this example, a resistive voltage divider R7, R8 connected between a transducer supply voltage Vss and ground (GND), and a buffering operational amplifier U4 of which the output V3 is the offset compensation voltage. A particular numerical example of the circuit shown in Figure 1 operates as follows: Transducer 1 has a 3v supply (Vss ■ = 3v) and generates a differential output (VI - V2) which is composed of a 30mv offset voltage and a 60mv full scale span voltage, giving a total of up to 90mv transducer output. Differential in, differential out gain stage 2 has resistor ratios R1/R2 - 10 and R3 - Rl which, according to the known formula: GAIN -= 1 + 2(R1/R2), gives a differential gain of 21. Thus the differential full scale output (V4 - V5) of the gain stage 2 will be 1.89v, of which 1.26v 1s the full scale span and 0.63v 1s offset. It 1s desired to deduct this offset from the output, leaving only the signal voltage. This is done by setting R5 ■ = R6 and adjusting the resistor ratio R7/R8 so that the offset compensation voltage V3 provided by the circuit 4 is also 0.63v. Suppose, then, that it has been decided that a full scale span voltage of 2.52v is required for the output (V0) of the amplifier U3 and thus a gain of 2 1s required for the differential summing amplifier 3. Resistor ratios are chosen using the formulae: R10 = G . R5 (a) R4 = C(G + D/G] . R9 (b) where G is the gain. In this case, where the required gain is 2, this gives R10/R5 = 2, and R4/R9 - 1.5. The circuit shown in Figure 1 has a practical disadvantage, in that, as between different but nominally Identical specimens of the transducer 1, the full scale span voltage may vary considerably, perhaps by a factor of two. For example, a transducer type with a nominal 60mv full scale span voltage may in fact vary from 45mv to 90mv full scale span. Thus it would be desirable to vary the signal gain of the signal conditioning circuitry by at least a factor of two so that the complete circuit always has the same full scale output. The usual way of doing this would be to calibrate the circuit by adjusting a variable resistor whilst the circuit is powered up. With the circuit shown in Figure 1 it is not possible to adjust the gain of the amplifier 3 using a single variable resistor, because the values of all the resistors are interrelated as shown by the formulae (a) and <b) above. However, with the modified circuit shown in Figure 2, adjustment of the gain can be achieved by adjustment of a single resistor. The modified circuit shown in Figure 2 is identical with that shown in Figure 1 except that the resistors R9 and RIO shown in Figure 1 are replaced in Figure 2 by two pairs of series connected resistors R9A and R9B and, respectively, R10A and R10B, and a resistor Rll is connected between the node of the resistors R9A and R9B and the node between the resistors R10A and R10B. As before, the transducer 1 is supplied with the voltage Vss of 3v, but let it be supposed in this instance that the differential output (VI - V2) of the transducer 1 comprises an offset voltage of up to 30mv offset and a full scale span voltage which may be as low as 45mv or as high as 90mv. Differential in, differential out gain stage 2 has a gain of 21, as described with reference to Figure 1. Thus the differential output (V4 - V5) will consist of a signal voltage with a full scale span of between 0.945v and 1.890v, plus an offset component of up to 0.63v. It is required to deduct this offset from the output leaving only the signal voltage. This is done, as described with reference to Figure 1, by setting R5 = R6 and adjusting resistor ratio R7/R8 so that the offset compensation voltage V3 is the same as the offset component. If a full scale span voltage of 2.5v is required from the circuit as its output voltage Vo, this implies a signal gain between approximately 1.32 and 2.64 from output stage 3. The resistor Rll 1s a gain boosting resistor which boosts the gain that the basic circuit would have 1f the gain boosting resistor Rll were omitted. Without the gain boosting resistor Rll, the circuit would be as shown in Figure 1 except for R9 being replaced by R9A and R9B, and RIO being replaced by R10A and R10B. Thus the formulae (a) and (b) stated earlier can be used to calculate resistor ratios as required. If the basic circuit (with Rll omitted) is chosen to have a gain of 1 then the gain boosting resistor Rll can be used to boost the gain to between 1.32 and 2.64 as required. The formulae (a) and (b) give the resistor ratios for a basic circuit gain of 1 as: R10A + R10B = R5 R4 = 2 . (R9A + R9B) The required value of the gain boosting resistor Rll 1s then determined by the resistor ratios R10A/R10B and R9A/R9B, but for the particular case where R9A ■ * R9B > R10A = R10B ■ = 10k ohm, a 50k ohm variable resistor provided as the resistor Rll will cover the gain adjustability requirement over the range between 1.32 to 2.64. It will be understood that the differential summing amplifier 3 as described above 1s similar to the known summing amplifier circuit and consequently may be subjected to the same known variations, such as the use of unequal input resistors to the summing junction and/or more than two input resistors to the summing junction, without affecting Its basic function. A typical example would be to split the offset compensation voltage V3 into several components and feed them into the summing junction using several resistors instead of feeding it all through the single resistor R6. It should also be understood that although for the sake of simplicity it has been assumed in the foregoing description that the offset in the circuit arises in the transducer, in fact an offset voltage can also arise due to operational amplifier offsets and resistor tolerances. These are, however, indistinguishable from transducer offset and the offset compensation voltage V3 can be used to compensate for all such offsets together. In the foregoing description it has been assumed that the offset voltage which is to be compensated is a constant voltage, and the compensation voltage generating circuits in Figures 1 and 2 are accordingly designed to provide a constant output voltage. In practice, however, such offset voltages are often temperature-dependent and there is therefore a requirement to provide an offset compensation voltage generating circuit which will supply an offset compensation voltage which varies appropriately with temperature. Such a circuit is shown in Figure 3, which comprises a temperature-dependent voltage generating circuit 5, a slope amplifying circuit 6, a false-ground voltage generating circuit 7, a resistive divider 8, a slope inverting circuit 9 and a slope selection circuit 10. The temperature-dependent voltage generating circuit 5 comprises resistors R12 and R13 in series between a regulated supply voltage Vr and ground (GND), with the node therebetween connected to the non-Inverting (+) input to an operational amplifier U5. The output of operational amplifier U5 is connected by a temperature dependent device, in this case a diode Dl , to the inverting (-) input of the amplifier, and the inverting (-) input is also connected via a resistor R14 to ground (GND). The operational amplifier U5 output provides a temperature- dependent output voltage V6, which is applied to the slope amplifying circuit 6. The slope amplifying circuit 6 comprises an operational amplifier U6 with its output connected via a resistor R15 to its inverting (-) input, to which the voltage V6 is applied via a resistor R16. The non-inverting (+) input of operational amplifier U6 has applied to it an output voltage V7 from the false ground voltage generating circuit 7, which comprises resistors R17 and R18 connected in series between the regulated supply voltage Vr and ground with the output voltage V7 appearing at the node of resistors R17 and R18. The operational amplifier U6 provides an output voltage V8 which, being derived from the temperature-dependent voltage V6, 1s also temperature-dependent. The voltage V8 1s applied to one terminal of a selector switch SI comprised by the slope selection circuit 10, and also to the slope inverting circuit 9. The slope Inverting circuit 9 comprises an operational amplifier U7 in inverting amplifier mode with Its output connected via a resistor R19 to its Inverting (-) input, to which the voltage V8 1s applied via a resistor R20. The non-inverting (+) input of the amplifier U7 is connected to the false ground voltage V7, and Its output provides a temperature-dependent voltage V9 which is applied to a second terminal of the switch SI. By means of switch SI, either the input voltage V8 or the output voltage V9 of slope Inverting circuit 9 is selected for application to the resistive divider 8, which comprises resistors R21 and R22 connected in series between the switch SI and ground; and the required temperature-dependent offset compensation voltage is a voltage VI0 which can be taken from the node of resistors R21 and R22. Thus the circuit shown in Figure 3 may replace the circuit 4 of Figure 1 or Figure 2 so that the temperature-dependent offset compensation voltage V10, instead of the constant voltage V3, is applied via the resistor R6 to the amplifier U3 of Figure 1 or Figure 2. The circuit shown in Figure 3 operates as follows:- Suppose the temperature-dependent offset compensation voltage V10 is required to have a value of 0.5V at 20°C and a linear slope, for the sake of example, of either +4mV/°C or -4mV/°C. To achieve this result, the temperature-dependent voltage generating circuit 5 is configured as a constant current circuit through diode Dl , with a voltage across the diode equal to 0.5V at 20°C and with a temperature-dependent slope of -2mV/°C. The resistor ratio R12:R13 is adjusted to give 0.5V at the non-inverting ( + ) input of operational amplifier U5 so that the total output voltage V6 1s IV at 20°C, with a slope of -2mV/°C. Resistors R17 and R18 in the false ground voltage generating circuit 7 are set so that the false ground voltage V7 is also IV. Thus, at 20°C, both inputs to the slope amplifying circuit 6 are at IV and its output V8 will also be IV irrespective of the values of resistors R15 and R16. Similarly, because both input voltages V7 and V8 of slope inverting circuit 9 are at IV at 20°C Its output V9 will also be IV at 20°C. Hence, 1t can be seen that whatever connection is made in the slope selection circuit 10, by means of the switch SI, the voltage at the top of resistive divider 8, whether it be V8 or V9, will always be IV at 20°C. Thus the offset compensation voltage VI0 requirement of 0.5V at 20°C is met by setting resistive divider 8 so that its output voltage is half its input voltage, that is with resistor ratio R21:R22 equal to 1. The resistor ratio in the resistive divider 8 also means that, 1n order to achieve a slope of ±4mV/*C for the offset compensation voltage V10, as required, a slope of ±8mV/°C must be applied to the top of resistive divider 8. In order for the slope amplifying circuit 6 to convert its input voltage slope of -2mV/°C to an output voltage slope of 8mV/°C, a slope gain of -4 is required. This is achieved by setting the resistor ratio R15:R16 to 4. In order to obtain access to a voltage slope of -8mV/"C instead of +8mV/ β C, a further slope gain of -1 is required. This is done in the slope inverting circuit 9 by setting the resistor ratio R19:R20 to 1. Voltage V8 now has a slope of +8mV/°C and voltage V9 has a slope of -8mV/°C and either of these can be applied to the top of resistive divider 8 using switch SI of the slope selecting circuit 10. This gives the required slopes of offset compensation voltage V10, of either +4mV/°C or -4mV/°C respectively. The circuit illustrated in Figure 3 has a disadvantage, in terms of practical circuit production. It is likely that such a circuit would in practice (for example, replacing the circuit 4 in Figure 1 or 2) be part of a larger signal conditioning circuit constructed as a silicon chip or a thick film hybrid, and in those circumstances it would be usual to laser-trim resistors to achieve a reduction of overall circuit offset in a continuous fashion. To interrupt laser trimming part way through the process, in order to adjust the switch SI or otherwise change connections, would slow down the production process. This disadvantage of the circuit shown In Figure 3 is avoided in the modified circuit, shown in Figure 4, which is Identical to that shown In Figure 3 except that its slope selection circuit 10 is of a form which facilitates the use of laser trimming in production. Since other parts of the circuit shown in Figure 4 are the same as those already described with reference to Figure 3, 1t will only be necessary to describe the slope selection circuit 10 of Figure 4. This comprises a resistive divider R23 and R24 connected between the input (V8) and the output (V9) of the slope inverting circuit 9. The node between resistors R23 and R24 is connected to the non-inverting (+) input of an operational amplifier U8. The output of operational amplifier U8, which provides an output voltage Vll, 1s connected to the inverting (-) input of the amplifier and also to the top of the resistive divider 8. Suppose, now, that the circuit shown in Figure 4 is required to provide, as its output voltage VI0, a temperature-dependent offset compensation voltage with a value of 0.5V at 20"C and a linear slope of some value between +3mV/°C and -3mV/°C. The temperature-dependent voltage generating circuit 5 gives an output voltage V6 of IV at 20°C with a linear slope of -2mV/°C, as described with reference to Figure 3. The false ground voltage V7 is also set to IV, as already described, so that at 20°C the output V8 of the slope amplifying circuit 6 will be IV, as also will be the output V9 of the slope inverting circuit 9. At 20°C, therefore, both ends of the resistive divider R23 and R24 are at a potential of IV, and since the node between these resistors has no current flowing in it the input to operational amplifier U8, and also its output voltage VI1 applied to the top of resistive divider 8, will be IV. As described with reference to Figure 3, the offset compensation voltage VI0 requirement of 0.5V at 20°C is met by setting the resistor ratio R21:R22, in resistive divider 8, equal to 1. The requirement that the output voltage V10 should have a temperature-dependent slope of some value between +3mV/ β C and -3mV/°C then means that the voltage VI1 must have a slope of corresponding value between +6mV/ β C and -6mV/°C. If slope amplifying circuit 6 is set with a slope gain of -4, I.e. the resistor ratio R15.*R16 is 4, as previously described, then the -2mV/°C slope of its input voltage V6 will be converted to a slope of +8mV/°C for its output voltage V8. This gives access to a slope of +8mV/°C at one end of resistive divider R23 and R24 in the slope selection circuit 10. If, as already described, the slope inverting circuit 9 is chosen to have a slope gain of -1, this gives access, at the other end of resistive divider R23 and R24, to a slope of -8mV/°C provided by the voltage V9. The required slope for the voltage Vll, at some value between +6mV/°C and -6mV/°C, is then simply achieved by varying the resistor ratio R23: R24, which can be done by laser trimming of one of these resistors as part of the overall laser trimming of the complete circuit. In the slope selector circuit 10, the operational amplifier U8 acts as a voltage-follower or buffer amplifier, which may be omitted if the resistive divider 8 does not draw very much current. In that case, the resistive divider would be directly connected to the node between resistors R23 and R24. Numerous variations of the circuits shown in Figures 3 and 4 are possible. It is therefore considered useful at this point to restate the general underlying principles. Circuits of this general type, for generating a temperature-dependent offset compensation voltage for a transducer, are often calibrated by first setting an offset compensation voltage to cancel out the transducer offset at room temperature, say 20 β C, and then, after the temperature has been raised so that the transducer offset changes and 1s no longer cancelled out by the offset compensation voltage, changing the gain in the offset compensation voltage generating circuit so that the offset compensation voltage again cancels out the transducer offset at the higher temperature. However, It will be found on return to room temperature that the offset compensation voltage no longer cancels out the transducer offset voltage, unless the gain at room temperature has been fixed independently of the gain at high temperature. This requirement to fix the gain at room temperature independently of the gain at high temperature 1s met, according to the Invention, by using an operational amplifier 1n inverting amplifier mode with a false ground voltage on the positive input and a temperature-dependent voltage on the negative Input, making the false ground voltage equal to the temperature-dependent voltage at the desired room temperature, and hence fixing the output voltage at this temperature as required. Hence the minimum requirements for this type of circuit are: means for providing a temperature-dependent voltage, means for providing a false ground voltage, at least one inverting amplifier with the false ground voltage applied to its positive Input and the temperature-dependent voltage applied to Its negative input, and a resistive divider to develop the offset compensation voltage output. It will be understood that although a circuit in accordance with Figure 3 or Figure 4 may be made on a printed circuit board or on a thick film hybrid, most if not all of it may advantageously be placed on a single piece of silicon, for example in combination with the circuit shown in Figure 1 or Figure 2 as part of a larger sensor signal conditioning circuit which might also include parts providing not only sensor output amplification but also span compensation and temperature- dependence for the span compensation such as is described and claimed in our co-pending UK Patent Application No. 8925577.2. In that latter case, the temperature-dependent voltage required to provide the temperature-dependent component of the span compensation may conveniently be derived from a suitable point in the circuit providing the temperature-dependent offset compensation. It will be appreciated that although the circuits shown in Figures 3 and 4 have been described above only as used for providing a transducer offset compensation voltage, such circuits are of wider application and may also be employed for other purposes and applications which require the provision of a temperature-dependent voltage having a selected value at one temperature and an Independently selected slope or rate of variation with temperature. A signal conditioning circuit as described above with reference to Figure 1 or Figure 2, or modified to incorporate the temperature-dependent offset compensation provided by a circuit as shown in Figure 3 or Figure 4 and possibly also to provide temperature span compensation for the transducer as referred to above, may often be mounted together with the transducer as a unit, contained within a plastic casing, for example, which has only three electrical terminals : supply voltage, ground, and signal output voltage. This output is ideal if it is required to activate a moving coil meter, for example. One simply connects the output across the meter - no serious electronics ability is required. Nowadays, there is also a requirement to interface these signal conditioning circuits with digital electronics so that the amplified output of the strain gauge or other transducer may be taken directly into a microprocessor or microcomputer. This is done by feeding the output of the signal conditioning circuit into an analogue to digital (A/D) converter which will then digitize the information and supply it to the microprocessor system. Unfortunately, interfacing between a signal conditioning circuit and an A/D converter is not easy for engineers who are not experienced in analogue electronics because an A/D converter often requires an offset voltage input and a reference voltage input as well as the input from the signal conditioning circuit. Extra analogue circuitry is used to supply these voltages which may involve the use of a voltage reference and two operational amplifiers in buffer mode. Additionally, it 1s likely that this extra circuitry will require a separate power supply since the standard T.T.L. 5V power supply can be electrically very noisy, as well as being of too low a voltage to allow the usual circuit configurations to function properly. A further disadvantage of this circuitry 1s that the output of a voltage reference drifts with time and temperature. The output of the signal conditioning circuit 1s ratiometric with a reference voltage inside the chip. This means that 1f this reference voltage should drift by, say 0.1% then the output will drift by 0.1%. However, the voltage outputs of the operational amplifiers are ratiometric with the external voltage reference. Thus the accuracy of the whole system 1s determined by the relative drifts of the Internal voltage reference 1n the signal conditioning circuit and the external reference in the operational amplifier circuit. From a systems engineer's point of view there are further problems which he may not even know about, such as settling time requirements on operational amplifier outputs, and their current output capability at low voltages. What a systems engineer needs is the ability to get a number into his microprocessor which is related to the transducer output and which he has a high level of confidence is accurate. He requires a signal conditioning circuit which connects directly to an A/D converter and requires no extra interface circuitry and which preferably uses the same 5V T.T.L. standard supply as the rest of his digital circuitry. Moreover, what he requires is a range of signal conditioning chips for all the other system inputs which may have to be measured, such as temperature, humidity, light, rotational speed, voltage and current, to name but a few. These chips should all run off the same voltage and connect to the A/D converter in the same manner. According to a further feature of the invention, therefore, there is provided a single chip signal conditioning circuit which incorporates circuitry as described above with reference to Figures 1 to 4 and which operates between ground and a single positive voltage supply, and which supplies not only a signal output voltage but also a full scale reference voltage output and, if desired, an offset voltage for application to an A/D converter to which the signal output voltage may be supplied. Figure 5 shows a simple form of such a combined circuit with its outputs connected to an A/D converter, and with an associated transducer. As shown in Figure 5, a transducer 1 (which may be the transducer 1 of Figure 1 or Figure 2) is connected to a signal conditioning chip 11 which comprises a signal processing circuit 12 (which may be the signal conditioning circuit shown in Figure 1 or Figure 2) and a voltage reference generating circuit 13. The outputs of the signal conditioning chip 11 are connected to an A/D converter 14. The power supply lines of the transducer 1 come from the signal processing circuit 12. The outputs of the transducer 1 are connected to the inputs of signal processing circuit 12. The power supply lines of signal processing circuit 12 are connected between a supply voltage Vss and ground GND. The output Vout of signal processing circuit 12 is connected to the V+ or Vin voltage input of the A/D converter 14. The voltage reference generating circuit 13 comprises an operational amplifier U9, in this case connected in buffer mode, with its output connected to its inverting (-) input, and a voltage that is ratiometric with the supply voltage Vss, in this case derived from the node between resistors R25 and R26, connected to its non-inverting (+) input. Resistors R25 and R26 are connected in series between the supply voltage Vss and ground GND. The positive supply pin of operational amplifier U9 is connected to the supply voltage Vss and its negative supply pin is connected to ground GND. The output Vref of voltage reference generating circuit 13 is connected to the voltage reference input of A/D converter 14. The supply pin of A/D converter 14 is connected to the voltage supply Vss and the ground pin 1s connected to ground GND. The digital inputs and outputs of A/D converter 14, which are connected to a microprocessor system, are not shown. The circuit just described is a relatively simple form of the circuit and conditions may require that a practical circuit has certain enhancements. Changing supply voltages and electrical noise on the supply line reduce the accuracy of the circuit. This problem can be reduced by incorporating a voltage regulator into the circuit. For battery operation 1t may be desirable to power down the signal conditioning circuit when not in use to prolong battery life. This can be done by replacing a standard voltage regulator with one which has a power down function. It is not easy to supply a voltage reference output from a signal conditioning circuit with a 5V supply using the standard circuitry described in Figure 5. A 5V T.T.L. supply may drop as low as 4.5V. If a full scale output voltage of 3V is required then the reference voltage output Vref would be set to 3V. Since the operational amplifier U9 in the voltage reference generating circuit 13 has a supply voltage of perhaps only 4.5V it would be unable to supply much current under these circumstances, whereas the voltage reference input on some A/D converters will sink several A under these conditions. If a voltage regulator is incorporated in the circuit the amplifier has an even lower supply voltage and this problem is even worse. The problem is overcome by supplying most or all of the reference current with a pull-up circuit (usually a resistor) and then allowing the operational amplifier to determine the voltage by sourcing or sinking the excess current. It will be understood that the amplified signal voltage output Vout does not require a pull-up resistor since there is virtually no current sunk by the A/D converter voltage input. The signal conditioning chip 11 shown in Figure 5 only supplies a reference voltage output to the A/D converter. A more sophisticated circuit would also supply an offset voltage to the A/D converter allowing the signal conditioning chip to "tell" the A/D converter not only the full scale of the output voltage but also its offset. Some A/D converters require not a "reference voltage" input but a "half reference voltage" input. For example, an A/D converter of this type, when supplied with a 1.5V reference, will set 3V as full scale. In order to accommodate this it is desirable to have a pin on the signal conditioning chip which when, for example, left open circuit will cause the reference output to supply the full scale reference voltage, whereas if the pin is tied to ground it will cause the reference output to supply a half full scale reference voltage. It may be desirable to bring the regulated voltage out to a pin on the chip to allow external analogue circuitry to make use of the regulated voltage supply rather than having its own extra voltage regulator. Figure 6 shows combined circuitry similar to that of Figure 5 but Incorporating the above-enumerated enhancements. As shown in Figure 6, a transducer 1A which may for example, be a thermocouple, is connected to the signal conditioning chip 11 which comprises signal processing circuit 12, voltage reference generating circuit 13 with, in this instance, an associated pull-up circuit 15, a voltage regulator 16, and an offset voltage generating circuit 17. The outputs of the signal conditioning chip 11 are connected to the A/D converter 14. The voltage regulator 16 is connected between the voltage supply Vss and ground GND. The output of voltage regulator 16 is the regulated voltage Vreg. A power down connection is taken from voltage regulator 16 to an external pin PI of signal conditioning chip 11. This will serve to inhibit the operation of the voltage regulator under certain conditions (normally when raised close to the supply voltage). The outputs of thermocouple 1A are connected to the inputs of signal processing circuit 12. The power supply lines of signal processing circuit 12 are connected between the regulated voltage Vreg and ground GND. The output Vout of signal processing circuit 12 is connected to the V+ or Vin voltage input of A/D converter 14. The voltage reference generating circuit 13 comprises an operational amplifier U9, in this case connected in non-inverting amplifier mode, with Its output connected to ground GND via series resistors R27 and R28. The node between resistors R27 and R28 is connected to the inverting (-) input of amplifier U9, and its non-Inverting (+) input is connected to the node between resistors R25 and R26, which are connected in series between the regulated voltage supply Vreg and ground GND. The non-inverting (+) input of amplifier U9 1s connected to an external pin P2 via a resistor R29. The value of resistor R29 1s chosen so that if it is placed in parallel with resistor R26, by externally connecting pin P2 to ground, the voltage on the non-Inverting (+ ) input of the operational amplifier U9 will be halved. This will cause the reference voltage Vref to be halved. The positive supply pin of operational amplifier U9 is connected to the regulated voltage supply Vreg and its negative supply pin is connected to ground GND. The offset voltage generating circuit 17 comprises an operational amplifier U10, in this case connected in buffer mode with its output connected to its inverting (-) input, and a voltage that is ratiometric with regulated voltage Vreg, in this case derived from the node between resistors R30 and R31 , connected to its non-inverting (+) input. Resistors R30 and R31 are connected in series between the regulated voltage supply Vreg and ground GND. The positive supply pin of amplifier U10 is connected to the regulated voltage Vreg and its negative supply pin is connected to ground GND. The output Voff of the offset voltage generating circuit 17 is connected to the offset voltage or V- input of A/D converter 14. The supply pin of the A/D converter 14 is connected to the voltage supply Vss and the ground pin is connected to ground GND. The digital outputs of the A/D converter 14, which are connected to a microprocessor system, are not shown. It should be noted that the means by which output voltage Vout is obtained from the sensor 1 or 1A via signal processing circuit 12 is not a key feature of the circuits shown in Figures 5 and 6: the particular arrangements shown are just illustrations. It is expected that with some sensors it will be convenient to have the sensing element soldered to, or part of, the signal conditioning chip 11, whereas with others the sensor will be physically remote from the chip but electrically connected to it. The voltages on the non-inverting (+) inputs of operational amplifiers U9 and U10 are shown as derived from the supply voltage Vss or the regulated voltage Vreg, but could just as easily be derived from some other relatively stable voltage in the circuit. Other features or subsidiary outputs could be added to the circuit without altering its basic purpose. A temperature dependent voltage output would be a very minor modification in some pressure sensor circuits, for example. Similarly, it may be convenient to bring one or more passive components or diodes off the chip. This would not be regarded as fundamentally altering the nature of the chip, particularly if no new circuit nodes are created off chip. For some applications it may be desirable to bring the A/D converter on to the chip. The use of the word "chip" implies "component". Thus it might be a thick film hybrid, small printed circuit board, or piece of silicon and it would be a single component used in a circuit with other components and mounted on the same circuit board or substrate as them. Indeed, the day may come when silicon replaces printed circuit boards as the usual substrate. One then has a situation where the signal conditioning chip can be selected as a standard cell in the design along with the microprocessor and the resistor. All the designer has to do 1s to connect the components together on the silicon. It is understood that if a designer designs a signal processing circuit from smaller components whether in silicon or on a printed circuit board then that circuit is not a component itself.

Claims: CLAIMS 1. A transducer signal conditioning circuit for amplifying a transducer output signal, deducting an offset voltage and further amplifying the remaining signal voltage, the circuit comprising a differential in, differential out first amplifying stage, a differential summing amplifier second amplifying stage and an offset compensation voltage generating circuit, the first amplifying stage being arranged to receive the transducer output signal as its differential input and having its differential output connected to the differential input of the second stage, and the offset compensation voltage generating circuit being connected to apply such offset compensation voltage to a summing junction at one side of the differential input of the second stage. 2. A circuit as claimed in Claim 1, wherein the second amplifying stage comprises an operational amplifier having positive and negative input terminals each connected by a respective input resistor to a respective side of the differential output of the first amplifying stage, and an output terminal connected by a resistive feedback connection to the negative input terminal, the output of the offset compensation voltage generating circuit being connected by a further input resistor to the negative input terminal of the second amplifying stage and the positive input terminal thereof being connected to ground by a resistive connection. 3. A circuit as claimed in Claim 1 or Claim 2, wherein the second amplifying stage incorporates a gain boosting resistor. 4. A circuit as claimed in Claim 2 and Claim 3, wherein the resistive feedback connection of the second amplifying stage comprises two resistors in series with a first node between them and the resistive connection between the positive input terminal and ground also comprises two resistors, with a second node between them, and the gain boosting resistor is connected between the first and second nodes. 5. A circuit as claimed in Claim 3 or Claim 4, wherein the gain boosting resistor is adjustable. 6. A circuit as claimed in any of Claims 1 to 5, wherein the offset compensation voltage generating circuit 1s designed to provide a temperature-dependent offset compensation voltage and comprises a resistive divider having at least one end connected to be supplied with a temperature-dependent voltage derived from a temperature-sensitive device such as a semiconductor diode via a sequence of one or more operational amplifiers. 7. A circuit as claimed in Claim 6, wherein the offset compensation voltage generating circuit comprises a first operational amplifier in inverting mode with resistive feedback from its output to its negative input, means for applying a selected false ground voltage to the amplifier positive input, and means Including the said temperature-sensitive device for applying a temperature-dependent voltage to the negative input of the operational amplifier through an input resistor. 8. A circuit as claimed in Claim 7, wherein the offset compensation voltage generating circuit comprises a further operational amplifier 1n inverting mode with resistive feedback from its output to its negative input, the output of the first operational amplifier being applied through an input resistor to the negative input of the further operational amplifier and there being connected between the negative input and the output of the further operational amplifier the said resistive divider to opposite ends of which, accordingly, temperature-dependent voltages of opposite slope are applied. 9. A circuit as claimed in any of Claims 1 to 8 and providing, in addition to the said amplified signal voltage, a full scale reference voltage which is ratiometric with the signal voltage. 10. A circuit as claimed in Claim 9 and incorporating a voltage regulator. 11. A circuit as claimed in Claim 9 or Claim 10 wherein the full scale reference voltage output is generated by an operational amplifier in buffer mode or non-inverting amplifier mode. 12. A circuit as claimed in any of Claims 9 to 11, wherein most or all of the current supplied by the reference voltage output comes from a pull-up circuit (usually a resistor). 13. A circuit as claimed in any of Claims 9 to 12 and having an offset voltage output generated by an operational amplifier in buffer mode or non-inverting amplifier mode. 14. A circuit as claimed in any of Claims 9 to 13 wherein the offset voltage output or the reference voltage output are ratiometric with a relatively stable voltage in the circuit. 15. A circuit as claimed in any of Claims 9 to 14 which has a power down feature. 16. A circuit as claimed in any of Claims 9 to 15 which supplies a regulated voltage output. 17. A circuit as claimed in any of Claims 9 to 16 which can supply a half full scale voltage reference. 18. A transducer signal conditioning circuit substantially as described herein with reference to any of the accompanying drawings.

Inventors: BINNS JOHN PHILIP LINCOLN, BINNS, JOHN, PHILIP, LINCOLN
Applicants: NAT RES DEV, NATIONAL RESEARCH DEVELOPMENT CORPORATION
Application year: 1990
Main classification: H03F3
IPC codes: H03F1, H03F3