Process for obtaining an N-channel single polysilicon level EPROM cell

Abstract: The process provides for the simultaneous N+ type implantation of areas (7, 8, 9) of a semiconductor substrate of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8), defining a channel region (4). After oxide growth (11, 12) there is executed the deposition and the definition of a polysilicon layer (10), one region of which constitutes a floating gate above the control gate (9) and the channel region (4) and partially superimposed over the regions of source (7) and drain (8).

Description: The present invention relates to a process for obtaining an N-channel single polysilicon level EPROM cell. It is known that for some applications it is preferable to use single polysilicon level EPROM cells (that is, with the floating gate coupled capacitively to doped source and drain regions of a semiconductor substrate and to a control gate also constituted by a doped region of the same substrate) rather than the more traditional double polysilicon level EPROM cells. An N-channel single polysilicon level EPROM cell is disclosed in Technical Digest of the IEDM 1988, 11-14 December 1988, San Francisco, pp. 60-63. The custom is also known of providing simultaneously with the cells of an EPROM memory matrix the transistors of an external circuitry. When very small transistors are needed, these can be manufactured with either the LDD (light doped drain) or the DDD (double doped drain) technology, that is, with the formation, on both sides of the floating gate, of oxide spacers superimposed over lightly doped substrate regions adjacent to highly doped source and drain regions. An LDD technology is disclosed in IEEE Transactions of Electron Devices, vol.36, n.6, June 1989, pp. 1125-1132. In this way it is possible to reduce the problems of aging of traditional transistors, while still maintaining the electrical continuity necessary for the transistor's correct operation. This technology is not applicable to EPROM cells, because the presence of such lightly doped regions would make the writing process extremely slow. For a normally-fast writing process it is indeed necessary for the EPROM cells to have their floating gate partially superimposed over highly doped source and drain regions. In order to accomplish a matrix of traditional single polysilicon level EPROM cells simultaneously with LDD- or DDD-type external circuit transistors it is, on the other hand, necessary to use an additional mask with a consequent increase in time and costs. Japanese Journal of Applied Physics; supplements (18th International Conference on Solid State Devices and Materials Tokyo 1986), 20-22 August 1986, pp. 323-326, teaches that D-type ion implantation can be used for CG layer formation. The object of the present invention is to provide a process for obtaining a single polysilicon level EPROM cell with the floating gate partially superimposed over double doped source and drain regions which, within the scope of a process for obtaining LDD- or DDD-type transistors, does not require the use of an additional mask. According to the invention such object is attained by means of a process for obtaining an N-channel single polysilicon level EPROM cell simultaneously with an LDD- or DDD-type transistor, as recited in claim 1. In this way it is possible to obtain in an integrated form and without an additional mask an N-channel single polysilicon level EPROM cell with its floating gate partially superimposed over highly doped source and drain regions, and thus capable of guaranteeing a very good performance in terms of writing speed and current absorption, simultaneously with LDD- or DDD-type external circuit transistors, that is, with lightly doped regions under oxide spacers located at the sides of the floating gate. This is obtained thanks to the fact that the high dope implantation utilized for the control gate is also used for the source and drain regions and thus it simultaneously defines the cell channel. The features of the present invention shall be made more evident by an embodiment illustrated as a non-limiting example in the enclosed drawings, wherein: Fig. 1 illustrates a single polysilicon level EPROM cell obtained with the process according to the invention; Fig. 2. is a cross-sectional view taken along the line II-II of Fig. 1, completed with a similar cross-sectional view of an external circuti transistor; Fig. 3 is a cross-sectional view taken along the line III-III of Fig. 1; Fig.s 4 to 7 show steps of a process for accomplishing a single polysilicon level EPROM cell and an external circuit transistor, seen in a cross-sectional view similar to that of Fig. 2; Fig.s 8 and 9 show steps of a process similar to those of Fig.s 6 and 7, seen in a cross-sectional view similar possible to that of Fig. 3. With reference to the above figures, Where there is indicated with 31 an area of an N-channel single polysilicon level EPROM cell and with 32 an area of an external ciruit transistor, the process according to the present invention provides for both areas the preliminary formation, illustrated in Fig. 4, of areas of field oxide 2 on a semiconductor substrate 1 of type P, for example of boron, with the simultaneous definition of active areas 33. As illustrated in Fig. 5, after the application of a resist mask 3 there is executed an implantation of type P in a channel region 4 of cell 31 with the purpose of raising the threshold voltage of the cell itself. With reference to Fig.s 6 and 8, the mask 3 is subsequently replaced by another resist mask 5 and there is executed in the area of cell 31 an implantation of type N+, for example of arsenic with an implant dose of from 1E14 to 1E15 atoms/cm 2 , for the creation of a control gate 9 and of highly doped regions of source 7 and drain 8, defining the channel region 4. With reference to Fig.s 7 and 9, once the mask 5 is removed there is executed in both areas 31 and 32 a growth of gate oxide 11 which in the area above the control gate 9 has a greater thickness than in the area above channel region 4 of cell 31 and the corresponding region of cell 31, given the greater concentration of dope in the first area with respect to the others and given that, as is known, the thicknesses of the oxide also depend on the concentration of dope in the regions below. There follows the deposition of a Layer of polysilicon (or polysilicide) 10, a region of which, after suitable definition, constitutes the floating gate of cell 31, above the control gate 9 and the channel region 4 with partial superimposition of the regions of source 7 and drain 8, while another region forms the gate of transistor 32. Lastly, as shown in figures 2 and 3, there is provided an implantation N- (preferably of phosphorus with an implantation dose of from 5E12 to 5E13 atoms/cm 2 ) of portions of the regions of source 7 and drain 8 with the formation of respective regions 16, 17 aligned with floating gate 10, and the formation of upper oxide spacers 12, 13 at the sides of the floating gate. A similar implantation of type N- is simultaneously executed in the area of transistor 32 for the creation of corresponding source and drain regions 37 and 38 and similar spacers 39 and 40 are created at the sides of the gate of transistor 32. There is thus obtained the EPROM cell 31 shown in Fig.s 1-3, and simultaneously the circuit transistor 32 shown in Fig. 2. In a manner known in itself both cell 31 and transistor 32 are then completed with N+ implantations self-aligned with spacers 12, 13 and 39, 40 in regions 16, 17 and 37, 38, respectively.

Claims: Process of manufacturing an N channel single polysilicon level EPROM cell with an LDD- or DDD-type transistor, comprising the following succession of steps: a) forming of field oxide areas (2) and active areas (33) in an EPROM cell part (31) and in a transistor part (32) of a P type semiconductor substrate (1); b) masking the substrate (1) outside selected portions of the active areas (33) of the EPROM cell part followed an IV + -type implantation to form a control gate region (9) and source and drain regions (7, 8) of the EPROM cell; c) forming a layer of gate oxide (11, 12) on the active areas (33) of the EPROM cell part and the transistor part; d) depositing a polysilicon layer (10) on the gate oxide layer (11, 12) and defining said polysilicon layer (10) to form a floating gate of the EPROM cell, which covers said control gate region (9) and a channel region (4) between said source and drain regions (7, 8) of the EPROM cell, and a gate of the transistor; e) simultaneously performing an IV - -type implantation into side extensions (16, 17) of the source and drain regions (7, 8) of the EPROM cell and at the sides of the gate of the transistor; f) forming oxide spacers (12,13) at the sides of the floating gate of the EPROM cell and of the gate of the transistor (39,40); g) performing an IV + -type implantation self-aligned with the oxide spacers (12, 13, 39, 40) into the source and drain regions of the EPROM cell (16,17) and the transistor (37,38). Process according to claim 1, characterized in that step a) is preceded by a preliminary step of implanting P type dopant into a further selected portion of the active areas (33), which is intended to form the channel region (4) of the EPROM cell.

Inventors: MAURELLI ALFONSO, RIVA CARLO, MAURELLI, ALFONSO, RIVA, CARLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29