Bit error rate detection

Abstract: There is provided a scheme for bit error rate detection. It is characterised by: detecting the bit value present in a received multi-level signal (102), more narrowly detecting the bit value present in that received multi-level signal (104), comparing the results of narrow detection with the results detected otherwise to identify errors in detection (203, 206, 207 and 209), and accumulating detected symbol errors over unit time. Bit error rate detection can be used for antenna selection-selecting one of a plurality of diversity antennas when the error rate exceeds (213) a certain error threshold.

Description: The Field Of Invention This invention is concerned with error detection. More particularly, this invention is concerned with bit error rate detection in multi-level data signals. Background Of The Invention Conventionally, received bit error rates are determined by one of two methods: by transmitting from time to time a known symbol pattern of sufficient length to have a high probability of at least one error, or by including an error-detecting code in the normal data and keeping a count of the errors so found. Either of these methods have the problem of requiring many bits of transmitted data to make an accurate estimate of the bit error rate. For instance, if the expected bit error rate is 1 in 100 thousand (a typical figure), an accurate estimate of the actual error rate would require the evaluation of several hundred thousand bits. The additional system overhead bits required by either of these schemes undermines system throughput and constrains BER measurements to ensue on specific events or at specific predetermined intervals. European Patent Application EP-A-0 323 606 published on 12th July 1989, i.e. after the priority date of the present application, discloses error correction based on detection of error codes within a received signal. Error codes are a classical example of an undesirable limitation placed on a data sequence. US-A-4 633 519 discloses antenna diversity selection based on received signal strength. FR-A-2 523 388 relates to interference regions and provides an "eye" diagram. US-A-4 305 150 discloses a soft decision demodulator that maps an analog signal into a multibit word. The soft demodulator measures the signal to noise ratio of a single level received signal. This invention, then, takes as its object to overcome these shortcomings and to realize certain advantages presented below. Summary Of The Invention Accordingly, in one aspect, the invention provides a method of performing error detection of multi-level symbol signals characterized by: receiving a multi-level symbol signal containing any data sequence; digitizing and detecting the level of the multi-level symbol received signal; more narrowly detecting the level of the multi-level symbol received signal; and accumulating predicted bit errors from detections outside the narrow detection, but otherwise detected, to produce a bit error rate estimate. In a second aspect, the invention provides an apparatus for performing bit error rate detection on multi-level data signals characterized by: an analog to digital converter receiving a multi-level data signal and producing digitized symbols; a clock recovery circuit coupled to the analog to digital converter, said clock recovery circuit receiving the multi-level data signal and producing a symbol clock signal and a frame start signal; a mapping circuit receiving the digitized symbols and producing a decoded data output and a noise function output which indicates the number of data symbols having a level between a narrow detection band and a wide detection band; and a counter responsive to the mapping circuit receiving and accumulating a number of pulses sent by the noise function output and receiving the frame start signal from the clock recovery circuit. Description of the Drawings Additional objects, features, and advantages of the invention will be more clearly understood and the best mode contemplated for practicing it in its preferred embodiment will be appreciated (by way of unrestricted example) from the following detailed description, taken together with the accompanying drawings in which: FIG. 1 is a waveform diagram of the bit value and voltage level of a multi-level symbol signal. FIG. 2 is a block diagram of the preferred embodiment of a bit error rate detector according to the instant invention. Detailed Description In systems that employ very high-speed data rates, multi-level data symbols are common sinve any given symbol takes on a value that would ordinarily require two or more binary bits to convey. However, multi-level symbols are more difficult to correctly recover and detect because the detector needs to detect not only the polarity of the symbol (in bipolar pulse systems, as with binary symbols), but also detect the level as well. Figure 1 is a waveform diagram of the bit value and voltage level of a multi-level symbol signal. For example, the multi-level signal of Figure 1 illustrates five levels representing (arbitrarily) an idle (or noisy) state at 0 volts and one of four possible (dual binary digit) symbol values: "00" at the most negative level (nominally -6 volts); "01" at the less negative level (nominally -2 volts); "10" at the least positive level (nominally +2 volts); and "11" at the most positive level (nominally +6 volts). Conventionally, this received signal - this multi-level symbol - would be detected with a set of three separate level detectors, each having a voltage detection range centered between nominal levels, establishing bands centered about the nominal level, as illustrated by the phantom bands (102) of Figure 1. The instant invention utilizes the conventional method of detecting a received signal (detailed above), but then employs another set of bands (104) also centered about the nominal level, but having a narrower detection range - about half as wide, as illustrated by the solid bands (104) of Figure 1. Under strong signal conditions with little noise or interference present, both sets of detectors should yield identical results, but as noise or interference increases, their outputs begin to differ. Under conditions of appreciable noise or interference, signal levels might move outside the narrow bands (104) (while still, perhaps, remaining within the wider bands (102)). Since there is little or no dead zone between adjacent wide bands (where few, if any, signals would not be detected at all), but an appreciable dead zone between narrow bands (where an increasing number of symbols will not be detected at all), the difference in the number of symbols detected by either set indicates and identifies "bit errors." Thus, the accumulated difference in the number of symbols detected from wide detection as compared with the number detected from narrow detection is, over time, an indicator of the received bit error rate. Restated, comparison of the results of narrow detection and the results otherwise detected indicates errors in detection and provides a measure of the confidence held in the detection. The absence of any errors so detected enhances the confidence in the detection. The dead zone between the narrow bands can be increased or decreased depending upon the desired detection sensitivity. For example, many more errors are tolerable with digitized voice before intelligibility is lost than with other data messages. Furthermore, the dead zone, and thus the sensitivity, can be altered as the system dynamics change by employing a programmable level detector. Projected error rates may be utilized to dynamically adjust the communications system upon which the signal was received to affect the error rate. In systems that can take some kind of corrective action (such as antenna selection in a system with diversity antennas or such as handoff to a different transmitter in cellular systems), the corrective action can be predicated, at least in part, on the bit error rate exceeding a certain error threshold. The instant invention is particularly advantageous in that bit error rates, determined according to the instant invention, can be determined aperiodically, continuously, or at will. Known bit sequences need not be transmitted from time-to-time, usurping valuable system overhead, undermining system throughput and constraining bit error rate measurements to specific happenings or predetermined intervals. In fact, bit error rate checking over short intervals of, say, one hundred symbols can, by extrapolation and integration, indicate bit error rates over hundreds of thousands of symbols. Figure 2 is a block diagram of the preferred embodiment of a bit error rate detector according to the instant invention. It depicts: A standard analogue-to-digital converter 201, such as Motorola part number MC10321DW, described in the "Motorola Linear and Interface Integrated Circuits" data manual. The input of the AID 201 is fed with the analogue signal comprising the symbols to be decoded in parallel with clock recovery circuit 208. This clock recovery circuit 208 produces a symbol timing signal that indicates the optimum position for sampling the symbol, and can be realized by any of a number of well-understood methods, such as taught in "Digital Communications and Spread Spectrum Systems" by Rodger E. Ziemer and Roger L. Peterson by the Mcmillan Publishing Company, New York in 1985". This circuit also produces the "frame start" signal that identifies the beginning of a new data burst; this is also taught by Ziemer and Peterson. The output lines 202 of AID 201 are connected to the input (address) lines of Read-Only Memory (ROM) 203 that is programmed to perform the mapping function illustrated in Figure 1 and described earlier. This mapping function produces two outputs on two sets of lines: the Decoded Data output 204, which is passed to the normal data-sink function, and the "Noise" function 205. The Noise function 205 feeds a simple counter 206, which is used as a digital integrator. This counter is reset by the Frame Start function at the beginning of a data burst, henceforth counts the pulses emanating from the Noise Function line 205, corresponding to the number of symbols that are within one of the "noisy" or "high bit error rate" regions of Figure 1. Meanwhile, Symbol Counter 207 keeps track of the number of symbols received; its output 211 is fed into Digital Divider 209 as the divisor. The output of Counter 206 is fed into the dividend input 212 of divider 209. The output 213 of divider 209 is then continuously an estimate of the Bit Error Rate of the incoming symbol string, and may be sampled by the data-reduction circuits (data sink) at any time. Note that many variations of this circuit are possible. For instance, if all symbols are of the same length, Counter 207 and divider 209 may be eliminated and the output of counter 206 read directly by the data sink. Alternatively, arrangements may be made to "freeze" counter 206 at a particular reading of symbol counter 207, eliminating the need for divider 209 by virtue of measuring the BER for a fixed portion at the beginning of each data burst. In summary then, there has been provided a scheme for bit error rate detection. It comprises: detecting the bit value present in a received multi-level signal, more narrowly detecting the bit value present in that received multi-level signal, comparing the results of narrow detection with the results detected otherwise to identify errors in detection, and accumulating detected symbol errors over unit time. Bit error rate detection can be used for antenna selection--selecting one of a plurality of diversity antennas when the error rate exceeds a certain error threshold. While the preferred embodiment of the invention has been described and shown, it will be appreciated by those skilled in the art that other variations and modifications of this invention may be implemented. For example, bit error rate could be associated (and stored) with the detected bit stream to indicate the level of confidence held in the detected bit or stream., and for example, individual comparators and a logic ladder could be used in place of the A/D's and ROMs. These and all other variations and adaptations are expected to fall within the ambit of the appended claims.

Claims: A method of performing error detection of multi-level symbol signals characterized by: receiving a multi-level symbol signal containing any data sequence; digitizing and detecting the level of the multi-level symbol received signal (102); more narrowly detecting (104) the level of the multi-level symbol received signal ; and accumulating predicted bit errors from detections outside the narrow detection (104), but otherwise detected, to produce a bit error rate estimate. A method of antenna selection using error detection according to claim 1 and further characterized by the step of de-selecting one of a plurality of diversity antennas when the bit error rate estimate exceeds a threshold value, thereby selecting another of the plurality of diversity antennas. The method of claim 1, further characterized by the step of de-selecting one of a plurality of communication channels when the bit error rate estimate exceeds a predetermined threshold value, thereby selecting another of the plurality of communication channels. The method of claim 1, wherein the bit error rate estimate is produced periodically, continuously, or at will. The method of claim 1, wherein said bit error rate estimate is accumulated over unit time. The method of claim 1, wherein the narrowness of the narrow detection (104) is adjustable. The method of claim 6, wherein the narrow detection (104) is adjusted to be approximately one half the width of a wide detection region (102). A method of handoff using error detection according to claim 1 and further characterized by the step of selecting one of a plurality of communication channels when the error rate estimate exceeds a threshold value. An apparatus for performing bit error rate detection on multi-level data signals characterized by: an analog to digital converter (201) receiving a multi-level data signal and producing digitized symbols (202); a clock recovery circuit (208) coupled to the analog to digital converter (201), said clock recovery circuit (208) receiving the multi-level data signal and producing a symbol clock signal and a frame start signal (210); a mapping circuit (203) receiving the digitized symbols (202) and producing a decoded data output (204) and a noise function output (205) which indicates the number of data symbols having a level between a narrow detection band (104) and a wide detection band (102); and a counter (206) responsive to the mapping circuit (203) receiving and accumulating a number of pulses sent by the noise function output (205) and receiving the frame start signal (210) from the clock recovery circuit (208). The apparatus of claim 9, wherein the counter (206) is reset by the frame start signal (210) at the beginning of a data burst. The apparatus of claim 9, further characterized by a symbol counter (207) responsive to the clock recovery circuit (210), said symbol counter (207) receiving the frame start signal (210) and producing a divisor signal (211). The apparatus of claim 11, further characterized by a digital divider (209) receiving a dividend signal (212) from the counter (206), receiving the divisor signal (211) from the symbol counter (207), and producing a bit error rate estimate (213). An antenna selector using the apparatus for performing bit error rate detection as recited by claim 12 and further characterized by means for selecting one of a plurality of diversity antennas when the bit error rate estimate exceeds a threshold.

Inventors: FREEBURG THOMAS A, FREEBURG, THOMAS A.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1990
Main classification: H04L1
IPC codes: H04L1