Negative overvoltage protection circuit for insulated vertical PNP transistors

Abstract: A negative overvoltage protection circuit for an insulated vertical PNP transistor (Q P ) the emitter whereof defines the input (V IN ), the collector whereof defines the output (V OUT ) and the base whereof is connected to an NPN driving transistor (Q N ). In order to maximally extend the negative overvoltage which can be applied to the output, the protection circuit comprises an output voltage sensor (R₄), a voltage reference (V B ), a comparator (Q₂,Q₃,D₁) which is connected in input to the voltage reference (V B ) and to the sensor (R₄) and generates in output an activation signal when the output voltage of the PNP transistor (Q P ) becomes smaller than the reference, a switch (Q₅) which is controlled by the comparator (Q₂,Q₃,D₁) to switch off the NPN driving transistor (Q P ) upon the reception of the activation signal and a low-impedance circuit (Q₄) which is connected between the emitter and the base of the insulated vertical PNP transistor (Q P ) and is activated by the activation signal, in a manner suitable for bringing the insulated vertical PNP transistor (Q P ) practically to BV CBO .

Description: The present invention relates to a negative overvoltage protection circuit for insulated vertical PNP transistors. As known, insulated vertical PNP transistors, by virtue of their relative advantages with respect to lateral PNP transistors (i.e. higher gain, higher cutoff frequency, smaller bulk) are preferred over the latter in certain applications. A low-drop control circuit is quite often used with said insulated vertical transistors (low-drop configuration), as shown in figure 1. As can be seen, the PNP transistor, indicated by Q P , has an emitter which defines the input terminal which receives the input voltage V IN , a collector which defines the output terminal on which the voltage V OUT is present and a base which is connected to the collector of an NPN transistor Q N the emitter whereof is connected to the ground and the base whereof is connected, by means of a current source I g , to the input terminal or to a reference voltage source. This circuital configuration is used for example in low-drop regulators, in driving devices which operate as switches for inductive loads, such as relays ("high side drivers") or in controlled switches. In all these applications, the need often arises to be able to connect the output V OUT to the ground or to a voltage more negative than the voltage of the substrate. However, this entails problems due to the physical execution of the insulated vertical PNP transistor. Said transistor is in fact executed in the manner illustrated in figure 2, wherein the reference numeral 1 indicates the P-type substrate which is connected to the ground, the reference numeral 2 indicates the N-type epitaxial layer, the reference numeral 3 indicates the junction insulation ring which surrounds the portion of epitaxial layer, indicated by 2′, which internally accommodates the PNP transistor. In particular, the N⁺-type buried layer 4, the P-type collector region 5, the N-type base region 6 (formed by a further portion of the epitaxial layer and provided with an N⁺-type enhanced region 7 to provide the contact) and the P-type emitter region 8 are defined within said portion 2′. The figure also indicates the collector contact C, the base contact B and the emitter contact E, as well as (in broken lines) the parasite structures constituted by the substrate diode D s which is formed between the insulation 3 and the N⁺-type enhanced region 9 (on which the contact A is formed), by the Zener diode D z which is formed between the collector region 5 and the buried layer 4, as well as by the diode D which is formed between the buried layer 4 and the substrate 1, and is therefore anti-series connected to D z . If the contact A (and therefore the ring formed by the portion 2′ of the epitaxial layer) is short-circuited with the collector C, as normally occurs, the substrate diode D s starts to conduct as soon as the voltage on the collector C drops to approximately -0.7 V with respect to the voltage of the substrate (ground). In order to solve this problem, it is currently preferred to leave the portion 2′ floating, i.e. with the terminal A not connected. In this condition, the negative voltage which the output can withstand is related to the breakdown of the Zener diode plus the drop across the diode D (see figure 1). However, even this solution is not free from disadvantages, which are related to the maximum voltage which the vertical PNP transistor can withstand between the emitter and the collector. To clarify this problems, consider for example an insulated vertical PNP transistor diffused with a process for which BV CE0 = 20 V, BV CB0 = 30 V and BV Dz = 15 V. In this case, if the input voltage V IN = 10 V, the output voltage V OUT cannot drop below -10 V, otherwise the transistor Q P breaks down for BV CE0 . Keeping the PNP transistor on when its collector reaches a voltage which is lower than the ground can furthermore entail several problems. Given this situation, the aim of the present invention is to provide a negative overvoltage protection circuit for insulated vertical PNP transistors which is capable of effectively protecting the PNP transistor even at output voltages which are lower than those which can be obtained with known solutions. Within the scope of this aim, a particular object of the present invention is to provide a protection circuit of the indicated type in which any possible parasite elements do not compromise the operation of the circuit itself. Another object of the present invention is to provide a protection circuit of the indicated type which can be easily integrated and occupies a small amount of area. Not least object of the present invention is to provide a protection circuit which has great reliability and does not require, for its manufacture, devices or procedures which differ from those commonly used in the electronics industry. This aim, the objects mentioned and others which will become apparent hereinafter are achieved by a negative overvoltage protection circuit for an insulated vertical PNP transistor, as defined in the accompanying claim 1. Substantially, the invention consists of a circuit which senses the voltage of the collector of the PNP transistor and, when said voltage reaches a value which is lower than the ground, switches said transistor off, bringing it to V CEV , which is equal to BV CB0 minus the drop V CEsat (i.e. it activates a low-resistivity path between the emitter and the base thereof). This configuration corresponds to the insertion of a constant-voltage source which, in a preferred embodiment, has a value which is equal to the collector-emitter drop of a transistor in saturation (on the subject, see P. Antognetti, "Power Integrated Circuits", McGraw Hill 1986, pages 2.16 and 2.17, figures 2-13, with R = 0). Since in the present case said drop is very small (typically 100 mV for NPN transistors) and is in any case much smaller than BV CB0 (which, as mentioned in the example considered, is equal to 30 V), in practice the PNP transistor operates at BV CB0 . The range of the negative overvoltage is consequently extended, in practice to the breakdown voltage of the Zener diode associated with the PNP transistor, said voltage being dependent on the manufacturing process employed. With this solution, and considering an insulated vertical PNP transistor which has the above indicated values, when the input voltage is 10 V the output can reach -15 V, instead of -10 V, i.e. in practice till the process limit of the Zener diode D z . The characteristics and advantages of the invention will become apparent from the description of a preferred embodiment, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is an equivalent circuit diagram of a currently used configuration, which comprises a known insulated vertical PNP transistor; figure 2 is a transverse sectional view taken across a silicon chip which integrates a known insulated vertical PNP transistor; figure 3 is a view of the protection circuit according to the invention; figures 4 and 5 are views of the physical execution of two components of the circuit of figure 3; and figure 6 is a view of a variated embodiment of the circuit of figure 3. With reference to figure 3, the protection circuit according to the invention is applied to the known configuration which has already been illustrated in figure 1 and comprises the PNP-type transistor Q P the emitter whereof defines the input terminal which receives the input voltage V IN , the collector whereof defines the output terminal set to the output voltage V OUT and the base whereof is driven by the NPN-type transistor Q N powered by the current source I g which is in turn connected to the input terminal or to a reference voltage source. The protection circuit according to the invention has been generally indicated by the reference numeral 15 and substantially comprises an output voltage sensor, a voltage reference, a comparator connected in input to the voltage reference and to the sensor, a switch for the NPN transistor which is controlled by the comparator, and a low-impedance circuit which is also activated by the comparator. In detail, the output voltage sensor is provided by a resistor R₄ which is connected with one terminal to the output so as to detect the output voltage V OUT and with the other terminal to an input of the comparator, which comprises herein a pair of transistors Q₂, Q₃ and a diode D₁. The bases of the transistors Q₂ and Q₃ are coupled and define a second input of the comparator; the emitters are also coupled and are connected to the anode of the diode D₁, the cathode whereof defines the first input of the comparator and is connected to the resistor R₄, as already indicated. The collectors of Q₂ and Q₃ instead define the outputs of the comparator. The voltage reference is formed here by a pair of resistors R₁, R₂ which are connected in series between a current source I p (which is furthermore connected to the input terminal or to another reference voltage) and the ground. The intermediate point between these two resistors is connected to the base of an NPN-type transistor Q₁, whereas the intermediate point between R₂ and the current source is connected to the collector of Q₁ and to the base of the transistors Q₂ and Q₃. In turn, the emitter of Q₁ is connected to the ground. R₁ and R₂ have a preset mutual ratio (in the illustrated example, R₂ = R₁/2), so as to constitute a multiplier of the voltage applied to R₁ (V be ). In practice, assuming that V BE is equal to 0.7 V, a voltage V B equal to 1.5·V be = 1.05 V is present on the bases of Q₂ and Q₃. The switch of the transistor Q N is formed here by the transistor Q₅, which is of the PNP type, is diode-connected and has a first collector C₁ and its base connected to the collector of Q₃, its emitter connected to the input terminal and a second collector C₂ connected to the base of a transistor Q₆ of the NPN type, the emitter whereof is connected to the ground and the collector whereof is connected to the base of Q N . A resistor R₃ is furthermore connected between the base of Q6 and the ground. The low-impedance circuit is finally formed by a transistor Q₄ of the PNP type which is also diode-connected, has its emitter connected to the input terminal, a first collector C₃ and the base connected to the collector of Q₂ and a second collector C₄ connected to the base of Q P . The operation of the circuit according to the invention is as follows: during nominal operation, with positive output voltage, and in any case until the output voltage V OUT (and therefore V C ) is higher than -0.35 V, the drop across the base-emitter junction of Q2 and across D₁ is such as to keep Q₂ and D₁ in the off state and therefore the circuit 15 is switched off. During this step, the diode D₁, since it is provided as a base-collector diode, withstands a voltage which is higher than BV EBO and is equal to approximately 0.7 V, and is therefore capable of preventing the breakdown of the base-emitter junctions of Q₂ and Q₃. When the output voltage V OUT drops below -0.35 V (i.e. V B - V be,Q2 - V D1 ), Q₂ and Q₃ start to conduct, and so do Q₄ and Q₅. Q₅ delivers current to Q₆, which thus switches off the driving transistor Q N , whereas Q₄, by saturating, creates a low-resistivity path between the emitter and the base of Q P , sending it to BV CB0 - V CEsat . Q N , too, due to the low-resistivity path constituted by Q₆, furthermore practically reaches BV CB0 (except for the saturation emitter-collector drop of Q₅). The current which flows across Q₂ and Q₃ is controlled and is equal to: I = 1/2 (V C - V OUT )/R₄ = 1/2 (-0.35 V - V OUT ) / R₄. In the circuit diagram of figure 3, the parasite elements associated with the components of the illustrated protection circuit have also been shown in broken lines. In particular, a parasite diode D p2 is associated with the resistor R₄, whereas the parasite diode D p1 is associated with the diode D₁. However, said parasite diodes do not compromise the operation of the protection device according to the invention. In fact (see figure 4, which illustrates a transverse sectional view of the portion of the silicon chip in which the resistor R₄ is executed) the latter is provided by a P-type region 22 which extends inside a portion 2″ of the epitaxial layer which is insulated from the rest by means of a P-type region 20 which extends in a ring around the portion 2″. A buried layer 21 of the N⁺ type is provided below the region 22 which constitutes the resistor, whereas an N⁺-type biasing region 23 extends at one end of the region 22. The figure also illustrates the contacts on which the voltages V C and V OUT are present. As shown in broken lines in figure 4, the biasing region 23 and the substrate 1 (or the insulation ring 20) form the parasite diode D p2 . However, said diode can never start conducting, since V C = -0.35 V (in general, it is sufficient that V C > -0.7 V). Similarly, the parasite diode D p1 associated with the diode D₁ is never activated. In fact (see figure 5, which illustrates a transverse sectional view of the portion of the silicon chip in which the diode D₁ is provided and includes the substrate 1 and the portion 2‴ of epitaxial layer which is surrounded by the P-type insulation layer 25) the cathode of the diode, which is constituted by the regions 26 and 27, forms, together with the substrate, the parasite diode D p1 , which however, since the cathode K of D₁ is at the voltage V C = -0.35 V, can never start conducting. In the figure, the P-type region 28 constitutes the anode of D₁ (which is set to the voltage V D ). Figure 6 illustrates a variated embodiment of the circuit of figure 3, since the part which generates the voltage reference has been replaced with a generic source of the voltage V R , whereas the other parts of the circuit remain unchanged. With this solution it is possible to switch the transistor Q P off at any collector voltage V OUT (as long as it is higher than -0.35 V) by appropriately choosing the value of the voltage V R . In fact, as soon as the following condition occurs: V OUT < V R - 2V be the protection circuit 15′ intervenes, switching the transistor Q P off and sending it in practice to BV CB0 , similarly to what is described for figure 3. The circuit according to the invention not only allows to maximally extend the range of the negative overvoltage on the output, as explained, but has a reliable operation, can be easily integrated and occupies a small area, since it is composed of transistors with a minimal area. The invention thus conceived is susceptible to numerous modifications and variations within the scope of the inventive concept as defined in the appended claims. In particular, within the scope of the appended claims, details may be replaced with other technically equivalent ones. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: Negative overvoltage protection circuit for an insulated vertical PNP transistor (Q p ), having emitter and collector terminals which define an input terminal (V IN ) and an output terminal (V OUT ) which generates an output voltage and a base terminal which receives a driving signal, characterized in that it comprises an output voltage sensor (R₄) connected to said output terminal (V OUT ), a line set at a reference voltage (V B ), comparator means (Q₂,Q₃,D₁) having a first input connected to said reference voltage line, a second input connected to said sensor (R₄) and an output which generates an activation signal when the output voltage becomes lower than said reference voltage (V B ), switch means (Q₅) controlled by said comparator means (Q₂,Q₃,D₁) and suitable for switching off said insulated vertical PNP transistor (Q P ) upon the reception of said activation signal and a low-impedance circuit (Q₄) connected between the emitter and base terminals of said insulated vertical PNP transistor (Q P ) and activated by said activation signal, in a manner suitable for bringing said insulated vertical PNP transistor (Q P ) substantially to BV CB0 . Circuit according to claim 1, characterized in that said sensor means comprise a resistor (R₄). Circuit according to claims 1 and 2, characterized in that said comparator means (Q₂,Q₃,D₁) comprise a pair of transistors (Q₂,Q₃) having base terminals which are mutually coupled and connected to said reference voltage line, emitter terminals which are mutually coupled and connected to said sensor (R₄), and collector terminals which define said output of the comparator means (Q₂,Q₃,D₁). Circuit according to claim 3, characterized in that said emitter terminals of said pair of transistors (Q₂,Q₃) are connected to said sensor (R₄) across a diode (D₁). Circuit according to the preceding claims, characterized in that said pair of transistors (Q₂,Q₃) is of the NPN type and said emitters are connected to the anode of said diode (D₁). Circuit according to the preceding claims, characterized in that said diode (D₁) is provided as a base-collector diode. Circuit according to one or more of the preceding claims, characterized in that said switch means (Q₅) comprise a third transistor (Q₅) of the PNP type which is diode-connected, has a first collector terminal (C₁) and the base terminal connected to the collector terminal of a first one (Q₃) of said pair of transistors (Q₂,Q₃). the emitter terminal connected to said input terminal (V IN ) and a second collector terminal (C₂) connected to the base terminal of a fourth transistor (Q₆) of the NPN type which has its collector terminal connected to the base terminal of an NPN driving transistor (Q N ) which drives said base terminal of said insulated vertical PNP transistor (Q P ), said fourth transistor (Q₆)having its emitter terminal connected to the ground. Circuit according to one or more of the preceding claims, characterized in that said low-impedance circuit (Q₄) comprises a fifth transistor (Q₅) of the NPN type which is diode-connected, has a first collector terminal (C₃) and the base terminal connected to the collector terminal of a second one (Q₂) of said pair of transistors (Q₂,Q₃), the emitter terminal connected to said input terminal (V IN )and a second collector terminal (C₄) connected to the base terminal of said insulated vertical PNP transistor (Q P ). Circuit according to one or more of the preceding claims, characterized in that said reference voltage line is connected to a voltage source circuit (R₁,R₂,Q₁) which comprises a sixth transistor (Q₁) the collector terminal whereof is connected to said reference voltage line, the emitter terminal whereof is connected to the ground and the base terminal whereof is connected to an intermediate point of a pair of resistors (R₁,R₂) which are respectively connected in series between said reference voltage line and the ground, a current source (I P ) supplying said voltage source circuit.

Inventors: GARIBOLDI ROBERTO, GOLA ALBERTO, GARIBOLDI, ROBERTO, GOLA, ALBERTO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H03K17
IPC codes: H02H9