Sampling rate converter

Abstract: In a sampling rate converter, an input digital video signal has its sampling rate converted from a first sampling frequency to a second or different sampling frequency by oversampling the input digital video signal at a rate which is an integral multiple of the first sampling frequency so as to generate zero values between data of the input digital video signal, interpolating an output signal from the oversampled input digital video signal, decimating the interpolated output signal for generating therefrom a digital video signal having the desired second sampling frequency, and only then applying the digital video signal having the second sampling frequency to a low pass filter, preferably of the finite impulse response type, for eliminating therefrom an undesirable signal component which is due to the sample rate conversion and which appears between frequency bands of one-half of the first and second sampling frequencies, respectively.

Description: Field of the Invention This invention relates to a sampling rate converter and, more particularly, is directed to an apparatus by which the sampling rate of a digital signal may be converted from an initial sampling frequency to a different sampling frequency having a low correlation therewith. Description of the Prior Art It has been proposed, for example, as disclosed in detail in Japanese Laid-Open Patent JP-A-60-4324, published January 10, 1985, and having a common assignee herewith, to provide a sampling rate converter primarily intended for use in connection with digital audio signals which have a relatively low sampling rate, and by which the initial sampling rate can be converted to an arbitrarily different sampling frequency having low correlation with the initial sampling rate. In such proposed sampling rate converter, the input digital signal is oversampled and the resulting oversampled signal is interpolated and then applied to a digital low pass filter, whereupon, the output of the digital low pass filter is supplied to a decimating circuit for generating therefrom a digital signal having the desired sampling frequency. Although the foregoing sampling rate converter comprising an interpolation circuit, a digital low pass filter and a decimation circuit, connected in series in the order named, can effect conversion of the sampling rate without aliasing noise, the digital low pass filter connected between the interpolation circuit and the decimation circuit has to be of a very high degree or order, particularly if the input digital signal is a digital video signal. For example, if the previously proposed sampling rate converter is used for converting a component-type digital video signal having a sampling frequency of 13.5 MHz into a digital video signal of the PAL composite-type having a sampling frequency of 17.734 MHz, the digital low pass filter, which is desirably of the finite impulse response (FIR) type, would need to have 16,500 stages in order to provide the sampling rate converter with desired predetermined conversion characteristics for maintaining the Nyquist frequencies in the transmission channel. Such a large number of stages in the digital low pass filter is impractical in that it makes it difficult to design the low pass filter as an integrated circuit. US-A-4472785, on which the precharacterising portion of appended claim 1 is based, discloses a similar sampling frequency converter, but, in order to overcome problems in the construction of a suitable FIR filter, proposes a combined FIR and IIF filter. Accordingly, it is an object of the present invention to provide a sampling rate converter which avoids the above described problems associated with the prior art. More specifically, it is an object of the present invention to provide a sampling rate converter which is relatively simple and small and capable of providing desirable converting characteristics and accuracy. Another object of the invention is to provide a sampling rate converter, as aforesaid, which employs a digital low pass filter comprised of a relatively small number of stages so as to reduce the size thereof and facilitate its design as an integrated circuit (IC). Still another object of this invention is to provide a sampling rate converter, as aforesaid, which is suitable for use with a digital video signal or the like having a relatively high sampling rate. In accordance with an aspect of this invention, there is provided a sampling rate converting apparatus for converting a sampling rate of an input digital signal having a first sampling frequency to a second sampling rate having a second sampling frequency different from said first sampling frequency, comprising: oversampling means receiving said input digital signal for oversampling the latter at a rate which is an integral multiple of said first sampling frequency so as to generate zero values between data of said input digital video signal; means connected to said oversampling means for interpolating an output signal therefrom; decimating means for generating therefrom a digital signal having said second sampling frequency; and low pass filter means for eliminating an undesired signal component due to the converting of the sampling rate and which appears between frequency bands of one-half of said first and second sampling frequencies, respectively; characterized in that the input digital signal is a digital video signal; said decimating means is arranged to act on the interpolated output signal to generate an intermediate output digital video signal; and said low pass filter means is arranged to receive said intermediate output digital video signal to eliminate therefrom the undesired signal component. The above, and other objects, features and advantages of the invention, will be apparent in the following detailed description of an illustrative embodiment thereof which is to be read in connection with the accompanying drawings forming a part hereof and in which corresponding parts are identified by the same reference numerals in the several views. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a sampling rate converter according to an embodiment of the present invention; Fig. 2 is a characteristic diagram showing Nyquist characteristics of filters included in the sampling rate converter of Fig. 1; Fig. 3 is a connection diagram showing details of a rate conversion filter constituting one of the components of the sampling rate converter of Fig. 1; Figs. 4A, 4B and 4C are signal waveforms to which reference will be made in describing the operation of the rate conversion filter of Fig. 3; and Fig. 5 is a connection diagram showing a low pass filter that is also included in the sampling rate converter of Fig. 1. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Referring to the drawings in detail, and initially to Fig. 1 thereof, it will be seen that a sampling rate converter 1 according to an embodiment of the invention is there shown for converting a digital signal DG₁ having a first sampling frequency f₁ into a digital signal DG₂ having a second sampling frequency f₂ different from the first frequency f₁. The sampling rate converter 1 generally comprises an oversampling or rate conversion filter 2 for oversampling the digital signal DG₁ at a predetermined frequency band corresponding to the Nyquist frequency f₁/2 or f₂/2 of the first or second sampling frequency f₁ or f₂, respectively, which has the higher frequency, thereby obtaining a digital signal DG₁₀ having the second sampling frequency f₂, and a low pass filter 3 for limiting the frequency band of the output signal DG₂ to the Nyquist frequency f₁/2 or f₂/2 of the first or second sampling frequency f₁ or f₂ having the lower frequency, whereby there is eliminated from the digital signal DG₁₀ an undesirable signal component which is due to the sample rate conversion and which appears between frequency bands of the Nyquist frequencies f 1/2 and f 2/2 . The sampling rate converter 1 according to this invention is particularly adapted for converting a digital signal DG₁ having a relatively low first sampling frequency f₁, for example, a component type digital video signal having a sampling frequency f₁ of 13.5 MHz, into a digital signal DG₂ having a relatively high second sampling frequency f₂, for example, a digital video signal of the PAL composite type having a sampling frequency f₂ of 17.734 MHz. It will be appreciated that, in practice, in converting the sampling rate of the digital signal DG₁ having a first sampling frequency f₁ to a digital signal DG₂ having a second sampling frequency f₂, no signals of substance appear between the Nyquist frequencies f₁/2 and f₂/2 of the signals DG₁ and DG₂, respectively. Therefore, undesirable signal components which appear between the Nyquist frequencies should be eliminated prior to transmission of the sampling rate converted signal DG₂ from the sampling rate converter 1. Thus, in the sampling rate converter 1, the rate conversion filter 2 is effective to convert the sampling rate from the frequency f₁ to the frequency f₂, and then the low pass filter 3 is effective to reject or eliminate the unnecessary or undesirable frequency components between the Nyquist frequencies. The rate conversion filter 2 may be formed of a finite impulse response (FIR) type digital filter having, for example, 4,500 stages, and constituting, as a whole, a 500 - times oversampling filter. In that case, the rate conversion filter 2 has the Nyquist characteristic C₂ represented by the dotted line on Fig. 2. In other words, the rate conversion filter 2 converts the sampling rate from the sampling frequency f₁ to the sampling frequency f₂ under the conditions of Nyquist characteristic C₂. Such Nyquist characteristic C₂ is shown to be substantially flat up to the vicinity of the Nyquist frequency f₁/2 of the first sampling frequency f₁, and then declines gradually from the Nyquist frequency f₁/2 to the Nyquist frequency f₂/2 of the second sampling frequency f₂. The digital signal DG₁₀ delivered from the rate conversion filter 2 to the low pass filter 3 for limiting by the latter to a predetermined frequency band, as previously described, is delivered from the low pass filter 3 as the output digital signal DG₂ having the sampling frequency f₂. The low pass filter 3 is desirably formed of an FIR-type digital filter which, for example, has 33 stages, and desirably has the characteristic C₁ shown in solid lines on Fig. 2. Such characteristic C₁ is shown to be flat up to a frequency which is just below the Nyquist frequency f₁/2 of the first sampling frequency f₁, and then falls sharply at the frequency f₁/2. Therefore, the frequency band of the digital signal DG₁₀ supplied to the low pass filter 3 is limited thereby in accordance with the characteristic C₁. In the preferred embodiment of this invention being described herein, the rate conversion filter 2 has the structural arrangement shown in Fig. 3 and includes, in addition to the FIR-type digital filter 2′ having 4,500 stages, an oversampling circuit 4, a decimating circuit 5 and a timing adjustment circuit 6. More specifically, the oversampling circuit 4 is shown to be in the form of a switch having a first fixed contact a which receives the input digital signal DG₁ (Fig. 4A) having the first sampling frequency f₁, and a second fixed contact b connected to ground. The switch 4 further includes a movable contact c which is made to alternately engage the fixed contacts a and b by a suitable input control signal CNT in which has an oversampling frequency 500 f₁, that is, an oversampling frequency 500 times the first sampling frequency f₁, and which is supplied by a suitable input timing control circuit (not shown). During each cycle of the input control signal CNT in , the movable contact c of the oversampling switch 4 engages the first contact a for a period of T₁/500, in which T₁ is the sampling period of the input digital signal DG₁. Thus, during each sampling period T₁ of the digital signal DG₁ the latter is sampled at a rate which is an integral multiple (500 times) of the first sampling frequency f₁ with zero values being generated between the oversampled data, that is, whenever the movable contact c engages the grounded fixed contact b . The output of the oversampling switch 4 constituted by its movable contact c is connected to the FIR-type digital filter 2′ which, in the illustrated embodiment, is shown to comprise a series circuit of 4,499 flip-flops (F.F.) D₁, D₂, --- D 4,499 which are operative as latches at the oversampling frequency 500 f₁ so as to each have a delay time of T₁/500. The FIR-type digital filter 2′ of Fig. 3 is adapted to have the predetermined characteristic C₂ (Fig. 2) by being an FIR-type digital filter of the 9th order for the sampling period T₁. The FIR-type digital filter of Fig. 3 is further shown to have 4,500 multipliers M₀, M₁ --- M 4,499 . The multiplier M₀ receives the digital signal input to the flip-flop D₁, while the multiplier M 4,499 receives the output digital signal from the flip-flop D 4,499 . The intervening multipliers M₁ - M 4,4498 , receive the output digital signals from the flip-flops D₁ - D 4,498 , respectively, which, of course, correspond to the input digital signals of the flip-flops D₂ - D 4,499 , respectively. The foregoing described inputs to the multipliers M₀ - M 4,4499 are multiplied therein by predetermined coefficients a₀ - a 4,499 , respectively, and the multiplied results from the multipliers M₀ - M 4,4499 are added together by means of corresponding adders A₁ - A 4,4499 , arranged as shown on Fig. 3. Thus, the input digital signal DG₁ is oversampled by a factor of 500 so as to provide an oversampled signal DG OVR (Fig. 4B) at the output of the adder A 4,499 . Although the input digital signal DG₁ is, in fact, oversampled by a factor of 500, the oversampled signal DG OVR is shown on Fig. 4B to be oversampled only by a factor of 6 for ease of illustration. The oversampled signal DG OVR is supplied to an input terminal d of the decimating circuit 5 which is shown on Fig. 3 to be in the form of a switch intermittently closed in response to an output control signal CNT OUT supplied from a suitable output timing control circuit (not shown) and having the second sampling frequency f₂ so as to be closed or turned ON at intervals of the sampling period T₂ of the second sampling frequency f₂. Thus, at the output terminal e of the decimating circuit 5 there is obtained a resampled or decimated signal DG RSP which is resampled approximately in synchronism with the second sampling signal f₂. This decimated or resampled signal DG RSP is input to the subsequently arranged timing adjustment circuit 6 in which it is suitably synchronized with the second sampling frequency f₂ for providing the digital signal DG₁₀ (Fig. 4C) having the second sampling frequency f₂ and which appears at the output of the rate conversion filter 2. In the preferred embodiment being presently described, the low pass filter 3 is structurally arranged as shown in Fig. 5, that is, is in the form of an FIR-type digital filter, which receives, at its input, the digital signal DG₁₀ whose sampling rate has been already converted by the rate conversion filter 2 to the second sampling frequency f₂. The FIR-type digital filter 3 is shown on Fig. 5 to comprise a series circuit of 32 flip-flops DD1, DD2, --- DD32 operative at the second sampling frequency f₂ and each having a delay equivalent to the sampling period T₂ of the sampling frequency f₂. The FIR-type digital filter 3 is adapted to have the predetermined characteristic C₁ (Fig. 2) by reason of its being formed as an FIR digital filter of the 33rd order for the sampling period T₂. The FIR-type digital filter 3 is further shown to have 33 multipliers MM₀, MM₁, --- MM₃₂. The multiplier MM₀ receives the digital signal DG₁₀ which is input to the flip-flop DD₁, while the multiplier MM₃₂ receives the output digital signal from the flip-flop DD₃₂. The intervening multipliers MM₁ - MM₃₁ receive the output digital signals from the flip-flops DD₁ - DD₃₁, respectively, which, of course, correspond to the input digital signals of the flip-flops DD₂ - DD₃₂, respectively. The foregoing described inputs to the multipliers MM₀ - MM₃₂ are multiplied therein by predetermined coefficients b₀ - b₃₂, respectively, and the multiplied results from the multipliers MM₀ - MM₃₂ are added together in an adder 7 to provide the digital signal DG₂ as the output therefrom. It will be understood that the FIR-type digital filter 3 is operative to limit the pass-band of the digital signal DG₁₀ input thereto with the result that the output digital signal DG₂ will have the predetermined desired characteristic C₁ and the second sampling frequency f₂. According to experiments that have been conducted, if a sampling rate converter employs only a rate conversion filter, as shown in Fig. 3, for oversampling the input digital signal DG₁ by a factor of 500 and for obtaining the output digital signal DG₂ with the desired characteristic C₁, it is necessary to provide the FIR-type digital filter 2′ with at least 16,500 stages, as earlier noted in discussing the published Japanese patent 60-4324. Obviously, such a large number of stages of the filter 2′ for achieving the desired characteristic C₁ is impractical from the standpoint of providing such filter as an integrated circuit. The large number of stages required in the filter disposed in advance of the decimating circuit if such filter is to be employed for limiting the output digital signal DG₂ to the characteristic C₁, results from the fact that the filter positioned in advance of the decimating circuit has to handle 500 times as much data as a low pass filter disposed after the decimating circuit, as in the case of the filter 3. In contrast to the arrangement according to the prior art which would require 16,500 stages in a low pass filter in advance of the decimating circuit for limiting the output digital signal having the second sampling frequency f₂ to the characteristic C₁, the apparatus according to the present invention can achieve the same results with only a total of 4,533 stages in the FIR-type filters, that is, 4,500 stages in the FIR-type filter 2′ of the rate conversion filter 2 and 33 stages in the low-pass filter 3 which follows the decimating circuit 5 and hence operates on a greatly reduced amount of data. It will be appreciated that, in view of the foregoing, the circuit configuration of the sampling rate converter 1 according to the present invention can be greatly simplified and easily incorporated in an integrated circuit without sacrificing either the converting characteristic or accuracy thereof. By way of summary, it will be seen that, in the preferred embodiment of the invention described above, a digital signal DG₁ having a first sampling frequency f₁ is oversampled at a predetermined frequency band corresponding to the Nyquist frequency f₂/2 of a second sampling frequency f₂ which is higher than the first sampling frequency f₁ so as to obtain a digital signal DG₁₀ having the second sampling frequency f₂, whereupon the frequency band of the digital signal DG₁₀ is limited according to the Nyquist frequency f₁/2 of the first sampling frequency f₁. Thus, the number of stages or orders of the oversampling filter can be very greatly decreased, for example, from 16,500 stages to 4,500 stages, with the result that a sampling rate converter having a predetermined sampling rate converting characteristic and accuracy can be achieved with a simplified overall structure. In the preferred embodiment of the invention specifically described above, the sampling rate of the input digital signal DG₁ having a first sampling frequency f₁ is converted to a second sampling frequency f₂ which is higher than the first sampling frequency f₁, but it is to be understood that the present invention is not limited in that respect. In other words, the present invention can be similarly applied to a situation in which the sampling rate of the input digital signal is to be converted to a lower sampling frequency. In such case, the order in which the rate conversion filter 2 and the low pass filter 3 are positioned in Fig. 1 may be reversed so that the input digital signal first has its frequency band limited by means of the low pass filter 3 and then the output of the filter 3 is supplied to the rate conversion filter 2 so as to issue therefrom with the desired sampling frequency lower than that of the input digital signal. Further, in the specifically described embodiment of the invention, an oversampling factor of 500 has been employed, but it will be appreciated that other oversampling factors can be selected, as desired. Similarly, although the specifically described embodiment of the invention employs 4,500 stages in the FIR-type digital filter 2′ of the rate conversion filter 2, that is, 9 stages for each of the 500 oversampled periods T₁/500 included in each sampling period T₁ of the input digital signal DG₁, and 33 stages in the low pass filter 3 for each period T₂ of the digital signal DG₁₀, the numbers of stages provided in each of the FIR-type digital filters 2′ and 3 are not limited to those specified, but may be otherwise suitably selected in accordance with the required Nyquist characteristics. Finally, although the specifically described embodiment of the invention refers to the case in which video signals of a PAL component type having a sampling frequency f₁ = 13.5 MHz are converted to video signals of a PAL composite type having a sampling frequency f₂ = 17.734 MHz, the invention is not limited thereto and can be applied similarly to any other situation where the sampling frequency of a digital signal is to be converted to another sampling frequency having a low correlation therewith.

Claims: A sampling rate converting apparatus (1) for converting a sampling rate of an input digital signal (DG₁) having a first sampling frequency (f₁) to a second sampling rate having a second sampling frequency (f₂) different from said first sampling frequency (f₁), comprising: oversampling means (4) receiving said input digital signal (DG₁) for oversampling the latter at a rate which is an integral multiple of said first sampling frequency (f₁) so as to generate zero values between data of said input digital video signal (DG₁) ; means (2') connected to said oversampling means (4) for interpolating an output signal (DG OVR ) therefrom; decimating means (5) for generating therefrom a digital signal (DG₁₀) having said second sampling frequency; and low pass filter means (3) for eliminating an undesired signal component due to the converting of the sampling rate and which appears between frequency bands of one-half of said first (f₁) and second (f₂) sampling frequencies, respectively; characterized in that the input digital signal (DG₁) is a digital video signal (DG₁) ; said decimating means (5) is arranged to act on the interpolated output signal (DG OVR ) to generate an intermediate output digital video signal (DG₁₀); and said low pass filter means (2) is arranged to receive said intermediate output digital video signal (DG₁₀) to eliminate therefrom the undesired signal component. A sampling rate converting apparatus according to claim 1; in which said second sampling frequency (f₂) is larger than said first sampling frequency (f₁). A sampling rate converting apparatus according to claim 2; in which said low pass filter means (3) has a cut off frequency which is one-half of said first sampling frequency (f₁). A sampling rate converting apparatus according to claim 3; in which input digital video signal (DG₁) having said first sampling frequency (f₁) is a component-type video signal. A sampling rate converting apparatus according to claim 4; in which said first sampling frequency (f₁) is 13.5 MHz. A sampling rate converting apparatus according to claim 4; in which said digital video signal (DG₂) having said second sampling frequency (f₂) is a composite-type video signal. A sampling rate converting apparatus according to claim 6; in which said component-type video signal and said composite-type video signal are both PAL signals. A sampling rate converting apparatus according to claim 7; in which said first (f₁) and second (f₂) sampling frequencies are 13.5 MHz and 17.734 MHz, respectively. A sampling rate converting apparatus according to claim 8; in which said low pass filter means (3) includes a finite impulse response type digital filter. A sampling rate converting apparatus according to claim 8; in which said interpolating means (2') includes a finite impulse response type digital filter.

Inventors: FUJITA TADAO, NINOMIYA TAKESHI, TAKAYAMA JUN, FUJITA, TADAO, NINOMIYA, TAKESHI, TAKAYAMA, JUN, FUJITA, TADAO, C/O SONY CORPORATION, NINOMIYA, TAKESHI, C/O SONY CORPORATION, TAKAYAMA, JUN, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H04N7
IPC codes: H04N7, H03H17