Wiring-pattern-determination system and method

Abstract: A wiring-pattern-determination system comprises a label setting unit (111) for setting labels from a starting point to an ending point by performing a labeling utilizing a maze running; and a reference point setting unit (121) for setting a corner of a wiring pattern to be determined or the ending point as a reference point for a back-trace of the maze running. The wiring-pattern-­ determination system has a corner judging unit (131) for judging the next corner as the next reference point based on the label set at the reference point, a ter­ mination judging unit (141) for judging the termination of the back trace when the starting point and the corner determined by the corner judging unit (131) match and a reference point revising unit (151) for instructing the reference point setting unit to set the next corner as a new reference point when the starting point and the corner determined by the corner judging unit (141) mismatch. In the back trace, the wiring pattern is immediately and quickly determined between the corner and the next corner obtained by the corner judging unit (141).

Description: Background of the Invention This invention relates to a wiring-pattern-determination system and method for designing wiring patterns of a PC board or LSI chip based on maze running. For instance, the problem of large scale combination including LSI CAD such as of wiring processing requires very high speed processing. The method can be speeded up by high speed processing of a massively paralle computer containing numerous processors. Maze running is an algorithm to find path of given two points in the shortest lengths, and is widely used for routing patterns of a PC board or LSI chip. In maze running, the plane in consideration comprises grid points which are wiring units. The source (originating point) and target ( end point) are set on grid points in the first stage. Then a labeling and a back-trace are used to determine the wiring pattern (net). Here, the labeling assigns the label n+1 to a grid point neighboring the nth empty (without an interference) grid point from the source, e.g., assigning label 1 to an empty grid point neighboring the source and assigning label 2 to an empty grid point neighboring the grid point assigned to label 1, until there is no more neighboring grid point or the label has reached the target. A back-trace traces back each grid point assigned to a label starting from the target to the source so that the numbers of the labels assigned to each grid point are reduced by one. Recently, as the PC board and LSI chip are increasing the density, the amount of data in consideration by maze running, i.e., the data scale handled, is increased. Then the speed up of a wiring processing is desired, and a specialized hardware and parallel processing has been tried. For instance, a processor is assigned in one-to-one correspondance to each grid point and a communication port connects between neighboring processors. Each processor on a wavefront (the grid point with the same label) is parallel activated in labeling, and labels to the neighboring processors travel done in parallel. The processor on the wavefront processes in parallel to speed up the method. However, it is a problem that the back-trace cannot be speeded up by the parallel processing easily. In the back trace, a wiring path is determined by tracing back to the processor corresponding to the source via the label assigned in the labeling from the processor corresponding to the target. While only two processors communicate information of the path, all other processors are standing by at a particular point in time. Hence, a disadvantage of the parallelism exists in the processing not fully exploited as a whole. From IEEE Trans. on CAD of INTEGRATED CIRCUITS AND SYSTEMS, vol. CAD-6, no. 2, March 1987, pages 241-250; T. Watanabe et al.: "A parallel adaptable routing algorithm and its implementation on a two-dimensional array processor" a wiring-pattern determination system and a wiring-pattern-determination method is known, wherein a plurality of processors are connected in a processor array. Labels are set to each of the processors from a beginning point to an ending point by performing a labeling operation utilizing a maze running. Then, a corner of a wiring pattern to be determined is set by setting the ending point as a reference point assigned with a label for a back-trace of the maze running and a next corner as a next reference point is determined based on the label assigned to the reference point. Finally, the termination of the back-trace is determined when the beginning point and the next corner determined before match. Otherwise, the next corner is set as the next reference point. However, according to this reference, no parallel processing is disclosed when the back-tracing is carried out. Summary of the Invention The object of the present invention is to provide a wiring-pattern-determination system and a wiring-pattern-determination method for speeding up the back-trace of maze running. According to the invention, this object is achieved by a wiring-pattern-determination system according to claim 1 and a wiring-pattern-determination method according to claim 8. According to the present invention, parallel back-tracing is performed by using a collection logical operation circuit connected to each of the processor elements which are connected in a processor array. Brief Description of the Drawings Figure 1 is a principle block diagram of the wiring-pattern-determination system of this invention, Figure 2 is a configuration diagram of the preferred embodiment of this invention, Figure 3A is a block diagram of a collection logical operation circuit used in the preferred embodiment, Figure 3B is a table that shows the content of the processor memory and global memory of this embodiment, Figures 4A through 4D explain how the labeling of this embodiment progresses, Figure 5 is a flow chart explaining the operation of the labeling of this embodiment. Figures 6A through 6G explains the back-trace of the embodiment, and Figures 7A and 7B are flow charts explaining the operation of the back-trace of this embodiment. Preferred Embodiment of the Invention Figure 1 is a principle block diagram of the wiring-pattern-determination system of this invention. In Figure 1, a label setting means 111 assigns a label from the origin to the end point by performing a labeling according to the maze running. A reference point setting means 121 sets a corner of the wiring pattern to be determined or the end point, as a reference point of the back-trace of the maze running. A corner judging means 131 determines the next corner of this reference point, based on the label assigned to the reference point set by the reference point setting means 121. A termination judging means 141 judges a termination of a back-trace when the origin and the corner determined by the corner judging means 131 match. When the origin and the corner determined by the corner judging means 131 mismatch, a reference point revising means 151, instructs a setting of the corner as a new reference point using the reference point setting means 121. Consequently, the determination of wiring pattern by the back-trace is configured to be made entirely in a unit of a corner. The label setting means 111 assigns labels from the origin to the end point according to the maze running. Then, the following back trace is made. First, the reference point setting means 121 sets the end point as the reference point. Based on this label assigned to this reference point, the corner judging part 131 detects the corner or bending angle next to the reference point (the end point) on a wiring pattern. The termination judging means 141 judges whether or not the detected corner is an origin, i.e., whether the back whether trace is completed. If the detected corner is not an origin, the reference point revising means 151 sends an instruction to the reference point setting means 121 to revise the reference point. The reference point setting means 121 then resets the corner detected by the corner detecting means 131 as the new reference point. Later, similar processings are performed by detecting the next corner for the new reference point, until the detected corner reaches the origin. In this invention, since the detection of the next corner by setting the corner as the reference point determines the wiring pattern, the bee line path between corners is determined immediately. The following is a detailed description of an embodiment of this invention by referring to Figure 2. Figure 2 shows a configuration of the embodiment applied to the wiring-pattern-determination system of this invention, and is for determining the wiring pattern of a PC board or an LSI chip by applying the maze running. In Figure 2, 211 is a processor array, 213 is a processor element (PE), 221 is a collection logical operation circuit; 231 is a global memory, and 241 is a controller. The processor array 211 is a plurality of processor elements 213 connected in a two dimensional matrix. Each processor element 213 corresponds to a grid point labeled by the maze running, and a communication port connects neighboring processor elements 213. At a labeling, labeling information is transmitted to the neighboring processor element 213 via this communication port. Each processor element 213 comprises a processor memory for retaining various data necessary for wiring, an operation circuit for executing an operation for these data, and four communication ports for communicating with the neighboring processor elements 213. The collection logical operation circuit 221 is connected to all the processor elements 213 of the processor array 211, and makes a predetermined operation for all output data. Predetermined operations include logical product, logical sum, addition, maximum value computation, minimum value computation and the like. The detailed configuration of the collection logical operation circuit 221 comprises a plurality of operation circuits (LU) 321, 323, ...., 329 of a tree structure, as shown in Figure 3A. Each operation circuit executes the above predetermined operation for the two inputs, and the kind of operation is instructed by the controller 241. Each pair of processor elements 213 is connected with an operation circuit 321. Each operation circuit 321 makes a predetermined operation for the output data from two corresponding processor elements 213 and inputs the operation result to the operation circuit 323 of the next stage. Likewise, the operation circuit 323 performs the predetermined operation for the output data from the two operation circuits 321. Finally, the result of the predetermined operations for the output data from all the processor elements 213 is outputted from the operation circuit 329 of the final stage. These output data are outputted as the operation result of the collection operation circuit means. Generally, regarding the processor array 211 having 2 n pieces of processor elements 213, 2 n pieces of input are inputted to an operation circuit 321 in the first stage of the collection logical operation circuit 221. The operation circuit 321 sends 2 n ×1/2=2 n-1 pieces of output to an operation circuit 323 in the second stage. Accordingly, to obtain one output (e.g. a maximum) from the outputs from 2 n pieces of the processor elements 213, a use of the collection logical operation circuit 221 comprising n stages of operation circuits is sufficient. A concrete example of the collection logical operation circuit 221 is disclosed in Japanese Patent Application No. 1988-234545. The global memory 231 retains the common data sent to all the processor elements 213 and retains the operation result of the collection logical operation circuit 221 after receiving it. The controller 241 gives an operating instruction such as operation execution and data input/output for each processor element 213, as well as an operating instruction such as the operation execution and the kind of operation to the collection logical operation circuit 221 and performs a sequential control for determining the wiring pattern by the maze running. Figure 3B shows the data content of the processor memory (not shown in the drawings) set in each processor element 213 and in the global memory 231. The content of the global memory 231 comprises an arrow directional label (4 bits), coordinate X (16 bits) and coordinate Y (16 bits). The content of the processor memory comprises a wiring prohibition flag (1 bit), a source flag (1 bit), a target flag (1 bit), an arrow (North) directional label (1 bit), an arrow (East) directional label (1 bit), an arrow (South) directional label (1 bit), an arrow (West) directional label (1 bit), coordinate X (16 bits), coordinate Y (16 bits), a back-trace starting point flag (hereafter referred to as a starting point flag: 1 bit), and a back-trace starting point candidate flag (hereafter referred to as a candidate flag: 1 bit). Also, hereafter the arrow directional label and the arrow directional label flag are both called directional labels. The following is an explanation of the operation when the maze running is applied to the embodiment of the above configuration. Labeling and back-trace are explained separately. (i) labeling Figures 4A through 4D outlines the labeling of the embodiment. Figure 5 shows its operating process. In the embodiment, a plane divided into 9×13 grid points, as shown in Figure 4A, is considered, and each processor element 213 corresponds to a grid point. The processor element 213 corresponding to the grid point (the shadowed area in Figure 4A) having an interference (line alignment prohibited area 411) does not participate in the processing of a wiring pattern determination, for instance with its operation being halted. Suppose first the controller 241 performs a labeling with the grid point of coordinate (3-H) as a source, S and the grid point of coordinate (8-H) as a target T, to determine the wiring path from the source S to the target T. Suppose also that the controller 241 gives operational instructions to each processor element 213, collection logical operation circuit 221, and the global memory 231. Step A1: (initialization) The controller 241 clears the variables, "source flag", "target flag", "directional label", "coordinate X", "coordinate Y", "starting point flag", and "candidate flag" of the processor memory in each processor element 213. Step A2: (setting of a source) The controller 241 gives an instruction to the processor element 213 in the grid point of coordinate (3-H) corresponding to a source. This processor element 213 then sets a seal S meaning a source to the variable "source flag" in its processor memory. Step A3: (selection of a target) The controller 241 gives an instruction to the processor element 21 3 of coordinate (8-H) corresponding to a target. This processor element 213 then sets a variable "target flag" to "1" in the processor memory. All other processor elements 213 then set their own variable "target flag" to "0" in the processor memory. Step A4: (transmission of a label) Only the processor element 213 not in the wiring-pattern alignment prohibited area 411, whose variables "directional label", "coordinate X", "coordinate Y", "starting point flag", and "candidate flag" are in the cleared condition, performs the following processings. In the labeling of this embodiment, a label is expressed directionally by an arrow in lieu of a number. The four directions pointed to by the arrow are expressed by a few bit data (e.g. 4 bits). First, as shown in Figure 4A, numbers are assigned from the source S to its neighboring grid points using the wavefront method. Second, as shown in Figure 4B, the number is incremented until the grid point to which the number is assigned contains the target T. Second, as shown in Figure 4C, an arrow is assigned to each grid point, so that the arrow direction points from the grid point of a larger number to the grid point of a smaller number. In a grid point having two or three neighboring grids with a smaller number, any of the arrow directions may be determined in accordance with the predetermined priority. In this embodiment, an arrow pointing East or West has priority over an arrow pointing North or South. For example, in Figure 4B, the two grid points, each assigned with a number, are determined to have an East or West arrow direction in accordance with the priority, although East-West or North-South arrow directoiins are considered for the grid point where "2" is assigned, with respect to the two neighboring grid points where the number "1" is assigned, as shown in Figure 4C. As a result, an arrow direction as shown in Figure 4C is assigned to each grid point. This kind of arrow direction assignment operation is performed in all grid points pursuant to the numbers shown in Figure 4B. As a result, as shown in Figure 4D, arrow directions are assigned to all grid points. This corresponds to a storage of "1" in any of the (North, East, South, or West) directional labels. The above description explains the case of determining the arrow direction based on a numeric label. The arrow direction of each neighboring grid point is set to point to the grid point itself. When any of the four directions is considered as a neighboring grid point, the East-West directions have priority over the North-South directions. When an arrow direction is used in lieu of a number for the label, the arrow directions of all grid points are determined as shown in Figure 4D. In this manner, each processor element 213 concurrently determines the variable "directional label". Step A5: (reading of a target) When the determination of the variable "directional label" of each processor element 213 is completed, the processor element 213 corresponding to the target and all other processors respectively outputs the determined value of the variable "target flag", i.e., "1"; and that of the variable "target flag", i.e., "0" to the collection logical operation circuit 221. The collection logical operation circuit 221 outputs the maximum calculated from the output of each processor element 213. This output is simply the value of the variable "target flag" of the processor element 213 corresponding to the target, and is sent to the controller 241 via the global memory 231. Step A6: (termination judgment) The controller 241 judges whether or not the value of the variable "target flag" of the processor element 213 corresponding to the target is in the cleared condition. If it is, the assignment of a directional label per labeling has not reached the target. The controller 241 judges positively and goes back to step A4 and repeats the processings. If the variable "target flag" is not in the cleared condition, i.e., if the variable "target flag" is "1", it indicates the assignment of the directional label flag has reached the target. Therefore, the controller 241 judges negatively and terminates the processing related to labeling. (ii) back-trace Figures 6A through 6G show how the back-trace of the embodiment progresses, and Figures 7A and 7B show the operating procedures of the back-trace. Each processor element 213 retains its own coordinate grid point (the coded value of e.g. the grid point of coordinate (2-H)) in its own processor memory. In Figures 6A through 6F, a rectangular mark indicate current starting points, 611, 621, 631, 641, 651 and 661; a thin ecliptic mark indicates grid points 612, 622, 632, 642, 652 and 662 on the same Y coordinate as the starting point; a bold elliptic circle indicates starting point candidate grid points 613, 623, 633, 643, 653 and 663; a circular mark indicates the next starting point grid points 614, 624, 634, 644, 654 and 664; and a bold solid bee line indicates wiring patterns 625, 635, 645, 655 and 665 determined as the back-trace progresses. In Figure 6A, the target T on the grid point of the coordinate (8 H) is set as starting point 611. First, as the directional label of starting point 611 points in the positive direction of coordinate X (the East direction), all grid points 612 on the X coordinate in the same and opposite directions of the arrow direction in the grid point of starting point 611 are detected. Second, a grid point having a larger X coo rdinate value is set as starting point candidate grid point 613. As later described, the grid point with the least X coordinate value is determined from among starting point candidate grid points 613 and is set as the next starting point grid point 614. Then, as shown in Figure 6B, the wiring pattern 625 is determined from starting point grid point 611 to the next starting point grid point 614, and wiring pattern 625 is determined immediately. Similar processings are repeatedly performed as shown in Figures 6B through 6F, so that a wiring pattern is formed from the target T to the source S, as shown in Figure 6G. The operation of the back trace will be explained by refering to Figure 7A. Step B1: (initialization) The controller 241 assigns "1" and "0", respectively, to a variable "starting point flag" in the processor memory of the each processor element 213 corresponding to the target and the processor elements 213 not corresponding to the target. Step B2: (reading the information at a search starting point) The processor element 213 whose variable "starting point flag" "1" is initially assigned to the processor element 213 corresponding to the target, outputs the flag of the variable "directional label" (which is the direction of the arrow assigned in the labeling) and its coordinate value to the collection logical operation circuit 221. All other processor elements 213 output "0" as the variable "directional label" and the coordinate value to the collection logical operation circuit 221. The collection logical operation circuit 221 outputs the maximum of each processor element 213, obtained from the calculation of the compared value of the output from each processor element 213. These outputs (the flag of the variable "directional label" and the value of the variable "coordinate value") are respectively stored in the variable "directional label" and the variable "coordinate value" of a global memory 231. Step B3: (initialization of a candidate flag) The controller 241 assigns "0" to a variable "starting point candidate flag" in the processor memory of all processor elements 213. Step B4: (determination of a candidate of the next corner) The controller 241 inputs (broadcasts) each value of the variable "directional label" and the variable "coordinate value" of the global memory 231 to all processor elements 213. Each processor element 213 inputted with these values assigns "1" to the variable "candidate flag", when the following conditions [1] and [2] are met. Condition [1]: The processor element 213 is located in the direction of the arrow shown in the variable "directional label" viewed from the grid point shown in the variable "coordinate value" inputted from the global memory 231. That is, the processor element 213 is located on the line drawn in the direction of the arrow shown in the variable "directional label" from the grid shown as the variable "coordinate value". Condition [2]: An arrow direction different from that shown in the variable "directional label" of the global memory 231 is set to its own variable "directional label" in the processor element 213. The above condition [1] is shown more concretely in the flow chart of Figure 7B. First, the variables "directional label" and "coordinate value" are inputted to the controller 241 (B40). Then, when the arrow direction points East or West (B41), it is judged whether or not the "Y coordinate value" of the processor memory and the "Y coordinate value" of the starting point stored in the global memory 231 match (B42). Among those that match (like grid point 612 shown with a thin elliptic circle in Figure 6A), when the variable "directional label" in the processor memory points in the positive direction of the X coordinate (B43), the grid (starting point candidate grid 613 marked by a bold elliptic circle shown in Figure 6A) having a processor element 213 whose processor memory has a larger X coordinate value than the X coordinate value of the starting point (B44) is judged as a corner candidate (B45). When the Y coordinate value of the processor memory and the Y coordinate value of the starting point do not match (B46), a grid having such a processor memory is not a candidate for a starting point or a corner (B47). Also, a processor memory whose X coordinate value is not larger than the X coordinate value of the starting point (B44) is not a candidate (B47). If the arrow direction of the processor memory is not positive, when the X coordinate value of its processor memory is smaller than the X coordinate value of the starting point (B46), it is judged as a candidate (B45); but if it is not smaller, it is not judged as a candidate (B47). If the variable "directional label" is not horizontal (East or West), processing is performed at each of the steps B42′, B43′, B44′, B45′, B46′ and B47′ in Figure 7B, as at each of the steps B42, B43, B44, B45, B46, and B47. Step B5: (detection of the next corner) The processor element 213 in which "1" is assigned to variable "candidate flag", outputs the coordinate element in the arrow direction shown in the variable "directional label" of the global memory 231 to the collection logical operation circuit 221, the coordinate element being selected from the coordinate values of the processor element 213. For instance, in Figure 4D, when the East direction is assigned to the variable "directional label" of the global memory 231, the processor element 213 (the processor element 213 on the grid point of coordinate (12-H)) in which "1" is assigned to variable "candidate flag" outputs the arrow direction element among its coordinate values, i.e. the horizontal direction element (the coded value of 12). The processor element 213 whose "candidate flag" "0" is assigned, outputs the expressible maximum (e.g. when the coordinate value is coded in eight bits, all bits are set to "1".) to the collection logical operation circuit 221 if the arrow direction shown in the variable "directional label" of the global memory 231 is in tle positive direction; and the processor element 213 outputs "0" to the collection logical operation circuit 221, if the arrow direction shown in the variable "directional label" of the global memory 231 is in the negative direction. The collection operation logical circuit 221 computes the minimum or the maximum, respectively, when the arrow direction shown in the variable "directional label" of the global memory 231 is the positive direction or the negative direction. The coordinate of the first processor element 213 located in this arrow direction but of a different direction (the coordinate in the arrow direction) is determined by computing the minimum or the maximum, depending on the arrow direction. For instance, in Figure 6A, the arrow directions of both the next starting point 614 and its right neighboring grid point 615 are different from the arrow direction of the target starting point 611. Since the next starting point 614 is a first grid whose arrow direction is different from that of the target, it is determined as the next corner. The result of the logical operation is stored in the element of the arrow direction shown in the variable "directional label" among the variable "coordinate values" in the global memory 231. The controller 241 designates the computation of either the minimum or the maximum at the collection logical operation circuit 221. Step B6: (termination judgment) The controller 241 reads the variable "coordinate value" in the global memory 231, and judges whether or not this value indicates the source. In case of a positive judgment when the back-trace has reached the source, the controller 241 terminates processings related to the back-trace. In case of a negative judgment, the controller 241 continues the following operations. Step B7: (setting of a new search starting point) The controller 241 broadcasts the value of the variable "coordinate value" in the global memory 231 to all processor elements 213. It then compares the inputted value of the variable "coordinate value" with its own corrdinate value and sets the variable "starting point flag" in the processor memory to "1" or "0", respectively, whether the compared values are the same or not same. Then, the controller 241 goes back to step B2 and repeats the processings. Thus, each corner of the wiring pattern to be determined is referenced and the next corner is obtained along the label (the arrow direction shown in the variable "directional label" in the global memory 231), the label corresponding to this corner. This operation is performed for each corner, and the wiring pattern is determined, until the back-trace finally reaches the source. For example, as shown in Figure 6G, the grid point of coordinate (12-H) is detected as the first corner; then the grid points of coordinates (12-E), (7-E), (7-C) and (3-C) are detected as the next corners in step B5; and finally source grid point of coordinate (3-H) is detected. The path connecting the center of each grid point of these coordinates becomes the wiring pattern. Therefore, the bee line paths between two consecutive corners are determined at once when a back-trace is performed, and the processing is sped up. Generally the number N of grid points corresponding to the total length of a wiring pattern is far greater than the number M of corners (i.e. N » M), and the time required for the processing is shortened to approximately M/N. In the embodiment of this invention described above, the memory in each processor element 213 secures storage areas for such variables as "starting point" and "coordinate value". But specialized hardware can be used, by providing such registers as a starting point register and a coordinate value register specifically for storing the values of such variables. Also the embodiment explains how the determination of the wiring pattern on a plane is determined. This invention is also applicable to the determination of the wiring pattern for a multilayer PC board, etc. As described so far, this invention determines the wiring pattern by detecting the next corner of this reference point based on the label corresponding to a reference point. Since the back-trace of the maze running is sped up by determining the bee line paths between two consecutive corners at once, this invention is extremely practical.

Claims: An automatic wiring-pattern-determination system including processors (213) connected in a processor array (211), each grid point having a processor (213) with its own processor memory, comprising: label setting means (A1-A6, 111) for setting labels corresponding to each of said processors (213) from a starting point (S) to an ending point (T) by utilizing a maze running, wherein an arrow is assigned to each of said labelled grid points so that its direction points to the neighbour grid point having a smaller number, and storing each of said labels and arrows in the respective processor memory; reference point setting means (B2, 121) for setting a corner of a wiring pattern to be determined by initially setting said ending point (T) as a reference point assigned with a label for a back-trace of said maze running, said reference point setting means including a tree-structured collection logical operation circuit (221) connected to all said processors (213); corner judging means (B3...B5,131) for determining a next corner of said wiring pattern as a next reference point by broadcasting the coordinates and the arrow direction of the present reference point to all processors (213) so that the next corner can be selected from all processors (213) being located on the line drawn in the present reference point's arrow direction and in addition having an arrow direction different from said present reference point's arrow direction; termination judging means (B6,141) for determining a termination of said back-trace when said starting point (S) and said next corner determined by said corner judging means (131) match; and reference point revising means (B7,151) for instructing said reference point setting means (121) to set said next corner as said new reference point when said starting point (S) and said next corner determined by said corner judging means (131) mismatch. A wiring-pattern-determination system according to claim 1, wherein said label setting means (111) comprises: means for initializing each processor element (213) including source and target processor elements; means for setting a source at said source processor element provided at said starting point (S) of said wiring pattern; means for setting a target at said target processor element at said ending point (T) of said wiring pattern; means for sequentially transmitting a label from said source to said target; means for determining whether said label has been transmitted until said label is transmitted to said target; and means for ending said labeling operation when said label has been transmitted to said target. A wiring-pattern-determination system according to claim 2, wherein said means for determining comprises means for reading a target flag in each of said processor elements (213), for determining whether said target flag is cleared and for transmitting said label to an adjacent processor element (213). A wiring-pattern-determination system according to claim 1, wherein said reference point setting means (121) reads said starting point (S) for said back-trace, and said corner judging means (131) comprises: means for initializing a candidate flag in each processor element (213); means for determining corner candidates; and means for determining said next corner selected from said corner candidates. A wiring-pattern-determination system according to claim 4, wherein said means for determining corner candidates comprises: means for determining whether a particular processor element (614, 624, 634, 644, 654) is on a line drawn in the arrow direction of said reference point (611, 621, 631, 641, 651 , 661) from a coordinate of said reference point (611, 621, 631, 641, 651, 661) ; and means for determining whether said arrow direction of said particular processor element (614, 624, 634, 6444, 654) is different from said arrow direction of said reference point (611, 621, 631, 641, 651, 661), and said means for determining said next corner selects a minimum coordinate from said corner candidates when said arrow direction of said reference point (611, 621, 631, 641, 651, 661) is positive or selects a maximum coordinate from said corner candidates when said arrow direction of said reference point (611, 621, 631, 641, 651, 661) is negative. A wiring-pattern-determination system according to claim 5, wherein said means for determining said next corner comprises said collection logical operation circuit (221) including a plurality of stages of comparison cirucits (321, 323, 329), each having a first stage of said comparison circuits (321) which receives outputs of two processor elements (213) and a last stage of said comparison circuits (329) for providing a maximum or minimum output. A wiring-pattern-determination system according to claim 4, wherein said means for determining corner candidates comprises: means for detecting whether an arrow direction in a particular processor element (213) having X and Y coordinates is horizontal; means for detetcting whether said Y coordinate of said particular processor element (213) is the same as that of said reference point when said arrow direction of said particular processor element (213) is horizontal; means for determining whether said arrow direction of said reference point is positive; and means for determining whether said X coordinate of said particular processor element (213) is larger than that of said reference point and for determining that said particular processor element (213) is a candidate of said X coordinate of said particular processor element (213) and is larger than that of said reference point. An automatic wiring-pattern-determination method implemented by a computer including processors (213) connected in a processor array (211), each grid point having a processor (213) with its own processor memory, comprising the steps of: (a) setting labels corresponding to each of said processors (213) from a beginning point (S) to an ending point (T) by performing a labeling operation utilizing a maze running, wherein an arrow is assigned to each of said labeled grid points so that its direction points to the neighbour grid point having a smaller number, and storing each of said labels and arrows in the respective processor memory (A1...A6); (b) setting a corner of a wiring pattern to be determined by initially setting said ending point (T) as a reference point assigned with a label for a back-trace of said maze running (B2), said reference point setting being based on a tree-structured collection logical operation circuit (221) connected to all said processors (213); (c) determining a next corner as a next reference point based on the label assigned to said reference point by broadcasting the coordinates and the arrow direction of the present reference point to all processors (213) so that the next corner can be selected from all processors (213) being located on the line drawn in the present reference point's arrow direction and in addition having an arrow direction different from said present reference point's arrow direction (B3-B5); (d) determining a termination of said back-trace when said beginning point (S) and said next corner determined by said determining step (c) match (B6); and (e) setting said next corner as said next reference point when said beginning point (S) and said next corner determined by said determining step (c) mismatch (B7).

Inventors: KAWAMURA KAORU, SHINDO TATSUYA, KAWAMURA, KAORU, SHINDO, TATSUYA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G06F17
IPC codes: G06F17, H01L21