A semiconductor memory device

Abstract: A semiconductor memory device in which the operation rate of each sense amplifiers is improved is disclosed. The memory device comprises: a sense amplifier block in which block a plurality of sense amplifiers are arranged in a row; a current source disposed in the vicinity of one end of the sense amplifier block: a first wiring connected commonly to the sense amplifiers, one end of the first wiring being connected to said current source; and a second wiring connecting the current source with one of the sense amplifiers which is most separated from the current source.

Description: This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an improved circuitry for supplying currents to sense amplifiers as defined in the preamble of claim 1. A semiconductor memory device includes a plurality of memory cell blocks each comprising a plurality of memory cells which are connected to a pair of bit lines. Conventionally, a sense amplifier is disposed for each memory cell block to amplify a microvoltage read from memory cells of the corresponding memory cell block via the pair of bit lines. The sense amplifiers are arranged in a row at one end of the memory cell blocks to form a sense amplifier block. With a higher degree cf integration of semiconductor memory devices, a memory cell block involves an increased number of memory cells therein, which leads to an increase of the number of memory blocks and an increase of the number of sense amplifiers provided in corresponding relation to the memory blocks. This results in increased parasitic resistance caused by a wiring (hereinafter, such resistance is referred to as merely "parasitic resistance"), and accordingly in a reduced rate of reading data from memory cells. However, a strong market demand exists for a highly integrated semiconductor memory device which can perform high-rate data reading. The structure of a conventional semiconductor memory device as it is known e.g. from IEEE JOURNAL OF SOLID STATE CIRCUITS, vol. 22, no. 5, October 1987, pages 651-656, New-York, US; K. KIMURA et al.: "A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier" (see preamble of claim 1) will be described more specifically with reference to Figure 7. The memory device of Figure 7 comprises sense amplifiers SAM₁, SAM₂, ..., SAM n for amplifying respectively signals from pairs of bit lines BLA₁ and BLB₁, BLA₂ and BLB₂, ..., BLA n and BLB n . These sense amplifiers SAM₁ - SAM n constitute a sense amplifier block 10. Each of the pairs of bit lines BLA₁ and BLB₁, BLA₂ and BLB₂, ..., BLA n and BLB n is connected commonly to a group of memory cells, which constitute a memory cell block. In Figure 7, only memory cells CE₁ - CE n to which signals are commonly given from word lines WL₁ and WL₂ are shown for individual memory cell blocks, and other memory cells are not shown. The memory cells CE₁ CE₂, ..., CE n respectively comprise memory cell transistors QA₁, QA₂, ..., QA n each having a gate connected to the word line WL₁, memory cell transistors QB₁, QB₂, ..., QB n each having a gate connected to the word line WL₂, memory cell capacitances CA₁, CA₂, ..., CA n connected to the memory cell transistors QA₁, QA₂, ..., QA n respectively and also to a line 3 to which a cell plate voltage V cp is applied, and memory cell capacitances CB₁, CB₂, ..., CB n connected to the memory cell transistors QB₁, QB₂, ..., QB n respectively and also to the line 3. When signals are supplied from the word lines WL₁ or WL₂, data retained in the memory cells CE₁ - CE n are sent to the pairs of bit lines BLA₁ and BLB₁ - BLA n and BLB n . The sense amplifier SAM₁ includes P-channel transistors QPA₁ and QPB₁, and N-channel transistors QNA₁ and QNB₁. To the source of each of the P-channel transistors QPA₁ and QPB₁, a current is supplied through a wiring SAP from a current source 1 which comprises a P-channel transistor QSA P , and, to the source of each of the N-channel transistors QNA₁ and QNB₁, a current is supplied through another wiring SAN from another current source 2 which comprises an N-channel transistor QSA N . The gates of the transistors QPA₁ and QNA₁ and the drains of the transistors QPB₁ and QNB₁ are commonly connected to the bit line BLB₁, and the gates of the transistors QPB₁ and QNB₁ and the drains of the transistors QPA₁ and QNA₁ are commonly connected to the bit line BLA₁. The other sense amplifiers SAM₂ - SAM n are constructed similarly. In Figure 7, V cc designates a power source voltage, and G P and G N designate respective gates of the transistors QSA P and QSA N . When the potential of the word line WL₁ is raised to HIGH, data stored in the memory cell capacitances CA₁, CA₂, ..., CA n are supplied to the bit lines BLA₁, BLA₂, ..., BLA n via the memory cell transistors QA₁, QA₂, ..., QA n . When, for example, the data supplied to the bit line BLA₁ is "H" (which is the data representing the H level), the voltage of the bit line BLA₁ is higher than that of the bit line BLB₁ by several hundreds of millivolts, so that the transistors QPA₁ and QNB₁ in the sense amplifier SAM₁ are turned on. Once an H level signal is given to the gate G N of transistor QSA N of the current source 2, the current source 2 begins to conduct the current withdrawal against the wiring SAN, whereupon the transistor QNB₁ which is in the conductive state begins to lower the voltage of the bit line BLB₁. On the other hand, an L level signal is inputted to the gate G P of the transistor QSA P of the current source 1 with a slight lag behind the timing of the application of the H level signal to the gate G N . Then, the current source 1 begins to supply current to the wiring SAP so that the transistor QPA₁ in the conducting state boosts the voltage in the bit line BLA₁. During this process, the transistors QNA₁ and QPB₁ do not operate. Such voltage changes in the bit lines BLA₁ and BLB₁ are shown respectively by vurves La₁ and Lb₁ in Figure 8. The difference between the voltages thus read on bit lines BLA₁ and BLB₁ which indicates the stored data is amplified by the sense amplifier. Figure 9 shows a simplified equivalent circuit of the sense amplifier block 10 comprising the sense amplifiers SAM₁ - SAM n . In Figure 9, R₁ and R₂ represent parasitic resistances in the wirings SAN and SAP, respectively. To simplify the illustration, only transistors which are at the turn-on state in the above-described condition are shown in the sense amplifier block 10. When the current source 2 begins to withdraw current from the wiring SAN, a voltage drop occurs in the wiring SAN because of the presence of the parasitic resistance R₁. Accordingly, the gate-source voltages in the transistors QNB₁ and QNB n change in such a way that the voltage in transistor QNB n is smaller, thereby causing a delay in the sense operation of the sense amplifier SAM n which is most remote from the current source 2. In Figure 8, curves La n and Lb n show voltage changes in the bit lines BLA n and BLB n , respectively. From Figure 8, it can be understood that there is some lag in voltage drop in the bit line BLB n as compared in the bit line BLB₁. In such a semiconductor memory device, the data reading rate depends on the sense operation speed of the sense amplifier SAM n which is most remote from the current source 2, and moreover the sense operation speed is determined by the length of the wiring extending from the current source 2 to the sense amplifier SAM n (that is, the magnitude of parasitic resistance therein). Therefore, in a highly integrated semiconductor memory device involving a long length of wiring SAN, the problem of increased read time is inevitable. The semiconductor memory device of this invention, which overcomes the above-discussed and numerous other disadvantages and deficiencies of the prior art, comprises a sense amplifier block in which block a plurality of sense amplifiers are arranged in a row; and a current source disposed in the vicinity of one end of said sense amplifier block, said memory device further comprises: a first wiring connected commonly to said sense amplifiers, one end of said first wiring being connected to said current source; and a second wiring connecting said current source with the other end of said first wiring at one of said sense amplifiers which is most separated from said current source. A preferred embodiment of the semiconductor memory device, according to the invention, comprises: a sense amplifier block in which block a plurality of sense amplifiers are arranged in a row; and a current source disposed in the vicinity of one end of said sense amplifier block, said memory device further comprises a strip including said first and said second wirings and made of a conductor material, said strip elongating along said row of said sense amplifiers, one end of said strip being connected to said current source, said strip being divided into first and second sections by a slit to form said first and said second wirings, which slit elongates along said row of said sense amplifiers, said first and second sections being connected with each other at both ends, said first section being connected to said current source and commonly to said sense amplifiers, said second section connecting said current source with one of said sense amplifiers which is most separated from said current source. In a preferred embodiment, the memory device further comprises a resistance means which is connected between said current source and said one end of said first wiring. Thus, the invention described herein makes possible the objectives: (1) providing a semiconductor memory device which has a high reading rate; (2) providing a semiconductor memory device in which sense amplifiers can operate at higher speed; and (3) providing a semiconductor memory device in which the voltage drop caused by parasitic resistance can be effectively reduced even if a wiring for supplying current to sense amplifiers is long. This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1 is a circuit diagram showing a first embodiment of the invention. Figure 2 is an equivalent circuit diagram of the vicinity of the sense amplifiers of the embodiment of Figure 1. Figure 3 is a graph showing voltage drops in a wiring of the embodiment of Figure 1. Figure 4 is a circuit diagram showing a second embodiment of the invention. Figure 5 is a circuit diagram showing a third embodiment of the invention. Figure 6 is an equivalent circuit diagram of the vicinity of the sense amplifiers of the embodiment of Figure 4. Figure 7 is a circuit diagram showing a conventional memory device. Figure 8 is a graph showing voltage drops in a wiring of the memory device of Figure 7. Figure 9 is an equivalent circuit diagram of the vicinity of sense amplifiers of a memory device. Figure 1 is an electric circuit diagram showing a basic arrangement of a semiconductor memory device according to the invention. In Figure 1, elements similar to those shown in Figure 7 are designated by the same reference numerals. In the semiconductor memory device of Figure 1, a first wiring SAN1 is connected commonly to a plurality of sense amplifiers SAM₁ - SAM n which constitute a sense amplifier block 10. One end of the first wiring SAN1 is connected to a current source 2. Further, a second wiring SAN2 is formed between the current source 2 and the sense amplifier SAM n which is disposed most remotely from the current source 2. Figure 2 is an equivalent circuit diagram of the vicinity of the sense amplifier block 10 in which only three sense amplifiers SAM₁ SAM₂ and SAM₃ (i.e., in the case of n = 3). In the first wiring SAN1 there is present parasitic resistance R₃ between the sense amplifiers SAM₁ and SAM₂, and also between the sense amplifiers SAM₂ and SAM₃, while in the second wiring SAN2 there is present a parasitic resistance R₄. Reference numeral R₅ designates a parasitic resistance which is present in a wiring SAP between the sense amplifiers SAM₁ and SAM₂ and also between the sense amplifiers SAM₂ and SAM₃. As described above, the operation of the first current source 1 lags behind that of the second current source 2 which has an important role in the reading operation, and does not affect the reading rate. Hence, in the following description, currents flowing during the period when the first current source 1 is activated are not considered. For the same reason, the parasitic resistance R₅ has no bearing upon the reading rate. Currents flowing respectively through the sense amplifiers SAM₁ SAM₂ and SAM₃ are the same in level. In the following description, these currents are represented by i. Where the current flowing through the second wiring SAN2 is represented by i₁, the current flowing between the sense amplifiers SAM₂ and SAM₃ in the first wiring SAN1 is represented by i₂, and the current flowing between the sense amplifiers SAM₂ and SAM₃ is represented by i₃, the following relations hold: i₁ = i - i₂ i₃ = i + i₂ i₁·R₄ = i₃·R₃ + i₂·R₃ When the first and second wirings SAN1 and SAN2 are constructed so as to have parasitic resistance equal to each other, R₄ = 2R₃ Then, the following relation holds: i₂ = i/4 Therefore, the voltage drop ΔV₁₂ between sense amplifiers SAM₁ and SAM₂, and the voltage drop ΔV₂₃ between sense amplifiers SAM₂ and SAM₃ can be expressed by the following relation: ΔV₁₂ = 5i·R₃/4 ΔV₂₃ = i·R₃/4 When assuming that the second wiring SAN₂ is not formed, that is, when the memory device has the prior art structure, the following relation holds: ΔV₁₂ = 2i·R₃ ΔV₂₃ = i·R₃ According to this embodiment, therefore, it can be understood that the voltage drops ΔV₁₂ and ΔV₂₃ can be effectively reduced as compared with the prior art level. Even if the parasitic resistance of the first wiring SAN1 is reduced by half in the prior art structure, the voltage drops ΔV₁₂ and ΔV₂₃ becomes as follows: ΔV₁₂ = i·R₃ ΔV₂₃ = i·R₃/2 From the above, it is apparent that the voltage drop ΔV₂₃ in this embodiment can be effectively reduced as compared with the above-mentioned ideal case. Figure 3 is a graph showing voltage changes in the bit lines BLA₁, BLB₁, BLA n and BLB n in the embodiment of Figure 1. In Figure 3, voltage changes in the bit lines BLA₁, BLB₁, BLA n and BLB n are shown by vurves LA₁, LB₁, LA n and LB n , respectively. By comparing Figures 3 and 8, it can be seen that the delay in voltage drop in the bit line BLB n is remarkably reduced. In this way, the sense operation rate of the sensor amplifier SAM n which is most remote from the current source 2 can be significantly improved. Figure 4 shows another memory device according to the invention. This embodiment has a structure which is similar to that of the memory device of Figure 1, except that the first and second wirings SAN1 and SAN2 are formed integrally. More specifically, the first and second wirings SAN1 and SAN2 are constituted respectively by first and second elongate sections of a metal strip SAN which extends in the direction of the row of the sense amplifiers SAM₁ - SAM n , and are separated by a slit SL which is formed in the center portion of the metal strip SAN. Both ends of the first and second wirings SAN1 and SAN2 are electrically connected to each other. The equivalent circuit of this embodiment is as shown in Figure 2, and the operation of this embodiment is substantially the same as that of the embodiment of Figure 1. Figure 5 shows a further memory device according to the invention. In this embodiment, a resistor R₀ is interposed between the current source 2 and one end of the first wiring SAN1. Figure 6 is an equivalent circuit diagram of this embodiment. As seen from above expressions (4) and (5), the voltage drops ΔV₁₂ and ΔV₂₃ in the memory device of Figure 1 are not equal. Thus, sense operation rates of the individual sense amplifiers including the one nearest to the current source and one remotest may be slightly different from each other. The memory device of Figure 5 can eliminate this difficulty. When the current flowing through the resistor R₀ is represented by i₄, the following relations hold: i₁ = i - i₂ i₃ = i + i₂ i₄ = 2·i + i₂ i₁·R₄ = i₄·R₀ + i₃·R₃ + i₂·R₃ When the first and second wirings SAN1 and SAN2 are constructed so as to have parasitic resistance equal to each other, R₄ = 2·R₃ The value of the resistance R₀ can be expressed using the parasitic resistance R₃ of the first wiring SAN1 as follows: R₀ = k·R₃ where k is a constant. Then, the following relations can be obtained from expressions (12) - (14): i₂ = i·(1 - 2k) / (k + 4) i₃ = i·(5 - k) / (k + 4) When assuming k = 2 that is assuming the value of the resistor R₀ is twice the value of the parasitic resistance R₃, i₂ = i₃ = i/2 The voltage drops ΔV₁₂ and ΔV₂₃ between sense amplifiers SAM₁ and SAM₂ becomes as follows: ΔV₁₂ = ΔV₂₃ = i·R₃/2 Consequently, the voltage drops ΔV₁₂ and ΔV₂₃ in the embodiment of Figure 5 can be significantly reduced as compared with the prior art device, and moreover the voltage drops ΔV₁₂ and ΔV₂₃ can be equalized. It can be understood from this fact that the resistor R₀ has a function which eliminates the effect of the parasitic resistance of the second wiring SAN2, and thereby uniformly reducing possible voltage drops in the wirings connected to the sense amplifiers. The voltage changes in the bit lines BLA₁, BLB₁, BLA n and BLB n in the embodiment of Figure 5 is substantially similar to those shown in Figure 3. In the above, embodiments having three sense amplifiers are illustrated. It is apparent that the number of sense amplifiers in a memory device according to the invention is not restricted to three. According to the present invention, as above described, a sense amplifier disposed most remote from a current source (the current source 2 in the illustrated embodiments) can be allowed to perform the sense operation with almost the same speed of response as that of another sense amplifier nearest to the current source, which means considerable improvement in the data read rate in the performance of the semiconductor memory device. In a highly integrated semiconductor memory device which involves increased wiring length and accordingly increased parasitic resistance, the arrangement of the invention is particularly advantageous in that voltage drop due to the parasitic resistance of the wiring can be reduced so that the sense amplifiers are allowed to operate at higher speed in order to perform higher-speed data reading.

Claims: A semiconductor memory device comprising: a sense amplifier block in which block a plurality of sense amplifiers (SAM₁-SAM n ) are arranged in a row and a current source (2) disposed in the vicinity of one end of said sense amplifier block, said memory device further comprises: a first wiring (SAN1) connected commonly to said sense amplifiers (SAM₁-SAM n ), one end of said first wiring being connected to said current source (2), characterized by a second wiring (SAN2) connecting said current source (2) with the other end of said first wiring at one of said sense amplifiers (SAM n ) which is most separated from said current source (2). A semiconductor memory device according to claim 1, said memory device further comprising a strip (SAN) including said first and said second wirings (SAN1, SAN2) and made of a conductor material, said strip (SAN) elongating along said row of said sense amplifiers (SAM₁-SAM n ), one end of said strip being connected to said current source, said strip being divided into first and second sections as said first and said second wirings by a slit (SL) which elongates along said row of said sense amplifiers, said first and second sections (SAN1, SAN2) being connected with each other at both ends. A semiconductor memory device according to one of claims 1 or 2, wherein said memory device further comprises a resistance means (R₀) which is connected between said current source (2) and said one end of said first wiring (SAN1) or said first section of said strip.

Inventors: SUMI TATSUMI, SUMI, TATSUMI
Applicants: MATSUSHITA ELECTRONICS CORP, MATSUSHITA ELECTRONICS CORPORATION
Application year: 1990
Main classification: G11C7
IPC codes: G11C11