Insulated gate bipolar transistor and method of making the same

Abstract: In an IGBT having a plurality of source regions (5) formed in a base region (4), the spacing (D) between the source regions (5) is adapted to be larger than twice the channel length (L). A high concentration region (14) can be formed in at least a portion of the base region (4) between the source regions (5) independently from the above measure. Other IGBTs are further disclosed: A 500-750 V IGBT having a channel width per unit area ranging from 140 cm-1 to 280 cm-1, a 1000-1500 V IGBT having a channel width per unit area ranging from 70 cm-1 to 150 cm-1, and a stripe cell IGBT having a source region (5) formed in only one side of the base region (4).

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) and, more particularly, to an IGBT having a high short-circuit withstandability (i.e., high short-circuit SOA) and a high latch-up withstandability (i.e., high latch-up current) suitable for an inverter. In particular, the invention relates to an insulated gate bipolar transistor, comprising: a first conductivity type first semiconductor layer having first and second major surfaces; a second conductivity type second semiconductor layer disposed on the first major surface of the first semiconductor layer and having a surface opposite to the first major surface; at least one first conductivity type first semiconductor region, each of the first semiconductor regions being disposed in the second semiconductor layer and exposed at the surface of the second semiconductor layer; a plurality of second conductivity type second semiconductor regions disposed in each of the first semiconductor regions and exposed at the exposed surface of each of the first semiconductor regions; the second semiconductor regions being spaced apart from each other in each of the first semiconductor regions and being spaced apart from the junction between the respective first semiconductor region in which they are disposed and the second semiconductor layer, all the portions of each of the first semiconductor regions located in a peripheral part of each of the first semiconductor regions, in the vicinity of the exposed surface of each of the first semiconductor regions and between the second semiconductor layer and all of the second semiconductor regions disposed in their respective first semiconductor regions, being defined as a channel region; an insulation film disposed on the channel region; a control electrode disposed on the insulation film; a first main electrode disposed on the surfaces of the first and second semiconductor regions; and a second main electrode disposed on the second major surface of the first semiconductor layer. Such a transistor is known in principle from the document DE-A-3 519 389 even though this document explicitly relates to a mosfet having a variable conductivity. In this prior art document it is intended to provide such a transistor having a variable conductivity wherein the latch-up effect caused by a parasitary tyristor is prevented. For this purpose, it is provided there that the transistor has a saturation current which is smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode thereof. For this purpose, several parameters are measured and taken into account. Description of the Background Art In general, an IGBT device has a plurality of IGBT elements (hereinafter referred to as IGBT cells) connected in parallel, each of which may have a polygonal configuration, such as a square configuration, or a striped configuration. Fig. 1A is a plan view showing a square IGBT cell in a conventional N channel IGBT device, and Fig. 1B is a sectional view taken along line A - A of Fig. 1A. As best shown in Fig. 1B, the IGBT cell includes a P collector layer 1, and an N⁺ buffer layer 2 and an N epitaxial layer 3 provided on the P collector layer 1 in this sequence. P base regions 4 are selectively formed in the surface of the N epitaxial layer 3 and, further, N emitter regions 5 are selectively formed in the surface of each of the P base region 4. Regions 6 in the vicinity of the surface of the P base region 4, between the surfaces of the N epitaxial layer 3 and N emitter regions 5, are defined as channel regions. Gate insulation films 7 are deposited on the channel regions 6. Each of the insulation films 7 also covers the N epitaxial layer 3 to be integrated in the adjacent IGBT cells. Gate electrodes 8 are formed of substances such as polysilicon on the gate insulation films 7. An emitter electrode 9 is formed of metal such as aluminum to be in electrical contact with both the P base layer 4 and the N emitter regions 5. In the IGBT device, all the gate electrodes 8 of the IGBT cells are electrically connected in common and all the emitter electrodes 9 of the IGBT cells are also electrically connected in common. A collector electrode 10 of metal is formed over the whole bottom surface of the P collector layer 1 to be integrated in all the IGBT cells. An IGBT is a voltage control type transistor having a MOS gate configuration similar to a MOSFET, so that the IGBT is advantageous because of its simplified drive circuit. When a positive voltage is applied to the gate electrodes 8 under a state where a positive voltage is applied to the collector electrode 10 and a negative voltage is applied to the emitter electrodes 9, inversion layers appear in the channel regions 6 allowing electrons to move into the N epitaxial layer 3 from the N emitter regions 5. On the other hand, holes are injected into the N epitaxial layer 3 from the P collector layer 1 through the N⁺ buffer layer 2 which controls the injection of those holes, so that the conductivity modulation is caused in the N epitaxial layer 3. This results in a significant reduction of resistance in the N epitaxial layer 3. Therefore, an IGBT device has an advantage since an ON state resistance in the N epitaxial layer 3 does not have much effect even in an IGBT device of high breakdown voltage, although an ON state resistance in a layer corresponding to the N epitaxial layer 3 has much effect in a MOSFET device with a high breakdown voltage. Because of these advantages, the IGBT has been noted as a device suitable for an inverter. However, as shown in Fig. 1B, there exists a parasitic thyristor formed of the P collector layer 1, the N epitaxial layer 3, the P base regions 4 and the N emitter regions 5 in the IGBT. When the parasitic thyristor once turns on, a voltage applied to the gate electrodes 8 can no longer control the main current. This phenomenon is called latch-up. Once latch-up is caused, an excess current results in a thermal breakdown of the IGBT. Accordingly, it is important for the IGBT to have a high latch-up breakdown voltage. The mechanism of occurrence of a latch-up will be described below. When a hole current flows just below the N emitter regions 5, a voltage drop occurs because of resistances R laterally extending in each of the P base regions 4. When this voltage drop becomes higher than the built-in potential in a PN junction formed of the N emitter regions 5 and the P base region 4, the PN junction is forwardly biased so that electrons are injected from the N emitter regions 5 to the P base regions 4. This provides a trigger and results in latch-up. As the main current I C is increased, the hole current flowing just below the N emitter regions 5 is increased, so that a latch-up is easily caused. Hence, the IGBT design is generally implemented so that I L > I C(Sat)Max is satisfied, where I L is the limit of the main current to which latch-up can be avoided and I C(Sat)Max is a saturation current at the maximum gate voltage actually used. Fig. 2 is a circuit diagram showing an inverter device in which six IGBTs 11a - 11f are used as switching elements. In a usual inverter device, when arms are shortcircuited, a current sensor 12 detects an excess current to force all the switching elements (the IGBTs 11a - 11f in the circuit shown in Fig. 2) to be turned off so as to prevent those switching elements from breaking down. However, since such protecting function does not immediately work, those switching elements can be subjected to an excess current for some time. Hence, it is important for the IGBT to have a high short-circuit breakdown voltage when it is incorporated into the inverter device as switching element. In the IGBT shown in Fig. 1B, an electron current flowing in the channel region 6 serves as a base current I B of a PNP transistor formed of the P collector layer 1, the N epitaxial layer 3 and the P base regions 4. Assuming that h FE represents a current amplification factor of the PNP transistor, the main current I C = h FE x I B . No P collector layer 1 is in a MOSFET.This means there is no amplification caused by the above mentioned PNP transistor in the MOSFET and, therefore, the above equation should be I C = I B . Thus, as shown in Fig. 3, a saturation current I C(Sat) of the IGBT, which is restricted by a channel resistance on the condition that a gate voltage is constant, is approximately h FE times larger than that of the MOSFET. The I C(Sat) corresponds to a self-restriction current in short-circuiting. Fig. 4 is a diagram showing a wave form in an IGBT short-circuiting test. Herein, a gate pulse shown in Fig. 4(C) is applied to the gate electrode 8 with power supply voltage being directly applied across the emitter electrode 9 and the collector electrode 10 of the IGBT without a load. As a result, a large main current I C ( < I C(Sat) ) flows for a period of time t W , as shown in Fig. 4(B), with a high collector voltage V C being applied as shown in Fig. 4(A). When I C x V C x t W goes beyond a critical value, the IGBT is thermally broken down. This critical value is determined depending upon the area of an IGBT chip, the resistance value and the thickness of the N epitaxial layer 3 and the like. It is preferable that I C(Sat) is as small as possible, in order to enhance the short-circuit SOA. To easily satisfy the previously mentioned relationship that the latch-up critical main current I L > I C(Sat)Max , also, the I C(Sat) may as well be small. However, it is impossible to make the I C(Sat) too small from an aspect of the conductive ability and in the ON state loss. To enhance the latch-up breakdown voltage, that is, to make the latch-up critical main current I L large, emitter bypass structures shown in Figs. 5 and 6 have been proposed. Sectional views taken along the line B-B of Fig.5 and the line C-C of Fig.6 are the same as in Fig. 1B. Since an N emitter region 5 is eliminated in a bypass region 13, the rate of a hole current flowing through a P base region 4 just below the N emitter region 5 is decreased. This supresses the occurrence of a latch-up. In the emitter bypass structure shown in Fig. 6, further, a channel width is somewhat reduced. This makes the I C(Sat) small more or less and results in the increase of the short-circuit SOA. A conventional IGBT is structured as has been described, and it has been desired to enhance its latch-up current and short-circuit SOA. For that purpose, the emitter bypass structure has been proposed. However, the fact is that it does not bring a sufficient latch-up current and short-circuit SOA suitable for an actual application to an inverter device under all conditions in practice. The object underlying the present invention is to provide an insulated gate bipolar transistor which has a high short-circuit 50A and a high latch-up current, and a method of making such a transistor so that such a transistor is suitable for an inverter device. The solution according to the invention is achieved by providing an insulated gate bipolar transistor of the type as specified above which is characterized in that the distance D taken along the peripheral part of the first semiconductor regions between the two regions of each pair of second semiconductor regions adjacent one to the other along the peripheral part of their respective first semiconductor region and the length L of the channel region, which length L is defined as the distance taken in the channel region between the second semiconductor layer and each of the second semiconductor regions, satisfy the relation D > 2L. According to a further development of the transistor according to the invention, the transistor comprises a plurality of first semiconductor regions each of which having a stripe configuration and defining a transistor cell, all of the cells being connected in parallel. A specific embodiment of transistor according to the invention is characterized in that the second semiconductor layer is composed of a buffer layer and an epitaxial layer, wherein the distance D between two respective adjacent semiconductor regions and a thickness X of the portion of the epitaxial layer located under the first semiconductor region satisfy the relation D < 2X. A further development of the transistor according to the invention is characterized by a first conductivity type high concentration region which is disposed at least in a portion of each of the first semiconductor regions located between the second semiconductor regions and exposed at the exposed surface of the first semiconductor regions, which high concentration region has an impurity concentration that is five times or more larger than that of the first semiconductor regions, and which high concentration region is closer to the second semiconductor layer in the peripheral part of the first semiconductor regions between the second semiconductor regions than are the second semiconductor regions. A specific embodiment of the transistor according to the invention is characterized in that the channel region has a width W which is defined as the length taken in the channel region along the peripheral part of the first semiconductor regions, and in that a value W U per unit area of a width of the channel region satisfies the relation 140 cm -1 ≤ W U ≤ 280 cm -1 , whereby the transistor has a breakdown voltage of about 500 to 750 Volt. An other specific embodiment of the transistor according to the invention is characterized in that the channel region has a width W which is defined as the length taken in the channel region along the peripheral part of the first semiconductor regions, and in that a value W U per unit area of a width of the channel region satisfies the relation 70 cm -1 ≤ W U ≤ 150 cm -1 , whereby the transistor has a breakdown voltage of about 1000 to 1500 Volt. A further development of the transistor according to the invention is characterized in that a plurality of second conductivity type third semiconductor regions are periodically disposed in the first semiconductor layer and penetrate the first semiconductor layer. The method of fabricating the insulated gate bipolar transistor according to the invention comprises the following steps: a) preparing a first conductivity type first semiconductor layer having first and second major surfaces; b) forming a second conductivity type second semiconductor layer on the first major surface of the first semiconductor layer; c) forming at least one first conductivity type first semiconductor region selectively in a surface of the second semiconductor layer; d) forming a plurality of second conductivity type second semiconductor regions selectively in a surface of each of the first semiconductor regions; wherein all the portions of each of the first semiconductor regions located in a peripheral part of each of the first semiconductor regions, in the vicinity of the exposed surface of each of the first semiconductor regions and between the second semiconductor layer, and all of the second semiconductor regions disposed in their respective first semiconductor regions, are defined as a channel region; e) forming an insulation film on the channel region; f) forming a control electrode on the insulation film; g) forming a first main electrode on the surfaces of the first and second semiconductor regions; and h) forming a second main electrode on the second major surface of the first semiconductor layer, wherein the distance D taken along the peripheral part of the first semiconductor regions between the two regions of each pair of second semiconductor regions adjacent one to the other along the peripheral part of their respective first semiconductor region and the length L of the channel region, which length L is defined as the distance taken in the channel region between the second semiconductor layer and each of the second semiconductor regions, satisfy the relation D > 2L. A further development of the method according to the invention comprises the following step: forming a first conductivity type high concentration region at least in a portion of the surface of each of the first semiconductor regions between the second semiconductor regions, which high concentration region is provided with an impurity concentration that is five times or more larger than that of the first semiconductor regions, and which high concentration region is formed closer to the second semiconductor layer in the peripheral part of the first semiconductor regions between the second semiconductor regions than are the second semiconductor regions. A still further development of the method according to the invention is characterized in that the step of forming at least one first conductivity type first semiconductor region selectively in a surface of the second semiconductor layer comprises the following steps: forming an insulation film on the second semiconductor layer; forming a control electrode layer on the insulation film; selectively removing the control electrode layer and the insulation film whereby windows are opened; implanting first conductivity type impurities in the second semiconductor layer through the windows; and in that the step of forming a plurality of second conductivity type second semiconductor regions selectively in a surface of each of the first semiconductor regions comprises the step of selectively implanting second conductivity type impurities in each of the first semiconductor regions. A specific embodiment of the method according to the invention is characterized in that the step of forming a second conductivity type second semiconductor layer comprises the steps of preparing a second conductivity type second semiconductor layer and attaching the second semiconductor layer to the first semiconductor layer. According to the present invention, the object underlying the present application is solved in a satisfying manner. Since the relation D > 2L is fulfilled in the transistor according to the invention the channel width can effectively be decreased and therefore the saturation current I C (Sat) of the IGBT can also effectively be decreased. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view showing a conventional IGBT; Fig. 1B is a cross-sectional view taken along the line A-A of Fig. lA; Fig. 2 is a circuit diagram showing an inverter device in which IGBTs are employed; Fig. 3 shows graphs of a saturation current of an IGBT and a MOSFET; Fig. 4 shows waveforms in an IGBT short-circuiting test; Fig. 5 and Fig. 6 are plan views showing conventional emitter bypass structures; Fig. 7A is a plan view showing an embodiment of an IGBT according to the present invention; Fig. 7B is a cross-sectional view taken along the line A-A of Fig. 7A; Fig. 8 is a plan view showing how an electric current flows in a channel region; Fig. 9A and Fig. 10A are plan views showing other embodiments of the IGBT according to the present invention; Fig. 9B and Fig. 10B are cross-sectional views taken along the lines E-E and F-F of Fig. 9A and Fig. 10A, respectively; Fig. 11 is a plan view showing the manner of formation of a depletion layer; Fig. 12 and Fig. 13 show graphs concerning a relationship between a channel width per unit area and a saturation current density as well as a calorific energy; Fig. 14 is a cross-section view showing a collector shorted structure; Fig. 15A to Fig. 15D are cross-sectional views showing an example of a fabricating method of the IGBT according to the present invention; and Fig. 16 is a view showing a modification of the fabricating steps. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 7A is a plan view showing an embodiment of an IGBT according to the present invention, and Fig. 7B is a sectional view taken along line D - D of Fig. 7A. The IGBT in this embodiment has a structure in which a number of IGBT cells having a stripe configuration are connected in parallel. As best shown in Fig. 7B, the IGBT cell includes a P collector layer 1, and an N⁺ buffer layer 2 and an N epitaxial layer 3 provided on the P collector layer 1 in this sequence. P base regions 4 are selectively formed in the surface of the N epitaxial layer 3 and, further, N emitter regions 5 are selectively formed in the surface of each of the P base region 4. The N emitter regions 5 are a plurality of islands which are formed by removing several parts of narrow strips of the original N emitter regions 5 at a regular interval. Areas from which those parts of the N emitter region 5 have been removed are defined as bypass regions 15. Regions 6 in the vicinity of the surface of the P base region 4, between the surfaces of the N epitaxial layer 3 and N emitter regions 5, are defined as channel regions. Gate insulation films 7 are deposited on the channel regions 6. Each of the insulation films 7 also covers the N epitaxial layer 3 to be integrated in the adjacent IGBT cell. Gate electrodes 8 are formed of substances such as polysilicon on the gate insulation films 7. An emitter electrode 9 is formed of metal such as aluminum to be in electrically contact with both the P base layer 4 and the N emitter regions 5. ln the IGBT device, all the gate electrodes 8 of the IGBT cells are electrically connected in common and all the emitter electrodes 9 of the IGBT cells are also electrically connected in common. A collector electrode 10 of metal is formed over the whole bottom surface of the P collector layer 1 to be integrated in all the IGBT cells. In operation, when a positive voltage is applied to the gate electrodes 8 with a positive voltage being applied to a collector electrode 10 and a negative voltage being applied to the emitter electrode 9, inversion layers are formed in portions of the P base regions 4 just below the gate electrodes 8 as shadowed with oblique lines in Fig. 8, so that a main current flows from the collector electrode 10 to the emitter electrode 9. Since such inversion layers are formed not only in a part corresponding to each of the N emitter regions 5 (i.e., a channel region 6) but also in a part corresponding to each of the bypass regions 15, electrons injected from the N emitter regions 5 to the N epitaxial layer 3 through the inversion layer spread at an angle of approximately 45°. In other words, an electron current from the N epitaxial layer 3 flows into the N emitter regions 5 spreading at an angle of 45° as shown with arrows in Fig. 8. Therefore, when the width D of the bypass region 15 (i.e., an interval between the emitter regions 5) is narrow, the reduction of the width W of the channel region 6 is hardly effective even if the width W is reduced on a pattern. In such a case, the saturation current I C(Sat) is hardly decreased and, therefore, the increase of the short-circuit SOA can not be expected. Thus, the width D must be sufficiently large to satisfactorily reduce the effective channel width. Allowing for the spreading of the electron current at an angle of 45°, the following relationship must be satisfied to reduce the effective channel width: D > 2L where L is a channel length. Fig. 9A is a plan view showing another embodiment of the IGBT according to the present invention, taking the above stated requirement into consideration Fig. 9B is a sectional view taken along line E - E of Fig. 9A. In this embodiment, D > 2L is fully satisfied by setting the width D of the bypass region 15 to be larger than in the previous embodiment. This reduces the effective channel width and results in decreasing the saturation current I C(Sat) effectively so that the increase of the short-circuit SOA can be attained. Indeed, D < 2X must be satisfied because there exists a region where no electron current flows when D > 2X and this leads to the considerable rise of an ON state voltage, where X is a thickness of the N epitaxial layer 3 just below the P base region 4. Hence, it is desirable that many bypass regions 15 whose width D is as small as possible are provided within a range of D > 2L. Fig. 10A is a plan view showing a still another embodiment according to the IGBT of the present invention, and Fig. 10B is a sectional view taken along line F - F of Fig. 10A. In this embodiment, the IGBT has a P⁺ base region 14 provided in the middle of a P base region 4. The impurity concentration of the P⁺ base region 14 is 5 times or more larger than that of the P base region 4. The end portion of the P⁺ base region 14, as will be recognized from dash-dot lines in Fig 10A, is near the end portion of the P base region 4 at portions corresponding to bypass regions 15 and is away from that at portions corresponding to N emitter regions 5, and thus makes an uneven edge configuration. In this IGBT, although inversion layers are formed in the P base region 4 just below base electrodes 8 when a positive voltage is applied to the base electrodes 8, no inversion layer is formed in the P⁺ base region 14. This makes the configuration of the inversion layers uneven as shadowed with oblique lines in Fig. 11, and the spreading of an electron current is supressed in concave portions of the inversion layers. The reduction of a channel width will be discussed from a quantitative point of view. When an IGBT is used in a DC 220 V line, a product of a class with a breakdown voltage of 500 to 750 V is usually used. The IGBT of such a class has a rated current density of approximately 100 A/cm² in the ordinary operation. On the other hand, when an IGBT is used in a DC 440 V line, a product of a class with a breakdown voltage of 1000 to 1500 V is usually used. The IGBT of such a class has a rated current density of approximately 50 A/cm² in the ordinary operation. An IGBT (Sample 1) with a rated breakdown voltage of 500 V and a rated current density of 100 A/cm² as a representative of the product of the 500 to 750 V breakdown voltage class, and an IGBT (Sample 2) with a rated breakdown voltage of 1000 V and a rated current density of 50 A/cm² as a representative of the product of the 1000 to 1500 V breakdown voltage class will be discussed below. Generally, a saturation current density j C(Sat) of an IGBT is in proportion to its channel width per unit area W U . j C(Sat) ∝ W U A solid line of a graph in Fig. 12 shows the relationship between the saturation current density j C(Sat) (A/cm²) and the channel width per unit area W U (cm⁻¹) of the IGBT of Sample 1, and a solid line of a graph in Fig. 13 shows the relationship between the saturation current density j C(Sat) (A/cm²) and the channel width per unit area W U (cm⁻¹) of the IGBT of Sample 2. The IGBT of Sample 1 requires a peak current over three times of the rated current density of 100 A/cm², that is, the saturation current density j C(Sat) must be 300 A/cm² or more. According to the solid line graph of Fig. 12, it is necessary that the channel width per unit area W U satisfies W U ≧ 140 cm⁻¹. On the other hand, the IGBT of Sample 2 requires a peak current over three times of the rated current density of 50 A/cm², that is, the saturation current density j C(Sat) must be 150 A/cm² or more. According to the solid line graph of Fig. 13, it is necessary that the channel width per unit area W U satisfies W U ≧ 70 cm⁻¹. When a calorific energy applied to tle IGBT in short-circuiting goes beyond a certain value, the IGBT is thermally broken down. The calorific energy E C in short-circuiting is given by the following equation: E C = j C(Sat) x V C x t W where V C is a voltage applied across the collector and the emitter of the IGBT in short-circuiting and t W is a period of time of the short-circuit. The IGBT of Sample 1 desirably requires a short-circuit breakdown voltage of 400 V at a minimum compared with the rated breakdown voltage of 500 V in the ordinary operation. The IGBT must endure without thermally breaking down for 10 µs at the shortest in the condition that the minimum voltage of 400 V is directly applied without load in its ON state. This is because a protection circuit can function effectively after that period. On the other hand, the IGBT of Sample 2 desirably requires a short-circuit breakdown voltage of 800 V at a minimum compared with the rated breakdown voltage of 500 V in the ordinary operation. Similar to the IGBT of Sample 1, the IGBT of Sample 2 must also endure without thermally breaking down for 10 µs at the shortest against the minimum voltage of 800 V applied in a short-circuiting manner. A dash-dot line of the graph in Fig. 12 shows the relationship between the channel width per unit area W U (cm⁻¹) and the calorific energy E C (Joule/cm²) when a voltage of 400 V is applied to the IGBT of Sample 1 for 10 µs in a short-circuiting manner. A dash-dot line of the graph in Fig. 13 shows the relationship between the channel width per unit area W U (cm⁻¹) and the calorific energy E C (Joule/cm²) when a voltage of 800 V is applied to the IGBT of Sample 2 for 10 µs in a short-circuiting manner. Marks x in Figs. 12 and 13 denote breakdown values given by an experiment. According to Figs. 12 and 13, it can be recognized that the IGBTs of Samples 1 and 2 are thermally broken down when the calorific energy E C reaches approximately 5 Joule/cm². As will be recognized from the dash-dot line graphs in Figs. 12 and 13, the channel width per unit area W U of the IGBT of Sample 1 must satisfy W U ≦ 280 cm⁻¹, and the channel width per unit area W U of the IGBT of Sample 2 must satisfy W U ≦ 150 cm⁻¹ in order that both the IGBTs of Sample 1 and Sample 2 may endure a thermal breakdown. Accordingly, the IGBT suitable for an inverter is desirably designed with the following channel width per unit area W U : The IGBT of a breakdown voltage class of 500 - 750 V: 140 cm -1 ≦ W U ≦ 280 cm -1 . The IGBT of a breakdown voltage class of 1000 - 1500 V: 70 cm -1 ≦ W U ≦ 150 cm -1 . Fig. 14 is a sectional view showing a collector shorted structure. In this structure, a P collector layer 1a and an N⁺ regions 2a are alternately formed on the bottom surface of an N epitaxial layer 3, and a collector electrode 10 is formed thereover. Since carriers in the N epitaxial layer 3 are rapidly drawn out to the collector electrode 10 through the N⁺ buffer layer 2a, switching speed is increaseed. Such a collector short structure may be applied to the IGBT according to the present invention. Figs. 15A to 15D are sectional views showing an exemplary method of manufacturing the IGBT (breakdown voltage class of 500 - 700 V) according to the present invention. As shown in Fig. 15A, the first process stage includes the steps of forming an N⁺ buffer layer 2 having a specific resistance of approximately 0,1 Ω·cm by about 20 µm in thickness on a P collector layer 1 of a P semiconductor substrate having a specific resistance of approximately 0,005 - 0,02 Ω·cm by means of epitaxial growing, further forming an N epitaxial layer 3 having a high specific resistance of approximately 30 Ω·cm by about 60 µm in thickness on the N⁺ buffer layer 2 by means of epitaxial growing, depositing an oxide film 70 over the whole surface of the epitaxial layer 3, and depositing a polysilicon layer 80 on the whole surface of the oxide film 70 by means of CVD or the like. Then, as shown in Fig. 15B, the oxide film 70 and the polysilicon layer 80 are selectively etched to open windows 90. This step develops gate oxide films 7 and gate electrodes 8 from the oxide film 70 and the polysilicon layer 80, respectively. The configuration of windows 90 corresponds to that of IGBT cells, such as a stripe configuration P type impurities are selectively added to the N epitaxial layer 3 through the windows 90 by means of ion implantation method, diffusion method and the like to form P base regions 4 of a configuration corresponding to the IGBT cell configulation. Then, a patterned mask not shown is formed and N type impurities are selectively added to the P base regions 4 by means of an ion implantation method, diffusion method and the like to form N emitter regions 5 of a desired pattern in accordance with any of the above stated embodiments, as shown in Fig. 15C. In the embodiment illustrated in Figs. 15A-15D, the interval D between the N emitter regions 5 are set to satisfy the following relationship: D > 2 x 0,8 (X jp - X jn ) where X jp and X jn are depths of the P base regions 4 and the N emitter regions 5, respectively. The coefficient 0,8 indicates the rate of the lateral diffusion to the vertical diffusion. Thus, 0.8(X jp - X jn ) corresponds to the channel length L of Fig. 8. As shown in Fig. 15D, the last process stage to finish the IGBT device includes the steps of forming the emitter electrode 9 of metal such as aluminum to be in ohmic contact with both the N emitter region 5 and the P base region 4, and thereafter forming the collector electrode 10 of metal such as Ti - Ni - Au to be in ohmic contact with the bottom surface of the P collector layer 1. In case of forming the P⁺ base region 14 of Fig. 10B, a process step of selectively injecting into the P base regions 4 P type impurities of an amount sufficiently larger (desirably 5 times or more) than in forming the P base regions 4 may be performed between the steps of Fig. 15B and Fig. 15C. Instead of forming the N⁺ buffer layer 2 and the N epitaxial layer 3 in sequence on the P semiconductor substrate 1 in the process step of Fig. 15A, the N⁺ buffer layer 2 may be formed by diffusing N type impurities over the whole bottom surface of a high specific resistance N semiconductor substrate 30, and then the P collector layer 1 of a P semiconductor substrate may be attached to the substrate 30, as shown in Fig. 16. In this case, both the substrates can easily be adhered to each other by subjecting the contact surfaces of both the substrates to a hydrophilic treatment, bringing the substrates into contact and then subjecting them to a heat treatment. In case of manufacturing the IGBT of a breakdown voltage in the class of 1000-1500 V, the specific resistance of the N epitaxial layer 3 may be changed to 60 Ω·cm and the thickness of the N epitaxial layer 3 may be changed to 100 µm. The specific resistance of the P collector layer 1, the specific resistnace of the N⁺ buffer layer 2 and the thickness of the N⁺ buffer layer 2 are the same as those in the above mentioned IGBT of the breakdown voltage class of 500-750 V. Although N channel IGBTs have been explained in the above embodiments, it should be noted that the present invention can also be applied to a P channel IGBT, as a matter of course.

Claims: An insulated gate bipolar transistor, comprising: a first conductivity type first semiconductor layer (1) having first and second major surfaces; a second conductivity type second semiconductor layer (2, 3) disposed on the first major surface of the first semiconductor layer (1) and having a surface opposite to the first major surface; at least one first conductivity type first semiconductor region (4), each of the first semiconductor regions (4) being disposed in the second semiconductor layer (3) and exposed at the surface of the second semiconductor layer (3); a plurality of second conductivity type second semiconductor regions (5) disposed in each of the first semiconductor regions (4) and exposed at the exposed surface of each of the first semiconductor regions (4); the second semiconductor regions (5) being spaced apart from each other in each of the first semiconductor regions (4) and being spaced apart from the junction between the respective first semiconductor region (4) in which they are disposed and the second semiconductor layer (3), all the portions (6) of each of the first semiconductor regions (4) located in a peripheral part of each of the first semiconductor regions (4), in the vicinity of the exposed surface of each of the first semiconductor regions (4) and between the second semiconductor layer (3) and all of the second semiconductor regions (5) disposed in their respective first semiconductor regions (4), being defined as a channel region (6); an insulation film (7) disposed on the channel region (6); a control electrode (8) disposed on the insulation film (7); a first main electrode (9) disposed on the surfaces of the first and second semiconductor regions (4, 5); and a second main electrode (10) disposed on the second major surface of the first semiconductor layer (1), characterized in that: the distance D taken along the peripheral part of the first semiconductor regions (4) between the two regions of each pair of second semiconductor regions (5) adjacent one to the other along the peripheral part of their respective first semiconductor region (4) and the length L of the channel region (6), which length L is defined as the distance taken in the channel region (6) between the second semiconductor layer (3) and each of the second semiconductor regions (5), satisfy the relation D > 2L. The transistor in accordance with claim 1, characterized in that the transistor comprises a plurality of first semiconductor regions (4) each of which having a stripe configuration and defining a transistor cell, all of the cells being connected in parallel. The transistor in accordance with claim 1 or 2, characterized in that the second semiconductor layer (2, 3) is composed of a buffer layer (2) and an epitaxial layer (3), wherein the distance D between two respective adjacent second semiconductor regions (5) and a thickness X of the portion of the epitaxial layer (3) located under the first semiconductor region (4) satisfy the relation D < 2X. The transistor in accordance with anyone of claims 1 to 3, characterized by a first conductivity type high concentration region (14) which is disposed at least in a portion of each of the first semiconductor regions (4) located between the second semiconductor regions (5) and exposed at the exposed surface of the first semiconductor regions (4), which high concentration region (14) has an impurity concentration that is five times or more larger than that of the first semiconductor regions (4), and which high concentration region (14) is closer to the second semiconductor layer (3) in the peripheral part of the first semiconductor regions (4) between the second semiconductor regions (5) than are the second semiconductor regions (5). The transistor in accordance with anyone of claims 1 to 4, characterized in that the channel region (6) has a width W which is defined as the length taken in the channel region (6) along the peripheral part of the first semiconductor regions (4), and in that a value W U per unit area of a width of the channel region (6) satisfies the relation 140 cm -1 ≤ W U ≤ 280 cm -1 , whereby the transistor has a breakdown voltage of about 500 to 750 Volt. The transistor in accordance with anyone of claims 1 to 4, characterized in that the channel region (6) has a width W which is defined as the length taken in the channel region (6) along the peripheral part of the first semiconductor regions (4), and in that a value W U per unit area of a width of the channel region (6) satisfies the relation 70 cm -1 ≤ W U ≤ 150 cm -1 , whereby the transistor has a breakdown voltage of about 1000 to 1500 Volt. The transistor in accordance with anyone of claims 1 to 6, characterized in that a plurality of second conductivity type third semiconductor regions (2a) are periodically disposed in the first semiconductor layer (1a) and penetrate the first semiconductor layer (1a). A method of fabricating the insulated gate bipolar transistor of anyone of claims 1 to 7, comprising the following steps: a) preparing a first conductivity type first semiconductor layer (1) having first and second major surfaces; b) forming a second conductivity type second semiconductor layer (2, 3) on the first major surface of the first semiconductor layer (1); c) forming at least one first conductivity type first semiconductor region (4) selectively in a surface of the second semiconductor layer (3); d) forming a plurality of second conductivity type second semiconductor regions (5) selectively in a surface of each of the first semiconductor regions (4); wherein all the portions (6) of each of the first semiconductor regions (4) located in a peripheral part of each of the first semiconductor regions (4), in the vicinity of the exposed surface of each of the first semiconductor regions (4) and between the second semiconductor layer (3), and all of the second semiconductor regions (5) disposed in their respective first semiconductor regions (4), are defined as a channel region (6); e) forming an insulation film (7) on the channel region (6); f) forming a control electrode (8) on the insulation film (7); g) forming a first main electrode (9) on the surfaces of the first and second semiconductor regions (4, 5); and h) forming a second main electrode (10) on the second major surface of the first semiconductor layer (1), wherein the distance D taken along the peripheral part of the first semiconductor regions (4) between the two regions of each pair of second semiconductor regions (5) adjacent one to the other along the peripheral part of their respective first semiconductor region (4) and the length L of the channel region (6), which length L is defined as the distance taken in the channel region (6) between the second semiconductor layer (3) and each of the second semiconductor regions (5), satisfy the relation D > 2L. The method in accordance with claim 8, further comprising the following step: forming a first conductivity type high concentration region (14) at least in a portion of the surface of each of the first semiconductor regions (4) between the second semiconductor regions (5), which high concentration region (14) is provided with an impurity concentration that is five times or more larger than that of the first semiconductor regions (4), and which high concentration region (14) is formed closer to the second semiconductor layer (3) in the peripheral part of the first semiconductor regions (4) between the second semiconductor regions (5) than are the second semiconductor regions (5). The method in accordance with anyone of claims 8 and 9, characterized in that the step of forming at least one first conductivity type first semiconductor region (4) selectively in a surface of the second semiconductor layer (3) comprises the steps of: forming an insulation film (70) on the second semiconductor layer (3); forming a control electrode layer (80) on the insulation film (70); selectively removing the control electrode layer (80) and the insulation film (70) whereby windows (90) are opened; implanting first conductivity type impurities in the second semiconductor layer (3) through the windows (90); and in that the step of forming a plurality of second conductivity type second semiconductor regions (5) selectively in a surface of each of the first semiconductor regions (4) comprises the step of selectively implanting second conductivity type impurities in each of the first semiconductor regions (4). The method in accordance with anyone of claims 8 to 10, characterized in that the step of forming a second conductivity type second semiconductor layer (2, 3) comprises the steps of preparing a second conductivity type second semiconductor layer (2, 30) and attaching the second semiconductor layer (2, 30) to the first semiconductor layer (1).

Inventors: HAGINO HIROYASU, HAGINO, HIROYASU, HAGINO, HIROYASU, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H01L29
IPC codes: H01L29