FSK data waveform shaping circuit

Abstract: A FSK data signal voltage inputted from an input terminal 4 is converted into current by a resistance R₁ and then the current is differentially amplified with respect to a reference voltage of a capacitor C₁ in a second differential amplifier circuit 2. As a result, a waveform-shaped signal is generated from each collector of transistors Q₂ and Q₃ constituting the second differential amplifier circuit 2. Meanwhile, the FSK data signal inputted from the input terminal 4, after an alternating current signal component thereof is removed, is applied to a third differential amplifier circuit 3 wherein a difference between the signal and the reference voltage of the capacitor C₁ is amplified. Charging/discharging the capacitor C₁ is controlled in response to an output of the third differential amplifier circuit 3.

Description: The present invention relates generally to FSK data waveform shaping circuits, and more particularly, to a waveform shaping circuit for use in a FSK data receiving system. The FSK data receiving system is for receiving FSK (Frequency Shift Keying) modulated data and it is used, for example, as the paging system. The paging system is a system wherein the determination is made whether or not received FSK data includes predetermined data, to inform a person of the detection of the FSK data including the predetermined data by a buzzer or the like. Fig. 1 is a block diagram showing a general arrangement of a FSK data receiving system for use as such paging system as described above or the like. In the drawing, the FSK data receiving system comprises a radio frequency amplifier circuit 31, a frequency converting circuit 32, an intermediate frequency amplifier circuit 33, an FM detecting circuit 34, a low pass filter 35, a waveform shaping circuit 36 and a CPU 37. The CPU 37 has the functions of FSK demodulation by discriminating the width of output pulse of the waveform shaping circuit 36, control of a receiving block based on the demodulated signal and calling or displaying. In the FSK data receiving system structured as described above, a direct current level of detection output of the FM detecting circuit 34 fluctuates due to fluctuations of the local oscillating frequency of the frequency converting circuit 32 and variations of characteristics of the FM detecting circuit 34 and the like. In the FSK demodulation, demodulation by discriminating the pulse width, because the data has the direct current level, it is impossible to perform fidelity demodulation by a waveform shaping circuit simply comparing the detection output with a fixed reference potential. Therefore, such waveform shaping circuit as shown in Fig. 2 is conventionally used in common. In Fig. 2, a terminal 41 receives an FM detecting signal V DET through the low pass filter 35 of Fig. 1. A time constant circuit comprising a resistance R 41 and a capacitor C 41 is connected between the terminal 41 and a non-inversion input terminal of a comparator 42. Since the frequency of a signal to be used in the FSK system is several hundreds Hz, the time constant of the time constant circuit is set to be relatively large. In addition, a resistance R 42 of the same resistance value as the resistance R 41 is connected between the terminal 41 and the inversion input terminal of the comparator 42 to prevent offset. Furthermore, the power supply terminal of the comparator 42 is grounded through a control transistor Q 41 . A battery save signal (referred to simply as a control signal) V BS which intermittently attains a high level is inputted to the base of the control transistor Q 41 . Consequently, the waveform shaping circuit 36 intermittently operates, which reduces power consumption. The control signal V BS is also supplied to other circuit blocks of the FSK data receiving system. Now, referring to a waveform diagram of Fig. 3, the operation of the conventional waveform shaping circuit shown in Fig. 2 will be described. As shown in Fig. 3, the control signal V BS is an intermittent signal attaining a high level in the periods I and II and a low level in the period III. When the control signal V BS attains the high level, the comparator 42 is brought into operation and the other circuit blocks start operating, so that the FM detecting signal V DET is inputted to the terminal 41. Then, in the period II after the lapse of about τ (= C 41 R 41 ) from the rise of the control signal V BS , the time constant circuit inputs a mean value voltage V AV of the FM detecting signal V DET to the non-inversion input terminal of the comparator 42. In the period III wherein the control signal V BS attains the low level after the period II, electric charges charged in the capacitor C 41 of the time constant circuit are discharged through the resistance R 41 and the low pass filter 35. Accordingly, out of the respective periods wherein the control signal V BS attains the high level, the comparator 42 performs accurate waveform shaping only in the period II. For the purpose of simplicity, the waveform of the FM detecting signal V DET of Fig. 3 is demodulation of the FSK data signal modulated by the data simply cycling "1010...". As the foregoing, in the conventional waveform shaping circuit shown in Fig. 2, the electric charges charged in the capacitor C 41 of the time constant circuit are discharged every time the idle period III comes as shown in Fig. 3. Therefore, even if the control signal V BS attains the high level, the normal waveform shaping operation can not be performed in the period I, whereby the power consumption during the period will be a wast. Accordingly, the electric power can not be made full use of. In addition, since the time constant circuit has a time constant of about 200 ms, it can not respond to transient fluctuations in a direct current level, causing the frequency to shift, which results in that accurate waveform shaping can not be performed. US-A-4 400 732 discloses a PCM signal extracting circuit which does not require FM detection. In this circuit, an input coupling capacitor is used to cut-off the DC component of the PCM signal, and a DC bias voltage is applied. Therefore, this known circuit is not capable of compensating for the output DC voltage of the FM detection. It is therefore an object of the invention to provide a waveform shaping circuit for reducing power consumption. An other object of the invention is to provide a waveform shaping circuit having excellent transient characteristics and by which accurate waveform shaping can be performed and which can compensate fluctuations in the output DC voltage of the FM detection. This object is achieved by a FSK data waveform shaping circuit as defined in claim 1; claim 2 refers to a further development of the invention. In the present invention, discharging the electric charges of the capacitance means can be prevented in an idle period. In addition, transient characteristics can be improved by rapidly charging/discharging the capacitance means by the output signal of the third differential amplifier circuit. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Figs. 1 is a block diagram showing a general arrangement of a FSK data receiving system. Fig. 2 is a circuit diagram showing an arrangement of a conventional FSK data waveform shaping circuit. Fig. 3 is a waveform diagram explaining an operation of the conventional waveform shaping circuit shown in Fig. 2. Fig. 4 is a circuit diagram showing an arrangement of a FSK data waveform shaping circuit according to one embodiment of the present invention. Fig. 5 is a waveform diagram showing an operation of the embodiment shown in Fig. 4. Fig. 4 is the circuit diagram showing the FSK data waveform shaping circuit according to one embodiment of the present invention. In the drawing, the waveform shaping circuit comprises first to third differential amplifier circuits 1 to 3. The first differential amplifier circuit 1 includes a transistor Q 1 having a base and a collector short-circuited to each other and a transistor Q 4 having an emitter connected to an emitter of the transistor Q 1 . The second differential amplifier circuit 2 includes a transistor Q 2 having a base and an emitter respectively connected to the base and the emitter of the transistor Q 1 and a transistor Q 3 having a base and an emitter respectively connected to a base and the emitter of the transistor Q 4 . Each emitter of the transistors Q 1 , Q 2 , Q 3 and Q 4 is connected in common to a collector of a current source transistor Q 21 . In addition, the third differential amplifier circuit 3 includes a transistor Q 5 having a base connected to the respective bases of the transistors Q 1 and Q 2 and a transistor Q 6 having a base connected to the respective bases of the transistors Q 3 and Q 4 . An input terminal 4 receives the output signal of the FM detecting circuit 34 shown in Fig. 1 through the low pass filter 35. The output signal voltage from the low pass filter 35 applied to the input terminal 4 is converted into current by a resistance R 1 and then supplied to the bases of the transistors Q 1 and Q 2 . Herein, since the transistor Q 1 has the base and the collector directly connected with each other, a base voltage thereof is virtually grounded in an alternating manner. Therefore, assuming that the voltage of the output signal from the low pass filter 35 which is applied to the input terminal 4 is V DET and the resistance value of the resistance R 1 is r1, a current value is represented as V DET /r1 and varies only with the voltage V DET . Then, the current converted by the resistance R 1 is amplified by the first and second differential amplifier circuits 1 and 2 and the amplified current is transmitted from collectors of the transistors Q 2 and Q 3 constituting the second differential amplifier circuit 2 to the circuits in the succeeding stage. Since the base of the transistor Q 5 constituting the third differential amplifier circuit 3 is connected to the base of the transistor Q 1 constituting the first differential amplifier circuit 1, the current converted by the resistance R 1 is amplified also in the third differential amplifier circuit 3, so that output current is generated at collectors of the transistors Q 5 and Q 6 . The output current of the transistors Q 5 is applied to a current mirror circuit comprising transistors Q 7 and Q 8 . The output current of the transistor Q 6 is applied to a current mirror circuit comprising transistors Q 11 and Q 12 through a current mirror circuit comprising transistors Q 9 and Q 10 . Accordingly, a current having the value of the difference between the output current of the transistor Q 5 and the output current of Q 6 is generated at a connection point P between the collector of the transistor Q 8 and the collector of Q 12 . Then, the difference current charges/discharges a capacitor C 1 provided between the bases of the transistors Q 3 , Q 4 and Q 5 connected in common and ground. For example, if the base direct current voltage of the transistor Q 5 becomes higher than the base direct current voltage of the transistor Q 6 , collector current of the transistor Q 8 becomes larger than collector current of the transistor Q 12 , so that capacitor C 1 is charged. In addition, when the base direct voltage of the transistor Q 5 becomes lower than the base direct current voltage of the transistor Q 6 , the collector current of the transistor Q 8 becomes smaller than the collector current of the transistor Q 12 , so that the capacitor C 1 is discharged. Now, with the capacitor being completely discharged, if the output voltage V DET of the FM detecting circuit 34 is applied to the input terminal 4, the transistors Q 1 , Q 2 and Q 5 are rendered conductive in response to the direct current voltage V AV . Therefore, current corresponding to the collector current of the transistor Q 5 is applied to the capacitor C 1 through the transistors Q 7 and Q 8 , whereby the capacitor C 1 is charged. After the lapse of a predetermined time period, a terminal voltage of the capacitor C 1 attains V AV , so that bias of the first and second differential amplifier circuits 1 and 2 becomes appropriate. In this state, when a signal voltage (alternating current voltage) in the output voltage of the FM detecting circuit 34 is applied to the input terminal 4, the signal voltage is converted into current by the resistance R 1 and the current is supplied to the transistors Q 1 and Q 2 . As a result, the first and second differential amplifier circuits 1 and 2 perform an amplificating operation (comparing operation) by using the terminal voltage V AV of the capacitor C 1 as a reference, whereby output signals are generated at the collectors of Q 2 and Q 3 . On this occasion, while the current corresponding to the above-described signal voltage is applied also to the base of the transistor Q 5 , setting a charging/discharging constant of the capacitor C 1 larger than a signal cycle prevents the terminal voltage of the capacitor C 1 from following the signal change, so that the reference voltage does not widely vary. The output voltages developed at the collectors of the transistors Q 2 and Q 3 are applied to emitters of transistors Q 13 and Q 14 . Each of the transistors Q 13 and Q 14 is connected to a diode-connected transistor Q 15 in a current-mirror manner. In addition, collector current of the transistor Q 15 is fixed corresponding to collector current of a current source transistor Q 16 . Therefore, when the output signal of the second differential amplifier circuit 2 is 0, emitter voltages of the transistors Q 13 and Q 14 become equal to an emitter voltage of the transistor Q 15 , so that collector current of the transistors Q 13 and Q 14 becomes equal to the collector current of the transistor Q 15 . Since a transistor Q 17 receiving the collector current of the transistor Q 13 constitutes a current-mirror circuit together with a transistor Q 18 , collector current of the transistor Q 18 becomes equal to the collector current of the transistor Q 13 . Herein, as described above, when the output signal of the second differential amplifier circuit 2 is 0, the collector current of the transistor Q 14 becomes equal to the collector current of the transistor Q 13 . Accordingly, in this case, the collector current of the transistor Q 14 and the collector current of the transistor Q 18 become equal to each other, so that no current is supplied to a base of a transistor Q 19 . Accordingly, the transistor Q 19 is turned off, whereby an output signal of a "H" (logical high) level is generated at an output terminal 5. In addition, assuming that an output voltage rendering the emitter voltage of the transistor Q 14 higher than that of the transistor Q 13 is generated from the second differential amplifier circuit 2, the collector current of the transistor Q 14 becomes larger than those of the transistor Q 13 . As a result, the collector current of the transistor Q 14 becomes larger than that of the transistor Q 18 , so that the transistor Q 19 is turned on. Consequently, an output signal of a "L" (logical low) level is generated at the output terminal 5. On the contrary, when an output voltage rendering the emitter voltage of the transistor Q 13 higher than that of the transistor Q 14 is generated from the second differential amplifier circuit 2, the transistor Q 19 is turned off, so that an output signal of the "H" level is generated at the output terminal 5, as in the above-described case wherein the output signal of the second differential amplifier circuit 2 is 0. Now, an operation of the embodiment of Fig. 4 in relation to a battery save signal V BS and a charge control signal V C will be described in reference to the waveform diagram of Fig. 5. In a battery saved state, the battery save signal V BS cycles the "H" level and the "L" level continuously and the charge control signal V C remains at the "L" level. In a signal received state, both of the battery save signal V BS and the charge control signal V C attain the "H" level, so that the entire circuit of Fig. 4 is brought into a normal operation. When the battery save signal V BS attains the "H" level, a transistor Q 20 is turned on and a diode-connected transistor Q 22 is turned on. In response thereto, the current source transistors Q 21 and Q 16 are turned on. When the charge control signal V C attains the "H" level, a transistor Q 23 is turned on, so that the third differential amplifier circuit 3 starts operating. In the signal received state, since both of the battery save signal V BS and the charge control signal V C attain the "H" level as shown in Fig. 5, a normal waveform shaping operation is carried out wherein an output signal V 0 as shown in Fig. 5 is generated at the output terminal 5. On this occasion, the terminal voltage of the capacitor C 1 becomes equal to the direct current voltage V AV in the input signal by the third differential amplifier circuit 3, as shown in Fig. 5. On entering the battery saved state, the charge control signal V C attains the "L" level, so that the third differential amplifier circuit 3 is turned off. As a result, the terminal voltage of the capacitor C 1 becomes the direct current voltage V AV in the input signal immediately before entering the battery saved state and remains at the same value during the battery saved state. Then, on entering another signal received state, since the terminal voltage of the capacitor C 1 is approximately V AV , the waveform shaping operation is immediately started. In addition, since the third differential amplifier circuit 3 starts operating on entering the signal received state, the slight discharge of the capacitor C 1 is immediately compensated for. Accordingly, the output signal V 0 obtained at the output terminal 5 has a right waveform immediately after entering the signal received state, as shown in Fig. 5. In the signal received state, if frequency shift of the carrier of the received signal occurs due to drift of the local oscillating frequency and the like, the direct current voltage in the output signal of the FM detecting circuit 34 varies. In the waveform shaping circuit of Fig. 4, if such change of the direct current voltage occurs, the third differential amplifier circuit 3 immediately detects the change and charges/discharges the capacitor C 1 to cause the terminal voltage of the capacitor C 1 to follow the direct current voltage after the change. Accordingly, even when the frequency shift occurs, it is possible to generate an output signal of the right waveform in a short time period. As an example, in case of Fig. 4, with respect to an input signal of about 500 Hz, the normal operation can be restored to in about 15 ms. Furthermore, since the transistor Q 1 is diode-connected, and its base is virtually grounded in an alternating manner, the input signal voltage applied to the input terminal 4 is converted into current only by the resistance R 1 . Therefore, the input signal voltage can be linearly converted into current. As described above, with the waveform shaping circuit according to the present invention, it is possible to perform an accurate waveform shaping except for in a predetermined time period after the application of the main power and remarkable effects can be obtained such as excellent transient characteristics. In particular, in the battery save state, the reference level can be maintained, whereby when the direct current voltage varies due to the frequency shift, it is possible to immediately cause the reference level to follow the change. Besides, it is also possible to cause the reference level not to follow the alternating current voltage of the input signal, and therefore rapid and accurate waveform shaping can be performed.

Claims: A FSK data waveform shaping circuit for waveform shaping FM-detected FSK data and outputting the waveform shaped FSK data comprising: a first differential amplifier circuit (1) including first and second transistors (Q1, Q4), said first transistor (Q1) having its base and collector short-circuited to each other, a second differential amplifier circuit (2) including third and fourth transistors (Q2, Q3), said third transistor (Q2) having its base and emitter respectively connected to the base and the emitter of said first transistor (Q1) and said fourth transistor (Q3) having its base and emitter respectively connected to the base and the emitter of said second transistor (Q4), a third differential amplifier circuit (3) including fifth and sixth transistors (Q5, Q6), said fifth transistor (Q5) having its base connected to the base of said first transistor (Q1) and said sixth transistor (Q6) having its base connected to the base of said second transistor (Q4), and capacitance means (C1) connected between the base of said second transistor (Q4) and ground and charged/discharged, in response to the output signal of said third differential amplifier circuit (3), by a charge/discharge means (Q7-Q12), the charge/discharge time constant of said capacitance means (C1) being larger than a cycle of the FSK data signal; the base of said first transistor (Q1) receiving the FSK data to be waveform-shaped, and a waveform-shaped output signal being generated at least at one of the collectors of said third and fourth transistors (Q2,Q3). A FSK data waveform shaping circuit according to claim 1, wherein said first and second differential amplifier circuits (1, 2) have a current source transistor (Q21), said current source transistor (Q21) being intermittently driven in response to a battery save signal (V BS ).

Inventors: ISHIGURO KAZUHISA, SEKIGUCHI YUTAKA, ISHIGURO, KAZUHISA, SEKIGUCHI, YUTAKA
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1990
Main classification: H04L27
IPC codes: H04L27, H03K5, H04B1