A level shift circuit for achieving a high-speed processing and an improved output current capability

Abstract: A level shift circuit of the present invention includes an input differential pair of transistors (Q1, Q2),as an input circuit section, which are operated in accordance with the level of an input signal supplied from a preceding circuit and an output circuit section composed of first and second emitter follower transistors (Q3, Q4). A third transistor (M1) has its current path connected at one end to an emitter of the first emitter follower transistor (Q3) and makes an output level of the first emitter follower transistor (Q3) at a predetermined level. A fourth transistor (M2) has its current path connected at one end to the other end of the third transistor (M1) and is driven by an output voltage of the second emitter follower transistor (Q4) to allow an output level of the first emitter follower transistor (Q3) to be shifted to a low level. An inverter circuit is connected to the outputs of the first and second emitter follower transistors (Q3, Q4) and composed of a P- and a N-channel transistor (M3, M4) commonly connected at their adjacent paths to each other. The inverter circuit is operated in accordance with an output level of the first emitter follower transistor (Q3) to allow an output level of the second emitter follower transistor (Q4) to be output from that common connection point.

Description: The present invention relates to a level shift circuit and, in particular, to a level shift circuit suitable for an integrated circuit device of an ECL-CMOS configuration. Of semiconductor IC devices, a bipolar complementary MOS (Bi-CMOS) structure is known generally as one of hybrid LSI's of analog/digital functions. In an IC device of a Bi-CMOS configuration, an ECL-CMOS level shift circuit is sometimes inserted, for example, between an ECL (Emitter-Coupled-Logic) and a circuit of a CMOS configuration. The level shift circuit is of such a type that, when an ECL signal cannot be input directly to the circuit of a CMOS configuration, the level shift circuit shifts that signal level to a predetermined level. In the level shift circuit, an emitter follower transistor for output is normally connected to a multi-input differential stage so that it operates at a non-saturated region. The level shift circuit normally comprises a differential pair-transistor circuit section, an output transistor circuit section driven upon receipt of a drive signal from the differential pair-transistor circuit to shift that input signal level to a predetermined level, and so on. In order to decrease a transmission delay time in the level shift circuit and achieve a high-speed processing throughout the whole circuit, a high-speed switching operation has to be achieved at the output transistor. Such a technique is performed normally by decreasing a capacitance of an output transistor, or the size of elements formed over a semiconductor substrate, and increasing a current by which the output transistor is driven. However, a decrease in capacitance of the output transistor results in a decreased output current capability of the level shift circuit. In order to increase a drive current of the output transistor, the output current of the differential pair transistor circuit can be increased but it is necessary to increase a current by which the differential pair transistor circuit is driven. In order to enhance an output current capability while maintaining a high-speed processing, it will be necessary to increase the size of the output transistor and hence to increase its drive current which is supplied as an output current from the differential-pair transistor circuit. Further, the increase in the drive current and hence the output current results in an increase in dissipation power throughout the whole circuit and hence in quantity of heat evolved in the circuit itself. On the other hand, a decrease in dissipation current (dissipation power) of the circuit is required from another aspect to achieve a higher integration density or higher microminiaturization for a semiconductor circuit. If a low dissipation power circuit is to be achieved by decreasing the drive current and output current of each element, the transistor in the circuit as set out above is delayed in switching operation, involving a longer signal transmission delay time and decreasing an output current capability of the level shift circuit. Even if the coming of an input signal is awaited at a standby time, a standby current needs to be flowed so as to effect a high-speed switching operation in the level shift circuit. If, in this case, such a standby current is to be decreased so as to decrease a dissipation current, then the output transistor becomes slower in switching operation to adversely affect a high/low (H/L) level difference. It is accordingly the object of the present invention to provide a level shift circuit which can achieve a high-speed processing by decreasing a signal transmission delay time without decreasing a dissipation power (dissipation current) and can improve an output current capability. Reference is made to IEEE Journal of Solid State Circuits, col. 23, no. 5, Oct. 1988, pages 1036 and 1037, in which, with reference to Fig. 14 thereof, there is shown an ECL/CMOS translator including a differential amplifier, in the form of an input differential pair of transistors, an emitter follower transistor pair whose transistors respectively receive the outputs of the input differential transistors, and cross-coupled NMOS transistors providing active pull-down at the outputs of the emitter follower transistor. According to the present invention there is provided a level shift circuit for achieving a high-speed processing and an improved output current capability, comprising: an input differential pair of transistors switchingly operated in accordance with a level of an input signal; first and second emitter follower transistors for receiving an output of the transistors in input differential pair; a third transistor having its current path connected at one end to an emitter of the first emitter follower transistor and at the other end to a reference potential and its control electrode connected to an emitter of the second emitter follower transistor and driven by an output voltage of the second emitter follower transistor to allow an output level of the first emitter follower transistor to be shifted to a low level; and a fourth, N-channel, transistor having its current path connected at one end to an emitter of the second emitter follower transistor and at the other end to said reference potential and its control electrode connected to an emitter of the first emitter follower transistor; characterized in that it further comprises a fifth transistor having its current path connected at one end to the emitter follower transistor and its other end connected to said one end of the current path of said third transistor and making an output level of the first emitter follower transistor at a predetermined level; and a sixth, P-channel, transistor whose current path is connected between the emitter of the second emitter follower transistor and the current path of the fourth transistor, said fourth and switch transistors together forming inverter means operated in accordance with an output level of the first emitter follower transistor and the common connection between the current paths of the fourth and sixth transistors being connected to an ouput terminal to allow an output level of the second emitter follower transistor to be output as an inverted level from that common connection point. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing an ECL-CMOS level shift circuit according to one embodiment of the present invention; Fig. 2 shows voltage waveforms at specific points in the level shift circuit shown in Fig. 1; and Fig. 3 shows a differential input circuit responsive to a plurality of input signals, which is used in place of a differential-pair transistor input circuit in the level shift circuit shown in Fig. 1. One embodiment of the present invention will be explained below with reference to the accompanying drawings. Fig. 1 is a circuit arrangement showing an ECL-CMOS level circuit according to a first embodiment of the present invention. In the level circuit shown in Fig. 1, a differential-pair of transistors Q1, Q2 are provided in which an input signal is supplied from an input terminal 1 to the base of the transistor Q1 and a reference potential is supplied from an input terminal 2 to the base of the transistor Q2. The collectors of the transistors Q1 and Q2 are connected respectively through resistors R1 and R2 to a power source VCC and the emitters of these transistors are connected to each other via a constant current source 3. The collector of the transistor Q1 is connected to the base of an emitter follower transistor Q3 and the collector of the transistor Q2 is connected to the base of an emitter follower transistor Q4. Upon receipt of the input signals, the transistors Q1 and Q2 in that differential pair deliver their output signals to the emitter follower transistors Q3 and Q4, driving these transistors Q3 and Q4. The transistor Q3 has its collector connected to the power source VCC and its emitter connected to the source of a grounded-gate, P channel MOS transistor M1. The drain of the P channel MOS transistor M1 is connected to that of an N channel MOS transistor M2. The MOS transistor M2 has a grounded source and a gate connected to the emitter of the transistor Q4. The transistor Q4 has its collector connected to the power source VCC and its emitter connected to the source of a P channel MOS transistor M3. The drain the transistor M3 is connected to that of an N channel transistor M4. The MOS transistors M3 and M4 constitute an inverter circuit. The gates of the transistors M3 and M4 are commonly connected to a connection point between the transistors M3 and M4. The drain of the transistors M3 and M4 are connected to a common connection point which is connected to an output terminal 4. The operation of the level shift circuit will be explained below with reference to voltage waveforms at predetermined circuit points. The voltage waveforms show voltage levels of the respective transistors at measuring points c to f shown in Fig. 1. The transistors Q3 and Q4 are turned ON and OFF, respectively, when they receive corresponding differential input signals switchingly supplied from the transistors Q1 and Q2. In this case, a current Ia flows along a line a as shown in Fig. 1. A "H" level signal appears on a measuring point c on the line a and the transistor M1 is turned ON to allow a "H" level signal to emerge on the measuring point e. If, in this case, the transistor Q4 is turned OFF, the transistors M3 and M4 are turned ON upon receipt of the "H" level signal on the measuring point c so that a "L" level output appears from the CMOS inverter at the measuring point f. As a result, a "L" level signal emerges on the measuring point d connected to the gate of the transistor M2 and a gate/drain voltage V GS of the transistor M2 emerges as a "L" level one. As will be appreciated from the above, the level shift circuit is of such a type as to achieve a high-speed switching operation using a standby current. In an usual case, a "L" level voltage is used as a standby level instead of a "H" level one, whereby a drain current is reduced and hence a current Ia on the connection line a is reduced. With the transistor Q3 OFF and the transistor Q4 ON, a "L" level voltage appears on the measuring point c and a current Ib flows along a connection line b as shown in Fig. 1. A "H" level voltage emerges on the measuring point d and the transistor M2 is turned ON so that a voltage on the measuring point e goes toward a ground level. Put it in another way, a rise voltage Vth on the transistor M4 drops by an extent corresponding to a drain/ground voltage on the transistor M2 and the output of the CMOS inverter at the measuring point f goes high. As will be appreciated from the above, rise voltages Vth (g, k in Fig. 2) on the transistors M3 and M4 vary upon receipt of the input signal switchingly delivered from the transistors in differential pair. It is thus possible to maintain a transmission delay time even if a current Ia at the standby time is reduced. As indicated by an input circuit section in Fig. 3, a plurality of transistors Q1, Q2, Q3 ... Qn can be constructed, instead of the differential pair of transistors Q1, Q2 as enclosed by a broken line in Fig. 1, to supply corresponding input signals to associated circuits. According to the present invention, as set out above, the inverter circuit is added to the output circuit section, achieving a decreased transmission delay time and hence a high-speed processing. Since a high-speed switching operation is achieved by a standby current supplied to the output transistors and a combination of an emitter follower configuration and transistor operated by an opposite-phase current, a standby current normally flowing at the time of standby is shifted to a low level one, whereby it is possible to achieve a low dissipation power. Thus the output current capability of the output transistor can be improved with the use of the saved dissipation power, that is, the output current capability is improved by utilizing a saved dissipation power for an output transistor now possible to increase in size for a reason as set out above. Even if the output transistor is increased in size, a quantity of heat evolved is not increased since other circuit elements dissipate less electric power. As will be understood from the above, the level shift circuit of the present invention can achieve a decreased transmission delay time and hence a high-speed processing and achieve an improved output current capability and hence a reduced dissipation power.

Claims: A level shift circuit for achieving a high-speed processing and an improved output current capability, comprising: an input differential pair of transistors (Q1, Q2) switchingly operated in accordance with a level of an input signal; first and second emitter follower transistors (Q3, Q4) for receiving an output of the transistors in input differential pair; a third transistor (M2) having its current path connected at one end to an emitter of the first emitter follower transistor (Q3) and at the other end to a reference potential and its control electrode connected to an emitter of the second emitter follower transistor (Q4) and driven by an output voltage of the second emitter follower transistor (Q4) to allow an output level of the first emitter follower transistor (Q3) to be shifted to a low level; and a fourth, N-channel, transistor (M4) having its current path connected at one end to an emitter of the second emitter follower transistor (Q4) and at the other end to said reference potential and its control electrode connected to an emitter of the first emitter follower transistor (Q3); characterized in that it further comprises a fifth transistor (M1) having its current path connected at one end to the emitter follower transistor (Q3) and its other end connected to said one end of the current path of said third transistor (M2) and making an output level of the first emitter follower transistor (Q3) at a predetermined level; and a sixth, P-channel, transistor (M3) whose current path is connected between the emitter of the second emitter follower transistor (Q4) and the current path of the fourth transistor (M4), said fourth and switch transistors (M4, M3) together forming inverter means operated in accordance with an output level of the first emitter follower transistor (Q3) and the common connection between the current paths of the fourth and sixth transistors (M4, M3) being connected to an ouput terminal (4) to allow an output level of the second emitter follower transistor (Q4) to be output as an inverted level from that common connection point. A level shift circuit according to claim 1, characterized in that said P- and N-channel transistors (M3, M4) constituting said inverter means are of a MOS structure to allow achievement of a high-speed processing and an improved output current capability. A level shift circuit according to claim 1, characterized in that said inverter means performs an inverting operation, by an opposite-phase current, against an operation of an emitter follower transistor configuration. A level shift circuit according to any preceding claim, wherein one (Q2) of the transistors of the input differential pair is itself one of a plurality of further transistors (Q3, ... Qn) each connected in the same way to the other transistor (Q1) of the input differential pair to be switchingly operated in accordance with levels of a plurality of input signals, each of said further transistors (Q3, ... Qn) being respectively connected to supply input signals to corresponding circuitry, each of which is the same as that to which said one differential transistor (Q2) is connected to supply input signals as aforesaid.

Inventors: UENO MASAJI C O INTELLECTUAL P, UENO, MASAJI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H03K19
IPC codes: H03K19, H01L27, H01L21