Method of manufacturing semiconductor laser

Abstract: According to this invention, a first cladding layer (2) of a first conductivity type, an active layer (3), a second cladding layer (4) of a second conductivity type, and a cap layer (5) much more susceptible to side etching than the second cladding layer (4) are sequentially grown on a (100) crystal plane of a semiconductor substrate (1) of the first conductivity type, and a stripe-like mask (7) extending in a <011> direction is formed on the grown substrate to etch the stacked substrate. This etching is performed in a crystal orientation for forming an reverse triangular mesa. However, since the cap layer (5) is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer (10) is formed on the etched portion by a vapor phase epitaxy method, the burying layer (10) having a flat surface can be obtained depending on crystal orientations.

Description: Background of the Invention (Field of the Invention) The present invention relates to a method of manufacturing a semiconductor laser and, more particularly, a buried semiconductor laser. (Description of the Related Art) Compared with a liquid phase epitaxy method, a vapor phase epitaxy (VPE) method, especially an organometallic vapor phase epitaxy (OMVPE) method, has the following advantages: (1) the VPE method can be applied to a large wafer, (2) the VPE method has good controllability of the thickness of a layer, and (3) the VPE method requires a short time in growth process as a whole. Therefore, the VPE method has been employed to form a burying layer of a semiconductor laser. As a method of manufacturing a buried semiconductor laser (especially an InP long-wavelength laser) by an OMVPE method or the like, the following methods are proposed. That is, as shown in Fig. 1A, a reverse triangular mesa 23 is formed using a stripe-like mask 22 formed on an InP cladding layer 21 as an etching mask, and, as shown in Fig. 1B, the reverse triangular mesa 23 is buried by a burying layer 24 using a VPE method. This method is disclosed in the Journal of Applied Physics vol. 64 (1988) pp.3684 - 3688. In another related art, as shown in Fig. 2A, a rectangular mesa 31 is formed, and, as shown in Fig. 2B, the rectangular mesa 31 is buried by a VPE method. This method is disclosed in the Journal of Applied Physics vol. 64 (1988) pp.3684 - 3688, or the Journal of Crystal Growth vol. 93 (1988) pp.248 - 253. In still another related art, a mesa is formed, and this mesa is buried by an VPE method, as shown in Fig. 3. This method is disclosed in the Journal of Applied Physics vol. 64 (1988) pp.3684-3688. According to the first related art, as shown in Fig. 1B, nongrown portions (grooves) 25 are easily formed in the burying layer 24 near the bottom of the reverse triangular mesa 23 due to a lack of material diffusion from the vapor. When the second related art is employed, nongrown portions (grooves) are formed less than the first related art. However, in the second related art, a height 32 of the mesa 31 and an undercut amount 33 under a mask 34 must be limited in a predetermined range. According to the above literature, the mesa height is less than 3 µm, and the undercut amount is about 1 µm when the mesa height is 2.5 µm. According to the third related art for performing burying growth in a crystal orientation for forming a curved mesa, as shown in Fig. 3, a (111)A crystal plane is formed on a burying layer 41, and the burying layer 41 extends on the mask 42 along this crystal face. Therefore, the mesa cannot be buried in a flat surface. Furthermore, the document J. L. Vossen et al., Thin Film Processes, Part V-1, pages 401 - 481, Academic Press, NY (1978) discloses a method in which a very thin layer of material which dissolves in an etchant more rapidly than a substrate film may be deposited prior to masking to achieve a small amount of controlled undercutting, since a sloped substrate edge is easier to coat uniformly than a sharp edge, if additional layers are to be deposited subsequently. Summary of the Invention It is an object of the present invention to solve the above problems. That is, it is an object of the present invention to provide a method of manufacturing a semiconductor laser, capable of forming a burying layer having a flat surface using an VPE method. This object is solved with the measures of claim 1. Particular embodiments of the invention are set out in the dependent claims 2 to 4. In particular, the direction of the mask formed on the cap layer is a direction for easily forming a reverse triangular mesa in the next etching step. However, since the cap layer is made of a material susceptible to side etching, namely, the material with a larger etching rate on (111)B plane than that of the second cladding layer, a rounded mesa which is tapered upward is formed. For this reason, in the next burying step, a nongrown portion is not formed at the proximal end of the mesa. In addition, unlike in a case wherein burying growth is performed in a crystal orientation for forming a rounded mesa, a (111)A crystal plane is not formed. Therefore, abnormal growth on the mask does not occur, and a burying layer having a flat surface is formed. Brief Description of the Drawings The invention is described in detail below with reference to the drawings, in which Figs. 1A, 1B, 2A, 2B and 3 are sectional views showing related arts, respectively; Figs. 4A to 4E are sectional views showing the steps in manufacturing a semiconductor laser according to the first embodiment of the present invention; and Figs. 5A and 5B are sectional views for explaining an optimal height of a burying layer. Detailed Description of the Preferred Embodiment An n-type Si-doped InP first cladding layer 2, an undoped GaInAsP active layer 3, a p-type Zn-doped InP second cladding layer 4, and a p-type Zn-doped cap layer 5 made of GaInAs as defined in Claim 1 are sequentially grown on an n-type Sn-doped InP (100) substrate 1 by a low-pressure organometallic vapor phase epitaxy method (low-pressure OMVPE method) to form a multi-layered substrate 6 (refer to Fig. 4A). Each thickness of the above layers is set as follows. The n-type InP first cladding layer has a thickness of 1 µm, the undoped GaInAsP active layer 3 has a thickness of 0.15 µm, the p-type InP second cladding layer 4 has a thickness of 0.4 µm, and the p-type GaInAs cap layer 5 has a thickness of 0.2 µm. An SiO₂ film is deposited on the multi-layered substrate 6 by a thermal chemical vapor deposition method (thermal CVD method). The SiO₂ film is coated with a resist film, and a stripe pattern of the resist film having a width of 6 µm is formed in a <011> direction (a direction perpendicular to the drawing surface), i.e., a direction for forming a reverse triangular mesa. The SiO₂ film is selectively etched by buffered hydrofluoric acid using the resist film as a mask to form a stripe SiO₂ film 7, and the remaining resist film is removed (Fig. 4B). At this time, the width of the stripe SiO₂ film 7 is slightly narrowed by side etching to be about 5 µm. The layers 2 to 5 are selectively etched using the stripe SiO₂ film 7 as a mask by an etchant (a volume ratio of Br₂ : methanol = 2.5 : 1000) made of Br-methanol sufficiently cooled with ice water to be about 0°C. This etching is performed for about 5 minutes while the etchant is churned, thereby forming a mesa having a depth 12 of about 2.5 µm and a side etching amount (undercut amount) 11 of about 1.7 µm (refer to Fig. 4C). According to an experiment performed by the present inventor, when the Br-methanol etchant (a volume ratio oF Br₂ : methanol = 2.5 : 1000) is used, an undercut amount of 0.5 to 0.7 per etching depth of 1 can be obtained. Although a crystal orientation is conventionally used to form a reverse triangular mesa in etching using the Br-methanol etchant, a rounded mesa tapered upward shown in Fig. 4C can be obtained. This is because the cap layer 5 susceptible to side etching by the Br-methanol etchant is formed immediately below the stripe SiO₂ film 7 for selective etching. Note that the active layer 3 according to this embodiment has a width of 1.5 µm at which fundamental transverse mode oscillation can be performed. A multi-burying layer 10 consisting of a p-type Zn-doped InP layer (thickness: about 1 µm) 8 and an n-type Si-doped InP layer (thickness: about 1 µm) 9 is grown by a low-pressure OMVPE method using the stripe SiO₂ film 7 as a selective growth mask (Fig. 4D). The InP layers 8 and 9 constituting the burying layer 10 are gradually thin from the lower portion of the mesa to the upper portion thereof, and the burying layer 10 can be formed such that its surface is almost parallel to the surface of the substrate 1. In addition, the burying layer 10 is a two-layered structure always having a correct deposition order at any place on the mesa side surface. Therefore, a pnpn structure (thyristor) is properly formed on the entire outer surface of the mesa by a third cladding layer 13 to be formed later, burying InP layers 9 and 8, and the first cladding layer 2, and the p-type InP layer 8 and the n-type InP layer 9 can serve as current blocking layers. In addition, since the p-type InP layer 8 is gradually made thin toward the upper portion of the mesa on the mesa side surfaces, a path for a leakage current flowing from the second cladding layer 4 to the first cladding layer 2 through the p-type InP layer 8 is narrow. Therefore, the structure for effectively reducing the leakage current can be obtained. The present inventor confirmed that, in the burying growth, no limitations were imposed on a mesa depth for burying the grooves to obtain a flat surface. In addition, the present inventor also confirmed that, in this burying growth, the burying layer 10 was not grown on the side surfaces of the cap layer (GaInAs) 5 immediately below the mask 7. For this reason, even when the burying growth is advanced, a vapor region can be sufficiently left on an undercut portion below the stripe SiO₂ film 7, and a lack of material diffusion can be prevented. In the burying growth, it is important that the height of the surface of the burying layer 10 does not exceed that of the stripe SiO₂ film 7 in order to flatten the surfaces of a third cladding layer and a contact layer formed in the subsequent steps. That is, when the surface height of the burying layer 10 largely exceeds that of the stripe SiO₂ film 7, as shown in Fig. 5A, a (111)B crystal plane is formed on the burying layer 10. Since the growth rate of the third cladding layer and the contact layer are smaller the (111)B crystal plane than on other crystal planes, as shown in Fig. 5B, W-shaped groove is formed on the layers not to flatten the layers. In other words, when the surface of the burying layer 10 exceeds the surface of the stripe SiO₂ film 7 in height only such that the (111)B crystal plane is not formed, the growth of the third cladding layer and the contact layer is not adversely affected. The W-shaped groove causes defective products and degradation of reliability. Especially, since the contact layer on the (111)B crystal plane is thin, a contact resistance of the resultant device is increased, thereby causing degradation of characteristics of the resultant device. Finally, the stripe SiO₂ film 7 is removed using buffered hydrofluoric acid, and the cap layer 5 is removed using an etchant consisting of phosphoric acid : hydrogen peroxide = 5:1. Thereafter, a p-type Zn-doped InP third cladding layer (thickness: about 1.5 µm) 13 and a p-type Zn-doped GaInAs contact layer (thickness: about 0.5 µm)) 14 are sequentially grown by a low-pressure OMVPE method (Fig. 4E). Note that, in this embodiment, the burying layer 10 may have a two-layered structure consisting of layers having different conductivity types, and a block layer using a p-n junction is formed by this structure. However, a high-resistance layer or a multi-layered structure including a high-resistance layer may be used as the burying layer 10 to constitute the block layer using a resistor. The conductivity types of the InP substrate 1, the first to third cladding layers, and the contact layer may be reversed. In this case, the burying layer 10 has a structure formed by stacking a p-type InP layer, an n-type InP layer, and a p-type InP layer, or a structure including a high-resistance layer. The cap layer is not limited to the GaInAs layer as in Claim 1. The cap layer may be made of Ga x In 1-x As y P 1-y (0.6 ≦ y < 1, x ≈ 0.47y). In this embodiment, a Br-methanol etchant is used, the temperature of the etchant is about 0°C, and the concentration of Br is 0.25 %. According to experiments performed by the present inventor, it is confirmed that, when the temperature falls within a range of 0°C to 30°C and the concentration of Br falls within a range of 0.1% to 5%, etching can be performed to substantially form a rounded mesa as in this embodiment. As the temperature is decreased, the reaction is slowed, thus obtaining good controllability. An etchant used in the present invention is not limited to a Br-methanol etchant. That is, this etchant may be an etchant for causing changes in etching rates of cladding layers 2 and 4 and an active layer 3, depending on their crystal faces. Practically, this etchant may be another alcohol solution of a halogen, e.g., an I₂ methanol etchant.

Claims: A method of manufacturing a semiconductor laser, comprising the steps of: sequentially growing a first cladding layer (2) of a first conductivity type, an active layer (3) and a second cladding layer (4) of a second conductivity type on a (100) crystal plane of a semiconductor substrate (1) of the first conductivity type, said substrate (1) and said both cladding layers (2, 4) being made of InP; forming a stripe-like mask (7) extending in a <011> direction on said multi-layered substrate (6); using said mask (7) as an anti-etching material and etching said multi-layered substrate (6) from a surface thereof to reach said first cladding layer (2) by using an etchant which essentially has a smaller etching rate on (111)B crystal plane than on other crystal planes of said multi-layered substrate (6); forming a burying layer (10) by a vapor phase epitaxy method on a region from which said multi-layered substrate (6) is removed by said etching step, using said mask (7) as a selective growing mask; and removing said mask (7) and growing a third cladding layer (13) of the second conductivity type and a contact layer (14) of the second conductivity type on the second cladding layer (4) not being etched and on the burying layer (10); characterized by the following steps: forming a cap layer on said second cladding layer (4) before forming said stripe-like mask (7), with said cap layer (5) being more susceptible to side etching than said second cladding layer (4) and being made of Ga x In 1-x As y P 1-y (0.6 ≦ y ≦ 1, x ≈ 0.47y); carrying out said burying layer forming step such that the surface of the burying layer (10) does not exceed in height the surface of the stripe-like mask (7) so that the (111)B crystal plane is not formed; and removing said cap layer (5) after said mask removing step. A method according to claim 1, wherein a growing method of said burying layer (10) is an organometallic vapor phase epitaxy method. A method according to claim 1 or 2, wherein an etchant used in said etching step is an alcohol solution of a halogen. A method according to claim 3, wherein said alcohol solution of a halogen is a Br-methanol solution.

Inventors: KAMEI HIDENORI C O YOKOHAMA WO, KAMEI, HIDENORI, C/O YOKOHAMA WORKS
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES, LTD.
Application year: 1990
Main classification: H01L33
IPC codes: H01S5, H01L33