Signal output circuit having bipolar transistor in output stage and arranged in CMOS semiconductor integrated circuit

Abstract: A signal from an input terminal is supplied to a CMOS inverter (16). An output from the inverter (16) is supplied to the bases of a pnp bipolar transistor (18) and an npn bipolar transistor (19). The base of an out­ put pnp bipolar transistor (21) is connected to the emitter of one bipolar transistor (18) through a resistor (20) for setting a base current. The base of an output npn bipolar transistor (24) is connected to the emitter of the other bipolar transistor (19) through a resistor (23) for setting a base current. The emitter of one output bipolar transistor (21) is connected to a node (11) for receiving a high-potential power supply voltage (VCC), and its collector is connected to an out­ put terminal (22). The emitter of the other output bipolar transistor (24) is connected to a node (14) for receiving a low potential power supply voltage (VSS) and its collector is connected to the output terminal (22).

Description: The present invention relates to a signal output circuit arranged in a CMOS digital semiconductor integrated circuit and, more particularly, to a signal output circuit having bipolar transistors in an output stage. In a digital semiconductor integrated circuit, when a load is driven by a large current, a signal output circuit having a Bi-CMOS (bipolar-complementary MOS) arrangement is used. Fig. 1 shows an example of a conventional Bi-CMOS signal output circuit. In the signal output circuit, reference numerals 31 and 32 denote p- or n-channel MOS transistors, the gates of which are commonly connected to an input terminal 33, and which perform switching operations in response to a signal from the input terminal 33; 34 and 35, pnp or npn bipolar transistors; 36 and 37, resistors for setting a base current; 38 and 39, pnp or npn output bipolar transistors, the collectors of which are commonly connected to an output terminal 40; and 41 and 42, resistors for absorbing excess base charges of the bipolar transistors 38 and 39. An operation of the circuit will be described in brief. When a signal at the input terminal 33 is "H" level, the p-channel MOS transistor 31 is turned off, and the n-channel MOS transistor 32 is turned on. At this time, a base current is flowed into the pnp bipolar transistor 38 through the bipolar transistor 34 and the resistor 37, so that the transistor 38 is turned on, and the output terminal 40 is charged with a high-potential power supply voltage VCC. On the other hand, when the signal at the input terminal 33 is "L" level, the p-channel MOS transistor 31 is turned on, and the n-channel MOS transistor 32 is turned off. At this time, a predetermined value of the base current is flowed into the npn bipolar transistor 39 through the resistor 36 and the bipolar transistor 35, so that the transistor 39 is turned on, and the output terminal 40 is discharged to a low-potential power supply voltage VSS. After supply of the base current to the transistor 38 is stopped, an excess base charge is absorbed by a node of the power supply voltage VCC through the resistor 41. On the other hand, after supply of the base current to the transistor 39 is stopped, an excess base charge is absorbed by a node of the power supply voltage VSS through the resistor 42. Therefore, a high-speed switching operation performed when the transistors 38 and 39 are turned off can be achieved. In the above-described conventional circuit, in a case that a 2-mA output current is to be obtained from the output terminal 40 when a value of the high-potential power supply voltage VCC is 5 V, a resistance R of the resistor 36 is determined by the following equation, assuming that a current amplification factor hfe(Q39) of the bipolar transistor 39 is, e.g; 5 (since the transistor 39 is operated in a saturation region when it is in an ON state, the current amplification factor at this time is decreased as compared with the operation in a non-suturation region), and a current amplification hfe(Q35) of the bipolar transistor 35 is, e.g; 100 wherein Vf in the following equation is a base-emitter voltage of the npn or pnp bipolar transistor. R = VCC - 2Vf output current hfe Q39 × hfe Q35 = 5 - 1.4 2 × 10 -3 5 × 100 = 900 kΩ As a result, the resistance of the resistor 36 becomes extremely large. Similarly, the resistance of the resistor 37 becomes extremely large. Note that the resistors 41 and 42 for absorbing base charges are normally set in values from 5 kΩ to 10 kΩ. In the above-described signal output circuit, the resistances of the resistors 36 and 37 are extremely large, so that charge and discharge rates of parasitic capacitors of the bases of the transistors 34 and 35 are low. As a result, switching speeds of the output bipolar transistors 38 and 39 are decreased, so the output switching speed is decreased. In addition, in the conventional circuit, the base charges of the output transistors 38 and 39 are absorbed by the resistors 41 and 42. As a result, when the output transistors 38 and 39 are turned on, wasteful currents not used as base currents are flowed into the resistors 41 and 42. Therefore, the base currents of the output transistors 38 and 39 are decreased by the wasteful currents, so that the turn-on speed of the output transistors is decreased, thereby further decreasing the output switching speed. The textbook E.Kühn, "Handbuch TTL- und CMOS-Schaltkreise", 1985, Dr. Alfred Hüthig Verlag, Heidelberg, Germany, pages 317 and 320 discloses the principle of moving a current-limiting resistor from the base to the emitter of a transistor in which the current should be limited. The textbook U. Tietze und Ch. Schenk, "Halbleiter-Schaltungstechnik", 1983, Springer Verlag, Berlin, Heidelberg, New York, Tokyo, pages 554 to 556 discloses the insertion of a current-limiting resistor between the emitter of a first transistor and the base of a second transistor. In Elektor, January 1980, page 48 to 53, J.P. Haas et al. disclose a "Geiger-Müller-Zähler". According to fig. 3 of this document a resistor is located in a Darlington arrangement of a first and a second transistor, namely between the emitter of said first and transistor and the base of said second transistor, said Darlington arrangement being driven by a logic gate. EP-A-0 058 958 discloses a complementary MOSFET logic circuit having a complementary MOS inverter with a pre-given ratio of the channel widths of a p-channel MOSFET and an n-channel MOSFET and pre-given threshold voltages of the FETs so as to provide an input voltage characteristic corresponding to an output voltage characteristic of a TTL-circuit, and a buffer circuit with such an arrangement that a bipolar transistor for receiving at the base a signal from the output terminal of said complementary MOS inverter and an n-channel MOSFET for receiving at the gate an input signal applied to the complementary MOS inverter connected in series between a high-potential applying point and a low-potential applying point, and an output signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof. Particularly the logic gates of this document are connectable to drive a Darlington pair instead of a single output bipolar transistor. It is, therefore, an object of the present invention to provide a signal output circuit capable of increasing an output switching speed. According to the present invention, there is provided a signal output circuit according to claim 1. Preferred embodiments are listed in the dependent claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram of a conventional signal output circuit; Fig. 2 is a circuit diagram of the first embodiment of the present invention; Fig. 3 is a circuit diagram of the second embodiment of the present invention; and Fig. 4 is a circuit diagram of the third embodiment of the present invention. The present invention will be described in detail hereinafter with reference to embodiments in conjunction with the accompanying drawings. Fig. 2 shows an arrangement of the first embodiment of a signal output circuit according to the present invention. Referring to Fig. 2, the source of a p-channel MOS transistor 12 is connected to a node 11 for receiving a power supply voltage VCC of 5 V. The drain of an n-channel MOS transistor 13 is connected to the drain of the MOS transistor 12. The source of the MOS transistor 13 is connected to a node 14 for receiving a power supply voltage VSS of 0 V. The gates of the MOS transistors 12 and 13 are commonly connected to an input terminal 15, and the MOS transistors 12 and 13 constitute a CMOS inverter 16. The bases of a pnp bipolar transistor 18 and an npn bipolar transistor 19 are connected to an output node 17 which is a common connection point of the drains of the MOS transistors 12 and 13 in the inverter 16. The collector of one bipolar transistor 18 is connected to the node 14, and one terminal of a resistor 20 for setting a base current is connected to the emitter of the transistor 18. The base of an output pnp bipolar transistor 21 is connected to the other terminal of the resistor 20. The emitter of the bipolar transistor 21 is connected to the node 11, and the collector of the transistor 21 is connected to an output terminal 22. The collector of the other bipolar transistor 19 is connected to the node 11, and one terminal of a resistor 23 for setting a base current is connected to the emitter of the transistor 19. The base of an output npn bipolar transistor 24 is connected to the other terminal of the resistor 23. The collector and emitter of the bipolar transistor 24 are respectively connected to the output terminal 22 and the node 14. The source of a p-channel MOS transistor 25 for absorbing a base charge of the bipolar transistor 21 is connected to the node 11 of the power supply voltage VCC. The drain and gate of the MOS transistor 25 are respectively connected to the base of the bipolar transistor 21 and the input terminal 15. The source of an n-channel MOS transistor 26 for absorbing a base charge of the bipolar transistor 24 is connected to the node 14 of the power supply voltage VSS. The drain and gate of the MOS transistor 26 are respectively connected to the base of the bipolar transistor 24 and the input terminal 15. In the signal output circuit having the above-described arrangement, when the signal at the input terminal 15 is "H" level, the n-channel MOS transistor 13 in the inverter 16 is in an ON state, and the output node 17 of the transistor 13 is "L" level. At this time, the pnp bipolar transistor 18 is in an ON state, and the base current is flowed into the output pnp bipolar transistor 21 through the resistor 20 and the transistor 18. As a result, the bipolar transistor 21 is turned on and the output terminal 22 is charged with the power supply voltage VCC to be "H" level. In this state, when the signal at the input terminal 15 is inverted into "L" level, the p-channel MOS transistor 12 in the inverter 16 is turned on, and the output node 17 is charged with the power supply voltage VCC to be "H" level. At this time, the pnp bipolar transistor 18 is turned off, and the npn bipolar transistor 19 is turned on. Since the base current is flowed into the output npn bipolar transistor 24 through the transistor 19 and the resistor 23, the bipolar transistor 24 is turned on, and the output terminal 22 is discharged to the power supply voltage VSS. As a result, the signal at the output terminal 22 is inverted from "H" level to "L" level. In addition, after the bipolar transistor 18 is turned off and supply of the base current into the transistor 21 is stopped, the input signal changes from "H" level to "L" level, and the p-channel MOS transistor 25 is in an ON state. As a result, supply of the base current is stopped, and the charge accumulated at the base of the bipolar transistor 21 to be turned off is absorbed by the node 11 of the power supply voltage VCC through the MOS transistor 25. Therefore, the bipolar transistor 21 is abruptly turned off. When the signal at the input terminal 15 is inverted again into "H" level, the n-channel MOS transistor 13 in the inverter 16 is turned on, the bipolar transistor 18 is turned on, and the bipolar transistor 21 is turned on. As a result, the signal at the output terminal 22 becomes "H" level as described above. In this case, after the bipolar transistor 19 is turned off and supply of the base current to the transistor 24 is stopped, the charge accumulated at the base of the bipolar transistor 24 to be turned off is absorbed by the node 14 of the power supply voltage VSS through the n-channel MOS transistor 26 in an ON state. As a result, the bipolar transistor 24 is abruptly turned off. In the above-described embodiment, in a case that a 2-mA output current is to be obtained from the output terminal 22 when the high-potential power supply voltage VCC is 5 V as in the conventional circuit, a resistance R of the resistors 20 and 23 is determined by the following equation, assuming that current amplification factors hfe (Q21) and hfe (Q24) of the bipolar transistors 21 and 24 are respectively 5, wherein Vf in the following equation is a base-emitter voltage of the npn or pnp bipolar transistor. R = VCC - 2Vf output current hfe Q21 = 5 - 1.4 2 × 10 -3 5 = 9 KΩ That is, the resistance of the resistors 20 and 23 becomes as low as 1/100 that in the conventional circuit, so that charge and discharge operations of parasitic capacitors of the bases of the bipolar transistors 21 and 24 can be performed at a higher speed than that in the conventional circuit. As a result, switching speeds of the output bipolar transistors 21 and 24 are increased, resulting in an increase in output switching speed. In addition, in the above-described embodiment, the excess base charges of the output transistors 21 and 24 are absorbed by the MOS transistors 25 and 26. For this reason, when one of the output transistors 21 and 24 is in an ON state, one of the base charge absorbing MOS transistors 25 and 26 in an ON state is turned off, so that a wasteful current is not flowed upon turn-on operation of the output transistor, unlike in the conventional circuit. As a result, the base current can be larger than that in the conventional circuit. Therefore, the turn-on speed of the output transistor is increased, thereby increasing the output switching speed. The second embodiment of the present invention will be described with reference to Fig. 3. In this circuit, two input terminals 15A and 15B are arranged. A two-input NAND gate 27 constituted by two p-channel MOS transistors 12A and 12B and two n-channel MOS transistors 13A and 13B is arranged in place of the CMOS inverter 16 in the first embodiment shown in Fig. 2. More specifically, the sources of the p-channel MOS transistors 12A and 12B are commonly connected to a node 11 of a power supply voltage VCC, and the drains of the p-channel transistors 12A and 12B are commonly connected to an output node 28 of the NAND gate 27. The source-drain paths of the n-channel MOS transistors 13A and 13B are connected in series between a node 14 of a power supply voltage VSS and the output node 28. The gates of one p-channel MOS transistor 12A and one n-channel MOS transistor 13A are connected to one input terminal 15A, and the gates of the other p-channel MOS transistor 12B and the other n-channel MOS transistor 13B are connected to the other input terminal 15B. In this embodiment, since the two-input NAND gate 27 is arranged in place of the inverter 16, the source-drain paths of two p-channel MOS transistors 25A and 25B are connected in parallel between the node 11 of the power supply voltage VCC and the base of a pnp bipolar transistor 21, and the source-drain paths of two n-channel MOS transistors 26A and 26B are connected in series between the node 14 of the power supply voltage VSS and the base of an npn bipolar transistor 24. The gates of the MOS transistors 25A and 26A are commonly connected to one input terminal 15A, and the gates of the MOS transistors 25B and 26B are commonly connected to the other input terminal 15B. In the signal output circuit with this arrangement, a signal of a level corresponding to signals supplied to the input terminals 15A and 15B is obtained from an output terminal 22. More specifically, when two input signals are "H" level, the output node 28 of the NAND gate 27 becomes "L" level, bipolar transistors 18 and 21 are respectively turned on, and an "H" level signal is output from the output terminal 22. When one of the two input signals is "L" level, the output node 28 of the NAND gate 27 becomes "H" level, bipolar transistors 19 and 24 are turned on, and a signal of "L" level is output from the output terminal 22. In this embodiment, with the arrangement of the bipolar transistors 18 and 19, the resistances of resistors 20 and 23 can be greatly decreased as compared with the conventional circuit, resulting in an increase in output switching speed. The third embodiment of the present invention will be described with reference to Fig. 4. This circuit has two input terminals 15A and 15B as in the second embodiment, and a two-input NOR gate 29 constituted by two p-channel MOS transistors 12A and 12B and two n-channel MOS transistors 13A and 13B is arranged in place of the CMOS inverter 16 shown in Fig. 2. More specifically, the source-drain paths of the p-channel MOS transistors 12A and 12B are connected in series between a node 11 of a power supply voltage VCC and an output node 30 of the NOR gate 29. The sources of the n-channel MOS transistors 13A and 13B are commonly connected to a node 14 of a power supply voltage VSS, and the drains of the n-channel MOS transistors 13A and 13B are commonly connected to the output node 30. The gates of one p-channel MOS transistor 12A and one n-channel MOS transistor 13A are connected to one input terminal 15A. The gates of the other p-channel MOS transistor 12B and the other n-channel MOS transistor 13B are connected to the other input terminal 15B. In this embodiment, since the two-input NOR gate 29 is arranged in place of the inverter 16, the source-drain paths of two p-channel MOS transistors 25A and 25B are connected in series between the node 11 of the power supply voltage VCC and the base of a pnp bipolar transistor 21. The source-drain paths of two n-channel MOS transistors 26A and 26B are connected in parallel between the node 14 of the power supply voltage VSS and an npn bipolar transistor 24. The gates of the MOS transistors 25A and 26A are commonly connected to one input terminal 15A and the gates of the MOS transistors 25B and 26B are commonly connected to the other input terminal 15B. In the signal output circuit with this arrangement, a signal of a level corresponding to signals supplied to the input terminals 15A and 15B is obtained from an output terminal 22. More specifically, when the two input signals are "L" level, the signal at the output node 30 in the NOR gate 29 becomes "H" level, bipolar transistors 19 and 24 are turned on, and a signal of "L" level is output from the output terminal 22. When one of the two input signals is "H" level, a signal of the output node 30 of the NOR gate 29 becomes "L" level, bipolar transistors 18 and 21 are turned on, and a signal of "H" level is output from the output terminal 22. In this embodiment, by the bipolar transistors 18 and 19, the resistances of resistors 20 and 23 can be greatly decreased as compared with the conventional circuit, and the output switching speed can be increased. As has been described above, according to the present invention, a resistance of a resistor for setting a base current of an output transistor can be greatly decreased as compared with the conventional circuit, so that the parasitic capacitor can be charged upon switching at a relatively high speed. In addition, the excess base charge of the output transistor is absorbed by a MOS transistor, so that a higher switching speed upon turn-off operation of the output transistor can be obtained. Therefore, according to a signal output circuit of the present invention, high input/output transfer characteristics can be obtained. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A signal output circuit comprising: at least one input terminal (15;15A,15B); an output terminal (22); first and second nodes (11,14) for respectively receiving power supply voltages having different values (V cc ,V ss ); a CMOS logic gate (16;27;29) for receiving a signal from said input terminal and for generating an output on an output node (17;28;30) in response to the signal from said input terminal (15,15A,15B); a first bipolar transistor (18) of a first polarity having a base for receiving the output from said CMOS logic gate (16;27;29); a second bipolar transistor (19) of a second polarity having a base for receiving the output from said CMOS logic gate (16;27;29); a first resistor (20) having one terminal connected to the emitter of said first bipolar transistor (18); a second resistor (23) having one terminal connected to the emitter of said second bipolar transistor (19); a third bipolar transistor (21) of the first polarity having an emitter connected to said first node (11), a collector connected to said output terminal (22), and a base connected to the other terminal of said first resistor (20); a fourth bipolar transistor (24) of the second polarity having an emitter connected to said second node (14), a collector connected to said output terminal (22), and a base connected to the other terminal of said second resistor (23); at least one first MOS transistor (25;25A,25B) of the first polarity, a source-drain path of which is connected between said first node (11) and the base of said third bipolar transistor (21), and a gate of which receives the signal from said input terminal (15;15A,15B); and at least one second MOS transistor (26;26A,26B) of the second polarity, a source-drain path of which is connected between said second node (14) and the base of said fourth bipolar transistor (24), and a gate of which receives the signal from said input terminal (15;15A,15B). A circuit according to claim 1, characterized in that said CMOS logic gate is a CMOS inverter (16). A circuit according to claim 1, characterized in that said CMOS logic gate is a CMOS NAND gate (27). A circuit according to claim 1, characterized in that said CMOS logic gate is a CMOS NOR gate (29). A circuit according to claim 1, characterized in that said CMOS logic gate is a CMOS inverter, a source-drain path of one of said at least one first MOS transistor (25) is connected between said first node (11) and the base of said third bipolar transistor (21), and the source-drain path of one of said at least one second MOS transistor (26) is connected between said second node (14) and the base of said fourth bipolar transistor (24). A circuit according to claim 1, characterized in that said CMOS logic gate is a CMOS NAND gate, source-drain paths of two of said at least one first MOS transistor (25A,25B) are connected in parallel between said first node (11) and the base of said third bipolar transistor (21), and source-drain paths of two of said at least one second MOS transistor (26A,26B) are connected in series between said second node (14) and the base of said fourth bipolar transistor (24). A circuit according to claim 1, characterized in that said CMOS logic gate is a CMOS NOR gate, source-drain paths of two of said at least one first MOS transistor (25A,25B) are connected in series between said first node (11) and the base of said third bipolar transistor (21), and source-drain paths of two of said at least one second MOS transistor (26A,26B) are connected in parallel between said second node (14) and the base of said fourth bipolar transistor (24).

Inventors: KOYA KIICHI, KOYA, KIICHI, KOYA, KIICHI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: H03K19
IPC codes: H03K19, H01L21, H01L27, H01L29