Decimation-interpolation circuits

Abstract: An apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device, the analog-digital-analog conversion device converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-­ digital-analog device. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation. Certain of the specified set of modules participate in both the decimation and interpolation operations. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation or to increase the iterations of interpolation, or to increase the iterations of both decimation and interpolation.

Description: The present invention is directed to a communications interface apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device. Specifically, in its preferred embodiment, the apparatus is used in effecting communications between a voice-band device, such as a telephone, and a data processing device. The apparatus receives digital signals from an analog-digital-analog conversion device, decimates those incoming digital signal to produce decimated incoming digital signals representative of the received incoming digital signals. The decimated incoming digital signals are recognizable by the data processing device. The apparatus also receives outgoing digital signals from the data processing device, interpolates those outgoing digital signals to produce an interpolated digital signal which is converted to an outgoing analog signal representative of the outgoing digital signal by an analog-digital-analog conversion device. The outgoing analog signal is recognizable by the analog device. IEEE Journal of Sold-State Circuits - Vol. SC-20, No. 3, June 1985, New York, USA, pages 679 - 687, Defraeye, et al, "A 3-µm CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting" describes a known apparatus which utilises a decimator comprising decimation filters and a separate interpolator comprising interpolation filters. The decimator performs decimation in three steps and the interpolator performs interpolation in two steps. Proceedings ICASSP, 1987 International Conference on Acoustics, Speech and Signal Processing April 1987, Dallas, Texas, pages 900 - 903, Hansen "Design of a multistage decimation-interpolation filter" describes a multi-stage decimation-interpolation filter which can either interpolate or decimate. The described digital filter is implemented by a cascade of decimation filters followed by a cascade of interpolation filters. IEE Proceedings PT. G. vol. 130, No. 6, December 1983, pages 225 - 235, Valenzuela et al "Digital signal processing schemes for efficient interpolation and decimation" discloses a structure for sampling rate alteration. The document discloses two structures, an interpolating structure and decimating structure, each employing N sub-filters to achieve an N-fold increase or reduction of the input sampling rate. In the manufacturing of such known apparatus, it is common that separate duplicate components be utilized for the decimation of incoming digital signals and for the interpolation of outgoing digital signals. Often there is duplication of components between the decimation circuitry and the interpolation circuitry. Such use of duplicate components results in several disadvantages. For example, in integrated circuit embodiments, the cost increase occasioned by such component duplication is not significant. However, such duplicate components require additional trimming during manufacture in order that gains, accuracy, and offsets and biases are balanced within the device. Another disadvantage is that the use of duplicate components necessarily requires that a greater chip area be occupied. Thus, the smallness of a chip implementation of such a device is inherently limited by the necessity to duplicate components to effect the two functions required, decimation and interpolation. The present invention is designed to overcome some of the shortcomings of duplicate-component interface apparata. We describe an apparatus adaptable for use with an analog-digital analog conversion device for effecting communications between an analog device and a digital device, having a digital signal processing circuit for decimating incoming digital signals received from the analog-digital conversion, and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal for digital-analog conversion. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation. Certain of the specified set of modules participate in both the decimation and interpolation operations. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation or to increase the iterations of interpolation, or to increase the iterations of both decimation and interpolation. Accordingly, there is described an apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device which is configured to share components for decimation functions as well as for interpolation functions. The apparatus is adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device, the manufacture of which may be accomplished with economies of component trimming and chip area. The apparatus is further adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device which is inexpensive to construct. In the accompanying drawings, by way of example only:- Fig. 1 is a schematic block diagram of a system embodying the present invention, Fig. 2 is an electrical schematic diagram of the decimation-interpolation circuit of Fig. 1, Fig. 3 is a space-time domain matrix representation of the decimation-interpolation circuit of Fig. 2 for implementation of the decimation transfer function, Fig. 4 is a space-time domain matrix representation of the decimation-interpolation circuit of fig. 2 for implementation of the interpolation transfer function, Fig. 5 is a schematic block diagram illustrating the modular design of the preferred embodiment of the present invention. In Fig. 1, an analog device 12, such as a telephone voice instrument, is connected to an analog-digital-analog circuit 14. Typically, the analog device 12 operates in the audio frequency range, approximately 300 Hz to 3.4 KHz. The analog-digital-analog circuit 14 samples the incoming analog signal which is conveyed from the analog device 12 via line 16. The sample rate of the analog-digital-analog circuit 14 is, in the preferred embodiment, approximately 2 MHz. Some advantages are incurred by the high frequency sampling by the analog-digital-analog circuit 14: for example, a higher frequency of operation allows for closer spacing of components in the invention when the invention is configured as an integrated circuit, i.e., a silicon chip construction; and the high frequency sampling allows for a more accurate digital representation of the incoming analog signal. The analog-digital-analog circuit 14 converts the incoming analog signal received on line 16 to an incoming digital signal and conveys that incoming digital signal to a decimation-interpolation circuit 18 via line 20. The decimation-interpolation circuit 18 receives the incoming digital signal on line 20, performs a decimation operation upon that signal, and outputs a decimated incoming digital signal on line 22. In the preferred embodiment, the incoming decimated digital signal is produced at a frequency of approximately 16 KHz, a frequency which still allows for obtaining the advantages of high frequency close spacing of components in a silicon chip structure and high resolution of the digital representation of the incoming analog signal. The incoming decimated digital signal is presented to the digital device 24 via line 22. The digital device 24 is, commonly, a device such as a data processing device or a computerized communications switching apparatus. The digital device 24 provides outgoing digital signals to the decimation-interpolation circuit 18 via line 26. The decimation-interpolation circuit 18 performs an interpolation operation upon the outgoing digital signals received on line 26 and outputs interpolated digital signals via line 28 to the analog-digital-analog circuit 14. The analog-digital-analog circuit 14 receives the interpolated digital signals on line 28, converts those interpolated digital signals to outgoing analog signals, and provides the outgoing analog signals to the analog device 12 via line 30. An electrical schematic diagram of the preferred embodiment of the present invention is presented in Fig. 2. For purposes of clarity in describing the preferred embodiment of the present invention, like elements will be labelled with like reference numerals throughout this description. In Fig. 2, an analog-digital-analog circuit 14 receives incoming analog signals on line 16 from an analog device (not shown in Fig. 2) and outputs outgoing digital signals on line 30. Further, the analog-digital-analog circuit 14 conveys incoming digital signals to a decimation-interpolation circuit 18 via lines 20a and 20b and receives interpolated digital signals from the decimation-interpolation circuit 18 via line 28. The decimation-interpolation circuit 18 is preferably comprised of digital input circuit 66, first digital cell circuit 68, second digital cell circuit 70, second digital cell circuit 72, and output circuit 92. The first digital cell circuit 68 is preferably comprised of a shift register R0 receiving an input from multiplexer 74 and providing an output to a one bit adder SA1, a multiplexer 96, and a shift register R1B. The output of the programmable logic array 78 is applied to shift register R1B via line 100. The output of multiplexer 96 is applied to a shift register R1A. The output of shift register R1A is applied to a multiplexer 104 as well as fed back to the multiplexer 96. Also applied to the multiplexer 104 is the output of shift register R1B. The output of multiplexer 104 is applied to multiplexer 84 as well as to one bit adder SA1. The output of multiplexer 84, which is also the output of first digital cell circuit 68, is applied to one bit adder SA2 of second digital cell circuit 70 as well as to shift register R0. Second digital cell circuit 70 further comprises a multiplexer 106 which also receives the output of multiplexer 84. The output of shift register R2 is applied to multiplexer 108 as well as fed back to multiplexer 106 and applied to one bit adder SA2. Also provided to multiplexer 108 is the output of one bit adder SA2. The output of multiplexer 108, which is also the output of second digital cell circuit 70, is applied to one bit adder SA3 and multiplexer 110 of second digital cell circuit 72. Further in second digital cell circuit 72, the output of one bit adder SA3 is applied to multiplexer 112 and the output of multiplexer 110 is applied to shift register R3. The output of shift register R3 is applied to multiplexer 112, to one bit adder SA3, and to multiplexer 110. The output of multiplexer 112, which is also the output of second digital cell circuit 72, is applied to output circuit 92. Specifically, the output of multiplexer 112 is applied to scaling subcircuit 114 which applies a scaled output to shift register R4. The output of shift register R4 is provided via multiplexer 94 to input bus 24a via line 22. The decimation-interpolation circuit 18 conveys decimated incoming digital signals to the input bus 24a of a digital device (only the input bus 24a and the output bus 24b of the digital device 24 are illustrated in Fig. 2) via line 22. The decimation-interpolation circuit 18 receives outgoing digital signals from the digital device output bus 24b via line 26, and conveys interpolated digital signals, as previously described, to the analog-digital-analog circuit 14 via line 28. The analog-digital-analog circuit 14 conveys outgoing analog signals to an analog device (not shown in Fig. 2) via line 30. The analog-digital-analog circuit 14, as illustrated in Fig. 2, includes counter 44 and digital-to-analog converter circuit 46. The decimation-interpolation circuit 18, when it receives an incoming digital signal from the analog-digital-analog circuit 14 via lines 20a and 20b, decimates the incoming digital signal in a manner to be described in greater detail below. Further, when the decimation-interpolation circuit 18 receives an outgoing digital signal from digital input bus 24b, it interpolates the outgoing digital signal to produce an interpolated digital signal and provide that interpolated digital signal to the analog-digital-analog circuit 14 via line 28, as will also be described in greater detail below. The digital input circuit 66 is preferably comprised of a multiplexer 74, a shift register 76, and a programmable logic array 78. When the analog-digital-analog circuit 14 provides an incoming digital signal on lines 20a and 20b, the decimation-interpolation circuit 18 is appropriately clocked to decimate incoming digital signals from the analog-digital-analog circuit 14. Thus, each succeeding digital pulse from the analog-digital-analog circuit 14 is applied to the digital input circuit 66 at two points. The current count output of the analog-digital-analog circuit 14 is applied via line 20a to the multiplexer 74, and the shift register 76 receives and stores a history of the pulse signals which appear on line 20b. The structure of the digital input circuit 66 is particularly adapted to the step-wise up and down signalling characteristic of the output of a first order integrator, which is employed in the preferred embodiment of the analog-digital-analog circuit 14 wherein steps up and down are of a predetermined amount for each clock cycle. Such a structure saves hardware and saves having the decimation-interpolation circuit operate at high speed. For purposes of illustration, the preferred embodiment of the present invention illustrated in Fig. 2 accomplishes a decimation by a factor of 16 implemented in a four stage structure which implements the following transfer function: 1/256 (1+z -1 ) 2 (1+z -2 ) 2 (1+z -4 ) 2 (1+z -8 ) 2 =H D (z) For example, for a sampling rate by the analog-digital-analog circuit 14 of 2.048 MHz, the decimator output would be 128 KHz. For purposes of this illustrative example, it is assumed that the analog-digital-analog circuit 14 employs a 6-bit digital-analog converter and a sigma-delta modulator of a first order type. Of course, the present invention can be used for larger digital analog converters and for higher order sigma-delta modulators. The architecture of the decimation-interpolation circuit 18 requires that the transfer function of Equation (1) be partitioned so that the second digital cell circuit 72 is preceded by all other sections of the decimation-interpolation circuit 18 (i.e., digital input circuit 66, first digital cell circuit 68 and second digital cell circuit 70) to form a transfer function: H D (z) : 1/256 [H 1D (z) * H 2D (z)] where H 2D (z) is implemented in the first digital cell circuit 70 and the second digital cell circuit 72, i.e., (1+z -8 ) 2 in Equation (1). The factor 1/256 is a scaling factor. Therefore, transforming Equation (1) into Equation (2) yields: H D (z) = 1/256 [(1+z -1 ) 2 (1+z -2 ) 2 (1+z -4 ) 2 ](1+z -8 ) 2 The term within the brackets [ ] of Equation (3) may be expanded to produce the following: H D (z) = 1/256 [1+2z -1 + 3z -2 + 4z -3 + 5z -4 + 6z -5 + 7z -6 + 8z -7 + 7z -8 + 6z -9 + 5z -10 + 4z -11 + 3z -12 + 2z -13 + z -14 ] And: H 2D (z) = (1 + 2z -8 + z -16 ] The annotation z -m indicates the value of z, m time periods past. By this partitioning method, H 1D (z) may be implemented in the programmable logic array 78 and the first digital cell circuit 68 and H 2D (z) may be implemented in the second digital cell circuit 70 and the second digital cell circuit 72. The time-domain implementation of Equation (4) is: y 1 (n)=x(n) + 2x(n-1) + 3x(n-2) + ... + x(n-14) Since the sigma-delta modulator employs a first order scheme, the difference, defined as d i , between successive counter values can only be ±1, i.e., x(n-1), can only differ from x(n) by ±1, x(n-2) can only differ from x(n-1) by ±1, and so on. Therefore the time-domain implementation of Equation (6) can be expressed as: y 1 (n) = x(n) + 2[x(n) - d 1 ] + 3(x(n) - d 2 - d 3 ] + ... + [x(n) - d 1 - d 2 - ... - d 14 ] where d i =±1, for i=1, 2, ..., 14. Expanding Equation 7 yields: y 1 (n) = 64x(n) - 63d 1 - 61d 2 - 58d 3 - 54d 4 - 49d 5 - 43d 6 - 36d 7 - 28d 8 - 21d 9 - 15d 10 - 10d 11 - 6d 12 - 3d 13 - d 14 The factors d i are representative of the successive outputs D i of analog-digital circuit 14 which also controls the incrementing or decrementing of the counter 44. The outputs D i are successively shifted in shift register 76 and are used as an address to the programmable logic array 78. The address is D 14 ... D 1 and comprises a succession of 1's and 0's, "1" meaning count up (d i =+1) and "0" meaning count down (d i =-1) By substituting all of the possible combinations of d 14 , ... d 1 , (i.e., 2 13 combinations) where d i =+1 or -1 for i=1, ..., 14 into Equation (8), one could determine the contents of the programmable logic array 78. For example, for the address: D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Successive outputs for the analog-digital-analog circuit 14 are all 0, which forces the counter 44 to decrement. Substituting d 14 , ... d 1 = -1 in Equation (8) yields: y 1 (n) = 64x(n) + 448 Thus, for the preferred embodiment illustrated in Fig. 2, the programmable logic array 78, with an input address of 0 ... 0, would yield an output value of +448. This result indicates that y 1 (n) is the sum of x(n), the present sample (provided to the shift register R0 via multiplexer 74), plus the sum of all the previous 14 samples. It is preferred that the output of the digital input circuit 66 be divided by 8. Consequently, every 8 clocks of the shift register 76, which holds the programmable logic array 78 address, is followed by a load of the counter 44 into shift register R0 via the multiplexer 74, with six zeroes added to the least significant end of the analog-digital-analog circuit 14 output to produce 64 times x(n) (the first term of Equation (8)). The remaining terms of Equation (8) are calculated by the programmable logic array 78 and are loaded into register R1B at the same instant in time as shift register R0 is loaded. The terms of Equation (8) are added using the bit serial adder SA1 in the first digital cell circuit 68 to determine the value of H 1D (z). The time-domain implementation of H 2D (z) is: y 2 (n) = y 1 (n) + 2y 1 (n-1) + y 1 (n-2) In the time domain, H 1D (z) is an input used in calculating H 2D (z) Thus, effectively, the time-domain output y 2 (n) is the time-domain result of the total transfer function H D (z). The second digital cell circuits 70, 72 produce another decimation of ÷2 to give an overall reduction in sampling rate of 16. The next successive expression of H 2D (z) is: y 2 (n+1) = y 1 (n+2) + 2y 1 (n+1) + y 1 (n) A comparison of Equations (10) and (11) clearly illustrates that successive samples (i.e., input values to H 2D (z)) are shifted up by two places each clock cycle to produce the decimation by a factor of ÷2. The first digital cell circuit 68, the second digital cell circuit 70, and the second digital cell circuit 72 implement the H D (z) transfer function as illustrated in Fig. 3. Referring to Fig. 3, columnar divisions of a matrix are delineated T 0 , T 1 , T 2 , ... to indicate successive time periods, each period being eight clock pulses in duration. Row divisions are representative of the various registers R0, R1A, R1B, R2, R3, and R4 and their associated serial adders SA1, SA2, and SA3 within the decimation-interpolation circuit 18. Accordingly, each box in the matrix of Fig. 3 represents the function(s) performed by a specific register and serial adder during a specific time period. As illustrated in Fig. 3, during the time period T 0 -T 1 , the quantity 64x(n) is loaded into register R0. Also, first digital cell circuit 68, second digital cell circuit 70, and second digital cell circuit 72 are triggered; the output of the programmable logic array 78 is loaded into register R1B and the contents of register R0 and register R1B are added to yield the quantity y 1 (n). Further during the time period T 0 -T 1 , the quantity y 1 (n) is added with the contents of register R2 by one bit adder SA2 to yield the quantity y 1 (n) + 2y 1 (n-1), using a scaling function provided by appropriate timing. Still within the time period T 0 -T 1 , the quantity y 1 (n) + 2y 1 (n-1) is shifted to second digital cell circuit 72 and combined with the then-residing contents of register R3 using one bit adder SA3 to yield the result y 1 (n) + 2y 1 (n-1) + y 1 (n-2). The quantity y 1 (n) remains in register R2. Finally, within the period T 0 -T 1 , the quantity y 1 (n) + 2y 1 (n-1) + y 1 (n-2) is shifted into register R4 in the output circuit 92 in scaled format, i.e., ÷256. During the second eight clock pulse period, T 1 -T 2 , the quantity 64x(n) is again loaded into register R0, first digital cell circuit 68 is triggered and its output is loaded into register R2, and the contents of register R2 are loaded into register R3. The programmable logic array 78 contents are loaded into register R1B and the quantity y 1 (n+1) is calculated by serial bit adder SA1, combining the contents of register R0 and register R1B. Thus, register R2 now contains y 1 (n+1) and register R3 now contains y 1 (n). During the third eight clock pulse period, T 2 -T 3 , the first digital cell circuit 68, the second digital cell circuit 70, and the second digital cell circuit 72 are triggered and the output of the programmable logic array 78 is combined with the 64x(n) information concurrently loaded into register R0 to produce the quantity y 1 (n+2). Serial adder SA2 computes the quantity y 1 (n+2) + 2y 1 (n+1) and retains the quantity y 1 (n+2) in storage. Serial adder SA3 calculates the quantity y 1 (n+2) + 2y 1 (n+1) + y 1 (n). The output of serial adder SA3 is then loaded into register R4 and the output which was previously loaded into register R4 during time period T 0 -T 1 is transferred to input bus 24a via line 22. Thus, during the time period T 0 -T 1 , a first value of H 2D (z) in the form of Equation (10) was loaded into register R4, i.e., y 1 (n) + 2y 1 (n-1) + y 1 (n-2). During the time period T 2 -T 3 , there is loaded into register R4 the next successive expression of H 2D (z) in the form of Equation (11), i.e., y 1 (n+2) + 2y 1 (n+1) + y 1 (n), and the first value of H 2D (z) is clocked through the multiplexer 94 of output circuit 92 to input bus 24a via line 22. The decimation-interpolation circuit 18 is also configurable, by appropriate clocking control, to interpolate digital signals received from output bus 24b. Interpolation is preferably effected using a four stage structure having a transfer function of the form: 1/256 (1+z -1 ) 2 (1+z -2 ) 2 (1+z -4 ) 2 (1+z -8 ) 2 = H I (z) Equation (12) can be realized as four cascaded blocks of the form H jI (z) where: H I (z) = [H 1I (z) * H 2I (z) * H 3I (z) * H 4I (z)] where H 1I (z) = 1/4 (1 + 2z -1 + z -2 ), H 2I (z) = 1/4(1 + 2z -2 + z -4 ), etc. for each of the terms in Equation (12). For example, with a sampling rate of 16 KHz at the input of multiplexer 74, the output frequency of the interpolated digital signal is 256 KHz (i.e., x 16). When interpolating by a factor of 2, using the transfer function of Equation (13), zeroes are inserted into the time-domain implementation between successive samples so that the output is at twice the input rate. The time-domain implementation of this interpolation is represented by: y I (n) = 1/4 [x(n) + 2x(n-1) + x(n-2)] where the alternate samples are zeroes so that the samples x(n-2), x(n-1), x(n) become: x(n-2), 0, x(n-1), 0, x(n), 0, x(n+1) The four stage interpolator is therefore implemented as: Thus, by way of illustration, in the first (I 1 ) stage, I 10 (n-1) equals: I 10 (n-1) = 1/2 [x(n-1) + 0 + x(n-2)] and: I 11 (n-1) = 1/2 [0 + 2x(n-1) + 0] The scaling factor has been adjusted to one-half to compensate for the inserted zeroes. Interpolation factor implementation functions hereinafter will, for the sake of clarity, be designated in the form: I abbbb... (n), where "a" indicates the interpolator stage involved (a = 1, 2, 3, 4), and "bbbb..." indicates successive interpolation factors. Thus, through the zero-insertion operation described above, each interpolator stage (I 1 I 2 , I 3 , I 4 ) generates two time-domain implementations for each input. Interpolator stage I 4 , therefore, will generate sixteen time-domain interpolation factors. For example, interpolator stage I 1 will generate: I 10 (n) = 1/2 [x(n) + x(n-1)]; and I 11 (n) = 1/2 [2x(n)] Thus, for one stage of the interpolator where, for example, sample x(n) arrives, the block I 1 outputs twice before x(n+1) arrives where the two outputs are of the form of Equations (18) and (19). The entire interpolation chain can then be generated for one input sample x(n) to produce 16 output samples, as illustrated below: The decimation-interpolation circuit 18 effects interpolation as illustrated in Fig. 4. Prior to the arrival of a sample x(n), the previous sample x(n-1) resides in shift registers R1A, R1B, R2, and R3. This situation occurs directly as a result of the computational scheme and, following the generation of 16 outputs from one input sample x(n), the sample x(n) will be held in shift registers R1A, R1B, R2, and R3. This situation simplifies the structure of decimation-interpolation circuit 18 because, as may be ascertained by inspection, I 11 (n-1) = x(n-1) and is required to compute I 10 (n). Similarly, I 200 (n) requires I 11 (n-1), for computation; and I 3000 (n) requires I 211 (n-1), i.e., I 11 (n-1); and I 4000 (n) requires I 3111 (n-1), i.e., I 211 (n-1), i.e., I 11 (n-1) Referring to Fig. 4, columnar divisions of the matrix are delineated at the top of the matrix in time periods 1-16 and 1, indicating the first clock pulse in the next cycle. Each period is one clock pulse in duration. Row divisions are representative of the various registers R0, R1A, R1B, R2, R3, and R4 with associated serial adders SA1, SA2, and SA3 within the decimation-interpolation circuit 18. Accordingly, each box in the matrix of Fig. 4 represents the function(s) performed by a specific register and serial adder during a specific time period. Referring to Fig. 4, during period 1, sample x(n) is loaded in register R0 from output bus 24b via line 26 and multiplexer 74, the contents of register R1A (sample x(n-1)) and the contents of register R0 (sample x(n)) are added in serial adder SA1 and the result of that summation, which is I 10 , is shifted into register R0. x(n), which is I 11 , is written back into register R1A. Thus, there resides at this point in time within register R1A the sample x(n), which is also interpolation factor I 11 (n). The "one-half" factor required to compute certain of the interpolation factors (such as, I 10 (n), I 200 (n), and so on) is provided by clocking control. That is, when a "one-half" factor is required for an interpolation factor calculation, the elements of that calculation are combined as required and stored in a register. Then the elements are shifted one place to the right (i.e., ÷2) prior to completion of the calculation of that respective interpolation factor. In such manner, the least significant adder output bit is lost and the second least significant output bit becomes the least significant output bit, i.e., ÷2. There is a symmetry about Fig. 4 which, however, does not extend to the operation of adder SA1. There is a pipelining of computations to ensure that the next required computation to be performed by adder SA1 occurs in period 2. This results in the first interpolation factor (I 40000 ) actually being shifted into register R4 during period 2. If adder SA1 were employed during period 1 to perform the calculations necessary to produce I 40000 during period 1, then adder SA1 would need to operate at a frequency greater than 10 MHz. By pipelining calculations, as illustrated in Fig. 4, the last interpolation factor (I 41111 (n-1)) for the previous cycle, which requires no calculations be performed by adder SA1, is shifted into register R4 during period 1. Thus, adder SA1 may be operated at the same speed as adders SA2 and SA3, preferably yielding an interpolator output period of approximately 3.9 µ sec. Continuing in Fig. 4, during time period 2, the register R1B contents (I 11 (n-1)) are added with the contents of register R0 (I 10 ), appropriately scaled, to calculate interpolation factor I 200 , and I 200 is shifted to register R2. Further during time period 2, the contents of register R2 (I 211 (n-1) = I 11 (n-1)) are combined with I 200 by adder SA2 to to produce I 3000 and that result is shifted to register R3. Adder SA3 combines I 3000 with the contents of register R3 (I 3111 (n-1) = I 11 (n-1) which has remained in register R3 since the previous calculation cycle) to calculate I 40000 , and I 40000 is shifted to register R4 during period 2. During period 2, I 10 /I 201 is rewritten into register R1B, I 200 /I 3001 is rewritten into register R2, and I 3000 /I 40001 is rewritten into register R3. During time period 3 in Fig. 4, register R1A continues to store sample x(n) (also I 11 ), register R1B is storing I 10 /I 201 , register R2 is storing I 200 /I 3001 , register R3 writes I 40001 (which is also I 3000 ) into register R4, and I 3000 /I 40001 is rewritten into register R3. During time period 4 in Fig. 4, register R1A continues to retain I 11 in storage. Adder SA3 combines I 3001 from register R2 with I 3000 from register R3 to calculate I 40010 , with appropriate scaling by right-shifting as previously described. I 3001 /I 40011 , is rewritten into register R3 and I 200 is rewritten into register R2. During time period 5 in Fig. 4, register R1A continues to store I 11 , register R3 shifts I 3001 /I 40011 to register R4, and I 3001 is rewritten into register R3. During the sixth time period illustrated in Fig. 4, interpolation factor I 10 /I 201 is shifted to shift register R0 in order that the factor I 10 will be available for subsequent computation of I 210 (later, in time period 10). Further, in time period 6, the then-contents of register R2 (I 200 ) are combined with the output of first digital cell circuit 68 (I 201 clocked from shift register R1B) by adder SA2 to produce I 3010 . I 3010 is combined by serial adder SA3 with the then-contents of register R3 (I 3001 /I 40011 ) to yield I 40010 . I 3011 /I 201 is rewritten to register R2 and I 3010 /I 40101 is rewritten to register R3. During time period 7, I 40101 is written from register R3 into register R4, and is also rewritten to register R3. In time period 8, serial adder SA3 combines I 3011 from register R2 with the then-existing contents of register R3 (I 3010 ) to produce I 40110 . Also during period 8, I 201 /I 3011 is rewritten to register R2, I 3011 /I 40111 is rewritten to register R3, and I 40110 is written to register R4. In time period 9, I 40111 is written into register R4 and is rewritten into register R3 for later use. In time period 10, the contents of register R0 (I 10 ), written into register R0 during time period 6, are combined by adder SA1 with the contents of register R1A (I 11 ) to produce I 210 which is, in turn, combined by adder SA2 with the then-contents of register R2 (I 201 ) to produce I 3100 . I 11 is rewritten to register R1A. I 3100 is combined by adder SA3 with the then-contents of register R3 (I 3011 ) to produce I 41000 , and I 41000 is written to register R4. Also during period 10, I 3100 /I 41001 is rewritten to register R3, and I 210 /I 3101 is rewritten to register R2. During period 11, I 11 is written from register R1A to register R0 and also rewritten to register R1A. Also during period 11, I 41001 is written to register 4 and I 3100 /I 41001 is rewritten into register R3. In time period 12, the contents of register R0 (I 11 ) are written to register R1B for further use during the next pass. Adder SA3 combines I 3101 with the then-contents of register R3 (I 3100 ) to produce I 41010 . Also during period 12, I 210 /I 3101 is rewritten to register R2, I 3101 /I 41011 is rewritten to register R3, and I 41010 is written to register R4. During period 13, I 41011 , is written to register R4; and I 3101 /I 41011 , is rewritten to register R3. During period 14, adder SA2 receives I 11 /I 211 from register R1A and combines I 211 with the then-contents of register R2 (I 210 ) to produce I 3110 . Adder SA3 receives I 3110 from register R2 and combines I 3110 with the then-existing contents of register R3 (I 3101 ) to produce I 41100 and writes I 41100 to register R4. Also during period 14, I 11 is rewritten to register R1A, I 211 /I 3111 is rewritten to register R2, and I 3110 /I 41101 is rewritten to register R3. During time period 15, I 41101 is written into register R4; and I 3110 /I 41101 is rewritten into register R3. During period 16, adder SA3 receives I 211 /I 3111 , from register R2 and combines I 211 /I 3111 with the then-contents of register R3 (I 3110 ) to produce I 41110 and writes I 41110 to register R4. Also during period 16, I 211 /I 3111 is rewritten to register R2, and I 3111 /I 41111 is rewritten to register R3. During time period 1 of the next (x(n+1)) cycle, I 41111 is written to register R4 and I 3111 /I 41111 is rewritten into register R3. At the same time, register R0 receives the next sample, x(n+1), for interpolation. Consequently, registers R1A, R1B, R2, and R3 all now contain x(n) available for computations during the next pass when sample x (n+1) is interpolated in the subsequent cycle. Further, the sixteen interpolation samples have been generated from the one original sample x(n) and have been passed to register R4 from which they may be clocked through multiplexer 94 via line 28 to analog-digital-analog device 14 for conversion to an outgoing analog signal as previously described. Referring to Fig. 5, a schematic block diagram illustrating the modular design of the preferred embodiment of the present invention is presented. In Fig. 5, an analog device 12 sends incoming analog signals via a line 16 to an analog-digital circuit 14. The analog-digital-analog circuit 14 passes incoming digital signals to a decimation-interpolation circuit 18 via line 20. The decimation-interpolation circuit 18 is comprised of decimator-interpolator module 19. Additional decimator-interpolator modules may be added to effect further decimation or interpolation as desired; such additional optional decimator-interpolator modules are represented in Fig. 5 by the dotted-line representation for decimator-interpolator module 19a. The decimator-interpolator module 19 is comprised of a digital input circuit 66, a first digital cell circuit 68, and second digital cell circuits 70, 72, 73. Second digital cell circuits within a given decimator-interpolator module 19 may be added to effect greater degrees of decimation or interpolation as desired, as indicated by second digital cell circuits 72 and 73. Additional decimator-interpolator modules 19a necessarily will contain second digital cell circuits 70a and 72a; the number of second digital cell circuits 70a, 72a need not be identical among the various decimator-interpolator modules 19, 19a. The last of the second digital cell circuits 73 in the decimator-interpolator module 19 provides input to second digital cell circuit 70a of a subsequent decimator-interpolator module 19a. The last second digital cell circuit 72a of the last decimator-interpolator module 19a provides outputs to output circuit 92 from which decimated incoming digital signals are passed via line 22 to digital device 24 and interpolated digital signals are passed to analog-digital-analog circuit 14 via line 28. It is to be understood that, while the detailed drawings and specific examples given describe preferred embodiments of the invention, they are for the purpose of illustration only, that the apparatus of the invention is not limited to the precise details and conditions disclosed, and that various changes may be made therein without departing from the scope of the invention which is defined by the following claims.

Claims: An apparatus for use with an analog-digital-analog conversion device (14) for effecting communications between an analog device (12) and a digital device (24), the apparatus comprising a digital signal processor means including: a decimator-interpolator means (18) for decimating incoming digital signals provided by said analog-digital-analog conversion device (14) and providing decimated incoming digital signals representative of said incoming signals to said digital device (24), and for interpolating outgoing digital signals received from said digital device and providing interpolated digital signals to said analog-digital-analog conversion device (14); said decimator-interpolator means (18) comprising: a module including a digital input circuit (66), a first digital cell circuit (68), and at least one second digital cell circuit (70,72,73); the decimator-interpolator means further including an output means (92) for providing digital outputs, said at least one second digital cell circuit (70,72,73) being arranged serially whereby each of said at least one second digital cell circuit after a first (70) of said at least one second digital cell circuit receives as its respective input the output of the preceding one of said at least one second digital cell circuit; said digital input circuit (66) selectively receiving said incoming digital signal from said analog-digital-analog conversion device (14) and producing an incoming clocked input to said first digital cell circuit (68), or receiving said outgoing digital signal from said digital device (24) and producing an outgoing clocked input to said first digital cell circuit (68); said first digital cell circuit (68) selectively producing a first iteration decimated digital signal to said at least one second digital cell circuit in response to reception of said incoming clocked digital signal, or producing a first iteration interpolated digital signal to said at least one second digital cell circuit in response to reception of said outgoing clocked input; said first (70) of said at least one second digital cell circuit selectively producing a second iteration decimated digital signal in response to reception of said first iteration decimated digital signal, or producing a second iteration interpolated digital signal in response to reception of said first iteration interpolated digital signal; the last (73) of said at least one second digital cell circuit being connected to provide its respective output to said output means (92); said output means (92) selectively providing said interpolated digital signal to said analog-digital-analog conversion device (14) or providing said decimated incoming digital signal to said digital device (24). An apparatus as claimed in claim 1, wherein said digital input circuit (66) includes a shift register or programmable logic means for producing said incoming clocked input. An apparatus as claimed in claim 1 or claim 2, wherein said decimator-interpolator means further comprises at least one second decimator-interpolator module (19a); each of said at least one second decimator-interpolator modules comprising at least one secondary digital cell circuit (70a,72a); said at least one second decimator-interpolator modules (19a) being arranged serially whereby a first of said at least one second decimator-interpolator modules receives as its input said outputs of said first decimator-interpolator module (19), and each of said at least one second decimator-interpolator modules after said first of said at least one second decimator-interpolator modules receives as its respective input the output of the next preceding of said at least one second decimator-interpolator modules; the products of the last of said at least one second decimator-interpolator modules being connected to said output means (92). An apparatus as claimed in claim 3, wherein said at least one secondary digital cell circuit (70a,72a) is substantially the same as said at least one second digital cell circuit. An apparatus as claimed in any preceding claim, wherein said at least one second digital cell circuit (70,72,73) is two second digital cell circuits. An apparatus as claimed in any preceding claim, wherein additional modules of said plurality of modules (19,19a) may be added to said specified set to selectively increase said iterations of said decimation or to increase said iterations of said interpolation. An apparatus as claimed in claim 6, wherein addition of said additional modules may increase both said iterations of said decimation and said iterations of said interpolation.

Inventors: ASGHAR SAFDAR M, BARTKOWIAK JOHN G, ASGHAR, SAFDAR M., BARTKOWIAK, JOHN G.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1990
Main classification: G06F3
IPC codes: H03H17, H03M1, H04B14, G06F3