Integrated circuit comprising a signal level converter

Abstract: An integrated circuit comprises a converter for converting a logic input signal of a first logic type into a logic output signal of a second logic type, for example from ECL to CMOS level. The converter comprises a buffer (10), including a controllable load (14) and a driver transistor (12), and a control circuit (20). In dependence on a control voltage and a reference voltage (V REF ) externally applied, the load (14) is controlled so that the output signal (V OUT ) is substantially equal to the reference voltage (V REF ) if the input signal (V IN ) is substantially equal to the control voltage. The load (14) and the driver transistor (12) in the buffer are controllable in a mutually opposed manner, a capacitance (25) being inserted between the control terminal of the load and the input terminal (16) of the driver so as to pass the AC effect of signal transitions to the load, thus speeding up the transition at the buffer. In one embodiment the control circuit (20) comprises a copy (30) of the buffer (10), which copy (30) receives the control voltage on its input, its load being controlled by a differential amplifier (40) whose inputs receive the reference voltage (V REF ) and the output voltage of the copy. A CMOS-SRAM comprising ECL/CMOS level converters of the above kind communicates with fast ECL circuits and has a low energy consumption.

Description: The invention relates to an integrated circuit, comprising a converter for transforming, under the control of a control voltage, an input signal with an input signal voltage with a first and a second extreme value on an input terminal into an output signal with an output signal voltage with a third and a fourth extreme value on an output terminal comprising: a buffer which comprises a current path which includes a current channel of a driver transistor which is connected to a first power supply terminal, and a controllable load which is connected to a second power supply terminal, the input terminal being coupled to a control electrode of the driver transistor, the output terminal being coupled to the current path between the load and the driver transistor; a control circuit for controlling the load under the control of both the control voltage and a reference voltage so that the output signal voltage is substantially equal to the reference voltage if the input signal voltage is substantially equal to the control voltage. STATE OF THE ART Such an integrated circuit is known from world patent application WO 89/00362 "CMOS input buffer receiver circuit". On the basis of the mutually independent control voltage and the reference voltage the control circuit adjusts the load in order to ensure that the trip point of the buffer is fixed. The switching components comprise only the buffer with a load and a driver transistor. An disadvantage of such a circuit is that there will be a delay between the arrival of signal transitions at the input and their corresponding appearance at the output that in view of the tendency of ever increasing clock frequencies considerably limits the application of the known circuit. OBJECT OF THE INVENTION It is, inter alia, the object of the invention to reduce the delay between transitions in the input and output. DESCRIPTION OF THE INVENTION To this end, the integrated circuit of the kind set fourth is characterized in that the load and the driver transistor in the first buffer are controllable in a mutually opposed manner, a capacitance being inserted between the control terminal of the load and the input terminal. Because of the capacitive coupling between the input terminal and the control terminal, the load is actively controlled in the case of input voltage transistors. Because the driver transistor and the load can be controlled in a mutually opposed manner, the voltage on the output terminal will respond more quickly than in the absence of the capacitive coupling. A further embodiment of an integrated circuit in accordance with the invention wherein the control circuit comprises: a second buffer which comprises a current path which includes a current channel of a second driver transistor which is connected to the first power supply terminal and a controllable second load which is connected to the second power supply terminal, the second driver transistor being controllable by the control voltage; a differential amplifier for controlling the first and the second load in dependence on a difference between the reference voltage and an output voltage of the second buffer, is characterized in that a resistance is arranged between the control terminal and the differential amplifier. The resistance ensures inter alia that a voltage variation at the control terminal does not disappear directly into the power supply via the low output impedance of the differential amplifier. Moreover, the combination formed by the capacitance and the resistance enhances the stability of the feedback loop by way of phase compensation. Embodiments in which at least the control voltage or the reference voltage can be controlled find a wide field of application. For example, one and the same integrated circuit in accordance with the invention, constructed in CMOS technology, will be suitable for converting logic signals of at least one of the following types: ECL level, TTL level, S-TTL level, I²L level, to the CMOS level by adaptation of the control voltage and the reference voltage. A further embodiment of an integrated circuit in accordance with the invention is characterized in that it comprises a CMOS SRAM, a CMOS converter being connected to an input thereof. When the converter is suitable, for example, for converting ECL signals to the CMOS level, a SRAM is realized which is capable of cooperating directly with (fast) ECL circuits and which has a low energy consumption and a high packing density in accordance with the properties of CMOS circuits. A combination of, for example, a CMOS gate array and such converters offers similar advantages. FIGURES The invention will be described in detail hereinafter with reference to a drawing; therein Fig. 1a shows a circuit in accordance with the prior art, Fig. 1b. shows a variation of Figure 1a. Fig. 2 shows an embodiment of an integrated circuit in accordance with the invention, Fig. 3 shows a transistor diagram illustrating the embodiment of Fig. 2, and Fig. 4 shows an example of a memory circuit in accordance with the invention. FIRST EMBODIMENT Fig. 1a shows an embodiment of an integrated circuit in accordance the prior art. The circuit comprises an inverter circuit 10 with a driver transistor 12 of the NMOS type and a load transistor 14 of the PMOS type. Input 16 of the inverter circuit 10 receives an input signal V IN , the signal voltage of which lies between two predetermined values, for example V A and V B . For example, if V IN is a logic signal at the ECL level, V A and V B are equal to 0.95 V below V DD and 1.7 V below V DD , respectively. Output signal V OUT at output terminal 18 is indicative of the instantaneous value of the input signal V IN , but represents a version thereof which has been translated to the CMOS level. For optimum conversion of the input signal V IN to the output signal V OUT it is inter alia necessary for V OUT to be situated approximately halfway between V DD and V SS when the input signal V IN lies approximately halfway between V A and V B . To this end, the circuit is provided with a control circuit 20 which controls the current through the load transistor 14 in dependence on the control voltage V C at control input 22. The control circuit 20 comprises a second inverter circuit 30 with a driver transistor 32 and a load transistor 34 which are of the NMOS type and the PMOS type, respectively, the load transistor 34 being controlled by means of a negative feedback loop. The feedback loop comprises a differential amplifier 40, a non-inverting input of which is connected to an output 38 of the second inverter circuit 30 , an inverting input being connected to a voltage divider 50 in order to receive a reference voltage V REF , an output of said amplifier 40 being connected to the interconnected gate electrodes of the load transistors 14 and 34. For a given control voltage V C and a given reference voltage V REF , the differential amplifier 40 controls the current through the load transistor 34 so that the voltage on the output 38 is substantially equal to V REF . The load transistor 14 receives the same control voltage as the load transistor 34. Assume that the construction of the inverter circuits 10 and 30 is identical, possibly except for a geometrical scale factor. In that case the output voltage V OUT of the inverter circuit 10 will be substantially equal to the reference voltage V REF if the input voltage V IN is substantially equal to the control voltage V C . For example, when the control voltage V C is adjusted to a value approximately 1.32 V below V DD , an input buffer for ECL signals to the CMOS level has been realized. Fig. 1b shows a variation of the known integrated memory circuit in which the supply voltages V DD and V SS and the PMOS and NMOS transistors have been interchanged. A driver transistor 212 in the first inverter circuit 10 is now of the PMOS type and receives the input voltage V IN at input terminal 216. In the second inverter circuit 30 a PMOS transistor 234 receives a control voltage V C via control terminal 222. NMOS load transistors 214 and 234 are controlled by the fed back differential amplifier 40. As has already been described with reference to Fig. 1a, the output voltage V OUT at the output terminal 218 will again be substantially equal to the reference voltage V REF if the input voltage V IN is substantially equal to the control voltage V C . This embodiment is to be preferred over the embodiment shown in Fig. 1a if the lowest extreme value of the signal voltage V IN is below the threshold of the NMOS transistor 12 of Fig. 1a. If this still would be the case, at least distortions of the output signal V OUT would occur and possibly also a loss of information. Similar considerations hold good mutatis mutandis for the embodiment shown in Fig. 1b if the highest extreme value of the signal voltage V IN is within the voltage range between V DD minus a threshold of the driver transistor 212 and V DD . For example, when a logic TTL having logic values of 0.2 V above V SS and 2.5 V above V SS is chosen for V IN and V C is adjusted to a value 1.35 V above V SS , an input buffer for TTL signals to the CMOS level has been realized. Inter alia depending on the technology in which the integrated circuit can be constructed (CMOS, NMOS, bipolar, MESFET, etc.), the foregoing can in principle be used for conversion of signals of different logic families (CMOS, TTL, S-TTL, ECL, I²L, etc.). Similarly, the foregoing can also be used for realizing comparators having a small offset. SECOND CIRCUIT DIAGRAM Fig. 2 shows a second circuit diagram of an integrated circuit in accordance with the invention which is again constructed, by way of example, in CMOS technology as in the previous Figure. References which correspond to those of the previous Figure refer to identical or corresponding parts and components. The circuit shown in Fig. 2 deviates from that shown in Fig. 1a in that a capacitance 25 is added between the gate electrodes of the driver transistor 12 and the load transistor 14 in the inverter circuit 10 and in that a resistance 27 is added between the gate electrode of the load transistor 14 and the output of the differential amplifier 40 . The capacitive coupling between the gate electrodes of the transistors 12 and 14 provides active control of the load transistor 14 during the transition of the voltage level of the input signal V IN at the input 16. Therefore, this embodiment is faster than that shown in the preceding Figure. The resistance 27 is provided inter alia in order to prevent the voltage variations at the gate electrode of the load transistor from disappearing immediately into the power supply via the (very low) output impedance of the differential amplifier 40. The resistance 27 has no effect on the d.c. biasing of the load transistor 14 for as long as the control voltage V C remains constant. The combination formed by the capacitance 25 and the resistance 27 also acts as a phase compensation in the previously mentioned feedback loop in order to prevent the occurrence of instabilities. Such instabilities could otherwise cause a serious problem because the feedback loop contains elements that have a phase shifting effect. The feedback is tapped between the output of the amplifier and the gates of the transistors that are used as controllable load. These gates form a capacitive load, that, in combination with the output resistance of the amplifier gives rise to phase shift. It is also to be noted that the gate delay of the circuits shown is shorter than the gate delay of a conventional CMOS inverter circuit if in the circuits of the Figs. 1a and 2 V C is larger than 1 2 (V DD - V SS ) and V C is smaller than 1 2 (V DD - V SS ) in the circuit shown in Fig. 1b. This is inter alia because of the mutually independent bias of the driver transistor 12 and the load transistor 14, which bias enables the sum of the gate-source voltages, in as far as DC components are concerned, to be considerably larger than in the case of a conventional CMOS inverter circuit. This implies a greater transconductance for the circuit in comparison with the conventional CMOS gate composed of the same transistors. TRANSISTOR DIAGRAM Fig. 3 shows a transistor diagram as an example of the implementation of the circuit shown in Fig. 2. References which correspond to the preceding Figures again refer to identical or corresponding parts. The differential amplifier 40 now comprises a transistor differential pair 42 with a current mirror 44 as a load. One input of the differential amplifier 40 is connected to the output of the inverter circuit 30 , the other input being connected to a voltage divider 50 which comprises a standard CMOS inverter gate whose input and output are interconnected. An impedance 27 comprises a parallel combination of current channels of a PMOS transistor and an NMOS transistor whose gate electrodes are connected to the power supply terminals for connection to V SS and V DD , respectively. As is known, the use of this parallel combination prevents the occurrence of threshold losses. An additional inverter circuit 60 for increasing the voltage swing at the output of the circuit may also be connected to the output 18 of the inverter circuit 10 . A gate delay of 0.6 ns and a power consumption of 1.1 mA have been determined experimentally for a circuit as shown in the transistor diagram, realized in a sub-micron CMOS process, for conversion from ECL to CMOS level with a power supply (V DD - V SS ) of 4.5 V ± 5% and for a temperature range of from 0°C to 125°C. MEMORY CIRCUIT Fig. 4 shows an example of a use of an integrated circuit in accordance with the invention. There are shown an IC 100 with power supply terminals 102 and 104 for connection to ECL level supply voltages of 0 V and -4.5 V, respectively. The IC 100 comprises a CMOS-SRAM 110 which is connected between the terminals 102 and 104. For the communication, and hence for level adaptation of the signals, there are provided an input buffer 120 and an output buffer 130 for converting ECL level signals to the CMOS level and for converting CMOS level signals to the ECL level, respectively. The IC 100 may also be provided with data processing circuits (not shown) which operate at the ECL level as denoted by arrows in broken lines which indicate a feasible data transport route. Such a set-up combines the low energy consumption of a CMOS-SRAM and the high data processing speed of ECL systems, the IC 100 being fully ECL compatible. The input buffer 120 comprises, for example the circuit shown in Fig. 3.

Claims: An integrated circuit for transforming an input signal (V IN ), having an input signal voltage with first and second extreme values at an input terminal (16), into an output signal (V OUT ), having an output signal voltage with third and fourth extreme values at an output terminal (18), under control of a control voltage (V C ), the circuit comprising a first buffer (10) with a current path that includes: a current channel of a first driver transistor (12) connected to a first power supply terminal (V SS ), the input terminal being DC coupled to a control electrode of the driver transistor; a controllable first load (14) connected to a second power supply terminal (V DD ), the output terminal being coupled to the path between the said first load and the said first driver transistor; the circuit further including a control circuit (20) for control of the said first load in dependence on the control voltage and a reference voltage (V REF ) so that in a steady-state the output signal voltage is substantially equal to the reference voltage when the input voltage is substantially equal to the control voltage, the control voltage lying between the first and second extreme values, and the reference voltage lying between the third and fourth extreme values; characterized in that the said first load and the said first driver transistor are controllable in a complementary manner, the control terminal of the said first load and the input terminal being AC coupled through a capacitance (25). The circuit of Claim 1, wherein the control circuit comprises: a second buffer (30) that comprises a current path including a current channel of a second driver transistor (32) being connected to the first power supply terminal and being controllable by the control voltage, and a controllable second load (34) connected to the second power supply terminal; a differential amplifier (40) to control the first and second load in dependence on a difference between the reference voltage an output voltage of the second buffer; characterized in that a resistor (27) is connected between the control terminal and the differential amplifier. An integrated circuit as claimed in Claim 2, characterized in that the second driver transistor (32) and the second load (34) are copies of the first driver transistor (12) and the first load, respectively. An integrated circuit as claimed in Claim 3, characterized in that the second buffer (30) is a copy of the first buffer (10). An integrated circuit as claimed in Claim 1, in which at least the control voltage (V C ) or the reference voltage (V REF ) is controllable. An integrated circuit as claimed in Claim 1, 2, 3, or 4, comprising several converters having a single control circuit in common. An integrated circuit as claimed in Claim 1, 2, 3, 4, 5 or 6, constructed in CMOS technology and suitable for converting logic input signals of at least one of the following types: ECL level, TTL level, S-TTL level, I²L level, to the CMOS level. An integrated circuit as claimed in Claim 7, comprising a CMOS-SRAM (110) which is coupled to at least one converter (120) at the input side. An integrated circuit as claimed in Claim 7, comprising a CMOS gate array which is coupled to at least one converter at the input side. An integrated circuit as claimed in Claim 1, 2, 3, 4 or 5, which is suitable for use as a comparator.

Inventors: DIKKEN JAN, SCHUHMACHER HANS-JUERGEN OTTO, SEEVINCK EVERT, DIKKEN, JAN, SCHUHMACHER, HANS-JUERGEN OTTO, SEEVINCK, EVERT, Schuhmacher, Hans-Jürgen Otto
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: H03K19
IPC codes: H03K5, H03K19, G11C11