Method of receiving program down-loaded to IC card and IC card thereof

Abstract: There is provided an IC card (1) comprising a memory (6) within the IC card for storing therein a program operating on a processor (4) included in the IC card and a ROM storing therein a system program (5) for down-loading the program onto the IC card. When a different program is present in the program storage area and a program to be down-loaded into the IC card is to be relocated to a space area, the destination address field of a jump instruction included in the program is altered by a processor (4) included in the IC card.

Description: BACKGROUND OF THE INVENTION The present invention relates to an IC card, and in particular to an IC card having such a structure that a program can be flexibly loaded from the outside onto a storage area. Such IC cards that an operation program stored in an internal memory of each IC card is run on an internal processor and predetermined processing is executed can be classified into two kinds. In one of the two kinds, a nonrewritable memory such as a mask ROM (read only memory) is used as the internal memory. In the other of the two kinds, a writable memory such as a RAM (random access memory) backed up by a battery or an EEPROM (electrically erasable programmable read only memory) is used as the internal memory. The latter cards gradually tend to be widely used because the user can freely set contents of the operation program afterwards. In accordance with invention disclosed in JP-A-63-6690, information relating to a value of final address of a region of a memory, in which a program down-loaded into an IC card by using a program of a control section of the IC card is stored, is stored into a system region of a data memory of the card, and (a plurality of) programs are downloaded to the card to be made executable on the basis of the abovedescribed information. An identifier for identifying programs from each other is assigned to each of the downloaded programs. Further downloading of a program having the same identifier is not allowed. For realising the download, it is necessary to specify a program identifier included in the IC card and execute a command for clearing a program. When this scheme is used and a program to be downloaded has an absolute address form, i.e. an address of a memory region of an IC card is directly indicated, therefore, the program producing apparatus must store therein the leading address of a memory within the card in which the program is stored, resulting in complicated program development. Further, when a program already downloaded must be modified or expanded, it is necessary to delete that program or it is necessary to download a new program after an identifier has been deleted or address information has been rewritten. EP-A-0 218 176 discloses an IC card in accordance with the prior art portion of claim 1 and which generally operates as discussed in relation to JP-A-63 6690. Thus an object met by the present invention is to eliminate the drawback that when a program already down-loaded must be modified or expanded, it is necessary to delete that program or to delete an identifier and rewrite address information and thereafter newly down-load a program, and to thereby provide an IC card facilitating partial modification of a program. A further object met by the present invention is to provide an IC card system, which allows selecting one out of two kinds of schemes, i.e., the relative address specification and absolute address specification at the time of down-loading, which, in case of relative address scheme, obviates the necessity of storing the program storage address and performing address management at the time of producing a down-load program, which, in case of absolute addressing, automatically corrects surplus and deficiency of memory capacity caused between the modified down-load program and the down-load program already written into the internal memory, which thus obviates the fear of overwriting a program on the already existing program included in the IC card and thereby destroying the program, and which raises the memory utilization efficiency by using the memory so that undesired space areas may be filled. In accordance with configuration of an IC card of the present invention as defined in claim 1 for achieving the above described objects, an internal processor of an IC card, in which an operation program is stored in an internal memory and predetermined processing is executed by the internal processor of the IC card on the basis of the above described operation program, has function of receiving a program from the outside of the IC card and storing the program thus received into the internal memory and function of checking, when a command specifying the storage address within the internal memory has been received, whether the required program or data is already present in the storage area or not, and of altering and relocating, in case the required program or data is already present, that program so as to meet space areas. When a program or data is not present in a region having the leading address and succeeding addresses, the operation program is stored in the specified address and succeeding addresses. When a command which does not specify the storage address of the internal memory is transmitted to the IC card, this internal processor searches a space area and stores that program therein. Further, in accordance with the configuration of an IC card of the present invention for achieving the above described objects, an internal processor of the IC card, in which an operation program is stored in the internal memory and predetermined processing is executed by the internal processor on the basis of the above described operation program, has function of receiving an operation program from the outside of the IC card and of storing the program into the internal memory at an address which is not accompanied by a specified storage address and which is specified by the internal processor. The IC card has a feature that the internal processor converts the absolute address written into the program to an address corresponding to the address specified by the internal processor. In this way, it is possible to place writing the operation program from the outside under the control of the internal processor and handle an instruction written in the absolute address form as if the program is written in the relative address form by adding an offset address to the absolute address in the internal processor. In case of later adjustment of a part of a program already loaded, for example, it is possible to modify that program by supplying an address from the outside and by handling the program as if the program is written in the absolute address form as in the prior art. If the number of steps of the program increases as a result of the later adjustment, succeeding programs are moved backward by the amount of the increase to perform relocation, and the destination address field of an instruction written in the absolute address form is corrected by adding, in the internal processor, the offset of the movement to the address. In this way, it is possible to handle an operation program, which is produced in the absolute address form, when down-loading the operation program from an external apparatus without being conscious of the absolute address of the IC card memory or without being shackled by it. Further, in case a program already loaded is to be partly modified, only the required portion of the program is rewritten by means of absolute addresses and, if necessary, succeeding programs are relocated by the internal processor. Therefore, the development efficiency of the program down-loaded from the outside onto the IC card is raised. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an IC card and an external apparatus of an embodiment of the present invention; Fig. 2 is a flow chart showing the processing of a system program for down-loading a program onto the IC card; Figs. 3A and 3B are memory map diagrams for describing in detail a scheme (step 5 of flow chart of Fig. 2) whereby a program is relocated and stored at the time of down-loading; Fig. 4 is a diagram for describing instruction conversion performed within the relocated program; Fig. 5 is a flow chart showing processing of a system program for down-loading a program onto an IC card according to another embodiment of the present invention; Figs. 6A to 6C are diagrams for describing examples of a command train including a loader start command and a down-load program; Figs. 7A to 7C are diagrams for describing in detail a scheme whereby programs are relocated and stored at the time of down-loading; and Figs. 8A and 8B are diagrams for describing an example of the memory map in case memory relocation is performed by address correction. DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will hereafter be described in detail by referring to drawings. Fig. 1 is a block diagram showing flow of a program and data transferred between an IC card of an embodiment according to the present invention and a work station. An IC card 1 is connected to a work station or an external apparatus 8 via a connector 2 and a card reader/writer 9. Input/output signals are transmitted from or received by a CPU 4 via an input/output interface 3. Basic function of the CPU 4 is controlled by a system program (loader) 5 written into an internal ROM. This system program implements I/O function with respect to the external apparatus 8, function of gaining access to an internal memory 6, and function of administering the arrangement of operation programs within the internal memory 6 by referring to an internal memory administration table 7. Operation of this IC card will now be described. Fig. 2 is a flow chart showing the processing of the system program 5 for down-loading an object program, which is used for operation of the IC card. When the system program 5 is started, it first checks whether there is a space area for storing a program or not in the internal memory 6 included in the IC card 1. This check is performed by checking the internal memory administration table 7 stored in a part of the internal memory 6 (step 1). Divided storage of a relative address program makes address computation complicated. It is desirable that down-loading is performed only when a down-loaded program can be accommodated into a very large storage area, and otherwise a response that there is no space is transmitted to the work station or apparatus. When there is a space, a response indicating that there is a space is transmitted to the external apparatus 8, and reception of a program to be down-loaded is waited (step 2). The destination address field of a jump instruction included in the down-loaded program is converted into a value with an offset address added by the CPU 4 so that this program may become operable when it is stored into a space area of the internal memory 6 included in the IC card 1. The converted value is stored at the top of the space area (step 5). A response indicating that down-loading has been finished is transmitted from the IC card 1 to the external apparatus 8 (step 6). If there is not a space of required amount in the area at step 1, a response indicating that there is no space is transmitted to the external apparatus 8, and the processing is finished (step 3). A scheme for relocating and storing a program at the time of down-loading (step 5 in the flow chart of Fig. 2) will now be described in detail by referring to Figs. 3 and 4. Fig. 3B shows down-load processing whereby the system program 5, which is the resident program of the IC card 1, inputs an object program 13 from the outside and stores the object program into a storage memory 11. The leading address of a space area 12 within the memory 11 obtained before the object program 13 is down-loaded is ADR N as shown in Fig. 3A. Further, it is now assumed that the leading address of the program obtained when the program 13 is produced by the external apparatus 13 is ADR G. When executing down-loading, the system program 5 adds an offset or difference (ADR N) - (ADR G) obtained between the leading address ADR G of the inputted program 13 and the leading address ADR N of the space area 12 of the memory 11 to each of the operand address or absolute address of conditional or unconditional JMP instructions, a GO TO instruction, a CALL instruction, and a BRANCH instruction included in the program 13 having a certain data length. The system program 5 thus generates a down-loaded program MM 14 and stores this into the space area 12 having the leading address ADR N and succeeding addresses. The value of a new leading address ADR Y stored in the system program is equal to (ADR N) + (data length). This conversion processing may be performed after the program 13 has been stored into the space area 12. Or the result of conversion performed in a different space area of the internal memory 6 may be stored into the space area 12. In other words, order of conversion and storage is arbitrary. Fig. 4 shows a state 15 of a program to be down-loaded before down-loading and a state 16 of the program after down-loading by using a jump (JMP) instruction. With regard to the offset value with respect to the space area, absolute addresses ADDXX and ADDYY of jump destination or address operand of a JMP instruction selected in accordance with the predetermined bit pattern of the operation code out of the instruction sequence before down-loading are respectively converted into addresses (ADDXX + offset) and (ADDYY + offset) and stored. Another embodiment of the present invention will now be described by referring to Figs. 5 and 6A to 6C. The hardware configuration for implementing this embodiment will not be described here, because it is the same as the hardware configuration of the first embodiment. In this embodiment, the system program is started by a load start command which is supplied from the external apparatus 8 to make the system program of the IC card start down-loading and which is shown in Fig. 6A or 6B (step 10). The loader start command has a command class 101 and a data length 102 put between a master code 31 having a predetermined bit pattern and a step code 32. When the command class 101 of the loader start command has the format of Fig. 6B in which the relative address form is specified, the system program proceeds to step 12 (Fig. 5). When the absolute address form is specified, the system program proceeds to step 19 (step 11). If relative address specification is found at step 11, it is judged whether data can be stored into the program storage memory or not by comparing the data length 102 with the capacity of the space area (steps 12 and 13). In this judgment, the end address (YYYY) included in the directory as shown in Fig. 7A is subtracted from the last memory address held in the internal memory administration table. When the capacity of the space area thus found is equal to or larger than the data length, the program proceeds to step 14. When there is a space as a result of judgement, the program proceeds to step 14. When there is not a required amount of space, a response indicating that there is not a space is transmitted, and the program is finished (step 18). When there is a space, a response indicating that there is a space is transmitted (step 14). At step 15, a program is received by using a command train as shown in Fig. 6C. Programs are discriminated each other by using an appended peculiar number (104). At step 16, a received program is stored closely at the top of a space area of an area 106. with respect to the program after storage, a directory is produced within the administration table on the basis of the data length 102, a start address 103, the identifier 104 and information of the space area within the IC card system program as shown in Figs. 6A to 6C. As shown in Fig. 7B, the produced directory comprises an indentifier 129, a start address 130 and an end address 131. At step 17, a response indicating that down-loading has been finished is transmitted. When the command class 101 indicates absolute address specification at step 11, it is possible to further insert a step for checking whether the specified address is legal or not on the basis of the data length 102 and the start address 103 of Fig. 6A (step 19). When the destination address of the jump instruction is within a range from the start address to the sum of the data length and the start address and is legal, the program proceeds to step 12. When the destination address is not legal, the program proceeds to step 25 (step 20). At step 25, a response indicating that the destination address is not legal is transmitted as shown in Fig. 7C. A third embodiment of the present invention will now be described by referring to Figs. 8A and 8B. This embodiment also has the hardware configuration as shown in Fig. 1. When a program P N down-loaded onto a memory 201 is updated in the work station 8 and a program P N ′ having the number of steps changed is downloaded onto the same memory area, the following problem occurs. That is to say, in case the P N ′ is larger than the program P N , the program P N ′ cannot be stored into the area of the previous program P N . Further, in case the program P N ′ is smaller than the program P N , a space is incurred in the area of the previous program P N , resulting in a degraded memory efficiency. Although identifier P N = P N ′, the program before alteration and that after alteration are represented by the absence and presence of a dash, respectively. Therefore, a difference (offset) α between the end address (YYYY + α) of the program P N ′ and the end address YYYY of the program P N is derived. This α is added to all of operand addresses of JMP instructions of the program P N+1 following the program P N and succeeding programs, and the results are stored again (203). At the same time, a directory 202 for administering the area of the internal memory 6, in which the program P N is stored, is changed to a directory 204 so as to conform to the program P N ′. When programs are altered, it is thus possible to prevent other down-loaded programs from being destroyed and prevent the memory efficiency being lowered.

Claims: An IC card (1), an operation program being stored into an internal memory (6) of said IC card, predetermined processing being executed in an internal processor (4) of said IC card, said IC card comprising: (a) means (5) for storing an operation program received from the outside of the IC card by said internal processor into said internal memory at an address specified by said internal processor; and being characterised by (b) a memory management table provided in the internal memory for having start address information and length information for each program stored in said internal memory; (c) means (step (13) for judging by means of said start address and length information, upon a command to store a program of a relative address form in the internal memory, whether or not there is space area in the internal memory for storing therein the operation program; and (d) means (step 16) for adding, upon presence of the space area in the internal memory, the difference between the leading address of the space area within said internal memory and the leading address of the operation program to displacement of a jump instruction included in said operation program. An IC card according to claim 1, comprising means (step 16) for outputting, when said space area is smaller than said data length information, a response command containing a code indicating that there is insufficient space. An IC card according to claim 1 or 2, further comprising: means for detecting the fact that a program identifier appended to said operation program is the same as a program identifier within a directory used to administer programs included in said IC card; means for overwriting, in response to the output of said detecting means, said operation program on the storage region of said program included in said internal memory according to said same identifier; and means for relocating a program following said operation program to another space area after adding a difference between a leading address of said space area and a leading address of said another space area to displacement of a conditional jump instruction and an unconditional jump instruction of said operation program. An IC card according to claim 1, 2 or 3, wherein said internal processor comprises an internal ROM (6), in which a system program for downloading said operation program onto said IC card is stored. A method of downloading an operation program onto an internal memory (6) included in an IC card (1), predetermined processing being executed in an internal processor (4) on the basis of an operation program stored in said internal memory, said method comprising: receiving an operation program and a command to store said operation program in said internal memory; and characterised by preparing a memory management table in the internal memory for receiving start address information and length information for each of programs stored in said internal memory; judging by means of said start address and length information, upon receipt of a command to store a program of a relative address form in the internal memory, whether or not there is a space area in the internal memory for storing therein the operation program; and adding, upon presence of the space area in the internal memory, the difference between the loading address of the space area within said internal memory and the leading address of the operation program to displacement of a jump instruction included in said operation program. A method of according to claim 5, characterised by comprising the steps of: detecting the fact that a program identifier appended to said operation program is the same as a program identifier within a directory used to administer programs included in said IC card; overwriting, in response to the output of said detecting step, said operation program on the storage region of said program included in said internal memory according to said same identifier; and relocating a program following said operation program to another space area after adding the difference between the leading address of said space area and the leading address of said another space area to displacement of a conditional jump instruction and an unconditional jump instruction of said operation program.

Inventors: KODERA YUJI, KODERA, YUJI
Applicants: HITACHI MAXELL, HITACHI MAXELL, LTD.
Application year: 1990
Main classification: G07F7
IPC codes: G06K19, G07F7, G06F9