Sixteen-bit arithmetic logic unit

Abstract: For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable, pipeline , register ("A"), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and "delay" the parameter represented by the state of signals externally developed on a "DA" bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for "bit-reverse order" addressing; and a unit for "rounding off" certain results.

Description: BACKGROUND ART Prior art type microprocessors are less than ideally suited for certain kinds of applications. Consider, for example, some of the operations performed in calculating a discrete, fast Fourier transformation (FFT) of the type commonly used in spectrum analysis. In what is commonly referred to as a "butterfly" certain operations are performed (four multiplications usually performed in parallel) followed by four additions or subtractions (also usually performed in parallel) during a total of at least two clock cycles on a first parameter before the first parameter is combined with (added to or subtracted from) a second parameter. Fetching the two parameters from memory at different times is undesirable in that it is inconsistent with high speed operations and it requires additional logic. Holding the second parameter, such as by holding a clocking signal, is undesirable. This is because it is inconsistent with high speed operation, requires additional logic, and requires the use of multiple clocks. Also, to reduce the number of computations required, certain discrete, fast Fourier transformation operations require that certain parameters (samples) be addressed in what is commonly referred to as a "bit-reverse order". Further, the "rounding off" of certain results is required in order to maintain accuracy. For additional information on discrete, fast Fourier transformation operations, the reader is referred to the application note by Julie Lin and Danh Le Ngoc which is designated AN-XX High Performance Fixed Point Fast Fourier Transformation Processor (10-14-1988) by Integrated Device Technology, Inc. The prior art type device which is designated 7381 by Integrated Device Technology, Inc., L4C381 by Logic Devices, Inc., and S614381 by Gould, Inc., includes an "A" and a "B" input register, an "A" multiplexer configured with one set of multiplexer data inputs connected to the data inputs of the "A" register and with another set of multiplexer data inputs connected to the data outputs of the "A" register; a "B" multiplexer configured with one set of multiplexer data inputs connected to the data inputs of the "B" register and with another set of multiplexer data inputs connected to the data outputs of the "B" register; an "R" multiplexer, configured with one set of multiplexer data inputs connected to the data outputs of the "A" multiplexer, and an "S" multiplexer configured with one set of multiplexer data inputs connected to the data outputs of the "B" multiplexer. In addition, the device includes a 16-bit arithmetic logic unit configured with one set of unit data (operand) inputs connected to the data outputs of the "R" multiplexer and with another set of unit data (operand) inputs connected to the data outputs of the "S" multiplexer. Further, the device includes an "F" output register configured with the register data inputs connected to the data outputs of the arithmetic logic unit, an "F" multiplexer configured with one set of multiplexer data inputs connected to the data inputs of the "F" register and with another set of multiplexer data inputs connected to the data outputs of the "F" register, and a tri-state output driver unit configured with the unit data inputs connected to the data outputs of the "F" multiplexer. Unfortunately, the device lacks means for "delaying" a parameter, means for "bit-reverse order" addressing, and means for "rounding off" certain results. A prior art bit-slice micro-programmable processor is known from WO-A 82/03481. A set of registers A1-A3 and B1-B3 are interconnected with multiplexers, but the arrangement is not sufficient for eliminating multiple fetches of parameter data from memory at different times. A thirty-two bit-slice device with the same limitation is known from EP-A 0 261 048. The present invention improves on such prior art by arranging, for example, four registers and four associated registers at the data input of an ALU to programmably provide for single four-deep and dual two-deep pipelining with a single clock to avoid fetching multiple parameters from memory at different times. The invention, as defined in claim 1, solves the problem of fetching multiple parameters from the memory at different times. The present invention provides an arithmetic logic unit which employs means for temporarily "delaying" an input parameter. Furthermore, the arithmetic logic unit employs means for "bit-reverse order" addressing. Also means for "rounding off" certain results can be used. It is an advantage of the present invention to provide an arithmetic logic unit which is relatively fast. Briefly, the presently preferred embodiment of an arithmetic logic unit in accordance with the present invention includes a number of multiplexers and registers, which, in combination, form a configurable, pipeline , register ("A"), that functions as a four-deep pipeline register; as two, two-deep, pipeline registers; or as four separate registers, to latch the state of signals externally developed on a "DA" bus to "delay" the parameter they represent. In addition, the unit includes a "B" register for latching the state of signals externally developed on a "DB" bus; an "A" multiplexer for developing on an "R" bus signals representing either the "A" register signals, the "B" register signals, the "DA" bus signals, the "DB" bus signals, or signals developed on a "FB" bus; a "B" multiplexer for developing on an "S" bus signals representing either the "B" register signals, the "DA" bus signals, the "DB" bus signals, or signals developed on the "FB" bus; an "R" multiplexer; an "S" multiplexer; and an arithmetic logic unit coupled to the "R" and "S" busses by the "A" and "B" multiplexers. Further, the unit includes the combination of a funnel shifter, a merge logic unit, and a multiplexer, the combination being connected to the "R" and "S" busses. Finally, in an output portion, the unit includes four multiplexers; an "F1", an "F2", and an "ACC" register; a bit reversing unit; a rounding unit; a shifter; and a tri-state output driving unit. The first output portion multiplexer is configured to selectively couple signals developed either by the arithmetic logic unit or the funnel shifter/merge logic unit multiplexer to the output portion registers; and, the second output portion multiplexer is configured to selectively couple signals developed by the output portion registers or developed on a "YO" bus to the "FB" bus. The third output portion multiplexer is configured to selectively couple signals developed by the output portion registers "F1" or "F2" or the first output portion multiplexer to the bit reversing unit, the rounding unit, and the shifter; and, the fourth output portion multiplexer is configured to selectively couple signals developed by the bit reversing unit, the rounding unit, the shifter, or the third output portion multiplexer to the output driving unit, which develops signals on the "YO" bus. These and other objects of the present invention will no doubt become apparent to those skilled in the art after having read the detailed description of the presently preferred embodiment of the present invention which is illustrated in the figures of the drawing. BRIEF DESCRIPTION OF THE FIGURES IN THE DRAWING Fig. 1 is a block diagram illustrating the presently preferred embodiment of an arithmetic logic unit in accordance with the present invention; and Fig. 2 is a block diagram further illustrating the funnel shifter, which is shown in Fig. 1. BEST MODE FOR CARRYING OUT THE INVENTION Illustrated in Fig. 1 of the drawing generally designated by the number 100 is the presently preferred embodiment of an arithmetic logic unit (ALU) (system) in accordance with the present invention. Unit 100 is shown to include a number of multiplexers and registers, which, in combination, form a configurable, pipeline , register, that is generally designated 110. Register 110 has data inputs, which are connected to a 16-line "DA(0-15)" bus, that is designated 114. In addition, register 110 has clock inputs, which are connected to a "CP" (clock) line, that is designated 116. Further, register 110 has load-address (configuration) inputs, connected to a 3-line "LDA(0-2)" bus 120, and output-select (configuration) inputs, connected to a 4-line "RS(0-3)" bus 122. Finally, register 110 has data outputs, connected to a 16-line "R" bus 126. Responsive to the state of load-addressing signals externally developed on "LDA" bus 120 and the state of output-selecting signals externally developed on "RS" bus 122, register 110 functions as a four-deep pipeline register, as two, two-deep, pipe registers, or as four separate registers, to latch the state of signals externally developed on "DA" bus 114 to "delay" the parameter they represent. More specifically, register 110 includes four, similar, 16-bit, D-type, edge-triggered (flip-flop) registers, which are respectively designated 140, 142, 144, and 146, and four multiplexers, which are respectively designated 150, 152, 154, and 156. Registers 140, 142, 144, and 146 are each of the type which, at each of a series of times marked by a signal developed at the register clock input, latch the state of each of 16 signals each developed at the corresponding one of the 16 register data inputs and which develop at the 16 register data outputs signals each of which has a respective one of the latched states. Register 140 ("A0") is configured, with the 16 register data inputs each connected to a respective line of the 16 lines of "DA" bus 114, with the register clock input connected to "CP" line 116, and with the 16 register data outputs each connected to a respective line of a 16-line bus 160. Multiplexer 150 ("A0") is of the type which has a first set of 16 (A) data inputs, a second set of 16 (B) data inputs, a number of select (control) inputs, and a set of 16 data outputs. Further, "A0" multiplexer 150 is of the type which is operative to develop at the 16 multiplexer data outputs signals the states of which correspond either each to the state of a respective one of 16 signals each developed at the corresponding one of the first set of 16 multiplexer (A) data inputs or each to the state of a respective one of 16 signals each developed at the corresponding one of the second set of 16 multiplexer (B) data inputs, as determined (selected) by the state of signals developed on the multiplexer select (control) inputs. "A0" Multiplexer 150 is configured, with the first set of 16 multiplexer (A) data inputs each connected to a respective one of the 16 lines of bus 160, with the second set of 16 multiplexer (B) data inputs each connected to a respective one of the 16 lines of "DA" bus 114, with the multiplexer select (control) inputs connected to lines of "LDA" bus 120, and with the set of 16 multiplexer data outputs each connected to a respective line of a 16-line bus 164. Register 142 ("A1") is configured, with the 16 register data inputs each connected to a respective line of the 16 lines of bus 164, with the register clock input connected to "CP" line 116, and with the 16 register data outputs each connected to a respective line of a 16-line bus 168. Multiplexer 152 ("A1"), which is similar to "A0" multiplexer 150, is configured, with the first set of 16 multiplexer (A) data inputs each connected to a respective one of the 16 lines of bus 168, with the second set of 16 multiplexer (B) data inputs each connected to a respective one of the 16 lines of "DA" bus 114, with the multiplexer select (control) inputs connected to lines of "LDA" bus 120, and with the set of 16 multiplexer data outputs each connected to a respective line of a 16-line bus 172. Similarly, register 144 ("A2") is configured, with the 16 register data inputs each connected to a respective line of the 16 lines of bus 172, with the register clock input connected to "CP" line 116, and with the 16 register data outputs each connected to a respective line of a 16-line bus 176. Multiplexer 154 ("A2") , which is, also, similar to "A0" multiplexer 150, is configured, with the first set of 16 multiplexer (A) data inputs each connected to a respective one of the 16 lines of bus 176, with the second set of 16 multiplexer (B) data inputs each connected to a respective one of the 16 lines of "DA" bus 114, with the multiplexer select (control) inputs connected to lines of "LDA" bus 120, and with the set of 16 multiplexer data outputs each connected to a respective line of a 16-line bus 180. Finally, register 146 ("A3") is configured, with the 16 register data inputs each connected to a respective line of the 16 lines of bus 180, with the register clock input connected to "CP" line 116, and with the 16 register data outputs each connected to a respective line of a 16-line bus 184. The select (control ) inputs of "A0" multiplexer 150, "A1" multiplexer 152, and "A2" multiplexer 154, which are connected to the three lines of "LDA" bus 120, are configured such that responsive to the state of signals externally developed on "LDA" bus 120, the multiplexers are operative to couple the signals as follows: Multiplexer 156 ("A") is of the type which has eight set of 16 data inputs, a number of select (control) inputs, and a set of 16 data outputs. Further, "A" multiplexer 156 is of the type which is operative to develop at the 16 multiplexer data outputs signals the states of which correspond each to the state of a respective one of a set of 16 signals developed at a selected one of the eight sets of 16 data inputs, the set of data inputs selected being determined by the state of signals developed on the multiplexer select (control) inputs. "A" Multiplexer 156 is configured, with (the first) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 168, with (the second) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 160, with (the third) one of the sets of 16 multiplexer data inputs connected to the 16 lines of bus 176, with (the fourth) one of the sets of 16 multiplexer data inputs connected to the 16 lines of bus 184, and with (the fifth) one of the sets of 16 multiplexer data inputs connected to the 16 lines of "DA" bus 114. Another (sixth) one of the sets of 16 "A" multiplexer 156 data inputs is connected, each input to a respective line of a 16-line "DB(0-15)" bus 190. Still another (seventh) one of the sets of 16 "A" multiplexer 156 data inputs is connected, each input to a respective line of a 16-line "feed-back" "FB" bus 190. The remaining (eighth) one of the sets of 16 "A" multiplexer 156 data inputs is connected each input to a respective line of a 16-line "B" bus 194. The "A" multiplexer 156 select (control) inputs are connected to lines of "RS" bus 122; and, the set of 16 multiplexer data outputs are connected, each output to a respective line of the 16 lines of "R" bus 126. Arithmetic logic unit 100 also includes another, 16-bit, D-type (flip-flop) register 200 and three more multiplexers, which are respectively designated 204, 206, and 208. Register 200 ("B"), which is similar to "A0" multiplexer 140, is configured, with the 16 register data inputs each connected to a respective line of the 16 lines of "DB" bus 190, with the register enable input connected to an "ENB" line 212, with the register clock input connected to "CP" line 116, and with the 16 register data outputs each connected to a respective line of the 16 lines of "B" bus 194. Multiplexer 204 ("B") is of the type which has four set of 16 data inputs, a number of select (control) inputs, and a set of 16 data outputs. Further, "B" multiplexer 204 is of the type which is operative to develop at the 16 multiplexer data outputs signals the states of which correspond each to the state of a respective one of a set of 16 signals developed at a selected one of the four sets of 16 data inputs, the set of data inputs selected being determined by the state of signals developed on the multiplexer select (control) inputs. "B" Multiplexer 204 is configured, with (the first) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of "DA" bus 114, with (the second) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of "DB" bus 190, with (the third) one of the sets of 16 multiplexer data inputs connected to the 16 lines of "B" bus 194, and with the remaining (fourth) one of the sets of 16 multiplexer data inputs connected to the 16 lines of bus "FB" 192. The "B" multiplexer 204 select (control) inputs are connected to lines of "RS" bus 122; and, the set of 16 multiplexer data outputs are connected, each output to a respective line of a 16-line "S" bus 220. The select (control) inputs of "A" multiplexer 156 and "B" multiplexer 204, which are connected to the four lines of "RS" bus 204, are configured such that responsive to the state of signals externally developed on "RS" bus 120, the multiplexers are operative to couple the signals as follows: Multiplexer 206 ("R") is configured, with one set of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of "R" bus 126 and with another set of 16 multiplexer data inputs connected, each input to a low logic level potential ("0"). The "R" multiplexer 206 select (control) inputs are connected to lines of a 5-line "ALU(0-4)" bus 222; and, the set of 16 multiplexer data outputs are connected, each output to a respective line of a 16-line bus 224. Multiplexer 208 ("S") is configured, with one set of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of "B" bus 194, and with another set of 16 multiplexer data inputs connected, each input to a low logic level potential ("0"). The "S" muitiplexer 208 select (control) inputs are connected to the lines of "ALU" bus 222; and, the set of 16 multiplexer data outputs are connected, each output to a respective line of a 16-line bus 226. Arithmetic logic unit 100 further includes a 16-bit, full carry look-ahead, arithmetic logic unit (ALU) 240. Arithmetic logic unit 240 is configured with the first set of 16 unit operand inputs connected, each input to the respective line of the 16 lines of bus 224 and with the second set of unit operand inputs connected, each input to the respective line of the 16 lines of bus 226. In addition, the arithmetic logic unit 240 flag outputs are connected, the unit carry flag output to a "C16" line 244, the unit negative/generate flag output connected to a "N/G*" line 246, the unit overflow/propagate flag output connected to a "OVF/P*" line 248, and the unit zero flag output connected to a "Z" line 250. Further, the arithmetic logic unit 240 control inputs are connected, the four unit function selecting inputs each to a respective line of the four lines of "ALU" bus 222, the unit carry control input to a "CO" line 262, and the unit position control input to a "MSL/LSL*" line 264. Finally, the 16 arithmetic logic unit 240 data outputs are connected, each to a respective line of a 16-line bus 270. Arithmetic logic unit 240 is of the type which, responsive to the state of four signals externally developed on "ALU" bus 222, is operative to execute the following functions: Further, arithmetic logic unit 100 includes a funnel shifter 300, a merge logic unit 302, and a multiplexer 304. Funnel shifter 300 is configured with the set of 16 funnel shifter "R" inputs connected, each input to the respective line of the 16 lines of "R" bus 126 and with the set of funnel shifter "S" inputs connected, each input to the respective line of the 16 lines of "S" bus 220. In addition, the funnel shifter control inputs of funnel shifter 300 are connected, five to the five lines of "ALU" bus 222, and one to "CO" line 262. Finally, the funnel shifter 300 carry input is connected to "MSL/LSL*" line 264; and, the 16 funnel shifter data outputs are connected each output to the respective line of a 16-line bus 310. Funnel shifter 300, which is illustrated in greater detail in Fig. 2, function as follows: and Merge logic unit 302 is configured with the set of 16 merge logic unit merge left "ML" data inputs connected, each input to the respective line of the 16 lines of bus 310, with the set of 16 merge logic unit merge mask "MM" data/control inputs connected, each input to the respective line of the 16 lines of "FB" bus 190, and with the set of 16 merge logic unit merge right "MR" data inputs connected, each input to the respective line of the 16 lines of "FB" bus 190. The 16 merge logic unit 302 data outputs are connected, each output to the respective line of a 16-line bus 314. Merge logic unit 302 is of the type which is described in the United States patent 4,760,517 of Michael J. Miller, Danh Le Ngoc, and John R. Mick. Employed in merge logic unit 302 (but not shown) are sixteen multiplexers, each of which has a special control portion. The multiplexers are each of the type which has a (single) ("ML") data input, that is connected to the respective line of the sixteen lines of bus 310, a single ("MM") data/control input, that is connected to the respective line of the sixteen lines of ("S") bus 220, another (single) ("MR") data input, that is connected to the respective line of the sixteen lines of ("FB") bus 190, and a (single) data output, that is connected to the respective line of the sixteen lines of bus 314. Multiplexer 304, which is similar to "A0" multiplexer 150, is configured, with the first set of 16 multiplexer (A) data inputs each connected to a respective one of the 16 lines of bus 310, with the second set of 16 multiplexer (B) data inputs each connected to a respective one of the 16 lines of bus 314, with the multiplexer select (control) inputs connected to lines of "ALU" bus 222, and with the set of 16 multiplexer data outputs each connected to a respective line of a 16-line bus 318. In an output portion, arithmetic logic unit 100, additionally, includes a multiplexer 400, three, 16-bit, D-type, edge-triggered (flip-flop) registers, respectively designated 404, 406, and 408, two more multiplexers, respectively designated 412 and 414, a bit reversing unit 418, a rounding unit 422, a shifter 426, another multiplexer 430, and a tri-state output driving unit 434. Multiplexer 400 (also referred to as an output portion input register), which is similar to "A0" multiplexer 150, is configured, with the first set of 16 multiplexer (A) data inputs each connected to a respective one of the 16 lines of bus 270, with the second set of 16 multiplexer (B) data inputs each connected to a respective one of the 16 lines of bus 318, with the multiplexer select (control) inputs connected to lines of a 6-line "FSEL(0-5)" bus 440, and with the set of 16 multiplexer data outputs each connected to a respective line of a 16 line bus 444. Registers 404 ("F1"), 406 ("F2"), and 408 ("ACC"), which are each similar to "A0" multiplexer 140, are each configured, with the 16 register data inputs each connected to a respective line of the 16 lines of bus 444, with the register clock input connected to "CP" line 116, and with the register enable input connected to a line of a 2-line "FEN(0-1)" bus 448. The 16 register data outputs of "F1" register 404 are each connected to a respective line of a 16 line bus 450; the 16 register data outputs of "F1" register 406 are each connected to a respective line of a 16 line bus 454; and the 16 register data outputs of "ACC" register 408 are each connected to a respective line of a 16 line bus 458. Multiplexer 412 (also referred to as an output portion feedback multiplexer), which, for clarity, is shown upside down, is similar to "B" multiplexer 204. Multiplexer 412 is configured, with (the first) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 450, with (the second) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 454, with (the third) one of the sets of 16 multiplexer data inputs connected to the 16 lines of bus 458, and with the remaining (fourth) one of the sets of 16 multiplexer data inputs connected to the 16 lines of a "YO" bus 462. The multiplexer 412 select (control) inputs are connected to lines of a 2-line "FBC(0-1)" bus 466; and, the set of 16 multiplexer data outputs are connected, each output to a respective line of "FB" bus 190. Multiplexer 414 (also referred to as an output portion register multiplexer) is of the type which has three set of 16 data inputs, a number of select (control) inputs, and a set of 16 data outputs. Further, multiplexer 414 is of the type which is operative to develop at the 16 multiplexer data outputs, signals, the states of which correspond each to the state of a respective one of a set of 16 signals developed at a selected one of the three sets of 16 data inputs, the set of data inputs selected being determined by the state of signals developed on the multiplexer select (control) inputs. Multiplexer 414 is configured, with (the first) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 450, with (the second) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 444, with (the third) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 454, with the multiplexer select (control) inputs connected to lines of "FSEL" bus 440, and with the set of 16 multiplexer data outputs connected, each output to a respective line of a 16-line bus 468. Bit reversing unit 418 is configured, with the set of 16 bit reversing unit data inputs connected, each input to a respective one of the 16 lines of bus 466, with the control (select) inputs connected to lines of "FSEL" bus 440, with a bit reversing unit control input connected to "MSL/LSL* line 264, and with the set of 16 bit reversing unit data outputs connected, each output to a respective line of a 16-line bus 470. For "bit-reverse addressing" bit reversing unit 418 is responsive to the state of the "FSEL" bus 440 signals and operative to couple the bus 466 signals to bus 470 so as to re-mapping the signals as follows: In a 10-bit mode: In a 12-bit mode: In a 14-bit mode: And, in a 16-bit mode: For this purpose, bit reversing unit 418 has a multiplexer (not shown), which is similar to multiplexer "B" 204. The bit reversing unit 418 multiplexer is configured, with the four sets of 16 multiplexer data inputs (all) connected to bus 466, with the multiplexer select (control) inputs connected to the lines of "FSEL" bus 444, and with the set of 16 multiplexer data outputs connected, each output to a respective line of bus 470. Each input of the first set of multiplexer inputs is connected to a line of bus 466 chosen to re-mapping the bus 466 signals so as to provide the 10-bit mode pattern; each input of the second set of multiplexer inputs is each connected to a line of bus 466 chosen to re-mapping the bus 466 signals so as to provide the 12-bit mode pattern; to provide the 14-bit pattern, each input of the third set of multiplexer inputs is connected to the appropriate line of bus 466; and, each input of the fourth set of multiplexer inputs is connected to a line of bus 466 chosen to re-mapping the bus 466 signals so as to provide the 16-bit mode pattern. Rounding unit 422 is configured, with the set of 16 rounding unit data inputs connected, each input to a respective one of the 16 lines of bus 466, with the rounding unit control (select) inputs connected to lines of "FSEL" bus 440, with the rounding unit borrow input connected to a "SIO0" line 474, with the rounding unit control input connected to "MSL/LSL* line 264, with the rounding unit carry output connected to a "SIO16" line 478, and with the set of 16 rounding unit data outputs connected, each output to a respective line of a 16-line bus 474. In a stand alone mode, and in a 32-bit mode in which rounding unit 440 is in the most significant slice, rounding unit is operative to increment by one the binary number represented by the state of the signals developed on bus 466 when a signal externally developed on "SIO0" line 474 has a high logic level ("1"), and to leave the number unchanged otherwise (when the "SIO0" line 474 signal has a low logic level ("0")). In the 32-bit mode when rounding unit 440 is in the least significant slice, the rounding unit is operative to round the binary number represented by the state of the signals developed on bus 466 from bit 13 into bit 14 or round from bit 14 into bit 15, as selected by the state of signals externally developed on the lines of "FSEL" bus 440, and to develop a suitable carry signal on "SIO16" line 478. Shifter 426 is configured, with the set of 16 shifter data inputs connected, each input to a respective one of the 16 lines of bus 466, with the shifter control (select) inputs connected to lines of "FSEL" bus 440, with the other shifter control input connected to "MSL/LSL*" line 264, with the shifter bit 16 (left end) shift input/output connected to "SIO16" line 478, with the shifter bit 0 (right end) shift input/output connected to "SIO0" line 474, and with the set of 16 shifter data outputs connected, each output to a respective line of a 16-line bus 478. Responsive to the state of signals externally developed on "FSEL" bus 440 and "MSL/LSL*" line 264, shifter 426 is operative to shift the bits of the binary number represented by the signals developed on bus 466 up logically, down logically, up arithmetically, or down arithmetically. Multiplexer 430 (also referred to as an output portion output multiplexer), which is similar to "B" multiplexer 204, is configured, with (the first) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 470, with (the second) one of the sets of 16 multiplexer data inputs connected, each input to a respective one of the 16 lines of bus 466, with (the third) one of the sets of 16 multiplexer data inputs connected to the 16 lines of bus 474, and with the remaining (fourth) one of the sets of 16 multiplexer data inputs connected to the 16 lines of bus 478. The multiplexer 430 select (control) inputs are connected to lines of "FSEL" bus 440; and, the set of 16 multiplexer data outputs are connected, each output to a respective line of A 16-line bus 482. Finally, tri-state output driver unit 434 is configured, with the set of 16 unit data inputs connected, each input to a respective one of the 16 lines of bus 482, with the unit output-enable input connected to a "OEA" line 486, and with the set of 16 unit data outputs connected, each output to a respective line of "YO" bus 462. The arithmetic logic unit 100 output portion is responsive to signals externally developed on "FSEL" bus 440 and operative to develop the "YO" bus 462 signals as follows: In the presently preferred embodiment, the components of arithmetic logic unit 100 are all integrated into a single device using CMOS technology.

Claims: A programmable, pipelined logic device (100) with an arithmetic logic unit (ALU) (240), a funnel shifter (426) and a merge logic unit (302), characterized by: a first data register (140) connected to a first data input bus (114); a fist data multiplexer (150) having a first input connected to an output of the first data register (140) and a second input connected to said first data input bus (114) for configuring the first data register as part of a two-deep or four-deep pipeline register or as an independent data register; a second data register (142) connected to an output of the first data multiplexer (150); a second data mutiplexer (152) having a first input connected to an ouput (168) of the second data register (142) and a second input connected to said first data input bus (114) for configuring the second data register (142) as part of said two-deep or four-deep pipeline register or as an independent data register; a third data register (144) connected to an output (172) of the second data multiplexer (152); a third data multiplexer (154) having a first input connected to an output (176) of the third data register (144) and a second input connected to said first data input bus (114) for configuring the third data register (144) as part of said two-deep or four-deep pipeline register or as an independent data register; a fourth data register (146) connected to an output (180) of the third data multiplexer (154); a single clock means (116) connected to the first through fourth data registers (140, 142, 144, and 146); and a fourth data multiplexer (156) having a first input (184) connected to an output of the fourth data register (146), a second input connected to said first data input bus (114), a third input connected to said output (168) of the second data register (142), a fourth input connected to said output (176) of the third data register (144), a fifth input connected to said output (160) of the first data register (140) and a control input (122) for selecting one of said first through fifth inputs through to a data output (126) for configuring the fourth data register (146) as part of said two-deep or four-deep pipeline register or as an independent data register, for latching and delaying arithmetic parameter data presented on said data input bus (114) to said ALU (240). The device of claim, further comprising: a bit reversing unit (418) connected to receive data from the ALU (240) for reversing the order of bits between a pair of buses (466 and 470) as output from the ALU (240). The device of claim 1 or 2, further comprising: a rounding unit (422) connected to receive data from the ALU (240) for rounding off a digital word represented between a pair of buses (466 and 474) as output from the ALU (240). The device of claim 1 wherein all components are in a single complementary metal oxide semiconductor (CMOS) chip, which further comprises: a bit reversing unit (418) connected to receive data from the ALU (240) for reversing the order of bits between a pair of buses (466 and 470) as output from the ALU (240); and a rounding unit (422) connected to receive data from the ALU (240) for rounding off a digital word represented between a pair of buses (466 and 474) as output from the ALU (240).

Inventors: LE NGOC DANH, MICK JOHN R, LE NGOC, DANH, MICK, JOHN R.
Applicants: INTEGRATED DEVICE TECH, INTEGRATED DEVICE TECHNOLOGY, INC.
Application year: 1990
Main classification: G06F17
IPC codes: G06F7, G06F17