Phase matching circuit

Abstract: A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region. The phase matching circuit includes an input buffer (210) for taking first data with a first clock; an output buffer (218) sending second data with a second clock: a phase detector (220) for comparing the phases of first and second clocks and detecting a phase difference within a predetermined value; a phase control unit (216) for directly outputting the first data to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data phase shifted to the output buffer, and for converting the first data synchronized with the first clock to the second data of the same content as the first data synchronized with the second clock in the same frequency as the first clock: an invalid data region detector (214) for detecting an invalid region of first data; and a phase shifter controller (212) for inhibiting phase shift control in the phase control unit (216) when the invalid data region detector does not detect the invalid region and for allowing phase shift control in the phase control unit when the invalid data region detector detects the invalid region.

Description: BACKGROUND OF THE INVENTION a. Field of the Invention The present invention relates to a phase matching circuit and a method for converting first data synchronized with a first clock into second data of the same content as the first data synchronized with a second clock which has the same frequency as the first clock, and more particularly to a phase matching circuit suitable for changing the clock from the receiving clock to a system clock at a terminal repeater in a synchronous multiplex transmission system for transmitting a signal having used and unused data regions. b. Description of the Related Art In an apparatus for high speed transmission of signals which multiplex a voice signal and an image signal, the transmitter and receiver are operated synchronously. In this case, a phase matching circuit is provided within a terminal repeater connecting respective units in order to match the phase of the clocks of the respective units for the purpose of changing the clocks in the adequate timing curing transfer of clocks between the units. However, although the prior art includes such a phase matching circuit, it has generated a problem in that accurate processing cannot be carried out in the receiving apparatus because valid data which are read in the receiving side apparatus are missed or such valid data are read twice due to the matching of the clocks using the phase matching circuit associated with the prior art. An example of the structure of a known phase matching circuit is shown in Fig. 1. CK1 denotes a first clock used in the transmitting side apparatus, while D1 denotes first data output from the transmitting side apparatus. CK2 denotes a second clock used in the receiving side apparatus, while D2 denotes second data input to the receiving side apparatus. The first data D1 and second data D2 have the same content, and the first clock and second clock have the same frequency. Reference numeral 101 denotes an input buffer which takes the first data D1 from the transmitting apparatus in accordance with the first clock CK1 used in the transmitting apparatus, 102 denotes an output buffer which sends the second data D2 of the same content as the first data D1 to the receiving apparatus in accordance with the second clock CK2 used in the receiving apparatus, 103 denotes a phase detector which inputs and compares the phases of the first clock CK1 and the second clock CK2 and determines whether the phase difference between the two clocks is within a predetermined value, and 104 denotes a phase controller which controls the timing for punching the first data D1 which is input in accordance with the second clock CK2 either directly or inverted based on the detection result of the phase detector 103. In the phase matching circuit shown in Fig. 1, the first data D1 is taken by the first clock CK1 from the transmitting apparatus. The phase detector 103 receives the first clock CK1 and the second clock CK2 and detects whether a phase difference is within the predetermined value or not. Detection of the phase difference is necessary because if the first clock CK1 and the second clock CK2 have the same phase, then there is a high probability that when data is taken the content of receiving data will be changing in the receiving apparatus. Thus, accurate data reading is not possible. Therefore, when two clocks come close to the same phase, this problem occurs. This problem has been solved by shifting the phase of the first data D1 with a phase matching circuit. The phase controller 104, which consists of an intermediate buffer 105 and a clock switch 106, receives the second clock CK2 and either inverts the second clock CK2 or uses it directly, depending on whether the phase difference between the first clock CK1 and the second clock CK2 is within the predetermined value or not. That is, the clock switch 106 causes data to be read from the intermediate buffer 105 with a clock, which is either the second clock CK2 directly or the second clock CK2 inverted depending on the phase difference detected by the phase detector 103. When the second clock CK2 is inverted due to such phase shift control, the inverted second clock is thereafter inverted again or normalized to the second clock CK2 when the phase difference is no longer within the predetermined value. As a result, phase shift control is carried out for the data being transmitted. However, the phase matching circuit associated with the prior art discussed above results in the following problems. Figs. 2A-2F and Figs. 3A-3F illustrate timing charts for the phase matching circuit associated with the prior art. Designations A-F shown in Fig. 1 correspond to the timing charts of Figs. 2A-2F and of Figs. 3A-3F, respectively. Figs. 2A-2F indicate that when the phase detector 103 detects the phase difference to be within the predetermined value, the phase of the second clock CK2 is shifted by inverting the second clock CK2 in the clock switch 106. Figs. 3A-3F indicate that when the phase difference exceeds the predetermined value after being within the predetermined value, the inverted second clock is inverted again or normalized to the normal phase of the second clock CK2 in the clock switch 106. These phase shift operations cause the phase of the data to shift. A problem of such phase shift control, however, is that data are missed or read twice, as shown in Figs. 2F and 3F. That is, the phase matching circuit associated with the prior art carries out phase shift control without relation to the content of the data. As a result, the above-mentioned problem arises in that the valid data to be read in the receiving side is missed or read twice. Thus, accurate processing cannot be conducted in the receiving side. From EP 0 004 887 a method and device for synchronizing digital transmissions via satellite is known. For synchronizing with on board timing of a regenerative satellite in TDMA digital transmissions there is effected a frequency conversion so as to bring the frequency of the regenerated signal to the nominal onboard operation frequency, and a phase correction is performed at the transitions between adjacent bursts of the TDMA signal, so as to eliminate phase discontinuities in the symbol sequence sent to the onboard processing device. From EP 0 153 107 a clock recovery apparatus and method for a ring-type data communications network is known which provides a digital data stream from an incoming stream of raw data. The apparatus employs a clock generator having a fixed operating frequency for providing a clock signal, a receiving circuitry for receiving the incoming data stream, a phase comparison circuit for comparing the phase of the incoming data stream with the clock signal, and a phase selection circuit responding to the phase comparison circuit for discretely changing the relative phase difference of the data stream and the clock when the phase difference between them exceeds a predetermined phase tracking criteria. The apparatus can change the clock generator output phase, keeping the frequency fixed, or can insert a delay of variable discrete increments in the input data path. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a phase matching circuit which realizes accurate data transmission and reception. This object is solved as defined in claims 1 and 13, respectively. The present invention provides a phase matching circuit which includes an input buffer for taking first data with a first clock; an output buffer for sending second data with a second clock; a phase detector for comparing phases of the first and second clocks and detecting a phase difference within a predetermined value; and a phase control unit for outputting directly the first data input from the input buffer to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data input from the input buffer phase shifted when the phase difference within the predetermined value is detected, and converting the first data synchronized with the first clock into the second data synchronized with the second clock. Further, the present invention is provided with an unused data region detector for detecting an unused data region of the first data, and a phase shift controller for inhibiting phase shift control by the phase control unit when the unused data region is not detected by the unused data region detector and for allowing phase shift control by the phase control unit when the unused data region is detected by the unused data region detector. The resulting improved phase shift circuit utilizes the fact that the data includes a valid region which is read in the receiving apparatus and an invalid region which is not read in the receiving apparatus by performing phase shift controi only during a valid region of the data. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a phase matching circuit of the prior art; Figs. 2A-2F and Figs. 3A-3F are timing charts illustrating the operation of Fig. 1; Fig. 4 is a block diagram illustrating the basic principal of the present invention; Fig. 5 is a block diagram illustrating a first embodiment of the phase matching circuit of the present invention; Fig. 6 is a block diagram illustrating a second embodiment of the phase matching circuit of the present invention; and Figs. 7A-7G and Figs. 8A-8G are timing charts illustrating the operation of the phase matching circuit of the present invention. These together with other objects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout. DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic principal of the invention together with preferred enbodiments of the present invention will be explained in detail below with reference to Figs. 4-7. The basic principle of the present invention is illustrated in Fig. 4. The present invention relates to phase matching circuit formed by an input buffer 210, a phase detection and inhibit unit 212, an unused data region and detection unit 214, a phase control unit 216, and an output buffer 218. The input buffer 210 receives input data as first data D1 and an input clock as a first clock CK1 from a transmitting apparatus. The first clock CK1 is sent to the phase detection and inhibit unit 212 and the unused data region detection unit 214. The output buffer 218 sends out output data as second data D2 to a receiving apparatus using a second clock CK2 provided by the receiving apparatus. The second clock CK2 is sent to the phase detection and inhibit unit 212 and the phase control unit 216. Next, the phase detection and inhibit unit 212 compares the phase of the first clock CK1 with the phase of the second clock CK2 to determine if the phase difference is within a predetermined value. This operation is performed by a phase detection unit 220 which is included within the phase detection and inhibit unit 212. Meanwhile, the unused data region detection unit 214 determines whether the first data D1 is in an unused data region (invalid region) or an used data region (valid region). Then, the phase detection and inhibit unit 212 produces a phase inversion signal based upon the phase difference detected by the phase detection unit 220 and the detection of data regions by the unused data region detection unit 214. More particularly, when the phase detection unit 220 detects the phase difference within the predetermined value the phase inversion signal is produced. However, the phase inversion signal is not output to the phase control unit 216 until an unused data region is detected by the unused data region detection unit 214. This gating or inhibiting operation is performed by a phase shift control unit 222 contained within the phase detection and inhibit unit 212. Once the phase inversion signal is output from the phase detection and inhibit unit 212, the phase control unit 216 controls the phase shift operation. The phase control unit 216 includes an intermediate buffer 224 and a phase inverter and normalizer 226. The phase inverter and normalizer 226 receives the phase inversion signal and shifts or inverts the second clock CK2 when the phase inversion signal indicates that the phase difference is within the predetermined value. The phase inverter and normalizer 226 outputs an intermediate clock which corresponds to either the second clock CK2 directly or the second clock after having been shifted or inverted. The intermediate buffer 224 then receives the first data D1 in accordance with the intermediate clock, thus causing a shift in phase of the first data. Finally, the first data, whether shifted or not, is output by the output buffer 218. Fig. 5 illustrates a first embodiment of the present invention. The first embodiment will be explained in detail with regard to Fig. 5. The phase matching circuit of the first embodiment is formed by an input buffer 310, an unused data region detector 314, a phase controller 316, an output buffer 318, a phase detector 320, and a phase shift controller 322. The input buffer 310 receives the input data as the first data D1 and the input clock as the first clock CK1, and is formed by a D-type flip-flop. The output buffer 318 receives the second clock CK2 and outputs the output data as the second data D2, and is also formed by a D-type flip-flop. The output data has the same content as the input data, and the output clock has the same frequency as the input clock. Although invalid data may be lost or read twice, the consequence of such is harmless to the correct reception of the valid data. The phase detector 320 detects whether the second clock CK2 has a phase difference from the phase of first clock CK1 that is within the predetermined value or not. The phase detector 320 can also be formed by a D-type flip-flop. The first clock CK1 is input to the data input (D input) and the second clock CK2 is input to the clock input (C input) of the D-type flip-flop 320. Therefore, the output of the D-type flip-flop 320 becomes "1" when the phase difference between the first clock CK1 and the second clock CK2 is within the predetermined value. In all other cases, the output of the D-type flip-flop 320 becomes "0". The phase controller 316 applies the first data D1 either directly or phase shifted to the output buffer 2 depending on the result of the detecting by the phase detector 320. Therefore, the phase controller 316 includes a phase inverter and normalizer 326 which inverts or normalizes the second clock CK2 depending on the result of the detecting by the phase detector 320. The phase inverter and normalizer 326 corresponds to the clock switch 106 described above. The phase controller 316 also includes an intermediate buffer 324 and a delay circuit 328. The intermediate buffer 324 receives data output from the input buffer 310 and applies such data to the output buffer 318. As the intermediate buffer 41, a D-type flip-flop can be used like the input buffer 310 and output buffer 318. The delay circuit 328 is provided to delay the second clock CK2 so that data can be accurately read in the intermediate buffer 324. The delay circuit 328 delays the second clock CK2 prior to its input to the phase inverter and normalizer 326. Note, however, that alternatively the delay circuit 328 could be located at the clock input (C input) of the output buffer 318. That is, the delay circuit 328 is provided so that the clock input to the intermediate buffer 324 and the clock input to the output buffer 318 are not in phase. The phase inverter and normalizer 326 inverts the second clock CK2 when the phase detector 320 detects a phase difference within the predetermined value between the first clock CK1 and the second clock CK2. Alternatively, the phase inverter and normalizer 326 outputs the second clock CK2 in its normal phase when the phase detector 320 detects a phase difference greater than the predetermined value between the first clock CK1 and the second clock CK2. As the phase inverter and normalizer 326, an exclusive OR gate (EXOR gate) can be used. The unused data region detector 314 can also be formed by a D-type flip-flop. The unused data region detector 314 detects an unused data region using identification data contained in the first data D1. The identification data is, for example, binary data which is "1" for a used data region or "0" for an unused data region. The data input (D input) of D-type flip-flop 314 receives the identification data and the first clock CK1 is input to the clock input (C input) as shown in Fig. 5. The identification data is a signal which exists, for example, in the header of each frame of the first data D1 to indicate whether or not the data in the frame includes data to be read and used in the receiving apparatus. The circuit diagram of the first embodiment shown in Fig. 5 indicates an apparatus for processing only one bit in order to simplify the explanation. The phase shift controller 322 inhibits phase shift control in the phase controller 316, even when a phase difference within the predetermined value is detected by the phase detector 320, until the unused data region detector 314 detects an unused data region in the first data D1. That is, the phase shift controller 322 allows phase shift control in the phase controller 324 only when the unused data region is detected and not when a used data region is detected. A D-type flip-flop can be used as the phase shift controller 322. The output from the phase detector 320 is input to the data input (D input) of D-type flip-flop forming the phase shift controller 322 and the output from the unused data region detector 314 is input to the clock input (C input) thereof. The result detected by the phase detector 320 is maintained in the phase shift controller 322 until an unused data region is detected by the unused data region detector 314. Once an unused data region is detected, the data maintained is then applied to the phase inverter and normalizer 326 of the phase controller 316. When the unused data region detector 314 detects an unused data region, it causes the phase shift controller 322 to latch the output from the phase detector 320. Namely, the phase shift controller 322 is inserted between the phase detector 320 and the phase controller 316 so that the data input to the phase controller 316 is not altered until the unused data region is detected. With the structure mentioned above, the first data D1 is applied to the output buffer 318 either directly or phase shifted depending on the detection result of the phase detector 320. However, if the unused data region detector 314 does not detect the unused data region of the input data D1, phase shift control in the phase shift controller 316 is inhibited by holding the detection result previously output from the phase detector 320 in the phase shift controller 322. Thereafter, phase shift control is allowed by latching the detection result currently output from the phase detector 320 when the unused data region detector 314 detects an unused data region of the first data D1. The unused data region corresponds to an invalid region in an over-head area of a signal format consisting of the over-head area and a pay-load area in units of a byte, such as the signal format used in a synchronous optical network. The invalid region indicates the region is not currently defined as the particular control byte, although it may be defined in the future as control information. In such a network, the processing is carried out byte-by-byte and the processing for each bit as explained in the above-described embodiment is conducted in parallel for 8 bits. Namely, the header bit of each byte is the identification data and the other seven (7) bits are processed in parallel depending on the content of identification data. The above-described phase control operation will be explained in more detail below with reference to the timing charts of Figs. 7A-7G and Figs. 8A-8G. Note, Figs. 7G-7G and Figs. 8A-8G take into consideration the differences of delays for each signal. Comparing Fig. 7 with Fig. 2 may facilitate the understanding of this control. In this embodiment, when a phase difference within the predetermined value is detected by the phase detector 320 (Fig. 6C), phase shift control for the first data D1 is carried out by inverting the second clock CK2 at EXOR 326 as shown in Fig. 6D. However, since data is used in the region (data used region), such control is not carried out. Nevertheless, phase shift control of the first data D1 is carried out by inverting clock CK2 at EXOR 326 when the unused data region is eventually detected ("0" region of Fig. 6B). Moreover, Fig. 8 shows the timing charts when a phase difference exceeds the predetermined value after the phase control operation has been performed. The phase shift control operation is carried out by normalizing the second clock CK2 at EXOR 326 when an unused data region (region "0" of Fig. 7B) is detected by the unused data region detector 314. With such control, only the unused data region is missed or read twice in the receiving apparatus, and the data regions used in the receiving side are never missed. Thus, accurate processing may be carried out in the receiving apparatus. In a synchronous multiplex transmission system, the unused data region is generated at a rate of about 1/30 of the used data region. Therefore, even when phase shift control of data is not carried out immediately after the phase difference within the predetermined value is detected, the phase shift of data is conducted after an unused data region occurs. Hence, the problem of reading the partitioning area of the data does not occur. Next, a second embodiment of the present invention will be explained. The phase matching circuit of the second embodiment has the structure as shown in Fig. 6. For example, the phase matching circuit is provided within the terminal repeater. The second embodiment is different from the first embodiment in the structure and location of the phase shift controller 322. Namely, a phase shift controller 322, of the second embodiment is formed as a gate circuit to control supply of the first clock CK1 to the clock input of the phase detector 320. For example, a NOR gate can be used as the gate circuit 422. This replaces the phase shift controller 322 of the first embodiment. The output from the unused data region detector 314 and the first clock CK1 are input to the gate circuit forming the phase shift controller 422. When the unused data region detector 314 detects an unused data region, the first clock CK1 is supplied to the phase detector 320. Accordingly, even in the structure of the second embodiment, if the unused data region detector 314 does not detect an unused data region of the first data D1, phase shift control by the phase controller 316 is inhibited. On the other hand, when the unused data region detector 314 detects an unused data region of first data D1, phase shift control by the phase controller 316 is allowed. Consequently, an effect similar to that of the first embodiment may also be obtained by the second embodiment.

Claims: A phase matching circuit for converting first data (D1) synchronized with a first clock (CK1) into second data (D2), the second data having the same content as the first data (D1) and synchronized with the second clock (CK2) having the same frequency as the first clock (CK1), said phase matching circuit comprising: input buffer means (210, 310) for taking the first data (D1) with the first clock, the first data (D1) including used and unused data regions; output buffer means (218, 318) for sending the second data (D2) with the second clock (CK2); phase detector means (220, 320) for comparing phases of the first (CK1) and second (CK2) clocks to detect a phase difference within a predetermined value; phase control means (216, 316) operatively connected to said input buffer means (210, 310), said output buffer means (218, 318) and said phase detector means (220), for performing phase shift control by one of outputting directly the first data (D1) to said output buffer means (218, 318) when the phase difference within the predetermined value is not detected by said phase detector means (220), and outputting the first data (D1) phase shifted to said output buffer means (218, 318) when the phase difference within the predetermined value is detected by said phase detector means (220); unused data region detector means (214, 314) for detecting one of the unused data regions within the first data (D1); and phase shift controller means (222, 322), operatively connected to said unused data region detector means (214, 314), for inhibiting the phase shift control by said phase control means (216, 316) when said unused data region detector means (214, 314) does not detect one of the unused data regions and for allowing the phase shift control in said phase control means (216, 316) when said unused data region detector means (214, 314) detects one of the unused data regions. A phase matching circuit according to claim 1, wherein said phase matching circuit is provided in a synchronous optical network, wherein the first data (D1) has a synchronous optical network format including an over-head portion and a pay-load portion, and wherein the unused data regions are defined regions in the over-head portion of the synchronous optical network format. A phase matching circuit according to claim 1, wherein said phase shift controller means (222, 322) inhibits the phase shift control in said phase control means (216, 316) by inhibiting an output (C) from said phase detector means (220, 320) to said phase control means (216, 316) when said unused data region detector means (214, 314) does not detect one of the unused data regions. A phase matching circuit according to claim 3, wherein said phase shift controller means (222, 322) comprises a D-type flip-flop (322) operatively connected to receive the output (C) of said phase detector means (220, 320) at a data input and an output (B) of said unused data region detector means (214, 314) at a clock input. A phase matching circuit according to claim 3, wherein said phase control means (216, 316) comprises: an exclusive OR gate (326), having a first input receiving the second clock (CK2) and a second input receiving an output of said phase shift controller means (222, 322), for producing an intermediate clock (D); and an intermediate buffer (324) for sending the first data in the timing of the intermediate clock. A phase matching circuit according to claim 1, wherein said phase shift controller means (222, 322) inhibits the phase shift control in said phase control means (216, 316) by inhibiting input of the first clock (CK1) to said phase detector means (220, 320) when said unused data region detector means (214, 314) does not detect one of the unused data regions. A phase matching circuit according to claim 6, wherein said phase shift controller means (222, 322) comprises a gate circuit (322), having a first input receiving the first clock (CK1) and a second input receiving an output of said unused data region detector means (214, 314), for inputting the first clock (CK1) to said phase detector means (220, 320) when said unused data region detector means (214, 314) detects the unused data region. A phase matching circuit according to claim 6, wherein said phase control means (216, 316) comprises: an exclusive OR gate (326) having a first input receiving the second clock (CK2) and a second input receiving an output of said phase detector means (320), for producing an intermediate clock; and an intermediate buffer (324) for sending the first data (D1) in the timing of the intermediate clock. A phase matching circuit according to claim 6 or 8, wherein said phase control means (216, 316) further comprises delay means (328) for delaying the second clock (CK2). A phase matching circuit as recited in claim 1, wherein said phase matching system is provided in a terminal repeater of a synchronous multiplex transmission system, and wherein the first data corresponds to the second data, and the first frequency equals the second frequency. A phase matching circuit as recited in claim 1, wherein said phase shift control means comprises: intermediate buffer means for receiving the first data from said input buffer means and for outputting the first data with one of the intermediate clock and the inverted intermediate clock; phase shift inhibit means for inhibiting the inverting of the intermediate clock until said data detection means detects an unused data region; and phase inversion and normalization means for producing one of the intermediate clock and the inverted intermediate clock. A phase matching circuit as recited in claim 1, wherein said phase shift control means further comprises delay means for delaying the second clock to produce the intermediate clock. A method for converting first data (D1) from a transmission system to second data (D2) for a reception system, the first data (D1) is synchronized with a first clock (CK1) having a first phase and the second data (D2) is synchronized with a second clock (CK2) having a second phase, the first data (D1) has used and unused data regions, said method comprising the steps of: (a) receiving the first data (D1), the first clock (CK1) and the second clock (CK2); (b) determining a phase difference between the phase of the first clock (CK1) and the phase of the second clock (CK2); (c) comparing the phase difference with a predetermined value; (d) producing a phase difference signal (C) based on said comparing in step (c); (e) detecting one of the used and unused data regions in the first data (D1); (f) shifting the first data (D1) to produce shifted first data (E) when the phase difference signal (C) indicates the phase difference is less than the predetermined value and when said detecting in step (e) detects one of the unused data regions; and (h) outputting one of the first data (D1) and the shifted first data as the second data (D2). A method as recited in claim 13, comprising the steps: converting the second clock (CK2) into an intermediate clock; inverting the intermediate clock to produce an inverted intermediate clock (D) when the phase difference signal indicates the phase difference is less than the predetermined value and when said detecting in step (e) detects one of the unused data regions; producing intermediate data (E) from the first data (D1) in accordance with one of the intermediate clock when the inverted intermediate clock (D) is not produced and the inverted intermediate clock (D) when the inverted intermediate clock is produced in step (g), and outputting the second data (D2) from the intermediate data (E) in accordance with the second clock (CK2). A method as recited in claim 14, wherein said method is performed by a terminal repeater of a synchronous multiplex transmission system, and wherein the first data (D1) corresponds to the second data (D2), and the first frequency equals the second frequency. A method as recited in claim 15, wherein said converting the second clock (CK2) into an intermediate clock comprises the step of delaying the second phase of the second clock (CK2) to produce the intermediate clock.

Inventors: ISHIHARA TOMOHIRO, TANIGUCHI ATSUKI, WAKISAKA TAKAAKI, YAMASHITA HARUO, ISHIHARA, TOMOHIRO, TANIGUCHI, ATSUKI, WAKISAKA, TAKAAKI, YAMASHITA, HARUO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H04J3
IPC codes: H04L7, H04J3