Integrated constant current circuit with a BJT and a JFET

Abstract: A constant current circuit comprises a junction type field effect transistor and a bipolar transistor. The channel forming region of the junction type field effect transistor and the base region of the bipolar transistor are constituted to be common to each other.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a constant current circuit and an integrated circuit having said circuit, particularly to a constant current circuit and an integrated circuit having said circuit which can be suitably used in an analog integrated circuit. Various circuits have been proposed up to date as the constant current circuit to be used in analog integrated circuits. Fig. 1 shows a circuit showing an example of the constant current circuit of the prior art. In the Figure, T a , T b and T 1 - T 3 represent transistors, Z 1 - Z 3 loads and R a , R b and R 1 - R 3 resistors. I 1 - I 3 are constant currents obtained in the circuit shown in Fig. 1. Such constant current circuit makes I 1 - I 3 constant currents respectively by setting T 1 and R 1 , T 2 and R 2 , and T 3 and R 3 based on the bias potential V b set by the transistor T a and T b and resistors R a and R b , not depending on fluctuations of Z 1 -Z 3 . Also, Fig. 2 shows another example of the constant current circuit of the prior art. In the Figure, T a , T b , T 1 and T 2 each represent a transistor, Z 1 and Z 2 each a load, I 1 and I 2 each a constant current obtained in the circuit shown in Fig. 2, and R a and R b each a resistor. Also in such constant current circuit, constant currents I 1 and I 2 are obtained on the basis of the bias potential V b generated by setting of I o with the band gap output voltages V BG and R a . However, the constant current circuits of the prior art as mentioned above had the following problems (1) In the constant current circuit shown in Fig. 1, errors of current values occur due to variance in characteristics of the transistors, whereby desired constant current cannot be sometimes obtained with good precision. Also, for solving this problem, choice of transistors is required or a more complicated circuit constitution is required. (2) In the constant current circuit shown in Fig. 2, because a band gap circuit and an amplifier circuit are required, the circuit scale is large and complicated. There is disclosed in the IBM Technical Disclosure Bulletin Vol. 24, No. 5, October 1981, an improved integrated current source for merged transistor logic (MTL) circuits which features a junction field-effect transistor (J-FET), and a bipolar transistor. In this prior art arrangement a common region acts as both the drain of the J-FET and an external base of an npn transistor. US Patent No. 4,403,395 relates to circuits and processes for the monolithic integration of vertical NPN, lateral NPN, lateral PNP, substrate PNP, P-MOS, N-MOS, D-MOS and J-FET components. There is disclosed a monocrystalline n-type semiconductor surface layer formed epitaxially on a substrate covering each of the device locations, P+ regions then being selectively formed in the epitaxial layer extending therethrough to provide p-n junction isolation between adjacent component regions. SUMMARY OF THE INVENTION According to the present invention, there is provided a circuit device comprising a bipolar transistor having a collector region of a first conductivity type, a base region of a conductivity type opposite to the first conductivity type and an emitter region of the first conductivity type, and a junction type field effect transistor having a gate region of the first conductivity type electrically connected to said collector region and a source region and a drain region of the opposite conductivity type provided in contact with the base region of said bipolar transistor with said gate region sandwiched therebetween, characterised in that the collector region of said bipolar transistor and the gate region of said junction type field effect transistor form a continuous region of the same conductivity type and the collector region surrounds the base and emitter regions and the junction type field effect transistor. How the invention may be carried out will now be described by way of example only and with reference to the accompanying drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an example of the constant current circuit of the prior art; Fig. 2 is a circuit diagram showing another example of the constant current circuit of the prior art; Fig. 3A is a schematic top view showing the pertinent portion of the constant current circuit according to the present invention; Fig. 3B is a schematic sectional view taken along X-X' of the circuit shown in Fig. 3A; Fig. 4 is a circuit diagram showing the equivalent circuit of the circuit shown in Fig. 3A and Fig. 3B. DESCRIPTION OF THE PREFERRED EMBODIMENTS The tasks as described above can be accomplished by the constitution as described below. That is, the constant current circuit and the integrated circuit having said circuit has a junction type field effect transistor and a bipolar transistor, and the channel forming region of said junction type field effect transistor and the base region of said bipolar transistor are constituted to be common to each other. In this constitution, it is preferable, also from the point of receiving little influence from other elements or circuits when formed into an integrated circuit, that the above-mentioned junction type field effect transistor and the above-mentioned bipolar transistor be formed in the same isolation. Further the gate region of the junction type field effect transistor and the collector region of the bipolar transistor be also made common to each other. Also, the circuit device of the present invention has a bipolar transistor having a collector region of a first conductivity type, a base region of a conduction type opposite to the first conductivity type and an emitter region of the first conductivity type, and a junction type field effect transistor having a gate region of the first conductivity type electrically connected to said collector region and a source region and a drain region of the opposite conductivity type provided in contact with the base region of said bipolar transistor and with said gate region sandwiched therebetween. More specifically, the present invention, by making the channel formation region of a junction type field effect transistor (hereinafter written as JFET) and the base region of a bipolar transistor (hereinafter written as BPT) common to each other, is adapted to compensate the variance of collector current of BPT due to variance of the width of the base of BPT (the width of channel formation region in JFET) with the drain current, thereby maintaining the collector current of BPT constant. Therefore, according to the constant current circuit of the present invention, variance of current value caused by variance of the base width of BPT can be excluded. Also, the constant current circuit of the present invention, by forming JFET and BPT within the same isolation, and further making the channel formation region of JFET and the base region of BPT common to each other, can simplify the circuit constitution and reduce the occupied area by the circuit within the integrated circuit. Further, by making the gate region of JFET and the collector region of BPT common to each other by forming continuously the gate region and the collector region as the same conduction type region, further simplification and area reduction are rendered possible. [Example] Referring now to the drawings, a preferable example of the constant current circuit of the present invention is described. Fig. 3A is a schematic top view showing the pertinent portion of the constant current circuit according to this example, and has a NPN type BPT (hereinafter written merely as BPT) and a P channel JFET (hereinafter written merely as JFET) formed therein. BPT and JFET correspond to the transistors T a and T b in Fig. 1 or Fig. 2, respectively. Fig. 3B is a schematic sectional view taken along X-X' in the circuit shown in Fig. 3A. In Figs. 3A and 3B, 1 is an isolation for separating other elements from the present circuit, 2 a collector region of a first conductivity type BPT, 12 a gate region of JFET of the same conductivity type electrically connected to the above-mentioned collector region 2, 2' a contact portion of the gate 12 functioning as both collector of BPT and JFET, 3 a source (or drain) region of JFET of the conductivity type opposite to the first conductivity type, 4 functioning as both a base contact region of BPT and a drain (or source) region of JFET, 4' a contact portion functioning as both a base region 6 of BPT and the drain 4 of JFET, 5 an emitter region of BPT, 5' a contact portion of the emitter 5 of BPT, 6 functioning as both a base region of BPT and a channel formation region of JFET. 13 is an embedded region of the first conductivity type. The amounts of the impurities doped to the respective conductivity types may be determined as desired. Fig. 4 is a circuit diagram showing the equivalent circuit of the circuit shown in Figs. 3A and 3B. In the Figure, terminals A, B, C correspond to the terminals A, B, C shown in Fig. 3B, respectively. By constituting a constant current circuit as shown in Fig. 2 by using such a circuit, a constant current circuit with little error of current value could be obtained. In the following, the reason why variance of the collector current of BPT can be suppressed as small with the constitution shown in Fig. 3A and Fig. 3B is described by referring to Fig. 3B. In Fig. 3B, W is the width of the base of BPT, and also the width of the channel formation region of JFET. Here, when W has become larger because of variance during preparation, the amplification ratio β of the BPT becomes smaller due to enlargement of the base width of BPT. However, because the width of the channel formation region of JFET is also enlarged at the same time, the drain current of said JFET, namely the base current of BPT becomes greater to compensate the reduction in the amplification ratio β, whereby the collector current of BPT becomes constant. On the contrary, when W has become smaller because of variance during preparation, the amplification ratio β becomes larger, but the drain current of JFET becomes smaller, whereby the collector current can be made constant. As described above, the constitution shown in Figs. 3A and 3B, and the circuit shown in Fig. 4 can make the collector current value of BPT constant, thereby removing substantially variance occurring during preparation, because the collector current value will not be changed depending on variance of W during preparation. Also, in this example, since the channel formation region of JFET and the base of BPT as well as the gate of JFET and the collector of BPT were made common to each other, respectively, the constitution of the constant current circuit could be simplified, and also the occupied area of the circuit could be made smaller. [Effect] As described above in detail, according to the present invention, a constant current circuit with small occupied area within the integrated circuit as well as good precision can be provided. Therefore, according to the present invention, an analog integrated circuit with small chip size and high reliability can be provided.

Claims: A circuit device comprising a bipolar transistor (Ta) having a collector region (2) of a first conductivity type, a base region of a conductivity type opposite to the first conductivity type and an emitter region (5) of the first conductivity type, and a junction type field effect transistor (Tb) having a gate region (12) of the first conductivity type electrically connected to said collector region (2) and a source region (3) and a drain region of the opposite conductivity type provided in contact with the base region (4) of said bipolar transistor (Ta) with said gate region (12) sandwiched therebetween, characterised in that the collector region of said bipolar transistor and the gate region of said junction type field effect transistor form a continuous region of the same conductivity type and the collector region surrounds the base and emitter regions and the junction type field effect transistor. A circuit device according to Claim 1, wherein said bipolar transistor has a high resistance region of the first conductivity type between said base region and said collector region. A circuit device according to Claim 2, wherein the high resistance region also forms the channel region of the junction field effect transistor. A circuit device according to Claim 1, 2 or 3, wherein at least one of said source region (3) and said drain region is a contact region for the base region (4) of said bipolar transistor (Ta). A circuit device according to Claim 1, 2, 3 or 4, wherein said first conductivity type is n type. A circuit device according to Claim 1, 2, 3 or 4 wherein said first conductivity type is p type.

Inventors: KATAO SHUICHI, KATAO, SHUICHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: G05F3
IPC codes: H01L27, G05F3, H01L21