FABRICATING ELECTRONIC CIRCUITRY UNIT CONTAINING STACKED IC LAYERS HAVING LEAD REROUTING

Abstract: A process and product are disclosed which apply advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers (fig. 1, 20), modification procedures are followed which create IC chips (fig. 4, 38) having rerouted gold leads (fig. 4, 30) on top of passivation (fig. 6, 52) (which covers the original silicon (fig. 6, 48) and its aluminum or other metallization (fig. 6, 44)). The modified chips (fig. 4, 38) are cut from the wafers (fig. 1, 20), and then stacked to form multi-layer IC devices (fig. 10b, 60). A stack has one or more access planes (fig. 10c, 64). After stacking, and before applying gold metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the gold metallization formed on the access planes (figs. 11 and 12). Gold terminal pads (fig. 15, 92) are formed in contact with the terminals of the gold rerouting leads (fig. 15, 66) on the stacked chips, thereby forming gold-to-gold T-connections (fig. 14) for maximum conducting efficiency.

Description: -i- Fabrieating Electronic Circuitry unit Containing Stacked IC Layers Having Lead Rerouting Background of the Invention This invention relates to the use of stacked structures (modules) comprising circuitry-carrying layers (IC chips) ; i.e., each layer has integrated circuitry thereon. Such modules provide very densely packaged electronic circuitry. They may be used whenever space conservation in circuitry is desired, e.g., memory units, logic units. The use of multiple layers in stacked units creates various processing problems, both during the pre-stacking chip preparation, and during completion of the stacked unit, or module. Because it is generally desirable to use IC wafers which are readily purchasable as standard (off-the-shelf) items, the existing on-chip leads require rerouting, in order to permit the eventual stacked unit to function as desired. In prior patents relating to the stacking of IC chips, it has been assumed that chip manufacturers will supply chips having leads suitable for use in stacked modules. Among the prior relevant patents assigned to the assignee of this application are U.S. Patents 4,525,921; 4,646,128; and 4,706,166. The first two listed patents deal with arrangements for avoiding short circuits in the stacked module, and for providing suitable electrical contact points on the access plane(s) of the stacked module, which contact points are available for connection to metallization on the access plane(s) . The third listed patent deals with arrangements for bonding terminals on an access plane of a stacked module to terminals on a supporting, circuitry- providing substrate. Rerouting the leads which are included in commercially available IC wafers has several advantages in the manufacture of stacked chip modules. It also creates new problems. The present application deals with those problems, in order to make those advantages available. The assignee of this application has pioneered the use of stacked chips as focal plane modules having photodetectors on the focal plane. For example, see U.S. Patents 4,551,629; 4,617,160; and 4,672,737. It also has pioneered the use of stacked chips as electronic modules for other fields, such as computer memory devices. There are significant differences between the two fields of use. The use as computer components may not require the extreme closeness of adjacent leads at the access plane; nor does it have the extremely restrictive power limits encountered in cryogenic photodetector enclosures. However,, a major challenge in providing stacked chips which serve as computer components is the zero tolerance of circuit failures. ,In a photodetector surveillance system, a certain percentage of outages (non-functioning circuits) is acceptable. But in a computer component, every circuit must function properly. In the initial stack, extra chips are included to provide redundancy. This permits a limited number of imperfect chips in a completed stack to be disconnected. But the chips which remain in the operating component must have no circuit outages. One of the electrical failure points in stacked chip modules has been the T-connections of the aluminum conductors on the chips with the metallization formed on the access plane. That problem also provides motivation for the present invention. Summary of the Invention The present invention includes both pre-stacking and post-stacking process steps which improve significantly the reliability of stacked chip electronic packages. Also, major commercial benefits are derived from the ability to utilize readily available IC wafers. In the pre-stacking process, the chip leads are rerouted by providing a second layer of metallization formed on a passivation (insulation) layer covering the initial chip circuitry. Major benefits are obtained by using a non-reactive (corrosion resistant) electrical conductor material, e.g., gold, to form the lead re-routing metallization. Gold has numerous advantages over aluminum in the stacked structure, including major improvement in the quality (reliability and conductivity) of the T-connections. The gold T-connections in the stacked structure constitute a marked advance over prior stacked structures. The gold rerouting layer also permits a significant simplification of the pre-stacking process steps. In the stacked chip electronic packages, it is necessary to prevent potential short circuits by eliminating all undesired metallization, including portions of the original aluminum. The present invention avoids several steps at the wafer processing level by using a selective etching step to remove all remaining unwanted metal from the completed stack. Only the desired gold metallization remains in the final layer- containing module. The use of a corrosion-resistant metallization material, i.e., gold, as the conducting material permits easy removal of the undesired material in the stack by a selective etching process performed on the stacked structure. A chemical is used which attacks and removes the undesired material, but does not damage the desired gold metallization. Brief Description of the Drawings Figure 1 is based on a photograph of a vendor-supplied IC wafer having a large number of separate dice, or chips; Figure 2 is based on a photograph showing a close up of a six dice group, which has been modified to provide a single die suitable for use in a stacked layer package; Figure 3 is a diagram of a wafer, on which are identified the one out of every six dice which are modifiable in this particular wafer; Figure 4 shows the layout of an individual modified die after it has been cut out of the wafer; Figures 5-9 are cross-sections (greatly enlarged) taken through a portion of a wafer, and showing the structural details during successive steps in the wafer modification process; Figures 10A-10J are isometric views illustrating successive steps in the previously developed post-stacking steps; Figures 11 and 12 are isometric views illustrating the stack before and after a new etching step which has been inserted into the post-stacking steps; Figure 13 shows a stack of chips mounted on a substrate; Figure 14 is a cross-section taken through a single (one of many) bump bonds between the stack and the substrate; and Figure 15 is a plan view of a T-connection, showing the relative sizes of a rerouted gold lead and a gold terminal formed on the lead. Detailed Description of Preferred Embodiment An important aspect of the present invention is its success in providing a stacked layer electronic unit by improving both pre-stacking and post-stacking process steps. Where IC chips are intended for use in stacked layer units, there are numerous steps needed to prepare the chips for lamination. Also, integrated planning of the end-to-end process (from wafer modification to final electronic stacked unit) provides various functional and processing improvements. In other words, pre-stacking steps can favorably affect post-stacking steps, and vice versa. Figure 1 shows a plan view, taken from a photograph, of one manufacturer's original wafer 20, containing numerous IC chips, or dice, each of which is intended to become a separate chip, or die, 22 when the wafer has been cut along orthogonally-extending streets 24. T -°. dice are tested at the wafer stage, and each failed die is marked with a black dot 26. The material in wafer 20 is silicon, although other IC chip materials may be used, e.g., gallium arsenide. The wafer in Figure 1 has approximately a five inch diameter, and is approximately 0.024 inch thick. A major reason for preferring silicon ships in stacked modules is their relatively high heat dissipation efficiency. For example, silicon is 2 to 3 times more thermally conductive than gallium arsenide. A trade off for the advantages of silicon is the need for electrical insulation of the silicon because it is a semiconductor material having relatively high electrical conductivity. Gallium arsenide, also a semiconductor material, has electrical conductivity 3 or 4 orders of magnitude lower than that of silicon, and therefore is, in relative terms, an electrically insulating material. Where the dice., or chips, are to be used as layers in a stacked structure, several steps should be performed in the wafer stage. Because the desired electronic density in the stack requires extremely thin chips, a thinning of the wafer is performed by removing material from its back surface. Performing the thinning process on individual chips would be extremely difficult, because of their minuteness. The thickness of the wafer 20 will be significantly reduced, e.g., from 24 mils to 4 mils (or less). The wafer 20 is wax mounted face down on a rigid disc whose thickness has been measured to an accuracy of 0.001 mils and shown to be flat to within 0.05 mils. The thickness of the disc is fed into a computer and a calculation is made to give a final thickness of the wafer/disc sandwich which will keep the wafer thickness within a 0.1 mil range. The wafer is then ground to a calculated thickness. After grinding, the wafer is etched to its final thickness. The etching serves two purposes: fine-tuning of the final thickness, and removal of strain induced in the material by the grinding. After demounting and cleaning, the wafer thickness is measured to within 0.001 mil. The thickness data is then fed into a computer stacking program for later use. Before describing the step-by-step wafer modification process, an explanation of the modification goal is in order. Figure 2 is based on a close up photograph of a single die after modification. After forming a passivation (insulation) layer on the front (top) surface of the existing wafer, rerouting leads have been formed, preferably using gold as the material. A plurality of electrically parallel gold leads 30 are shown connecting gold terminals 32 to gold terminals 34. The terminals 32 extend through holes in the passivation layer to make electrical contact with the metal terminals, usually aluminum, formed on the original IC chip 36, which is having its leads rerouted for use in a stacked layer module. At the other ends of the leads 30, new terminals 34 are provided, which will be in electrical (and mechanical) contact with metallization formed on the access surface of the stacked layer module. Thus far, it has been preferable to locate all of the terminals 34 along one edge of the modified chip. However, the rerouting process could be used to bring gold leads to more than one face of the stacked layer module. The rerouting is highly desirable because it permits (a) the use of standard wafers to provide chips for stacking, and (b) the use of gold leads and terminals, which have numerous advantages as electrical conductors over aluminum. As seen in Figure 2, and as diagrammed in Figures 3 and 4, the modified chip taken from the wafer of Figure 1 uses six of the dice included in the wafer. This ratio is subject to improvement as different wafers are developed. In Figure 3, the cross-hatched dice 36a are those which are modifiable, if each modified chip requires six original dice. In Figure 2, the gold rerouting leads are shown crossing over two vertical streets 24a and 24b, and over one horizontal street 24c. Those original die which show black dots in Figure 1 are not usable as IC chips chosen for lead rerouting. Figure 4 shows the shape of a chip 38 which has been cut from the wafer, in order to be used in a stacked chip module. The area of the stackable chip is the entire area of Figure 4, whereas the area of the original chip, whose terminals have been connected to the gold rerouting leads, is that included in the dashed line rectangle 36a. After thinning of the original wafer, and before the rerouting of leads, layers of passivation (insulation) are applied to both the front and back surfaces of the wafer. The front surface passivation is required because additional rerouted electrical conductors are to be formed above the existing IC circuitry. The back surface passivation is required because each layer (chip) will be next to the electrical conductors formed on the layer below. Choosing the passivation material(s) presents certain problems. The insulating layers are chosen on the basis of: their electrical insulating properties; their mechanical properties - which include strength, porosity, etc. ; their method of deposition; and their ease of delineation. There are a number of insulating thin film materials that are used in the semiconductor device industry. Primary materials are silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass, and various polyimides. Silicon nitride (SiN) and silicon oxynitride (SiON) are probably the best all around materials, based upon mechanical strength, humidity barrier, etching qualities, and ease of deposition. Of these two materials, silicon nitride is more difficult to etch and tends to have greater built-in stress as a result of the deposition chemistry. Stress in silicon nitride can be controlled to some extent by choice of deposition parameters. However, stress fracture at geometries below 2 microns may be a problem for silicon nitride films. But it is not a problem for silicon oxynitride. Silicon nitride is, however, risk free on the back (bottom) of the wafer. Another consideration of interest in choosing between SiN and SiON is their etch rates. SiON etches eight times faster than SiN in buffered oxide etch (7:1). When buffered oxide etchant is used to remove unwanted passivation, the great difference in etch rates allows full etching of the SiON on the top surface of the wafer, while SiN thickness on the bottom is reduced only by about 12%. If the starting thickness of both insulation layers is approximately the same, removal of the SiON from selected locations on the top surface will leave the SiN on the bottom surface largely intact. By using SiON as the insulation layer on the front surface (i.e., the device-carrying surface) of wafer 20, and SiN as the insulation layer on the back surface of wafer 20, synergistic benefits are obtained. The fracture safe SiON is used where that characteristic is of value; and the relatively etch-resistant SiN is used where that characteristic is ,of value (because adequate passivation remains on the entire back surface, _ while being fully removed in selected locations on the front surface) . Figures 5-9 show the changes in a small segment of the wafer cross-section as subsequent modification steps are taken. Figure 5A provides a guide to the drawing symbols used to identify the different materials shown in Figures 5- 9. Figure 5 shows the wafer cross-section before any modification. The silicon body of the wafer is indicated by numeral 40. Streets 24e and 24f provide, the cutting lines along which three dice - 22a, 22b and 22c - would have been separated if the modification steps were not used. The arrows between the dashed lines show the width of the modifiable center die 22b. A device area on the upper surface of die 22b is indicated by a bracket having the numeral 42. Aluminum (Al) metallization indicated by numeral 44 is used to provide conductors which connect the IC device area 42 to the terminals at which the chip will be connected electrically to exterior circuitry. A first layer 46 of silicon dioxide (Siθ2) is shown below the aluminum metallization 44; and a second layer 48 of silicon dioxide is shown above the aluminum metallization 44. The Siθ2 provides protection and insulation for the wafers supplied by the vendor. Openings 50 provided in upper layer 48 of Siθ2 are available for connecting metallic conducting material which will contact the aluminum 44, and will thus provide terminal pads for connection to exterior circuitry. As discussed above, and as shown in Figure 6, a layer 52 of silicon oxynitride (SiON) is deposited over the entire upper (device) surface of the wafer; and a layer 54 of silicon nitride (SiN) is deposited over the entire lower surface of the wafer. Deposition of the insulating films 52 and 54 may be performed by plasma-enhanced chemical vapor deposition (PECVD) at 380'C in gas mixtures of silane, nitrous oxide, nitrogen, ammonia and argon. The exact mixture is dependent upon which of the two films is being deposited. The plasma-enhanced chemical vapor deposition (PECVD) is used instead of chemical vapor deposition (CVD) because PECVD is performed at 380 » C, whereas CVD is performed above 700'C. Since the eutectic temperature of aluminum-silicon is 577'C, the CVD temperature would be destructive. Above 450'C, silicon is readily dissolved in aluminum, moving rapidly along aluminum grain boundaries, and precipitating out of solution some distance from the dissolution site. The thickness of the insulation films 52 and 54 must be carefully chosen. The SiON film 52 should be thick enough to prevent cross-talk between the aluminum conductors below the film and the gold conductors above the film. However, excessive thickness of film 52 may cause stress on the metallic conductors. The presently preferred film thicknesses are about 1.0 micron for the SiON film 52, and about 1.1 micron for the SiN film 54. A reason for the slightly greater initial thickness of the lower surface film 54 is that it will be subject to etching while the desired openings in the upper surface film 52 are being formed by etching. Figure 7 shows the wafer cross-section after performing selective etching to form certain openings in the SiON layer 52. New streets 56 and 58 are formed in the adjacent dice 22a and 22c, respectively. And the SiON film is removed from the openings 50, into which metal will be deposited to provide conductor terminals. Prior to etching, a photolithographic process is used to permit etching only where desired. The entire surface of the SiON passivation is covered with a layer of photoresist. Then a mask is placed over the photoresist, and the uncovered portions of the photoresist are subjected to ultraviolet radiation. If the photoresist is positive, the areas in which the SiON is to be removed will be those defined by the holes in the mask. Those areas are then left unprotected by removing (dissolving) the photoresist, i.e., at the new streets 56 and 58, and at the terminal openings 50. Then the wafer is placed in a buffered oxide etch (BOE) , in which the SiON in the unprotected areas is removed. Silicon ,is not etched by the BOE. The etching time to remove passivation is carefully controlled to avoid undercutting. Witness wafers may be used for such control. They are wafers which were covered with SiON along with the wafers being modified. Since a witness wafer will have the same SiON thickness as its companion modified wafer, the time required to etch the latter can be determined by etching the former. The passivation films (SiON and SiN) are hydrophilic. Bare silicon (the wafer body) is hydrophobic. The latter property is used as the end point indicator for the etching reaction; i.e., when hydrophobia starts, the film has been completely etched. The undeveloped photoresist limits etching of the passivation to the desired locations. After the etching is completed, the photoresist is removed by a solvent. At this point, the cross-section of the wafer is as shown in Figure 7. Except for the terminal openings 50 and the new streets 56 and 58, the front wafer surface is covered by a layer 52 of SiON about 1.0 micron thick. During the BOE etching, the thickness of SiN layer 54 was reduced slightly. But its etching rate was only about one-eighth or the etching rate of the SiON. So the passivation layer 54 remains sufficiently thick after the BOE etching. Figure 8 shows the wafer cross-section after deposition of a field metal layer, then plating-up of the gold leads, and finally removal of the undesired portions of the field metal layer. The initial field metal layer covers the entire surface of the wafer, and acts as an electrical conductor during the gold plating process. A very thin layer of field metal is first deposited over the entire front surface of the wafer. This field metal layer consists of a coating of titanium-tungsten (Ti-W) alloy, followed immediately by a coating of gold (Au) . The Ti-W and Au materials are deposited by a sputtering process, which is continuous, i.e., deposition of the Ti-W and of the Au is accomplished during the same sputtering run. The Ti-W alloy has excellent adhesion to both the oxide and metal surfaces that it covers, and it also makes good electrical contact. Because any exposed aluminum tends to form an oxide, just prior to sputtering on the field metal, a light sputtering etch is carried out, in order to remove aluminum oxide, which would have an insulating effect. Gold, which does not oxidize, does not adhere well to an oxide. Its inclusion in the sputtering run prevents formation of an oxide on the surface of the Ti-W alloy. Subsequently, the gold leads will be built up (thickened) by electro-plating additional gold on the initial gold coating until the gold reaches a thickness of approximately 2.5 microns. This is done after photoresist is applied to cover the field metal, except where gold leads are desired. The dimensions and routing of the metallization which provides the gold rerouting leads have been chosen to minimize both resistance and capacitance. Gold is preferred for its low electrical resistance, electroplating ease, and chemical inertness, especially because it does not form an oxide. This latter property means that it is expected to have low electrical contact resistance, but poor adherence to oxide-like surfaces. That shortcoming is overcome by the use of an adhesion metal beneath the gold, such as titanium, aluminum or, better, the titanium-tungsten alloy. Metals other than gold may be used instead of gold, if the trade-off is considered desirable in a given situation. In other words, persons skilled in the art will readily perceive that it may be preferable to use, as material for the rerouting or extending leads, a material having certain characteristics which are better than aluminum, but inferior to gold, if other characteristics of such material provide an attractive trade-off relative to gold. The primary disadvantages of gold are (a) its high cost; (b) the special efforts needed to cause it to adhere to certain materials; and (c) its undesirable property as a recombination center in silicon. The latter characteristic is due to the position of gold in the band gap in silicon, which makes gold a potential destroyer of carriers, under the influence of high processing temperatures, such as those used in diffusion and in thermal oxidation. As stated in this application, the favorable characteristics of gold include (a) its excellent electrical conduction both in the rerouted or extended leads and at the T-connections, (b) the ease of thickening it by plating, and (c) its resistance to etching when aluminum is removed after stacking. The non-oxidizing nature of gold, and its relative chemical inertness, contribute to its favorable characteristics. Other metals, such as copper, silver, nickel, and/or their various alloys, may in some cases provide desirable trade-offs relative to gold, because they will provide, to a significant extent, its favorable qualities, while they will avoid, to some extent, one or more of its disadvantages. The resistivity figures for the metals referred to are, in the order of highest conductivity: silver 1.59, copper 1.67, gold 2.35, aluminum 2.65, and nickel 6.48. Photolithography is used to delineate the paths of the plated gold leads. The entire field metal coating is covered with photoresist. A mask is then used having openings which define the terminals and the desired paths of the rerouted gold leads. After removing the photoresist from those lead-defining paths, an electroplating process is used to build up the gold thickness of the rerouted leads. The entire wafer is put into a gold plating bath, in which the electrical current is provided via the field metal coating. Next, the field metal layer is removed (except for the rerouted leads) by first dissolving the remaining photoresist, and then briefly placing the wafer in successive etching materials which remove the thin field metal coating. A first etchant is used for the thin gold layer and a second etchant for the thin Ti-W layer. Each etchant is used for a very short period. The gold etchant also removes some of the plated gold of the rerouted leads, but not enough to affect the conducting efficiency of the leads. Gold is one of the most corrosion (etching) resistant metals, but it can be removed by suitable etchants. For example, the gold etch which has been successfully used in the present process contains potassium (K) , iodine (I) and water, in the proportions of 113 grams of K, 65 grams of I, and 100 cc. of water. A satisfactory etch for the Ti-W layer is hydrogen peroxide (H2O2) at 45*c. The etchants used to remove the field metal do not remove either the passivation material or the aluminum. At this point the cross-section corresponds to Figure 8. The thick gold leads 30 (see also Figures 2 and 4) have gold terminals 32 which are in electrical contact with the aluminum metallization 44. The rerouting gold leads 30 extend from the terminals 32 to the new terminals (34 in Figures 2 and 4) which will be in electrical contact (by means of T-connections) with metallization (gold) applied to the access surface of the stacked module into which the modified chips have been incorporated. Note that the new gold leads pass through the streets 24e and 24f in the original wafer. Figure 9 shows the wafer cross-section of the modified die, which is ready to be cut out of the wafer and then placed in a stacked module. The only change from Figure 8 to Figure 9 is the removal of the aluminum 44 from the new streets 56 and 58. This removal may be accomplished b exposing the wafer to an aluminum-only etching material containing phosphoric acid and nitric acid. This etching material attacks the aluminum, but does not attack the gold leads, the passivation layers, or the silicon. Subsequently, after wafer testing, the modified dice (chips) are cut out of the wafer, cutting along the lines provided by the new streets (56, 58, and the orthogonal streets) . A modified chip, ready for stacking, is shown in Figure 4. In addition to the gold rerouting leads, the modified chip has four spacer pads 59 which engage the next layer after stacking. Two of the pads, located at the chip edge having lead terminals 34, are triangular. This shape later permits depth of lapping of the edge to be determined by measuring the width of the triangular pads. The stack building steps are then performed, using the chips provided by the modified dice. The particular laminating process is not part of the present invention. One such process is described and claimed in common assignee Pat. No. 4,617,160. Generally, the chips of a stack are (a) selected in accordance with precise thickness measurement; (b) stacked in a fixture which holds them in alignment; (c) provided with a measured amount of adhesive (epoxy) between each pair of adjacent chips; and (d) heated to cure the epoxy and create a solid stack. One advantage of the present invention, which improves the stacking process, is the ability of the relatively thick plated gold terminals on each chip to act as supplemental spacers between adjacent chips, thus helping to insure glue (epoxy) lines in the stack which have consistent (and very slight) thickness. Controlling the thickness of the glue lines, in order to maintain accurate lead spacing in one of the two access plane dimensions, has been a problem in stacked chip modules. After forming a laminated stack of chips, several process steps are required to prepare the terminals on the access plane of the stack. Figures 10A-10J are isometric views illustrating successive steps, which lead to the completion of the stacked chip module ready for attachment to a carrier substrate. Those post-stacking process steps are disclosed and claimed in common assignee Pat. No. 4,525,921. Figures 11 and 12 illustrate a new step, inserted into the process, which is a significant part of the present invention. Referring first to the previously patented process. Figure 10A symbolizes the multiple steps leading to the laminated stack 60 of Figure 10B, which consists of a plurality of glued together chips 62. Each chip 62 is a complete IC chip, having a multiplicity of parallel integrated circuits, each circuit having its own lead which terminates (see Figure IOC) at the access plane 64 of the stack (shown as the top plane) . Figure IOC represents the lapping and polishing step, which removes silicon to expose the multiplicity of leads 66 seen in Figure 10D. Note that the leads 66 form a two-dimensional pattern. The spaced leads on the edge of a single chip are considered to extend along the X-axis. The Y-axis dimension includes the aligned leads on separate chips, whose spacing is determined by the thickness of the chips. Figure 10E shows a chamber 68, used in a plasma etching step, which removes silicon, epoxy, and insulation materials from the access plane of the stack, leaving the metal leads 66 protruding from the access plane 64 of the stack, as seen in Figure 10F. The plasma etching is performed only on the access plane surface (or surfaces) of the module. A flash etch step may be needed to remove any remaining silicon oxide (Siθ2) from the access plane. This is accomplished by very briefly exposing the module to hydrofluoric acid. Figures 11 and 12 disclose a significant aspect of the overall process which is part of the present invention. They represent a step performed between Figures 10F and 10G. A single step performed on the stacked module accomplishes what either (a) would not be feasible, or (b) would require multiple steps and much more complexity if performed prior to formation of the stack. As a consequence of the requirement to extend the rerouted gold signal leads (30 in Figure 2) outside the area of the active (original) die, a selective metallization removal is necessary before placing the T-connection metallization on the access plane of the module. The aluminum metal 67 removed at this stage is in the dice adjacent to the modifiable die. It lies beneath the extended gold leads (or in a plane below the gold lead plane) and it has been exposed (along with the gold leads) by the plasma etching of the silicon. Initially, it was planned to remove this aluminum at the wafer level, but such removal would have required many more processing steps, and would have degraded performance. By performing the removal after all the chips have been stacked in the module (module level) , the metal removal is accomplished for all the chips at one time. If this spurious, unwanted original metal is not removed, there is a possibility of shorting between the various signals of the active chips in the module. The process that was developed is removal of the spurious aluminum metal using a selective chemical etch solution (H 3 Pθ4:HNθ 3 :H2θ) . This process is performed after the silicon etch procedure (Figure 10F) has been performed on the stacked module. The special chemical solution removes only the unwanted aluminum metal, while not affecting the gold leads of the module. In Figure 11, there is a mixture of unwanted aluminum metal 67 with the gold signal leads 66. Figure 12 shows the gold signal leads 66 still protruding, while the unwanted aluminum metal has been removed. Next, in accordance with the prior process, the access plane is covered with a passivation layer 70, as shown in Figure 10G. The preferred passivation material is polyimide. assivation is required to insulate the metallic conductors from the silicon body of the stack. After the polyimide is applied, the metal leads need to be re-exposed. Figure 10H shows another lapping and polishing step which uncovers the gold leads without removing the surrounding polyimide insulation. Figure 10J shows the re-exposed leads 66. And Figure 10K shows metallization deposited on top of, and in electrical contact with, the leads 66. In the process of applying this metallization, metallic busline strips 72 are laid down, and also metallic chip select pads 74. Beneath the strips 72 and pads 74 are terminal pads which contact the exposed leads 66, and which have larger areas than the leads 66. These junctions are referred to as "T- connections", because the leads and pads meet at right angles, and because each pad extends across and beyond the ends of its lead 66. The metallization seen in Figure 10K preferably is applied in a plurality of layers, as detailed below. Both Ti-W and Au are used in order to obtain maximum electrical conduction and effective adhesion at the contact areas. In the presently preferred version of the invention, the completed stack, as shown in Figure 10K, has its conductors (metallization) all on access plane 64. Some of the conductors are shown as bus lines, and some as rectangular terminal pads. The access plane then has its conductors connected to external circuitry in any preferred manner. For example, as disclosed in common assignee Pat. No. 4,706,166, the access plane may be placed face down on a substrate face having electrical conductors which provide routing of signals between the stack circuitry and external circuitry. Suitable insulation is formed between the substrate and the access plane of the stack; and bonding bumps serve as connections between terminals on the substrate and terminals on the access plane. Other external circuitry connecting schemes are available. Figure 13, which is similar to Figure 5 of Pat. No. 4,706,166, shows a substrate 80 having mounted thereon a stack 82 containing numerous chips 84, each of which extends in a plane perpendicular to substrate 80. Both electrical conductivity and thermal conductivity are provided by soldered bumps between terminals on the stack and aligned terminals on the substrate. If necessary, extra heat conducting (but not current conducting) bumps can be used to enhance heat dissipation. In circuitry packed as densely as that in the stacked IC chips, heat transfer is a major consideration. Heat dissipation in the range of 40-100 watts can be accomplished with silicon chips which have effective heat transfer to and through the substrate 80. A stacked chip module can have more than one access plane, if the chips extend in planes parallel to the substrate. In such an arrangement the chip conductors could lead to more than one edge of each chip; and electrical conductors could be brought down the sides of the module to contact conductors on the substrate. The present invention is applicable to such an arrangement. One problem with that concept, if semiconductor chips are used, is that more extensive electrical insulation between the stack and the substrate would also tend to create thermal insulation. Another potential problem is providing adequate electrical contact at the substrate/stack interface. In other words, the T-connection arrangement would not be readily available. Figure 14 is a greatly enlarged close up showing successive layers of material which provide one bump bond between the stack and the substrate. The dimensions are not intended to be proportionally accurate. The metallic layers applied to the access plane of the stack are all applied by a sputtering process. One of the gold rerouting electrical leads 66a is shown terminating at 66b, where it extends to the lower surface of an insulation layer 86 of polyimide material. The polymide layer 86 may be approximately 3.0 microns thick. The gold conductor 66a has a thickness of about 2.5 microns. Power conductor gold leads may be 10 mils wide. Other gold leads may be 5 mils wide at their terminals, and 2 mils wide between terminals. (1 mil equals 25.4 microns). The conductor 66a is one of numerous such parallel conductors located between two silicon chips 88a and 88b. (The SiON and SiN insulation layers on the chips are not shown) . Building up the bumps on the stack for bonding to a silicuii substrate 102 involves numerous steps. Building up matching bumps on the substrate 102 also involves numerous steps. Eventually the matched, aligned bumps will be soldered together under heat and pressure. Primary emphasis is given in this description to the metallization on the access plane of the stacked chips. There are, in effect, three metallization patterns formed on the access plane. The first is pad metallization, which provides pads used for testing purposes. The second is busline and chip-select metallization, which is formed on top of the first metallization. If testing the first pad metallization indicates any defective chip(s) , a layer isolation process is performed. Using photoresist and a mask, the metal pads protruding from the failed chip(s) are etched back, and then covered with polyimide. The first metallization applied is one consisting of 0.005 by 0.010 inch pads and 0.010 by 0.010 inch pads. The larger pads are placed on Vcc and Ground lead ends. The pads have a thin initial layer 90 of sputtered titanium-tungsten alloy to provide good adhesion and low electrical resistance to the gold lead ends 66b, and also to provide good adhesion to the surrounding polyimide. The Ti-W thickness is about 0.2 micron. A much thicker (about 1.0 micron) gold layer 92 is deposited upon the Ti-W. This pad metallization allows electrical inspection of individual chips after the stacking process. The T-connect structure (intersection of two perpendicular planes of metal) is further illustrated in Fig. 15. Two pads 92 are shown. Each pad contacts a lead 66, which is the end of a conductor extending fro the interior of the stack of chips. The lead 66 is perpendicular to its pad 92.A line 120 represents th planar engaging surfaces of two adjacent chips. Th area of each pad 92 is substantially larger than th lead 66 which is joined to it; and the full conductiv cross-section of each lead 66 is in electrical conductin contact with its pad 92. Their perpendicula engagement, and the sputtering of the gold pad materia into contact with the gold lead material insures a effective conductive bond. The gold T-connections replace aluminum T-connection used in prior developments. The advantages of gold T connects are extensive. Aluminum T-connects have problems of brittleness, uneven edges due to corrosion, poor conductivity due to oxide formation, and lack of cross- sectional thickness. Gold T-connects solve all of these problems, and result in major performance improvements. In fact, gold T-connects appear to have conductivity which is 2 to 3 orders of magnitude better than aluminum T-connects. The second metallization consists of pads and buslines. Except for the chip select pads 74 (Fig. 10K) , the pads 92/94 are connected from one chip to the next by the buslines 72 (Fig. 10K) . For those pads not connected by buslines, a second pad layer is applied, in order to maintain equal height throughout the stack. Since buslines must also cross stack regions of nonmetallized polyimide, a thin (0.2 micron) adhesion metal layer 94 of Ti-W alloy must precede the thicker (1.0 micron) gold layer 96. The third, and final, metallization is the solder pad metallization. The relatively thick gold layer 96 is followed by a thin (e.g., 0.2 micron) layer 98 of a barrier metal (e.g., nickel), followed by a thicker (e.g., 2 micron) layer 100 of tin/silver (Sn:Ag, 96.5:3.5%) solder. A dashed line 101 represents the engaging surfaces of solder bumps on the access plane of the stack with solder bumps on the substrate 102. As already indicated, the preferred process in applying metallization to the access plane (or planes) of the stack is sputtering, which is particularly successful in forming highly conductive T-connects. A less attractive alternative is use of deposition by evaporation. In controlling the metallization pattern to provide fine delineation, two possibilities are: (a) etch delineation and (b) lift-off. Etch delineation requires the use of chemical etchants; and where a plurality of metals are to be etched, a plurality of etchants must be used. This has major inherent difficulties. So the lift-off method is preferred. The lift-off method applies photoresist prior to metal delineation. Broadly the lift-off process includes: (a) covering the surface with photoresist, (b) masking the photoresist to provide the metallization pattern, (c) developing the exposed photoresist, (d) dissolving the exposed photoresist to uncover those portions of the access plane which provide the desired metallization pattern, (e) applying metal to the entire surface, and (f) dissolving the remaining photoresist, which carries along with it the metal not included in the metallization pattern. In order to minimize bridging between the retained and removed metal, a two-stage lift-off process is used. A first layer of photoresist is applied to the entire access plane. This entire layer is only briefly exposed to ultraviolet light. Then a second layer of somewhat different photoresist is applied the access plane. A mask is used to delineate the exposed (and developed) portions of the second layer of photoresist. After the second exposure, the photoresist is removed. By using two layers of photoresist and two exposures to develop the photoresist, a slight photoresist overhang is produced in the areas where metal is to be deposited. This creates discontinuity of the sputtered metal. The sputtering process is first used to apply the thin layer 90 of titanium-tungsten (Ti-W) to the access plane; and it is then used to apply the much thicker layer 92 of gold (Au) on top of layer 90. Layer 92 is a gold terminal pad in the first metallization stage. The Ti-W is necessary to provide adhesion of the gold layer to the polyimide, while at the same time providing electrical conductivity which maintains the full electrical contact efficiency of the gold-to-gold T-connection (i.e., 66b to 92). Suggested thicknesses of layers 90 and 92 are 0.2 micron and 1.0 micron, respectively. After testing the terminal pads 92, and isolating any defective chips, the second stage of metallization is applied. Like the first stage, it comprises the thin (0.2 micron) layer 94 of Ti-W, and the thicker (1.0 micron) layer 96 of Au. These layers are also applied by sputtering. Because the first stage has rectangular pads, and the second -22- stage primarily has elongated buslines, the first and second stages require separate photoresist lift off patterns. Also the busline gold deposited will be thicker in the spaces between the first stage terminal pads. 5 The third stage of metallization also requires a photoresist lift off pattern; and also comprises two layers. The mask used in the first pad deposition may be used. A thin (0.2 micron) layer 98 of nickel (Ni) is sputtered on. And then the thicker (1.5 micron) layer 100 of solder 10 (tin/silver) is sputtered on. The layer of Ni is required to prevent leaching of the gold into the solder when heat is applied .to bump bond the solder bumps on the stack to the solder bumps on the substrate. As previously stated, suitable tin/silver composition of solder bumps 100 is 96.5 15 Sn/3.5 Ag. The lower portion of Figure 14 shows the material layers on the substrate. The silicon substrate 102 carries a top surface passivation layer 104 of SiON (about 1.0 micron thick) , and a bottom surface passivation layer of SiN 20 (about 1.0 micron thick). A gold conductor 108 leads into a much thicker gold terminal pad 112. Above pad 112 is a thin (about 0.2 micron thick) Ni layer 114. And above layer 114 is a tin/lead solder bump 116. A suitable composition of the tin/lead solder bumps 116 is 63 Sn/37 Pb. When the 25 aligned solder bumps 100 and 116 are engaged with one another (see line 101) under suitable heat and pressure, the stack of chips is effectively secured to the substrate mechanically, and each pair of engaging solder bumps provides an electrical and/or thermal path. The resulting 30 electronic module has extremely dense circuitry (e.g., a terabit of memory in a volume less than one cubic foot) , combined with very effective heat dissipation. Because of the effective heat conduction of silicon, and the high bump density at the access plane/substrate interface, this module 35 can dissipate 100 watts of heat or more, depending upon the heat sink which is used. The solder bump bonding, therefore, is not only vital as an electrical interface, but as a heat dissipation path. In fact, in some instances, extra bump bonds may be added solely as heat conductors (without electrical conduction) . From the foregoing description, it will be apparent that the apparatus and method disclosed in this application will provide the significant functional benefits summarized in the introductory portion of the specification. The following claims are intended not only to cover the specific embodiments and methods disclosed, but also to cover the inventive concepts explained herein with the maximum breadth and comprehensiveness permitted by the prior art.

Claims: -24- What Is Claimed Is: 1. A method of forming a dense electronic package comprising: modifying a wafer having multiple IC chips formed thereon, each chip having metallization forming I/O terminals; adding a layer of passivation over the active surface of the wafer; forming a plurality of rerouting electrical conductors on top of the passivation layer, such conductors (a) being formed of metallic material which is more chemically inert and easier to electroplate than the chip metallization, and (b) each extending between a first I/O terminal lead in contact with a chip I/O terminal and a second I/O lead terminal available for external electrical " I/O connection; cutting from the wafer a plurality of individual IC chips, each having a plurality of rerouted conductors and each having its second I/O terminal leads accessible for external connection; integrating a plurality of such IC chips in a stack which has at least one access plane on which the second I/O terminal leads of the rerouting electrical connectors are exposed; forming a plurality of terminal pads on the access plane, each pad (a) being in electrical contact with one of the access plane I/O terminal leads in the form of a T- shaped connection, and (b) being formed of the same metallic material as that of the electrical conductor which it contacts; and connecting the access plane terminal pads to exterior circuitry. 2. The method of claim 1 in which: the metallic material which forms the rerouting conductors and their T-connection lead/pad terminals is gold. 3. The method of claim 2, which also comprises: electroplating the gold rerouting electrical conductors to substantially increase their thickness and thus their conductivity. 4. The method of claim 2, which also comprises: forming a thin layer of an adhesive metal between each gold surface and non-gold surface, in order to provide adhesion of the non-oxidizing gold to the other surface. 5. The method of claim 4, in which: the adhesion metal is titanium/tungsten alloy. 6. The method of claim 1 which also comprises: removing, from the access plane of the stack, material of the IC chip edges, in such a way as to leave protruding from the access plane the metal I/O terminal leads formed by the rerouting electrical conductors; selectively etching to remove any metal other than that of the rerouting electrical conductors; and applying a layer of passivation to cover the access plane except where I/O terminal leads are exposed. 7. The method of claim 6, in which: the protruding leads comprise aluminum in the original wafer and non-aluminum metal leads provided by the rerouting electrical conductors; and the selective etching removes the aluminum, but not the other metal. 8. The method of claim 1 in which: the layer of passivation added over the active surface of the wafer is silicon oxy-nitride. 9. The method of claim 8, in which: -26- the layer of silicon oxy-nitride is formed by plasma- enhanced chemical vapor deposition. 10. The method of claim 8 which also comprises: adding a layer of silicon nitride passivation over the non-active surface of the wafer. 11. The method of claim 10 which also comprises: subjecting the wafer passivation to an etching in which._ desired openings are formed through the silicon oxy-nitride passivation without significantly reducing the thickness of the silicon nitride layer. 12. The method of claim 2 in which: the terminal pads on the access plane which form T- shaped connections with the rerouting conductors are formed by means of a sputtering process. 13. The method of claim 12 in which, the terminal pad forming process comprises: first sputtering a layer of pad-shaped adhesive material on top of each access plane I/O lead; and then sputtering a layer of gold on top of the adhesive material. 14. A dense electronic package comprising: a stack of layers, each of which contains IC circuitry, said stack having an access plane for I/O electrical connections, a two dimensional array of gold leads exposed on said access plane, each such lead being electrically connected to IC circuitry; an array of gold terminal pads on said access plane, each pad forming an electrical T-connection with one of the gold leads; and exterior circuitry connected to the gold terminal pads. 15. The dense electronic package of claim 14, which also comprises: a substrate adapted to be mechanically and electrically connected to the layer-containing stack; an array of solder bumps on the access plane, each having electrically and thermally conductive connection with one of the gold terminal pads; and an array of solder bumps on the substrate, each having electrically and thermally conductive connection with one of the solder bumps on the access plane. 16. The dense electronic package of claim 14 in which: the layers in the stack are silicon chips; and the silicon in such chips is fully insulated from the gold leads. 17. The dense electronic package of claim 15 in which: the layers in the stack are silicon chips; and the silicon in such chips is fully insulated from the gold leads.

Inventors: GO TIANG C, MINIHAN JOSEPH A, SHANKEN STUART N, GO, TIANG, C. +DI, MINIHAN, JOSEPH, A., SHANKEN, STUART, N.
Applicants: IRVINE SENSORS CORP, IRVINE SENSORS CORPORATION
Application year: 1990
Main classification: A01D34
IPC codes: H01L23, H01L25