Semiconductor memory device

Abstract: A semiconductor memory device comprises a memory cell array (1), a row decoder (2) connected to the memory cell array by a plurality of word lines for selecting a word line in response to a first address signal supplied thereto, a column decoder (13) connected to the memory cell array by a plurality of bit lines for selecting a bit line in response to a second address signal supplied thereto, and a data discrimination unit (4) connected to the column decoder by a common data bus for producing an output data signal indicative of the data stored in the addressed memory cell. The the column decoder (13) includes a plurality of sense amplifiers (41 - 44) each connected to a corresponding bit line for selecting an addressed bit line, the plurality of sense amplifiers being connected to a common data bus (49, 52) for transferring data stored in the addressed memory cell, and a plurality of switching devices (50, 53) provided in correspondence to the plurality of sense amplifiers for selectively transferring the data detected by the sense amplifier to the common data bus, wherein each of the switching devices includes a bipolar transistor (50, 53) having a collector connected to a power voltage source, an emitter connected to the common data bus (49, 52), and a base connected to the corresponding sense amplifier for receiving the output signal of the sense amplifier indicative of the data.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor memory devices and more particularly to a semiconductor memory device having an improved access time. In semiconductor memory devices, delay at the time of reading or writing data is caused by various reasons. Among others, contribution of peripheral circuits occupies a significant part. It should be noted that the delay caused by the peripheral circuits is much larger than the delay caused by the memory cell itself. Such peripheral circuits include sense circuits and decoders. FIG.1 shows a construction of a typical conventional semiconductor memory device. Referring to FIG.1, semiconductor memory device comprises a memory cell array 1 including a number of memory cells 1a arranged in a row and column formation, a row decoder 2 connected to word lines WL for addressing a memory cell 1a connected to one of the word lines in response to an address signal ADDRESS1 supplied thereto, a column decoder 3 acting also as a sense circuit as well as a write circuit, connected to bit lines for addressing a memory cell 1a connected to a pair of addressed bit lines BL and BL in response to another address signal ADDRESS2. Further, an output buffer circuit 4a and a read write control circuit 4b are provided for reading data from the addressed memory cell and writing data to the addressed memory cell respectively. FIG.2 shows a construction of the circuit 3 in detail. Only the part of the circuit 3 which is used for reading the data is illustrated. Referring to FIG.4, a number of sense amplifiers 11 - 14, each comprising a transistor 5 and a transistor 6, are connected to corresponding pairs of bit lines BL1 and BL1 , BL2 and BL2 , BL3 and BL3 , and BL4 and BL4 and so on. Further, there are provided a common data bus pair 8 and 9 wherein the data bus 8 is connected commonly to the collector of the transistor 5 forming the sense amplifiers 11 - 14 and the data bus 9 is connected commonly to the collector of the transistor 6 also forming the sense amplifiers 11 - 14. The buses 8 and 9 are connected to the output buffer circuit 4a which is a sense amplifier for detecting the difference in the current flowing through the buses 8 and 9. In response to the detected difference, the output buffer circuit 4a produces a data signal at an output terminal D OUT . FIG.3 shows a construction of the output buffer circuit 4a used for detecting the difference in the current between the bus 8 and the bus 9. As can be seen from FIG.3, the output buffer circuit 4a comprises a differential amplifier 4a′ having a well known construction and produces a high level output at the output terminal D OUT when the voltage level on the bus 8 is higher than that on the bus 9. Otherwise, the amplifier 4a′ produces a low level output at the output terminal D OUT . As the construction and operation of such a differential amplifier is well known, further description thereof will be omitted. Each of the sense amplifiers 11 - 14 includes the transistor 5 and the transistor 6 wherein the transistor 5 having the collector connected to the bus 8 has a base connected to the bit line BL and an emitter connected, commonly to the emitter of the transistor 6, to a current source 7. Similarly, the transistor 6 having the collector connected to the bus 9 has a base connected to the bit line BL and an emitter connected, commonly to the emitter of the transistor 5, to the current source 7. The current source 7 is selectively turned on in response to a column select signal which is produced by decoding the address signal ADDRESS2 by a decoding unit 3a shown in FIG.4. FIG.4. shows the construction of the current source 7 in more detail. Referring to FIG.4, the current source 7 comprises a field effect transistor connecting the emitters of the transistors 5 and 6 to the ground. The transistor 7 has a gate to which the column select signal produced by the decoding unit 3a is supplied and the transistor 7 is turned off and turned on in response to the address data ADDRESS2 supplied to the decoding unit 3a. Thus, when the sense amplifier 1 is selected in response to the turning on of the current source 7, a current may be caused to flow either from the bus 8 to the current source 7 through the transistor 5 or from the bus 9 to the current source 7 through the transistor 6 depending on the content of information stored in the selected memory cell 1a. Thus, when there is a high level state in the bit line BL1, a current is caused to flow from the bus 8 to the current source 7 through the collector and emitter of the transistor 5. In correspondence to the high level state in the bit line BL1, a low level state appears in the bit line BL , and flow of the current through the transistor 6 is prohibited. Thus, there appears an inequality in the current flowing through the bus 8 and the bus 9, and this inequality of the current is detected by the sense amplifier 4a. When the high level state is on the bit line BL and the low level state on the bit line BL , on the other hand, a reversed situation appears such that the current flows from the bus 9 to the current source 7 through the transistor 6 while flowing of the current through the transistor 5 is prohibited. Although such a so-called "collector dot" construction of the memory device is effective in reducing the delay of the decoding circuit, there still remains a problem in that the response of the memory device is not satisfactorily fast. FIG.5 explains the reason why a satisfactorily quick response cannot be obtained in the foregoing construction. Referring to FIG.5 showing the cross-sectional view of a transistor used for the transistors 5 and 6, the transistor has an n⁺-type buried collector layer 22 provided on a p-type substrate 21, and an n-type collector layer 23, p-type base layer 24 and an n-type emitter layer 25 are provided on the buried collector layer 22. Further, it will be seen that the transistors are isolated from each other by an isolation structure 26 forming a p-n junction. Although such transistors are easy to fabricate with reduced number of fabrication steps, there is a problem that a large capacitance appears at the boundary between the substrate 21 and the buried collector layer 22 forming a p-n junction and at the boundary between the collector layer 23 and the base layer 24 also forming a p-n junction. It should be noted that junction between the substrate 21 and the collector layer 22 or the junction between the collector layer 23 and the base layer 24 has a substantial area. Because of this, there appears a substantial capacitance such as C sub or C CB at the collector of the transistors 5 and 6. Such a capacitance at the collector of the transistors 5 and 6 connected to the buses 8 and 9 inevitably causes a delay at the time of reading the data and the access characteristic of the memory device is deteriorated. It should be noted that these parasitic capacitance connected parallel with each other to the bus 8 or 9 can cause a significant delay at the time of operation of the memory device. Such a parasitic capacitance may be reduced by using the isolation structure formed of grooves as shown in FIG.6. Referring to FIG.6, there are provided isolation grooves 26′ in place of the isolation structure 26 of junction type of FIG.5. Other parts are identical to the structure of FIG.5 and further description of the device of FIG.6 will be omitted. It should be noted that the area of the p-n junction formed along the interface between the collector layer 23 or the buried collector layer 22 and the substrate 21 is substantially reduced by replacing the p-type region 26 by the groove 26′. However, such an isolation structure using the groove is disadvantageous from the viewpoint of yield and fabrication cost. US-A-4,785,259 discloses-a sense amplifier circuit of a memory in which the output of the sense amplifier is supplied to an output terminal via emitter-follower transistors. However, there is no decription of a plurality of sense amplifiers connected to a common bus. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor memory device wherein the foregoing problems are eliminated. Another object of the present invention is to provide a semiconductor memory device having an improved response and a reduced access time. These objects are achieved by the features of claim 1. According to the present invention, the delay at the time of reading the data is substantially reduced by using the emitter follower construction of the bipolar transistor for the bipolar transistors forming the switch devices. The objects and features of the present invention will become apparent from the following detailed description when read in conjunction with attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a block diagram showing the general construction of a conventional semiconductor memory device; FIG.2 is a circuit diagram showing a part of the device of FIG.1; FIG.3 is a circuit diagram showing an amplifier used in the device of FIG.1; FIG.4 is a circuit diagram showing a part of the device of FIG.1; FIG.5 is a cross-sectional view showing the structure of a conventional bipolar transistor used in the device of FIG.1; FIG.6 is a cross-sectional view similar to FIG.5 showing another example of the bipolar transistor used in the device of FIG.1; FIG.7A is a circuit diagram showing a first embodiment of the present invention; FIG.7B is a circuit diagram showing a part of the circuit of FIG.7A in detail; and FIG.8 is a circuit diagram showing a second embodiment of the present invention. DETAILED DESCRIPTION Hereinafter, the present invention will be described with reference to FIGS.7A and 7B showing a first embodiment. In the present embodiment, the semiconductor memory device has a construction substantially identical to that of FIG.1 except for the column decoder 3 which is now replaced by a column decoder 13 which also acts as the sense and write circuit. It should be noted that, in FIG.1, the memory cell array 1 and the row decoder 2 have well known constructions and the description thereof will be omitted. Similarly, the address decoder 3a shown in FIG.4 has a well known construction and the description thereof will be omitted. Referring to FIG.7A showing the column decoder 13, a number of sense amplifiers 41, 42, 43, 44, each comprising a pair of bipolar transistors 45 and 46, are connected to respective bit line pairs BL1 and BL1 , BL2 and BL2 , BL3 and BL3 , and BL4 and BL4 . In the case of the sense amplifier 41 connected to the bit lines BL1 and BL1 , the transistor 45 has a base connected to the bit line BL1 and an emitter connected to a selectively activated current source 47 to be described later. Further, the transistor 45 has a collector connected to a base of a transistor 50 forming a switching element. Similarly, the transistor 46 has a base connected to the bit line BL1 and an emitter connected, commonly to the emitter of the transistor 45, to the selectively activated current source 47. The collector of the transistor 46 is connected to the base of a bipolar transistor 53 acting as a switching device together with the transistor 50. The transistor 50 has a collector connected to a voltage source V P and an emitter connected to a common data bus 49. Similarly, the transistor 53 has a collector connected to the voltage source V P and an emitter connected to a common data bus 52. The data bus 49 and the data bus 52 extend to the output buffer circuit 4a similarly to the buses 8 and 9 of FIG.2, and a number of other sense amplifiers 42 - 44, each having a construction identical to the sense amplifier 41, are connected commonly thereto as illustrated in FIG.7A. Further, a clamp circuit 54 is connected to respective collectors of the transistors 45 and 46 as shown in FIG.7A. Referring to FIG.7A, the clamp circuit 54 includes p-channel type MOS transistors 61 and 63 connected parallel with each other, with respective gates connected commonly to an input terminal A and respective sources connected commonly to a positive voltage source V H . Further, the clamp circuit 54 includes another pair of p-channel MOS transistors 62 and 64 connected parallel with each other, with respective gates connected commonly to an input terminal B and respective sources connected to respective drains of the transistors 61 and 63. The drains of the transistors 62 and 64 are connected commonly to a negative voltage source V L , and the drain of the transistor 61 is connected, commonly with the collector of the transistor 45, to the base of the transistor 50. Similarly, the drain of the transistor 63 is connected, commonly with the collector of the transistor 46, to the base of the transistor 53. As the construction of the sense amplifiers 41 - 44 are identical with each other, the description with respect to the sense amplifiers 42 - 44 will be omitted. FIG.7B shows the circuit diagram of the selectively activated current source 47 used in the sense amplifiers 41- 44. As can be seen from this drawing, the current source 47 actually comprises an n-channel MOS transistor having its source connected to the ground and the drain connected to the emitter of the bipolar transistors 45 and 46. The MOS transistor 47 has a gate which is connected to commonly to the input terminal B. Next, the operation of the memory device of FIG.7A will be described. When the sense amplifier 41 is selected, a low level signal L is supplied to the input terminal A while a high level signal H, which is the inversion of the signal L, is supplied to the input terminal B. In response to the signal H to the input terminal B, the n-channel MOS transistor forming the current source 47 is turned on. Further, the p-channel MOS transistors 61 and 63 connected to the input terminal A are turned on in response to the input signal L to the input terminal A and the p-channel MOS transistors 62 and 64 are turned off in response to the signal H to the input terminal B. Thereby, the positive voltage V H is supplied to the collector of the transistors 45 and 46 after passing through the MOS transistors 61 and 63 which act as the load resistance, to the transistors 45 and 45. Now, when the bit line BL1 is in the high level state reflecting the logic data "1" stored in the addressed memory cell 1a, the transistor 45 is turned on and current flows through the transistor 45 from the collector to the emitter. Thereby, the voltage at the base of the transistor 50 becomes low and the transistor 50 connected to the common data bus 49 is turned off. At the same time to the high level state of the bit line BL1, a low level state appears on the conjugate bit line BL1 and in response to the low level state of the bit line BL1 , the transistor 46 is turned off. Thereby, the base voltage of the transistor 53 becomes high and the transistor 53 is turned on. As a result, a current flows through the common data bus 52 from the voltage source V P . As there are constant current sources 48 and 51 connected to the common data bus 49 and 52 respectively, a high level voltage appears on the common data bus 52 and a low level voltage appears on the common data bus 49. The output buffer circuit 4 which may be a differential amplifier shown in FIG.3 detects the voltage difference between the data bus 49 and the data bus 52, and produces a data output at the output terminal D OUT indicative of the logic data "1". In the case where the voltage level on the bit line BL1 is low and the voltage level on the bit line BL1 is high in correspondence to the logic level "0" stored in the memory cell 1a, a reversed state appears wherein a high level output is obtained on the bus 49 and a low level output is obtained on the bus 52. In response thereto, output data indicative of the logic data "0" is obtained at the output terminal D OUT . As the operation of the device in this case is obvious from the foregoing description, further description will be omitted. When the sense amplifiers 41 - 44 are not addressed, signals with reversed states are applied to the input terminals A and B. Thus, the low level signal L is applied to the input terminal B and the high level signal H is applied to the input terminal A. In this case, the current source 47 is disabled in response to the low level signal L to the input terminal B (see FIG.7B), and the transistors 45 and 46 forming the sense amplifier are both turned off. Further, the transistors 62 and 64 are turned on in response to the low level signal L at the input terminal B while the transistors 61 and 63 are turned off in response to the high level signal H at the input terminal A. As a result, the negative voltage V L is supplied, after passing through the transistors 62 and 64 acting as the load resistance, to the base of the transistors 50 and 53 irrespective of the voltage level of the bit lines BL and BL , and the transistors 50 and 53 are both turned off. Thereby, no voltage signal is supplied to the common data bus 49 or 52 from the non-selected sense amplifiers. Only the voltage from the selected sense amplifiers are supplied to these data buses and a reliable reading operation is achieved. It should be noted that, in the present embodiment, the common data bus such as the bus 49 or the bus 52 are connected to the emitter of the bipolar transistor 50 or 53. As can be seen from the cross-sectional view of the transistor of FIG.5, the interface between the emitter and base of the bipolar transistors has a substantially reduced area, and the adversary effect due to the parasitic capacitance on the signal transfer on the common data bus is effectively minimized. It should be noted that the emitter and base of the transistors 50 and 53 in the non-selected sense amplifiers are all strongly reverse biased and the effect of the parasitic capacitance is further reduced. Another advantage of the present invention is that such an emitter follower construction of the transistors 50 and 53 provides a large common emitter current gain which enables to flow a large current through the data buses 49 and 52. Thereby, the remaining parasitic capacitance is, if any, charged up immediately and the delay in transfer of signals along the bus is minimized. Because of these preferable features pertinent to the present invention, the semiconductor memory device of the present invention operates at a high speed and reading of data can be performed with reduced access time. Further, the semiconductor device allows the use of bipolar transistors having the junction isolation structure for the transistors 50 and 53 without sacrificing the operational performance. Thus, the yield of fabrication of the device is improved and the cost of fabricating the memory device is reduced. FIG.8 shows a second embodiment of the present invention. In this embodiment, the sense amplifier shown by a numeral 71 has the drain of the p-channel MOS transistor 61 and the source of the p-channel MOS transistor 62 connected together similarly to the first embodiment, and the drain of the transistor 61 and the source of the transistor 62 are connected to the base of the transistors 50 and 53 respectively via a load resistance 72 and a load resistance 73. In operation, when an input signal having the level L is supplied to the input terminal A and an input signal having the level H to the input terminal B in correspondence to the selection of the sense amplifier 71, the transistor 61 is turned on while the transistor 62 is turned off, and the source voltage V H at the source of the transistor 61 is supplied to the base of the transistors 50 and 53 respectively via the load resistances 72 and 73. Thereby, the base voltage of the transistors 50 and 53 are determined in response to the content of the data stored in the addressed memory cell 1a similarly to the case of the first embodiment. When the sense amplifier 71 is not selected, the signal H is supplied to the input terminal A while the signal L is supplied to the input terminal B. Thereby, the transistor 61 is turned off and the transistor 62 is turned on. Thus, the negative voltage V L is supplied to the base of the transistors 50 and 53 via the load resistances 72 and 73, and the transistors 50 and 53 are both turned off. Other operations are identical to the case of the first embodiment and further description will be omitted. In this embodiment, too, the advantageous features described with reference to the first embodiment is obtained. Further, the present invention is not limited to these embodiments described heretofore, but various variations and modifications may be possible within the scope of the invention.

Claims: A semiconductor memory device, comprising: a memory cell array (1) comprising a plurality of memory cells (1A) arranged in a row and column formation for storing data, each of the memory cells being connected to a word line (WL) and a bit line (BL) such that a plurality of memory cells arranged in a row direction are connected to a common word line and a plurality of memory cells arranged in a column direction are connected to a common bit line; row decoder means (2) connected to the memory cell array by a plurality of said word lines, said row decoder means being supplied with a first address signal addressing a word line to which an addressed memory cell is connected for selecting said word line; column decoder means (13) connected to the memory cell array by a plurality of said bit lines, said column decoder means comprising a plurality of sense amplifiers (41 - 44) each connected to a corresponding bit line and supplied selectively with a second address signal addressing a bit line to which the addressed memory cell is connected, said addressed sense amplifier selecting the addressed bit line in response to the second address signal for detecting data stored in the addressed memory cell which is connected to the addressed bit line, each of said sense amplifiers producing an output signal indicative of the detected data, a common data bus (49, 52) connected commonly to the plurality of sense amplifiers for transferring the data stored in the addressed memory cell, and a plurality of switching devices (50, 53) provided in correspondence to the plurality of sense amplifiers respectively for selectively transferring the data detected by the addressed sense amplifier to the common data bus; wherein each of the switching devices comprises a first bipolar transistor (50, 53) having a collector connected to a power voltage source, an emitter connected to the common data bus, and a base connected to the corresponding sense amplifier for receiving the output signal of the sense amplifier indicative of the data, characterized in that data discrimination means are connected to the common data bus for producing an output data signal indicative of the data stored in the addressed memory cell in response to the output signal of the sense amplifier transferred along the common data bus, and in that said column decoder means (13) further comprises a plurality of control circuits (54) provided respectively in correspondence to the plurality of sense amplifiers (41 - 44), said control circuit selectively disabling the first bipolar transistor (50) of the switching device in response to an absence of the second address signal incoming to the sense amplifier. A semiconductor memory device as claimed in claim 1, characterized in that each of said sense amplifiers comprises a second bipolar transistor (45) having a base connected to the bit line (BL), a collector connected to the base of the first bipolar transistor, and an emitter connected to a current source (47) which is turned on selectively in response to the second address signal addressing the bit line to which the sense amplifier is connected. A semiconductor memory device as claimed in claim 1 or 2, characterized in that said control circuit comprises a first MOS transistor (61) having a source connected to a first voltage source (V H ) providing a first predetermined voltage and a drain connected to the base of the first bipolar transistor (45) forming the switching device, and a second MOS transistor (62) having a source connected to the base of the first bipolar transistor commonly with the drain of the first MOS transistor and a drain connected to a second voltage source (V L ) providing a second predetermined voltage different from the first predetermined voltage, said first and second MOS transistors having respective gates connected to a first and a second input terminals (A, B) for receiving the second address signal and a logic inversion signal of the second address signal respectively, wherein said second predetermined voltage is determined such that a base voltage sufficient to turn the first bipolar transistor (50) off is supplied to the base of the first bipolar transistor when there is no second address signal to the sense amplifier. A semiconductor memory device as claimed in claim 1 characterized in that each of said bit lines (BL) comprises a first bit line (BL1, BL2, BL3, BL4) for transferring data stored in the addressed memory cell (1a) and a second bit line ( BL1 , BL2 , BL3 , BL4 ) for transferring the data stored in the addressed memory cell with an inverted logic state; said common data bus comprises a first data bus (49) connected to the emitter of the first bipolar transistor (50) and a second data bus (52); wherein each of the switching devices further comprises a second bipolar transistor (53) having a collector connected to the power voltage source (v P ), an emitter connected to the second data bus (52), and a base connected to the corresponding sense amplifier for receiving the output signal of the sense amplifier indicative of the data; wherein said sense amplifier comprises a third bipolar transistor (45) having a base connected to the first bit line (BL1), a collector connected to the base of the first bipolar transistor (50) and an emitter connected to a current source (47) which is turned on in response to the second address signal, and a fourth bipolar transistor (46) having a base connected the second bit line ( BL1 ), a collector connected to the base of the second bipolar transistor (53) and an emitter connected to the current source (47) commonly with the emitter of the third bipolar transistor (45). A semiconductor memory device as claimed in claim 4 characterized in that said column decoder means (13) further comprises a plurality of control circuits (54) provided respectively in correspondence to the plurality of sense amplifiers (41 - 44) for selectively disabling the first and second bipolar transistors (50, 53) of the switching device in response to an absence of the second address signal to a sense amplifier, wherein said control circuit comprises a first MOS transistor (61) having a source connected to a first voltage source (V H ) providing a first predetermined voltage and a drain connected to the base of the first bipolar transistor (50) forming the switching device, a second MOS transistor (62) having a source connected to the base of the first bipolar transistor (50) commonly with the drain of the first MOS transistor (61) and a drain connected to a second voltage source (V L ) providing a second predetermined voltage different from the first predetermined voltage, said first and second MOS transistors (61, 62) having respective gates connected to a first and a second input terminals (A, B) for receiving the second address signal and a logic inversion signal of the second address signal respectively, a third MOS transistor (63) having a source connected to the first voltage source (V H ) and a drain connected to the base of the second bipolar transistor (53) forming the switching device, a fourth MOS transistor (64) having a source connected to the base of the second bipolar transistor (53) commonly with the drain of the third MOS transistor (63) and a drain connected to the second voltage source (V L ), said third MOS transistor (63) having a gate connected to the first input terminal (A) commonly with the gate of the first MOS transistor, said fourth MOS transistor (64) having a gate connected to the second input terminal (B) commonly with the gate of the second MOS transistor, wherein said second predetermined voltage is determined such that a base voltage sufficient to turn the first and second bipolar transistors (50, 53) off is supplied to the base of the first and second bipolar transistors (50, 53) when there is no second address signal to the sense amplifier. A semiconductor memory device as claimed in claim 4 characterized in that said column decoder means (13) further comprises a plurality of control circuits (54) provided respectively in correspondence to the plurality of sense amplifiers (41 - 44) for selectively disabling the first and second bipolar transistors (50, 53) of the switching device in response to an absence of the second address signal to the sense amplifier, wherein said control circuit (54) comprises a first MOS transistor (61) having a source connected to a first voltage source (V H ) providing a first predetermined voltage and a drain, a second MOS transistor (62) having a source connected to the drain of the first MOS transistor (61) and a drain connected to a second voltage source (V L ) providing a second predetermined voltage different from the first predetermined voltage, said drain of the first MOS transistor (61) being connected to the base of the first bipolar transistor (50) via a first resistance (72) and to the base of the second bipolar transistor (53) via a second resistance (73), said first and second MOS transistors (61, 62) having respective gates connected to a first and a second input terminals (A, B) for receiving the second address signal and a logic inversion of the second address signal respectively, wherein said second predetermined voltage is determined such that a base voltage sufficient to turn the first and second bipolar transistors (50, 53) off is supplied to the base of the first and second bipolar transistors when there is no second address signal to the sense amplifier.

Inventors: MAKI YASUHIKO, OKAJIMA YOSHINORI, MAKI, YASUHIKO, OKAJIMA, YOSHINORI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G11C7
IPC codes: G11C7, G11C8, G11C11