Dynamically variable digital delay

Abstract: An ultrasound system (100) for investigating a subject (91) comprises a probe (102), a signal processing module (104), and an interconnecting cable (106). The probe includes an annular phased array transducer (120) defining multiple signal processing channels Ch1-CH12. The signal processing module includes a controller (106), a transmitter (110), a receiver (112), delay circuitry (114), and a video section (116). Within the delay circuitry, each signal processing channel includes an inphase branch and a quadrature branch. Each branch includes an analog-to digital converter (ADC 412, 422) and a delay first-in-first-out (FIFO 416, 426) memory. Dynamically variable delays are implemented by varying the sampling and FIFO input rates relative to constant FIFO output rates. The variable clock rates are derived by switching between phase-staggered replicas of a master clock MCLK, which has a rate at the nominal center frequency of the ultrasound signal prior to sampling. The timing circuit (700) used to derive the variable clock rate signal uses a focus FIFO (706) to serve as a timing buffer between the variable clock rate signal and the master clock signal. Inphase data streams from each channel are combined in a pipelined adder (314); quadrature data streams are similarly combined. An interpolator (318) permits accurate combinations of the summed inphase and quadrature data streams. The resulting combination is directed to the video section for output. Advantages of the disclosed system include low signal processing, memory and data rate requirements, resulting in a more reliable and economical high-performance ultrasound system.

Description: The present invention relates to a dynamically variable digital delay which may be used in a digital ultrasound system for medical imaging, particularly a high-resolution digital ultrasound system with modest memory and processing requirements. A typical ultrasonic imaging system comprises an electronics module and a probe. The electronics module generates an electrical pulse which is converted to an ultrasonic pulse by a transducer in the probe. When the probe is pressed against a body, the ultrasonic pulse is transmitted into the body and is reflected to different degrees at tissue boundaries within the body. The reflections from the various tissue boundaries reach the transducer at different times, depending on their distances from the probe. The transducer converts the reflections to a time-varying electrical signal. This electrical signal is processed to form a video representation of the body being imaged. Relatively simple ultrasound systems are known which employ spherical or parabolic transducers to transmit and receive ultrasound signals. Generally, these transducers are fixed focus in that their focal point is a fixed distance from the transducer. Provisions are typically made to steer the transducer to obtain image information over a range of angles. The resolution of the ultrasound image is limited by the aperture of the transducer, with larger apertures allowing greater resolution. However, larger apertures produce shallower depths of field so that a smaller range of depths to either side of the focal point can be imaged within a given tolerance of maximum resolution. It is theoretically possible to provide both greater range and high resolution by deforming a transducer to vary its focal length so that a high resolution image is obtain for each of many focal depths. Apparently, it has not been practical to achieve the desired focal length control by mechanically deforming a transducer. On the other hand, "electronic deformation" of phased array transducers, a technology derived from radar, has permitted high-resolution imaging without significant depth-of-field limitations. Phased array transducers comprise multiple transducer elements arranged in annular, linear or planar arrays. By varying time delays between elements of any array one can vary the depth of focus dynamically. Thus, a large aperture array transducer can be used to obtain high-resolution imaging and its depth of focus can be varied to overcome the limitation of a shallow depth of field. Annular arrays come closest to simulating a mechanically deformable single-element spherical transducer. An annular array comprises multiple annular transducer elements arranged coaxially. As reflections are received by each of the annular elements, each annular element generates a corresponding electrical signal. By controlling the relative delays introduced in these electrical signals, the focal depth of the annular array transducer can be controlled. As with a spherical single-element transducer, an annular array must be mechanically steered to obtain a two-dimensional ultrasound image. Thus, an annular array involves a hybrid of mechanical and electronic control of the transducer focal point. A linear phased array comprises a series of narrow elements arranged side-by-side. Such an array can be electronicallyu steered and focussed. A disadvantage of a linear phased array is poor azimuthal resolution in the direction perpendicular to the plane of the image. Planar array transducers comprise a multitude of small-aperture elements arranged in a two-dimensional array. As with linear array transducers, both focal depth and steering can be effected electronically. In fact, steering can be in two-dimensions. A major advantage of planar array transducers, when contrasted with linear array transducers is that they resolve in the azimuthal dimension. However, planar array transducers are not widely implemented due to the large number of separate signal channels, one for each transducer element, which must be processed. Most ultrasound systems use analog processing to obtain video representations of the subject being imaged. However, as in other technological fields, several advantages are obtainable using digital processing. Once the signals are converted to digital format, they are less vulnerable to distortion, noise etc. In addition, digital systems are more amenable to automated testing and require few adjustments. Therefore, it is generally easier to manufacture reliable digital systems. Costs can be lowered through integration and flexibility can be provided through programming. Digital ultrasonic imaging systems are disclosed in U.S. Patent No. 4,290,310 to Anderson. These systems are all based on linear phased arrays, although the suggestion is made that the principles can be applied to other transducer configurations, including other phased array transducers. Each transmit/receive transducer or each transmit/receive transducer pair corresponds to a channel, with 32 or more channels being preferred to obtain practical resolution. Steering and focus are controlled as a function of relative delays between the channels. These relative delays are implemented by controlling the time between reading in and reading out reflection data from a analog memory device such as a serial analog memory (SAM) or a charge-coupled device (CCD), or a digital memory such as a first-in-first-out memory (FIFO). Analog-to-digital converters (ADCs) are used to convert the analog reflection signals to digital form before they are read into the FIFO memories. The output of the memory devices are combined by a summing circuit, the output of which is directed to a video detector, and thence to a display. A master controller synchronizes the ADCs, memories, summing circuit and video sweep to provide a coherent image of the subject being scanned. A major disadvantage of the system disclosed by Anderson is that focus depth cannot be swept dynamically. Anderson controls focal depth by filling memory devices to achieve a desired delay and then creates an image at the corresponding focal depth. Each depth requires a refilling of the memories, introducing delays in the imaging process. In effect, Anderson uses zone focussing--relying on a relatively small aperture, rather than dynamic focus, to provide the required resolution throughout the range of depths represented by the zones. Other disadvantages of these digital systems are basically cost and complexity, the latter impinging on reliability. Anderson required 32 channels of ultrasonic reflection information to be synchronized and processed in parallel. A high performance system using the same design principles would require more than 100 linear transducer elements and a corresponding number of signal processing channels. Each channel requires its own ADC and memory as well as ancillary components. The activity of each component in each channel must be synchronized with the transmitter and the video output section In addition, each of the components must be capable of handling data at high speeds. Ultrasound imaging frequencies typically range from 2-10 MHz. Sampling by the ADCs generally is over two and, preferably, about four times the maximum ultrasound frequency so that components should be rated from about 15 MHz to 40 MHz. Anderson discloses a 60 MHz master clock to produce component clocks of 15 MHz and 20 MHz. Component costs rise dramatically with maximum clock rate, so a premium must be paid for these high speed components. In addition, operation of the memories at high speeds lowers the range of delays that can be implemented using the components. Anderson combines memory devices serially to obtain longer delays, but this multiplies cost and complexity as well. Furthermore, Anderson's implementation using linear arrays results in poor azimuthal resolution. This problem can be addressed by opting for two-dimensional arrays. However, this would greatly exacerbate the problems of component count, component, cost and system complexity. Several hundred channels would be required for practical resolution in a digital two-dimensional phased array system. It is thus desirable to provide an ultrasonic imaging system which has the advantages of dynamic focus and digital control without the cost and complexity of the systems previously disclosed by Anderson. Preferably, high resolution in all three dimensions would be provided. Furthermore, the component clock ratings should be modest so that less costly components can be used and so that longer delays can be implemented without serially combining memory devices or using larger, more expensive memories. In ULTRASOUND IMAGING vol. 9, no. 2, March 1987, DULUTH MN USA, pages 75-91; J.H. KIM et al. :"Pipelined sampled-delay focusing in ultrasound imaging systems", there is disclosed an ultrasound system with a phased array transducer in which delays are introduced using asynchronously driven FIFO's. Each transducer element defines a signal processing channel. Each channel includes an inphase branch and a quadrature branch to further reduce data rate requirements for the system. Each channel and each branch, includes an analog-to digital converter (ADC) and a delay FIFO providing a dynamically variable digital delay. Timing circuitry converts master clock signals to timing signals used to drive the ADCs and delay FIFO inputs asynchronously relative to the delay FIFO outputs which are governed by the master clock. The asynchronous relation between FIFO input and output timings permits dynamic control of the number of samples stored in each delay FIFO, and thus dynamic control of the delay introduced in each signal channel. Dynamic control of the delays introduced by all delay FIFOs permits focal length to be swept continuously. This permits the practical use of larger aperture transducers without sacrificing imaging speed or limiting focussing range to a fixed depth of field. In this disclosure by Kim (see Figure 10) a sampling clock generator (SCG) provides inputs to the analog-digital converters (ADC). As shown in Figure 11, the components of the SCG are a memory, a latch and a multiplexer. The memory of the SCG generates the sampling clock for each array element. This sampling clock is synchronous with respect to the master clock. Thus, the sampling frequency and master clock frequency are identical. The master clock frequency required is equal to the number of discrete delays available times the center frequency of the transducer. On page 89, Kim teaches that the sampling frequency is constrained by the maximum operating speed of the memory. An object of the present invention is to overcome the constraint in the Kim disclosed system just referred to. According to the present invention there is provided a dynamically variable digital delay comprising: a signal source for providing a signal; sampling means for providing a digital representation of said signal, said sampling means having a signal input for receiving said signal, a digital output for transmitting said digital representation, and a control input for receiving a sample rate signal having a variable sample rate for controlling the timing used to generate said digital representation and thus the output rate of said digital representation; a delay FIFO having a data input, a data output, an input enable port and an output enable port, said data input being coupled to said source for receiving said digital representation from said source; the dynamically variable digital delay being characterised in that there are provided controller means for providing a master clock signal having a constant master clock rate, said controller means being coupled to said output enable port of said delay FIFO so that said digital representation is transmitted from said data output at said master clock rate, said controller means providing multiple phases of said master clock; and variable timing means cooperatively coupled to said controller means to select among said multiple phases of said master clock so as to produce a variable timing signal from a signal output, said signal output being coupled to said control input of said sampling means for providing said variable sample rate signal thereto, said signal output also being coupled to said input enable port of said delay FIFO so that said sample rate signal also controls the rate at which said digital representation is input into said delay FIFO whereby, said sampling rate can be varied relative to said master clock rate so that said digital representation can be input to said delay FIFO at a sampling rate which is dynamically variable relative to said master clock rate at which said digital representation is transmitted from said delay FIFO. An ultrasound system can thus be provided incorporating dynamically variable digital delays each as defined in the preceding paragraph and in which the asynchronous timing signals are derived by switching among multiple phases of the master clock of the system. In a dynamically variable digital delay according to the present invention, said variable timing means may include a multiplexer having signal inputs, said signal output and select inputs, said signal inputs being coupled to respective ones of said multiple phases so that one of said multiple phases can be selected for transmission from said signal output, said variable timing means may include a timing data generator for generating a digital delay data stream, said timing data generator having an output enable port coupled to said controller so that said digital delay data stream is characterised by said master clock rate; and said variable timing means may include a timing FIFO having a timing data input, a timing data stream output, and an input enable port said timing data input being coupled to said timing data generator for receiving said digital delay stream therefrom, said input enable port of said timing FIFO being coupled to said controller means so that said digital data stream is input into said timing FIFO at said master clock rate, and said select inputs of said multiplexer being coupled to said timing data stream output of said timing FIFO so that said timing data stream determines which one of said multiple phases is selected at any given time so that said sample rate can be adjusted by progressive phase changes as dictated by said timing data stream, said timing FIFO serving as a timing buffer between said master clock rate and said sampling rate. An ultrasound system can thus further be provided incorporating dynamically variable digital delays each as defined in the preceding paragraph. A phase shifter, which can be a digital shift register, can be used to generate the multiple clock phases which are provided as inputs to clock the phase multiplexers for each channel of the ultrasound system. The multiplexers can be switched so that the output phase is controlled precisely. Successive phase shifts effect a frequency shift so that each multiplexer output is essentially asynchronous relative to the master clock. Deriving sample rate and delay FIFO input signals by swithing between multiple phases of a master clock greatly reduces switching rate requirements of the system circuitry. Unlike the prior disclosure by Kim, the sampling clock for each digital delay may be phase shifted to provide an effective sampling clock which is asynchronous with respect to the master clock so that a much lower master clock frequency is required. Unlike Kim when the memory, that is the above defined timing data generator, is operated at the same frequency as the master clock, sampling frequencies above the master clock frequency are available for the digital delay of this invention. This and other features and advantages of the present invention are apparent from the description below with reference to the following drawings. Figure 1 is a schematic view of an ultrasound system in which dynamically variable digital delays, each in accordance with the present invention are incorporated. Figure 2 is a schematic perspective view of a transducer of the ultrasound system of Fig. 1. Figure 3 is a block diagram of the ultrasound system of Fig. 1 showing the bus widths between components of the system and detailing stages of delay circuitry for the system. One-and two-digit numbers represent the number of analog or digital data paths. Figure 4 is a block diagram depicting dynamically variable sampling and delay stages of the delay circuitry of Fig. 3. Figure 5 is a block diagram of a pipelined adder used in the delay circuitry of Fig. 3. "I" and "Q" designations indicate whether inphase or quadrature data streams were the source of data being transferred along a particular line at the instant represented by Fig. 5 Figure 6 is a block diagram of an interpolator used in the delay circuitry of Fig. 3. Figure 7 is a block diagram of the timing circuit for the delay circuitry of Fig. 3 and in particularly the sampling and delay stages of Fig. 4. Figure 8 is a timing diagram showing multiple phases of a master clock of the ultrasound system of Fig. 1 and the output of the timing circuit of Fig. 7. Figure 9 is a graph illustrating a dynamic focus sweep strategy employed by the present invention. An ultrasound system 100 includes a probe 102 and a signal processing module 104 which are connected via a cable 106, as shown in FIG. 1. Signal processing module 104 comprises a controller 108, a transmitter 110, a receiver 112, delay circuitry 114, and a video section 116. Probe 102 includes a body 118, a transducer 120, a probe window 122, a motor 124, a motor shaft 126, and a drive belt 128. Transducer 120 includes twelve concentrically arranged annular transducer elements 201-212 configured to conform to a section of a sphere, as indicated in FIG. 2. Each transducer element 201-212 defines a respective signal channel CH1-CH12. In operation, each channel CH1-CH12 receives a respective electrical pulse from transmitter 110 along a transmit bus 130 and cable 106. These pulses are initiated by a trigger signal from controller 108 and directed along a control bus 132 to transmitter 110. When all electrical pulses reach respective transducer elements 201-212 at the same time, the effective focal length of transducer 120 is its geometric focal length. Transmitter 110 also can introduce relative delays in pulses across channels CH1-CH12 to provide for selection of different focal zones. Delay circuitry 114 provides for dynamic focussing within each zone selected by transmitter 110. Transducer 120 converts the transmit pulses to ultrasound pulses which are transmitted through probe window 122 and into a subject 91 being characterized by ultrasound. The transmitted ultrasound pulses partially reflect at tissue boundary 93 and other boundaries characterized by ultrasound impedance mismatches. Transducer 120 detects the resulting echoes as an ultrasound signal. More precisely, each transducer element 201-212 detects an ultrasound signal. Each detected ultrasound signal is in the form of time-varying ultrasonic energy. Each transducer element 201-212 converts the signal it detects into a respective electrical signal. The twelve electrical signals generated by transducer elements 201-212 are transmitted along channels CH1-CH12 via cable 106 and a receiver bus 134 to receiver 112, which processes channels CH1-CH12 in parallel. Receiver 112 amplifies and time-gain compensates the electrical signals in each of the channels. Since each electrical signal is the result of multiple reflections of a single pulse, later portions of each signal represent reflections from deeper tissue boundaries. The greater depth correlates with greater attenuation. Time-gain compensation, i.e., amplification which increases over time, compensates for accumulated attenuation which increases as a function of time of detection. Controller 108 synchronizes time-gain compensation with the transmit pulses triggered via control bus 132. The time-gain compensated signals are accepted by delay circuitry 114 from receiver 112 along delay bus 136. The purpose of delay circuitry 114 is to introduce dynamic, relative delays among signals in channels CH1-CH12 so as to sweep electronically the focal length of transducer 120. The range of this sweep extends over a zone as selected by delays introduced by transmitter 110. Successive sweeps over different transmit zones can be used to extend focussing range. Video bus 138 conveys the output of delay circuitry 114 to video section 116. This output is a digital representation of the ultrasonic image of subject 91 with successive portions of the digital representation representing respective depths within a transmit zone. The process as described so far provides a one-dimensional image representing a vector within subject 91. A fan-shaped two-dimensional image is obtained by combining successively obtained one-dimensional images while steering transducer 120. Motor 124 is mechanically linked to transducer 120 via shaft 126 and drive belt 128 to effect steering. Controller 108 controls motor 124 via control bus 132 and cable 106 so that steering can be synchronized with video output. Delay circuitry 114 is shown in greater detail in FIG. 3. As indicated, detected ultrasound signals are converted to twelve electrical signals which are directed to receiver 112 along receiver bus 134. The twelve amplified signals are conveyed along delay bus 136 to delay circuitry 114. Delay circuitry 114 includes a node bank 302 which splits each channel CH1-CH12 into two branches, i.e., inphase and quadrature branches, resulting in a 24-branch analog link 304 to ADC bank 306. ADC bank 306 digitizes the signals in each branch to provide twenty-four digital data streams along a 24-branch FIFO input link 308 to delay FIFO bank 310. The delays required for focussing are introduced at this delay FIFO bank 310, and the delayed digital data streams are conveyed along delay FIFO output link 312 to a piplelined adder 314. Pipelined adder 314 combines inphase data streams across channels and quadrature data streams across channels. It thus provides two digital data streams along interpolator link 316 to an interpolator 318. Actually, interpolator link 316 is a single data communications line with the inphase and quadrature streams being time-multiplexed thereon. The output of interpolator 318 is directed along video bus 138 to video section 116 for display. The intersection of a channel CH5 with node bank 302, ADC bank 306, delay FIFO bank 310 and pipelined adder 314 is illustrated in FIG. 4. Line 402 is the channel CH5 signal line of delay bus 136. Node 404 is the channel CH5 node of node bank 302. The signal received along line 402 is divided into two replica signals to be processed by the inphase branch 406 of channel CH5 and the quadrature branch 408 of channel CH5, respectively. Inphase branch 406 includes an inphase sample input line 410, an "inphase" analog-to-digital converter 412, an "inphase" FIFO input line 414, an "inphase" delay FIFO 416, and an inphase FIFO output line 418. Correspondingly, quadrature branch 408 of channel CH5 includes a quadrature sample input line 420, a "quadrature" analog-to-digital converter 422, a "quadrature" FIFO input line 424, a "quadrature" delay FIFO 426, and a quadrature FIFO output line 428. FIGS. 3 and 4 are related as follows. Both sample input lines 410 and 420 are part of 24-line analog link 304. Inphase ADC 412 and quadrature ADC 422 belong to ADC bank 306; inphase FIFO input line 414 and quadrature FIFO input line 424 belong to 24-line FIFO input link 308; inphase delay FIFO 416 and quadrature delay FIFO 426 are part of FIFO bank 310, and inphase FIFO output line 418 and quadrature FIFO output line 428 belong to 24-line FIFO output link 312. Lines 418 and 428 are hardwired together at a node 430 at the input of an add gate 432. Add gate 432 and an associated latch 434 are elements of pipelined adder 314. Despite their different labels, inphase sample input line 410 and quadrature sample input line 420 carry identical analog signals with negligible phase differential. The difference between the inphase and quadrature components arises from the different timing signals. Inphase ADC 412 samples the analog input at port A at a rate determined by a timing signal at its CLK port to yield an 8-bit digital output at its D port. Quadrature ADC 422 is functionally identical but is driven by a timing signal which lags the timing signal to inphase ADC by 90°. Inphase delay FIFO 416 inputs data received at its data-in port DI at a rate determined by a timing signal applied to its input clock port IC and outputs data on a first-in-first-out basis from its data-out port DO at a rate determined by a timing signal applied to its output-clock port OC. Quadrature delay FIFO 426 is functionally identical and is driven 90° out of phase relative to delay FIFO 416. The delay FIFOs in FIFO bank 310, FIG. 3, are clocked out at the same rate, which is the master clock rate and the nominal center frequency of the ultrasound signals. The even-numbered inphase delay FIFO outputs and the odd-numbered quadrature delay FIFO outputs are in phase with each other and 180° out of phase with odd-numbered inphase delay FIFO outputs and even-numbered quadrature delay FIFO outputs. Specifically, the outputs of the even-numbered inphase delay FIFOs and of the odd-numbered quadrature FIFOs are driven by the master clock MCLK and the outputs of the odd-numbered inphase FIFOs and of all even-numbered quadrature FIFOs are driven by the complement MCLK* of master clock signal MCLK. In contrast to the constant rate timing signals applied to the delay FIFO output clock ports OC, variable rate clocks are applied to the delay FIFO input clock ports IC as well as the to the clock ports CLK of the ADCs. For example, inphase ADC 412 and input port IC of inphase delay FIFO 416 are driven by a variable rate channel CH5 inphase timing signal CLK5I. Quadrature ADC 422 and input port IC of quadrature delay FIFO 426 are driven by a variable rate channel CH5 quadrature timing signal CLK5Q, which is derived from CLK5I by adding a 90° phase delay. In operation, CLK5I is operated at an average rate above that of MCLK. This causes inphase delay FIFO 416 to fill, resulting in an increasing delay in the data stream through the inphase branch of channel CH5. For each channel, the sampling rate and the delay FIFO input rate is varied to effect an increasing depth of focus for transducer 120. Channel CH1 is an exception, its sampling rate can be at MCLK to serve as a reference for the relative delays introduced in the other channels CH2-CH12. As indicated above, the output of inphase delay FIFO 416 is driven 180° out of phase with respect to the output of quadrature delay FIFO 426. In effect, these two FIFOs 416 and 426 take turns providing values to the input A1 of add gate 505. The value applied to input A1 is added to a value received at input A2 of add gate 505 and the result is directed to the latch input LI of latch 525 for storage therein. Latch 525 receives a clock signal MCLKX2 which operates at twice the rate of MCLK. The effect is that the contents of latch 525 alternate between inphase and quadrature sums. The outputs from the different channels are combined by pipelined adder 314 as indicated in FIG. 5, which shows a portion of adder 314 at an arbitrary nth cycle of the master clock, with "I" representing inphase values and "Q" representing quadrature values. During this cycle, quadrature delay FIFO 426 is providing its quadrature output to add gate 505, while the output of inphase delay FIFO is disabled, as indicated by the broken line representing inphase delay FIFO output 418 in FIG. 5. The quadrature value from channel CH5 is added to a cumulative quadrature value from a latch 526 associated with channel CH6 and the sum is stored in latch 525 of channel CH5. In turn, the prior contents of channel CH5 latch 525, which reflected an inphase cumulative sum, are transmitted to channel four 224 adder 504 for addition with an inphase value being output from channel CH4. This result is stored in channel CH4 latch 524. In the same cycle, the present quadrature value from channel CH1 is directed to channel one add gate 501 for addition with the prior contents of channel CH2 latch 532. The result is the sum: where m is the the channel number and n is the master clock cycle, and Q m / n is the quadrature value from channel CHm during the nth master clock cycle. On the next half master clock cycle the output of the pipelined adder will be: where I m / n is the inphase value from channel CHm during the nth clock cycle. Note that each channel provides two values, an inphase value and a quadrature value, during each clock cycle. Thus, the output of pipelined adder 314, which is directed along line 316 to interpolator 318, is an alternating series of 12-bit cumulative quadrature values x q and cumulative inphase values x i . The cumulative quadrature and inphase values must be recombined to provide a single data stream for use by video section 116. However, without additional processing, combination of the x i and x q values would introduce errors due to the difference in the timing of the I and Q samples. Interpolation can be used to derive values corresponding to the incoming analog signal between actual sample points. Thus, interpolation can be used to define I and Q values corresponding to coincident samples, rather than phase offset samples. This interpolation is performed by interpolator 318. Interpolator 318 comprises a data compression ROM 602, a series of five latches 611-615, a 2-point finite impulse response (FIR) filter 620, a 3rd-point FIR filter 622, another latch 624, and a complex adder 626. Data compression ROM 602 receives the cumulative quadrature and inphase values output from pipelined adder 314. Compression ROM 602 is a look up table which converts the incoming twelve-bit values to six-bit values using a non-linear transformation to preserve the most significant information. The twelve incoming bits select an address which stores the square root of the address and the six most significant digits of the square root are output to the series of latches 611-615. Like pipelined adder 314, the interpolator components are clocked by MCLKX2. The exceptions are complex adder 626 and the associated latch 624, which are operated at the master clock rate. At any given time, latches 511-515 store five successive output values from compression ROM 602. The first, middle, and last latches of this series will either store three successive quadrature values or store three successive inphase values. When all three hold compressed quadrature values, last latch 515 holds the first in a series of three such values, the middle latch 513 holds the middle of three successive values, and first latch 511 holds the third of three successive quadrature values. The outputs of the first and last latch are the inputs to 2-point FIR 620, which is a look-up table ROM. Thus the inputs to 2-point FIR 620 are the first and third points in a series of either three quadrature values or three inphase values. These values serve to select an address and the contents of the selected address represent the desired FIR transformation. The required transformation depends on whether the values are quadrature or inphase values. Accordingly, 2-point FIR 620 includes two look-up tables. Alternation between these look-up tables is effected by the MCLK signal tied to a highest order address bit for 2-point FIR filter 620. The result of 2-point FIR filter 620 is combined with the second of the three intermediate values, which was stored in middle latch 513, at 3rd-point FIR 622. The output of 3rd point FIR 622 is a series of alternating I* and Q* values with each pair representing coincident samples of the actual inphase and quadrature components of the signal. The interpolator minimizes the errors in these pairs of I* and Q* samples due to the time differences between inphase and quadrature samplings. Latch 624 is clocked to receive interpolated quadrature values. Complex adder 626 is clocked to receive interpolated inphase values at its first input I1 and interpolated quadrature values are received at its second input I2 via latch 624. Complex adder 626 thus combines the interpolated values to provide a unitary image intensity stream at its output. This image intensity stream is directed along line 138 to video section 116 for display. Almost all clocked components in the channels are operated at the master clock rate or, in the case of pipelined adder 314 and some components of interpolator 318, at twice the master clock rate. The exceptions are the ADCs and the delay FIFO inputs. These are driven essentially asynchronously relative to the master clock. The portions of the timing circuitry required to provide the asynchronous timing signals for the ADCs and delay FIFOs of channel CH5 are shown as timing circuit 700 in FIG. 7. Controller 108 is shown providing master clock signals MCLK to this timing circuit 700 which comprises a depth counter 702, a focus PROM 704, a focus FIFO 706, a phase counter 708, a phase multiplexer 710, and a phase shifter 712. Depth counter 702 simply counts master clock signals MCLK and outputs the count on a twelve-bit address bus 714 coupled to the address inputs AX of focus PROM 704. This focus PROM 704, which can comprise multiple PROMS in parallel, provides a twelve-bit output. The contents of each address of focus PROM 704 is a twelve-bit word containing timing information for all 'twelve channels CH1-CH12 . For each count of depth counter 702, focus PROM 704 provides one bit of information to each channel. This information is used to affect the effective frequency of the ADC and delay FIFO input timing signals. Stored in focus PROM 704 are about 1000 bits of timing information for each channel. This timing information is a "program" governing delay as a function of time, i.e., the delay profile, for the channel. For example, one output line 715 from focus PROM 704 is coupled to the channel CH5 focus FIFO 706. The other eleven output lines 716 from the focus PROM are coupled to respective focus FIFOs for the other channels. The input enable of focus FIFO 706 is connected to the controller for receiving master clock signal MCLK. Thus, focus PROM data is read into focus FIFO 706 at the master clock rate. Data, in the form of a string of Os and 1s is transmitted from focus FIFO 706 on a first-in-first-out basis to phase counter 708 along line 718. Phase counter 708 increments its stored value each time a 1 is received, while no increment is applied when a 0 is received. The three lowest order output bits of phase counter 708 are tied to three select inputs 3S of phase multiplexer 710 via select bus 720. In effect, phase counter is a modulo eight counter, recycling every eight 1s. In turn, the cycling of phase counter 708 cycles phase multiplexer 710 through eight possible switch positions. Phase multiplexer 710 has eight data inputs 8D, all tied to controller 108. Controller 108 includes phase shifting circuitry for providing eight evenly staggered replicas of master clock MCLK. In other words, eight-bit-wide clock bus 724 carries MCLK, MCLK + 45°, MCLK + 90°, MCLK + 135°, MCLK + 180° which is MCKL*, MCLK* + 45°, MCLK* + 90°, and MCLK* + 135°, shown in FIG. 8. Each time phase counter 708 increments, phase multiplexer 710 switches from one input to one leading that input by 45°. By way of example, the inphase timing signal CLK5I for channel CH5, which is the same as the output of phase multiplexer 710, is shown in FIG. 8 initially in-phase with MCLK. Specifically, CLK5I is in-phase with MCLK during a first cycle 801 so that a first positive transition 811 of CLK5I is concurrent with a positive transition 821 of MCLK. A first 1 received from focus PROM 704 during a second cycle 802 of CLK5I causes phase multiplexer 710 to select MCLK + 45° so that a second positive transition 812 of CLK5I is concurrent with a positive transition 822 of MCLK + 45°. A second 1, received during cycle 803, causes phase multiplexer 710 to advance to MCLK + 90° so that positive transition 813 is concurrent with a positive transition 823 of MCLK + 90°. A 0 is received during a fourth cycle 804 of CLK5I so that phase multiplexer 710 does not advance; as a result, positive transition 814 of CLK5I is concurrent with a second positive transition 824 of MCLK + 90°. A third 1, received during fifth cycle 805, causes fifth positive transition 815 to be concurrent with a positive transition 825 of MCLK + 135°. The next 1 (not. represented in FIG. 8) received places CLK5I in-phase with MCLK*. Four more 1s return CLK5I to an in-phase relationship with MCLK. However, at this time, CLK5I would have progressed through one more cycle than MCLK. In effect, CLK5I has a higher frequency than MCLK. The degree to which the frequency of CLK5I exceeds that of MCLK is a function of the ratio of 1s to 0s in the data stream through focus FIFO 706. Thus, where MCLK is 5 MHz, CLK5I has an average frequency of 5.42 MHz for the illustrated duration. A string of all 1s would yield a frequency of 5.63 MHz. Thus, the present scheme allows CLK5I to vary from between about 5 MHz to 5.63 MHz, or from a nominal frequency to 12.5% above that. In an alternative embodiment using two focus data streams for each channel and an up/down counter, the sample timing signals for each channel could be dynamically varied 12.5% to either side of MCLK. The phase multiplexer output CLK5I is directed along line 726, FIG. 7, to govern the sampling rate of inphase ADC 412 and the input clock IC for inphase delay FIFO 416. Phase shifter 712 produces a replica of CLK5I which is delayed by one-quarter cycle to produce CLK5Q which is directed along line 728 to drive quadrature ADC 422 and the input of quadrature delay FIFO 426. CLK5Q is also directed along line 730 to the output clock OC of focus FIFO 706. This ensures that phase multiplexer switching is appropriately synchronized with variable timing signals. In effect, focus FIFO 706 acts as a timing buffer between the external circuitry governed by MCLK and the timing circuit for channel CH5 which is operated at the variable clock rate corresponding to CLK5Q. From the foregoing, it should be apparent that while CLK5I and CLK5Q are derived from MCLK, their common rate can vary independently of MCLK. In this sense, they are asynchronous relative to MCLK. As described, timing circuit 700 only allows for advancing CLK5I relative to MCLK. However, by providing two data lines and parallel focus FIFOs, and using an up/down phase counter, CLK5I can be made to vary above and below MCLK as required. Each channel includes a timing circuit essentially like timing circuit 700 for channel CH5. In operation, the differences between the channels arise from the programs stored in focus PROM 704. For example, channel CH1 may have all 0s in its program so that channel CH1 operates at MCLK. The remaining channels are delayed relative to channel CH1 to effect the desired focus sweep. Of course, any channel could serve as the reference channel in place of channel CH1. It should also be clear that a timing circuit is not required for a reference channel governed solely by master clock MCLK. However, ultrasound system 100 incorporates timing circuits for all channels to maximize programming flexibility. The contents of focus PROM can be determined by working backward from delay curves, such as those illustrated in FIG. 9. Curves 901,905 and 908 correspond to channels CH1, CH5 and CH8, by way of example. Channel CH1 corresponds to central annular element 201 of transducer 120. Each curve 901, 905 and 908 includes an initialization segment 911, 915, 918, respectively, ending at and an operational segment, beginning at t i , and an operational segment 921, 925, 928, respectively, beginning at t i . Operational segment 921 indicates a constant delay for channel CH1, which is used as the reference for the other channels. Operational segment 925 for channel CH5 begins with a delay shorter than that assigned to channel CH1 and ends with a greater delay. This corresponds to a depth sweep which begins with a near focus and ends with a far focus. Operational segment 925 intersects operational segment 921 at a point corresponding to the geometric focus for transducer 120. Operational segment 928 is similar to operational segment 925; since transducer element 208 is further from element 201 than is element 205, operational segment 928 is more accentuated than operational segment 925. The delays associated with the different channels are coordinated so that at all times they share a common focus. At time t f , all channels share the geometric focus for transducer 120. Dynamic digital delay requires digital approximation of the delay curves. A step function 935 is shown approximating operational segment 925 for channel CH5. Step function 935 is obtained by dividing operational segment 925 into subsegments corresponding to master clock cycles. Step function 935, like the step functions for the other channels, is constant during master clock cycles and during some transitions between master clock cycles. However, transitions to the next higher level are introduced as necessary to approximate operational segment 925. Step function 935 can be encoded as shown in data stream 945 which has zeroes corresponding to clock cycles without transitions and ones corresponding to transitions. This data stream 945 is stored in the appropriate column of the focus FIFO and is read out as the depth counter is incremented. The effect on CLK5I of first five bits, e.g., 01101, of digital stream 945 have been discussed with reference to FIG. 8 above. At time t i , the delay FIFO corresponding to channel CH1 is half full and is maintained at that level. This level is achieved by filling the channel CH1 delay FIFO while its output is disabled and enabling the output once the delay FIFOs for channel CH1 are half full. The first column of the focus PROM is correspondingly all zeroes. Increasing delays are introduced in the remaining channels. Therefore it is preferable that the corresponding delay FIFOs begin less than half full, as is indicated for channels CH5 and CH8 at time t i for delay curves 905 and 908. Again, the desired initial FIFO levels are set by filling the FIFOs with the output disabled and enabling the outputs at time t i . There are many alternatives to the embodiments described above. Different strategies can be used to generate the data streams for the channels. In fact, the data streams could be reprogrammable, and where appropriate feedback is available, real-time reprogrammability could provide for a closed-loop ultrasound tracking system. Different clock rates, component counts, transducer geometries, and signal processing techniques are provided for.

Claims: A dynamically variable digital delay (114) comprising: a signal source (112) for providing a signal; sampling means (ADC 412) for providing a digital representation of said signal, said sampling means having a signal input (A) for receiving said signal, a digital output (D) for transmitting said digital representation, and a control input (CLK) for receiving a sample rate signal having a variable sample rate for controlling the timing used to generate said digital representation and thus the output rate of said digital representation; a delay FIFO (416) having a data input (DI), a data output (DO), an input enable port (IC) and an output enable port (OC), said data input being coupled to said source for receiving said digital representation from said source; the dynamically variable digital delay (114) being characterised in that there are provided controller means (108) for providing a master clock signal having a constant master clock rate, said controller means being coupled to said output enable port (OC) of said delay FIFO (416) so that said digital representation is transmitted from said data output (DO) at said master clock rate, said controller means providing multiple phases of said master clock; and variable timing means (700) cooperatively coupled to said controller means (108) to select among said multiple phases of said master clock so as to produce a variable timing signal from a signal output (724), said signal output (724) being coupled to said control input (CLK) of said sampling means (ADC 412) for providing said variable sample rate signal thereto, said signal output (724) also being coupled to said input enable port (IC) of said delay FIFO (416) so that said sample rate signal also controls the rate at which said digital representation is input into said delay FIFO (416); whereby, said sampling rate can be varied relative to said master clock rate so that said digital representation can be input to said delay FIFO (416) at a sampling rate which is dynamically variable relative to said master clock rate at which said digital representation is transmitted from said delay FIFO (416). A dynamically variable digital delay as claimed in claim 1, wherein said variable timing means (700) includes a multiplexer (PHASEMUX 710) having signal inputs (8D), said signal output (724) and select inputs (3S), said signal inputs (8D) being coupled to respective ones of said multiple phases so that one of said multiple phases can be selected for transmission from said signal output (724); said variable timing means (700) includes a timing data generator (FOCUS PROM 704) for generating a digital delay data stream (715), said timing data generator (704) having an output enable port (AX) coupled to said controller so that said digital delay data stream is characterised by said master clock rate; and said variable timing means (700) includes a timing FIFO (FOCUS FIFO 706) having a timing data input (D1), a timing data stream (718) output (DO), and an input enable port (IC), said timing data input (DI) being coupled to said timing data generator (704) for receiving said digital delay data stream therefrom, said input enable port (IC) of said timing FIFO (706) being coupled to said controller means (108) so that said digital delay data stream (715) is input into said timing FIFO (706) at said master clock rate, and said select inputs (3S) of said multiplexer (710) being coupled to said timing data stream (718) output (DO) of said timing FIFO (706) so that said timing data stream (718) determines which one of said multiple phases is selected at any given time so that said sample rate (CLK) can be adjusted by progressive phase changes as dictated by said timing data stream (718), said timing FIFO (706) serving as a timing buffer between said master clock rate and said sampling rate. A dynamically variable digital delay as claimed in claim 2, wherein said timing FIFO (706) has an output enable port (OC) which is coupled to said signal output (724) of said multiplexer (710). A dynamically variable digital delay as claimed in claim 2 or claim 3, wherein said variable timing means (700) further includes phase selector means (PHASECOUNTER 708) for providing a select output (720) which varies as a function of said timing data stream (718), said phase selector means (708) being coupled to said timing data output (DO) of said timing FIFO (706) for receiving said timing data stream therefrom, said phase selector means (708) being coupled to said multiplexer (710) for providing said select output (720) to said select inputs (3S) of said multiplexer (710).

Inventors: CORL PAUL D, CORL, PAUL D.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1990
Main classification: G01S15
IPC codes: G10K11, G01S15