MOS-pilot structure for an insulated gate transistor and method of providing a pilot current in such a transistor

Abstract: A MOS-pilot structure for an IGT device consisting of a multiplicity of IGT cells interconnected in a lattice network includes a plurality of pilot emitter electrodes each in electrical contact with only at least one pilot emitter region of a first plurality of the multiplicity of IGT cells and electrically isolated from a common cathode electrode of the multiplicity of IGT cells. The plurality of pilot emitter electrodes are each electrically connected to a contact metal strip deposited on the substrate surface and spaced therefrom by a layer of insulation. The contact metal strip is connected to ground potential through a sense resistor for producing a sense voltage responsive only to the channel currents flowing through the at least one pilot emitter regions; therefore, a MOS pilot structure that utilizes only the MOS channel current to produce the sense voltage to cause turn-off of the IGT device at a large total current is disclosed. The MOS-pilot structure does not suffer from the avalanche breakdown problems during turn-off, that are associated with other prior art IGT pilot structures.

Description: The present invention relates to metal-oxide-semiconductor (MOS) devices and, more particularly, to a novel MOS-pilot structure for providing a pilot current which is an accurate representation of the total current then flowing in an insulated gate transistor (IGT). The total current flowing in an operational IGT consists of two components: the MOS channel current and the bipolar current. The MOS channel current flows in response to a voltage being applied to the gate of the IGT, and the bipolar current is the current which is conducted by the bipolar transistor formed by the lower three semiconductor layers of the IGT when a voltage is also applied to the anode of the IGT. A known prior art IGT pilot structure that allows sensing of the bipolar current has a base region contact connected to ground through a sense resistor. This bipolar pilot is undesirably subject to inaccuracies because the bipolar current may not linearly track the main IGT current due to fluctuations in the gain of the bipolar transistor and because of the recombination of the electrons and holes in the drift region of the IGT substrate, due to the lifetime of the majority and minority current carriers. Additionally, during turn-off the bipolar current can develop an undesirably large potential difference across the sense resistor between the IGT's base region and ground relative to the cathode of the main IGT cell and ground which can cause avalanche breakdown of the main IGT cell. Another IGT pilot structure allows the combined MOS channel current and the bipolar current to be sensed. This MOS-Pilot structure has a common contact electrically connected to both the emitter region and the base region of the IGT and also through a sense resistor to ground. This pilot structure will more accurately track the main IGT current but can also develop the undesirably large potential difference across the sense resistor during turn-off, which can cause avalanche breakdown of the IGT. EP-A-0 139 998 discloses a power semiconductor device which has a plurality of current-carrying cells, a majority of which comprise a main current section and a minority of which comprise an emulation current section. A device termination region surrounds both the main current section and the emulation current section. The current level in the emulation current section closely emulates the current level in the main current section which constitutes only a fraction of that of the main current section. It is accordingly a primary object of the present invention to provide a novel IGT MOS-pilot structure which is not subject to the foregoing disadvantages, is simple in construction and inexpensive to manufacture, and can be provided as a MOS-pilot for a multiplicity of IGT cells interconnected in a lattice structure by modifying the lattice structure. These and other objects of the invention, together with the features and advantages thereof, will become apparent from the following detailed description when read with the accompanying drawings in which like reference numerals refer to like elements. Accordingly, as set out in claim 1, the present invention provides an insulated gate transistor device disposed in a semiconductor substrate having a first substrate surface and a second substrate surface, the said device comprising: a first region of a first conductivity type semiconductor material, terminating at said second substrate surface; a first main electrode electrically connecting said first region to a first terminal of said device; a second region of a second conductivity type semiconductor material, being a drift region, having a first surface physically contacting said first region and having a second surface opposite to said first surface exposed at said first substrate surface; a third region of said first conductivity type semiconductor material, being a base region, disposed in said second region and having a boundary with the second region exposed at said first substrate surface; at least one fourth region of said second conductivity type semiconductor material, disposed in said third region adjacent to a first portion of said third region boundary; a second main electrode electrically connecting all of said at least one fourth regions and the adjacent third region to a second terminal of said device; at least one fifth region of said second conductivity type semiconductor material, disposed in said third region adjacent to a second portion of said third region boundary different from the said first boundary portion; an insulated gate electrode overlying both of said third region boundary portions, as well as an adjacent portion of said second region and an adjacent portion of said third region located between said second region and all of said at least one fourth and fifth regions; whereby a channel current (I MOSa +I MOSb +I MOSc ) is caused to flow through said third region first boundary portion and between said first and second main electrodes, responsive to application of a bias potential between said second main electrode and a gate terminal of said device, connected to said gate electrode; and pilot means electrically connecting all of said at least one fifth regions to a third terminal of said device, thereby providing a pilot current (I P ) flowing through said third terminal, responsive to application of a bias potential to the gate terminal of said device; characterised in that: said pilot means comprises an electrode electrically isolated from said second main electrode and disposed on the said first substrate surface in electrical contact only with all of said at least one fifth regions; whereby the pilot current (I P ) has a magnitude substantially equal to a fixed proportion of the said channel current (I MOSa +I MOSb +I MOSc ) then flowing. Particular embodiments of the transistor of the invention are disclosed in dependant claims 2-9. Further, the present invention provides a method of providing a pilot current in the insulated gate transistor device according to the embodiment disclosed in any of claims 4-9, as set out in claim 10. The description and drawings relate to an embodiment of the invention in which a MOS-pilot structure for sensing total current flow through a multiplicity of IGT cells formed in a lattice network includes a plurality of pilot emitter electrodes, each in electrical contact with at least one pilot emitter region of a first plurality of the multiplicity of IGT cells. A metal contact strip electrically connects each of the plurality of emitter electrodes and the metal strip is connected to ground through a sense resistor. Each of the first plurality and a second plurality of the multiplicity of IGT cells includes a region of a first conductivity type having one surface in contact with a first main electrode for connecting the device to an external circuit. A drift region of a second conductivity type overlies and contacts another surface of the said region. A base region of the first conductivity type is formed in the drift region, with a plurality of emitter regions of the second conductivity type being formed in the base region. The emitter regions are spaced from the drift region by a base region boundary portion. An insulated gate electrode overlies all of the drift region, the base region boundary portion and a segment of each emitter region, to cause formation of a channel across the gate region boundary portion when a voltage is applied to the gate to permit channel current to flow between the drift region and the emitter regions. A voltage is produced across the sense resistor by the channel current flowing from the at least one pilot emitter region of the first plurality of IGT cells to ground through the sense resistor. The resistor voltage can be compared to a reference voltage to cause the IGT cells to be turned-off when the resistor voltage exceeds the reference voltage level. The MOS-pilot structure, as defined above, provides an indication of the total current flowing through the device by sensing only the magnitude of the channel current flowing in the at least one pilot emitter region of the first plurality of IGT cells. The combined channel currents, flowing in each of the at least one pilot emitter regions and in the MOS-pilot structure, defines a pilot current. Since the total number of cells of the first plurality and the total number of cells of a second plurality of the multiplicity of IGT cells are known, the ratio of pilot current to the total current flowing in the device is established; therefore, a large pilot current, corresponding to a proportionally large total current, produces a large voltage across the sense resistor to cause the IGT cells to be turned-off if the reference voltage level is exceeded. A method for providing a MOS-pilot structure for a multiplicity of IGT cells formed in a lattice network, includes the steps of: designating at least one emitter region of each of a first plurality of the multiplicity of IGT cells; depositing a plurality of pilot emitter electrodes in electrical contact with each of the at least one designated emitter regions; and fabricating a metal contact strip connected to the plurality of pilot emitter electrodes and electrically isolated from a second main electrode of the multiplicity of IGT cells, to facilitate electrical connection to the pilot structure. The metal contact strip can be electrically connected to ground through a sense resistor to provide a voltage across the sense resistor responsive to channel current flow. In the accompanying drawings: Figure 1 is a cross-sectional view of a prior art MOS-pilot structure for sensing bipolar current. Figure 2 is a cross-sectional view of a prior art MOS-pilot structure for sensing combined MOS channel and bipolar currents. Figure 3 is a plan view of a portion of a prior art lattice network of IGT cells. Figures 4, 5 and 6 are cross-sectional views through the prior art lattice network of figure 3 taken along lines 4-4, 5-5 and 6-6, respectively. Figure 7A is a schematic plan view of a lattice network of IGT cells with a MOS-pilot structure in accordance with the present invention. Figure 7B is a detailed plan view of a portion of the lattice network of Figure 7A. Figure 8A is a cross-sectional view of the lattice network of Figure 7B taken along line 8A-8A. Figure 8B is a cross-sectional view of the lattice network of Figure 7B taken along line 8B-8B . Referring now to Figure 1, a prior art device 10 has a MOS-pilot structure for sensing bipolar current I bip , which is the current conducted by the bipolar transistor formed by the lower three semiconductor layers of an IGT. Device 10 includes a semiconductor substrate 12 having a principal substrate surface 14 and a region 16 of a first conductivity type semiconductor material (e.g. N type cathode region). Region 16 has a bottom surface 18 which is also the bottom surface for semiconductor substrate 12 opposite principal substrate surface 14. A main electrode 20 is deposited on bottom surface 18 and a main terminal 20a is provided for connecting the device to an exterior circuit. A drift region 22 of a second conductivity type semiconductor material (e.g. P type) abuts against another region surface 17 opposite bottom surface 18. Drift region 22 may have a lightly doped upper portion 22a and a more heavily doped lower portion 22b to provide a higher breakdown voltage and a lower forward voltage drop when device 10 is operational. An annular base region 24 of the first type conductivity is formed in drift region 22; an opening 26 is formed through the center of the base region 24 so that a portion 23 of drift region 22 extends to principal substrate surface 14 (in opening 26). An emitter region 28, of the second conductivity type, is formed in one base region portion 24a immediately below principal surface 14 and at sufficient spacing from the adjacent drift region portion 23 to provide a base region boundary portion 30 between emitter region 28 and drift region portion 23. A gate electrode 32 is disposed adjacent substrate surface 14 and is separated therefrom by a layer of insulative material 34. A gate terminal 32a is provided for connecting gate electrode 32 to an external circuit. Gate electrode 32 overlies all of: drift region portion 23, boundary portion 30 and a segment of emitter region 28. The presence of a voltage on gate electrode 32, with respect to a first electrode 36 (contacting emitter region 28), causes a channel 37 (shown with broken line boundary) to be created across base region boundary portion 30 to permit channel current I MOS to flow between drift region 22 and emitter region 28, when the biasing voltage is of proper amplitude and polarity. The first electrode 36 is electrically connected to both emitter region 28 and to the adjacent base region portion 24a and is further connectable to an external ground potential through a terminal 36a. A second electrode 38 is connected to another base region portion 24b and is connectable to ground potential through a terminal 38a and through a sensing resistor 40. Bipolar current I bip will flow from ground, through resistor 40 and via second electrode 38 through the device, to main electrode 20; channel current I MOS and bipolar current I′ bip will flow from ground, through the device via first electrode 36, to main electrode 20, during operation of device 10. The total current I a flowing through the device is then the summation of these currents as shown in Figure 1, i.e., I a = I MOS + I′ bip + I bip . Bipolar current I bip flowing through resistor 40 creates a sense voltage V sense across the resistor which provides an indication of the magnitude of the main current I a and therefore the total current flowing through the entire device 10. The sense voltage can be compared to a reference voltage and the device can be turned-off if the sensed voltage exceeds the reference voltage. This method of predicting the total current flow through device 10 by sensing the bipolar current I bip may be inaccurate because the bipolar current may not linearly track the total device current I a due to gain fluctuations in the bipolar transistor formed by base region portion 24b, drift region 22 and anode region 16. These gain fluctuations may be attributed to debris deposited in the vicinity of a PN junction 42, formed between drift region 22 and region 16, at the edges of semiconductor substrate 12 during the fabrication of device 10. The gain of the bipolar transistor and the accuracy with which the bipolar current I bip will track the total current I a in the device may also be affected by the recombination activity of the electrons and holes in drift region 22. Additionally, during turn-off of the device a large potential difference can be created across resistor 40, due to the large potential difference between contact 38 and ground, relative to the ground potential at contact 36, to cause avalanche breakdown to occur across any reverse-biased PN junctions in the device. Referring now to Figure 2, another prior art device 10′ has a MOS-pilot structure that also allows sensing of the combined MOS channel current I MOS and bipolar current I bip . This device 10′ includes substantially all of the regions of the device 10 of Figure 1 and also has at least one additional emitter region 46 formed in other base region portion 24b′ (separate from emitter region 28′), and at a spacing from drift region portion 23′ to provide another base region boundary portion 48 therebetween. Base region boundary portions 30′ and 48, respectively, may be more lightly doped than respective base regions 24a′ and 24b′, to increase the breakdown voltage along respective PN junctions 49a and 49b in the vicinity of base region boundary portions 30′ and 48, respectively. Gate electrode 32′, disposed adjacent substrate surface 14′ and separated therefrom by insulation layer 34′, overlies all of: drift region portion 23′; boundary portions 30′ and 48 and a segment of each of emitter regions 28′ and 46, to cause channels 37′ and 47 (shown with broken line boundaries) to be created across base region boundary portions 30′ and 48, respectively, to permit channel current I′ MOS to flow between drift region portion 23′ and emitter region 28′ and to permit channel current I MOS to flow between drift region portion 23′ and emitter region 46, when a biasing voltage of proper amplitude and polarity is applied to gate electrode 32′ through terminal 32′a. Second electrode 38′ is electrically connected to both emitter region 46 and base region 24b′ of the device, so that both MOS channel current I MOS and bipolar current I bip will flow through resistor 40′ when device 10′ is operational. Second electrode 38′ is connected to resistor 40′ by terminal 38′ a. The voltage V′ sense sense across resistor 40′ caused by these combined currents may be compared to a reference voltage and if that reference voltage is exceeded, device 10′ may be turned-off. This prior art pilot structure, for sensing the combined MOS channel and bipolar currents to obtain an indication of the magnitude of the main current I′ a passing through the IGT, has inherent inaccuracies for the same reasons as discussed with regard to the bipolar pilot of Figure 1. Additionally, bipolar current may continue to flow through resistor 40′ during device turn-off and a large potential difference can exist between second electrode 38′ and ground, relative to the ground potential at first electrode 36′. This potential difference can be of sufficient magnitude to cause avalanche breakdown of those PN junctions within the device which are reverse-biased. Another prior art device 50, shown in Figure 3, includes a multiplicity of interconnected IGT cells formed in a lattice network. The IGT cells are generally interconnected by their gate electrodes 64, a common anode electrode (not shown in Figure 3) and a common cathode electrode (not shown in Figure 3) so that multiple cells may be utilized together to improve the voltage and current capacity of the overall device. While individual cells are shown to be substantially circular shaped, other geometric shapes could be utilized as well. Figures 4, 5 and 6 show cross-sections of the lattice network of Figure 3 taken along lines 4-4, 5-5, and 6-6, respectively. Referring initially to Figures 3 and 4, the lattice structure is formed in a semiconductor substrate 52 having a principal substrate surface 54. Substrate 52 includes a region 56 of a first conductivity type (e.g. N+ type cathode region) which terminates at a substrate bottom surface 58. A main electrode 60 is in electrical contact with region 56 at bottom surface 58 and a drift region 62 of a second conductivity type (e.g. P type) overlies and contacts region 56 at a surface 63 opposite bottom surface 58. Drift region 62 may have a lightly doped upper portion 62a and a more heavily doped lower portion 62b to provide a high breakdown voltage and a lower forward voltage drop when device 50 is operational. A plurality of gate electrodes 64 are disposed adjacent principal substrate surface 54 and spaced therefrom by a layer of insulation 66. Adjacent gate electrodes are interconnected by gate bridges 68 which are best shown in Figures 3 and 6. Gate bridges 68 are also spaced from substrate surface 54 by insulation layer 66. Insulation layer 66 is not shown in Figure 3 for sake of clarity. A base region 70 of the first conductivity type is diffused into drift region 62 through openings 72 formed in principal substrate surface 54 between gate electrodes 64 and gate bridges 68; base region 70 is laterally diffused under gate bridges 68 and partially under gate electrodes 64, as best shown in Figures 4 and 6. Base region portion 70a, partially diffused under gate electrodes 64 in Figure 4, and base region portion 70b, laterally diffused under gate bridges 68 in Figure 6, may both be more lightly doped relative to the remainder of base region 70 to improve the breakdown voltage of the PN junction between base region 70 and that portion of drift region 62 near principal substrate surface 54. Gate electrodes 64 act as a mask during diffusion of base region 70 and therefore a plurality of openings 74 are formed in base region 70 under gate electrodes 64; a drift region portion 75 extends through each of openings 74 to substrate surface 54. A plurality of emitter regions 76 of the second conductivity type are diffused into base region 70 through openings 72. Emitter regions 76 are also laterally diffused partially under gate electrodes 64 as shown in Figure 4 and are each spaced from drift region portion 75 by a base region boundary portion 78. A main electrode 80, for making electrical connections to the IGT cells of structure 50, is disposed on principal substrate surface 54 and in electrical contract with base region 70 and with emitter regions 76 at openings 72. Main electrode 80 may extend between adjacent openings 72 over gate electrodes 64 and gate bridges 68, and is maintained at a spacing therefrom by insulation layer 66′. Main electrode 80 is not shown in Figure 3 for sake of clarity. A more detailed discussion of the lattice structure of figures 3-6 is contained in our US Patent No. 4 823 176, the disclosure in which is incorporated herein by reference. The IGT cells become operational when a negative potential is applied to gate electrodes 64 and to main electrode 60, with respect to the main electrode 80 potential. The negative voltage applied to gate electrodes 64 enhances a channel 82 (shown with broken line boundary in Figure 4) across base region boundary portions 78 to permit channel current flow from emitter region 76 to drift region 62 and the negative voltage applied to main electrode 60 causes current to flow to main electrode 60 from main electrode 80 through the bipolar transistor formed by region 56, drift region 62 and base 70. This current is the bipolar current-I bip and is related to the MOS channel current-I MOs by the gain β of the bipolar transistor, i.e., I bip =β I MOS . The total current I T through the IGT is the sum of the MOS channel current I MOS and the bipolar current I bip ; therefore, I T =(1+β)I MOS . In accordance with an embodiment the present invention, as shown in Figure 7A, a device 100 includes a MOS-pilot structure for a multiplicity of IGT cells formed in a lattice network, or cell array. The multiplicity of IGT cells includes a first plurality of IGT cells 102 (within the broke line boundary) and a second plurality of IGT cells 104 (outside the broken line boundary). For explanatory purposes, only the gate electrodes 106 and gate bridges 108 interconnecting adjacent gate electrodes are shown in Figure 7A. The pilot structure includes a portion of at least one column 110 (or row or diagonal) of the array of IGT cells formed without any gate electrodes, and which may be referred to as a gateless column (or gateless row). The first plurality of IGT cells 102 are then the IGT cells in the columns immediately adjacent to gateless column 110. The MOS-pilot structure 112 will be discussed in detail hereinbelow, but basically includes a strip of contact metal 114 deposited along the principal substrate surface (not shown) of gateless column 110 and used with a plurality of contact metal bridges 116 to electrically connect each of a plurality of emitter electrodes 118, each in electrical contact with at least one emitter region (not shown) of each of the first plurality of IGT cells 102, to a pad 120, of contact metal. Contact metal strip 114, metal bridges 116 and pad 120 are electrically isolated from the principal substrate surface. Pad 120 may be integrally formed with contact metal strip 114 on the principal substrate surface proximate to one edge of the substrate, to facilitate electrical connection of contact metal strip 114, to some other element, e.g., to ground potential through a sense resistor 122. Sense resistor 122 may be either an externally connected resistor or integrally formed with device 100 during the fabrication process, in a manner well known in the art, to form a completely packaged device. Contact metal strip 114, contact metal bridges 116 and emitter electrodes 118 may be formed from an alloy of aluminum and 0.5% by weight of copper. Other contact metal compositions may be used as well, provided that the compositions utilized exhibit a good ohmic connection to the emitter regions of first plurality 102 and do not present electro-migration problems when the device is annealed or sintered. Figure 7B is a plan view of a portion of the lattice network of Figure 7A showing in detail a portion of the gateless column 110 and the interconnection of contact metal strip 114, contact metal bridges 116 and emitter electrodes 118 to at least one emitter region 124′ of each IGT cell of first plurality 102. Emitter electrodes 118 may also be called pilot emitter electrodes and the at least one emitter regions 124′ may be referred to as pilot emitter regions. Contact metal strip 114 and contact metal bridges 116 are deposited on the principal substrate surface and spaced therefrom by a layer of insulation 126. Windows are formed in insulation layer 126 over pilot emitter regions 124′ of first plurality 102 to permit pilot emitter electrodes 118 to be deposited in electrical contact with only pilot emitter regions 124′. Pilot emitter electrodes 118 and the remaining MOS-pilot structure metallization must not contact base region 128 into which pilot emitter regions 124′ are diffused. Pilot emitter electrodes 118 are substantially arcuately shaped to correspond to the arcuate shape of pilot emitter regions 124′ which are diffused around circularly shaped gate electrodes 106 into base region 128. While the gate electrodes and IGT cells are represented in Figure 7B as being substantially circular in shape, other geometric configurations may also be used. First plurality of cells 102 and second plurality of cells 104 of the multiplicity of IGT cells are preferably formed at the same time during the fabrication process and have similar structures; therefore, the two structures will be described simultaneously and the differences will be pointed out with reference to Figures 8A and 8B. The structure of the second plurality of cells 104 can be similar to that of the prior art device of Figures 3-6. Figure 8A shows one IGT cell 104 of the second plurality, in a cross-sectional view taken along line 8A-8A in Figure 7B and Figure 8B shows one IGT cell 102 of the first plurality, in a cross-sectional view taken along line 8B-8B in Figure 7B. The first plurality of IGT cells and the second plurality of IGT cells are formed in a common semiconductor substrate 130 which has a principal substrate surface 132 and a bottom substrate surface 134. A region 136 of a first conductivity type semiconductor material (e.g. N+ cathode region) is formed in substrate 130 and terminates at bottom surface 134. A main electrode 138 is in electrical contact with region 136 at bottom surface 134 and a drift region 140 of a second conductivity type semiconductor material (e.g. P) overlies and contacts region 136 at a surface 142 opposite bottom surface 134. A first terminal 138a is provided for connecting main electrode 138 to an external circuit. Drift region 140 may have a lightly doped upper portion 140a and a more heavily doped lower portion 140b to provide a high breakdown voltage and a lower forward voltage drop when the array of IGT cells are operational. As previously discussed with respect to Figure 7A, a plurality of gate electrodes 106 are disposed adjacent principal substrate surface 132 and spaced therefrom by a layer of insulation 144. The gate electrodes 106 and interconnecting gate bridges 108 form a mask having a plurality of openings or windows 146 as best shown in Figures 7A and 7B. Base region 128 of the first conductivity type semiconductor material is diffused into drift region 140 through windows 146 formed between gate electrodes 106 and gate bridges 108; base region 128 is laterally diffused under gate bridges 108 (not shown) and laterally diffused, partially under gate electrodes 106 as shown in Figure 8A. Base region 128 may be a single region or a plurality of separate base regions if base region 128 is not laterally diffused under gate bridges 108 to join adjacent regions. Base region portions 152a, 152b, 152c and 152d which are partially diffused under gate electrode 106 may be more lightly doped, relative to the remainder of base region 128, to improve the breakdown voltage along PN junction 148 near principal substrate surface 132. A plurality of openings 150 are formed in base region 128, under gate electrodes 106 (during the diffusion of base region 128) as a result of the masking effect of gate electrodes 106; each drift region 140 has a portion 141 extending through one of openings 150 to substrate surface 132. A plurality of emitter regions 124 and pilot emitter regions 124′ (in first plurality cells 102) of the second conductivity type semiconductor material are diffused into base region portions 128a, 128b, 128c and 128d, respectively, through windows 146, and are positioned in a substantially arcuate arrangement around each gate electrode 106, as best shown in Figure 7B. Base region portions 128a, 128b, 128c and 128d may be portions of a single base region or may each be a portion of a separate base region of a plurality of base regions if base region 128 is not laterally diffused under gate bridges 108 to join adjacent separate base regions into a single region as described hereinabove. As best seen in Figures 8A and 8B, each emitter region 124 and pilot emitter region 124′ is laterally diffused, to partially extend under gate electrode 106, and is spaced from drift region portion 141 by intervening base region boundary portions 152a, 152b, 152c and 152d, respectively. Pilot emitter regions 124′ of first plurality of IGT cells 102, which are to form MOS-pilot structure 112, may be increased in size along principal substrate surface 132, as shown in Figure 8B, by diffusing additional P+ material through opening 146 and into base portion 128d or by providing a bigger window 146 in the mask when the plurality of emitter regions 124 and pilot emitter regions 124′ are originally diffused into base region 128. The increased area of pilot emitter region 124′ exposed at principal substrate surface 132 will facilitate the deposition of pilot emitter electrode 118 and improve the ohmic contact between pilot emitter region 124′ and pilot emitter electrode 118, when emitter electrode 118 is deposited in contact with emitter region 124′ as shown in Figure 8B. Referring to Figures 8A and 8B, a main electrode 154 (not shown in Figures 7A and 7B) is disposed on principal substrate surface 132 and electrically contacts both base region or regions 128 and emitter regions 124 of second plurality cells 104, through openings 146. Main electrode 154 is also disposed on principal substrate surface 132 in electrical contact with base region 128 and with emitter regions 124 of the first plurality 102 of IGT cells but is not in contact with pilot emitter regions 124′. Main electrode 154 may extend between adjacent openings 146, over gate electrodes 106 and gate bridges 108, and is maintained at a spacing from gate electrodes 106 and gate bridges 108 by insulation layer 144′. A portion 154a of the main electrode 154 (shown in phantom in Figure 8A) would not be deposited on (or would be removed from) substrate surface 132 at opening 146 if a first plurality IGT cell 102 is to be formed so that pilot emitter electrode 118 may be formed separately from main electrode 154. Main electrode 154 is connected to a second device terminal 155 for electrically connecting main electrode 154 to an external circuit. Referring now to Figure 8B, in accordance with an embodiment of the present invention, pilot emitter electrode 118 is deposited on substrate surface 132 in electrical contact with only pilot emitter region 124′. As previously described with respect to Figures 7A and 7B, emitter electrode 118 is connected to ground potential through an electrical path which includes contact metal bridge 116, contact metal strip 114, pad 120, a third device terminal 120a and sense resistor 122 (shown in phantom in Figure 8B). The MOS-pilot structure metallization (which includes emitter electrodes 118, contact metal bridges 116 and contact metal strip 114) may be formed during the same process step as main electrode 154 to form a single metallization pattern, or may be formed in another process step and may be deposited over portions of main electrode 154, as required, to define a dual level metallization pattern. In any event, the MOS-pilot structure metallization of pilot emitter electrodes 118 and pilot emitter regions 124′ are connected together, but both must be electrically isolated from main electrode 154, as by a layer 156 of insulation (Figure 8B). Main electrode 154 is electrically connected to ground as shown in Figure 8B through terminal 155 to maintain base region 128 and emitter region 124 at ground potential. Referring back to Figure 8A, in operation, channels 158a and 158b will be increasingly enhanced across base region boundary portions 152a and 152b, respectively, when an increasingly negative voltage is applied to gate electrode 106, with respect to main electrode 154, through gate terminal 106a. MOS channel currents I MOSa and I MOSb will then flow through channels 158a and 158b, from emitter regions 124, to drift region portion 141. Similarly, referring to Figure 8B, channels 159a and 159b will be increasingly enhanced across base region boundary portions 152d and 152c, respectively, and MOS channel currents I′ MOS and I MOSc will respectively flow through channels 159a and 159b when the increasingly negative voltage is applied to gate electrode 106, with respect to main electrode 154. MOS channel current I′ MOS will further flow to pilot emitter region 124′ from ground through an electrical path comprising pilot emitter electrode 118, contact metal bridges 116, contact metal strip 114, third terminal 120a and sense resistor 122. The magnitude of the voltage across the resistor 122 will be a function of the resistance of resistor 122 and the pilot current I p , which is the combined channel currents I′ MOS flowing to those pilot emitter regions 124′ selected to be interconnected to contact metal strip 114. The voltage created across resistor 122, by pilot current I p , may be used as required, e.g., may be compared to a reference voltage and, if the reference voltage is exceeded, device 100 may be turned-off to protect the device from damage. Since the voltage across resistor 122 is a function of only the MOS channel current I′ MOS and the resistance of resistor 122, and not the bipolar current I bip (conducted by the bipolar transistor formed by the combination of base region 128, drift region 140 and region 136), the MOS-pilot structure of device 100 is not subject to the inaccuracies and avalanche breakdown problems associated with the prior art MOS-pilots previously discussed. While the present invention was described with each semiconductor region having a particular type of conductivity, opposite conductivities could be used as well with corresponding opposite polarities of voltage and opposite directions of current flow.

Claims: An insulated gate transistor device (100) disposed in a semiconductor substrate (130) having a first substrate surface (132) and a second substrate surface (134), the said device (100) comprising: a first region (136) of a first conductivity type semiconductor material, terminating at said second substrate surface (134); a first main electrode (138) electrically connecting said first region (136) to a first terminal (138a) of said device (100); a second region (140) of a second conductivity type semiconductor material, being a drift region, having a first surface (142) physically contacting said first region (136) and having a second surface opposite to said first surface (142) exposed at said first substrate surface (132); a third region (128) of said first conductivity type semiconductor material, being a base region, disposed in said second region (140) and having a boundary (148) with the second region (140) exposed at said first substrate surface (132); at least one fourth region (124) of said second conductivity type semiconductor material, disposed in said third region (128) adjacent to a first portion (152a,152b,152c) of said third region boundary (148); a second main electrode (154) electrically connecting all of said at least one fourth regions (124) and the adjacent third region (128) to a second terminal (155) of said device (100); at least one fifth region (124′) of said second conductivity type semiconductor material, disposed in said third region (128) adjacent to a second portion (152d) of said third region boundary (148) different from the said first boundary portion (152a,152b,152c); an insulated gate electrode (106) overlying both of said third region boundary portions (152a,152b,152c,152d), as well as an adjacent portion of said second region (140) and an adjacent portion of said third region (128) located between said second region (140) and all of said at least one fourth and fifth regions (124,124′); whereby a channel current (I MOSa +I MOSb +I MOSc ) is caused to flow through said third region first boundary portion (152a,152b,152c) and between said first and second main electrodes (138,154), responsive to application of a bias potential between said second main electrode (154) and a gate terminal (106a) of said device (100), connected to said gate electrode (106); and pilot means (118,116,114,120) electrically connecting all of said at least one fifth regions (124′) to a third terminal (120a) of said device (100), thereby providing a pilot current (I P ) flowing through said third terminal (120a), responsive to application of a bias potential to the gate terminal (106a) of said device (100); characterised in that: said pilot means (118,116,114,120) comprises an electrode (118) electrically isolated from said second main electrode (154) and disposed on the said first substrate surface (132) in electrical contact only with all of said at least one fifth regions (124′); whereby the pilot current (I P ) has a magnitude substantially equal to a fixed proportion of the said channel current (I MOSa +I MOSb +I MOSc ) then flowing. The device of Claim 1, characterised in that the third region is a single region. The device of Claim 1, characterised in that: the third region is composed of a first base region and at least one other, separate base region, having respective first and second boundaries with the second region exposed at said first substrate surface; the at least one fourth region is disposed in said at least one separate base region, the said first portion of the third region boundary being a portion of the said second, separate base region boundary; the second main electrode electrically connects the at least one fourth region and the adjacent separate base region to the second terminal of the said device; all of the at least one fifth regions are disposed in said first base region, the said second portion of the third region boundary being a portion of the said first base region boundary. The device of Claim 2, characterised in that: the third region has a multiplicity of openings (150) therein, with each opening occupied by a portion (141) of said second region; the said device is composed of a multiplicity of interconnected cells disposed in a lattice structure and having the first, second and third regions and the first main electrode in common, and comprising a first plurality of cells (102); each cell of the said first plurality (102) includes: (a) a different first one of said portions (141) of second region; (b) at least one of said at least one fourth regions disposed adjacent said first one of said portions (141) of second region, (c) a portion of the second main electrode, (d) at least one of said at least one fifth regions disposed adjacent said first one of said portions (141) of second region, (e) a portion of the said gate electrode which overlies the part of the said third region located between the said first one of said portions (141) of second region and all of said at least one of said at least one fourth and fifth regions, as well as at least the part of the said first one of said portions (141) of second region adjacent to said part of the third region; whereby the said pilot current (I P ) has a magnitude substantially equal to a fixed proportion of the sum of all channel currents (I MOSc ) then flowing in the cells of said first plurality of cells (102). The device of Claim 4, characterised in that: it comprises a second plurality (104) of said multiplicity of cells, different from said first plurality (102); each cell of the second plurality (104) includes: (a) a different second one of said portions (141) of second region, (b) at least one of said at least one fourth regions disposed adjacent said second one of said portions (141) of second region, (c) a portion of the second main electrode, (d) none of said at least one fifth regions, (e) a portion of the said gate electrode which overlies the part of the said third region located between the said second one of the said portions (141) of second region and all of said at least one of said at least one fourth regions, as well as at least the part of the said second one of said portions (141) of second region adjacent to said part of the third region; whereby the said pilot current (I P ) has a magnitude substantially equal to a fixed proportion of the sum of all channel currents (I MOSa , I MOSb , I MOSc ) then flowing in the cells of said first and second plurality of cells (102). The device of Claim 3, characterised in that: the third region is composed of a plurality of base regions having a multiplicity of openings (150) therebetween, with each opening occupied by a portion (141) of said second region; the said device is composed of a multiplicity of interconnected cells disposed in a lattice structure and having the first, second and third regions and the first main electrode in common, and comprising a first plurality of cells (102); each cell of the said first plurality (102) includes: (a) a different first one of said portions (141) of second region, (b) at least one of said at least one fourth regions disposed adjacent said first one of said portions (141) of second region in one of said at least one separate base regions, (c) a portion of the second main electrode, (d) at least one of said at least one fifth regions disposed adjacent said first one of said portions (141) of second region in said first base region, (e) a portion of the said gate electrode which overlies the part of the said first base region and that of the at least one separate base region located between the said first one of said portions (141) of second region and all of said at least one of said at least one fourth and fifth regions, as well as at least the part of the said first one of said portions (141) of second region adjacent to the said parts of the said first and at least one separate base regions; whereby the said pilot current (I P ) has a magnitude substantially equal to a fixed proportion of the sum of all channel currents (I MOSc ) then flowing in the cells of said first plurality of cells (102). The device of Claim 6, characterised in that: it comprises a second plurality (104) of said multiplicity of cells are provided, different from said first plurality (102); each cell of the second plurality (104) includes (a) a different second one of said portions (141) of second region, (b) at least one of said at least one fourth regions disposed adjacent said second one of said portions (141) of second region in a further one of said at least one separate base regions, (c) a portion of the second main electrode, (d) none of said at least one fifth regions, (e) a portion of the said gate electrode which overlies the part of the said further one of said at least one separate base regions located between the said second one of said portions (141) of second region and all of said at least one of said at least one fourth regions, as well as at least the part of the said second one of said portions (141) of second region adjacent to said part of the said further one of said at least one separate base regions; whereby the said pilot current (I P ) has a magnitude substantially equal to a fixed proportion of the sum of all channel currents (I MOSa ,I MOSb ,I MOSc ) then flowing in the cells of said first and second plurality of cells (102). The device of any preceding claim, characterised in that said pilot means further include means (122) producing a sense voltage responsive to the pilot current (I P ) flowing through said third terminal (120a). The device of Claim 8, characterised in that said means producing a sense voltage is a sense resistor (122) electrically connected to said pilot electrode (118). A method of providing a pilot current in an insulated gate transistor device (100) according to any of claims 4 to 9, which device is accordingly composed of a multiplicity of interconnected cells disposed in a lattice structure and having the first, second and third regions and the first main electrode in common and comprising a first plurality of cells (102), each cell of the said first plurality including a gate electrode portion and at least one fourth region (124), said method comprising the steps of: designating, in at least one selected cell, at least one of the fourth regions (124) as a pilot region (124′); connecting a pilot electrode (118), separate and electrically isolated from the second main electrode (154), between each designated pilot region and the said third terminal (120a) of the device, and disposed on the said first substrate surface (132) in electrical contact only with each designated pilot region (124′); causing a total channel current to flow through the said second device terminal (155); whereby a pilot current (I P ), having a magnitude substantially equal to a fixed proportion of the sum of the total channel current then flowing, simultaneously flows through the said third terminal (120a). The method of claim 10, further comprising the step of producing a sense voltage responsive to the pilot current (I P ) flowing through said third terminal (120a). The method of claim 10, wherein the cells of the said multiplicity of cells are interconnected in rows and columns defining the said lattice structure and wherein a plurality of gate bridges (108) interconnect the said gate electrode portions (106) of adjacent cells, said method further comprising the steps of: avoiding forming a selected number of cells of a selected one (110) of a column and a row of the lattice structure, whereby a corresponding gateless portion of the said one (110) of a column and a row is obtained, which has no gate electrode portion (106) and no associated gate bridges (108); depositing a conductive contact strip (114) on the said first substrate surface (132) along the said gate-less portion of the said one (110) of a column and a row, said conductive contact strip (114) electrically connecting each of the pilot electrodes (118); wherein: the designating step includes the step of selecting at least one cell immediately adjacent to the selected gateless portion of the said one (110) of a column and a row; and the connecting step includes electrically connecting the said conductive contact strip (114) only between each pilot electrode (118) and the said third terminal (120a) of the device.

Inventors: BALIGA BANTAVAL JAYANT, PATTANAYAK DEVA NARAYAN, BALIGA, BANTAVAL JAYANT, PATTANAYAK, DEVA NARAYAN
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1990
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27