Method for correcting waveform data in digital signal modulation and base band signal generator using data provided by this method

Abstract: This invention relates to a method for correcting quantized waveform data which are made by a process of quantizing a base band waveform, so optimized as to make a sum of errors included in a single bit range of input digital data smaller than one quantizing step, and are output as the base band waveform which is to be accumulated or integrated in the requirement of the system (such as frequency-to-phase conversion). Since an accumulated sum of the quantized waveform data has some error from the real base band waveform when those quantized waveform data are accumulated so as to generate phase information from frequency information, the quantized waveform data have to be corrected previously. For the purpose of restraining the accumulated error, this method has the steps of defining states corresponding to input data patterns, establishing simultaneous equations corresponding to state transition routes respectively, solving the equations, and deciding correcting values to the quantized data.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for correcting waveform data in digital signal modulation and, more particularly, to a method for correcting waveform data stored in a base band generator of a digital modulator so as to reduce an accumulated error (The method is hereinafter referred to as the waveform data correction method.), and a base band signal generator using data provided by the method. Description of the Prior Art Fig. 1 is a block diagram showing a base band waveform generator in a quadrature modulation type digital FM modulator. In the figure, numeral 1 is a shift register (an element that can make reference to consecutive data) for storing a binary digital signal (input data) consecutively. Numeral 2 is a waveform memory for storing waveform data obtained by quantizing a base band waveform and outputting a waveform similar to the base band waveform. Numeral 3 is a counter for counting a clock signal. Numeral 4 is an adder for adding the waveform data output from the waveform memory 2 to the output data from a latch circuit 5. The latch circuit latches the output data from the adder 4 and supplies the data back to the adder 4. The adder 4 and the latch circuit 5 constitute an integrator that add up consecutively the waveform data coming out of the waveform memory 2. Numeral 6a is a COS-ROM for converting the output data from the adder 4 into an I signal (in-phase signal). Numeral 6b is a SIN-ROM for converting the output data from the adder 4 into a Q signal (quadrature-phase signal). Numerals 7a and 7b are D-A converters for converting the I signal and the Q signal into an analog waveform each, respectively. Numerals 8a and 8b are low-pass filters (LPF) for shaping a waveform output from the respective D-A converters. Numerals 9a and 9b are respectively an I output and a Q output, being fed to the quadrature modulator (not shown in this figure). In the setup described above, the waveform memory 2 stores a quantized base band waveform as waveform data. This means that the waveform data contains a quantization error. As the waveform data from the waveform memory 2 are added up by the adder 4, the quantization errors involved are accumulated. To eliminate the accumulated quantization errors requires suitable arrangements for error correction. There is known a method in which the waveform data stored in the waveform memory 2 are previously corrected. Fig. 3 is a flowchart showing how this kind of correction is done. What follows is a description of how the base-band generator works and how the waveform data is corrected thereby. First, the operation of the base band generator is explained. Where the modulation process involves the so-called intersymbol interference, input data is stored in the shift register 1. A base band waveform corresponding to all the patterns of the data stored in the shift register 1 is stored in the waveform memory 2 as quantized values obtained by sampling the base band waveform at a rate of n times the bit rate. Thus a clock signal generated at the rate of n times the bit rate is counted by the n-based counter 3. Every time a counted value reaches n, the shift register 1 shifts the input data. The waveform memory 2 is arranged to output waveform data every time the counter 3 counts one clock pulse. The waveform data from the waveform memory 2 are added up consecutively, i.e., integrated, by the adder 4 and the latch circuit 5. In this manner, frequency information is converted to phase information. The phase information thus obtained is converted by the COS-ROM 6a and the SIN-ROM 6b into the I signal and Q signal for quadrature modulation. The two signals are then converted to analog signals by the D-A converters 7a and 7b. After waveform shaping by the LPF's 8a and 8b, the I output 9a and the Q output 9b are output as analog signals. Fig. 2 illustrates a typical relationship between a base band waveform 10 and waveform data 11b. The waveform memory 2 outputs a quantized base band waveform 11a similar to the base band waveform 10. That is, the waveform data 11b is stored at an address specified by the value in the shift register 1 and by the value in the counter 3. In Fig. 2, it is assumed that sixteen items of waveform data 11b correspond to a single bit interval of input data (i.e., n = 16). In this case, the value obtained by the adder 4 adding up the sixteen items of waveform data 11b is so optimized as to fall within the width of one quantize step with respect to the value obtained by adding sixteen sampled values. That is, sixteen items of waveform data 11b in a single bit interval of input data are arranged so that the added value of waveform data 11b keyed to the single bit interval has its error fall within one quantized step with respect to the base band waveform. For example, adding up the sixteen items of waveform data 11b in Fig. 2 provides a value of 89. With this value, the quantization error with respect to the base band waveform 10 is within one quantization step. As described above, as far as waveform data 11c in a single bit interval is concerned, it is relatively easy not to let the accumulated error from additions exceed the quantization step width. When waveform data 11c of multiple bits is consecutively added, there is a possibility that the accumulated error may exceed the quantization step width. To eliminate the error simply requires correcting a number of waveform data items. Fig. 3 is a flowchart outlining the conventional error correction method. In step ST30, a state transition diagram is prepared. Fig. 4 is a state transition diagram in effect where the shift register 1 has three shift stages. In Fig. 4, there exist eight states according to the bit patterns in the shift register 1. In this figure, a value parenthesized on the right of Jn (n = 0-7) indicates an accumulated error of waveform data in one bit range. In a state J0, it is shown that to input "1" to the shift register 1 causes transition to a state J1. Now a case is assumed in which a loop is formed by starting from the state J0 and returning to that state through any routes. This is step ST31 in Fig. 3. For example, a route J0 → J1 → J2 → J4 → J0 may be taken. As to this route, errors included in the waveform data 11c of one bit range are accumulated. The resulting accumulated value is 1.05, which exceeds the quantization step width (1.0 = quantization step width). So each of the states along the above-described route is given a note saying "accumulated error present" (steps ST32 and ST33). Then another typical route J0 → J1 → J3 → J6 → J4 → J0 may be taken. In this case, the accumulated value of errors is 0.0, which does not exceed the quantization step width. So each of the states along the route is given a note saying "no correction needed" (step ST34). The process from step ST31 to step ST34 is repeated until every branch (a branch is a path that connects two states) is passed at least once. Whether every branch is passed at least once or not is judged in step ST35. When every branch has been passed at least once, there may remain states with a note "accumulated error present" attached to each. In the example above, states J2 and J5 remain noted for having an accumulated error each. In Step ST36, the states to be corrected are suitably selected to correct the waveform data 11c corresponding to these states. Then each route whose accumulated value of errors exceeds the quantization step width is checked again. Steps ST36 and ST37 are repeated until the accumulated value falls within the quantization step width. The three-stage shift register has been used in the example above for the purpose of explanation. In practice, the number of stages of the shift register may be much larger because of the need to consider the degree of intersymbol interference. The number of states involved is 2 to the number of stages. This poses quite a challenge in verifying all the branches involved. A similar signal generator as to that mentioned above is described in the essay "Design of Quadrature Modulator for Digital FM Signalling with Digital Signal Processing" by Hiroshi Suzuki et al. in "Electronics and Communications in Japan", vol. 65-B, no. 9, September 1982, New York, US, pages 66 to 73. In particular, this essay describes a quadrature modulator which provides accurate phase control using digital signal processing (DSP). GMSK is used as a modulation scheme. In general, the output of a modulator adapting DSP contains deviations from the ideal analog waveforms attributable to sampling, quantization and truncation errors. These errors are superposed as noise on the modulating waves and cause degradation in signal transmission. Since waveform data has been conventionally corrected as described above, there are no definite criteria for making the correction (in step ST36 of Fig. 3). Errors can only be minimized through the trial and error approach. Also, there are no criteria for selecting a route (in step ST31 of Fig. 3). This has made it necessary for redundant routes to be selected many times before every branch has been passed at least once. SUMMARY OF THE INVENTION These are the problems that the present invention proposes to solve. A waveform data correction method according to the invention can correct waveform data logically. Also, the method can verify all the branches efficiently without omission. In a waveform data correction method according to the present invention, an element such as a shift register or the like that can make reference to sequential data of a predetermined number of bits stored therein, is used (this element is hereinafter referred to as a shift register). When waveform data which is used for generating a base band waveform based on the digital data stored in the shift register, is accumulated for modulation, errors deviating from the base band waveform are accumulated. The accumulated errors are suitably reduced by the method to fall within a predetermined range. At the beginning of the correction process, it is necessary to define 2 M states (M = number of stages of shift register) that correspond to the bit patterns of the data stored in the shift register. Each state is keyed to a single bit interval of digital data as waveform data. The initial state is a state that corresponds to a bit pattern in effect when the M bits are all zeros. (Alternatively, the initial state can be a state corresponding to the bit pattern in effect when the M bits are all ones.) Data comprised of odd numbers in binary format from 1 to 2 M -1 (or data in inverted binary format) is followed by the bit pattern keyed to the initial state (i.e., a pattern of a series of M bits of either zeros or ones). The data and the bit pattern are regarded collectively as a data pattern. State transition according to each of the generated data patterns forms a route. On each route, errors contained in the waveform data in each state are added up. When the result of the error accumulation has exceeded a predetermined level of a quantization step, an equation ΣS k = -(accumulated error) is formed, where S k is assumed to represent a correction value directed to the waveform data of the states included in the target route (k corresponds to the state number). After the accumulated errors are calculated on every route, the resulting simultaneous equations are solved. The error correction value for a specific S k is thus determined for waveform data correction. In the step of generating the data pattern in an embodiment of the present invention, all routes covering all the state transition can be determined efficiently. In the step of solving the above-mentioned simultaneous equations, it is possible to determine logically the correction value for any candidate waveform data to be corrected. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a base band generator of a quadrature modulation type digital FM modulator; Fig. 2 is a view typically showing waveform data during a single bit interval of input digital data prior to correction; Fig. 3 is a flowchart showing a conventional waveform data correction method; Fig. 4 is a state transition diagram in case a shift register depicted in Fig. 3 is of a three-stage type (M = 3); Fig. 5 is a flowchart showing how waveform data modulated by GMSK is corrected in an embodiment of the present invention; and Fig. 6 is a flowchart depicting a generalized algorithm for eliminating accumulated errors in another embodiment according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will now be explained by referring to the accompanying drawings. Fig. 5 is a flowchart showing how a correction value is obtained. Waveform data 11c has an error from a base band waveform not exceeding a quantization step width in a single bit interval of digital data. A route is formed by starting from state J0 (corresponding to a state where each stage of the shift register in Fig. 1 is zero) and by returning to that state. Along this route, errors in the waveform data 11c are accumulated; the accumulated error is to be corrected by using a value obtained by the steps in this chart. The operations depicted in Fig. 5 are now explained. In step ST11, a state transition diagram is prepared in the same manner as before. Then the value of a counter i is initialized to 1 in step ST12. The value of the counter i is indicated in binary form in step ST13. This value is regarded as a data pattern. According to this data pattern, transition begins from state J0. Every time a state is passed, the error of the waveform data corresponding to that state is accumulated. Then transition is allowed to continue by assuming that zero bits are input successively until returning to state J0. The error contained in the waveform data 11c keyed to each state passed is further accumulated, in step ST14 and ST15. If the accumulated error has exceeded the quantization step width, a correction equation is formed, in step ST17, where S k (k = a state number) represents a correction value for the waveform data 11c. Here, Σ is the sum of the errors of all k corresponding to all states passed. INT(x) means the integer part of x. On the other hand, if the accumulated error is not in excess of the quantization step width, another equation, {S k = 0} is formed in step ST18. Here, k corresponds to each state passed in step ST14 and ST15. Referring now to the state transition diagram in Fig. 4, steps ST12 through ST15 represent the route of state transition of J0 → (1) → J1 → (0) → J2 → (0) → J4 → (0) → J0 The accumulated error on the route is 0.0 + 0.2 + 0.4 + 0.45 = 1.05 Since INT(1.05) = 1, a correction equation of S₀ + S₁ + S₂ + S₄ = -1 is obtained. In step ST19, two is added to the value of the counter i. Steps ST13 through ST18 are repeated until immediately before the value of the counter i exceeds 2 M (M = the number of stages of shift register). In the process described above, every time step ST14 is carried out, a data pattern of "1" (i=1), "11" (i=3), "101" (i=5), "111" (i=7), ..., and "11...1" (i=2 M -1) is handled. Where the so-called GMSK (Gaussian filtered Minimum Shift Keying) is adopted as the modulation method, all the states in the state transition diagram and three-fourths of the branches involved can be covered because of these input of data patterns. Considering the symmetry of state transition under the GMSK method, it can be said that all branches are in fact covered. In this manner, the routes passing all branches are verified mechanically. In the example shown in Fig. 4, when the value of the counter i is three, a data pattern of "11" is handled. That is, the state transition takes place as J0 → J1 → J3 → J6 → J4 → J0 The accumulated error is 0.0 + 0.2 + (-0.45) + (-0.2) + 0.45 = 0.0 Therefore, a correction equation of S₀ = S₁ = S₃ = S₆ = S₄ = 0 is obtained. Similarly, when the value of the counter i is five, a correction equation of S₀ + S₁ + S₂ + S₅ + S₂ + S₄ = -1 is obtained. When the value of the counter i is seven, a correction equation of S₀ = S₁ = S₃ = S₇ = S₆ = S₄ = 0 is obtained. Under the GMSK method, the symmetry of filter response translates into the symmetry of state transition and the symmetry of error configuration. This characteristic is used, in step ST21, to eliminate variables. That is, the characteristic represented by an expression (5), shown below, is utilized. S k = -S₂M -1-k where, k = 2 M-1 , ..., 2 M -1 When M = 3 (in the case of Fig. 4), an expression (5) becomes S k = -S 7-k where, k = 4, 5, 6, 7 By applying the expression (6) to the expressions (1) through (4), simultaneous equations of S₀ + S₁ + S₂ - S₃ = -1 S₀ = S₁ = S₃ = 0 S₀ + S₁ + S₂ - S₃ = -1 are obtained. When these equations are solved in step ST22, the correction value for the waveform data 11c corresponding to each state is obtained. For waveform data correction, the correction value is assigned to any appropriate item of the waveform data 11b contained among the waveform data 11c of a single bit interval. In the embodiment described above, the route that starts from state J0 and returns to that state has been selected for verification of all routes. It is also possible to select a route that starts from a state J(2 M -1) and returns to the same state. In the latter case, all bits of I D (the value i in binary format) obtained in step ST13 are inverted to form a data pattern. Using that data pattern, '1' bits may be kept being input during state transition until the state J(2 M -1) is reached again in step ST15. In the above-described embodiment, the GMSK method has been adopted as the modulation method. The modulation method may also be TFM (Tamed Frequency Modulation) or other versions of digital frequency modulation. Where the present invention is embodied, these arrangements also prove as effective as the GMSK method. But it is required that both routes starting from JO state and starting from J(2 M - 1) state are selected unless used modulation method has symmetry of filter response. The invention may also be applied to the correction of waveform data where another base band generator equivalent to that shown in Fig. 1 is used for modulation. In addition to applications of digital modulation, the method of correcting accumulated errors according to the present invention has a wide range of applications in which additions are carried out according to a given state transition diagram. Fig. 6 is a flowchart generalizing the flowchart of Fig. 5. In this generalized setup, state transition is allowed to start from any of the states in the state transition diagram in step ST25, and to return to the same state, in step ST26, to form a route. All the patterns that constitute such a route are mechanically generated in this step. State transition takes place according to each pattern generated so as to obtain equations in step ST27. When the processing is completed on all patterns in step ST28, the resulting simultaneous equations are solved in step ST29. Those corrected waveform data as described above are set in the waveform memory 2 in Fig. 1. A base band signal generator having corrected waveform data performs in the same manner of a conventional generator. But the designer of a modulation system can design the data in the waveform memory 2 more quickly and logically as compared to conventional designing. As described above, the waveform data correction method according to the present invention makes it possible to determine mechanically the routes such as to cover all branches of the state transition involved. The method then allows simultaneous equations to be formed corresponding to these routes. By solving these equations, it is possible to determine the waveform data to be corrected and the corresponding correction value. This method ensures the verification of accumulated errors in waveform data in any applications where the waveform data is added up consecutively. The method is also reliable and efficient in determining the assignment of correction values to the respective items of waveform data.

Claims: A method for correcting waveform data in digital signal modulation which accomplishes a correction to quantized waveform data (11b) stored in a waveform memory (2) for generating a base band waveform (11a) according to consecutive M-bit digital data (M is a predetermined positive number) among input digital data stored in an element capable of making reference to said consecutive M-bit digital data, so as to reduce an accumulated error in an accumulated value of said quantized waveform data deviating from an accumulated value of said base band waveform within a predetermined value; characterized by the steps of: defining states, each of which corresponds to respective bit patterns of said consecutive M-bit digital data stored in said element and outputs said quantized waveform data of a single bit interval, and defining one of the states as first initial state corresponding to a bit pattern of all "0" bits and another one of the states as second initial state corresponding to a bit pattern of all "1" bits; generating data patterns, each of which contains respective binary data comprised of odd numbers in binary format from one to (2 M - 1) followed by consecutive "0" bits until reaching the bit pattern corresponding to said first initial state, or the data being complement numbers of those comprised of odd numbers in binary format from one to (2 M - 1) followed by consecutive "1" bits until reaching the bit pattern corresponding to said second initial state; computing said accumulated error along each state transition route set in accordance with each of said data patterns generated above; establishing simultaneous equations, corresponding to said routes, each left hand of which is a sum of correction variables to said accumulated error computed along each state transition route, and in each right hand of which are correction values to said quantized waveform data output from said states existing along said state transition route subjected to computation; determining states to be corrected concerning said quantized waveform data and those correction values by solving the simultaneous equations established after computing said accumulated errors along all the routes; and correcting said quantized waveform data in accordance with said correction value. The method according to claim 1, for correcting waveform data in digital signal modulation having symmetrical character of filter response, characterized by the further step of eliminating, after the establishing step and before the determining step, some of said variables in the equations because of symmetrical character of filter response. A base band signal generator in a digital signal modulation system comprising; a shift register (1) which shifts input digital data and outputs parallel data; a counter (3) which counts clock signals generated at a rate of n times bit rate of said input digital data, outputs count value, and orders to said shift register (1) so as to shift the data every time the count value reaches to n; and a waveform memory (2) which has quantized data (11b) made by a process of quantizing a base band wave (10) corresponding to all patterns indicated in said parallel data, and outputs said quantized data (11b) as the base band waveform at the rate n times the bit rate from addresses pointed by said parallel data and said count value to an adder (4) connected to this memory (2); characterized in that said waveform memory (2) contains said quantized data (11b), which have been optimized by; defining states, each of which corresponds to respective bit patterns of said consecutive M-bit digital data stored in said element and outputs said quantized waveform data of a single bit interval, and defining one of the states as first initial state corresponding to a bit pattern of all "0" bits and another one of the states as second initial state corresponding to a bit pattern of all "1" bits; generating data patterns, each of which contains respective binary data comprised of odd numbers in binary format from one to (2 M - 1) followed by consecutive "0" bits until reaching the bit pattern corresponding to said first initial state, or the data being complement numbers of those comprised of odd numbers in binary format from one to (2 M - 1) followed by consecutive "1" bits until reaching the bit pattern corresponding to said second initial state; computing said accumulated error along each state transition route set in accordance with each of said data patterns generated above; establishing simultaneous equations, corresponding to said routes, each left hand of which is a sum of correction variables to said accumulated error computed along each state transition route, and in each right hand of which are correction value to said quantized waveform data output from said states existing along said state transition route subjected to computation; determining states to be corrected concerning said quantized waveform data and those correction values by solving the simultaneous equations established after computing said accumurated errors along all the routes; and correcting said quantized waveform data in accordance with said correction value. The base band signal generator according to claim 3, in a digital signal modulation system having symmetrical character of filter response, characterized in that said quantized data (11b) stored in said waveform memory (2) have been subjected to optimization by the further step of eliminating, after the establishing step and before the determining step, some of said variables in the equations because of symmetrical character of filter response.

Inventors: IWANE YASUSHI C O MITSUBISHI D, IWANE, YASUSHI, C/O MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H04L27
IPC codes: H04L27