Self-adapting vertical scan circuit for raster-scanned cathode ray tube displays

Abstract: A vertical scan circuit for a display is described which allows automatic picture height and centering. The deflection voltages at the start and end of active video time, are stored by capacitors fed via switches activated by signal pulses. These stored voltages are compared to margin reference voltages Vtmref and Vbmref which correspond to the desired top and bottom of the picture as displayed for a particular monitor. The maximum deflection voltage on flyback (Vmax) and the slope of the signal (dv/dt) are adjusted so that the top margin voltage (Vtm) and the bottom margin voltage (Vbm), bear desired relationships to these reference voltages (Vtmref and Vbmref respectively), thus ensuring that the top and bottom of the picture as displayed remains constant for different screen formats.

Description: This invention relates to a vertical scan circuit for a raster-scanned cathode ray tube (CRT) display, in particular to a circuit which allows automatic picture height adjustment and centering for different screen formats. In raster-scan CRT video displays, an electron beam(s), is deflected and modulated to produce an image on the screen. Horizontal and vertical scan frequencies refer to the rate at which the beam can scan a single horizontal line or a complete screen respectively: bandwidth indicates how fast the beam can be turned on or off. These performance indices dictate the resolution of the display. Particular functions require different resolutions or screen formats, that is the number of characters or picture elements (pixels or pels) per line or horizontal lines per screen. The majority of systems are designed such that an individual display is configured for a particular screen format. However, many standards have evolved, and attempts have been made to provide one display capable of presenting data in several of such formats. The NEC Multisync II (trademark) is an example of a multimode display, which can "lock into" a range of formats: however, picture height and centering need to be reset manually for each one. US Patent No. 4,574,279 describes a multiple format system in which horizontal and vertical scan frequencies are generated such that one of two formats can be selected. the same picture size being maintained by the application of one of two preset voltages to height adjustment circuits. IBM Technical Disclosure Bulletin Vol. 28, No. 12, pp.5603-4, illustrates a method of increasing the number of vertical resolution modes of a display without altering the horizontal scan rate: the width of the video display enable signal, which corresponds to the number of horizontal lines displayed, is converted to a resistance value and used to control the vertical position of the beam. Apparatuses for controlling the vertical scan of a display are also known from EP-A-0 149 730 and EP-A-0 310 419. Whilst it is clear, therefore, that multiformat displays do exist, nowhere in the prior art is the function fulfilled of automatic picture height adjustment and centering for a wide range of non-present screen formats. In raster video displays, the vertical position of the electron beam is controlled by the generation of deflection voltage signals, the voltage value varying with time. A change in format could involve, for example, varying the duration of the active video time when data is actually being displayed on screen. The essence of the present invention is to provide means for automatically modifying the vertical deflection signal such that the deflection voltages at the start and end of the active video time are the same for differing screen formats; that is the top and bottom margins of the picture as displayed remain constant. In accordance with the present invention, there is now provided apparatus for controlling the vertical scan of a display, the apparatus comprising: synchronisation means for controlling the scanning frequency; means for generating a video duty cycle signal corresponding in duration to the active video time; a ramp generation circuit for generating a ramp deflection voltage signal; characterised in that the apparatus comprises: a signal processor for generating, in response to the video duty cycle signal, a start pulse indicative of when the active video time starts and an end pulse indicative of when the active video time ends; first sampling means for storing a first sample of the voltage deflection signal in response to the start pulse; a first differential amplifier for generating a first error signal as a function of the difference between the first sample and a first reference voltage; first feedback means connected to the ramp signal generator for determining a peak of the ramp deflection voltage signal in response to the first error signal; second sampling means for storing a second sample of the voltage deflection signal in response to the end pulse; a second differential amplifier for generating a second error signal as a function of the difference between the second sample and a second reference voltage lower than the first reference voltage; and second feedback means connected to the ramp signal generator for determining the slope of the ramp deflection voltage signal in response to the second error signal. Viewing the present invention from another aspect, there is provided a method for controlling the vertical scan of a display, the method comprising: controlling the scanning frequency; generating a video duty cycle signal corresponding in duration to the active video time; generating a ramp deflection voltage signal; generating, in response to the video duty cycle signal, a start pulse indicative of when the active video time starts and an end pulse indicative of when the active video time ends; storing a first sample of the voltage deflection signal in response to the start pulse; generating a first error signal as a function of the difference between the first sample and a first reference voltage lower than the first voltage reference; determining a peak of the ramp deflection voltage signal in response to the first error signal; storing a second sample of the voltage deflection signal in response to the end pulse; generating a second error signal as a function of the difference between the second sample and a second reference voltage; and determining the slope of the ramp deflection voltage signal in response to the second error signal. A specific example of the invention will now be described in detail with reference to the accompanying diagrams, in which :- Figure 1 is a block diagram of a vertical scan system; Figure 2 shows the waveforms generated by the circuit blocks of Figure 1. K1 and K2 are constants; Figure 3 shows a typical ramp generation circuit; Figure 4 illustrates a circuit for generating top and bottom margin pulses from a video duty cycle signal; Figure 5 shows the waveforms generated by the circuit shown in Figure 4. Figure 1 includes a ramp generation circuit (1) (see also Fig. 3) configured to accept three inputs:- a) a vertical synchronisation signal on line 2 to start the flyback action, b) a control signal on line 3 to control the level at which the ramp flyback ends and forward scanning begins, and c) a control signal on line 4 to enable the forward slope of the scanning ramp to be varied. The output (5) of the ramp generation circuit (1) (see Fig. 3) is a ramp voltage as shown in Figure 2a. This ramp voltage starts at a maximum voltage level of Vmax, set by the control input. The voltage decreases or "ramps down" with time (t), until tm (the so-called "back porch" time) when it reaches a voltage Vtm corresponding to the top margin of the video picture as displayed. After a further time period tv the ramp reaches a voltage level of Vbm, corresponding to the bottom margin of the video picture as displayed. The ramp voltage continues to fall to a voltage Vmin, at which time the vertical sync pulse (Fig. 2e) resets the ramp and the cycle continues. By controlling the level of Vmax and the forward scanning slope (dv/dt), it can be seen that the levels of Vtm and Vbm can also be controlled. A typical ramp generation circuit is shown in Figure 3. It produces a ramp by using a constant current source using an NPN transistor (Q2) and a PNP transistor (Q3) to discharge a capacitor (C1). The constant current source is in turn controlled by the dv/dt input (4). The ramp is reset by a field-effect transistor switch (Q1) which, when triggered by the vertical sync signal (Fig. 2e), recharges the capacitor (C1) to the voltage, Vmax, as controlled by the second input (3). A second block shown in Fig. 1 is that of the video duty cycle signal processor (6) (see Fig. 4). The video duty cycle signal (V1), which can be seen in Figures 2b and 5, indicates when data is being presented on the screen. This signal can be sent directly from the logic on line 7 or, in an alternative embodiment of the invention not shown, can be coded into the vertical sync signal (Fig. 2e), on line 2, and separated by the block (6) to produce the vertical video duty cycle signal. This is processed by the duty cycle signal processor, a typical circuit and associated waveforms being shown in Figs. 4 and 5 respectively, to produce two signals as shown in Figures 2c and 2d, a short pulse Vs1 on line 8 indicating the time video starts (the beginning of active video time), and a pulse Vs2 on line 9, indicating when the video ends, (the end of active video time). A top margin control circuit (10) which supplies the control signal on line 3 has three inputs: a) the video signal start (Vs1), on line 8, b) the output signal of the ramp generator on line 5, and c) a variable reference voltage (Vtmref) In order for the top and bottom of the picture to remain in the same place for different screen formats, reference voltages vtmref and Vbmref are defined. These are, or have a known relationship to, the deflection voltage values that correspond to the desired top and bottom of the screen region where data is actually to be displayed. They can be varied, depending on the physical screen size of the monitor but, once set, would be constant for a particular display. The ramp signal on line 5 is fed into a capacitor (11) via a switch (12) activated during the video start time pulse. This forms a sample and hold circuit, storing the value of the ramp voltage at the time Ttm, this being the level of the top margin voltage Vtm. This is fed into a differential amplifier (13) that compares this voltage to the reference voltage, Vtmref. The difference between these constitutes an error signal that is amplified with appropriate frequency compensation and is fed back on line 3 to the ramp generator to control the maximum voltage after flyback. A similar "sample, hold and control" circuit (14) controls the bottom margin, wherein it is fed with the video end signal Vs2 on line 9 and samples the ramp voltage at the time (Ttm + Tv), thus sampling the level of Vbm. This is again compared to a second reference voltage Vbmref, the resulting output being fed back on line 4 to control the ramp slope (dv/dt). By controlling both the slope and the Vmax on flyback, the same relationships between Vtm and Vtmref and between Vbm and Vbmref can be maintained automatically for a wide-range of screen formats. In this fashion the above circuit blocks 1, 6, 10 and 14 operating together form a dual control system capable of maintaining accurate height and picture position over a wide range of formats. The ramp voltage on line 5 , is coupled via a DC amplifier (15) to the vertical deflection yoke (16) of a display, the vertical scan frequency range employed being from 30Hz to 100Hz. Despite there being additional circuitry in the system described compared to a basic vertical deflection stage, its complexity and component count are very similar to a multiple fixed mode scan circuit which requires demultiplexors and multiple adjustments, or close tolerance resistor networks. The performance of the present system is also theoretically more accurate than a multiple fixed mode scan circuit and has the additional advantage of being unlimited for use with future or specialised format standards. Being of low power signal operation, this circuit function could readily be encorporated into an integrated circuit. The references to top and bottom margins, being of DC nature, could be controlled by digital to analogue converters if a digital set up procedure were required. Although a vertical scan circuit has been described, it is obvious that the same principles could also be applied to the horizontal scan circuit, the reference to top and bottom of the picture being replaced by reference to the left and right hand margins.

Claims: Apparatus for controlling the vertical scan of a display, the apparatus comprising: synchronisation means (2) for controlling the scanning frequency; means (7) for generating a video duty cycle signal corresponding in duration to the active video time; a ramp generation circuit (1) for generating a ramp deflection voltage signal; characterised in that the apparatus comprises: a signal processor (6) for generating, in response to the video duty cycle signal, a start pulse (Vs1) indicative of when the active video time starts and an end pulse (Vs2) indicative of when the active video time ends; first sampling means (11,12) for storing a first sample (Vtm) of the voltage deflection signal in response to the start pulse (Vs1); a first differential amplifier (13) for generating a first error signal (Vmax) as a function of the difference between the first sample and a first reference voltage (Vtmref); first feedback means (3) connected to the ramp signal generator (1) for determining a peak of the ramp deflection voltage signal in response to the first error signal (Vmax); second sampling means (17,18) for storing a second sample (Vbm) of the voltage deflection signal in response to the end pulse (Vs2); a second differential amplifier (19) for generating a second error signal (SLOPE) as a function of the difference between the second sample (Vbm) and a second reference voltage (Vbmref) lower than the first reference voltage (Vtmref); and second feedback means (4) connected to the ramp signal generator (1) for determining the slope of the ramp deflection voltage signal in response to the second error signal (SLOPE). Apparatus as claimed in claim 1, wherein the first sampling means comprises a capacitor (11) fed by a switch (12) activated by the start pulse (Vs1). Apparatus as claimed in claim 1, wherein the second sampling means comprises a capacitor (17) fed by a switch (18) activated by the end pulse (Vs2). Apparatus as claimed in any preceding claim, wherein the ramp signal generator (1) comprises a capacitor (C1); a current source connected to the capacitor (C1) and controlled by the error signal (SLOPE) to discharge the capacitor (C1); and a switch (Q1) for selectively connecting the capacitor (C1) to the first error signal (Vmax) to recharge the capacitor (C1) in response to a synchronisation pulse from the synchronisation means (2). Apparatus as claimed in any preceding claim wherein the scan frequency is in the range 30Hz to 100Hz. Apparatus as claimed in any preceding claim in which the ramp deflection voltage signal is coupled via a DC amplifier (15) to the vertical deflection yoke (16) of a display. A method for controlling the vertical scan of a display the method comprising: controlling the scanning frequency; generating a video duty cycle signal corresponding in duration to the active video time; generating a ramp deflection voltage signal; generating, in response to the video duty cycle signal, a start pulse (Vs1) indicative of when the active video time starts and an end pulse (Vs2) indicative of when the active video time ends; storing a first sample (Vtm) of the voltage deflection signal in response to the start pulse (Vs1); generating a first error signal (Vmax) as a function of the difference between the first sample and a first reference voltage (Vtmref) lower than the first voltage reference (Vtmref); determining a peak of the ramp deflection voltage signal in response to the first error signal (Vmax); storing a second sample (Vbm) of the voltage deflection signal in response to the end pulse (Vs2); generating a second error signal (SLOPE) as a function of the difference between the second sample (Vbm) and a second reference voltage (Vbmref); and determining the slope of the ramp deflection voltage signal in response to the second error signal (SLOPE).

Inventors: MORRISH ANDREW JOHN, MORRISH, ANDREW JOHN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: G09G1
IPC codes: H04N3, H03K4, G09G1