Method of manufacturing a semiconductor device

Abstract: A semiconductor device such as a Bi-CMOS having vertical or lateral bipolar transistors and MOS transistors is disclosed. The MOS transistors include a gate electrode made of a first conductive thin film, and sidewall spacers formed on the sides of the gate electrode and consisting of at least one deposited insulation film. The vertical bipolar transistors include an emitter electrode made of a second conductive thin film, and an emitter diffusion window formed in the deposited insulation film which is disposed under the emitter electrode. The lateral bipolar transistors include a base width defining region for defining the base width, and an insulation film formed between the base width defining region and the collector and emitter, which includes the deposited insulation film. Sidewall spacers for the emitter electrode or the base width defining region respectively are alternatively also supplied.

Description: The present invention relates to methods of manufacturing semiconductor devices having one or more vertical bipolar transistors and one or more MOS transistors integrated on one semiconductor substrate. Recently, extensive attempts have been made to develop semiconductor devices having a so-called Bi-CMOS structure in which a bipolar transistor and complementary MOS transistors (CMOS transistors) are integrated on one semiconductor substrate. Hereinafter, such a semiconductor device having a Bi-CMOS structure is often referred to as merely "Bi-CMOS". Figure 16 shows a conventional Bi-CMOS. This Bi-CMOS comprises: a P-silicon substrate 1 having an N + -buried region 2 formed on its surface; an N-epitaxial layer 4 formed on the P-silicon substrate 1; a field oxide 6 formed adjacent the top surface of the N-epitaxial layer 4 and in an isolation region of a P + -buried region 3 formed in the N-epitaxial layer 4 below the field oxide 5 in such a manner that it surrounds a region formed where the field oxide 6 is not formed (hereinafter, such a region is referred to as "an active region"), and reaches the substrate 1; a vertical bipolar transistor VBT formed in a portion of the active region within the N-epitaxial layer 4; two MOS transistors MT formed in the other portion of the field oxide region within the N-epitaxial layer 4; and an insulating layer 14 formed so as to cover the bipolar transistor VBT, the MOS transistors MT and the field oxide 6. The vertical bipolar transistor VBT has a P-base region 7 formed within the N-epitaxial layer 4, an N-emitter region 9 within the P-base region 7, a gate oxide 8 formed on the emitter region 9, an emitter diffusion window 15 formed in a predetermined portion of the gate oxide 8, and an emitter electrode 11 formed on the gate oxide 8 for contact with the N-emitter region 9 through the emitter diffusion window 15. One of the MOS transistors MT is an N-type MOS transistor having a P-well region 5 formed in the N-epitaxial layer 4, a gate oxide 8 formed on the P-well region 5, a gate electrode 10 formed on the gate oxide 8, and an N + -diffusion region 13 formed adjacent to the surface of the P-well region 5 in a region where the gate electrode 10 is not formed. A contact window 17 for interconnecting the N + -diffusion region 13 and a metal wiring layer (not shown) is formed in a specified portion of the insulating layer 14 on the N + -diffusion region 13. The other MOS transistor is a P-type MOS transistor having a gate oxide 8 formed on the N-epitaxial layer 4, a gate electrode 10 on the gate oxide 8, and a P + -diffusion region 12 formed adjacent to the surface cf the N-epitaxial layer 4 in a region where the gate electrode 10 is not formed. A contact window 18 for interconnecting the P + -diffusion region 12 and a metal wiring layer (not shown) is formed in a specified portion of the insulating layer 14 on the P + - diffusion region 12. When manufacturing the Bi-CMOS of Figure 16, the emitter diffusion window 15 for the bipolar transistor VBT is formed after the gate oxide 8, and before a poly-Si film (which serves as the gate electrode 10 and emitter electrode 11) are deposited on the gate oxide 8. According to this method, the surface of the P-base region 7 in a region where the emitter region 9 is to be formed is exposed as a result of the formation of the emitter diffusion window 15. This involves a problem in that P-type impurities come out from the exposed P-base region 7 to contaminate the gate oxide 8 before the poly-Si film which serves as the emitter electrode 11 is deposited on the gate oxide 8. In this method, when the poly-Si film has been deposited on a wafer after the formation of the emitter diffusion window 15, there may remain an oxide film in the interface between the P-base region 7 within the emitter diffusion window 15 and the poly-si film (i.e., the emitter electrode 11). This oxide film is a native oxide grown by the oxidation of the surface of the P-base region 7 exposed through the emitter window 15, after the formation of the emitter window 15. If the native oxide film is thick, the trouble is caused in that the diffusion of impurities for forming the emitter region 9, from the poly-Si film to the P-base region 7 may not be properly effected. Even if the emitter region 9 is formed, moreover, the presence of the native oxide film may cause an excessive electric resistance to be formed between the emitter region 9 and the emitter electrode 11. Therefore, it is necessary to carry out an etching process in order to remove the native oxide film immediately before the poly-si film serving as the emitter electrode 11 is formed on the wafer. In the above prior art technique, however, the gate oxide 8 is exposed on the wafer during the etching process, and hence the surface of the gate oxide 8 is also subject to the etching. Where the gate oxide 8 is designed so as to be as thin as 10 nm or so, any decrease in the thickness of the gate oxide 8 causes a substantial degradation in the characteristics of the transistor. If pin holes are formed in the gate oxide 8, serious trouble is caused in that no proper operation of the transistor can be realized. The insulation between the emitter electrode 11 and the P-base region 7 is provided by the gate oxide 8 formed below the emitter electrode 11. If the thickness of the gate oxide 8 is reduced as a result of the etching process, therefore, the dielectric strength of the interface between the emitter electrode 11 and the P-base region 7 degrades, with the result that a leakage current will flow between the emitter electrode 11 and the P-base region 7. In the MOS transistor MT, the P + -diffusion region 12 and N + -diffusion region 13 are formed in self-aligned relation with respect to the gate electrode 10 by the ion implantation technique in which the gate electrode 10 is used as a mask. If both the diffusion regions 12 and 13 are diffused laterally, the diffusion regions 12, 13 will find their way into a region below the gate electrode 10, with the result that the effective channel length of the MOS transistors is reduced. Recent micronized MOS transistors have a gate electrode 10 with a gate length of the order of, for example, 800 nm. Such micronized transistors involve an inherent problem in that the reduced channel length due to the lateral diffusion of the diffusion regions 12 end 13 causes the performance characteristics of the transistors to degrade considerably. Moreover, in the bipolar transistor of a conventional Bi-CMOS, the contact window 15 is formed in the base diffusion region 7, which is an active base diffusion region, resulting in that the base contact resistance and time base resistance are further increased. From GB-A-2 208 965 a bipolar/CMOS integrated circuit is known comprising vertical bipolar transistors and MOS transistors formed on a semiconductor substrate, said MOS transistor comprising a gate oxide film, a gate electrode made of a first conductive thin film and a sidewall spacer formed on the sides of said gate electrode. Furthermore the vertical bipolar transistor of said known device comprises an emitter electrode made of a second conductive thin film and an emitter diffusion window. The silicon dioxide provided for insulation purposes is formed between the P-base diffusion region and the emitter electrode of said vertical bipolar transistor. The silicon dioxide is deposited on the semiconductor device during manufacturing and is removed from the horizontal parts of the semiconductor device, whereas the vertical parts remain. From JP-A-63-31156 a semiconductor device is known comprising a bipolar transistor having a film deposited on the sides and the upper face of a gate electrode. In this film and in another film the emitter diffusion windows are formed, both films consisting of the same PSG film. The source and drain regions of this known device are formed before the PSG film is deposited. EP-A-O 281 235 discloses a bipolar transistor fabrication utilizing CMOS techniques. In this prior art the bipolar transistor comprises a gate oxide film in which the emitter diffusion window is formed. Prior art document EP-A-0 215 583 discloses a bipolar and/or MOS device fabricated on integrated circuit substrates, where the devices are provided with oxide spacer portions formed on the sides of both the electrode and the gate electrode. Methods of manufacturing a semiconductor device according to the present invention are defined in claim 1 and claim 2. This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: Figure 1A is a partial sectional view of a Bi-CMOS formed by using a method according to claim 2. Figure 1B shows a vertical bipolar transistor formed in the Bi-CMOS of Figure 1A. Figures 1C arid 1D show MOS transistors formed in the Bi-CMOS of Figure 1A. Figures 2 to 11 illustrate steps of manufacturing the Bi-CMOS of Figure 1A. Figure 12A is a partial sectional view of another Bi-CMOS formed by using a method according to claim 1. Figure 12B shows a vertical bipolar transistor formed in the Bi-CMOS of Figure 12A. Figures 12C and 12D show MOS transistors formed in the Bi-CMOS of Figure 12A. Figures 13 to 15 illustrate steps of manufacturing the Bi-CMOS of Figure 12A. Figure 16 is a partial sectional view of a prior art Bi-CMOS. (Example 1) Figure 1A shows a Bi-CMOS formed by using a method according to claim 2. The Bi-CMOS of Figure 1A comprises: a P-single crystal silicon substrate 20S having an N + -buried region 21 and a P + -buried region 22 formed in specified regions adjacent to the top surface of the substrate 20S; an epitaxial layer 20E formed over the entire surface of the substrate 20S; a field oxide (SiO 2 ) film 25 formed adjacent to the top surface of the epitaxial layer 20E and within isolation regions in which no element is to be formed; a vertical NPN bipolar transistor VBT formed in a portion of an active region of the epitaxial layer 20E; MOS transistors PMT and NMT formed in other portions of the active region of the epitaxial layer 20E, an Si 3 N 4 film 48 formed so as to cover the vertical NPN bipolar transistor VBT, MOS transistors PMT and NMT, and field oxide film 25; a BPSG film 49 formed on the Si 3 N 4 film 48; and a metal wiring layer 50 formed on the BPSG film 49. As shown in Figure 1B, the vertical NPN bipolar transistor VBT has an N-well 23 formed in the epitaxial layer 20E, a P-base region 34 formed in an upper portion of the N-well 23, an N + -emitter region 39 formed in an upper portion of the P-base region 34, an oxide (SiO 2 ) film 27 formed on the surface of the epitaxial layer 20E, a first deposition film 36 formed on the oxide film 27, an emitter diffusion window 38 formed in the first deposition film 36 and oxide film 27, and an emitter polysilicon electrode 40 which contacts the N + -emitter region 39 through the emitter diffusion window 38. A second deposition film 41 which functions as a sidewall spacer is provided at the sides of the emitter electrode 40 and on the first deposition film 36. Under both the emitter electrode 40 and second deposition film 41, consequently, the first deposition film 36 is formed. A P + -external base diffusion regicn 46 is formed in the P-base region 34 in such a manner that it surrounds the N + -emitter 39. In specified portions of the BPSG film 49 and Si 3 N 4 film 48 on the P + -external base diffusion region 46 and emitter electrode 40, formed are contact windows 70 and 71 through which the emitter electrode 40 and P + -external base diffusion region 46 are connected with the metal wiring layer 50, respectively. An N + -collector wall diffusion region 26 connected to the N + -buried region 21 is formed within the N-well 23 and in a region opposite to the P + -external base region 46 across the field oxide film 25 in the N-well, In the BPSG film 49 and Si 3 N 4 film 48 on the N + -collector wall diffusion region 26, there is formed a contact window 72 for connecting the N + -collector wall diffusion region 26 to the metal wiring layer 50. Figure 1C shows the P-channel MOS transistor PMT having a gate oxide film 29 formed over an N-well region 23 which is formed in the epitaxial layer 20E, a gate electrode 31 formed on the gate oxide film 29, and P + -diffusion regions 45 formed adjacent to the surface of the N-well region 23 in the region in which the gate electrode 31 is not formed. The P + -diffusion regions 45 function respectively as a source and a drain. In the BPSG film 49 and Si 3 N 4 film 48 on the P + -diffusion regions 45, formed are contact windows 73 for respectively connecting the P + -diffusion regions 45 to the metal wiring layer 50. As shown in Figure 1D, the N-channel MOS transistor NMT has a gate oxide film 29 formed over a P-well region 24 which is formed in the epitaxial layer 20E, a gate electrode 32 formed on the gate oxide film 29, and N + -diffusion regions 43 formed adjacent to the surface of the P-well region 24 in the region in which the gate electrode 32 is not formed. The N + -diffusion regions 43 function as a source or a drain. In the BPSG film 49 and Si 3 N 4 film 48 on the N + -diffusion regions 43, formed are contact windows 73 for respectively connecting the N + -diffusion regions 43 to the metal wiring layer 50. In the MOS transistors PMT and NMT, a sidewall spacer 80 is disposed on each of the sides of the gate electrodes 31 and 32. The sidewall spacers 80 is formed by the first deposited film 36 and the second deposited films 41 which are placed in that order from the gate electrode side. As described above, this embodiment has a Bi-CMOS structure in which the vertical bipolar transistor VBT and the P-channel and N-channel MOS transistors FMT and NMT are formed on one substrate 20S, and the P-channel and N-channel MOS transistors PMT and NMT are complementarily connected to form a CMOS structure. The active regions where these transistors are respectively formed are separated from each other by the field oxide (SiO 2 ) film 25. A method of manufacturing the Bi-CMOS of Figure 1A will be described with reference to Figures 2 to 11. First, the N-type epitaxial layer 20E was formed on the single crystal silicon substrate 20S with the N + - buried region 21 and P + -buried region 22 previously formed on the surface. P-type or N-type impurities were diffused into selected regions within the epitaxial layer 20E, thereby forming the P-well 24 or the N-well 23 in the epitaxial layer 20E. The field oxide film 25 was formed in regions other than the active regions by using the LOCOS technique. Thereafter, the Si 3 N 4 film (not shown) used in the LOCOS process was removed. In this removal process, the SiO 2 film 27 formed under the Si 3 N 4 film was not removed. Subsequently, the N + -collector wall diffusion region 26 for the vertical NPN bipolar transistor VBT was formed (Figure 2). A photoresist 28 having a pattern covering regions other than the MOS transistor region was formed over the field oxide film 25 and SiO 2 film 27 on the epitaxial layer 20E, and then the SiO 2 film 27 in the MOS transistor region not covered by the photoresist 28 was removed to expose the surface of the MOS transistor region of the epitaxial layer 20E (Figure 3). In the embodiment, the SiO 2 film 27 in the bipolar transistor region was not removed so that the non-removed SiO 2 film 27 prevents the outward diffusion of the collector wall diffusion region 26 from occurring. When the outward diffusion from the collector wall diffusion region 26 is insignificant, the SiO 2 film 27 over the bipolar transistor region may be removed. After the removal of the photoresist 28, the surface of the epitaxial layer 20E in the MOS transistor region was subjected to oxidization, whereby the gate oxide film 29 was formed on the surface of the epitaxial layer in the MOS transistor region. In succession to the oxidizing process, a non-doped first poly-Si film was deposited on the wafer. Then, the first poly-Si film was doped with impurities to lower its resistance. Alternatively, a doped poly-Si film containing impurities may be deposited on the wafer to obtain the low-resistance first poly-Si film. A photoresist 30 having a pattern which defines the patterns of the gate electrodes 31 and 32 was formed on the first poly-Si film, and the first poly-Si film was etched by using the photoresist 30 as a mask to form the gate electrodes 31 and 32 (Figure 4). A photoresist 33 was formed, and patterned as shown in Figure 5. Using this patterned photoresist 33 as a mask, Boron was doped in the isolation region for isolating the bipolar transistor VBT from other elements (not shown) and also in the base region of the bipolar transistor VBT by the ion implantation technique. Thus, the P-base diffusion regions 34 and P + -diffusion regions 35 were formed (Figure 5). Then, SiO 2 film 36 (thickness: 100 nm) which is the first deposition film was formed over the wafer by using the LPCVD (Low Pressure Chemical Vapor Deposition) technique. After a photoresist 37 having a pattern for the emitter diffusion window 38 was formed on the SiO 2 film 36, the SiO 2 films 36 and 27 were etched using the photoresist 37 as a mask to form the emitter diffusion window 36 (Figure 6). In order to remove the thin native oxide film on the surface of the P-base region 34 exposed in the emitter diffusion window 38, the wafer was immersed in a suitable MF etchant for a predetermined period of time. A second poly-Si film serving as the emitter electrode 40 of the bipolar transistor VBT was deposited on the wafer, and then doped with As by using the ion implantation technique. Thereafter, the wafer was heat treated or annealed so that a portion of the P-base diffusion region 34 was doped with As from the As-doped second poly-Si film through the emitter diffusion window 38, thereby forming the N + -emitter diffusion region 39 in the P-base diffusion region 34. A photoresist (not shown) having a pattern defining the emitter electrode 40 was formed on the second poly-Si film. Subsequently, by etching the second poly-Si film with using the photoresist as a mask, the emitter electrode 40 was formed over a region including the region in which the emitter diffusion window 38 was formed, and wider than the emitter diffusion window 38 (Figure 7). Alternatively, the N + -emitter diffusion region 39 may be formed by doping As with the ion implantation technique onto the surface of the P-base diffusion region 34 exposed in the emitter diffusion window 38, before the deposition of the second poly-Si film. In the embodiment, during the steps of forming the emitter diffusion window 38, depositing the second poly-Si film, and forming the emitter electrode 40, the MOS transistor region was covered with the SiO 2 film (the first deposition film) 36. Therefore, the MOS transistor region was not contaminated with P-type impurities from the P-base diffusion region 34 exposed in the emitter diffusion window 38. Since the gate oxide film 29 was covered with the first deposition film or SiO 2 film 36, furthermore, the gate oxide film 29 was prevented from being etched in the step of removing the native oxide present on the P-base region 34. Accordingly, there was no unfavorable degradation in the transistor characteristics of the device which may otherwise arise from the thickness reduction of the gate oxide film 29 or formation of pin holes in the gate oxide film 29. There was no possible degradation in dielectric strength between the emitter electrode 40 and the P-base region 34, with the result that no-leakage current flows between them. Then, the second deposition film or SiO 2 film 41 (of 150 nm in thickness) was deposited over the entire surface of the wafer (Figure 8). The SiO 2 films 41, 36 and 29 were sequentially etched away by using the anisotropic etching technique to expose the surface of the epitaxial layer 20E (Figure 9). In this etching process, it was required to expose the surface of the epitaxial layer 20E in the source and drain regions of the MOS transistors PMT and NMT, but it was not required to completely remove the SiO 2 films on the epitaxial surface 20E in the bipolar transistor region. Larger portions of the SiO 2 films 41, 36 and 29 were removed by the anisotropic etching, but the portions of the SiO 2 films 41 and 36 on the sides of the gate electrodes 31 and 32 remained to form the sidewall spacers 80 (of 250 nm in thickness). Under the emitter electrode 40 there remained the SiO 2 film, (of 100 nm thick) 36, and at sides of the emitter electrode 40 there were formed sidewall spacers (of 150 nm thick) consisting of the SiO 2 film 41. As shown in Figure 10, then, a photoresist 42 was formed to cover the regions where the N-channel MOS transistor NMT was not to be formed. Using the photoresist 42 and gate electrode 32 as masks, As was implanted into the specified regions in the P-well 24 by the ion implantation technique. In this way, the N + -diffusion regions 43 which serve respectively as the source and the drain of the N-channel MOS transistor NMT were formed in a self-aligned manner with respect to the gate electrode 32 which has the sidewall spacers 80 on its sides. Immediately after the ion implantation process, the distance between the N + -diffusion region 43 as the source and the one as the drain was greater by the thicknesses of the sidewall spacers than the width of the gate electrode 32, because of the presence of the sidewall spacers 80. Therefore, even when the N + -diffusion regions 43 were expanded laterally as a result of the heat treatment or annealing described later, the N + -diffusion regions 43 were prevented from intruding into the region of the P-well 24 which is immediately under the gate electrode 32, with the result of little or no degradation of the transistor characteristics of the resulting N-channel MOS transistor NMT. As shown in Figure 11, a photoresist 44 was formed to cover the specified regions of the wafer. Using the photoresist 44, gate electrode 31 and emitter electrode 40 as masks, boron was implanted into the N-well 23, P-base diffusion region 34 and P-diffusion regions 35 by the ion implantation technique, thereby forming the P + -diffusion regions 45 and the P + -external base diffusion region 46, and making the concentration of the P + -diffusion regions 35 higher for the isolation of elements. The P + -diffusion regions 45 which serve respectively as the source and the drain of the P-channel MOS transistor PMT were formed in a self-aligned manner with respect to the gate electrode 31 which has the sidewall spacers 80 on its sides. In the same manner as described above, immediately after the ion implantation process, the distance between the P + -diffusion region 45 as the source and the one as the drain was greater by the thicknesses of the sidewall spacers than the width of the gate electrode 31, because of the presence of the sidewall spacers 80. Therefore, even when the P + -diffusion regions 45 were expanded laterally as a result of the heat treatment or annealing described below, the P + -diffusion regions 45 were prevented from intruding into the region of the N-well 23 which is immediately under the gate electrode 31, with the result of little or no degradation of the transistor characteristics of the P-channel MOS transistor PMT. Because the SiO 2 films 36 and 27 were disposed under emitter electrode 40, and the sidewall spacers consisting of the SiO 2 film 41 were situated on the sides of the emitter electrode 40, boron was implanted into the P-active base diffusion region 34 located remote from the emitter diffusion region 39. Thus, the P + -external base diffusion regions 46 having a low resistance were formed in specified regions within the P-active base region 34, in a self-aligned relationship with respect to both the emitter electrode 40 and the N + -emitter diffusion region 39. Because of the existence of the P + -external base diffusion regions 46 having a low resistance, considerable improvement was obtained in the transistor characteristics of the resulting vertical NPN bipolar transistor VBT. Thereafter, the Si 3 N 4 film 48 and the BPSG film 49 were deposited on the wafer, and then the wafer was annealed, whereby smoothing the surface of the BPSG film 49. As a result of this heat treatment, the N + -diffusion regions 43 and P + -diffusion regions 45 expanded laterally to intrude somewhat under the sidewall spacers 80 for the gate electrodes 31 and 32 (i.e., the SiO 2 films 36 and 41), as shown in Figures 1C and 1D. The contact windows 70, 71, 72 and 73 were opened in the Si 3 N 4 film 48 and BPSG film 49, and the metal wiring layer 50 was formed on the BPSG film 49. In this way, the Bi-CMOS of Figure 1A was obtained. According to the above-described method, the sidewall spacers 80 consisting of the first and second deposition films 36 and 41 were formed on the sides of the gate electrodes 31 and 32 of the MOS transistors. Furthermore, the first deposition film 36 was formed under the emitter electrode 40 of the vertical bipolar transistor, and the sidewall spacers consisting of the second deposition film 41 were formed on the sides of the emitter electrode 40. By adjusting the thickness of the first deposition film 36, the degree of the level difference appearing in a portion of the first deposition film 36 in which the emitter diffusion window 38 is formed can be moderated so that the emitter electrode 15 is prevented from being disconnected at a portion involving such a level difference. The necessary insulation between the emitter electrode 40 and the epitaxial layer 20E can be achieved arbitrarily by adjusting the thickness of the first deposition film 36. Furthermore, the thickness of the sidewall spacers for the gate electrodes 31 and 32 can be freely determined by adjusting the thickness of the first and second deposition films 36 and 41. In the above-described method, as shown in Figures 6 and 7, each MOS transistor region was covered with the first deposition film or SiO 2 film 36 during the steps of forming the emitter diffusion window 38, depositing the second poly-Si film 41, and forming the emitter electrode 40. Therefore, the MOS transistor regions were not contaminated with P-type impurities from the P + -base diffusion region 34 exposed in the emitter diffusion widow 38. Since the gate oxide film 29 was covered with the first deposition film or SiO 2 film 36, the gate oxide film 29 was not etched when the native oxide present on the P-base region 34 exposed through the emitter diffusion window 38 was removed by etching. Therefore, any decrease in the thickness of the gate oxide film 29 and the formation of pin holes in the gate oxide film 29 were prevented from occurring, resulting in the desired transistor characteristics of the Bi-CMOS being obtained. Furthermore, the dielectric strength between the emitter electrode 40 and the P-base region 34 did not degrade so that there was no leakage current flowing between the emitter electrode 40 and the P-base region 34. (Example 2) Another Bi-CMOS formed by using a method according to claim 1 is shown in Figure 12A. Figures 12B to 12D illustrate a vertical NPN bipolar transistor VBT, a P-channel MOS transistor PMT and an N-channel MOS transistor NMT of the Bi-CMOS of Figure 12A, respectively. In this embodiment, sidewall spacers consisting of a deposition film 60 are formed on the sides of gate electrodes 31 and 32 of the MOS transistors, and the deposition film 60 is also formed under an emitter electrode 64 of the vertical NPN bipolar transistor. With reference to Figures 13 to 15, a method of manufacturing the Bi-CMOS of the embodiment will be described. The steps illustrated with reference to Figures 2 to 5 in Example 1 were repeated to obtain a wafer having a sectional configuration as shown in Figure 5. Then, a deposition film or SiO 2 film 60 having a thickness of 250 nm was deposited on the entire surface of the wafer by using the LPCVD technique. After photoresist 61 having a pattern for the emitter diffusion window 62 was formed on the SiO 2 film 60, the SiO 2 films 60 and 27 were etched using the photoresist 61 as a mask to form the emitter diffusion window 62 (Figure 13). In order to remove a thin native oxide film on the surface of the P-base region 34 exposed in the emitter diffusion window 62, the wafer was immersed in a suitable HF etchant for a predetermined period of time. A second poly-Si film serving as the emitter electrode 64 of the bipolar transistor VBT was deposited on the wafer, and then doped with As by the ion implantation technique. Thereafter, the wafer was heat treated to form an N + -emitter diffusion region 63 in the P-base region 34. A photoresist (not shown) having a pattern defining the emitter electrode 64 was formed on the second poly-Si film. Subsequently, by etching the second poly-Si film with using the photoresist as a mask, the emitter electrode 64 was formed over a region including the region in which the emitter diffusion window 62 was formed, and wider than the emitter diffusion window 62 (Figure 14). The SiO 2 films 60 and 29 were sequentially etched away by using the anisotropic etching technique to expose the surface of the epitaxial layer 20E ( Figure 15). Larger portions of the SiO 2 films 60 and 29 were removed by the anisotropic etching, but the portions of the SiO 2 film 60 on the sides of the gate electrodes 31 and 32 remained to form the sidewall spacers (of 250 nm in width). Under the side portions of the emitter electrode 64, the SiO 2 film (of 100 nm thick) 60 remained. Thereafter, the steps illustrated with reference to Figures 10 and 11 were repeated to obtain the Bi-CMOS of the embodiment. In the embodiment, as shown in Figures 13 and 14, each MOS transistor region was covered with the deposition film or SiO 2 film 60 during the steps of forming the emitter diffusion window 62, depositing the second poly-Si film, and forming the emitter electrode 64. Therefore, the MOS transistor regions were not contaminated with P-type impurities from the P-base diffusion region 34 exposed in the emitter diffusion window 62. Since the gate oxide film 29 was covered with the deposition film or SiO 2 film 60, the gate oxide film 29 was not etched when the native oxide present on the P-base region 34 exposed through the emitter diffusion window 62 was removed by etching. Therefore, any decrease in the thickness of the gate oxide film 29 and the formation of pin holes in the gate oxide film 29 were prevented from occurring, resulting in the desired transistor characteristics of the Bi-CMOS were obtained. Furthermore, the dielectric strength between the emitter electrode 64 and the P-base region 34 did not degrade so that there was no leakage current flowing between the emitter electrode 64 and the P-base region 34. According to the embodiment, the thickness of the sidewall spacers for the gate electrodes 31 and 32 can be freely selected by adjusting the thickness of the deposition film 60, thereby simplifying the overall manufacturing process. In the above-described embodiments, the gate electrode, emitter electrode, and base width defining portion are made of poly-Si, but these elements may be made of other materials such as refractory metals (e. g., tungsten) and amorphous Si. Furthermore, these elements are structured by one film of poly-Si, but may have other structures such as a polyside structure having a lower film of poly-si and an upper film of refractory sllicide. The Bi-CMOSs of the above-described embodiments has a structure in which a P-substrate, N-epitaxial layer and twin (P and N) well are formed. According to the invention, however, the semicinductor device may have another structure such as those in which a P-substrate, P-epitaxial layer and twin well; a P-substrate, N-epitaxial layer and P-well; or P-substrate and N-well without an epitaxial layer. For the thickness of deposition films, it is of course possible to use values other than those employed in the foregoing embodiments.

Claims: A method of manufacturing a semiconductor device comprising at least one vertical bipolar transistor (VBT) and at least one MOS transistor (PMT, NMT), said bipolar and MOS transistors (VBT, PMT, NMT) being formed on a semiconductor substrate, comprising the steps of: a) forming a gate oxide film (29) at least in a MOS transistor region on a main surface of said semiconductor substrate; b) forming an oxide film (27) at least in a bipolar transistor region on the main surface of said semiconductor substrate; c) forming a gate electrode (31, 32) of said MOS transistor (PMT, NMT) on said gate oxide film (29), said gate electrode (31, 32) being made of a first conductive thin film; d) forming a deposition film (60) over said substrate such that said deposition film is located on said oxide film (27); and on said gate electrode (31,32); e) etching said deposition film and the underlying oxide film at least in the bipolar transistor region (VBT) to form an emitter diffusion window (62) ; f) forming an emitter electrode (64) of said bipolar transistor (VBT) over said emitter diffusion window (62), said emitter electrode being made of a second conductive thin film and being larger in size than said emitter diffusion window ; and g) etching further said deposition film by using the anisotropic dry etching technique to form sidewall spacers (60) on sides of said gate electrode, said sidewall spacers being made of said deposition film, and to leave said deposition film under said emitter electrode which is arranged to be an etching mask; h) forming an insulating film (48) to cover said vertical bipolar transistor (VBT) and said MOS transistor (PMT, NMT). A method of manufacturing a semiconductor device comprising at least one vertical bipolar transistor (VBT) and at least one MOS transistor (PMT, NMT), said bipolar and MOS transistors (VBT, PMT, NMT) being formed on a semiconductor substrate, comprising the steps of: a) forming on oxide film (27) at least in a bipolar transistor region on the main surface of said semiconductor substrate forming a gate oxide film (29) at least in a MOS transistor region on the main surface of said semiconductor substrate; b) forming a gate electrode (31, 32) of said MOS transistor (PMT, NMT) on said gate oxide film, said gate electrode (31, 32) being made of a first conductive thin film; c) forming a first deposition film (36) over said semiconductor substrate such that said first deposition film is located on said gate electrode and on said oxide film (27); d) etching said first deposition film (36) and the underlying oxide film at least in a bipolar transistor region (VBT) to form an emitter diffusion window (38); e) forming an emitter electrode (40) of said bipolar transistor (VBT) over said emitter diffusion window (38), said emitter electrode (40) being made of a second conductive thin film and being larger in size than said emitter diffusion window (38); f) forming a second deposition film (41) over said semiconductor substrate; and g) etching further said first and second deposition films (36, 41) by using the anisotropic dry etching technique to form first sidewall spacers (36, 41, 80) on the sides of said gate electrode (31), said first sidewall spacers (36, 41; 80) being made of said first (36) and second deposition films (41), to leave said first horizontal deposition film (36) under said emitter electrode (40) unaffected, and to form secondly sidewall spacers (41) on the sides of said emitter electrode (40), said second sidewall spacers (41) being made of said second deposition film (41).

Inventors: KAMEYAMA SHUICHI, KIKUCHI KAZUYA, SEGAWA MIZUKI, SHIMOMURA HIROSHI, KAMEYAMA, SHUICHI, KIKUCHI, KAZUYA, SEGAWA, MIZUKI, SHIMOMURA, HIROSHI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21