Hardware simulator

Abstract: The hardware simulator comprises a plurality of interconnected programmable logic devices (20). The devices are connected via a data bus (22) and a control bus (24). Address signals on the control bus are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the device to the data bus. Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices that are required.

Description: This invention relates to the field of hardware simulators. More particularly this invention relates to hardware simulators of the type comprising a plurality of interlinked programmable logic devices. It is essential when designing and developing integrated circuits to test the design of the circuit before the circuit is manufactured. This testing is done by simulating how a circuit built to that design will operate. The traditional method of logic simulation is to use a software simulator running on a conventional (non parallel) computer. A problem with such methods is that the performance of the simulator is usually millions of times slower than the actual performance of the hardware being simulated. This problem is made worst as the size of the chip becomes larger. With the current generation of Very Large Scale Integration (VLSI) integrated circuits the problem of the time taken to run these simulations is becoming critical. One solution to this problem is to use special purpose computers to carry out the simulation. These special purpose computers are parallel processors, typically with up to 256 Central Processor Units (CPUs). Special software prepares the logic being simulated so that the processors may work on it in parallel. These systems are extremely expensive - in some cases millions of dollars. An alternative less expensive solution which has been suggested is to use programmable logic devices (PLDs). These are integrated circuits that may be programmed or personalised in a few minutes to perform any logical function or combination of logical functions that may be desired. Known PLDs may be programmed to perform the desired function by the use of fusible links or electrical programming techniques such as those used with Electrically Programmable Read Only Memories (EPROMS). Such programmable logic devices have a much lower density than the VLSI integrated circuits they are simulating and so many tens or possibly hundreds of PLDs may be needed to simulate one VLSI intergrated circuit. The major problem with this approach is the large number of interconnections that have to be made between the PLDs. The interconnection needs to be specific to the hardware being simulated. In the past the interconnectio has been hand-wired which is not only extremely time consuming and error prone but also has the result that when built the simulator is unique to the hardware being simulated and cannot easily be reused. In addition, the control of the wiring and its documentation presents a problem of a similar size to the design and control of the intergrated circuit itself. Another problem is ensuring the designs of the simulator and the simulated integrated circuit rmain in step as the design of the integrated circuit is modified. All the problems with these hand-wired simulators are made worse as the size of the circuits being simulated increases. FR-A-2 578 338 describeds a hardware simulator having a plurality of programmable logic devices, a data bus, a control bus, and a control signal generator, each device having an output latch storing an output signal from the said device and an input latch storing an input signal to the said device, each input latch and output latch being selectively connected to the data bus under control of a programmable interconnect logic block, and the control signal generator and each programmable interconnect logic block being connected to the control bus, as set out in the preamble of claim 1. In accordance with the present invention, there is now provided a hardware simulator as set out in claim 1. The invention provides a hardware simulator in which the interconnections between the PLDs are made by programming the programmable interconnect logic blocks associated with each device. There is no need to hand-wire the connections. This allows a quicker, less error prone and more automated setting up of the simulator. The invention also makes it practical to use this type of PLD simulator to simulate VLSI integrated circuit without the problems of controlling and documenting the interconnection becoming unmanageable. It is also easier to make changes to the interconnections as the design of the integrated circuit being simulated is modified. The key element in the hardware simulator is the programmable interconnect logics blocks which allow random logical interconnections to be made via a regular physical hardware structure. It will be appreciated that the interconnect logic block may be a separate device or may be part of the programmable logic device. An example of the operation of this simulator is as follows. The output latches correspond to 'real latches' within the hardware being simulated and the output signals represent the results of the signal processing that has been carried out by the functional logic programmed within the associated PLD during the last simulated clock cycle. The inputs to that functional logic for the last simulated clock cycle were and still are held in the input latches for that PLD. Many of the output latches within the simulator will be holding signals which are in fact required as inputs at other points within the simulator. The task that must be accomplished before the next clock cycle may be simulated is to transfer the signals stored in the output latches to their corresponding input latches as necessary. No separate input latch being needed as the output latch would also directly store the input signal. The invention provides data and control buses for carrying out the transfer of the signals in the output latches to the input latches where they may then be used to simulate the next clock cycle. The overall operation is that a clock cycle is simulated by the PLDs and then the control signal generator issues a sequence of commands on the control bus to the programmable interconnect logic blocks drive the necessary signal transfers. Each command results in one or more output latches writing their signals on to the data bus and one or more input latches, which may be associated with the same or a different PLD, to read in and store the signals on the data bus. When the complete sequence of commands has been run through all the necessary input signals will be in place and up-to-date and the next clock cycle may be simulated. It will be appreciated that the control signals could take a number of forms. What is important is that the programmable interconnect logic devices can interpret the control signals to connect the necessary output latches and input latches to the data bus in the required sequence. One possibility would be to provide a control signal in the form of a master clock signal fed to all the programmable interconnect logic block. The programmable interconnect logic block would have internal clocks synchronised to the master clock and would be programmed to connect the appropriate output latches and input latches to the data bus at predetermined times relative to the master clock signal. In preferred embodiments of the invention said control signals comprise multibit address signals, and each said address signal identifies selected output latches and selected input latches to be connected to said data bus by said programmable interconnect logic blocks. This arrangement permits each data transfer to be individually addressed and allows considerable flexibility in the number, sequencing and timing of the data transfers. Another preferred feature of the invention concerns the manner in which external input signals may be fed to the simulator to test its response in differing conditions and the manner in which diagnostic information is read from the simulator. Preferred embodiments of the invention include a monitor system linked to said data bus and said control bus, said monitor system being responsive to said control signals to read and store output signals from said data bus and to write stimulus signals on to said data bus to be stored in selected input latches. This preferred embodiment allows the monitor system to take advantage of the existing system provided by the hardware simulator to transfer signals between input latches and output latches to feed stimuli into the simulator and read the state of the latches out of the simulator. It will be appreciated that the majority of the time taken to run a simulation with the present invention is taken up with transfer of the signals between the output latches and the input latches. As the size of the integrated circuit increases so the total number of latches to be simulated increases. Simplistically, one would expect an approximately linear increase in simulation time with the number of latches to be simulated. However, most VLSI circuits are composed of a number of quasi self-contained units or functional islands which have relatively few latches in communications with other parts of the integrated circuit. Preferred embodiments of the invention exploit this fact by providing a hardware simulator according to the invention linked to one or more further hardware simulators according to the invention by a master data bus and a master control bus, wherein a master control signal generator issues master control signals on said master control bus control to said hardware simulators to transfer signals from selected output latches in a first hardware simulator to selected input latches in a second hardware simulator via said master data bus. Thus it will be seen that the hardware simulators may carry out their internal signal transfers in parallel with the smaller number of signal transfers between hardware simulators (each corresponding to a functional island) taking place separately. This feature allows VLSI integrated circuits to be simulated without the simulation times becoming too large. In preferred embodiments of the invention said programmable logic devices comprise electrically programmable logic arrays (EPLAs). Such EPLAs may easily be programmed using automated techniques thereby reducing the time taken to configure the hardware simulator and the likelihood of error. Similarly, in preferred embodiments of the invention said programmable interconnect logic blocks comprise electrically programmable logic arrays. Preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 illustrates the prior art interconnection system for the programmable logic arrays. Figure 2 illustrates the simulation strategy when using a hardware simulator composed of programmable logic arrays. Figure 3 illustrates the interconnection structure of one embodiment of the invention. Figure 4 illustrates a programmable logic device / programmable interconnect logic block unit of one embodiment of the invention. Figure 5 illustrates in more detail the programmable logic device / programmable interconnect logic block shown in Figure 4. Figures 6, 7 and 8 illustrate alternative embodiments for interconnection systems for use when simulation integrated circuits have a large number of latches. Figure 1 illustrates a known interconnection system for a hardware simulator comprising a plurality of programmable logic arrays (PLAs) (2). As can be seen the hand-wired links (4) are complex even for the relatively small numbers of PLAs (2) shown. As the number of PLAs (2) increases the complexity and unsuitability of hand-wired links (4) rapidly increases. There is no pattern to the interconnection, it is unique to the integrated circuit being simulated. Figure 2 illustrates the design flow of a simulation strategy using a hardware simulation system composes of programmable logic arrays. The left hand side of Figure 2 covers the design of the logic structure. First a behavioural description (6) is written to verify the design of the whole system. The 'blocks' may be integrated circuits or major portions of integrated circuits. This high level design is converted to a detailed logic description (8) either by hand or by logic synthesis. This logic description (8) is then prepared by software (10) for use on the hardware simulator. There are two parts to this. The first is to determine how to program each of the PLAs to carry out its allocated part of the logical function. The second is to determine the necessary interconnections. As will be discussed later this interconnection involves the programming of the programmable interconnect logic blocks, which themselves comprise PLAs. All the PLAs will be bulk erased (e.g. by exposure to UV light) on their cards and then programmed in situ. The output of the software preparation stage can be a file of programming instructions which can be directly applied to the PLAs. Once the PLAs have been programmed the hardware simulator contains a model of the integrated circuit being modelled. The right hand side of Figure 2 shows the simulation method. When the behavioural model is simulated (12) it produces a self checking test case (14) for the logic level model. This is done by a monitor which records all transitions at the inputs and outputs of a block of logic as if it were the whole system. From these a list of Stimuli and 'Expects' (16) can be generated, one set for each clock cycle. This list is loaded into the monitor system of the hardware simulator. This monitor system applies the first set of stimuli, clocks the programmable logic devices and then checks the appropriate output signals against the expects. No delay simulation is carried out. Timing analysis plus limited software simulation will be adequate for this. Figure 3 illustrates the interconnection structure of one embodiment of the invention and Figure 4 illustrates a unit comprising a programmable logic device (PLD) (20) and a programmable interconnect logic block (PILB) (18) from which the structure of Figure 3 is built up. The PLDs (20) and the PILBs (18) are programmed PLAs. All the PLDs (20) and PILBs (18) are linked to a data bus (22) extending therebetween. All the PILBs (18) are connected to an address bus (24) extending therebetween. The address bus (24) is also connected to an address signal generator (26), whilst the data bus (22) is also connected to a monitor system (28). Both the address signal generator (26) and the monitor system (28) may be embodied within a computer such as a personal computer. Each PLD (20) is programmed to perform the same logical function as a portion of the hardware being simulated. Associated with each PLD (20) are a set of output latches (32). The output latches (32) correspond to latches within the hardware being simulated and store the output signals from their PLD (20) which result from the signal processing carried out by that PLD (20). Some of the output latches will be directly fed back into the PLD (20) to enable the simulation of complex logical functions within the PLD (20). Each PILB (18) is programmed to be responsive to the addresses issued by the address generator (26) on the address bus (24). The address signal generator (26) and the address bus (24) are specific embodiments of the control signal generator and control bus previously discussed. The address signal generator (26) sequentially writes addresses corresponding to selected sets of output latches (32) on to the address bus (24). The PILBs watch for the address of their associated set of output latches (32) to be written on the address bus (24) whereupon the PILB (18) triggers (via line (34)) its associated set of output latches (32) to write their stored output signals on to the data bus (22). The PILBs (18) are also programmed to look for addresses corresponding to the output latch address from which one of their associated set of input latches (30) must receive stored signals. When such an address is on the address bus (24) the PILB (18) response by connecting the input latch concerned to the appropriate line of the data bus (22) from where the selected input latch reads in and stores the signal value which it will feed to the PLD in the next simulated clock cycle. Thus it can be seen that the function of the PILBs (18) is two-fold. They control the writing of signals on to the data bus (22) by associated output latches (32) and they control the read of signals off the data bus (22) by associated input latches (30). Both of these functions are driven by the sequence of addresses written on the address bus (24). When all the sets of output latches have been addressed each output signal will have been written on the data bus (22) from where it should have been picked up by the appropriate input latch (30). Whilst this signal transfer is taking place between the various output and input latches the monitor system (28) can read and store the values on the data bus (22). These values effectively give a snap shot picture of the state of the simulated hardware and may be compare with the lists of 'Expects' to check that the hardware is behaving as it should. A mismatch between the signals read and stored and the 'Expects' would be indicative of an error in the circuit design. It is possible for the monitor system (28) only to read and store certain key signals within the simulated hardware to compare with its 'Expects'. If a design error was found at this level the monitor system (28) could be reprogrammed to look in more detail at the latches associated with the latch upon which the error was occurring to assist in the solving of the error. The monitor system (28) can also be used to supply the 'Stimuli' to the simulator. The monitor system will simply wait for the appropriate address to be written on the address bus (24) whereupon it will write the 'Stimuli' signals on to the data bus (22) from where they will be latched up by the appropriate input latches (30). Once all the signal transfers have been completed the PLDs (20) will all be clocked to simulate a clock cycle of the hardware being simulated. The clock signal fed to the PLDs (20) to trigger the simulation of a clock cycle may be provided by the monitor system or may be provided by an external clock source (not shown). The appropriate input signals generated in the previous simulated clock signal will have been transferred to their inputs and a new set of output signals will be generated and stored in the output latches (32). These fresh output signals will then be transferred and the process repeated. Figure 5 shows in more detail an implementation of one sixteen bit unit of the invention. Since current PLAs are not optimised for the PILB (18) function, a small Intel 5C90 PLA is used with a separate MSI register serving as the input latches (30). The PLD (20) is an Intel 5C180 PLA which provides more inputs and outputs than are needed for a sixteen bit system. The auxiliary inputs of one PLD (20) may be connected to the auxiliary outputs of another PLD (20) yielding an increase in the capability of the system. As previously mentioned it is possible to increase the size of the simulator by simply adding more units to the data bus (22) and the address bus (24). However, simply adding units to the bus in this way would increase the time taken to address every latch and complete a data transfer cycle before the next clock cycle could be simulated. Figure 6 illustrates a different embodiment of the invention which enables larger integrated circuits to be simulated without too large an increase in the time taken to transfer all the signals around the simulator between simulated clock cycles. Each of the blocks (42) represents a system as illustrated in Figure 3. Each of these systems is linked to a master address bus (38) and a master data bus (40). The master address bus corresponds to the master control bus previously described. A master control signal generator (44) monitors the operation of each of the monitor systems (28) within the individual blocks and allows the exchange of signals within each block (42) to proceed in parallel. When the signal exchange within the blocks (42) has been completed the master signal generator (44) then proceeds to carry out the necessary signal transfers between the blocks (42) via the master data bus (40) and the master address bus (38). The master control signal generator (44) is able to selectively connect the local data and address buses within each of the blocks (42) to the master data and address buses via interposed bus transceivers (36). The bus transceivers (36) provide two way switchable gates which allow the local data and address bus in one block (42) to be connected to those of another block via the master data bus (40) and master address bus (38). The overall operation of this system is that first all the local signal transfers are completed in parallel and then the necessary transfers are undertaken between the blocks (42). Figures 7 and 8 show alternative expanded system configurations. In the embodiment of Figure 7 one monitor system is used to control two bus systems. The same addresses are supplied to each bus system but the data buses of each can be selectively connected or kept separate by the action of the bus transceivers (36). Accordingly, transfers can take place in parallel within each bus system and the data buses need only be connected when a transfer between bus systems is required. In the embodiment of Figure 8 the number and size of the local data buses is itself configurable using the bus transceivers (36). The same address signal is supplied to each programmable logic device but the grouping of the devices into local block sharing a data bus is controlled by the bus transceivers (36). Accordingly, some local blocks may be small and others large depending upon the circuit being simulated. Figures 7 and 8 illustrate the diversity and flexibility of systems using the invention that can be produced.

Claims: A hardware simulator for simulating logic function of integrated circuit hardware according to simulated clock cycles initiated by clock signals, the simulator comprising: a data bus (20) for carrying input and output data signals; a control bus (24); a control signal generator (26) connected to the control bus; and a plurality of programmable logic devices (20); and a plurality of programmable interconnect logic blocks (18) connected to the control bus, each said block being connected to a corresponding one of the said devices; said simulator further comprising that: the said programmable logic devices executing programmed algorithmic functions on input data signals and providing corresponding output signals upon receipt of a clock signal indicative of a simulated clock cycle, each said device comprising a set of input latches (30) storing input signals to said device and a set of output latches (32) storing output signals from said device, each said device being preprogrammed to execute an algorithmic function corresponding to a logic function of the hardware being simulated, and the input latch of each said device storing input data signals prior to executing the algorithmic function; the control signal generator (26) providing control signals on the control bus in a sequence, the sequence being provided between the simulated clock cycles; and, each said block (18) being preprogrammed for selectively connecting the input and output latches of the corresponding said device to the data bus in response to the control signals on the control bus; whereby the control signal generator (26) controls the said blocks according to the sequence of control signals to effect a corresponding sequence of signal transfer steps in which input and output data signals are transferred between the input latches, the output latches, and the data bus between the simulated clock cycles; said simulator characterised by: the output latches corresponding to a real latch within the hardware being simulated; and said control signals provided by the control signal generator (26) including first master clock signals fed to all said blocks (18), whereby said blocks use internal clocks that are synchronised to said first master clock for said selective connecting of the input and output latches. A hardware simulator as claimed in claim 1, wherein said control signals compromise multibit signals. A hardware simulator as claimed in claims 1 or 2, further comprising a monitor system (28) linked to said data bus and said control bus, said monitor system being responsive to said control signals to read and store output signals from said data bus and to write stimulus signals on to said data bus to be stored in selected input latches. A hardware simulator as claimed in claims 1, 2 or 3 wherein said programmable logic devices comprise electrically programmable logic arrays. A hardware simulator as claimed in any preceding claim, wherein said programmable interconnect logic blocks comprise electrically programmable logic arrays. A hardware simulator system comprising a hardware simulator (42) as claimed in any preceding claim linked to one or more further hardware simulators (42) as claimed in any preceding claim by a master data bus (40) and a master control bus (38), wherein a master control signal generator (44) issues second master control signals on said master control bus control to said hardware simulators to transfer signals from selected output latches in a first hardware simulator to selected input latches in a second hardware simulator via said master data bus. A system as claimed in claim 6, wherein the size of the data buses of each simulator is configurable by bus transceiver means (36).

Inventors: WINLOW THOMAS, WINLOW, THOMAS
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: G06F17
IPC codes: G01R31, G06F17