Photoelectric converting apparatus

Abstract: There is provided a photoelectric converting apparatus comprising: an accumulating unit to accumulate charges which were light excited; an amplifying unit to amplify charges of a control electrode; a switching device to connect the accumulating unit and the control electrode; a first reading unit to read out an output of the amplifying unit as a first signal when the switching device is set into a nonconductive state; a transferring unit to make the switching device conductive and to transfer the charges in the accumulating unit to the control electrode; a second reading unit to read out the output of the amplifying unit as a second signal after the charges were transferred; and a subtraction proces­ sing circuit to execute a subtracting process between the first and second signals.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric converting apparatus which intends to reduce sensor noises. Description of the Related Background Art As a sensor which is used in a solid state image pickup device or the like, an amplifying type sensor is preferably used to increase an output signal level and the like. The amplifying type sensor is constructed by a transistor of the MOS type, SIT type, FET type, bipolar type, etc. and charge amplifies or current amplifies the charges accumulated in their control electrodes and outputs from a main electrode. For instance, an example of the amplifying type sensor has been disclosed in Japanese Patent Publication Gazette No. 55-28456. As one of the problems of such amplifying type sensors, a point that the sensor noises are large can be mentioned. The sensor noises are generally mainly classified into fixed pattern noises (hereinafter, referred to as FPN) which fixedly appear and random noises which are fetched to the control electrode when the control electrode is reset. Among the sensor noises, since the FPN fixedly appear, they can be completely eliminated by subtracting a dark-state output of the sensor from the photo signal output of the sensor. The dark-state output can be obtained by reading out the output immediately after the accumulation time was set to almost zero, that is, after the sensor was reset. On the other hand, in order to also eliminate the random noises which were fetched to the control electrode, it is sufficient to subtract the sensor output (photo signal) after completion of the accumulation from the sensor output (sensor noises) just after the start of the accumulation. As such a photoelectric converting apparatus which can execute the subtracting process, there is an apparatus disclosed in Japanese Patent Application No. 63-47492 which has already been filed by the applicant of the present invention. The above photoelectric converting apparatus has means for storing a photo signal and storage means for storing sensor noises, wherein a difference between the photo signal and the sensor noises which were stored in both of the storage means is obtained. Although such a photoelectric converting apparatus is very practical when it is used for a line sensor, in the case where it is used for an area sensor, a chip area of the storage means for storing the sensor noises increases. Even if the storage means is provided in the outside of an image pickup device, a field memory or a frame memory is necessary and there is a problem on costs, so that it is difficult to put such an apparatus into practical use. On the other hand, there is an apparatus in which a photoelectric converting region is laminated to the upper portion of an amplifying transistor in order to increase the sensitivity of the sensor and to relatively reduce an influence by the sensor noises. As such a solid state image pickup apparatus, there is an apparatus disclosed in Japanese Patent Application No. 1-9089 (EP-A-0379349) which has already been filed by the applicant of the present invention. According to the above solid state image pickup apparatus, if a photoconductive film is laminated, a numerical aperture of the photoelectric converting region is extremely large, so that a sensor output (S) also similarly increases. However, to realize a further higher S/N ratio, it is necessary to reduce sensor noises (N). EP-A-0232593 and EP-A-0260954 both describe arrangements in which a noise signal and a photo signal are read from an amplifying sensor transistor and subtracted in a differential amplifier. In EP-A-0260954 a switching means connects the noise signal and the photo signal in turn to the input of a common amplifier, so that the signals are amplified before they reach the differential amplifier. JP-A-63-100879 proposes a photoelectric conversion device having a two-dimensional array of pixels. Each pixel comprises an amplifying MOSFET, a photodiode, two switching MOSFETS and a resetting MOSFET. The photodiode is connected to the gate of the amplifying MOSFET through the two switching MOSFETS. In each pixel, one switching MOSFET is controlled by a row select control line and the other switching MOSFET is controlled by a column select control line. The resetting MOSFET is also connected to the gate of the amplifying MOSFET. In operation, the gate of the amplifying MOSFET is reset and then this transistor is turned on, providing a source follower output to a correlation double sampling means. Subsequently, the switching MOSFETS for the selected pixel are turned on, connecting the photodiode to the gate of the amplifying MOSFET, and a further source follower output is provided to the correlation double sampling means. Thus the correlation double sampling means is able to compensate the second source follower output (representing the photodiode signal) for the noise component represented by the first source follower output. SUMMARY OF THE INVENTION According to the present invention there is provided a photoelectric conversion device as set out in claim 1. The remaining claims set out optional features. By providing the switching transistor between the accumulating means for accumulating photo-induced charges and the control region of the amplifying transistor, the sensor noises can be independently read out irrespective of the operation of the accumulating means. Not only the FPN but also the dark current component of the amplifying device and the random noises can be eliminated. In an embodiment, there is provided resetting means for resetting the control region of the amplifying transistor before the charges of the accumulating means are coupled to it, the output of the amplifying transistor is read out as the first signal after the control region is reset, and after the switching transistor couples the charges in the accumulating means to the control electrode, the output of the amplifying transistor is read out as the second signal. Due to this, the dark current component of the amplifying transistor is eliminated before the photo charges are coupled and the potential of the control region of the amplifying transistor is set to be lower than the accumulation potential of the accumulating means. Thus, the photo charges can be completely transferred from the accumulating means to the amplifying transistor. If an accumulating region serving as accumulating means and the amplifying transistor are formed on a substrate and a photoelectric converting region is laminated over the amplifying transistor and the photoelectric converting region and the accumulating region are connected, the numerical aperture can be enlarged and the S/N ratio can be increased. In an embodiment, there is provided a photoelectric converting apparatus having a plurality of pixels in each of which accumulating means for accumulating light excited charges, an amplifying transistor for amplifying charges of a control region, and a transferring device to connect the accumulating means and the control region are used as component elements, wherein the apparatus comprises: resetting means which is provided between the control regions of the pixels which are adjacent in the sub-scanning direction; means for (i) resetting the control regions by the resetting means and for reading out an output of the amplifying transistor as a first signal; (ii) making the transferring devices conductive and for transferring the charges of the accumulating means to the control regions; and (iii) for reading out the output of the amplifying transistor as a second signal after the charges were transferred; and subtracting processing means for executing a subtracting process between the first and second signals. Therefore, according to the above embodiment, further, the resetting means for resetting the control region of the amplifying transistor before the charges in the accumulating means are transferred to the amplifying transistor is provided, the output of the amplifying transistor is read out as a first signal after the control regions were reset, and the output of the amplifying transistor is read out as a second signal after the transferring devices were made conductive and the charges in the accumulating means were transferred to the control regions. Therefore, the dark current component of the amplifying transistor is eliminated before the photo charges are transferred and the potential of the control region of the amplifying transistor is set to be lower than the accumulation potential of the accumulating means. Therefore, the photo charges can be completely transferred from the accumulating means to the amplifying transistor. On the other hand, according to the embodiment of the invention, the resetting means is provided between the control regions of the pixels which are adjacent in the sub-scanning direction and the control regions are reset by the resetting means. Therefore, the pixels arranged in the sub-scanning direction can be reset simultaneously with the resetting operation in the main scanning direction and an operation to reduce smear is obtained. In the specification, the term "smear" denotes a phenomenon in which when the signal corresponding to the accumulated charges is read out, the potentials of the control regions of the amplifying transistors which are not selected rise and outputs appear from those amplifying transistors due to excessively strong light irradiation or the like. The reason why smear can be reduced by the embodiment is because the control regions of the amplifying transistors which are not selected can be also reset together with the control region of the amplifying transistor which is selected, before the signal corresponding to the accumulated charges is read out of the selected amplifying transistor, so that no output appears from the amplifying transistors which are not selected. Embodiments of the present invention will be described in the following detailed description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial circuit diagram of a first embodiment of a photoelectric converting apparatus of the invention; Fig. 2 is a schematic plan view of pixels of the photoelectric converting apparatus of Fig. 1; Fig. 3 is a cross sectional view taken along the line X-X′ of the photoelectric converting apparatus of Fig. 2; Figs. 4A and 4B are cross sectional views taken along the line Y-Y′ of the photoelectric converting apparatus of Fig. 2; Fig. 5 is a timing chart for the photoelectric converting apparatus of Fig. 1; Fig. 6 is a partial circuit diagram of the second embodiment of a photoelectric converting apparatus of the invention; Fig. 7 is a partial circuit diagram of the third embodiment of a photoelectric converting apparatus of the invention; Figs. 8A and 8B are cross sectional views of sensors in the fourth and fifth embodiments of the invention; Fig. 9 is a schematic constructional diagram of a solid state image pickup device to which the invention is applied; Fig. 10 is a timing chart for a photoelectric converting apparatus of the sixth embodiment of the invention; Fig. 11 is a partial circuit diagram of the seventh embodiment of a photoelectric converting apparatus of the invention; Fig. 12 is a schematic plan view of pixels of the photoelectric converting apparatus of Fig. 11; Fig. 13 is a cross sectional view taken along the line X-X′ of the photoelectric converting apparatus of Fig. 12; Fig. 14 is a cross sectional view taken along the line Y-Y′ of the photoelectric converting apparatus of Fig. 12; and Fig. 15 is a timing chart for explaining the operation of the photoelectric converting apparatus of Fig. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 1 is a partial circuit diagram of the first embodiment of a photoelectric converting apparatus of the invention. Fig. 2 is a schematic plan view of pixels of the photoelectric converting apparatus. Fig. 3 is a cross sectional view taken along the line X-X′ of the photoelectric converting apparatus of Fig. 2; Figs. 4A and 48 are cross sectional views taken along the line Y-Y′ of the photoelectric converting apparatus of Fig. 2. As shown in Fig. 1, one pixel comprises: a PMOS transistor Tr A to reset the pixel; a capacitor Co X to control the transient resetting operation of the pixel and the accumulating and reading operations of a signal; a photodiode D serving as accumulating means for accumulating charges which were light excited; an amplifying transistor Tr C to amplify a signal from the photodiode D; and a PMOS transistor Tr B serving as a switching device to transfer the charges which were generated in a photoelectric converting unit of the photodiode D to a base serving as a control electrode of the amplifying transistor Tr C .  VR and  TB denote pulses to control the PMOS transistors Tr A and Tr B , respectively. An emitter of the amplifying transistor Tr C is connected to accumulation capacities C1 and C2 through MOS transistors T 1 and T 2 .  T1 and  T2 denote pulses to control the MOS transistors T 1 and T 2 , respectively. T VC denotes an MOS transistor to reset a vertical signal line. A potential of the MOS transistor T VC is set to a potential V VC by the control of a pulse  VC . As shown in Figs. 2 and 3, the pixels are isolated by the PMOS transistors Tr A (shown by a broken line in Fig. 3). The capacitor Co X is formed in a part of a base B of the amplifying transistor Tr C by a poly layer L 1 provided on an SiO 2 layer. An emitter E is wired and connected as a vertical output line over the pixel isolation region by an Aℓ layer L 2 . As shown in Figs. 2, 4A and 4B, the photodiode D serving as a photoelectric converting unit and the base B of the amplifying transistor Tr C are isolated by the switching device comprising the PMOS transistor Tr B (shown by broken lines in Figs. 4A and 4B). Although the portions other than the photodiode D are generally light shielded, a light shielding layer is omitted in Figs. 2 to 4B. n′ denotes a channel doping region. The operation of the photoelectric converting apparatus will now be described hereinbelow with reference to Figs. 1 to 4B. Fig. 5 is a timing chart for explaining the operation of the photoelectric converting apparatus. In Fig. 5, first, T 1 denotes a resetting interval (f 0 ) of a pixel line in the horizontal direction. The pulses  VR and  TB are set to a negative potential (-V) and the PMOS transistor Tr A and the switching device Tr B are set to the ON state, and the horizontal pixel line after completion of the reading operation of the charges are reset. T 2 indicates a transient resetting interval of a pixel line in the horizontal direction. When the pulse  VR is set to a positive potential (+V), the PMOS transistor Tr A is turned off and the potential of the base of the amplifying transistor Tr C and the potential of the photodiode D increase through the capacitor Co X . At the same time, the pulse  VC is set to the high level and the MOS transistor T VC is turned on, thereby setting the emitter of the amplifying transistor Tr C to a predetermined potential V VC . At this time, the residual charges in the photodiode D and the base of the amplifying transistor Tr C are eliminated by the recombination with an emitter current (such a state is called a transient reset). After that, when the pulse  VC is set to the low level and the MOS transistor T VC is turned off and the pulse  VR is set from the positive potential to the earth potential (GND), the potential of the base of the amplifying transistor Tr C and the potential of the photodiode D also decrease through the capacitor Co X . Further, when the pulse  TB is set to the high level and to the earth potential (GND), the PMOS transistor Tr B is turned off and the photodiode D starts the accumulation. T 3 denotes a switching interval (f 0 → f 1 ) of the row which is selected by vertical scan. The vertical scan to change over the rows is executed by a vertical shift register (not shown). A horizontal pixel line of the next row are selected by the control of pulses  V1 and  V2 . T 4 indicates a residual charge clearing interval of the accumulation capacitor C 1 . When the pulses  VC and  T1 are set to the high level, the MOS transistors T VC and T 1 are turned on and the residual charges in the accumulation capacitor C 1 are cleared. After that, the pulse  VC is set to the low level and the MOS transistor T VC is turned off. T 5 represents a reading interval of the sensor noises. By setting the pulse  VR to a positive potential (+V) and raising the base potential of the amplifying transistor Tr C , the reading operation of the signal from the amplifying transistor Tr C is executed. At this time, the base potential is a dark-state output potential. An output voltage depending on the characteristics of the amplifying transistor Tr C appears in the emitter. Such an output voltage is generally called an offset voltage. Since parameters of a plurality of amplifying transistors slightly differ, their emitter output voltages, that is, their offset voltages also differ. Differences among the offset potentials are now called sensor noises. The sensor noises are accumulated in the accumulation capacitor C 1 . T 6 denotes a residual charge clearing interval of the accumulation capacitor C 2 . When the pulses  VC and  T2 are set to the high level, the MOS transistors T VC and T 2 are turned on and the residual charges in the accumulation capacitor C 2 are cleared. After that, by setting the pulse  VC to the low level, the MOS transistor T VC is turned off. T 7 indicates an interval to transfer the photo charges of the photodiode D to the base of the amplifying transistor Tr C . When the pulse  TB is set to the low level and to a negative potential (-V), the PMOS transistor Tr B is turned on, so that the photo charges accumulated in the photodiode D are transferred to the base of the amplifying transistor Tr C . T 8 represents a reading interval of a photo signal. When the pulse  VR is set to a positive potential (+V), the base potential of the amplifying transistor Tr C rises through the capacitor Co X and a photo signal output is read out of the amplifying transistor Tr C . The foregoing sensor noises are included in the photo signal and are accumulated into the accumulation capacitor C 2 . Signals of respective columns from the accumulation capacitors C 1 in which the sensor noises are accumulated and signals of repective columns from the accumulation capacitors C 2 in which the photo signals are accumulated are transferred to horizontal output lines through horizontal transfer switches Th which are driven and selected by a horizontal shift register HSR. Since output terminals of the horizontal output lines are connected to a differential amplifier DA, the sensor noises are eventually subtracted from the photo signals and only the photo signals can be obtained. The subtracting process of the sensor noises will now be described in detail hereinbelow. According to the results of the experiments, the FPN after completion of the transient resetting differ due to differences of parameters such as h FE and the like of the amplifying transistors Tr C and a variation of ΔV occurs among base potentials V B after completion of the transient resetting. In the case of the emitter output, such a variation ΔV is increased by about (1 + Cb e /C B ) times by the reading operation. C B denotes a synthesized capacity of a base-collector capacity C bc , a base-emitter capacity C be , and the capacity Co X . On the other hand, the random noise component corresponds to kTC noises upon resetting which depend on the synthesized capacity C B for the interval T 1 , random noises upon execution of the reading operation of the sensor transistor, and random noises upon transfer of the photo charges of the photodiode D for the intervals T 7 and T 8 . The kTC noises upon resetting slightly decrease by the transient resetting and are set to a value multiplied with about K (= 1/√2) . However, such kTC noises are eliminated by the above subtracting process. On the other hand, the random noises upon transfer of the photo charges are band limited by a base input time constant and are so small to be ignored. Further, although the random noises upon reading operating depend on the base capacity C B , a load capacity C V and an accumulation capacity C T when they are seen from the emitter side, a current amplification factor h FE , and the like, it has been found out that by setting the current amplification factor h FE to a large value to thereby increase a nondestructive degree, the random noises upon reading operation can be set to be extremely smaller than the random noises upon resetting. This means that with respect to the FPN and kTC noises of the sensor, the S/N ratio can be fairly improved by the subtracting process between the photo signal and the sensor noises. In the CCD, after the charge/voltage conversion output was amplified, the kTC noises due to the reset transistor are eliminated by a correlation double sampling method; however, the amplification noises are dominant because of the high-speed driving. In the apparatus in which each pixel is constructed by an amplifying device as in the embodiment, the scanning is executed at a low speed by one horizontal scanning interval (1H), so that the amplification noises, that is, the readout noises are extremely small. On the other hand, the dark current component of the amplifying transistor is also eliminated when the subtraction between the sensor noises and the photo signal is executed. Fig. 6 is a partial circuit diagram of the second embodiment of a photoelectric converting apparatus of the invention. It is a feature of the second embodiment that the PMOS transistors Tr A and Tr B are serially connected and the photodiode D is arranged at a node of those transistors. Such an arrangement is preferably used in the case where the horizontal pixel size is larger than the vertical pixel size. The pixels are reset by setting pulses  VR1 and  VR2 to a negative potential and turning on the PMOS transistors Tr A and Tr B . The transient resetting is executed in a manner such that the pulse  VR2 is set to a positive potential to thereby turn off the PMOS transistor Tr B , the potential of the base of the amplifying transistor Tr C is increased through the capacitor Co X , and the emitter of the amplifying transistor Tr C is set to a predetermined potential. The accumulation of the charges is executed in a manner such that the pulses  VR1 and  VR2 are set to the earth potential (GND) to thereby turn off the PMOS transistors Tr A and Tr B and the charges are accumulated into the photodiode D. The sensor noises are read out in a manner such that after completion of the charge accumulation, the pulse  VR2 is set to a positive potential to thereby turn off the PMOS transistor Tr B , the base potential of the amplifying transistor Tr C is increased through the capacitor Co X , and the sensor noises are read out of the emitter of the amplifying transistor Tr C . The photo signal is read out in the following manner. That is, the pulse is  VR2 set to the earth potential (GND) to thereby turn off the PMOS transistor Tr B . The pulse  VR1 is set to a negative potential to thereby turn on the PMOS transistor Tr A . The photo charges of the photodiode D are transferred to the base of the amplifying transistor Tr C . The pulse  VR1 is set to the earth potential (GND) to thereby turn off the PMOS transistor Tr A . The pulse  VR2 is set to a positive potential to thereby turn off the PMOS transistor Tr B . The base potential of the amplifying MOS transistor Tr C is raised through the capacitor Co X . The photo signal is read out of the emitter of the amplifying MOS transistor Tr C . Although the operating method of the second embodiment slightly differs from that of the first embodiment, the sensor noises can be eliminated in a manner similar to the first embodiment. Fig. 7 is a partial circuit diagram of the third embodiment of a photoelectric converting apparatus of the invention. A feature of the third embodiment is that an MOS transistor is used as an amplifying device. In the diagram, an MOS transistor Tr A ′ is a resetting MOS transistor to clear the residual charges in a gate region serving as a control electrode of an MOS transistor Tr C ′. In the first embodiment, the transient resetting has been executed since the amplifying device is constructed by a bipolar transistor. However, in the third embodiment, since the amplifying device comprises an MOS transistor, the transient resetting operation is unnecessary. The random noises included in photo charges accumulated in the photo diode D which are transferred to the gate and are read out from the MOS transistor, result in that the correlation between the sensor noises and the sensor noises included in the photo signal output is very high. Because the gate charges in a control electrode are not destroyed upon reading if an MOS transistor or an FET is used as an amplifying device of the sensor MOS transistor. Therefore, the sensor of a high S/N ratio can be eventually obtained. Figs. 8A and 8B are cross sectional views of sensors in the fourth and fifth embodiments of the invention, respectively. It is a feature of the 4th and 5th embodiments that a laminated photoconductive film is used in a photoelectric converting region. As shown in the diagrams, a pixel electrode from a photoconductive film is connected to the photodiode unit in Fig. 4 in the first embodiment of the photo-electric converting apparatus. In the diagram, reference numeral 1 denotes a photoconductive film; 2 indicates a transparent electrode; 3 a pixel electrode; and 4 an insulative layer. The film 1 is connected to ap type semiconductor region constructing the photodiode unit through the pixel electrode 3. According to the 4th and 5th embodiments, since the photoconductive film can be also provided over the amplifying device unit, the numerical aperture can be increased and the S/N ratio can be raised. Fig. 9 is a schematic constructional diagram of a solid state image pickup device to which the invention is applied. In the diagram, an image pickup device 201 in which photosensors are arranged like an area is television scanned by a vertical scanning unit 202 and a horizontal scanning unit 203. A signal output from the horizontal scanning unit 203 is output as a standard television signal through a processing circuit 204. Drive pulses  HS ,  H1  H2 ,  VS ,  V1 ,  V2 , etc. of the vertical and horizontal scanning units 202 and 203 are supplied by a driver 205. On the other hand, the driver 205 is controlled by a controller 206. As described in detail above, according to the photoelectric converting apparatus of each of the embodiments of the invention, by providing the switching means between the accumulating means for accumulating the light excited charges and the amplifying means for amplifying the charges of the control electrode, the sensor noises of the amplifying device can be independently read out irrespective of the operation of the accumulating means. Not only the FPN but also the dark current component and random noises of the amplifying device can be eliminated. On the other hand, the amplifying device can be driven at a low speed. The noises upon reading can be fairly reduced. Thus, an image pickup device of a high S/N ratio can be realized. If the accumulating region serving as accumulating means and the amplifying region serving as amplifying means are formed onto the substrate and the photoelectric converting region is laminated onto the amplifying region and the photoelectric converting region and the accumulating region are connected, the numerical aperture can be increased and the S/N ratio can be raised. Fig. 10 is a timing chart for the sixth embodiment of the invention. In Fig. 10, T 11 denotes a complete resetting interval of the amplifying transistor Tr C in the horizontal direction. T 11 also indicates an output interval of signals and sensor noises from the accumulation capacitors C 1 and C 2 , which will be explained hereinlater. The complete resetting is performed by setting the pulse  VR to a negative potential (V L shown in the diagram) and turning on the PMOS transistor Tr A . The base potential is clamped to the GND by the complete resetting. Due to this, the dark current component of the amplifying transistor can be eliminated. For an interval T 12 , the transient resetting is executed subsequently to the complete resetting at the interval T 11 . By setting the pulse  VR to a positive potential (V H shown in the diagram), the PMOS transistor Tr A is turned off. The base potential of the amplifying transistor Tr C increases through the capacitor Co X . At the same time, by setting the pulse  VC to the high level, the MOS transistor T VC is turned on, thereby setting the emitter of the amplifying transistor Tr C to a predetermined potential V VC . At this time, a quantity of base charges of the amplifying transistor Tr C rapidly decreases due to the recombination with the emitter current. On the other hand, by setting the pulse  T1 to the high level, the MOS transistor T 1 is turned on and the accumulation capacitor C 1 is set to a predetermined reset potential V VC . T 13 denotes a reading interval of the sensor noises. The pulse  VR is held to the positive potential V H . In this state, by setting the pulse  VC to the low level, the MOS transistor T VC is turned off and the emitter of the amplifying transistor Tr C is set into the floating state. Thus, the voltage of the emitter terminal is set to a potential to which the base voltage is reflected. The base potential at this time corresponds to the dark-state output potential. An offset voltage depending on the characteristics of the amplifying transistor Tr C appears at the emitter. In the specification, the differences among the offset potentials of the amplifying transistors are called sensor noises. The sensor noises are accumulated into the accumulation capacitor C 1 . After the sensor noises were read out, the pulse  VR changes from the high voltage V H to an intermediate voltage V M . The base of the amplifying transistor Tr C is reversely biased through the capacitor Co X by such a potential change. T 14 denotes an interval to transfer the photo charges of the photodiode D to the base of the amplifying 1, transistor Tr C . By setting the pulse  TB to a low voltage and to a negative potential (V L ), the transfer device Tr B is turned on and the photo charges accumulated in the photodiode D are transferred to the base of the amplifying transistor Tr C . Since the base potential of the amplifying transistor Tr C is set to be lower than the potential of the photodiode D, the photo charges are completely transferred from the photodiode D to the amplifying transistor Tr C . After the interval T 14 , by setting the pulse  VC to the high level, the MOS transistor T VC is turned on. By setting the pulse  T2 to the high level, the MOS transistor T 2 is turned on. Thus, the accumulation capacity C 2 is set to a predetermined reset potential V VC . T 15 indicates a reading interval of the photo signal. When the pulse  VR is set to a positive potential (V H ), the base potential of the amplifying transistor Tr C rises through the capacitor Co X and the photo signal output is read out of the amplifying transistor Tr C . The above sensor noises are included in the photo signal and accumulated into the accumulation capacity C 2 . Signals of respective columns from the accumulation capacitors C 1 in which the sensor noises are accumulated and signals of respective columns from the accumulation capacitors C 2 in which the photo signals are accumulated are transferred to horizontal output lines through horizontal transfer switches Th which are driven and selected by the horizontal shift register HSR. Since output terminals of the horizontal output lines are connected to the differential amplifier DA, the sensor noises are eventually subtracted from the photo signals and only the photo signals can be obtained in a manner similar to the cases of the first to fifth embodiments. At the timing in the embodiment shown in Fig. 10, the transient resetting is executed at the interval T 12 . However, the transient resetting is not an inevitable condition. For instance, in the case where a bipolar transistor is used as an amplifying transistor, the transient resetting can be executed. However, in the case of an MOS transistor, the transient resetting cannot be performed. As mentioned above, according to the sixth embodiment of the invention, the resetting means for resetting the control electrode of the amplifying means before the charges in the accumulating means are transferred to the amplifying means is provided and, after the control electrode was reset, the output of the amplifying means is read out as a first signal, while after the transfer device was made conductive and the charges in the accumulating means were transferred to the control electrode, the output of the amplifying means is read out as a second signal. Thus, the dark current component of the amplifying means can be eliminated before the photo charges are transferred. The potential of the control electrode of the amplifying means is set to be lower than the accumulation potential of the accumulating means. The photo charges can be completely transferred from the accumulating means to the amplifying means. The seventh embodiment of the invention will now be described in detail with reference to the drawings. Fig. 11 is a partial circuit diagram of the seventh embodiment of a photoelectric converting apparatus of the invention. Fig. 12 is a schematic plan view of pixels of the photoelectric converting apparatus of Fig. 11. Fig. 13 is a cross sectional view taken along the like X-X′ of the photoelectric converting apparatus of Fig. 12. Fig. 14 is a cross sectional view taken along the line Y-Y′ of the photoelectric converting apparatus of Fig. 12. Although photoelectric converting units of the photoelectric converting apparatus of the seventh embodiment are arranged like a matrix, only four pixels are shown for simplicity of drawing in Fig. 11. As shown in Fig. 11, one pixel comprises: the PMOS transistor Tr A to reset the pixel; the capacitor Co X to control the transient resetting of the pixel and the accumulating and reading operations of the signal; the photodiode D serving as accumulating means for accumulating the light excited charges; the amplifying transistor Tr C to amplify the signal from the photodiode D; and the transfer device Tr B to transfer the charges generated in the photoelectric converting unit of the photodiode D to the base serving as a control electrode of the amplifying transistor Tr C . The gates of the PMOS transistors Tr B of the pixels arranged in the main scanning direction and one of the terminals of each of the capacitors Co X are commonly connected. All of the gates of the PMOS transistors Tr A of the pixels arranged in the main scanning direction and the sub-scanning direction are commonly connected.  C and  VR(n) denote pulses to control the PMOS transistor Tr A and the transfer device Tr B , respectively. The emitter of the amplifying transistor Tr C is connected to the accumulation capacitors C 1 and C 2 through the MOS transistors T 1 and T 2 . The sensor noises and signals are respectively accumulated into the accumulation capacitors C 1 and C 2 and are output as a sensor noise output (S out ) and a signal output (N out ) by the control of the pulses  H1 and  H2 from the horizontal shift register HSR.  T1 and  T2 denote the pulses to control the MOS transistors T 1 and T 2 , respectively. T VC indicates an MOS transistor to reset vertical signal lines. The MOS transistor T VC is set to the potential V VC by the control of the pulse  VC . As shown in Figs. 12 and 14, the bases B serving as control electrodes of the pixels are isolated in the sub-scanning direction by the PMOS transistor Tr A (shown by a broken line in Fig. 14). When the PMOS transistor Tr A is turned on, the base B of each pixel is reset. Although each pixel is formed over a p type substrate as shown in Figs. 13 and 14, it can be also formed over an n type substrate. On the other hand, as shown in Fig. 13, the capacitor Co X is formed in a part of the base B of the amplifying transistor Tr C by the poly layer L 1 provided over the SiO 2 layer. The emitter E is wired and connected as a vertical output line by the Aℓ layer L 2 . As shown in Fig. 12, the photodiode D serving as a photoelectric converting unit and the base B of the amplifying transistor Tr C are isolated by the transfer device comprising the PMOS transistor Tr B (shown by a broken line in Fig. 13). When the PMOS transistor Tr B is turned on, the charges accumulated in the photodiode D are transferred to the base B of the amplifying transistor Tr C . Although the portions other than the photodiode D are generally light shielded, this is omitted in Figs. 12 to 14. The operation of the photoelectric converting apparatus will now be described hereinbelow with reference to Figs. 11 to 14. Fig. 15 is a timing chart for explaining the operation of the photoelectric converting apparatus. In Fig. 15, T 21 denotes a resetting interval of a pixel train in the sub-scanning direction. By setting the pulse  C to a negative potential (-V), the PMOS transistor Tr A is turned on, and the control electrode (base) of the amplifying transistor Tr C is reset before the sensor noises and the signal are read out. T 22 indicates a transient resetting interval of a pixel train in the sub-scanning direction. When the pulse  VR is set to a positive potential (+V), the base potential of the amplifying transistor Tr C rises through the capacitor Co X . At the same time, by setting the pulse  VC to the high level, the MOS transistor T VC is turned on and the emitter of the amplifying transistor Tr C is set to a predetermined potential V VC . At this time, the base potential of the amplifying transistor Tr C rapidly decreases by the recombination of the charges at the base and the emitter current (such a phenomenon is called a transient reset). By also setting the pulse  T1 to the high level, the MOS transistor T 1 is turned on and the potential of the accumulation capacitor C 1 is set to the potential V VC . For an interval T 23 , by setting the pulse  VC to the low level, the MOS transistor T VC is turned off, the emitter of the amplifying transistor Tr C is set into a floating state, and the sensor noises are read out. The base potential at this time corresponds to the dark-state output potential and the output voltage depending on the characteristics of the amplifying transistor Tr C appears at the emitter. Such an output voltage is generally called an offset voltage. Since parameters of a plurality of amplifying transistors slightly differ, the emitter output voltages, that is, the offset voltages also differ. The differences of the offset potentials are called sensor noises. The sensor noises are accumulated into the accumulation capacitor C 1 . After the interval T 23 , the pulse  VC is set to the high level and the MOS transistor T VC is turned on. At the same time, by setting the pulse  T2 to the high level, the MOS transistor T 2 is turned on and the potential of the accumulation capacitor C 2 is set to the potential V VC . T 24 denotes an interval to transfer the photo charges in the photodiode D to the base of the amplifying transistor Tr C . When the pulse  VR(n) is set to a low level and to a negative potential (-V), the PMOS transistor Tr B is turned on. The photo charges accumulated in the photodiode D are transferred to the base of the amplifying transistor Tr C . T 25 indicates a reading interval of the photo signal. When the pulse  VC is set to a positive potential (+V), the base potential of the amplifying transistor Tr C rises through the capacitor Co X and the photo signal output is read out of the amplifying transistor Tr C . The sensor noises are included in the photo signal. The sensor noises are accumulated into the accumulation capacitor C 2 . The horizontal transfer switches Th are controlled to be turned on and off by the pulses  H1 and  H2 which are output from the horizontal shift register HSR and the signals of respective columns from the accumulation capacitors C 1 in which the sensor noises are accumulated and the signals of respective columns from the accumulation capacitors C 2 in which the photo signals are accumulated are output as a sensor noise output (S out ) and a signal output (N out ) to the horizontal output lines (interval T 26 ) under control of the horizontal transfer switches. Since the output terminals of the horizontal output lines are connected to a differential amplifier, the sensor noises are eventually subtracted from the photo signal and only the photo signal can be obtained. According to the seventh embodiment of the invention, by providing the resetting means between the control electrodes of the pixels which are adjacent in the sub-scanning direction and by resetting the control electrodes by the resetting means, the pixels arranged in the sub-scanning direction can be reset simultaneously with the resetting of the pixels arranged in the main scanning direction and the smear can be reduced.

Claims: A photoelectric conversion device comprising a two-dimensional array of pixels, each pixel comprising: (i) an amplifying transistor (Tr C , Tr C ') for providing an amplified read-out signal to an output line in accordance with the effect of photo-induced charges on its control region; (ii) accumulating means (D) for accumulating photo-induced charges; and (iii) a switching transistor (Tr B , Figs. 1-5, 7, 8, 10-15; Tr A , Fig. 6) for separating the accumulating means from the control region of the amplifying transistor and for coupling the photo-induced charges from the accumulating means to the control region, the photoelectric conversion device further comprising means for reading a first signal from the amplifying transistor before the stored charges are coupled to the control region and for reading a second signal from the amplifying transistor after the stored charges have been coupled to the control region, the first signal providing a noise compensation signal for use in processing the second signal by subtraction between the first and second signals, and means (T VC ) for resetting the said output line to a predetermined potential (V VC ). A device according to claim 1 in which the switching transistor is an MOS transistor. A device according to claim 1 or claim 2 in which the accumulating means (D) comprises a photodiode. A device according to claim 1 or claim 2 in which the accumulating means comprises an accumulating region formed on a common substrate with the amplifying transistor, and a photoelectric converting region (1) is formed over the amplifying transistor and is electrically connected to the accumulating region. A device according to any one of claims 1 to 3 in which the amplifying transistor (Tr C ') is an MOS transistor and the control region is its insulated gate. A device according to any one of claims 1 to 4 in which the amplifying transistor (Tr C ) is a bipolar transistor and the control region is its base. A device according to any one of the preceding claims which comprises resetting means (Tr A , Figs. 1-5, 10-15; Tr A , Tr B , Fig. 6, Tr A ', Fig. 7, Cox, Figs. 1-6, 8, 10-15) for resetting the control region of the amplifying transistor before the charges in the accumulating means are coupled to the control region. A device according to claim 7 when dependent on claim 6 in which the resetting means comprises a capacitor (Cox) formed by an electrode (L1) capacitively coupled to the base region through an insulating layer, the electrode being coupled to a potential source for applying a voltage pulse to forward bias the base-emitter junction of the bipolar transistor. A device according to claim 7 or claim 8 in which the resetting means comprises an MOS transistor for connecting the control region to a potential source. A device according to any one of claims 7 to 9 in which the resetting means is connected between the said control regions of the amplifying transistors of pixels which are adjacent in a sub-scanning direction. A device according to any one of claims 7 to 9 in which the resetting means is connected between the said control regions of the amplifying transistors of pixels which are adjacent in a main scanning direction. A device according to any one of claims 7 to 9 in which the resetting means of pixels which are adjacent in a main scanning direction are connected together and the resetting means of pixels which are adjacent in a sub-scanning direction are connected together so that the resetting means reset the control regions of the amplifying transistors of the respective pixels simultaneously. A device according to any one of claims 7 to 9 which comprises control means connected to control simultaneously the resetting means for a plurality of pixels distributed in a main scanning direction. A device according to any one of the preceding claims which comprises memory means for storing the first and second signals. A device according to claim 14 in which the memory means comprises a first capacitor (C1) for storing the first signal and a second capacitor (C2) for storing the second signal. A device according to claim 15 in which the amplifying transistors of a plurality of pixels spaced from each other in a sub-scanning direction are connected to a common first capacitor (C1) for storing the first signal and a common second capacitor (C2) for storing the second signal. A device according to claim 15 or claim 16 in which the first and second capacitors (C1 and C2) are connected to be reset to said predetermined potential (V VC ) by the means (T VC ) for resetting the output line. A device according to any one of the preceding claims, comprising control means for operating the means (T VC ) for resetting the output line at a first time (T4, T12, T22) immediately before the first signal is read from the amplifying transistor, and at a second time (T6, between T14 and T15, between T23 and T24) after the first signal is read and before the second signal is read from the amplifying transistor. A device according to any one of the preceding claims which comprises control means for reading out the first signals and the second signals of the pixels and for controlling the switching transistors to couple the photo-induced charges from the accumulating means to the control regions. A device according to claim 19 in which the control means is connected to control simultaneously a plurality of said switching transistors distributed in a main scanning direction. A device according to claim 19 or claim 20 in which the control means is connected to control simultaneously a plurality of said amplifying transistors distributed in a main scanning direction. A device according to any one of the preceding claims which comprises subtraction processing means for subtracting the respective first signals from the respective second signals. A device according to claim 22 in which the subtraction processing means comprises a differential amplifier.

Inventors: HASHIMOTO SEIJI, HASHIMOTO. SEIJI, Hashimoto. Seiji, c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, H04N3, H04N5