Liquid crystal display apparatus having controlled power-off

Abstract: A display apparatus includes a display panel having a matrix electrode arrangement of intersecting scanning lines and data lines, a driving voltage generating means for supplying voltages to be applied to scanning lines to a scanning line driving means for driving scanning lines, as well as voltages to be applied to data lines to a data line driving means for driving data lines, at least one voltage level being supplied to the scanning and to the data line driving means, a switching means for turning on or off an electrical connection between the driving voltage generating means to a power source for supplying or disconnecting power to the driving voltage generating means, and a control means for controlling the scanning line driving means and the data line driving means such that a scanning signal voltage is applied to a scanning line to scan the same while a data signal voltage corresponding to image data is applied to a data line when the switching means is on, such that the one voltage level is supplied to the scanning line driving means and to the data line driving means after the switching means is turned off.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to liquid crystal display devices, and more particularly, to display devices having a memory effect, such as ferroelectric liquid crystal panels. Description of the Related Art: In previous ferroelectric liquid crystal panels described in, for example, U. S. Patents US-A- 4,655,561, US-A- 4,836,656 and US-A- 4,844,590, a desired screen is written by selectively applying to each pixel on a selected scanning line at two different phases a voltage having one polarity and a voltage having the other polarity which are high enough to switch a pixel. Thus, writing is conducted on the ferroelectric liquid crystal panel in accordance with the polarity of a DC pulse which is applied to the liquid crystal. It is therefore necessary for a voltage having one polarity and a voltage having the other polarity to be applied by both a scanning driving circuit for driving scanning lines and a data line driving circuit for driving data lines using a predetermined voltage as a reference. In an example of the driving method shown in Fig. 6, V₁ (36 volts), V₂ (0 volts) and V C (18 volts) are supplied to the scanning line driving circuit while V₃ (24 volts), V₄ (12 volts) and V C (18 volts) are supplied to the data line driving circuit. The voltages supplied to the driving circuits, such as voltages V₁ to V₄ and V C , are generally generated on the basis of power supplied from an external power source of 100 volts (as used in Japan), 110 volts (as used in the United States), or a battery power source. The present inventors conducted experiments and found that DC voltages are applied irregularly to the liquid crystal due to a difference in the time constant between the scanning line driving circuit and the data line driving circuit. This difference in the time constant results in an image disturbance of a few (i.e., one to two) seconds immediately after the voltage supply to the scanning line driving circuit and the data line driving circuit is interrupted (i.e., power is turned off) during a writing period during which refresh (i.e., repetitive) scanning is performed on the display panel. In particular, the present inventors discovered that a DC voltage is supplied to the liquid crystal on a writing scanning line immediately before the power is turned off which is sufficiently large to disturb the uniform orientation of the liquid crystal along that scanning line. Furthermore, it is commonly understood that a scanning signal having a one polarity pulse for erasing the written state of a pixel and a pulse of another polarity are used advantageously in ferroelectric liquid crystal panel driving methods because it provides a sufficient driving margin, assures a fast screen rewriting speed and can be implemented by a simple control system. However, such a driving margin changes with time, as described below. SUMMARY OF THE INVENTION An object of the present invention is to provide a display panel which eliminates image disturbance from a display panel, even when power is turned off during a writing period in which refreshing scanning or the like is performed on the display panel, and which enables uniform orientation of a ferroelectric liquid crystal to be maintained sufficiently. The present invention provides a display device as defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a display device according to the present invention; Fig. 2 is a block diagram of a driving circuit employed in the present invention; Fig. 3 is a circuit diagram of an output stage of a V C power line employed in the present invention; Fig. 4 is a circuit diagram of a voltage detecting circuit employed in the present invention; Fig. 5 (A) is a timing chart showing a time series state of the display device according to the present invention; Fig. 5 (B) is a flowchart showing the operation of a display device according to the present invention; Fig. 5 (C) is a timing chart showing another time series state of the display device according to the present invention; Figs. 6 and 7 (A) to (C) show driving waveforms employed in the present invention; and Figs. 8 (A) to (B) schematically show driving margins. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings. Fig 1 is a block diagram of an embodiment of a display device according to the present invention. The display device includes a display panel 101 which employs a conventional matrix electrode arrangement (not shown) formed by scanning lines and data lines and a ferroelectric liquid crystal, a scanning line driving circuit 102 for driving the scanning lines, a data line driving circuit 103 for driving the data lines, a driving voltage generating circuit 104 for supplying voltages V₁, V₂ and V C to scanning line driving circuit 102 and voltages V₃, V₄ and V C to data line driving 103, a control circuit 105 for controlling scanning line driving circuit 102, data line driving circuit 103 and the driving voltage generating circuit 104, a voltage detecting circuit 106 for detecting the electrical interruption of switch 110 (i.e., the interruption of supply of power from power source 111), a logic control circuit 107, a logic control voltage source 108, and a data generating unit 109 to output image information for display. The logic control circuit 107 outputs a switch control signal to activate a switching element 34 provided in the driving voltage generating circuit 104 (described below) and thereby output, either the voltage V C or a grounded potential, a scanning side V C control signal to control a switching array 21 in the scanning line driving circuit 102 which is connected to a voltage V C line from the driving voltage generating circuit 104 such that the switching array 21 outputs, as the voltage applied to the scanning lines, only the voltage V C from the scanning line driving circuit 102 after the switch 110 is turned off, a scanning line driving control signal to control the switching array 21 (such that it outputs to a selected scanning line a scanning selection signal consisting of consecutive voltages V₁ and V₂, and to a non-selected scanning line the voltage V C shown in Fig. 6), a data side V C control signal to control a switching array 22 in the data line driving circuit 103 which is connected to the voltage V C line from the driving voltage generating circuit 104 such that the switching array 22 outputs only the voltage V C to the data lines after the switch 110 is turned off, a data line driving control signal to control the switching array 22 such that it selectively outputs to the data lines an image signal corresponding to the image data from the data generating circuit 109 being either a white data signal or a black data signal shown in Fig. 6, both signals consisting of a sequence of voltages V₃, V₄ and V C based on the image signal, and an image signal. Fig. 2 includes a block diagram of the scanning line driving circuit 102 and the data line driving circuit 103. The scanning line driving circuit 102 includes an address decoder 23 for decoding the scanning line address data in the scanning line driving control signal and a scanning waveform control logic circuit 24 for activating the switching array 21 such that it outputs the scanning selection signal shown in Fig. 6 to respective scanning lines 1011 in sequence. The data line driving circuit 103 includes a shift register/latch circuit 25 for converting a serial image signal into a parallel image signal, and a data line waveform control logic circuit 26 for generating a data signal voltage shown in Fig. 6 in accordance with the image data and for activating the switching array 22 such that it outputs the image signal voltage to a data line 1012. Fig. 3 includes a circuit diagram of the driving voltage generating circuit 104 showing the output stage for the voltage V C . The driving voltage generating circuit 104 includes a terminal 31 which assumes a voltage V C level, a voltage regulator 32, a current booster 33, and a switching device 34 for connecting either the voltage V C or a grounded potential to the scanning line driving circuit 102 and to the data line driving circuit 103 in accordance with the switch control signal from the logic control unit 107. Fig. 4 shows a circuit diagram of the voltage detecting circuit 106. A terminal 41 of the voltage detecting circuit 106 is connected to the logic control voltage source 108. The voltage detecting circuit 106 includes a 4.5 volts Zener 42 and a comparator 43. The voltage detecting circuit 106 outputs its logical low or high detection signal to the logic control circuit 107. Fig. 5 (A) is a timing chart showing on a time series basis (t : time) an output level of the logic control voltage source 108, the detection signal, an output level of the scanning line side output stage and an output level of the data line side output stage of the driving voltage generating circuit 104, an output level of the switch control signal, an output level of the output stage of the scanning line driving circuit 102 (e.g., a level of the output to the scanning lines S₁ and S₂), an output level of the output stage of the data line driving circuit 103 (e.g., an level of the output to the data line I₁), and a voltage level at a pixel (I₁ - S₁) at an intersection of the scanning line S₁ and the data line I₁. The signals shown in Fig. 5 (A) are obtained by using a waveform shown in Fig. 7 (A). As shown in Fig. 5 (A), (2) the logic control circuit 107 outputs a scanning side V C control signal and a data side V C control signal to the driving circuits 102 and 103, respectively, such that the output stages thereof output a voltage V C several µsec (1) after the logic control circuit receives a detection signal from the voltage detecting circuit 106. Thereafter, (3) the logic control circuit 107 outputs, for a period of several tens to several hundreds of microseconds, a control signal to activate the switching array 21 of the scanning line driving circuit 102 such that the switching array 21 outputs the voltage level V C to all the scanning lines, and a control signal to activate the switching array 22 of the data line driving circuit 103 such that the switching array 22 outputs the voltage level V₄ to all the data lines, to thereby erase the screen of the display panel 101 in white or black. Thereafter, (4) the logic control circuit 107 outputs a control signal to control the driving circuits 102 and 103 such that the driving circuits 102 and 103 output only the voltage V C over the several µsec. Thereafter, (5) the logic control circuit 107 outputs a switch control signal to the driving voltage generating circuit 104 to activate the switching element 34 and thereby connect the voltage V C output terminal in the driving voltage generating circuit 104 to a grounded potential. In step (3) of the flowchart of Fig. 5 (B), all the display contents which are written by the refresh scanning of the display panel 101 after power is turned off are erased in order to eliminate storage of the contents displayed on the display panel 101 after the power off. Fig. 5 (C) is a timing chart of another embodiment of the present invention. In the erasing period T E , an erasing voltage (V R ) is applied to all the scanning lines which effects erasure regardless of the voltage applied to the data lines. The erasing voltage V R may be applied to the scanning lines concurrently, as shown in Fig. 5 (C), or sequentially for each scanning line. Fig. 8 (A) shows an example of voltage ranges in which "white" (light state) and "black" (dark state) can be written on the display panel in accordance with the image data when driving waveforms shown in Fig. 7 and the timing chart shown in Fig. 5 (C) are used. The pixel voltage range in which "black" can be written and the pixel voltage range in which "white" can be written have both a lower limit. As a measure for both limits, a positive voltage VOP for writing "black" (VOP = V₄ - V₂) and a positive voltage VOP for writing "white" (VOP = V₅ - V₂) are defined. The driving margin is defined as the difference (effectively V₄ - V₅) between both voltages VOP defined above. Fig. 8 (A) shows the driving margin when the driving waveforms shown in Fig. 7 (A) are used and when one horizontal scanning period is 240 µsec (in Figs 7 (A), | V₄ | = | V₅ |). Fig. 8 (B) shows a change in driving margin with time. That is, Fig. 8 (B) shows the driving margin when the drive starts after the display panel is left unused for ten hours. As can be seen in Fig. 8 (B), the voltage range in which "black" can be written after the panel remains in black for ten hours decreases as does the voltage range in which "white" can be written after the panel remains in white for ten hours. The overlapping driving margin thereby decreases. It is possible according to the present invention to eliminate a decrease in the driving margin with time. Figs. 7 (A) to (C) show examples of waveforms which are employed in the present invention. In Figs. 7 (A) to (C), S n , S n+1 , S n+2 ... respectively denote the nth scanning (n: an integer) line, the n+1th scanning line, the n+2th scanning line. I m denotes the mth data line. The voltage waveform applied in the scanning selection period is a scanning selection signal. A desired scanning line is selected by applying the scanning selection signal. "Erasing signal" in the scanning selection signal has a voltage sufficient to erase the written state of a pixel in spite of the data signal. "Writing signal" is a combination of data signal and voltages V₄ and V₅ and determines the written state. A grounded voltage Vc is applied to the non-selected scanning electrodes to which a scanning selection signal is not applied. "Black" and "white" respectively denote the waveform of a black data signal and the waveform of a white data signal. In addition to the driving waveforms shown in Figs. 7 (A) to (C), those disclosed in U. S. Patents Nos. 4,655,561 and 4,836,656 can also be used in the present invention. Table 1 shows driving margins obtained when the display panel is driven using the driving waveforms shown in Figs. 7(A) to (C). According to the present invention, it is possible to ensure a sufficient driving margin when the display panel is driven after it is left unused for a long time. Furthermore, it is possible to restrict the generation of image disturbances which occur when the power is turned off. In particular, it is possible to eliminate or sufficiently decrease the application of a high DC voltage to the pixels on the writing scanning line immediately after power is turned off. This keeps the liquid crystal in a uniform orientation. Ferroelectric liquid crystal display panels disclosed, for example, in U. S. Patents Nos. 4,639,089, 4,709,994, 4,472,873 and 4,712,874 and the active matrix liquid crystal display panel which employs thin film transistors as switching elements for pixels, disclosed in, for example, U. S. Patent No. 4,697,887, can be employed as the display panel 101 of this invention, particularly, those which have the memory effect.

Claims: A display apparatus comprising: a liquid crystal display device (101 to 104) having a memory effect and comprising a plurality of picture elements, each picture element including a liquid crystal material disposed between a respective pair of electrodes; detecting means (105 to 110) for detecting a predetermined voltage level corresponding to the power supplied from a power source (111) applied to said display apparatus; erasing means (102-104) for applying an erasing signal (scanning line = V C and data line = V₄, or scanning line = V R and data line = V C ) to said liquid crystal display device (101 to 104) for erasing display contents of said picture element; and setting means (102-104) for setting all of the pairs of electrodes corresponding to the picture elements to substantially the same electric potential (V C ), wherein said setting means sets all the pairs of electrodes to the substantially same electric potential (V C ) before said erasing means applies said erasing signal (scanning line = V C and data line = V₄, or scanning line = V R and data line = V C ), in accordance with the detection of the power-off state by said detecting means (105 to 110). An apparatus according to Claim 1, wherein said liquid crystal display device comprises an active matrix liquid crystal device (101). An apparatus according to Claim 1, wherein said liquid crystal display device comprises a ferroelectric liquid crystal device. An apparatus according to Claim 1, wherein said detecting means (105 to 110) comprises a switch (110) for cutting off an electrical connection between the power source (111) and said apparatus, and a detecting circuit (106) for detecting a cutoff-state of said switch (110). An apparatus according to Claim 4, wherein said detecting circuit (106) generates a detecting signal when said voltage level declines below a predetermined voltage. An apparatus according to Claim 1, wherein said picture elements are arranged in a matrix of scanning lines (1011) and data lines (1012) perpendicular thereto, and wherein said erasing means causes the liquid crystal material for all the picture elements to assume a same orientation state by simultaneously applying a first voltage (V C or V R ) to all the scanning lines (1011) of said liquid crystal display device and a second voltage (V₄ or V C ) to all the data lines (1012) for a predetermined period. An apparatus according to Claim 1, wherein said picture elements are arranged in a matrix of scanning lines (1011) and data lines (1012) perpendicular thereto, and wherein said setting means supplies a reference voltage (V C ) as said same electric potential to all the scanning lines (1011) and all the data lines (1012) from a circuit (104) for generating a driving voltage. An apparatus according to Claim 7, wherein said circuit (104) for generating a driving voltage also generates a plurality of driving signals (V₁ to V₄) for performing a display operation. An apparatus according to Claim 1, wherein said picture elements are arranged in a matrix of scanning lines (1011) and data lines (1012) perpendicular thereto, said apparatus further comprising: scanning line and data line drivers (102 and 103) connected with a driving voltage generator (104) for generating a reference voltage (V C ), as said same electric potential wherein said setting means supplies a command to the scanning line and data line drivers (102 and 103) to supply said reference voltage (V C ) to all the scanning lines (1011) and all the data lines (1012). An apparatus according to Claim 1, wherein said liquid crystal display device further comprises a circuit (109) for forming data to be displayed when said apparatus is in a power-on state.

Inventors: INOUE HIROSHI, KANNO HIDEO, KATAKURA KAZUNORI, MIYAMOTO KATSUHIRO, MIZUTOME ATSUSHI, TSUBOYAMA AKIRA, INOUE, HIROSHI, KANNO, HIDEO, KATAKURA, KAZUNORI, MIYAMOTO, KATSUHIRO, MIZUTOME, ATSUSHI, TSUBOYAMA, AKIRA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: G09G3
IPC codes: G09G3