Rapid-response differential amplifier with rail-to-rail input capability

Abstract: A differential amplifier contains first and second differential portions (20 and 22) that operate together to achieve rail-to-rail input amplification capability. A main current supply (6) provides a main supply current (I L ) for the two differential portions. The circuit transconductance is controlled in a desired manner with a control amplifier (AN) suitably coupled to the differential portions and main current supply. A current-steering circuit typically formed with a pair of voltage clamps (30 and 32) enables a pair of level-shift current supplies (16 and 18) in the second differential portion to remain conductive as the input common-mode voltage traverses the entire supply voltage range. Consequently, the differential amplifier achieves a very fast response to changes in the input voltage difference irrespective of the value of the input common-­ mode voltage.

Description: FIELD OF USE This invention relates to differential amplifiers that can be made in semiconductor integrated circuit form and, more specifically, to an electronic circuit, coupled between sources of a first supply voltage and a second supply voltage whose difference is a power supply voltage that defines a supply voltage range, for amplifying an input signal differentially provided between first and second input terminals, the circuit comprising: first differential means for amplifying the input signal when its common-mode voltage V CM is in a part of the supply range extending to the second supply voltage, the first differential means comprising like-configured first and second input amplifiers of a first polarity type, the first and second amplifiers having respective control electrodes coupled respectively to the first and second input terminals, respective first flow electrodes coupled to a first supply point, and respective second flow electrodes coupled respectively to first and second output terminals; second differential means for amplifying the input signal when V CM is in a part of the supply range extending to the first supply voltage, the two parts of the supply range partially overlapping, the second differential means comprising (a) like configured third and fourth input amplifiers of a second polarity type opposite to the first polarity type, the third and fourth input amplifiers having respective control electrodes coupled respectively to the first and second input terminals, respective first flow electrodes coupled respectively to first and second nodes, and respective second flow electrodes coupled to the source of the first supply voltage, (b) a first current supply coupled between the first node and the source of the second supply voltage, (c) a second current supply coupled between the second node and the source of the second supply voltage, and (d) like-configured fifth and sixth amplifiers of the first polarity type, the fifth and sixth amplifiers having respective control electrodes coupled respectively to the first and second nodes, respective first flow electrodes coupled to a second supply point, and respective second flow electrodes coupled respectively to the first and second output terminals; a main current supply coupled between the first supply point and the source of the first supply voltage; and a control amplifier of the first polarity type, the control amplifier having a control electrode for receiving a control voltage a first flow electrode coupled to the first supply point, and a second flow electrode coupled to the second supply point. Such an electronic circuit is known from U.S. Patent 4,555,673 and is a differential amplifier formed with a pair of parallel differential portions that work as a unit to achieve rail-to-rail input capability. BACKGROUND ART A differential amplifier formed as part of an integrated circuit often utilizes a low power supply voltage in amplifying a differential input signal. This severely constrains the voltage range of the common-mode portion of the input signal. Consequently, it is desirable that the amplifier have rail-to-rail input capability. That is, the amplified output signal should be representative of the input signal as its common-mode voltage travels the full range of the power supply voltage. U.S. Patent 4,555,673 describes several embodiments of a differential amplifier that uses complementary pairs of input transistors to attain rail-to-rail input capability. Referring to the drawings, Fig.1 illustrates one of the bipolar embodiments disclosed in U.S. Patent 4,555,673. This device amplifies an input signal differentially supplied between input terminals T I1 and T I2 as input voltages V I1 and V I2 . The common-mode voltage V CM of the input signal is (V I1 + V I2 )/2. The device in Fig. 1 is connected between a source of a high supply voltage V HH (the high rail) and a source of a low supply voltage V LL (the low rail). The voltage difference V HH - V LL is the overall power supply voltage V PS for the amplifier. V PS is somewhat greater than 2V BE , where V BE is the absolute value of the standard voltage across the base-emitter junction of a bipolar transistor when it is just turned on. V BE is about 0.6 - 0.8 volt. The amplifier contains a main current source 6 connected between a supply point P1 and the V LL supply. Current source 6 provides a main supply current I L for a pair of differential amplifying portions 8 and 10. The circuit in Fig. 1 largely divides current I L into operating currents I P1 and I P2 . Differential portion 8 consists of NPN input transistors Q1 and Q2 that enable the amplifier to perform signal amplification up to the high rail. Voltages V I1 and V I2 are provided to the bases of transistors Q1 and Q2. Their emitters are connected together at point P1 to receive operating current I P1 . When the input common-mode voltage V CM is in a part of the V PS range extending from V HH down to a prescribed voltage greater than V LL , transistors Q1 and Q2 amplify the input signal by largely dividing current I P1 into intermediate currents I A and I B whose difference is representative of the input signal. Differential portion 10 contains a voltage level-shift circuit 12 that translates the input signal into a shifted differential signal whose common-mode voltage is at least 1V BE higher than V CM . Level-shift circuit 12 centers around PNP input transistors Q3 and Q4 that enable the amplifier to provide signal amplification down to the low rail. Voltages V I1 and V I2 are supplied to the bases of transistors Q3 and Q4. Their collectors are tied to the V LL supply. The emitters of transistors Q3 and Q4 are coupled through level-shift resistors RL1 and RL2 to nodes N1 and N2 at which the shifted differential signal is supplied. The Q3 and Q4 base-emitter junctions provide the 1V BE part of the level shift. Resistors RL1 and RL2 augment the level shift beyond 1V BE as necessary. Current sources 16 and 18 provide supply currents I H1 and I H2 for the level shifting. Current source 16 is connected between node N1 and the V HH supply. Current source 18 is similarly connected between node N2 and the V HH supply. The actual signal amplification in differential portion 10 is done with an amplifier circuit 14 consisting of NPN transistors Q5 and Q6. The shifted differential signal at nodes N1 and N2 is supplied to the bases of transistors Q5 and Q6. Their emitters are connected together at a supply point P2 to receive operating current I p2 . When voltage V CM is in a part of the V PS range extending from V LL up to a prescribed voltage less than V HH , transistors Q5 and Q6 amplify the differential input signal (in its level-shifted form) by largely dividing current I P2 into intermediate currents I C and I D whose difference is representative of the input signal. The Q1 and Q5 collectors are connected together to provide an output current I O1 at an output terminal T₀₁. Likewise, the Q2 and Q6 collectors are connected together to provide a complementary output current I₀₂ at another output terminal T₀₂. The final component of the amplifier is an NPN control transistor QN whose emitter and collector are respectively connected to points P1 and P2. In response to a control voltage V RN supplied to its base, transistor QN regulates the values of currents I P1 and I P2 as a function of V CM . Control voltage V RN lies in a range extending from V LL + V SM + V BE to V HH - V SM - V BE . V SM is a small safety-margin voltage typically about 0,2 - 0,3 volt. Fig. 2 illustrates an idealized graph useful in understanding the operation of the circuit in Fig. 1. By choosing voltage V RN in the foregoing way, the parts of the V PS range in which differential portions 8 and 10 provide signal amplification partially overlap. Portions 8 and 10 are both operationally conductive when V CM is in a narrow intermediate subrange generally centering on V RN . In Fig. 2, this subrange extends from V RN - V W to V RN + V W , where 2 VW is the approximate 100-millivolt width of the subrange. As V CM is raised from V LL to V HH , the differential amplifier first goes through a low subrange extending from V LL to V RN - V W in which differential portion 10 provides all of the signal amplification. Transistors Q3 - Q6 are turned on. Transistors Q1 and Q2 are turned off so as to make differential portion 8 non-conductive. The amplifier then goes through the intermediate subrange extending from V RN - V W to V RN + V W in which transistor QN progressively steers supply current I L away from portion 10 and to portion 8. Transistors Q5 and Q6 turn progressively off as transistors Q1 and Q2 turn progressively on. The differential amplifier finally goes through a high subrange extending from V RN + V W to V HH in which portion 8 provides all of the signal amplification. Transistors Q1 and Q2 are turned fully on. Transistors Q5 and Q6 are non-conductive so that portion 10 is thus turned off. If V CM gets sufficiently close to V HH , transistors Q3 and Q4 also turn off. The circuit transconductance -- i.e., the ratio of incremental change in the output current difference I₀₁ - I₀₂ to an incremental change in the input voltage difference V I1 - V I2 -- is proportional to the sum of currents I P1 and I P2 in the differential amplifier of Fig. 1. Due to the current steering provided by transistor QN, the sum of I P1 and I P2 is approximately equal to I L at any value of V CM in the V PS range. As a result, the transconductance is largely constant. In contrast to the situation in which large changes occur in the transconductance as V CM traverses the V PS range, the constant transconductance of the circuit in Fig. 1 enables an optimum frequency response to be achieved irrespective of the value of V CM when the differential amplifier is used in an operational amplifier with negative feedback. When V CM rises to a high enough point that transistors Q3 and Q4 turn off, level-shift current sources 16 and 18 go into saturation and/or turn off. Current sources 16 and 18 thereby take a relatively long time to return to their normal non-saturated fully conductive condition when V CM drops down low enough to turn transistors Q3 and Q4 back on. Consequently, the response of the amplifier circuit to changes in the value of input difference V I1 - V I2 is unduly slow. While the turnoff of transistors Q3 and Q4 is basically unavoidable, it would be highly desirable to prevent current sources 16 and 18 from going into saturation and/or turning off during circuit operation. It is therefore the object of the invention to provide a solution to overcome this problem. GENERAL DISCLOSURE OF THE INVENTION According to the invention an electronic circuit of the type set forth in the opening paragraph is characterised by current-steering means enabling the first and second current supplies to remain operationally conductive as V CM traverses substantially the entire supply range. The current-steering means enable the first and second level-shift current supplies to remain operationally conductive as V CM traverses the full supply range. When the voltage level-shift circuit turns off, the current-steering means open paths to the first voltage supply for current provided from the level-shift current supplies. This typically entails suitably clamping the voltages at the first and second nodes. The level-shift current supplies are inhibited from going into an undesirable condition, such as saturation or turn-off, when V CM gets close to the second supply voltage. As a result, the present electronic circuit provides a very fast response to changes in the input voltage difference as V CM varies across the full supply range. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawing, in which Fig. 1 shows a circuit diagram of a prior art differential amplifier, Fig. 2 shows a graph illustrating operational characteristics of the differential amplifiers in Figs. 1 and 4, Fig. 3 shows a circuit diagram of a general differential amplifier in accordance with the invention, and Fig. 4 shows a circuit diagram of a bipolar embodiment of the differential amplifier in Fig. 3. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 3, it illustrates a general arrangement for a differential amplifier having rail-to-rail input capability and controlled transconductance. The amplifier employs a current-steering mechanism in accordance with the teachings of the invention to achieve a rapid response irrespective of the value of input common-mode voltage V CM as it varies across the entire V PS range from V LL to V HH . The amplifying device in Fig. 3 uses various three-electrode amplifiers identified by reference symbols beginning with the letter "A". Each "A" amplifier has a control electrode (1E), a second flow electrode (2E), and a control electrode (CE) for controlling current flow between the flow electrodes (1E and 2E). Charge carriers. either electrons or holes, that move between the flow electrodes of each "A" amplifier originate at its first flow electrode and terminate at its second flow electrode. Current flow begins when the voltage between the control electrode and the first flow electrode passes a specified threshold level. The current (if any) flowing in the control electrode is much smaller than that otherwise moving between the flow electrodes. Each "A" amplifier preferably consists of a single transistor. In the case of a bipolar transistor, its emitter, collector, and base are respectively the first, second, and control electrodes. These elements are respectively the source, drain, and gate for a field-effect transistor (FET) of either the insulated-gate or junction type. In some cases, each "A" amplifier could consist of more than one transistor. One example is a bipolar Darlington circuit in which the emitter of an input transistor is connected to the base of a trailing transistor. In this case, the control electrode of the "A" amplifier is (connected to) the base of the input transistor, while the first and second control electrodes are (connected to) the emitter and collector of the trailing transistor. As used in describing two (or more) of the "A" amplifiers, "like-configured" means that the amplifiers have corresponding elements interconnected in the same way and that each set of corresponding elements is of the same semiconductor polarity. For example, two of the "A" amplifiers are like-configured if both are NPN transistors but not if one is an NPN transistor while the other is a PNP transistor. Likewise, Darlington circuits are like-configured as long as the input transistors are of the same polarity and the trailing transistors are of the same polarity (even if different from that of the input transistors). If electrons move between the flow electrodes of one "A" amplifier, while holes move between the flow electrodes of another "A" amplifier, the two amplifiers may be referred to as being "complementary" or "of opposite polarity". Thus, an "A" amplifier formed with a PNP transistor is of opposite polarity to an "A" amplifier formed with an NPN transistor. The differential amplifier in Fig. 3 centers around differential amplifying portions 20 and 22 that receive main supply current I L from main current source 6 connected between point P1 and the V LL supply. Differential portions 20 and 22 work together to amplify the input signal formed by the difference between input voltages V I1 and V I2 . Portion 20 is operationally conductive when V CM is in a part of the V PS range extending from V HH down to a prescribed voltage V AL that is somewhat greater than V LL . Portion 22 is operationally conductive when V CM is in a part of the V PS range extending from V LL up to another prescribed voltage V AH that is somewhat less than V HH . The circuit parameters are chosen in such a way that V AH is greater than V AL . That is, the two parts of the V PS range partially overlap. As a result, portions 20 and 22 are both conductive in the intermediate V AL - to - V AH subrange so that the differential amplifier attains rail-to-rail input capability. Differential portion 20 is formed with like-configured input amplifiers A1 and A2 of a first polarity type. The first electrodes of amplifiers A1 and A2 are tied together at supply point P1 to receive operating current I P1 . Input voltages V I1 and V I2 are supplied to control electrodes of amplifiers A1 and A2. Their second electrodes provide complementary intermediate currents I A and I B as the output signals of portion 20. When V CM is in the V AL -to-V HH range, amplifiers A1 and A2 largely divide current I P1 between currents I A and I B at values whose difference is representative of the differential input signal. Differential portion 22 contains a voltage level-shift circuit 24 for translating the differential input signal into a shifted differential signal whose common-mode voltage exceeds V CM by a specified amount. The main part of level-shift circuit 24 consists of like-configured input amplifiers A3 and A4 of a second polarity type opposite to the first polarity type. Voltages V I1 and V I2 are provided to the control electrodes of amplifiers A3 and A4. Their second electrodes are connected to the V LL supply. Because amplifiers A3 and A4 are complementary to amplifiers A1 and A2, portion 22 performs signal amplification at the opposite end of the V PS range from portion 20. The A3 and A4 first electrodes are coupled to nodes N1 and N2 at which the shifted differential signal is supplied. A voltage level shift occurs between the control and first electrodes of each of amplifiers A3 and A4. If this level shift is less than the total level shift needed, a level-shift element 26 is connected between node N1 and the A3 first electrode. A largely identical level-shift element 28 is similarly connected between node N2 and the A4 first electrode. Level-shift current sources 16 and 18 are again connected to the V HH supply to provide supply currents I H1 and I H2 at nodes N1 and N2. Currents I H1 and I H2 are substantially equal. When amplifiers A3 and A4 are turned on so that level-shift circuit 24 is conductive, currents I H1 and I H2 flow through level shifts 26 and 28 and then through amplifiers A3 and A4 to the V LL supply. A current-steering circuit provides alternate paths for currents I H1 and I H2 to flow to the V LL supply when V CM gets sufficiently close to V HH that amplifiers A3 and A4 turn off so as to make level-shift circuit 24 non-conductive. The action of the current-steering circuit prevents current sources 16 and 18 from going into an undesired condition, such as saturation or turn-off, when amplifiers A3 and A4 turn-off. Consequently, current sources 16 and 18 remain in their (non-saturated) fully conductive state during the full traverse of V CM across the V PS range. The current-steering action involves preventing the voltages at nodes N1 and N2 from rising to values that would otherwise cause current sources 16 and 18 to decay into an undesired condition when V CM gets close to V HH . More particularly, the current-steering circuit prevents the difference V C1 between the voltage at node N1 and a clamping reference voltage V RC from exceeding a specified value V CMAX . The steering circuit also prevents the difference V C2 between the voltage at node N2 and voltage V RC from exceeding V CMAX . Current source 16 would go into an undesirable condition (e.g., saturation) if the difference between the N1 voltage and V HH dropped down to or went below a minimum value V MINH . Current source 18 would likewise be in an undesirable condition if the difference between the N2 voltage and V HH were less than or equal to V MINH . As a result, V CMAX is slightly less than V HH - V MINH - V RC . V MINH is typically 0.1 - 0.3 volt. For the normal case in which the differential amplifier includes level shifts 26 and 28, the current-steering circuit is preferably implemented by utilizing clamps 30 and 32 as shown in Fig. 3. Clamp 30 is connected between the V LL supply and a node N3 lying in the path between level shift 26 and the A3 first electrode. Clamp 32 is similarly connected between the V LL supply and a node N4 lying in the path between level shift 28 and the A4 first electrode. In the foregoing situation, clamps 30 and 32 operate directly only on the voltages at nodes N3 and N4. That is, clamp 30 prevents the difference between V RC and the N3 voltage from exceeding a given value, while clamp 32 prevents the difference between V RC and the N4 voltage from exceeding that value. The clamping on nodes N1 and N2 is achieved by way of level shifts 26 and 28 whose level shift is added to the clamping voltage of clamps 30 and 32. Level shifts 26 and 28 thereby form part of the current-steering circuit here. The advantage of this arrangement is that clamps 30 and 32 also prevent elements 26 and 28 from turning off when V CM gets too close to V HH . Alternatively, clamps 30 and 32 could be connected directly to nodes N1 and N2 as indicated in dotted line in Fig.3. This alternative can be used regardless of whether level shifts 26 and 28 are absent or not. Of course, if elements 26 and 28 are present, the above-mentioned advantage is lost. Clamps 30 and 32 are typically implemented in the manner shown in Fig. 3. The principal elements are like-configured clamping amplifiers AC1 and AC2 of the second polarity type. The first electrodes of amplifiers AC1 and AC2 are coupled to nodes N3 and N4. Reference voltage V RC is supplied to the control electrodes of amplifiers AC1 and AC2. Their second electrodes are tied to the V LL supply. Clamp 30 may include a resistor RC1 connected between node N3 and the AC1 first electrode. If so, clamp 32 includes a matching resistor RC2 connected between node N4 and the AC2 second electrode. As the preceding discussion indicates, amplifiers AC1 and AC2 are of the same polarity as amplifiers A3 and A4. Because amplifiers AC1 and A3 are coupled together through node N3, amplifier AC1 turns on as amplifier A3 turns off and visa versa. Likewise, amplifier AC2 turns on as amplifier A4 turns off and vice versa due to the coupling through node N4. An amplifier circuit 34 formed with like-configured amplifiers A5 and A6 performs the actual signal amplification in differential portion 22. The shifted differential signal at nodes N1 and N2 is supplied to the control electrodes of amplifiers A5 and A6. Their first electrodes are connected together at supply point P2 to receive operating current I P2 . The A5 and A6 second electrodes supply complementary intermediate currents I C and I D as the output signals of portion 22. When V CM is in the V LL -to-V AH range, amplifiers A5 and A6 largely divide current I P2 between currents I C and I D at values whose difference is representative of the voltage difference between nodes N1 and N2 and is therefore representative of the differential input signal. The A1 and A5 second electrodes are both connected to output terminal T₀₁ so as to provide it with output current I₀₁ at the value equal to I A + I C . The A2 and A6 second electrodes are likewise both connected to output terminal T O2 in order to provide it with complementary output current I₀₂ at a value equal to I B + I D . A low-resistance load 36, tied to the V HH supply, preferably converts currents I₀₁ and I₀₂ into complementary output voltages V₀₁ and V₀₂. Alternatively, a summing circuit 38 could subtract one of currents I₀₁ and I₀₂ from the other to produce a composite output current I O representative of the difference between I₀₁ and I₀₂. A control amplifier AN of the first polarity type controls the values at which currents I P1 and I P2 are supplied to differential portions 20 and 22. Control amplifier AN has its first and second electrodes respectively connected to points P1 and P2. Control voltage V RN is provided to the AN control electrode at a value sufficient to enable both of portions 20 and 22 to be operationally conductive in the intermediate V AL -to-V AH subrange. V RN is typically near the middle of the V AL -to-V AH subrange. The current control provided by amplifier AN allows the circuit transconductance to be regulated in a desired manner. The present differential amplifier operates in a manner similar to that of the prior art circuit described above, except that current sources 16 and 18 do not go into an undesirable condition when V CM gets close to V HH . More specifically, the operation proceeds as follows when V CM is raised from low rail V LL to high rail V HH . As V CM rises from V LL to V AL , amplifier AN is fully conductive and steers all of current I L to differential portion 22. I P2 equals I L . Amplifiers A3 - A6 are fully turned on. Portion 22 is in a state of full operational conductivity. I P1 is zero. Amplifiers A1 and A2 are turned off so that differential portion 20 is non-conductive. The steering circuit formed with clamps 30 and 32 is inactive. In the particular embodiment shown in Fig. 3, amplifiers AC1 and AC2 are turned off. When V CM goes from V AL (past V RN ) up to V AH , amplifier AN turns progressively off so as to progressively divert more of the main supply current away from portion 22 and toward portion 20. I P1 increases progressively to I L . Amplifiers A1 and A2 turn progressively on as portion 20 goes from its non-conductive state to a state of full operational conductivity. Conversely, I P2 drops progressively to zero. Amplifiers A5 and A6 turn progressively off, causing portion 22 to go from its fully conductive state to a non-conductive state. As V CM rises from V AH to V HH , amplifier AN is turned fully off. All of the main supply current is now steered to portion 20. I P1 equals I L . Amplifiers A1 and A2 are turned fully on. Portion 20 is in its fully conductive state. I P2 equals zero. Amplifiers A5 and A6 are both turned off so that portion 22 is non-conductive. When V CM gets sufficiently close to V HH , amplifiers A3 and A4 turn off. As this happens, the current-steering circuit of the invention becomes active to ensure that current sources 16 and 18 remain in their fully conductive (non-saturated) state. Currents I H1 and I H2 are steered through the steering circuit to the V LK supply. For the embodiment of clamps 30 and 32 depicted in Fig. 3, amplifiers AC1 and AC2 turn on as amplifiers A3 and A4 turn off. This occurs when V CM is in the vicinity of, and typically slightly higher than, V RC . Alternate paths are thereby opened through resistors RC1 and RC2 (if present) and through amplifiers AC1 and AC2 for supply currents I H1 and I H2 to flow to the V LL supply. Let I H represent the steady-state value of each of currents I H1 and I H2 , while R C represents the value of each of resistors RC1 and RC2. The voltages across resistors RC1 and RC2 are then equal to I H R C when amplifiers AC1 and AC2 are fully conductive. Let V LSE be the extra level-shift voltage supplied by level-shift elements 26 and 28. The voltages from the control electrodes of amplifiers AC1 and AC2 to their respective first electrodes reach approximately the same value, referred to here as V LSC . As a result, the N1 and N2 voltages are clamped at a value equal to V RC + V CMAX , where V CMAX equals V LSE + I H R C + V LSC If clamps 30 and 32 were to clamp the N1 and N2 voltages at the preceding value before amplifier AN reduced current I P2 to zero, the amplification provided by amplifiers A5 and A6 in circuit 34 would be cut off prematurely, resulting in loss of transconductance. This problem is avoided by choosing the value of voltage V RC and the characteristics of amplifiers AC1, AC2, A3, and A4 and resistors RC1 and RC2 in such a way that amplifiers AC1 and AC2 do not start to turn on until I P2 has indeed dropped substantially to zero. In particular, V RC is normally chosen to be greater than or equal to V RN . The value of V CM at which amplifiers AC1 and AC2 start to become conductive must be greater than V AH . The way in which amplifier AN is differentially connected to amplifiers A1 and A2 is similar to the way in which amplifiers AC1 and AC2 are differentially connected to amplifiers A3 and A4, except for the presence of resistors RC1 and RC2. If amplifier AN switches from a fully conductive condition to a non-conductive condition in a voltage space approximately equal to V AH - V AL , and if V RC is as low as V RN , the parameter I H R C should be approximately equal to V AH - V AL . This ensures that amplifiers AC1 and AC2 switch from a non-conductive state to a fully conductive state at a V CM value sufficiently higher than V AH as to avoid prematurely cutting off amplifiers A5 and A6. However, I HRC could be lower if V RC is greater than V RN . For example, I H R C could be zero if V RC - V RN equals V AH - V AL . When nodes N1 and N2 are clamped, the voltage across each of current sources 16 and 18 equals V HH - V LSE - I H R C - V LSC -V RC . Consequently, V RC is less than V HH - V MINH - V LSE - I H R C - V LSC . Looking now at the level-shifts requirements, let V LSI represent the level shift that amplifiers A3 and A4 provide from their control electrodes to their respective first electrodes. The total level shift V LSTOT provided by level-shift circuit 24 at nodes N1 and N2 then equals V LSI + V LSE . Amplifiers A5 and A6 are turned on when V CM is at V LL . Since amplifier AN is also turned on, V LSTOT must be greater than or equal to V MINL + V MINN + V LSO , where V MINL is the minimum tolerable voltage across current source 6 (i.e. between point P1 and the V LL point), V MINN is the minimum tolerable voltage across amplifier AN (i.e. between points P1 and P2, and V LSO is the voltage that amplifiers A5 and A6 provide from their control electrodes to their respective first electrodes. V MINL and V MINN each are typically 0.1 - 0.3 volt. If V LSO is approximately equal to V LSI , it turns out that level shift V LSE provided by elements 26 and 28 need only be greater than V MINL + V MINN . Turning to voltage V RN , it must exceed V LL + V MINL + V LSN , where V LSN is the voltage between the control and first electrodes of amplifier AN when it is fully conductive. V RN is also less than V HH - V MINH - V LSE - V LSI . The transmission delay through portion 22 is somewhat longer than that through portion 20. Accordingly, it is desirable that portion 20 provide as much of the signal amplification across the V PS range as possible.For this reason, V RN is normally set at a value near the lower limit. Fig. 4 depicts a preferred bipolar embodiment of the preceding device in which amplifiers A1 - A6 and AN consist of transistors Q1 - Q6 and QN configured as shown in Fig.1 and operable in the manner described above. Since V LSN and V LSI both equal 1V BE , V RN lies in the range from V LL + V MINL + V BE to V HH - V MINH - V BE - V LSE . This corresponds generally to the range given above for the prior art circuit of Fig. 1. Consequently, the transconductance of the differential amplifier in Fig.4 is substantially constant. In Fig. 4 current source 6 is formed in a conventional way with a resistor RL and an NPN transistor QL responsive to a reference voltage V RL . Current source 16 consists of a PNP transistor QH1 and a resistor RH1 arranged in a conventional manner. Current source 18 likewise consists of a PNP transistor QH2 and a resistor RH2 arranged in the same way. Transistors QH1 and QH2 both respond to the same reference voltage V RH . Level shift 26 consists of PN diodes D1X and D1Y connected in series. Level shift 28 similarly consists of PN diodes D2X and D2Y connected in series. As a result, V LSE equals 2V BE . Each of diodes D1X, D1Y, D2X and D2Y is preferably formed as and NPN transistor having its collector connected back to its base in order to minimize transmission delay caused by base resistance and base charge storage effects. In Fig.4, the current-steering circuit of the invention utilizes clamps 30 and 32 connected directly to nodes N3 and N4. In addition too preventing diodes D1X, D1Y, D2X, and D2Y from turning off when transistors Q3 and Q4 turn off, this arrangement avoid undesired temperature dependencies within the circuit. Amplifiers AC1 and AC2 in clamps 30 and 32 of Fig.3 are implemented with PNP transistors QC1 and QC2 in Fig.4. V RC equals V RN here. Clamps 30 and 32 also include resistors RC1 and RC2 in this bipolar embodiments. By inspection, V CMAX equals 3V BE + I H R C . The voltage drop I H R C across each of resistors RC1 and RC2 when nodes N1 and N2 are clamped is at least 120 millivolts and is typically 200 millivolts. This is sufficient to avoid the previously mentioned amplification notches that would otherwise result from premature turn-off of transistors Q5 and Q6. The embodiment in Fig. 4 employs load 36 to produce complementary output voltages V₀₁ and V₀₂. Load 36 consists of resistors R1 - R3 and a capacitor C1 arranged as shown. Capacitor C1 prevents spurious common-mode signals from appearing on the V HH supply line. Alternatively, elements C1 and R3 could be deleted. In the preferred embodiment, V HH and V LL are 5.0 and 0.0 volts, respectively. V RN /V RC , V RL , and V RH are 1.25, 0,9, and 4.1 volts, respectively. I L and I H1 /I H2 are 380 and 200 microamperes, respectively, RH1/RH2, RC1/RC2, R1/R2, and R3 are 500, 1.250, 750, and 100 ohms, respectively. C1 is 15 picofarads. The differential amplifier is fabricated as part of a monolithic integrated circuit using oxide isolation to separate active regions in a semiconductive wafer. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, semiconductor elements of opposite polarity to those described above might be used to accomplish the same results. FETs could replace some or all of the bipolar transistors. An input level-shift circuit of the type described in EP patent application EP-A-0 382 302 claiming US-priority of 10th February 1989, and which thus represents state of the art according to Art. 54(3), EPC could be inserted in front of differential portions 20 and 22 to enable the differential amplifier to operate at a power supply voltage of 1 volt or slightly less.

Claims: An electronic circuit, coupled between sources of a first supply voltage (V LL ) and a second supply voltage (V HH ) whose difference is a power supply voltage that defines a supply voltage range, for amplifying an input signal (V I1 , V I2 ) differentially provided between first and second input terminals, (T i1 , T i2 ) the circuit comprising: first differential means (20) for amplifying the input signal when its common-mode voltage V CM is in a part of the supply range extending to the second supply voltage, the first differential means comprising like-configured first and second input amplifiers (Q₁, A₁; Q₂, A₂) of a first polarity type, the first and second amplifiers having respective control electrodes coupled respectively to the first and second input terminals, respective first flow electrodes coupled to a first supply point (P₁), and respective second flow electrodes coupled respectively to first and second output terminals (T₀₁, T₀₂); second differential means (34) for amplifying the input signal when V CM is in a part of the supply range extending to the first supply voltage, the two parts of the supply range partially overlapping, the second differential means comprising (a) like configured third and fourth input amplifiers (Q₃, A₃; Q₄, A₄) of a second polarity type opposite to the first polarity type, the third and fourth input amplifiers having respective control electrodes coupled respectively to the first and second input terminals, respective first flow electrodes coupled respectively to first and second nodes (N₁, N₂), and respective second flow electrodes coupled to the source of the first supply voltage (V LL ), (b) a first current supply (16) coupled between the first node (N₁) and the source of the second supply voltage (V HH ), (c) a second current supply (18) coupled between the second node (N₂) and the source of the second supply voltage (V HH ), and (d) like-configured fifth and sixth amplifiers (Q₅, A₅; Q₆, A₆) of the first polarity type, the fifth and sixth amplifiers having respective control electrodes coupled respectively to the first and second nodes, respective first flow electrodes coupled to a second supply point (P₂), and respective second flow electrodes coupled respectively to the first and second output terminals (T₀₁, T₀₂); a main current supply (6) coupled between the first supply point (P₁) and the source of the first supply voltage V LL ; and a control amplifier (AN) of the first polarity type, the control amplifier having a control electrode for receiving a control voltage (V RN ), a first flow electrode coupled to the first supply point (P₁), and a second flow electrode coupled to the second supply point (P₂), characterized by current-steering means (30, 32) enabling the first and second current supplies (16, 18) to remain operationally conductive as V CM traverses substantially the entire supply range. A circuit as in Claim 1 characterized in that the current-steering means establishes paths by which current from the first and second current supplies flows to the source of the first supply voltage as the third and fourth amplifiers turn off. A circuit as in Claim 2 characterized in that the current-steering means prevents (a) the difference between the voltage at the first node and a clamping reference voltage from exceeding a specified clamping value and (b the difference between the voltage at the second node and the reference voltage from exceeding the specified clamping value. A circuit as in Claim 3 characterized in that the current-steering means comprises (a) a first voltage clamp coupled between the first node and the source of the first supply voltage and (b) a second voltage clamp coupled between the second node and the source of the first supply voltage. A circuit as in Claim 4 characterized in that the first and second voltage clamps respectively comprise first and second clamping amplifiers of the second polarity type, the first and second clamping amplifiers having respective control electrodes for receiving the reference voltage, respective first flow electrodes coupled respectively to the first and second nodes, and respective second electrodes coupled to the source of the first supply voltage. A circuit as in Claim 4 in which charge carriers that move between the flow electrodes of each amplifier originate at its first electrode and terminate at its second electrode under control of its control electrode. A circuit as in Claim 3 in which the second differential means includes (a) a first voltage level-shift element coupled in the path between the first node and the first electrode of the third amplifier and (b) a second voltage level-shift element coupled in the path between the second node and the first electrode of the fourth amplifier. A circuit as in Claim 7 characterized in that the current-steering means comprises (a) a first voltage clamp coupled between the source of the first supply voltage and a third node located in the path between the first level-shift element and the first electrode of the third amplifier and (b) a second voltage clamp coupled between the source of the first supply voltage and a fourth node located in the path between the second level-shift element and the first electrode of the fourth amplifier. A circuit as in Claim 4 characterized in that the first and second voltage clamps respectively comprise first and second clamping amplifiers of the second polarity type, the first and second clamping amplifiers having respective control electrodes for receiving the reference voltage, respective first flow electrodes coupled respectively to the third and fourth nodes, and respective second electrodes coupled to the source of the first supply voltage. A circuit as in Claim 9 characterized in that each amplifier comprises a bipolar transistor having a base, an emitter, and a collector respectively coupled to the control, first, and second electrodes of that amplifier. A circuit as in Claim 10 characterized in that (a) the first clamp further includes a first clamping resistor coupled between the third node and the emitter of the transistor in the first clamping amplifier and (b) the second clamp further includes a second clamping resistor coupled between the fourth node and the emitter of the transistor in the second clamping amplifier. A circuit as in Claim 11 characterized in that each level-shift element comprises at least one diode. A circuit as in Claim 11 characterized in that the transistors in the first and second clamping amplifiers and in the third and fourth input amplifiers are PNP transistors, the remaining transistors all being NPN transistors. A circuit as in Claim 11 characterized in that the reference voltage is substantially equal to the control voltage.

Inventors: TERO JOHN PHILIP, TERO, JOHN PHILIP
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: H03F3
IPC codes: H03F3