Charge transfer device and solid state image pickup device using charge transfer device

Abstract: There is provided a charge transfer device comprising a shift register (S) comprised of a plurality of shift stages directly connected to each other, phase pulses for a multi-phase control pulse () being delivered to the shift stages, respectively, a transfer control pulse being delivered to the shift register stage arranged at one end of the plurality of shift stages; and a transfer unit having a plurality of transfer electrodes (E) provided in correspondence with the shift stages of the shift register, transfer pulses being delivered from the shift stages of the shift register to the transfer electrodes, respectively, to apply transfer pulses in a predetermined order from the shift stages of the shift register to the transfer electrodes of the transfer unit, respectively, to thereby sequentially transfer signal charges stored below the transfer electrodes in a predetermined direction. In this device, the transfer electrodes are such that transfer electrodes having a large electrode area and transfer electrodes having a small electrode area are arranged one after other, and that they are connected to the respective stages of the shift register in order. It is desirable that the area relationship of the transfer electrodes is such that the ratio between transfer electrodes having a large electrode area and a small electrode area is set to a sufficiently large value. This charge transfer device is combined with a photoelectrlc conversion unit comprised of a plurality of photosensitive elements (P) to constitute a solid state image pickup device. The photosensitive elements of the photoelectric conversion unit are respectively connected to transfer electrodes of the transfer unit to deliver signal charges taken out by respective photosensitive elements to the transfer electrodes.

Description: BACKGROUND OF THE INVENTION This invention relates to a charge transfer device and a solid state image pickup device comprising a charge transfer device. Heretofore, a solid state image pickup device called an accordion imager has been known. This device is described in detail on pages 40 to 43 in the Technical Digest IEDM (International Electron Device Meeting) 1984, A.J.P. Thenwissen; "The Accordion Imager : An Ultra-High-Density Frame Transfer CCD". A conventional accordion imager is shown in FIG. 20. This imager includes six charge transfer devices 1 arranged in parallel, 20 transfer electrodes 2 per each charge transfer device constituting respective transfer devices, a shift register 3, two-phase control pulse supply lines 4 and 5 for controlling the shift operation of the shift register, and transfer pulse supply lines 6 for delivering outputs from the shift stages as transfer pulses to corresponding transfer electrodes, respectively. Each charge transfer device 1 functions as photoelectric conversion elements to store or accumulate, for a predetermined time, carriers generated by light incident to the transfer channel through the electrodes 2 and transfer them. The electrodes 2 have equal sizes. This operation will be described in detail in conjunction with FIG. 21. In FIG. 21(a), reference symbols S 1 to S 12 represent respective shift stages, reference numeral 7 an input terminal for inputting a transfer control pulse to the shift register, and reference symbols E 0 to E 11 respective transfer electrodes when one of a plurality of charge transfer devices is taken out. Further, the slanting line portions represent the state where signal charges are stored below the transfer electrodes (the electrode voltage corresponds to high level which will be referred to as H level hereinafter, respectively, and non-slanting line portions represent the state no signal charge is stored below the transfer electrodes (the electrode voltage corresponds to low level which will be referred to as L level), respectively. In addition, reference symbols A 1 to A 15 represent transfer states at respective times after the transfer operation is initiated. Reference symbols  1 and  2 denote shift register control pulses of first and second phases, respectively. Such a two-phase clock pulse is conventionally used. Reference symbol PI denotes a transfer control pulse inputted to the shift register. As shown in FIG. 22, each of shift stages S 1 to S 12 comprises a sample hold circuit comprised of a MOS transistor 11a and a capacitor 11b, and an inverter 12. When a pulse of L level is inputted as the transfer control pulse PI, a signal of H level is outputted. Namely, a signal is inverted every time it is shifted by one stage and the inverted signal is transmitted to the succeeding stages. Accordingly, when the shift register continues to be operated under the state where the transfer control pulse PI is held at L level, the transfer state of A 1 lasts, so H level is held every other electrode. In this state, where carriers produce by photo conversion are stored, one pixel is formed by two electrodes in a vertical direction. In the example of FIG. 21, six pixels are formed. After storage operation for a predetermined time is completed, when the transfer control pulse PI shifts to H level, the electrode E 0 is placed at H level. As a result, signal charge Q 1 moves to the portion below two electrodes extending from E 1 to E 0 , resulting in the state of A 2 . When a control pulse  2 is applied at time t 3 , the shijft stage S 1 becomes operative. As a result, a transfer control pulse PI of H level is inverted and that inverted pulse is transmitted to the electrode E 1 . Thus, the electrode E 1 is placed at L-level, so signal charge Q 1 moves from the electrode E 1 to E 0 , and predetermined other devices succeeding thereto (e.g., a horizontal transfer device) (state of A 3 ). When the transfer control pulse PI shifts to L level, the electrode E 0 is placed at L level. When the control pulse  1 is applied at time t 4 , L level of the electrode E 1 moves to the electrode E 2 as H level inverted by the shift stage S 2 , resulting in the state of A 4 . The signal charge Q 1 has completed transfer from the transfer device 1 to other devices, and a portion of the signal charge Q 2 moves to the portion below the electrode E 2 . Subsequently, when the control pulse  2 is applied, potential levels of the shift stages S 1 and S 3 are inverted, resulting in the state of A 5 . As a result, signal charge Q 1 moves to the portion below the electrodes E 1 and E 2 . At this time, the electrode E 3 is placed at L level. Thus, transfer of signal charges Q 1 from the electrode E 3 is completed. Subsequently, when the transfer control pulse PI shifts to H level and the control pulse  1 is applied at time t 6 , there results the state of A 6 . Namely, the electrode E 4 is placed at H level by the level inversion of the shift stage S 4 . As a result, signal charge Q 3 moves to the portions below the electrodes E 4 and E 5 , and signal charge Q 2 moves to the portions below the electrodes E 0 and E 1 by the level inversion of the shift stage S 2 by the transfer control pulse PI. When the control pulse  2 is applied at time t 7 , there occur level inversions of the shift stages S 1 , S 3 and S 5 , resulting in the state of A 7 . Subsequently, when the transfer control pulse PI shifts to L level and the control pulse  1 is applied at time t 8 , levels of the shift stages S 2 , S 4 and S 6 are inverted, resulting in the state of A 8 . Thus, signal charge Q 2 has been completely transferred from the transfer device to other devices. By repeating such an operation, signal charges Q 3 , Q 4 , Q 5 and Q 6 are transferred. Thus, all signal charges can be transferred to other devices. This charge transfer process in this prior art is similar to the transfer process of a well known four-phase driven charge transfer device constructed to store charges below two electrodes and transfer them. However, this prior art differs from the four-phase driven charge transfer device in the following point. First, in the case of the four-phase driven charge transfer device, since a common transfer pulse is applied every four electrodes, it is unable to independently transfer signal charges stored every other electrode by a four-phase drive in sequence. Namely, since a pixel must be formed using four electrodes as one set, only three pixels are formed in a vertical direction in the case of the number of electrodes of FIG. 21. Accordingly, the degree of integration of pixels is one half of that of the above-mentioned prior art. Secondly, since phases of four pulse can be arbitrarily set in general in the case of the four-phase driven charge transfer device, a four-phase type maximum transfer charge quantity available in principle can be transferred. On the other hand, in the case of the conventional accordion type charge transfer device, it is impossible to arbitrarily set inversion timings of H level and L level inverted every other electrode. Thus, the transfer ability of the four-phase type cannot be necessarily utilized. This will be described with reference to FIGS. 23, 24 and 25. FIG. 23 shows electrodes E 2 to E 10 connected to output stages S 2 , ... S 10 of the shift register, respectively, and FIG. 24 shows a potential distribution in charge transfer channels below corresponding electrodes. As shown in FIG. 21, at time t 6 , electrodes E 2 and E 3 are placed at L level, electrodes E 4 and E 5 are placed at H level, and electrodes E 6 , E 7 , E 8 , E 9 , E 10 are set so that they are at L level and H level one after another. In accordance with this, potentials of L level and H level of the transfer channel are formed as shown in FIG. 24 (t 6 ). Thus, signal charges Q 3 , Q 4 and Q 5 are stored into the portions of H level. Since a maximum quantity of charges which can be stored and transferred prescribes the upper limit of the dynamic range, it is preferable that such a quantity is as large as possible. Further, since a quantity of charges which can be stored is substantially proportional to the electrode area, it is preferable that the charge storage state, i.e., the areas of the electrodes E 1 , E 3 , E 5 , E 7 , E 9 , and E 11 set to H level before time t 2 are set to a relatively large value. In the case where such a setting is made, at time t 7 , if the electrode E 3 is first inverted to H level and the electrode E 5 is then inverted to L level, the merit of the four-phase drive can be utilized, resulting in no problem. However, the above-mentioned two operations are carried out at the same time in principle in the prior art. Let now consider the case where the rise time t r of the circuit constituting respective output stages of the shift register is large and the fall time t f thereof is small. The transfer pulse waveforms of respective output stages in this case is shown in FIG. 25. At time t 7 , the output of the shift stage S 5 is already inverted to L level, but the output of the shift stage S 3 is not yet inverted to H level. Accordingly, as shown in FIG. 24 (t 7 ), the electrodes E 3 and E 5 adjacent to the electrode E 4 having a small area are placed at L level. At this time, signal charge Q 3 of which quantity is larger than a quantity of charges which can be stored only below the electrode E 4 overflows below the electrode E 4 and diffuses into the portion below electrodes of H level close thereto. ΔQ 3 shown in FIG. 24 (t 8 ) shows a portion of signal charge Q 3 which overflows up to the electrode E 7 and is mixed with signal charge Q 4 . Such a phenomenon will occur with respect to signal charge Q 4 at time t 10 shown in FIG. 24 (t 10 ), and will occur eventually with respect to all charges. In other words, in the case of the conventional accordion type charge transfer device, where a relative difference between the electrode areas is provided as shown in FIG. 23, the ability of the charge transfer device would be lowered. Accordingly, equally setting the areas of all the electrode results in a best structure. Namely, a maximum quantity of transfer charges cannot be larger than one half of that corresponding to all the area of the two electrodes. It has been described that the rise time t r of the output stage of the shift register and the fall time t f thereof are assumed to be expressed as t r > t f . However, generally in the case of a complementary MOS inverter circuit (see FIG. 13) used at the output stage, a p-type channel transistor prescribing the rise time has a mobility smaller than that of an n-channel transistor prescribing the fall time. Ordinarily, the relationship expressed as t r > t f holds. In addition, when the fact that it is very difficult to conduct a waveform control because of large unevenness of a load capacity of the electrodes and unevenness of the resistance over the entire transfer device is taken into consideration, it is difficult to realize an ideal four-phase drive using the conventional accordion type charge transfer device. SUMMARY OF THE INVENTION This invention has been made in view of the above-described problems, and its object is to provide a charge transfer device and a solid state image pickup device comprising same which permit the maximum storage and transfer charge quantity to be large as far as possible. To achieve this object, in accordance with the invention, there is provided a charge transfer device according to claim 1. Further, in accordance with the invention, there is provided a solid state image pickup device comprising according to claim 3. Preferred embodiments of the invention are indicated in dependent claims 2, 4-11. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is a view for explaining the principle of the operation of transfer of signal charges in a solid state image pickup device according to this invention, FIG. 2 is a partial plan view showing a first embodiment of a solid state image pickup device according to this invention, FIG. 3 is a partial plan view showing a second embodiment of a solid state image pickup device according to this invention, FIG. 4 is a view showing an arrangement of a charge transfer device according to this invention, FIG. 5 is an explanatory view showing a charge transfer process of the charge transfer device shown in FIG. 4, FIG. 6 is a timing chart showing transfer pulses applied to the charge transfer device shown in FIG. 4, FIG. 7 is a block diagram showing the configuration of a circuit for delivering a readout pulse for reading out signal charges in the solid state image pickup device shown in FIG. 2, FIG. 8 is a plan view showing a third embodiment of a solid state image pickup device according to this invention, FIG. 9 is a diagram showing the operating sequence of the television system of the solid state image pickup device shown in FIG. 8, FIG. 10 is a plan view showing a fourth embodiment of a solid state image pickup device according to this invention, FIG. 11 is a schematic diagram showing an example of shift control pulse lines, FIG. 12 is a timing chart showing control pulses delivered to respective supply lines, FIG. 13 is a circuit diagram showing respective shift stages of a shift register, FIG. 14 is a plan view showing a CMOS inverter circuit, FIG. 15 is a graph showing output waveforms of the CMOS inverter circuit shown in FIG. 14, FIG. 16 is a graph showing an input/output characteristic of a CMOS inverter circuit, FIG. 17 is a circuit diagram showing respective stages of a shift register, FIG. 18 is a time chart showing transfer pulses applied to the shift stages shown in FIG. 17 and output waveforms of respective shift stages, FIG. 19 is a block diagram showing a shift register constituted by the shift stages shown in FIG. 17, FIG. 20 is a plan view showing an arrangement of a conventional accordion type solid state image pickup device, FIG. 21 is a view showing the principle of the operation of the conventional solid state image pickup device shown in FIG. 20, FIG. 22 is a circuit diagram showing a shift register used in the conventional solid state image pickup device shown in FIG. 20, FIG. 23 is a schematic diagram showing an arrangement of the solid state image pickup device shown in FIG. 20, FIG. 24 is an explanatory view showing a charge transfer process of the charge transfer device shown in FIG. 23, and FIG. 25 is a timing chart showing transfer pulses applied to the charge transfer device shown in FIG. 23. DESCRIPTION OF PREFERRED EMBODIMENTS Preferred embodiments of this invention will now be described with reference to the attached drawings. FIG. 2 is a partial plan view showing a first embodiment of a solid state image pickup device according to this invention. In FIG. 2, reference numeral 40 represents photosensitive element trains each comprised of photosensitive elements P 1 ... P 6 , and reference numeral 30 represents charge transfer devices each comprised of transfer electrodes E 0 to E 12 . The transfer electrodes E 1 , E 3 , E 5 , E 7 , E 9 and E 11 also serve as electrodes for reading out charges from respective photosensitive element Pi (i = 1, ... 6). By simultaneously applying readout pulses which will be described later to these electrodes, signal charges are read out from the respective photosensitive elements. In this figure, reference symbols Q 1 , Q 2 , Q 3 , Q 4 , and Q 5 represent signal charges which have been read out. In this case, the electrode areas of the electrodes E 1 , E 3 , E 5 , E 7 , E 9 and E 11 are set so that they are sufficiently larger than those of the electrodes E 2 , E 4 , E 6 , E 8 , E 10 and E 12 . Thus, this electrode structure function to read out a quantity of charges as large as possible and store them. The principle of the transfer operation of the above-described first embodiment will be described with reference to FIG. 1. Reference numeral 33 represents a shift register, and reference symbols S 1 to S 13 represent the first to the thirteenth shift stages, respectively. Reference numeral 34 represents a supply line for a first shift control pulse  1A , and reference numerals 35, 36 and 37 represent supply lines for the second, third, and fourth shift control pulses  2A , 1B , and  2B , respectively. In addition, reference symbols B 1 to B 26 show the states as respective times of a distribution (H and L levels of the electrodes) of signal charges below the electrodes E 0 to E 12 , respectively. Reference symbol B 1 shows the state where signal charges have been read out from the photosensitive elements. When a transfer control pulse PI inputted to the input terminal 43 shifts to H level at time t 1 , signal charges Q 1 are stored below the electrodes E 0 and E 1 , resulting in the state of B 2 . This state is unchanged until time t 4 when a control pulse  2A for allowing the shift stage S 1 to be operative is applied at the subsequent time. When the control pulse  2A is applied at the time t 4 , the state of the shift stage S 1 is inverted. As a result, signal charge Q 1 moves from the electrode E 1 to initiate transfer to other transfer means. When a control pulse  1B is delivered at time t 5 , the state of the shift stage S 2 is inverted. As a result, the output level of the shift stage S 2 shifts to H level, so a portion of the signal charge Q 2 moves from the portion below the electrode E 3 to the portion below the electrode E 2 . Then, the transfer control pulse PI shifts to L level. At time t 6 , transfer of signal charge Q 1 from the electrode E 0 to other means is entirely completed. At time t 7 , the control pulse  2A is delivered, so signal charge Q 2 is stored into the portion extending over three electrodes E 1 , E 2 and E 3 (state of B 8 ). When a control pulse  2B is delivered at time t 8 , the state of the shift stage S 3 is inverted, and the electrode E 3 is placed at L level. As a result, signal charge Q 3 move so that they are stored only into the portions below the electrodes E 1 and E 2 (state of B 9 ). When a control pulse  1A is delivered at time t 9 , the state of the shift stage S 4 is inverted, so a portion of the signal charge Q 3 moves to the portion below the electrode E 4 . At this time, the transfer control pulse PI also shifts to H level, so signal charge Q 2 is stored into the portions below the three electrodes E 0 , E 1 and E 2 (state of B 10 ). When a control pulse  1B is applied at time t 10 , the state of the shift stage S 2 is inverted, so signal charge Q 2 is stored only into the portions below E 0 and E 1 (state of B 11 ). When a control pulse  2B is delivered at time t 11 , the state of the shift stage S 3 is inverted, so the electrode E 3 is placed at H level. Accordingly, signal charge Q 3 is stored into the portions below three electrodes E 3 , E 4 and E 5 , resulting in the state of B 12 . At time t 12 , a control pulse  2A is delivered, so the states of the shift stages S 1 and S 5 are inverted. Thus, the electrode E 5 is placed at L level, so signal charge Q 3 moves to only the portions below the electrodes E 3 and E 4 and are stored thereinto (state of B 13 ). Since the electrode E 1 is also placed at L level at this time, transfer of signal charge Q 2 to other devices is initiated. Similarly, when a control pulse  1B is delivered at time t 13 , the states of the shift stages S 2 and S 6 are inverted, so the electrodes E 2 and E 6 are placed at H level. Thus, portions of signal charges Q 3 and Q 4 move to the portions below the electrodes E 2 and E 6 , respectively (state of B 14 ). Then, the transfer control pulse PI shifts to L level and signal charge Q 2 is completely transferred. At time t 14 , the shift stage S 4 is inverted by the control pulse  1A , resulting in the state of B 15 . At time t 15 , a control pulse  2A is delivered, so the shift stages S 1 and S 5 are inverted. Thus, signal charges Q 3 and Q 4 are stored into the portions below three electrodes E 1 , E 2 and E 3 and the portions below three electrodes E 5 , E 6 and E 7 , respectively (state of B 15 ). Further, when a control pulse  2B is delivered at time t 16 , the states of the shift stages S 3 and S 7 are inverted. As a result, signal charges Q 3 and Q 4 move to portions below two electrodes E 1 and E 2 and the portions below two electrodes E 5 and E 6 , By repeatedly carrying out the above-mentioned operation, transfer of signal charges Q 3 , Q 4 , Q 5 and Q 6 to other devices can be completed. The feature of the above-described first embodiment resides in that, in transferring one signal charge, an approach is employed to once store it into the portion below the three electrodes thereafter to store it into the portion below the two electrodes. With the prior art, as previously described, such a control cannot be performed, with the result that there may occur the case where a signal charge is once stored into the portion below one electrode and is then stored into the portions below two electrodes. Accordingly, it is impossible to enlarge an electrode area of an initial storage electrode (also serving as a readout electrode) to increase a relative storage capacity. On the contrary, this embodiment can easily realize this. The reason thereof will be described in detail with reference to FIGS. 4, 5 and 6. FIG. 4 shows a connection relationship of shift registers S 2 to S 11 , electrodes E 2 to E 10 connected to the respective output stages, and supply lines 34, 35, 36 and 37 for delivering shift control pulses  1A ,  2A ,  1B and  2B for controlling respective output stages. FIG. 5 shows a potential distribution at respective times formed in the transfer channels below respective electrodes wherein the slanting line portions show signal charges as the liquid model. FIG. 6 shows a supply pulse timing from time t 10 to t 17 . At time t 10 , a control pulse  1B is delivered to shift registers S 2 , S 6 and S 10 , resulting in the state of B 11 of FIG. 1(a). Namely, the shift stage S 2 is inverted to L level by signals of H and L levels of the transfer control pulse PI inputted from the input terminal 43. The shift stages S 6 and S 10 hold the previous state. At time t B11 , a potential distribution shown in FIG. 5 (t B11 ) is formed. At time t 11 , a control pulse  2B is delivered to shift stages S 3 , S 7 and S 11 . Thus, the shift stage S 3 is inverted to H level, so the electrode E 3 is placed at H level. As a result, a portion of signal charge Q 3 moves to the portion below the electrode E 3 . As shown in FIG. 5 (t B12 ), the signal charges Q 3 are stored into the portions below three electrodes E 3 , E 4 and E 5 . It is at time t 13 that the signal charge Q 3 is stored into the portions below two electrodes E 3 and E 4 . The potential distribution in this case is shown in FIG. 5 (t B13 ). When a control pulse  1B is delivered to the shift stages S 2 , S 6 and S 10 for a second time at time t 13 , a change in the state of the shift stage S 5 is transmitted also to the shift state S 6 . As a result, the states of the shift stages S 2 and S 6 are inverted. The potential distribution at time t B14 is shown in FIG. 5 (t B14 ). The signal charge Q 3 is stored into the portions below three electrodes, and a portion of signal charges Q 4 moves to the portion below the electrode E 6 and is stored into the portions below two electrodes. When a control pulse  1A is delivered at time t 14 , the shift stage S 4 is inverted. At time t 15 , signal charges Q 3 and Q 4 are both placed in two electrode storage state as shown in FIG. 5 (t B15 ). When a control pulse  2A is delivered at time t 15 , the shift stage S 1 (not shown) and the shift stage S 5 are inverted. At time B 16 , signal charges Q 3 and Q 4 are both placed in a three electrode storage state as shown in FIG. 5 (t B16 ). At time t B17 , those charges are placed in two electrode storage state for a second time as shown in FIG. 5 (t B17 ). By repeatedly carrying out such an operation, all charges are transferred. As stated above, since it can be completely prevented that charges of which transfer operation has been initiated are stored into only one electrode, there is no possibility that the maximum transfer charge quantity is prescribed by the area of only one area. Accordingly, when setting is made such that the lengths of electrodes E 1 , E 3 , E 5 , E 7 , E 9 and E 11 sharing an initial storage (readout storage) of signal charges are larger than those of electrodes except for the above, these electrode lengths prescribe the maximum transfer charge quantity. By setting these electrode lengths to a value as large (long) as a limited value of the processing technology, the maximum performance can be realized. FIG. 7 is a circuit diagram showing a shift register and circuit elements associated therewith in the case where the readout electrodes and the transfer electrodes are integrally formed. Reference numerals 76 and 78 represent readout/transfer electrodes having a relatively large area (E 3 and E 5 in this case), and reference numeral 77 denotes small area electrodes (E 4 in this case) except for small area electrodes. These electrodes are electrically coupled as plural sets thereof, respectively. Further, reference numerals 79, 80 and 81 represent shift stages (S 3 , S 4 , S 5 ) of a shift register, respectively. Their output terminals are connected to respective electrodes through wiring 82, 83 and 84. Reference numeral 75 denotes a readout signal supply line, reference numerals 72 and 73 switch circuits for selectively delivering readout signals to the electrodes 76 and 78 through wiring 71 and 70, respectively, and reference numeral 74 a switch control pulse supply line for controlling ON/OFF of the switch circuits 72 and 73. At the time of reading out signal charges, the electrodes E 3 (76) and E 5 (78) are set so that they are at H level. In this state, when the switch circuits 72 and 73 are turned ON, a readout signal 75 of H level is delivered to the electrodes 76 and 78. Thus, signal charges are read out from photosensitive elements (not shown) to respective electrodes. In this case, the readout signal 75 of H level is transmitted also to the output terminals of the shift stages 79 and 81. However, since these portions are set so that they are at H level, there is no possibility that the state of the shift register is inverted. Further, in the case where one electrode commonly performs such readout and transfer operations, it is preferable that H level, L level, and readout potential at the time of transfer is zero or a slight positive potential, a negative potential, and a positive high potential (e.g., 10 volts), respectively. A second embodiment of a solid state image pickup device according to this invention is shown in FIG. 3. This embodiment differs from the above-described first embodiment in that there are provided electrodes 32 for an exclusive use in reading out signal charges from the photosensitive elements 40 to the respective charge transfer devices 31. Since each electrodes 32 is electrically independent of transfer electrodes E 0 to E 12 , readout operation can be realized at an arbitrary timing without necessity of the above-described switch circuit, etc. The solid state image pickup device of the second embodiment can provide the same advantages with those of the solid state image pickup device of the first embodiment. A third embodiment of a solid state image pickup device according to this invention is shown in FIG. 8. In FIG. 8, reference numerals 85 represents a plurality of photosensitive element trains, respectively, reference numerals 86 vertical charge transfer devices, respectively, reference numeral 87 a register for controlling the transfer operation of each charge transfer device, reference numeral 88 a first horizontal charge transfer device, reference numeral 89 a second horizontal charge transfer device, reference numeral 90 a first output circuit, and reference numeral 91 a second output circuit. The operating sequence of the television system in this arrangement is shown in FIG. 9. In FIG. 9, reference numeral 92 represents an output signal time series, reference numerals 95 are intervals or time periods during which signals of two lines are outputted from the output circuits 90 and 91, respectively, reference numerals 96 horizontal blanking intervals, respectively, and a reference numeral 97 a vertical blanking interval. Reference numeral 93 represents a readout voltage pulse which is delivered for the vertical blanking interval 97. Reference numeral 99 represents a supply sequence of a shift register control pulse, reference numerals 94 intervals or time periods during which a train of pulses from time t 0 to time t 16 of FIG. 1(b) are applied, respectively, and reference numeral 100 an interval or time period for initializing respective vertical charge transfer device 86 prior to application of the readout voltage pulse 93. This initialization is realized by setting the transfer control pulse PI so that it is at L level to operate the shift register by the number of shift stages. All signal charges in the photosensitive elements are read into the vertical transfer devices 86 by the readout voltage pulse 93. Then, charges of two lines are transferred to the first and second horizontal transfer devices 88 and 89 for respective intervals 94 on the basis of the above-described principle of FIG. 1(a). By operating these horizontal transfer devices, outputs are provided for respective intervals 95. As stated above, by carrying out the operation of each vertical transfer device for the blanking interval, occurrence of pulsated noises jumping into an output signal can be completely eliminated. By carrying out this operation a predetermined times, all signal charges forming one frame can be entirely independently read out for a time period of one field (one field of the interlace). A fourth embodiment of a solid state image pickup device according to this invention is shown in FIG. 10. This embodiment differs from the embodiment of FIG. 8 in that there is provided a storage transfer unit 102 between the vertical transfer devices 86 and the horizontal transfer devices 88 and 89. The storage transfer unit 102 is supplied with transfer pulses from the shift register 101 to transfer charges transferred from the vertical transfer devices 86 in a direction perpendicular to the plane of paper (in a vertical direction). The operation of the storage transfer unit 102 is carried out in accordance with the above-described four-phase drive to repeat the two electrode storage and the three electrode storage. In order that charges transferred are stored in succession from the lowermost row to one electrode, transfer control pulses inputted to the shift register 101 are set. Actually, for this purpose, a procedure may be taken to repeat the operation having the sequence from the time t 0 to the time t 16 as a unit to set an input voltage to the shift register 101 to represent L level at the time point when the leading charge has reached the portion below the final storage electrode of the storage transfer unit 102 to keep that input voltage at L level unit all charges are transferred to the storage transfer unit 102. The transfer from the shift register 101 to the horizontal transfer device is exactly the same as the transfer process of the vertical charge transfer device 86 of FIG. 8. It is desirable that the transfer from the vertical charge transfer devices 86 to the storage transfer unit 102 is carried out at a relatively high speed (high frequency) for a vertical blanking interval. It is to be noted that even if a conventional charge transfer device is used as the storage transfer unit 102, the effects and/or advantages with this invention using vertical charge transfer devices 86 cannot be impeded. It is to be noted that four kinds of shift register control pulses used in this invention must not be necessarily supplied from the external. An example of shift control pulse supply lines is shown in FIG. 11. Reference symbols S 1 and S 8 represent respective shift stages of the shift register, reference numerals 103 and 104 switch circuits for controlling connection between supply lines 108 and 107 and respective shift stages for shift control pulses  B and  A , and reference numerals 105 and 106 supply lines for two-phase pulses  1 ' and  2 ' for controlling the switch circuit, respectively. An example of control pulses delivered to respective supply lines is shown in FIG. 12. Reference symbol  A represents a pulse delivered to the supply line 107, reference symbol  B a pulse delivered to the supply line 108, reference symbol  1 ' a pulse delivered to the supply line 105, and reference symbol  2 ' a pulse delivered to the supply line 106. In response to supply of these pulses, pulses  1A ',  2A ',  1B ' and  2B ' similar to those in FIG. 1(b) are delivered to the shift stages S 1 to S 8 . More particularly, the pulse  1A ' is delivered to the shift stages S 4 and S 8 , the pulse  2A ' is delivered to the shift stages S 1 and S 5 , the pulse  1B ' is delivered to the shift stages S 2 and S 6 , and the pulse  2B ' is delivered to the shift stages S 3 and S 7 . It is to be noted that in the case where a buffer circuit is provided between the output circuit of the shift register or the output circuit and the transfer electrodes, the same advantages as those with this invention can be provided by allowing the fall time with respect to the rise time of the output circuit to be sufficiently large. An example for realizing this is shown as follows. FIG. 13 is a typical circuit diagram showing one shift stage of the shift register circuit. Reference numerals 117a and 117b represent n-channel type sample hold elements, respectively, and reference numerals 118 and 119 an n-channel type MOS transistor and a p-channel type MOS transistor, respectively, which constitutes a well known CMOS inverter circuit. A voltage of H level is delivered to the node 121, and a voltage of L level is delivered to the node 120. A voltage of H level is inputted to the input terminal 122. When the transistor 117a is turned ON, a voltage of H level is delivered to the gates of the transistors 118 and 119. As a result, the transistor 118 becomes conductive and the transistor 119 becomes non-conductive. Accordingly, the output terminal 123 is placed at L level. In contrast, when a voltage of L level is inputted to the input terminal 122, the transistor 117a is turned ON. As a result, the transistor 118 becomes non-conductive, and the transistor 119 becomes conductive. Accordingly, the output terminal 123 is placed at H level. The fall from H level to L level is determined by the operating speed of the n-channel transistor 118, and the rise from L level to H level is determined by the operating speed of the p-channel transistor 119. On the other hand, as well known, the positive hole mobility of the p-channel transistor is about one third of the electron mobility of the n-channel transistor. Accordingly, the operating speed also becomes equal to about one third. Namely, in order to realize this invention by an ordinary two-phase shift control, it is necessary to set the channel width/the channel length (W/L) of the p-channel transistor to be at least three times or more than that of the n-channel transistor. FIG. 14 is a plan view showing a CMOS inverter circuit. Reference numeral 129 represents an n-channel MOS transistor formed within a p-well 159 wherein the mesh slanting line portion 132 represents a channel region, Ln a channel length, and Wn a channel width. Reference numeral 130 represents a p-channel MOS transistor formed on an n-type substrate wherein the mesh slanting line portion 131 represents a channel region, Wp a channel width, and Lp a channel length. Reference numerals 133 and 134 represent an input terminal and an output terminal of the inverter gate, respectively. In this case, since Wp/Lp is set so that it is about six times than Wn/Ln, the operating speed of the transistor 130 become equal to a value about two times larger than the operating speed of the transistor 129. Thus, an output waveform shown in FIG. 15 is provided. In FIG. 15, reference numeral 135 represents a rise waveform from L level to H level, reference numeral 136 represents a fall waveform from H level to L level, t r a rise time, and t f a fall time. As seen from this figure, the relationship expressed as t r t f is sufficiently satisfied. Thus, there is no possibility that at least maximum transfer charge quantity is prescribed only by one electrode like a signal charge Q 3 shown in FIG. 23 (t 7 ). An input/output characteristic of a CMOS inverter is shown in FIG. 16. As shown in FIG. 16, the threshold voltage Vthn of the n-channel type MOS transistor is set to a value sufficiently larger than the threshold voltage Vthp of the p-channel type MOS transistor. Accordingly, the time when the n-channel type MOS transistor starts to rise can be sufficiently delayed with respect to the time when the p-channel type MOS transistor starts to rise. Thus, the intention of this invention can be realized. An example for realizing a unit shift stage of the shift register according to this invention by a circuit configuration is shown in FIG. 17. Reference numeral 148 represents an input terminal, reference numerals 141a and 141b an n-channel MOS transistor and a capacitor constituting a sample hold circuit, respectively, and reference numeral 159 an input wiring for a CMOS inverter. Reference numerals 142 and 143 represent a p-channel type MOS transistor and an n-channel type MOS transistor constituting the CMOS inverter, respectively. The transistor 143 is connected to a L level voltage supply line 161 through an n-channel type MOS transistor 144. The conductive state of the transistor 144 is controlled by another input line 145. The operation of the above-described shift register will be described with reference to FIGS. 18 and 19. An example of control pulses inputted to the transistor 141a and the input line 145 is shown in FIG. 18. FIG. 19 shows a shift register comprised of shift register unit shift circuits of this invention shown in FIG. 17. In FIG. 19, reference symbols S 3 to S 6 represent shift stages, respectively, reference numerals 165, 166, 162 and 163 supply lines for the pulses  1 ,  2 ,  3 and  4 shown in FIG. 18, respectively. The pulses  1 and  2 are inputted to the transistor 141a as a control pulse of the sample hold circuit, and the pulses  3 and  4 are delivered to the input line 145. Let suppose the case where, e.g., the output of the shift stage S 3 is at L level, the outputs of the shift stages S 4 and S 5 are at H level, and the output of the shift stage S 6 is at L level. When a signal of L level is inputted to the input line 164 of the shift stage S 3 and the pulse  1 is delivered, transistors 141a of the shift stages S 3 and S 5 become conductive. As a result, the inverter input 159 of the shift stage S 3 shifts to L level, so the transistor 142 is turned ON. Thus, a voltage of H level delivered from the supply line 160 is transmitted to the output terminal 147. On the other hand, the inverter input of the shift stage S 5 shifts to H level. As a result, the transistor 142 is turned OFF and the transistor 143 is turned ON. However, this transistor 143 does not conductive with the L level supply line 161 as long as the transistor 144 is turned ON. At times t 7 " and t 11 " of FIG. 18, the pulse  4 is delivered to the input line 145, so the transistor 144 is turned ON. As a result, the output terminal 147 and the L level supply line 161 become conductive. Thus, the output terminal 147 of the shift stage S 5 is placed at L level. An operation similar to the above will be conducted also for the shift stages S 4 and S 6 to which pulse  1 and  3 are delivered. Namely, the time when the potential level of the output terminal 147 is inverted from H level to L level with respect to the time when that potential level is inverted from L level to H level will be delayed by a difference T 1 (T 2 ) between a rise time of the pulse  2 ( 1 ) and that of the pulse  4 ( 3 ). Accordingly, by controlling this time difference, the fall of the output can be delayed by a predetermined time. Thus, this invention can be realized. Output waveforms of respective output stages are shown in FIG. 18. These outputs serve as transfer pulses delivered to the transfer electrodes. As shown at times t 6 " and t 13 ", three pulses are kept substantially at H level at the time when inversion from H level to L level is initiated with respect to all the output pulses. It is apparent that this invention may be realized by an approach in which a delay circuit 146 shown in FIG. 17 is inserted to delay a pulse inputted to the transistor 143 by a predetermined time to input such a delayed pulse to the transistor 144. In this case, pulses  3 and  4 of FIG. 18 entirely become unnecessary. In accordance with this invention, storage of charges into the electrode and readout of charges therefrom can be formed using a two transfer electrode as a unit. Further, the electrode area used for storing charges is enlarged to thereby increase its storage capacity. Thus, charges can be transferred without reducing the maximum charge transfer capacity. As a result, the degree of integration of elements can be improved and the maximum dynamic range (maximum signal charge quantity) can be provided. Furthermore, the restriction of pulse timings in transfer can be relaxed to a great extent. It is to be noted that this invention is not limited to the implementation of two electrodes per each photosensitive element. In the case of carrying out the interlace operation known as the television system, an arrangement of two electrodes by two photosensitive elements may be realized and other various arrangements may be adopted. In addition, it is needless to say that the technology of this invention is not necessarily limited to a solid state image pickup device, but may be applied to charge transfer type memory devices. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A charge transfer device comprising (a.1) a shift register (S) having a plurality of shift stages ((S 1 -S 13 ) connected in series; (a.2) shift control pulse supply lines (34, 35, 36, 37) for supplying a multi-phase control pulse (Ø) to said shift stages (S 1 -S 13 ); (a.3) an input terminal (43) for supplying a transfer control pulse (Pℓ) to that shift stage (S 1 ) arranged at one end of said plurality of shift stages (S 1 -S 13 ) ; (b.1) a transfer unit (30) having a plurality of storage electrodes (E 0 -E 12 ) provided in correspondence with said shift stages (S 1 -S 13 ) of said shift register (S); (b.2) each common node of two adjacent ones of said shift stages (S 1 -S 13 ) being connected to a corresponding one of said storage electrodes (E 0 -E 12 ) for applying transfer pulses from said shift stages (S 1 -S 13 ) to said storage electrodes (E 0 -E 12 ), to thereby sequentially transfer signal charges stored below said storage electrodes (E 0 -E 12 ) in a predetermined transfer direction; (c.1) wherein said storage electrodes comprise first storage electrodes (E 1 ,E 3 ,E 5 ,...) having a larger width in said predetermined transfer direction; (c.2) and second storage electrodes (E 0 ,E 2 ,E 4 ,···) having a smaller width in said predetermined transfer direction; (c.3) said first and second storage electrodes (E 0 -E 12 ) are arranged in alternating fashion one after another; (d) the areas of said first storage electrodes (E 1 ,E 3 ,E 5 ,...) having a larger width are larger than the areas of said second storage electrodes (E 0 ,E 2 ,E 4 ,...) having a smaller width such that said first storage electrodes can store a larger charge than said second electrodes; and (e) said multi-phase control pulse (⊘;⊘ 1A ,⊘ 2B ,⊘ 1B ,⊘ 2A ) and said transfer control pulse (Pℓ) have a configuration such that a charge stored below a first group of two storage electrodes (E 3, E 2 ) is transferred along the transfer direction by storing said charge below a second group of three storage electrodes (E 3 ,E 2 ,E 1 ) and then below a third group of two storage electrodes (E 2, E 1 ), said first, second and third groups of storage electrodes being arranged along the transfer direction, said first and second group of storage electrodes having two electrodes in common, and said second and third group of storage electrodes having two electrodes in common. A charge transfer device according to claim 1, characterized in that said multi-phase control pulse (Ø) comprises at least four control pulses (⊘ 1A ,⊘ 1B ,⊘ 2A ,⊘ 2B ) having different phases. A solid state image pickup device comprising a charge transfer device according to claims 1 or 2 and further comprising a photoelectric conversion unit (40) having a plurality of photosensitive elements (P 1 ,P 2 ,...) for converting an optical input into electrical charges. A solid state image pickup device according to claim 3, wherein: each of said shift stages of said shift register comprises a sample-hold circuit (117a, 117b) and an inverter circuit (118,119) that inverts the output of said sample-hold circuit, with four continuous shift stages being controlled by signals transmission with respectively different control pulses. A solid state image pickup device according to claim 4 comprising: a read electrode (76,78) to read a signal charge from one of said photosensitive elements, and signal supply means provided individually for said shift registers, and supplying read control signals to read signal charges at a read cycle. A solid state image pickup device according to claim 5, comprising: switch circuits (72,73) that electrically connect said signal supply means and said transfer electrode during a read cycle, and separate said signal supply means and said transfer electrode during other cycles. A solid state image pickup device according to claim 3, wherein each of said shift stages of said shift register (S) comprises a sample-hold circuit (117a,117b) and an inverter circuit (118,119) that inverts the output of said sample-hold circuit, and said inverter circuit has a shorter rise (t r ) time than its fall time (t f ). A solid state image device according to claim 7, wherein: each of said shift stages of said shift register (S) comprises a gate circuit that controls at least a first time for a rise and a fall of said inverter circuit. A solid state image pickup device according to claim 3, wherein a readout control electrode (32) is provided between said photosensitive elements (40) in said photoelectric conversion unit and said transfer electrodes (31) in said transfer unit. A solid state image pickup device according to claim 3, wherein: plural sets of photoelectric conversion units and transfer units are provided as said photoelectric conversion unit and said transfer unit, respectively, and said solid state image pickup device further comprises a plurality of transfer devices for deriving outputs respectively from said transfer units and taking them out from said transfer units. A solid state image pickup device according to claim 10, wherein: a storage transfer unit (102) is provided between said transfer units and said transfer devices.

Inventors: YAMADA TETSUO, YAMADA, TETSUO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H04N3
IPC codes: H01L29, H01L27, H01L21, H04N5, H04N3