A semiconductor device and its manufacturing method

Abstract: A semiconductor device comprising CMOS type field effect transistors wherein the gate electrodes of both the P-channel and N-channel transistors are of p⁺ polycrystalline silicon containing grains of a size of greater or equal to 1 mycrometer. Further disclosed is a method of manufacturing a semiconductor device wherein a conductive layer is formed by the following steps: first, forming a noncrystalline semiconductor layer mainly composed of silicon containing impurities, such as phosphrous or boron 1 x 10¹⁶ to 1 x 10²² cm⁻³ by plasma CVD and then performing a thermal treatment for solid phase recrystallization of said noncrystalline semiconductor layer.

Description: This invention relates to a semiconductor device comprising CMOS type field effect transistors and to its manufacturing method, in particular, a semiconductor device on an insulating material and its manufacturing method. Experiments have been performed to form high quality semiconductor elements on insulating materials, such as insulating amorphous substrates, for example, glass, quartz or the like, insulating amorphous layers, for example SiO 2 , Si 3 N 4 and the like, and so forth. In recent years, expectations for improved high quality semiconductor elements formed on the foregoing insulating amorphous materials have been substantial as the needs for large, high resolution liquid crystal display panels, high speed, high resolution contact type image sensors, three dimensional ICs, and the like have increased. In the case of, for example, forming a thin film transistor (TFT) on an isulating amorphous material, the following methods have been studied: (1) TFT comprising amorphous silicon formed by plasma CVD or the like as an element material, (2) TFT comprising polycrystalline silicon formed by CVD or the like as an element material, (3) TFT comprising single crystalline silicon formed by fusion recrystallization or the like as an element material, and the like. However, realization of high quality TFTs has been very difficult because the field effect mobility of TFTs comprising amorphous silicon or polycrystalline silicon is substantially lower than that of TFTs comprising single crystalline silicon (amorphous silicon TFTs < 1 cm 2 /V.sec, polycrystalline silicon TFT about 10cm 2 N/V.sec). On the other hand, the fusion recrystallization technique employing a laser beam has not been quite complete yet, and many technical difficulties are encountered when elements are to be formed on a large area, such as liquid crystal display panel. Thus, the method of forming large grain polycrystalline silicon by solid phase recrystallization was noticed, and the research has been proceeded. [Thin Solid Films Vol. 100 No. 3 (1983) P.227, JJAP Vol. 25 No. 2 (1986) p. L121] However, the conventional method of the prior art is that, first polycrystalline silicon is formed by CVD, and after said polycrystalline silicon is amorphized by Si + ion implantation, heat treatment is performed at approximately 600°C for nearly 100 hours. Because of that, there are such problems as: (1) since polycrystalline silicon is amorphized after if has once been formed, the process is complicated causing a cost up, (2) an expensive ion implantation system is necessary, (3) the heat treatment is extremely long, (4) it is very hard to handle a large substrate (for example, 30 cm x 30 cm), (5) the crystallized volume fraction after solid phase recrystallization is low and, therefore, it is very difficult to fabricate a high quality semiconductor device, and the like. A semiconductor device comprising CMOS type field effect transistors whose gate electrodes of both the P-channel and N-channel transistors are of n + type polycrystalline silicon is disclosed in EP-A-0 296 747. The document Appl. Phys. Lett. 41(4), 15. August 1992, pp. 379-381 discloses polycrystalline silicon formed by solid phase recrystallization on an amorphous substrate according to the method explained above and having an average grain size of 1 µm. The document US-A-4,448,632 discloses a method of forming a monocrystalline silicon layer by first forming a polycrystalline silicon layer on an amorphous substrate, increasing the grain size of the polycrystalline layer to 5 µm and more by laser fusion recrystallization, forming an epitaxial layer on the polycrystalline layer and converting the two layers into monocrystalline silicon by a second step of laser fusion recrystallization. The document US-A-4,249,957 discloses p and n type polycrystalline silicon for use in a solar cell, which has a grain size of 0.05 to 0.5 mm. The document US-A-4,129,463 discloses a method of forming uniformly n type phosphorousdoped polycrystalline silicon having a mean grain size of less than 1000 µm suitable for use in photovoltaic devices. It is an object of this invention is to provide means to realize a high quality semiconductor device including CMOS type field effect transistors wherein good TFT characteristics can be obtained in both p channel and n channel without requiring channel doping. This object is achieved with a semiconductor device and a manufacturing method as claimed. Specific embodiments of the invention are subject of dependent claims. Specific embodiments of the invention will be described below with reference to the drawings, in which: Fig. 1(a) to (d) show a manufacturing process of a semiconductor device. Fig. 2(a) to (d) show graphic illustrations of the temperature rise in a thermal treatment process. Fig. 3(a) to (e) show graphic illustrations of temperature rise in a thermal treatment process. Fig. 4(a) to (f) show a manufacturing process of a semiconductor device according to an embodiment of this invention. Fig. 5 shows gate voltage - drain current characteristics of an n channel TFT of this invention. Fig. 6 shows gate voltage - drain current characteristics of a p channel TFT of this invention. Fig. 1 shows one example of the manufacturing process of a semiconductor device. The case wherein a thin film transistor (TFT) is formed as a semiconductor element is shown as an example in Fig. 1. Fig. 1(a) shows a process of forming a silicon layer 102 over an insulating material 101, such as an insulating amorphous substrate, for example, glass, quartz and the like, an insulating amorphous material layer, for example, SiO 2 , Si 3 N 4 and the like, and so forth. Other insulating crystalline substrates, such as a sapphire substrate (Al 2 O 3 ), MgO.Al 2 O 3 , BP, CaF 2 , and the like can also be employed as a substrate instead of quartz and glass. One example of the film growth condition is described hereinafter. When the substrate temperature is maintained approximately in the range of room temperature up to 600°C, monosilane or monosilane gas diluted with hydrogen, argon, helium, or the like is introduced to a reactive chamber and RF power is applied to dissociate the gas, then a silicon layer is formed at a thickness of about 0.01 - 0.2 µm on a desired substrate by plasma CVD. However, the method of forming the film is not limited to the foregoing. Fig. 1(b) shows a process of forming a polycrystalline silicon layer 103 via crystal growth by performing a thermal treatment or the like on said silicon layer 102. The best condition of the thermal treatment differs depending upon the method of forming the silicon layer in process (a). For example, depending upon the substrate temperature difference at the time of forming the silicon layer, there are differences as follows: (1) A film formed while the substrate temperature is in the range of room temperature up to 150°C, which is relatively low, becomes amorphous silicon containing a large amount of hydrogen in the film, however, hydrogen in the film can be removed by a thermal treatment at a lower temperature compared to a film formed in the temperature range of approximately 200 to 300°C. One example of a thermal treatment condition is described hereinafter. After an amorphous silicon film has been formed by plasma CVD, the film is annealed before vacuum is broken. Since an amorphous film formed at low temperature becomes porous, if it is taken out to the air as is after the film growth, then oxygen and the like will enter into the film rendering a low quality film. However, if the film is given proper thermal treatment before it is taken out to the air, then the film becomes dense, thereby preventing oxygen from entering in the film. The desirable thermal treatment temperature is over 300°C, and if the temperature is raised to approximately 400 to 500°C, substantially effective results can be achieved. Also, even when the thermal treatment temperature is lower than 300°C, film densification can be achieved. However, when annealing for solid phase recrystallization is continuously performed without breaking vacuum, the above annealing can be omitted. Next, said amorphous silicon film undergoes a thermal treatment or the like for solid phase recrystallization. When thermal treatment of about 550°C to 650°C is performed for about several hours to 20 hours on an amorphous silicon film which was formed at low temperature, hydrogen removal and crystal growth occur, and polycrystalline silicon containing large grains of about ≥(1 to 2 µm) is formed. It is not desirable to raise the temperature of annealing for both achieving density and solid phase recrystallization to the prescribed degree suddenly in short time. The reason for this is that hydrogen removal in the film starts to occur as the temperature rises (especially over 300°C), and if the temperature rise speed is too high, defects in the film will occur more easily. In some cases pin holes may appear, and in other cases film separations may occur. If the temperature is gradually raised by less than 20°C/min (particularly, a rising temperature speed of less than 5°C/min is desirable.) at least when the annealing temperature is over 300°C, defects in the film will be less likely. The detailed explanation of the method of raising the temperature is described later in this text. (2) The amount of hydrogen in a film is less if the film is formed when the substrate temperature is in the range of 150°C to 300°C compared to an amorphous silicon film formed at low temperature as described above; however, the temperature shifts to a higher degree when hydrogen removal starts. Since the film is more dense compared to the film formed at lower temperature, the annealing for achieving density can be omitted. When solid phase recrystallization is performed under the thermal treatment temperature of 550°C to 650°C for about several hours to 40 hours, then hydrogen removal and crystal growth occur, and polycrystalline silicon containing large grains of about 1 to 2 µm is formed. Although the detailed explanation of the method of raising the temperature to 550°C to 650°C is described later in this text, if the temperature is gradually raised by less than 20°C/min (particularly, a rising temperature speed of 5°C/min is desirable) when the annealing temperature is over 300°C, defects in the film will be less likely as was described in (1). Also, the substrate temperature of 150°C to 200°C is particularly desirable because large grains can be formed and film separation, which may occur during temperature rise to the prescribed degree for solid phase recrystallization does not occur easily. (3) Although hydrogen in the film decreases even more when the substrate temperature exceeds 300°C, hydrogen removal is less likely to occur by annealing at the temperature of approximately 550°C to 650°C. Therefore, in some cases it becomes important to perform thermal treatment at a higher temperature than said temperature, and the description concerning this method will appear later in this text using Fig. 2(d). The thermal treatment condition, particularly, the method of raising the temperature to the prescribed degree is described hereinafter. Fig. 2 shows graphic illustrations of examples of the method of raising the temperature. Fig. 2(a) shows the case wherein, first, the temperature is raised to the prescribed level (T 1 ) at the specified temperature rise speed and then annealing is performed at this prescribed level (T 1 ). As it was mentioned previously, the desirable temperature rise speed is less than 20°C/min (preferably it is 5°C/min) so that occurrence of defects associated with hydrogen removal is suppressed. Also, the temperature rise speed need not be constantly the same, but it can fluctuate within the foregoing range. Fig. 2(b) shows the case wherein, first, the temperature is raised to the prescribed level (T 2 ) at the specified temperature rise speed, then the temperature is further raised to the annealing temperature of T 1 by a lower temperature rise speed. The reason for the change of the temperature rise speed around T 2 is that, as it was mentioned previously, hydrogen removal in the film starts at a temperature higher than about 300°C. Therefore, after hydrogen removal has started, the temperature rise speed is slowed down to less than 20°C/min (preferably 5°C/min) so as to suppress the occurrence of defects (it also contributes to shorten the temperature rise time.) The desirable level of T 2 is about 250°C to 400°C. Also, as in the case of Fig. 2(a), the temperature rise speed need not be constantly the same. Further, when the temperature rise speed is changed around T 2 , this does not have to be sudden, but it can be changed gradually. Also, there may be a stepwise change with a plurality of intermediate temperatures like T 2 . Fig. 2(c) shows the case wherein, first, the temperature is raised to T 2 , then T 2 is maintained for a certain time and then the temperature is further raised to the annealing temperature of T 1 . A large amount of hydrogen in the film can be removed without generating polycrystalline nuclei by maintaining a temperature lower than the annealing temperature for a certain time (for example, about 20 minutes to 2 hours). Thus, even when the temperature is raised fast to the annealing temperature for solid phase recrystallization after maintaining T 2 for a certain time, the occurence of defects associated with hydrogen removal is less likely to occur. The desirable value of T 2 is about 350°C to 550°C. T 2 need not be constantly the same. For example, it is alright to slowly raise the temperature by less than 5°C/min. There may be a stepwise change with a plurality of intermediate temperatures like T 2 also. For example, after maintaining the temperature at about 350°C, the temperature can be again maintained around 500°C. By doing so, hydrogen in the film can be removed more completely suppressing the occurence of defects in the film at the same time. Fig. 2(d) shows the case wherein, first, the temperature is raised to the annealing temperature of T 1 , then the temperature is raised in a period of several minutes to T 3 , which is higher than the annealing temperature, then the temperature is cooled down to T 1 in a period of several minutes and then annealing is performed at T 1 . By having the step of raising the temperature to T 3 , crystalline growth can be progressed with complete hydrogen removal, compared to the time when crystalline growth is hindered by hydrogen in the film at the time of annealing at about 550°C to 650°C. The desirable value of T 3 is about 700°C to 800°C. It is necessary to keep the time for raising the temperature to and cooling down from T 3 short (preferably within the range of 1 to 10 minutes) in order to suppress generation of polycrystalline nuclei. Therefore, lamp annealing is effective to raise the temperature to T 3 in short time. It is also possible to suppress occurrence of defects even more by combining a plurality of the methods in Fig. 2(a) - (d). Further, Fig. 2(a) - (d) are just examples. The important point is the realization of a manufacturing method of forming polycrystalline silicon by solid phase recrystallization with large size grains from amorphous silicon formed by plasma CVD, which was considered difficult previously. (Although amorphous silicon films can be produced in quantities by plasma CVD and they can be applied in a large area, since the hydrogen content in the film is large and the hydrogen hinders solid phase recrystallization, it was thought that thus was not a desirable method for forming an amorphous silicon film on which solid phase recrystallization is to be performed.) Fig. 1(c) shows a process of forming a gate insulation film 104 by oxidizing said polycrystalline silicon layer 103 by thermal oxidation. The gate oxidation temperature is approximately 1,000°C to 1,200°C. Polycrystalline silicon layer 103 was formed by solid phase recrystallization described in the process (b), however, the crystallized volume fraction is not necessarily high. Especially, when a silicon film formed by plasma CVD (amorphous silicon or micro-crystalline silicon, which has minute crystal regions in the amorphous phase were generated) is formed by solid phase recrystallization, the crystallized volume fraction is low at approximately 40% to 85% (it varies depending upon the film growth condition and solid phase recrystallization). Our study confirmed, therefore, that in the case of oxidizing said polycrystalline silicon layer by thermal oxidation, if the temperature is raised to a high value of 1,000°C to 1,200°C suddenly in short time, crystallinity of the remaining (60% to 15%) amorphous regions is damaged. Presently, the relation of the cause and effect is not clear, however, some assumptions made are as follows: When the temperature is raised suddenly, (1) many crystal nuclei are generated in the amorphous region, thereby forming many minute crystal grains, (2) crystallization in the amorphous region during the process of temperature rise and thermal oxidation does not progress very much, (3) remaining hydrogen in the film suddenly removes during temperature rise causing defects, or the like. In order to solve these problems, we have invented means to substantially improve crystallinity of polycrystalline silicon layers by controlling the temperature rise speed and the method of raising the temperature to the thermal oxidation temperature of 1,000°C ∼ 1,200°C. Also, it was confirmed that the substrate temperature of a film formed by plasma CVD and the method of temperature rise at the time of gate oxidation have a profound relationship. That is, (1) the higher the substrate temperature is, the smaller the amount of hydrogen content in the film. When the substrate temperature is over 350°C, preferably over 400°C, hydrogen content in the film decreases extremely. Thus, the occurrence of defects associated with hydrogen removal during the temperature rise to the solid phase recrystallization temperature of 550°C to 650°C decreases. However, since the temperature at which hydrogen removes almost completely from the film shifts to a higher temperature compared to the case when a film is formed at low temperature, as it will be mentioned later in the text, it is very important to optimize the temperature rise speed, the method of temperature rise, and the like when the temperature is raised to the gate oxidation temperature of 1,000°C to 1,200°C. Also, since in the case of solid phase recrystallization performed on a film which was formed at the substrate temperature of over about 550°C, polycrystalline silicon or micro-crystalline silicon whose orientation is <110> can be obtained, it is effective in lowering TFT Si/SiO 2 interface state density and improving field effect mobility, and the like. (2) Since a large amount of hydrogen is contained in a film formed at the substrate temperature lower than around 350°C, it is, therefore, important to remove hydrogen in the film in order to avoid occurrence of many defects in the film before solid phase recrystallization at about 550°C to 650°C is performed. When hydrogen removal is performed under a desirable condition, there is a tendency that the lower the film growth temperature is, the larger the polycrystalline silicon grains will become. However, since the lower the temperature is, the lower the crystallized volume fraction after the solid phase recrystallization becomes, as it is described later in the text, it is important to optimize the temperature rise speed, the method of temperature rise, and so forth after the solid phase recrystallization. It became evident that performing thermal treatment after solid phase recrystallization at about 550°C to 650°C is effective for a thin film formed by other film growth methods besides plasma CVD. Particularly, this invention is very effective for the film with low polycrystalline nucleus generation density at the time of solid phase recrystallization (i.e., polycrystalline silicon with large grains can be easily obtained by solid phase recrystallization). An amorphous silicon film formed by plasma CVD contains less contaminants, e.g. oxygen (O), nitrogen (N), or carbon (C), compared to the amorphous silicon film formed by electron beam evaporation or LPCVD. Thus, a polycrystalline silicon film with high purity has been obtained by solid phase recrystallization on the amorphous silicon film by plasma CVD. Also, less contaminants in an amorphous silicon film makes it easy to promote solid phase recrystallization, which results in obtaining a polycrystalline silicon film with a large grain size. In particular, the amorphous silicon deposited at a temperature range of about 150°C to 350°C contains the lowest amount of contaminants which is derived from an insulating support, and a reactor chamber of PCVD. On the other hand, the amorphous silicon deposited at a temperature range of about room temperature to 150°C releases hydrogen easily by heat treatment, which makes heat treatment time short. The amount of C and O in an amorphous silicon formed by PCVD can be reduced to the order of 10E17 to 10E18 cmE-3. Particularly, it is also possible to reduce the amount of C and O to less than 10E16 by improving purity of gas source, and suppressing generation of contaminants for inner wall if the reactor chamber. As an example, a very important relationship between the film growth temperature of a film formed by LPCVD and the method of temperature rise at the time of gate oxidation is described hereinafter. When comparing a silicon layer formed at high temperature (for example, about 580°C to 610°C) to a silicon layer formed at low temperature (for example, about 500°C to 550°C), if the temperature rise to the gate oxidation temperature is sudden, the crystallized volume fraction of the silicon layer formed at low temperature is lower, and TFT field effect mobility is smaller. However, when the method of temperature rise explained above is employed, inversely, a silicon layer formed at low temperature formed larger grains and achieved higher crystallized volume fraction and higher field effect mobility. The suspected reasons are (1) a film formed at a low temperature of 500°C to 550°C by PCVD became amorphous silicon or micro-crystalline silicon containing minute crystalline regions in the amorphous phase. Therefore, compared to a film formed at high temperature, polycrystalline nucleus generation density at the time of solid phase recrystallization is lower and, therefore, polycrystalline silicon with large grains can be obtained by solid phase recrystallization, (2) however, crystalline quality was damaged in the film formed at low temperature when the temperature was raised suddenly at the time of gate oxidation because of the large amorphous phase ratio after the solid phase recrystallization. Therefore, the method explained above is effective in the following cases besides for a film formed by LPCVD and CVD: (1) in the case wherein amorphous silicon or micro-crystalline silicon is formed by vapor deposition, EB vapor deposition, MBE, sputtering, ECR-PCVD, or the like, (2) after micro-crystalline silicon, polycrystalline silicon, or the like is formed by plasma CVD, CVD, ECR-PCVD, vapor deposition, EB vapor deposition, MBE, sputtering, or the like and then ion implantion of Si, Ar, or the like is performed to form complete amorphous silicon or partially amorphous silicon from said micro-crystalline silicon or polycrystalline silicon. Especially, this method is effective for a film whose amorphous phase ratio of as-deposited film is high and polycrystalline nucleus generation density is low (i.e., polycrystalline silicon with large grains can easily be obtained by solid phase recrystallization). Next, thermal treatment conditions, in particular, the method of raising the temperature to a prescribed degree (for example, gate oxidation temperature) is described hereinafter. Fig. 3 shows graphic illustrations of examples of a temperature rise in one embodiment. Fig. 3(a) shows, as it was shown in Fig. 1(b), the case wherein annealing is performed in an inert gas atmosphere, such as argon, nitrogen, or the like at a prescribed temperature (T 1 ) to perform solid phase recrystallization on silicon layer 102 to form polycrystalline silicon layer 103, then gate oxidation is performed after the temperature is raised at a specified speed to the prescribed gate oxidation temperature (T 2 ). When the temperature rise speed from T 1 to T 2 is lower than about 20°C/min (preferably 5°C/min), it is desirable because the crystallized volume fraction after gate oxidation is high. There is another method wherein while the temperature is raised, the atmosphere is changed from an inert gas atmosphere, such as argon, nitrogen, or the like to the atmosphere containing at least one or more gas from oxygen, water vapor, hydrogen chloride, or the like to promote oxidation. (This method can be applied to the method described hereinafter.) The temperature rise speed need not be constantly the same, but it can fluctuate within the foregoing range. Also, there is another method wherein the sample is taken out after thermal treatment has been performed at T 1 and then again the temperature is raised to T 2 at a specified speed. For example, after solid phase recrystallization a sample is taken out once then placed into an oxidation chamber which is maintained at a prescribed temperature of 600°C to 900°C (preferably 600°C to 750°C). Then, the temperature is raised slower than by about 20°C/min (preferably 5°C/min), to the gate oxidation temperature. However, when thermal treatment was performed continuously without taking the sample out, crystalline quality was better because less impurity was introduced to the film. Fig. 3(b) shows, as it was shown in Fig. 1(b), the case wherein annealing is performed on silicon layer 102 for solid phase recrystallization at the prescribed temperature (T 1 ) in order to form polycrystalline silicon layer 103. Then, the temperature is raised to the gate oxidation temperature (T 2 ) at a speed becoming lower as the temperature becomes higher, and gate oxidation is performed. Especially, when the temperature exceeds the range of about 800°C to 1,000°C, the desirable temperature rise speed is lower than 5°C/min. On the other hand, when the temperature is lower than about 700°C, temperature rise can be faster than 10°C/min. Fig. 3(c) shows, as it was shown in Fig. 1(b), the case wherein annealing is performed at the prescribed temperature (T 1 ) on silicon layer 102 by solid phase recrystallization, and polycrystalline silicon layer 103 is formed. Then the temperature is raised to a prescribed value (T 2 ) at a prescribed temperature rise speed, and after it has been maintained for a certain time, the temperature is raised to the prescribed gate oxidation temperature (T 3 ). By maintaining the temperature T 2 lower than the gate oxidation temperature (T 3 ) for a certain time (for example, 10 min to 1 hour) the crystallization ratio can be raised without damaging the crystalline quality. Therefore, in the case when the temperature is raised to the gate oxidation temperature at a fast temperature rise speed after the temperature maintained at T 2 for a certain time, defects occur less likely. The desirable value of T 2 is in the range of about 700°C to 900°C. The prescribed temperature (T 2 ) need not be constantly the same. For example, the temperature can be raised slower than 5°C/min. Also, there may be stepwise change with a plurality of intermediate temperatures like T 2 . For example, after the temperature was maintained at about 700°C, it can be maintained again around 800°C. This is effective to lessen defects in the film. Fig. 3(d) shows the case wherein gate oxidation is performed after the temperature has been raised to the gate oxidation temperature (T 1 ) at a specified temperature rise speed. It contributes to shorten the process time because it does not need a special stage for solid phase recrystallization wherein the temperature need to be maintained at a specified level because solid phase recrystallization progresses while the temperature is raised. The desirable temperature rise speed is less than 5 to 10°C/min (preferably 2°C/min) to achieve a high crystallization ratio because solid phase recrystallization progresses while the temperature is rising. The temperature rise speed need not be fixed, but it can fluctuate within the foregoing range. Fig. 3(e) shows the case wherein gate oxidation is performed after the temperature has been raised to the gate oxidation temperature (T 1 ) at a speed becoming lower as the temperature becomes higher. Especially, when the temperature exceeds the range of about 700°C to 1,000°C, the desirable temperature rise speed is lower than 5°C/min (preferably 2°C/min), because the crystalline quality of polycrystalline silicon improves. On the other hand, when the temperature is lower than about 250°C, even if the temperature rise speed is faster than 40°C/min, there is almost no effect on the crystalline quality of polycrystalline silicon, therefore, it contributes to shorten the process time. Since in the range of about 300°C to 500°C hydrogen removal progresses, the desirable temperature rise speed is lower than 5 to 10°C/min (preferably 2°C to 4°C/min). Since in the range of about 500°C to 700°C solid phase recrystallization progresses, the desirable temperature rise speed is lower than 5°C/min (preferably 2°C/min). Also, it is possible to suppress occurrence of defects by combining a plurality of the Fig. 3(a) to (e) methods and improve crystalline quality and crystallization ratio. Fig. 3(a) to (e) are just examples. Fig. 1(d) shows a process of forming a semiconductor device. With reference to Fig. 1(d), the case wherein a TFT is formed as a semiconductor element is described as an example. In the figure, 104 is a gate insulator film, 105 is a gate electrode, 106 is a source/drain region, 107 is an interlevel insulator, 108 is a contact hole, and 109 is an interconnection. One example of forming a TFT is as follows: After a gate electrode has been formed, a source/drain region is formed by ion implantation, thermal diffusion, plasma doping, or the like, and an interlevel insulator is formed by CVD, sputtering, plasma CVD, or the like. Further, contact holes are made in said interlevel insulator, and interconnections are formed. In this embodiment, the case of performing gate oxidation is employed as an example of a high temperature thermal treatment. For example, it is sufficient to perform only a thermal treatment at a prescribed temperature (for example, about 700°C to 1,200°C) after raising the temperature at a specified temperature rise speed. In this case, the method of forming a gate insulation film is not limited to thermal oxidation, but CVD, sputtering, plasma CVD, ECR-PCVD, and the like are also good. However, in the case when a gate insulation film of an insulated gate type semiconductor element is formed by thermal oxidation, performing said thermal treatment also works as a thermal oxidation process contributing to shorten the process time. Further, by including a process of exposing a semiconductor element to a plasma atmosphere containing at least hydrogen gas or ammonia gas, in said TFT manufacturing process, and said TFT is hydrogenated, the defect density existing in grain boundaries decreases, and said field effect mobility improves even more. As described above, when a thin film transistor is manufactured employing a polycrystalline silicon thin film with large grains made of a boron doped amorphous silicon thin film by solid phase recrystallization, controlling the threshold voltage is realized by an easy process. The method of forming a doped polycrystalline silicon thin film with large grains by solid phase recrystallization during the film growth is also advantageous as a means to form materials for gate electrodes and interconnections. Based on Fig. 4, the description of an embodiment follows hereinafter employing a manufacturing method of a semiconductor device of this invention. In this embodiment, amorphous silicon is employed for a description purpose as an example of an amorphous semiconductor, however, amorphous Ge, amorphous SiGe, and the like can also be applied. Fig. 4(a) shows a process wherein an amorphous or polycrystalline silicon layer 502 is formed at a thickness of about 0.01 to 0.2 µm by plasma chemical vapor deposition (PCVD) low pressure chemical vapor deposition, (LPCVD), or the like over an insulating amorphous material 501. Then, etching is performed on this silicon layer to form a prescribed pattern, and if it is required solid phase recrystallization, laser annealing, or the like is performed to obtain larger grains either before or after forming the pattern. Next, an insulating film 503 comprising an SiO 2 layer is formed over the silicon layer at a thickness of about 0.03 to 0.15 µm by thermal oxidation, sputtering, or the like. Fig. 4(b) shows a process wherein an amorphous silicon layer 504 is formed over said SiO 2 layer at a thickness of about 0.3 to 0.7 µm by PCVD, ECR-PCVD, sputtering, Si ion implantation on a polycrystalline silicon thin film, or the like. PCVD is employed as an example for a description purpose in this embodiment. SiH 4 and H 2 gas are employed as the film growth gas in PCVD, and PH 3 gas or B 2 H 6 gas is employed as the doping gas. In the case PH 3 is employed, N + polycrystalline silicon can be formed, and in the case B 2 H 6 is employed, P + polycrystalline silicon can be formed. The substrate temperature was 180 to 250°C, the internal pressure was 0.8 Torr (107 Pa), and 13,56 MHz RF power was employed. The flux ratio of PH 3 or B 2 H 6 and SiH 4 was set so that the P or B concentration would be 1 x 10 16 to 1 x 10 22 cm -3 . Fig. 4(c) shows a process wherein the previously formed amorphous silicon layer 504 is formed to have the pattern of gate electrode 505, and then solid phase recrystallization is performed. The solid phase recrystallization can be performed before the pattern forming. The substrate under this condition is preannealed at 450°C for 30 minutes in N 2 to remove hydrogen contained in the amorphous silicon layer. The purpose of this step is to avoid producing a porous film because if solid phase recrystallization annealing is performed while the amorphous silicon contains hydrogen, the parts where hydrogen is removed become void. Also, there are various other types of thermal treatment before the solid phase recrystallization as shown in Fig. 2 besides the foregoing method. PCVD has a merit in that if the gas for film growth is diluted with He gas, the amount of hydrogen which will be introduced into the amorphous silicon layer can be reduced. After this step, solid phase recrystallization annealing is performed. The annealing is performed in N 2 gas at 550 to 650°C for several hours to 40 hours. The amorphous silicon layer becomes polycrystallized by this solid phase recrystallization annealing, and the average grain size of silicon in the gate electrode becomes about 1 to 3µm containing many of ≥ 5µm in size. Laser beam annealing, halogen lamp annealing, and the like are also good besides N 2 annealing. In the case laser beam or halogen lamp annealing is employed, the annealing time can be shortened compared to N 2 annealing. The P or B element, which was introduced during the film growth is activated in the annealing process concurrently. As a result, the resistivity of polycrystalline gate electrode 105 in both N + polycrystalline silicon and P + polycrystalline silicon becomes 1 to 3 x 10 -3 Ω·cm, and when it is compared to the resistivity of 2.5 x 10 -3 Ω·cm which is that of an N type doped gate electrode employing polycrystalline silicon formed by conventional LPCVD with an average grain size of ≤0.3 µm and not containing grains of ≥ 1µm at all, approximately the same level of resistivity can be obtained. Fig. 4(d) shows a process wherein a source region 508 and a drain region 507 are formed by implanting P + ions in the case of an N channel TFT and B + ions in the case of a P channel TFT, employing the gate electrode 505 as a mask. After this step, N 2 annealing is performed at about 800°C to 1,000°C so that the source and drain regions are activated. As a result of this annealing, B or P in gate electrode 105 is completely activated and an increase in crystallized volume fraction is achieved at the same time, and the resistivity of N + polycrystalline silicon and P + polycrystalline silicon lowers to approximately 1 x 10 -3 Ω·cm. ECR PCVD is also suitable for forming an amorphous silicon film for the gate electrode. The hydrogen content in an amorphous silicon layer formed by ECR-PCVD can be reduced, therefore, it has the advantage of omitting the preannealing process for hydrogen removal. It is also good to form the amorphous silicon layer by remote plasma CVD at a substrate temperature of over 370°C as is described in Journal of Noncrystalline Solids Vol. 107, P. 295 (1989) and the like. By following this method, hydrogen contained in an amorphous silicon layer can be removed almost completely, so it is more suitable for solid phase deposition. Fig. 4(e) shows a process of forming an interlevel insulator comprising an SiO 2 layer 509 by CVD, PCVD, sputtering, or the like. A silicon nitride film can also be employed as an interlevel insulator. At this stage, if hydrogen is introduced into the polycrystalline layer 502 by a hydrogen plasma method, hydrogen ion implantation, a hydrogen diffusion method from a plasma nitride film, or the like, then dangling bonds at Si/SiO 2 interface, grain boundaries, or the like, can be terminated by hydrogen atoms, providing the effect to decrease trap state density. This hydrogenation process can be performed before depositing the interlevel insulator. Fig. 4(f) shows a process wherein source and drain contact holes are made, and a metal film, for example, Al for interconnections is deposited by sputtering or the like at a thickness of about 0.8 µm to form source electrode 511 and drain electrode 510. Although an amorphous substrate, such as a quartz substrate was used in the foregoing description, the substrate could be crystalline, such as sapphire, CaF 2 , or the like. Fig. 5 and Fig. 6 show the characteristics of the TFT in the case p + polycrystalline silicon is employed for the gate electrode. Fig. 5 shows the characteristics of drain current versus gate voltage of an n channel TFT, and Fig. 6, that of a p channel TFT. In the case wherein p type polycrystalline silicon is employed for the gate electrode, the voltage for forming a flat band condition in the structure of gate electrode/insulator film/semiconductor becomes about 1V higher than in the case an n type polycrystalline silicon gate is employed. On the other hand, it is known that conventional hydrogenated non-doped polycrystalline silicon shows slightly n type characteristics. For this reason, when an n type polycrystalline silicon gate electrode was employed in an n channel TFT, the gate voltage which would cause the drain current to be minimum was about -1V (Fig. 5, 700). On the other hand, when a p type polycrystalline silicon gate electrode was employed, Vth shifted to a positive value, and the gate voltage which caused the drain current to be minimum was close to OV (Fig. 5, 701). In a p channel TFT, when n type polycrystalline silicon is employed as the gate electrode, the gate voltage which causes the drain current to be minimum is about -0.5V, however, even when a p type polycrystalline silicon gate is employed, the shift of Vth does not occur to the degree that the OFF current increases, therefore, good characteristics can be obtained (Fig. 6, 800). Thus, when a p type polycrystalline silicon gate electrode is employed, good TFT characteristics can be obtained in both p channel and n channel without increasing the number of processes. Therefore, channel doping which is inevitable when n + polycrystalline silicon is employed as a gate electrode becomes unnecessary.

Claims: A semiconductor device comprising CMOS type field effect transistors wherein the gate electrodes of both the P-channel and N-channel transistors are of polycrystalline silicon, characterized in that the transistors are thin film transistors having their drain, source and channel region formed from polycrystalline silicon with the channel region being undoped, and that said gate electrodes are of p + polycrystalline silicon containing grains of a size of ≥ 1 µm. The semiconductor device according to claim 1, wherein the grain size of said polycrystalline silicon is larger than 1 µm. The semiconductor device according to claim 1 or 2, wherein the resistivity of said polycrystalline silicon is in the range of 1 to 3 x 10 -3 Ω·cm. A method of manufacturing a semiconductor device as defined in claim 1, wherein forming of said gate electrodes comprises the following steps: first, forming a non-crystalline semiconductor layer mainly composed of silicon containing boron impurities of 1 x 10 16 to 1 x 10 22 cm -3 by plasma CVD, and then performing a thermal treatment for solid phase recrystallization of said non-crystalline semiconductor layer to said p + polycrystalline silicon.

Inventors: KUNII MASAFUMI, OKA HIDEAKI, TAKENAKA SATOSHI, KUNII, MASAFUMI, OKA, HIDEAKI, TAKENAKA, SATOSHI, KUNII, MASAFUMI, C/O SEIKO EPSON CORPORATION, OKA, HIDEAKI, C/O SEIKO EPSON CORPORATION, TAKENAKA, SATOSHI, C/O SEIKO EPSON CORPORATION
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, H01L21