Forming and removing polysilicon LDD spacers

Abstract: A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl₃ dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900°C in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer. The POCl₃ doping of the polysilicon layer increases the etch rate of the polysilicon, thus enhancing the selectivity of the etching of the polysilicon versus the oxide layer.

Description: The present invention generally relates to the fabrication of field effect transistors (FETs) having lightly-doped drain (LDD) regions; more particularly, to the formation and removal of LDD spacers. Lightly-doped drain (LDD) regions have commonly been used in reducing the length of the channel region in an FET, thereby reducing the size of transistor. The reduction in the length of the channel region is made possible by LDD regions which separate the source and drain regions from the channel region, and thus increase the channel breakdown voltage and reduce electron impact ionization (hot electron effects) by reducing the electric field at the source and drain pinch-off regions. A FET having LDD regions is typically fabricated in an active region of a substrate. The active region is bounded by field oxide (FOX) regions which electrically isolate the FET from other devices formed in the same substrate. Conventional processing techniques are utilized to implant regions at both ends of a gate with a light dose of an N/P-type dopant using the gate as a mask. Two N - /P - regions formed by the implant define a channel underlying the gate. (Either N-type or P-type dopants may be utilized, and the following discussion refers only to N-type dopants for convenience only. In some cases, where either N-or P-type dopants may be used, the dopant type will be noted as N/P.) A spacer material layer is formed over the entire structure and etched so that spacers remain at the ends of the gate. These spacers overlie portions of the N - /P - regions adjacent to the gate structures. Thereafter, a second implant is performed with a heavier dose of an N/P-type dopant to form N + /P + source and drain regions. During the second implant the spacers mask the underlying N - /P - regions. The N - /P - regions which do not receive the second implant become the LDD regions. Thus, the width of the spacers defines the width of the implanted LDD regions. The conventional manner of forming spacers is to perform a blanket etch of the spacer material layer. Because there are non-uniformities in the thickness of the spacer material layer, and because of non-uniformities of the etching rate over the entire wafer area, there are areas of the wafer where over-etching occurs and other areas where there is an incomplete removal of the spacer material layer. Conventionally, the spacer material layer is an oxide (usually a CVD oxide), and it is critical that the oxide layer be completely removed from the top of the gate and from the portions of the active region overlying the source and drain regions. However, when the strength of the etchant and the etching time are adjusted to assure complete removal of the oxide from the gate and S/D regions, the etchant often removes material from the field oxide regions. Typically, 1,000-2,000Å (10Å = 1nm) of the field oxide is removed. Removal of the field oxide, referred to as oxide loss, reduces the threshold breakdown voltage between the metalization layers and the substrate. Further, oxide loss results in a degradation of device isolation. Further, it is desirable to select an etching time which provides the proper width of the spacers, rather than basing the etching time on complete removal of the spacer material layer. While the channel breakdown voltage of a LDD FET and its ability to resist hot electron effects can be increased by increasing the width of the LDD regions, the LDD regions can increase the series resistance of the transistor channel and degrade the current drive capability of the FET. Consequently, it is important to control the fabrication process so that an optimum LDD width is achieved. One proposed method of reducing oxide loss is to form the spacer material layer from a thin layer of a thermal oxide, e.g., SiO 2 , (for protecting the substrate) and a thicker layer of polysilicon overlying the thermal oxide. The polysilicon layer is then etched with an etchant which has a much higher etch rate for polysilicon than for the silicon oxide to form the spacers at the ends of the gate. Because the etchant selectively etches polysilicon, the oxide layer protects the underlying FOX regions from etching, thereby reducing oxide loss. The fabrication of a semiconductor device having an LDD structure wherein lightly doped regions are formed in a semiconductor substrate by implantation using a gate as a mask, providing an oxide layer and a polysilicon layer over the substrate and the gate and etching the polysilicon layer to form spacers at the ends of the gate in known from DE-A-3 530 065. If the spacers are formed of an oxide, the spacers may be left in the device -- since the oxide is an insulator, the oxide does not disturb the electrical characteristics of the device. Polysilicon is conductive and must be removed before the device is completed. It is, however, very difficult to remove the polysilicon spacers after the N + /P + implant since the implant process forms a skin on the surface of the polysilicon; in the case of the P-type dopant boron, the skin is a boron skin. The device must then be exposed to the etchant for a period which is long enough for the etchant to penetrate the skin on the polysilicon spacers, usually a period which allows the etchant to penetrate the oxide layer protecting the source and drain regions and to remove a significant amount of oxide from the FOX regions. After penetrating the protective oxide layer, the etchant will attack the substrate in the source and drain regions, thereby destroying the device being fabricated. In Extended Abstracts/Spring Meeting Vol. 88-1, 15-20 May 1988, pp 207-208 there is disclosed a process for etching a polysilicon sidewall spacer for an LDDFET structure wherein the etching of the polysilicon terminates at the surface of a previously grown oxide, and wherein the polysilicon is deposited and doped before it is etched to form the spacer. After n + ion implantation, the polysilicon spacer is removed. During formation and removal of the spacer, the doped polysilicon is etched away faster then the oxide. According to the present invention there is provided a method of fabricating a semiconductor device having lightly doped source and drain regions, the method comprising implanting lightly doped regions in a substrate using a gate on the substrate as a mask, providing an oxide layer overlying the gate and the substrate, providing a doped polysilicon layer overlying the oxide layer, etching the doped polysilicon layer to form spacers at the respective ends of the gate, implanting source and drain regions through the oxide layer using the spacers to mask portions of the lightly doped regions, and removing the spacers by etching, characterized by rapid thermal annealing of the device after the source and drain regions are implanted and before the spacers are removed. The step of implanting source and drain regions damages the oxide, increasing the etch rate of the oxide layer and causing the oxide layer to be etched non-uniformly. The rapid thermal annealing cures the damage to the oxide layer while it forms only an extremely thin oxide skin on the polysilicon spacers, thereby reducing the etch rate of the oxide layer while maintaining the ability to etch the spacers more rapidly than the oxide layer. In the accompanying drawings, by way of example only: Figs. 1-4 are partial, sectional views useful for describing a process embodying the invention; and Figs. 5-8 are graphs useful for describing the beneficial effects of such a process. The process will be described with reference to the formation of a FET. A substrate (a wafer) 10 doped with a background of N-type impurities (e.g., phosphorous) is shown in Fig. 1. As discussed above, the dopants selected are for convenience and the method of the present invention applies to both enhancement mode and depletion mode devices. Using conventional fabrication techniques, field oxide regions 12 are formed on the wafer to define an active region 13, and a gate structure 14 is formed in active region 13. A P-type dopant is implanted to form lightly doped regions 16 1-2 . The implant dosage is selected so that lightly doped regions 16 1-2 have P - electrical characteristics. The P-type dopant used to implant LDD lightly doped regions 16 1-2 may be, for example, BF 2 , and the implant dosage may be, for example, 6x10 15 cm -2 . Portions of lightly doped regions 16 1-2 will become the LDD regions of the FET formed in active region 13. As shown in Fig. 2, a thin etch stop layer 18 (approximately 100-500Å) is formed over the active region 13 of substrate 10 and over gate structure 14. The etch stop layer may be a silicon oxide layer, which in the preferred embodiment is a thermal oxide formed using conventional oxidation techniques. The oxidation process does not form an oxide layer on field oxide regions 12; rather, a small amount of oxide is grown at the interface of field oxide regions 12 and substrate 10. A spacer material layer 20 is formed over oxide layer 18. The spacer material layer 20 is formed of polysilicon and has a thickness of 500-8000Å. After being deposited, polysilicon layer 20 is doped with an N-type dopant to achieve a resistivity of approximately 20-1000 ohms per square. The method of doping may be ion implantation or vapor phase diffusion. In the preferred embodiment, polysilicon layer 20 is doped in an atmosphere of POCl 3 gas at a temperature of approximately 875°C for approximately 30 minutes. Alternatively, spacer material layer 20 may be deposited as a doped layer by using a gas including PH 3 and silane (SiH 4 ) to form a phosphorous doped polysilicon layer by CVD. Polysilicon layer 20 is then etched until only spacers 24 1-2 remain at the ends of gate structure 14, shown in Fig. 3. Reactive ion etching (RIE) is one example of an etching process which may be used to etch spacer material layer 20. As shown in Fig. 4, after the formation of spacers 24 1-2 , an ion implantation is performed to form N + source and drain regions 26 1-2 The source/drain (S/D) implant is performed in accordance with conventional techniques, well known to those of ordinary skill in the art and may include a diffusion (or activation) of the implanted ions. During the S/D implant, spacers 24 1-2 serve as masks to prevent ion implantation in the portions of lightly doped regions 16 1-2 underlying spacers 24 1-2 . After the S/D implant, it is important to remove all of the remaining polysilicon material, i.e., spacers 24 1-2 . Any polysilicon which remains may create leakage currents which would detract from device performance. To remove spacers 24 1-2 it is desirable to perform a high-selectivity etching process which removes the polysilicon portions of spacers 24 1-2 without etching through oxide layer 18. Further, it is desirable that the etching process be isotropic. However, oxide layer 18 is damaged during the S/D implant which penetrates the oxide layer. The damage to the oxide layer increases the etch rate of the oxide layer making it difficult to assure that an etching process which selectively etches polysilicon and not a silicon oxide will have the same selectivity with respect to a damaged oxide of silicon. To cure (or repair the damage to) oxide layer 18, oxide layer 18 is annealed. In order to prevent oxidation during the annealing process, the anneal is an RTA process performed in an inert (non-oxidizing) atmosphere (nitrogen (N 2 ) or argon (Ar) in the preferred embodiment) for a time of less than approximately 100 seconds (20 seconds in the preferred embodiment) and at a temperature ranging from approximately 600°C to approximately 1200°C (900°C in the preferred embodiment). The time and temperature of the RTA process must be balanced -- a low temperature requires a longer processing time, whereas a higher temperature requires a shorter processing time. The RTA process may activate the ions implanted in the S/D implant to form source and drain regions 26 1-2 , eliminating the need for a separate activation step. After the RTA process, an etching process is performed to remove spacers 24 1-2 . The etchant is selected for its ability to selectively etch polysilicon at a much faster rate than silicon oxide. One example of such an etchant is a combination of nitric acid, acetic acid, hydrofluoric acid, and iodine. The etchant concentration is optimized to yield an etch time of approximately 30 seconds for control purposes. In particular, it is less advantageous to have a shorter etch time, i.e., a faster etch rate, which makes it more difficult to remove the structure from the etchant before the etchant penetrates oxide layer 18. The inventors have determined that an S/D implant using boron as a P-type dopant forms a "skin" on the polysilicon portions of spacers 24 1-2 . This skin is a boron-rich film which must be penetrated before the etchant can remove the polysilicon. Forming spacers 24 1-2 using polysilicon doped with an N-type dopant has proved to greatly reduce the effects of skin formation on polysilicon portions of spacers 24 1-2 during the boron S/D implant. To achieve the benefits of POCl 3 doping, the polysilicon must be doped with POCl 3 prior to the S/D implant. The benefits of doping the polysilicon and of the RTA process have been experimentally demonstrated, and will be discussed with reference to Figs. 5-8. For all of the experimental results discussed, etching was performed using an etchant comprising 1,300cc of nitric acid, 100cc of hydrofluoric acid, 5,600cc of acetic acid, and 2gm of iodine, an etchant which has a high selectivity for polysilicon over silicon oxide. Fig. 5 is a graph having curves I-V. Fig. 5 demonstrates the benefit of the RTA process of the subject invention. Curve I (□) shows the etching rate for a control sample of polysilicon which is not treated after formation, i.e., there is no doping, annealing, or RTA treatment of this sample. The fact that no etching of the polysilicon occurs for 40 seconds indicates that an oxide layer was present on the polysilicon. Curve II (o) shows the etching rate for a polysilicon sample subjected to an ion implantation with BF 2 , such as the S/D implant used to form source and drain regions 26 1-2 . Curve II demonstrates that the ion implantation forms a skin on the polysilicon layer and that the etchant does not penetrate this skin for approximately 90 seconds. Curve III (x) shows the etching rate for a polysilicon layer subjected to an S/D implant and then annealed in a furnace tube. An oxide layer formed on the polysilicon layer during the anneal, and thus the etchant did not penetrate the oxide layer for approximately 65 seconds. Curves IV (Δ) and V (▿) show the etching rates for polysilicon layers which were subjected to an S/D implant and then an RTA process for 20 seconds and 60 seconds, respectively, at 900°C in a nitrogen ambient. Curves III, IV and V demonstrate that the annealing improves the etch rate of polysilicon with respect to the control sample of polysilicon and with respect to a non-annealed polysilicon through which an implant was performed. Further, curves IV and V demonstrate that the RTA process forms a very thin skin on the polysilicon layer, and thus etching of the polysilicon commences within 20 seconds of exposure to the etchant. Fig. 6 illustrates the benefit of POCl 3 doping of polysilicon layer 20. Curve VI (□) shows the etch rate for a POCl 3 doped polysilicon layer through which a source or drain implant was performed, but which is not treated by annealing or an RTA process. The etch rate shown by curve VI is greater than 4600Å per minute. Curves VII (▿) and VIII (Δ) show the etching rates for polysilicon films which are not doped, through which an implant was performed, and which were subject to an RTA process for 20 seconds and 60 seconds, respectively. The etch rate for curves VII and VIII is approximately 1,300Å per minute. Curve IX (o) shows the etching rate for an undoped polysilicon film through which an implant is performed, and which is annealed for 30 minutes, at a temperature of 900°C, in an argon atmosphere in a furnace tube. The etching rate for curve IX is approximately 1,500Å per minute, and the anneal process formed an oxide skin on the polysilicon which prevented etching of the polysilicon for approximately 90 seconds. Curve X (x) shows that the etching rate for a polysilicon layer which is undoped and which is not subjected to an implant or an annealing process is approximately 800Å per minute. The etching rate of POCl 3 doped polysilicon is more than 3.5 times greater than undoped polysilicon. Fig. 7 shows the etching rates for four POCl 3 doped polysilicon films. Curve XI (□) relates to a POCl 3 doped control sample. Curve XII (o) relates to a POCl 3 doped polysilicon film which was subjected to an S/D implant. Curves XIII (Δ) and XIV (▿) relate to POCl 3 doped polysilicon films which were subjected to an implant and an RTA process of 20 seconds and 60 seconds, respectively. Fig. 8 demonstrates the benefits of the RTA process for curing an oxide layer damaged by the S/D implant. Curve XV (□) shows the etching rate for a control sample of plain oxide. Curve XVI (o) shows that the etching rate for an oxide which is subjected to an S/D implant is much higher than that of the control sample. The etching rate for an oxide subjected to an S/D implant and then annealed is shown by curve XVII (x), and the etching rates for oxide samples which are subjected to a source/drain implant and then an RTA process for 20 seconds and 60 seconds, respectively, are shown by curves XVIII (Δ) and XIX (▿). Clearly, the etch rate for the RTA processed, implanted oxides is lower than the etch rate for the non-cured (non-RTA processed) implanted oxide, and thus the etching selectivity for polysilicon versus the oxide is enhanced by the RTA treatment. The following table will be useful to understand how the experimental results demonstrate the benefits of the present invention. Curve # POCL 3 Implant Anneal RTA I, X No No No No II No Yes No No III, IX No Yes Yes No IV, VII No Yes No Yes V, VIII No Yes No Yes VI, XII Yes Yes No No XI Yes No No No XIII, XIV Yes Yes No Yes A comparison of curves II versus curve VI and of curve I versus curve XI shows the benefits of the POCl 3 doping. Etching of the POCl 3 doped polysilicon began much sooner than etching of the undoped polysilicon, indicating that the boron skin on the polysilicon is much thinner for a POCL 3 doped polysilicon. Further, the etch rate of a POCl 3 doped polysilicon is much larger than the etch rate of undoped polysilicon. Comparing curves IV and V versus curves XIII and XIV demonstrates that the POCl 3 doping increases the etch rate of the polysilicon. The many features and advantages of the method of the present invention will be apparent to those skilled in the art from the specification. The following claims are intended to cover all modifications and equivalents falling within the scope of the method of the invention.

Claims: A method of fabricating a semiconductor device having lightly doped source and drain regions, the method comprising implanting lightly doped regions (16 1 ,16 2 ) in a substrate (10) using a gate (14) on the substrate as a mask, providing an oxide layer (18) overlying the gate and the substrate, providing a doped polysilicon layer (20) overlying the oxide layer, etching the doped polysilicon layer to form spacers (24 1 ,24 2 ) at the respective ends of the gate, implanting source and drain regions (26 1 ,26 2 ) through the oxide layer (18) using the spacers (24 1 ,24 2 ) to mask portions of the lightly doped regions, and removing the spacers by etching, characterized by rapid thermal annealing of the device (18) after the source and drain regions (26 1 ,26 2 ) are implanted and before the spacers (24 1 ,24 2 ) are removed. A method according to claim 1 in which the polysilicon layer (20) is doped after the step of providing the polysilicon layer (20) using POCl 3 gas. A method according to claim 1 or claim 2, in which said rapid thermal annealing is for 10-100 seconds at a temperature of 600-1200°C in an inert atmosphere. A method according to claim 1, in which the substrate (10) has N-type background doping, the source and drain regions (26 1 ,26 2 ) are implanted with P-type dopant ions through the oxide layer (18), and the polysilicon layer (20) is doped with N-type dopant.

Inventors: HADJIZADEH-AMINI ZAHRA, HSU JAMES JUEN, SHEN LEWIS N, HADJIZADEH-AMINI, ZAHRA, HSU, JAMES JUEN, SHEN, LEWIS N.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L29