High frequency amplifier circuit capable of optimizing a total power consumption

Abstract: In a high frequency amplifier circuit comprising an input amplifier device (23) and an output amplifier (21) which are supplied with a total electric power of a supply current value variable dependent on a total power consumption in the input amplifier device and the output amplifier, a current detection circuit (30) detects the supply current value to produce a current detection signal representative of the supply current value. A bias voltage control circuit (31) controls a bias voltage of the output amplifier in response to the current detection signal to make the total power consumption have an optimum value. Preferably, the bias voltage control circuit should comprise a bias voltage generator (33) for generating a control voltage, a bias voltage controller (32) for producing a bias control signal dependent on the supply current value, and a modulator (34) for modulating the control voltage into a modulated voltage for use as the bias voltage.

Description: This invention relates to a high frequency amplifier circuit. In "Design Technique for Mobile Communication Devices" published on 10th January 1988 by Trikepps Inc., there is described at page 67 a high frequency amplifier circuit for producing an amplified output signal with automatic level control (ALC). The amplifier circuit is typically a radio frequency amplifier circuit and is particularly useful in a portable radio communication device. The amplifier circuit has a high frequency output amplifier supplied with a constant bias voltage for amplifying an intermediate amplified input signal to produce a circuit output signal which is the above-mentioned amplified output signal, the level of which is automatically controlled in a manner which will presently be described. A high frequency input amplifier device is connected to the output amplifier and amplifies a circuit input signal to produce the intermediate amplified signal, which it supplies to the output amplifier. The input amplifier device is supplied with the circuit output signal from the output amplifier, and operates to keep the circuit output signal at a predetermined output level. In this manner, automatic level control is carried out in the complete amplifier circuit comprising the input amplifier device and the output amplifier. The level of the circuit input signal is of course variable. The intermediate amplified input signal supplied to the output amplifier has a gain controlled level. The input amplifier device may consist of a single high frequency input amplifier for producing the intermediate amplified signal. Alternatively, the input amplifier device may additionally comprise at least one high frequency intermediate amplifier connected to the input amplifier to produce the intermediate amplified signal for delivery to the output amplifier. US-A-3514710 describes a radio frequency amplifier having a field effect transistor as the amplifying device, radio frequency input signal terminals at the ends of a radio frequency choke coupling the source of the transistor to ground, and an output broad band transformer having its primary grounded at one end and capacatively coupled to the drain of the transistor at its other end. Direct current for the drain-source circuit is supplied by a control circuit coupled through a radio frequency choke to the drain of the transistor. A detector senses the signal level across the primary of the output transformer and supplies a controlling signal to the control circuit, which also applies a bias signal to the gate of the transistor. The detector and control circuit co-operate to cause the direct current power supplied to the transistor to be a function of the input signal level. When used in a portable radio communication device, the amplifier circuit is supplied with the electric power usually from a battery unit. The input amplifier device is supplied with a portion of the electric power as an input amplifier power. The output amplifier is supplied with another portion of the electric power as an output amplifier power. The power consumed by the combination of the input amplifier device and the output amplifier should be kept as small as possible. This can be achieved by providing each of the input amplifier device and the output amplifier with a bias voltage control circuit. Use of such bias control circuits is, however, undesirable because the amplifier circuit then becomes expensive. It is therefore an object of this invention to provide a high frequency amplifier circuit which is capable of optimizing a total power consumption. It is another object of this invention to provide a high frequency amplifier circuit which is not expensive. According to the present invention there is provided a high frequency amplifier circuit comprising an input amplifier means for amplifying a circuit input signal to produce an intermediate amplified signal, an output amplifier means for amplifying the intermediate amplified signal to produce a circuit output signal, means for supplying power current to the input and output amplifier means, means for so coupling the circuit output signal to the input amplifier means as to determine the gain of the input amplifier means, and means for so supplying a bias voltage to the output amplifier means as to determine the gain of the output amplifier means, the circuit being such that the gain of the input amplifier means is determined by the circuit output signal to provide a predetermined circuit output signal level, characterised in that the means for supplying the said bias voltage includes a modulator for imposing a periodic modulation on the bias voltage and the means for supplying power current includes a current detection circuit that senses the combined current supplied to the amplifier means and in response thereto supplies to the bias voltage supplying means a current detection signal representative of phase and value of the combined current, and in that the bias voltage supplying means is such as to adjust the value of the bias voltage to optimise the power consumed by the amplifying means. The invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional high frequency amplifier circuit; Fig. 2 is a block diagram of a high frequency amplifier circuit according to a first embodiment of this invention; Fig. 3 is a graphical representation for use in describing first and second supply current values in an input amplifier device and an output amplifier shown in Fig. 2; Fig. 4 is a graphical representation for use in describing a current characteristic of a supply current value in the high frequency amplifier circuit shown in Fig. 2; Fig. 5 is a graphical representation for use in describing another current characteristic of a supply current value in the high frequency amplifier circuit shown in Fig. 2; Fig. 6 is a block diagram of a high frequency amplifier circuit according to a second embodiment of this invention; Fig. 7 is a block diagram of a high frequency amplifier circuit according to a third embodiment of this invention; Fig. 8 shows a partial circuit arrangement which is suitable for the high frequency amplifier circuit illustrated in Fig. 7; Fig. 9 illustrates signal waveforms for use in describing operation of the circuit arrangement illustrated in Fig. 8; and Fig. 10 illustrates signal waveforms for use in describing operation of the circuit arrangement illustrated in Fig. 8. Fig. 1 is a diagram of the high frequency amplifier circuit disclosed at page 67 of "Design Technique for Mobile Communication Devices" mentioned hereinbefore and will be described first in order to facilitate understanding of the present invention. The amplifier of Fig. 1 is typically a radio frequency amplifier circuit and is particularly useful in a portable radio communication device. The amplifier circuit amplifies a circuit input signal IN to produce a circuit output signal having a controlled output level. The amplifier circuit has a high frequency output amplifier 21 which comprises an output FET (field effect transistor) 21a supplied with a bias voltage Vgc of a constant level from a bias voltage supply unit (not shown). The output amplifier 21 further comprises first and second coupling capacitors 21b and 21c and a choke coil 21d. The output amplifier 21 amplifies an intermediate amplified signal to produce a circuit output signal the level of which is automatically controlled in a manner which will shortly be described. A high frequency input amplifier unit 22 is connected to the output amplifier 21 through the first coupling capacitor 21b and includes a high frequency input amplifier device 23 which comprises an input FET (not shown). As will later be described, the input amplifier unit 22 serves as an automatic level control (ALC) circuit. The input amplifier device 23 may consist of a single high frequency input amplifier for amplifying the circuit input signal IN to produce the intermediate amplified signal to deliver to the output amplifier 21. Alternatively, the input amplifier device 23 may additionally comprise at least one high frequency intermediate amplifier connected to the input amplifier to produce the intermediate amplified signal for delivery to the output amplifier 21. The input amplifier unit 22 further comprises an output level detection circuit 24 supplied with the circuit output signal from the output amplifier 21. The output level detection circuit 24 detects the circuit output signal to produce a d.c. voltage as a level detection signal representative of the output level. The level detection signal is sent to a comparator 25 which is supplied with a reference voltage signal (d.c. reference voltage Vs) from a reference voltage generator (not shown). The reference voltage signal is used in setting the circuit output signal at a predetermined output level. The comparator 25 compares the level detection signal with the reference voltage signal to produce a supply voltage control signal having a level representative of a result of this comparison. The supply voltage control signal is supplied to a supply voltage controller 26 which receives a supply voltage from a power supply unit (not shown) and outputs a controlled supply voltage determined by the supply voltage control signal. The input amplifier device 23 is supplied with the controlled supply voltage from the supply voltage controller 26 and causes the circuit output signal to produce the predetermined output level. It is to be noted here that the circuit input signal IN has a variable input level. The amplifier input signal of the output amplifier 21 has a gain controlled level. When used in the portable radio communication device, the amplifier circuit is supplied with the electric power from a battery unit used as the power supply unit. The input amplifier device 23 is supplied with a portion of the electric power through the supply voltage controller 26. The output amplifier 21 is supplied with another portion of the electric power through the choke coil 21d. The amplifier circuit is kept in operation with a total power consumption associated with the supplying of a certain supply current value. The total power consumption should be kept as low as possible. It is to be noted in this connection that the total power consumption is influenced by fluctuation of the gain controlled level. However, no consideration is given to compensating for the fluctuation of the gain controlled level. In other words, the output amplifier 21 cannot compensate for the fluctuation of the gain controlled level because the output FET 21a is supplied with the bias voltage Vgc which has a constant level. This means that the output amplifier 21 wastes power. Such a defect also applies to the input amplifier device 23. Consequently, the amplifier circuit has a degraded power consumption efficiency. The input FET and the output FET 21a have transistor characteristics which are different from each other. The power consumption efficiency of the amplifier circuit is influenced by the transistor characteristics. In order to optimize the power consumption efficiency, each of the input amplifier device and the output amplifier should include a bias voltage control circuit. The provision of such bias control circuits is, however, undesirable because the amplifier circuit then becomes expensive. Fig. 2 shows a high frequency amplifier circuit according to a first embodiment of this invention. The amplifier circuit comprises similar parts designated by like reference numerals and additionally a current detection circuit 30 and a bias voltage control circuit 31 for supplying bias voltage Vg to the ouput amplifier 21. In Fig. 2, the input amplifier device 23 and the output amplifier 21 in combination are supplied from the power supply unit with a combined supply current having a certain supply current value IS. The input amplifier device 23 is supplied with a portion of the electric power, referred to as the input amplifier power and associated with a first supply current value IS1, through the supply voltage controller 26. The output amplifier 21 is supplied with another portion of the electric power, referred to as the output amplifier power and associated with a second supply current value IS2. The current detection circuit 30 senses the combined supply current to produce a current detection signal reprsentative of the phase of a modulation of the supply current and the combined supply current value IS. As will presently be described in more detail, the bias voltage control circuit 31 produces the bias voltage Vg in response to the current detection signal in such a manner that the total power consumption has an optimum value. Referring to Fig. 3, it is assumed that the output level of the circuit output signal is kept at a predetermined output level by the automatic level control circuit 22 as mentioned before. In the example being illustrated, the first supply current value IS1 decreases as the bias voltage Vg increases. The second supply current value IS2 increases as the bias voltage Vg increases. The combined supply current value IS is a sum of the first and the second supply current values IS1 and IS2 and is defined by a current characteristic CC shown by a dashed-line curve. In this case, if the bias voltage Vg decreases, the output amplifier 21 amplifies the intermediate amplified signal with a low gain because the second supply current value IS2 decreases. However, the circuit input signal IN is amplified by the input amplifier device 23 with a high gain because the first supply current value IS1 is increased by operation of the automatic level control circuit 22. Thus the first supply current value IS1 increases when the second supply current value IS2 decreases. It is to be noted here that the combined supply current value IS is at a minimum value when the output amplifier 21 is supplied with a specific bias voltage Vg1 even though the output level is kept at the predetermined output level. The specific bias voltage Vg1 is defined by the first and the second supply current values IS1 and IS2 being equal to each other. In accordance with the invention, the bias voltage Vg is controlled by the bias voltage control circuit 31 in accordance with the current characteristics CC. Referring to Fig. 4, the current characteristic CC has a portion depicted in a left half of the current characteristic CC in which it descreases with an increase in the bias voltage Vg of the output amplifier 21. Another portion is depicted in a right half of the current characteristics CC in which it increass with the increase in the bias voltage Vg. An extremum is present between the descreasing and the increasing portions. If the bias voltage Vg is modulated by amplitude modulation, the combined supply current value IS varies with variation of the modulated bias voltage. For example, when the output amplifier 21 is supplied with the modulated bias voltage which is depicted at Vm1 and which is lower than the specific bias voltage Vg1, the combined supply current varies as depicted at 11 and has a first phase. Similarly, when the output amplifier 21 is supplied with the modulated bias voltage which is depicted at Vm2 and which is higher than the specific bias voltage Vg1, the combined supply current varies as depicted at I2 and has a second phase. It is to be noted here that the first phase leads by π radians relative to the second phase. The current detection signal indicates leading and lagging phases when the combined supply current varies as depicted a I1 and I2. When the output amplifier 21 is supplied with the modulated bias voltage which is depicted at Vm3, which is substantially equal to the specific bias voltage Vg1, the combined supply current varies as depicted at I3 with an amplitude of variation which is much smaller than the amplitudes at I1 and I2. The total power consumption has the optimum value when the output amplifier 21 is supplied with the modulated bias voltage Vm3 because the combined supply current value is then substantially equal to the minimum value. Turning back to Fig. 2, the bias voltage control circuit 31 comprises a bias voltage controller 32, a bias voltage generator 33, and a modulator 34. The bias voltage controller 32 is supplied with the current detection signal from the current detection circuit 30 and produces a bias voltage control signal having a bias voltage control level dependent on the combined supply current value IS. The bias voltage controller 32 comprises a phase detector (not shown) for detecting the phase represented by the current detection signal. Operation of the bias voltage controller 32 will now be described in detail. By detecting the phase represented by the current detection signal, the bias voltage controller 32 determines whether the combined supply current value IS is in the decreasing (left) or the increasing (right) portions of the current characteristic CC (Fig. 4). When the combined supply current value is in the decreasing portion, the bias voltage controller 32 produces a bias voltage control signal which serves to increase the bias voltage Vg up to the specific bias voltage Vg1. Conversely, the bias voltage controller 32 produces a bias voltage control signal which serves to decrease the bias voltage Vg down to the specific voltage Vg1, when the combined supply current value IS is in the increasing portion of CC. In this manner, the bias voltage controller 32 produces the bias voltage control signal that tends to hold the combined supply current value IS at the minimum value. The bias voltage generator 33 generates a control voltage which is controlled by the bias voltage control signal. The control voltage is supplied to the modulator 34. As will later be described in more detail, the modulator 34 comprises a pulse generator (not shown) for generating a pulse signal and modulates the control voltage by using the pulse signal. The modulator 34 supplies the modulated voltage for use as the bias voltage to the output amplifier 21. Thus, the total power consumption is kept at the optimum value. A gallum-arsenide type FET may be used as the output FET 21a. When the supply voltage is 6 volts high, the input amplifier device 23 is given a constant bias voltage of minus 4 volts. The bias voltage Vg is controlled between minus 1.5 volts and minus 4 volts. When a circuit input signal of 5 milliwatts reaches the amplifier circuit, the circuit output signal should be 30dBm. It should be noted in general that the battery unit has a restricted voltage. The first supply current value IS1 is restricted to a predetermined value when the output level of the circuit output signal should keep a high level. Referring to Fig. 5, let the first supply current value be restricted to predetermined values exemplified by IS1′. The current characteristic CC′ represents the supply current value which is a sum of the first and the second supply current values IS1′ and IS2. The current characteristic CC′ has a restricted portion deviating from the corresponding portion of the current characteristic CC that is shown by a dashed line. When the first supply current value IS1′ is restricted, it is difficult to keep the output level at the predetermined output level. Moreover, if the bias voltage Vg is reduced down to a prescribed bias voltage Vg2 which corresponds to a supply current value IVa located between the restricted portion and the decreasing portion of the current characteristic CC′, the bias voltage control circuit 31 may operate so as to reduce the bias voltage Vg. This means that the bias voltage control circuit 31 falls into an uncontrollable state. This is because the bias voltage control circuit 31 fails to distinguish the supply current Iva in the restricted portion from a supply current value Ivb in the increasing portion. Under the circumstances, the bias voltage Vg should be kept at the prescribed voltage Vg2 when the first supply current value IS1′ is restricted at the predetermined value. Referring to Fig. 6, the description will proceed to a high frequency amplifier circuit according to a second embodiment of this invention. The amplifier circuit is similar to the amplifier circuit illustrated in Fig. 2 except that a bias voltage control circuit 40 is used instead of the bias voltage control circuit 31. The bias voltage control circuit 40 includes a signal level detection circuit 41 and a subsidiary control circuit 42 in addition to the bias voltage controller 32, the bias voltage generator 33, and the modulator 34. The bias voltage controls circuit 40 keeps the bias voltage Vg at the prescribed bias voltage Vg2 when the first supply current value IS1′ is restricted to the predetermined value. When the first supply current value IS1′ is restricted to the predetermined value, the comparator 25 produces a supply voltage control signal having a control signal level which is higher than a predetermined control level and this causes the supply voltage controller 26 to supply the input amplifier device 23 with a supply voltage of a maximum level. The signal level detection circuit 41 detects whether or not the control signal level is lower than the predetermined control level. The signal level detection circuit 41 delivers a detection signal to the subsidiary control circuit 42 when the control signal level is not lower than the predetermined control level. Supplied with the detection signal, the subsidiary control circuit 42 stops supply of the bias voltage control signal to the bias voltage generator 33 to keep the bias voltage Vg at the prescribed bias voltage Vg2. Namely, the bias voltage generator 33 supplies the control voltage to the modulator 34 with a predetermined voltage on blocking of the bias voltage control signal. The modulator 34 modulates the control voltage for use as the prescribed bias voltage Vg2. The detection signal may be supplied to be modulator 34. In this event, the modulator 34 stops modulation of the control voltage on reception of the detection signal and produces the control voltage as it stands for use as the prescribed bias voltage Vg2. If the first supply current value IS1′ is lower than the predetermined value, namely, if the control signal level is lower than the predetermined control level, operation of the bias voltage control circuit 40 is similar to that of the bias voltage control circuit 31. Fig. 7 shows a high frequency amplifier circuit according to a third embodiment of this invention. The amplifier circuit is similar to the amplifier circuit illustrated in Fig. 6 except that a bias voltage control circuit 50 is used instead of the bias voltage control circuit 40. The bias voltage control circuit 50 comprises a ratio detection circuit 51 instead of the signal level detection circuit 41 illustrated in Fig. 6. The ration detection circuit 51 is supplied with the supply voltage and the reference voltage. It is to be noted here that the first supply current value IS1′ is restricted when the comparator 25 is supplied with a high reference voltage in order to increase the first supply current IS1′, namely, in order to keep the output level at a high level, although the supply voltage is low. By detecting the ratio of the reference voltage to the supply voltage, it is possible to detect whether or not the first supply current value IS1′ is restricted. Supplied with the supply voltage and the reference voltage, the ratio detection circuit 51 detects the ratio of the reference voltage to the supply voltage. The ratio detection circuit 51 delivers a ratio detection signal to the subsidiary control circuit 42 when the ratio is not higher than a predetermined ratio. Supplied with the ratio detection signal, the subsidiary control circuit 42 stops supply of the bias voltage control signal to the bias voltage generator 33 to keep the bias voltage Vg at the prescribed bias voltage Vg2. The bias voltage generator 33 supplies the control voltage to the modulator 34 with the predetermined voltage on blocking of the bias voltage control signal. The modulator 34 modulates the predetermined voltage for use as the prescribed bias voltage Vg2. If the ratio is higher than the predetermined ratio, operation of the bias voltage control circuit 50 is similar to that of the bias voltage control circuit 40 illustrated in Fig. 6. Referring to Figs. 8, 9 and 10, the description will proceed to a circuit arrangement which is suitable for use in the high frequency amplifier circuit illustrated with reference to Fig. 7. In Fig. 8, the supply voltage controller 26 comprises a first operational amplifier OP1 supplied with the supply voltage control signal from the comparator 25 through a non-inverting input terminal. A first transistor TR1 is connected to an output terminal of the first operational amplifier OP1. A second transistor TR2 is supplied with the supply voltage through the current detection circuit 30. In the manner known in the art, the supply voltage controller 26 controls the supply voltage by the use of the supply voltage control signal and supplies a controlled supply voltage to the input amplifier device 23. The current detection circuit 30 is supplied with the electric power through a first resistor R1. The first resistor R1 develops a voltage that is dependent on the supply current value IS. The supply current value IS varies as illustrated in Fig. 9(a) when the supply current value IS is in the decreasing portion of the current characteristic CC′ shown in Fig. 5. The supply current value IS varies as illustrated in Fig. 10(a) when the supply current value IS is in the increasing portion of the current characteristic CC′. It is to be noted here that the phase of the supply current value IS shown in Fig. 9 (a) is different from the phase of the supply current value IS shown in Fig. 10(a). In the current detection circuit 30, the variation of the voltage across the resistor R1 is detected at a point P1 through a first capacitor C1. The first capacitor C1 detects the variation of the supply current value IS as variation of a charged voltage. By the use of a second operational amplifier OP2 connected to the first capacitor C1 through a second resistor R2, the variation of the charged voltage is amplified and the amplified voltage is generated at a point P2. The amplified voltage is illustrated in Figs. 9(b) and 10(b) and is supplied, as the current detection signal, to the bias voltage controller 32. The amplified voltage has an inverse phase relative to the phase of the supply current value IS because the phase of the supply current is inverted by the second operational amplifier OP2. Thus, the current detection circuit 30 detects the variation of the supply current value in the form of the variation of the voltage at the point P1. The bias voltage controller 32 comprises an inverting amplifier AM1, first and second switching circuits SW1 and SW2, and an integrating amplifier AM2. The inverting amplifier AM1 is supplied with the amplified voltage through a third resistor R3 and is connected to the first switching circuit SW1. The inverting amplifier AM1 has an amplification factor equal to unity and produces an inverted voltage having an inverted phase relative to the phase of the amplified voltage. The inverted voltage is generated at t point P3 and is illustrated in Figs. 9(c) and 10(c). The first switching circuit SW1 is connected to the inverting amplifier AM1 and the integrating amplifier AM2 and is controlled by the pulse signal supplied from the modulator 34 which will later be described. The second switching circuit SW2 is connected to the second operational amplifier OP2 and the integrating amplifier AM2 and is controlled by the pulse signal through a first inverter IV1. As a result, the first switching circuit SW1 is turned on and turned off and the second switching circuit SW2 is turned off and on in synchronism with the pulse signal. When the supply current value IS is in the decreasing portion of the current characteristic CC′, the switching circuits SW1 and SW2 supply a positive-going full wave rectified waveform of the amplified voltage to the integrating amplifier AM2. The positive-going full wave rectified waveform is generated at a point P4 and is illustrated in Fig. 9(d). When the supply current value IS is in the increasing portion of the current characteristic CC′, the switching circuits SW1 and SW2 supply a negative-going full wave rectified waveform of the amplified voltage to the integrating amplifier AM2. The negative-going full wave rectified waveform is generated at the point P4 and is illustrated in Fig. 10(d). The inverting amplifier AM1 and the first and the second switching circuits SW1 and SW2 may be collectively called a phase detector because the positive-going and the negative-going full wave rectified waveforms are delivered in accordance with the phase of the supply current. When the supply current value IS is in the decreasing portion of the current characteristic CC′, the integrating amplifier AM2 integrates the positive-going full wave rectified waveform. The integrating amplifier AM2 produces an integrated voltage signal, as the bias voltage control signal. In the manner depicted in Fig. 9(e), this integrated voltage signal grows from a reference level Vr indicated by a dashed horizontal line and may herein be referred to as an increasing voltage signal. The increasing voltage signal is generated at a point P5 and serves to raise the bias voltage Vg up to the specific bias voltage Vg1. On the other hand, the integrating amplifier AM2 integrates the negative-going full wave rectified waveform when the supply current value IS is in the increasing portion of the current characteristic CC′. The integrating amplifier AM2 produces another integrated voltage signal, as the bias voltage control signal. In the manner depicted at Fig. 10(e), the latter integrated voltage signal decreases from the reference level and may herein be referred to as a decreasing voltage signal. The decreasing voltage signal is generated at the point P5 and serves to decrease the bias voltage Vg down to the specific bias voltage Vg1. The ratio detection circuit 51 comprises a third operational amplifier OP3 and a first voltage dividing circuit 51a supplied with the supply voltage. The third operational amplifier OP3 is supplied with the reference voltage Vs and a divided supply voltage produced by the first voltage dividing circuit 51a. As described before, the ratio detection circuit 51 detects the ratio of the reference voltage to the supply voltage and delivers the ratio detection signal to the subsidiary control circuit 42 when the ratio is not higher than the predetermined ration, namely, when the high reference voltage is supplied to the comparator 25, although the supply voltage is low. The subsidiary control circuit 42 comprises a third switching circuit SW3 supplied with the bias voltage control signal and a second voltage dividing circuit 42a supplied with a driving voltage Vdd. When supplied with the ratio detection signal, the third switching circuit SW3 stops supply of the bias voltage control signal to the bias voltage generator 33 and supplies the divided driving voltage from the second voltage dividing circuit 42a. The bias voltage generator 33 comprises a fourth operational amplifier OP4. The fourth operational amplifier OP4 converts whichever one of the bias voltage control signal and the divided driving voltage is supplied into a converted voltage dependent on operation of the third switching circuit SW3. The converted voltage is used as the control voltage. The modulator 34 comprises a pulse generator 34a and a differentiation circuit 34b comprising a fifth operational amplifier OP5 supplied with the control voltage from the bias voltage generator 33. The pulse generator 34a generates the pulse signal illustrated in Figs. 9(f) and 10(f). The pulse signal is supplied to an inverting input terminal of the differentiation circuit 34b through a second inverter IV2. The differentiation circuit 34b modulates the control voltage with the pulse signal into the modulated signal for use as the bias voltage Vg. At a point P6, the modulated signal rises up to the specific bias voltage Vg1 from the state shown in Fig. 9(g) when the supply current value IS is in the decreasing portion of the current characteristic CC′. On the other hand, the modulated signal is decreased down to the specific bias voltave Vg1 from the state shown in Fig. 10(g) when the supply current value IS is in the increasing portion of the current characteristic CC′. The pulse signal should have a frequency which is lower than that of an information signal carried by the circuit input signal. When an audio signal is carried by the circuit input signal, the pulse signal should preferably have a frequency selected between 50 and 60 Hz. While this invention has thus far been described in conjunction with a few embodiments thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the pulse generator 34a may be placed in the bias voltage controller 32 rather than in the modulator 34. In this event, the pulse signal is supplied to the modulator 34 from the bias voltage controller 32.

Claims: A high frequency amplifier circuit comprising an input amplifier means (23) for amplifying a circuit input signal (IN) to produce an intermediate amplified signal, an output amplifier means (21) for amplifying the intermediate amplified signal to produce a circuit output signal, means for supplying power current (IS) to the input and output amplifier means, means (24,25,26) for so coupling the circuit output signal to the input amplifier means (23) as to determine the gain of the input amplifier means (23), and means for so supplying a bias voltage (Vg) to the output amplifier means (21) as to determine the gain of the output amplifier means (21), the circuit being such that the gain of the input amplifier means (23) is determined by the circuit output signal to provide a predetermined circuit output signal level, characterised in that the means (31) for supplying the said bias voltage (Vg) includes a modulator (34) for imposing a periodic modulation on the bias voltage (Vg) and the means for supplying power current (IS) includes a current detection circuit (30) that senses the combined current (IS) supplied to the amplifier means (21,23) and in response thereto supplies to the bias voltage supplying means (31) a current detection signal representative of phase and value of the combined current (IS), and in that the bias voltage supplying means (31) is such as to adjust the value of the bias voltage (Vg) to optimise the power consumed by the amplifying means (21,23). A circuit according to claim 1, characterised in that the bias voltage supply means (31) includes a bias voltage controller (32) coupled to the current detection circuit (30) and responsive to the current detection signal to produce a bias voltage control signal having a level representative of the phase and value of the combined current (IS), and means (33) for so coupling the bias voltage controller (32) to the modulator (34) as to generate the modulated bias voltage (Vg). A circuit according to claim 1 or 2, characterised in that the means for coupling the circuit output signal to the input amplifier means (23) comprises an output level detection circuit (24) so coupled to the output amplifier means (21) as to produce a level detection signal representative of the circuit output signal level, a comparator (25) coupled to the output level detection circuit (24) to receive the level detection signal and so compare the level detection signal with a reference voltage (Vg) as to produce a voltage control signal having a level representative of the result of the comparison, and a supply voltage controller (26) so coupled between the comparator (25), the current detection circuit (30) and the input amplifier means (23) as to determine the portion of the combined current (IS) supplied to the input amplifier means (23). A circuit according to claims 2 and 3, characterised in that a signal level detection circuit (41) is connected to the comparator (25) and detects whether or not the level of the said voltage control signal is lower than a predetermined control level and produces a detection signal when the voltage control signal is not lower than the predetermined control level, and the said means for coupling the bias voltage controller (32) to the modulator (34) includes a subsidiary control circuit (42) connected to the signal level detection circuit (41) and responsive to the detection signal to substitute a set bias voltage control signal for the bias voltage control signal supplied by the bias voltage controller (32). A circuit according to claims 2 and 3, characterised in that a ratio detector circuit (51) is connected to the said means for supplying power current (IS) and sensing the ratio of the said reference voltage (Vg) to a voltage established by the said power current supplying means and produces a detection signal when the ratio is not higher than a predetermined ratio, and the said means for coupling the bias voltage controller (32) to the modulator (34) includes a subsidiary control circuit (42) connected to the ratio detector circuit (51) and responsive to the detection signal to substitute a set bias voltage control signal for the bias voltage control signal supplied by the bias voltage controller (32).

Inventors: MIYAZAKI SHINICHI C O NEC CORP, MIYAZAKI, SHINICHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: H03F1
IPC codes: H03F1, H03F3, H03G3