BIPOLAR TRANSISTOR AND METHOD FOR THE MANUFACTURE THEREOF

Abstract: A method for producing a bipolar transistor which is highly reproducable, provides a high yield and does not need a very high vacuum.

Description: BIPOLAR TRANSISTOR AND METHOD FOR THE MANUFACTURE THEREOF In VSLI (Very Large Scale Integration) technique bipolar transistors are coming in for renewed attention, especially as switching transistor and for controlling logic wherein high speed and/or a relatively great capacity are necessary. For these purposes bipolar transistors are more suitable than FETs (Field Effect Transistors). The present invention has for its object to provide a method wherein bipolar transistors with relatively small dimensions, for example in the sub-micron region, can be manufactured in comparatively simple and/or elegant manner, the yield of a production process is high, the reproducibi- lity of the bipolar transistors is great and/or connections between the transistors in an integrated circuit can be established in an easy manner. Existing methods for manufacturing thin layers make use of MBE (Molecular Beam Epitaxy) ; these techniques require an extremely high vacuum (10 "8 Pa) and produce a very low yield because of the low growth rate. Further features, advantages and details of the present invention will be elucidated on the basis of a des¬ cription of a preferred embodiment thereof, with reference to the annexed drawing, wherein: fig. 1-10 respectively show consecutive cross sections of (a portion of) a substrate wherein according to method steps according to the invention a bipolar transistor according to the present invention is manufactured. In a wafer or substrate 1 (fig. 1) of the p-type a buried region 2 - of which an epitaxial low layer (not shown) usually forms part - doped with Sb or As is arranged, prefer- ably by means of ion implantation. Oxidized regions 3, 4 and 5 (fig. 2) are subsequently applied hereto in likewise known manner, which regions define, as will later become apparent, regions for emitter, base and collector. A p-type doped epitaxial region 6 of silicon is then arranged between and partially over the oxide regions 3, 4 using VLPCVD (Very Low Pressure Chemical Vapour Deposition) technique, which technique is described for example in the European Patent publication 0 259 759 in the name of the International Business Machines Corporation, but which can also be performed in a manner other than described therein. Because of the low temperature (less than 1,000°C, preferably lower than 800°C) and the low pressure (less than, for ex¬ ample, 1.5 x 10 "4 mbar), an accurately defined junction is obtained wherein the epitaxial layer as base layer can be extremely thin (0.1-0.5 m) . The crystalline structure of the buried region is taken over into the portion of the region thereabove; polycrystalline silicon occurs above the oxide regions. During etching at the sides of the layer 6 an etching away of the buried layer takes place at the upper surface 7 between the oxidized regions 4 and 5, as can be seen in fig. 3. Subsequently, using known art (fig. 4) , a region 9 of nitride (Si 3 N 4 ) is applied approximately centrally on the epitaxial layer 6 as well as a region 8 of nitride between the insulating regions 4 and 5. The region or the layer 6 is then provided with an oxidized insulation layer 11 except at the location of the nitride region 9 (fig. 5). The oxide layer 11 on either side of the nitride region 9 has a bird beak-like shape, the purpose of which will become apparent hereinafter. The epi- taxial region 6 is doped by ion implantation (indicated schematically with the arrows 12), except for directly under the nitride region 9. The non-doped portion of the region 6 can thus serve as (intrinsic) base. Subsequent thereto the nitride layer is removed (fig. 7) in known manner. Hereafter, regions 13, 14 of epitaxially grown silicon are arranged for the formation of emitter and collec- tor regions. These emitter and collector regions are doped using ion implantation (arrows 16), for example with As. Polycrystalline silicon occurs above the bird beak-like protrusions. Following this (fig. 8) the side portions of the insulating regions 11 are etched away, whereby the bird beak¬ like protrusions 17 remain behind. This etching step can be performed accurately because of the transition between the insulating region 11 and the epitaxial layer 6, while lateral accuracy, that is, in the direction along the upper surface of the substrate, does not gives rise to problems; etching in the intrinsic base does not take place. In the following step (fig. 9) the n-type regions 13, 14 are provided at the sides with insulating spacers 21, 22, 23 and 24. Finally, conducting contacts (fig. 10) are arrang¬ ed, preferably of silicide. The contacts 26 and 27 form the base contacts while contacts 28 and 29 serve for the collec¬ tor and the emitter, wherein these contacts can be arranged directly in an integrated circuit. The method described and the bipolar transistor thus manufactured comprise the following advantages: - the process is relatively simple; the contact between connection contacts for the base and the intrinsic base is direct, while the base can have an extremely small thickness; - the emitter, base and collector contacts can also be used for connection between the different transistors for an integrated circuit; there are no contacts present in the active region, which results in a small active transistor and prevents diffusion of metal in the shallow junctions; - the division between intrinsic and extrinsic base is self-aligning; - the thickness of the collector, base and emitter layer can be controlled extremely accurately; and - a packing density of 4 to 5 million transistors per cm 2 can be achieved.

Claims: CLAIMS 1. Method for manufacturing a bipolar transistor, comprising the following steps of: - arranging in a substrate a buried, doped first region with a determined conductivity; - arranging thereon oxidized regions which define active regions; - arranging epitaxially thereon a second region with a conductivity opposed to that of the first region, at a temperature lower than approximately 1,000°C and at a pressure lower than approximately 1.5 x 10 " " mbar; - arranging in alignment with the second region of a third region with the first stated conductivity; and - applying conductive contact layers. 2. Method as claimed in claim 1, wherein insulating spacers are arranged at the sides relative to the third region. 3. Method as claimed in claim 1 or 2, wherein the epitaxial second layer is doped by means of ion implantation. 4. Bipolar transistor manufactured according to the method as claimed in any of the claims 1, 2 or 3. 5. Bipolar transistor as claimed in claim 4, where¬ in the second region has a breadth of less than 0.5 m and forms the base region. 6. Bipolar transistor as claimed in claim 4 or 5, provided with insulating spacers which are arranged at the sides relative to the second region. 7. Bipolar transistor provided with a junction between base and emitter, wherein the emitter comprises bird beak-like insulating portions. 8. Bipolar transistor provided with insulating spacers which are arranged laterally relative to the emitter and which insulate the base contact of the emitter.

Inventors: DEFERM LUDO XAVIER JOSEPH, NIJS JOHAN FRANCIS ALBERT, DEFERM, LUDO, XAVIER, JOSEPH, NIJS, JOHAN, FRANCIS, ALBERT
Applicants: IMEC INTER UNI MICRO ELECTR, INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW
Application year: 1990
Main classification: H01L29
IPC codes: H01L21, H01L29