Solid state image sensing device and method of manufacturing the same

Abstract: In a solid state image sensor device including photoelectric conversion elements and charge transfer devices, an impurity layer (21) constituting a surface layer formed on each of the charge storage layers (22) of the photoelectric convertion elements extends in the lateral direction of the semiconductor layer (9) so that, when viewed from stop, an end of the surface impurity layer coincides with an end of a transfer electrode (10) of each of the charge transfer devices and serves as an isolation layer, thereby obviating problems associated with the degradation of performance of the sensor device due to expansion of the isolation layer in thermal diffusion.

Description: This invention relates to a solid state image sensing device and a method of manufacturing the device, and more particularly, to a highly integrated solid state image sensing device and a method of making such a device. A plan view of a part of a prior art solid state image sensing device is shown in Fig. 1, wherein the reference numeral 1 is a first transfer electrode and 2 a second transfer electrode, which are generally of a two layer structure of polysilicon layers, which in Fig. 1 are shown in the form of a single layer for the sake of brevity. The hatched areas 3 indicate isolation regions, 4 indicates a photoelectric conversion element and 5 indicates a charge transfer channel region. As an aid in understanding the structure, a cross section of the device taken along the line XII - XII of Fig. 1 is shown in Fig. 2. Each channel region 5 is generally formed of an N-type impurity layer and serves as a buried channel known in the art. The photoelectric conversion element 4 is in the form of a buried region formed by covering the surface of an N + type impurity layer 7 with a P + type impurity region 6. This arrangement permits the surface region of the N + type impurity layer 7 to be maintained in a non-depleted state to render inactive carriers that are present in the interface. The significance of this is that the dark current is greatly decreased. The isolation region 3 is formed of a P + type impurity layer and electrically isolates the layer 7 from the layer 5 lying at one side thereof. No isolation layer 3 is formed, but a charge readout channel 15 is formed, between each layer 7 and layer 5 lying at the opposite side thereof. The charge readout channel 15 is controlled by the voltage of the electrode 2 and transfers signal charges (electrons) from the layer 7 to the layer 5. Numeral 8 indicates an N type substrate, 9 a P type well layer, 10 light shield films for preventing image light from being incident to the charge transfer devices, and 11 an insulating film. In the conventional structure, to ensure that the P layer 3 is positively overlapped with an end of each electrode 2 even when a masking deviation occurs in the manufacturing steps, an allowance of 0.5-1.0 µm in the lateral direction of the layer 3 is provided for compensating the deviation. Thus, the P layer 3 is formed prior to the formation of each electrode 2. Device performance, on the other hand, is determined by the abilities of the photoelectric conversion elements and the charge transfer devices, and is enhanced virtually in proportion to their areas lying in the horizontal plane. That is, the area of the layer 7 need to be increased to attain high sensitivity, and the N layer 5 need to be broadened to implement a wide dynamic range (a large maximum amount of signal charge). It therefore is required that the isolation layer 3 be formed as narrow as possible in width. In forming the isolation layer 3, a P type impurity is implanted into a substrate by lithographic techniques using a resist pattern having been patterned to the possible minimum size. The implanted impurity, however, is thermally diffused in a subsequent thermal step to finally render the isolation layers 3 to occupy broad regions 12. For example, the P type layer formed with 1.0 µm width by use of a resist pattern of a 1.0 µm size is expanded to a 2.0 µm width after the heating step. The structure shown in Figs. 1 and 2 requires the formation of P layers 3 at both sides of the photoelectric conversion element. If the above method is applied to this structure, the width of the isolation layer 3 formed after the thermal step by a lithographic technique of a minimum width of 1.0 µm results in 2 µm required at each side of the conversion element and hence totally amounts to 4 µm. This is obviously against the goal of achieving high integration (a number of pixels) in the fabrication of solid state image sensors. EP-A-0 410 465 forming prior art under Article 54(3) EPC discloses a solid state image pickup device having a photo-shield plate in contact with a photo-electric converting region via a Schottky barrier, wherein the photo-shield plate provides a resistivity against a blooming phenomena and is, at the same time, adapted for a large integration density and for easy fabrication. Especially, there is disclosed a solid state image pickup device comprising a substrate, a well, photo-electric converting regions, charge transferring regions, channel forming regions, (heavily doped) stopper regions, insulating films, transfer electrodes and a photo-shield plate. Further, there is provided a spacer region at the surface of the photoelectric conversion elements. The spacer regions may be contiguous to the stopper regions but are not aligned with the edges of the surrounding transfer electrodes. EP-A-0 360 595 also falling under Article 54(3) EPC discloses a solid state image sensor which is designed for suppressing dark currents. There is described that by heat treatment boron ions of a surface impurity layer are diffused toward the polycrystalline silicon transfer electrode, thereby forming a P-type region in a shape partly overlapping with the polycrystalline silicon transfer electrode in the charge readout channel region. The surface impurity layers are, however, not aligned with the remaining edges of the surrounding transfer electrodes. It is the object of the invention to provide a highly integrated solid state image sensor device, by which the disadvantages mentioned above can be overcome. This object is solved by a solid state image sensor device according to claim 1. Claim 2 shows a further development of the device according to claim 1. A method for manufacturing the device according the invention is described by claim 3. More specifically, according to the invention, an impurity layer constituting a surface layer of a photoelectric conversion element in the solid state image sensor extends to a position corresponding to an end of a transfer electrode of each charge transfer device and the extended portion serves as an isolation layer, thereby obviating problems associated with the degradation of device performance due to expansion of the isolation layer in thermal diffusion. Further, the invention provides a method of making a solid state image sensor of a structure which is free of a drop of the gate threshold value of the charge readout channels due to short-channel effect, by utilizing an extension formed in the surface P type layer by thermal diffusion, and which is capable of avoiding layer deviations by using a self-alignment technique. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view of a conventional solid state image sensor device; Fig. 2 is a sectional view of the device shown in Fig. 1; Fig. 3 is a plan view of a solid state image sensor device according to an embodiment of the invention; Figs. 4 and 5 are sectional views of the device shown in Fig. 3; Fig. 6A is a sectional view of the solid state image sensing device according to another embodiment of the invention; Figs. 6B and 6C are views showing potential profiles of the embodiment shown in Fig. 6A; and Figs. 7A to 7C are views illustrating a further embodiment of a method of making the device according to this invention. A plan view of the essential parts of the solid state image sensor device according to a first embodiment of the invention is illustrated in Fig. 3. The structure in cross section of the essential parts taken along the line XII - XII of Fig. 3 and a similar view taken along the line XV - XV are shown, respectively, in Figs. 4 and 5. The illustrated embodiment takes the form comparable with the conventional device referred to above, so that corresponding parts are denoted by the same reference numerals. In Fig. 3, the reference numerals 16 and 17 designate first and second transfer electrodes of the charge transfer device formed of a CCD (charge-coupled device), the hatched areas 18 designate isolation regions (isolation layers), the numeral 19 a photoelectric conversion element region, and 20 a transfer channel region (a channel layer). The hatched area 48 represents a P type high concentration impurity layer for electrically coupling the isolation layers 18 (23 in Figs. 4 and 5) separated by the electrodes, the layer 48 being formed prior to the formation of the electrodes. The P layer 48 becomes necessary where the concentration of the P well 9 is particularly low and the resistance between the elements is considerably high. In Figs. 4 and 5, numeral 8 indicates an N type substrate, 9 a P type well layer, 10 light shield films for preventing image light from being incident to the charge transfer devices, and 11 an insulating film. As shown in Figs. 4 and 5, the transfer channel region 20 is an N type charge transfer channel layer and the numeral 21 represents a high concentration, P type impurity region overlying on the surface of the photoelectric conversion element, and including an extended portion 23. 22 denotes an N type impurity region constituting the body of the photoelectric conversion element having photoelectric conversion function and charge-storage function. 24 denotes a channel layer for reading a charge. In Fig. 4, the differences of the solid state image sensor device of this embodiment with the known device of Fig. 2 are in the absence of the isolation layer 3 according to this embodiment and in the presence as an isolation layer of the extended portion 23 of the impurity region 21 overlying the surface of the photoelectric conversion element. The forward end 32 of the extended portion 23 and a proximating end 26 of the second transfer electrode 17 approximately coincide with each other when viewed from top. In other words, they lie approximately in a single vertical plane. This structure can be readily realized, for example, by a self-alignment technique to be described later. Since the P type impurity region 23 defines the extended portion of the impurity region 21 overlying the N layer 22 to cover the surface area thereof and has a far shallower junction than at least the N layer 22, almost no reduction of the area of the N layer 22 due to impurity diffusion in the lateral direction from the P type impurity region 23 occurs. The result is that the width of the isolation layer 23 approximately equals to the distance between its end 32 and the N layer 22 at its end 33 proximate the isolation layer 23. Accordingly, the minimum value of the width is determined by aligning precision during the manufacturing process of the electrode 17 and the N layer 22. Further, the forward end 32 of the extended portion 23 approximately coincides with the proximating end of the transfer electrode 17 as viewed from top and extends no further making approximately equal the width of the charge transfer channel layer 20 and that of the electrode 17. In other words, the transfer channel width of the charge transfer device is defined by the ends of the surface impurity layer 21 which substantially coincide with the ends of the electrode when viewed from top. This permits the whole semiconductor region directly underneath the electrode 17 to function as the transfer channel, thus minimizing the size of a inactive region. Fig. 5 shows a cross section taken along the line XV - XV of Fig. 3 in which the charge readout channel does not appear. The surface P-type layer 21 includes extended portions 23 at both ends, which serve as isolation layers and whose respective ends 27 and 28 both approximately coincide with, respectively, to the proximating ends 29 and 30 of the transfer electrodes 16 and 17 when viewed from top. The forward ends 27 and 28 of the extended portions 23 respectively define the proximating ends of the corresponding channel layers 20. As illustrated, the entire semiconductor region except the extended portions 23, as viewed from top, provides for valid active regions for the photoelectric conversion element and the charge transfer device, thus greatly increasing device performance. The increased width of the photoelectric conversion layer 22 increases the amount of incident light to the solid state image sensor to increase its sensitivity. Increasing the width of the channel layer 20 as far as to the ends of the electrode 16 increases the amount of transferable charge per unit electrode width and hence broadening the dynamic range of the solid state image sensor. As has been described, the width of the isolation layer 3 in the conventional device finally reaches to about 2.0 µm after a thermal treatment even when a lithographic technique providing a minimum manufacturing width of 1.0 µm is relied upon. In comparison, the structure according to the embodiment may attain a resulting width of the isolation layer 23 of about 0.5 to 1.0 µm even if a deviation of ± 0.3 µm is taken into account between the left end 29 of the electrode 16 and the right end 33 of the photoelectric conversion layer 22, i.e., between the ends of the two elements closer to each other. The structure in cross section of the solid state image sensor according to a second embodiment of the invention is shown in Fig. 6A, wherein the numeral 34 denotes an N type impurity layer forming a photoelectric conversion element, and 35 a P type impurity layer covering the layer 34, and 39 an extended portion of the layer 35, having an isolating function. The numeral 36 is an N type impurity layer, at least a major portion of which forms the charge transfer channel layer. The P type impurity layer 35 is formed in high impurity concentration and the impurity is diffused by thermal diffusion by being subjected to a thermal treatment step. By appropriately controlling the thermal treatment step the P layer 35 may extend into the charge readout channel of the electrode 17 by a very short distance, the extended portion being denoted as 40. The extended portion 40 is in high concentration so that if the channel length is reduced, it may govern the channel threshold voltage. Potential distributions over the channel region ranging from the N layer 34 to the N layer 36 are shown in Figs. 6B and 6C. 41 indicates the potential of the extended portion 39 of the P layer 35, which has an isolation function, the potential being fixed to a reference level. 42 shows the potential of the layer 34 in the state in which a signal charge has been read and the photoelectric conversion element 34 has been completely depleted, and 43 (Fig. 6B) the potential of the charge transfer channel when the electrode 17 is at a low level and the N layers 34 and 36 are electrically separated from each other by a potential barrier formed therebetween. 44 is a readout channel potential which governs the threshold voltage of the read channel, which is brought about by the extended portion 40, and controlled by a potential applied to the electrode 17, which is in an off state in this instance. When the electrode 17 is set to a high potential level, the potential 44 is increased to potential 45 as shown in Fig. 6C to electrically couple the N layer 34 to the N layer 36, and a signal charge bundle 46 stored in the photoelectric conversion element 34 travels to the transfer channel 36. The formation and governing of the read channel by the extended portion 40 results in reducing the read channel length substantially to 1 µm or less, which heretofore has been required to be about 2 µm, for the prevention of short channel effect. This means that both the width of the photoelectric conversion element and the charge transfer device is increased correspondingly, improving device performance, such as sensitivity and dynamic range. The numeral 37 in Fig. 6A indicates an additional impurity layer that is used when the concentration of the N layer 36 is insufficient for itself to function as the transfer channel. In this case, the potential distribution from potential 44 to 43 and from potential 45 to 47 appears in stepped fashion as shown. 38 shows a P well for preventing the N layer 36 and the substrate 8 from punching through due to depletion of the P well 9. P well 38 is not an indispensable element. An embodiment of a method of fabricating the device according to the invention is shown in Figs. 7A to 7C. While the method as illustrated is directed to making the solid state image sensing device according to the second embodiment as shown in Figs. 6A to 6C, the method is applicable in principle to the fabrication of the device of the first embodiment. In Fig. 7A, the numeral 51 indicates a N type substrate, 52 a first P well, and 53 second P wells. 61 is an insulating film. After the formation of the P layers 52 and 53 on the N substrate 51 by ion implantation and thermal diffusion, N layers 54 and 55 are formed by ion implantation. While the N layers 54 and 55 are formed in the same ion implantation step, the layer formed in the first well 52 is indicated as an N layer 54 and those formed in the second P wells 53 as N layers 55 for the purpose of distinction. In fabricating the device according to the first embodiment, only the N layers 55 may be formed. Successively, a polycrystalline silicon electrode 56 is formed on the insulating film 61 in confronting relationship with each N layer 55 as shown in Fig. 7B using polysilicon vapor deposition and selective etching processes, followed by the formation of an insulating film 63 on each electrode 56 by using an oxidation step and a selective etching step, followed further by the formation of an N layer 57 by using partly a self-alignment technique using the insulating films 63 as a part of a mask (ion implantation inhibition layer) and by using an ion implantation step. One end of the N layers 57 is self-aligned with the left end 64 of each insulating film 63, and the other end thereof is defined by an end of a mask formed, for example, of a photoresist pattern (not shown). The photoresist mask in this instance extends further from the right end 65 of the insulating film 63 by a predetermined distance, whereby said other end of the N layer 57 is spaced apart from the right end 65 of the insulating film 63 by the above mentioned distance. High concentration P type layers 58 are then formed by a self-alignment technique in an ion implantation step using the insulating films 63 as a mask. A solid state image sensing device is manufactured finally after being subjected to a removal step for removing the insulating films 63, a thermal step for diffusing impurities, and vapor deposition and selective etching steps for forming wiring layers. The N layers 55 function as charge transfer channel layers whose both ends are defined by the P layers 58 and which correspond to the charge transfer channel layers 36 of Fig. 6A. The N layers 57 form photoelectric conversion elements whose surfaces are covered by the P layers 58 and correspond to the N layer 34 of Fig. 6A. Of the P layers 58 P ++ portions 59 extending leftwardly of the N layers function as isolation layers and correspond to the extended portions 39 in Fig. 6A. The readout channel portions 60 (portions surrounded by broken lines in Fig. 7C) for reading a charge from the photoelectric conversion elements 57 to the transfer channel impurity layers 55 are formed in a thermal step by the diffusion in the lateral direction of the impurities from the P layers 58, to semiconductor regions under the electrodes so that potential barriers defining channel threshold voltages are formed between the charge storage layers and the charge transfer devices. The channel threshold voltage are controlled by the concentrations and junction lengths of the read out channel regions 60. In the solid state image sensing device according to this invention, inactive regions created by the presence of the isolation P ++ layers can be decreased to a considerable extent, and further, a considerably large charge readout channel length (for example, 2 µm) which has been required for avoiding the short-channel effect may be reduced to the order of submicrons. This results in an increase in the areas of the photoelectric conversion elements and the charge transfer channel, thus providing for improvements in sensitivity and dynamic range. Needless to say, the invention achieves minimum size elements and high integration. The invention may be modified in various ways without being limited to the foregoing embodiments. For example, all indicated conductivity types of the elements may be reversed, in which case the potential relationship appears also reversed. The substance of the method of fabrication resides in that the P ++ type surface layers 58 are formed (self-aligned) using the electrodes surrounding the photoelectric conversion elements as a mask, that one end of the respective N layers 57 coincides with one end of one of the adjacent electrodes when viewed from top, and that the other end thereof is spaced apart with a fixed spacing from one end of the other of the adjacent electrodes. The other manufacturing steps described are not essential to the present invention. As will be apparent from the foregoing description, the surface impurity layers of the photoelectric conversion elements according to this invention extend to the ends of the transfer electrodes for use as isolation layers, to obviate problems associated with degradation of device performance due to expansion of the isolation layers by thermal diffusion in the prior art device. Widening the surface impurity layers by thermal diffusion avoids lowering of the gate threshold value of the charge readout channels due to short-channel effect, and readily achieves high integration. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A solid state image sensor device comprising on a semiconductor body (8, 9) a plurality of photoelectric conversion elements (19) and a plurality of associated charge transfer channels (20) for transferring signal charges stored in said photoelectric conversion elements, each of said photoelectric conversion elements being connected to its associated charge transfer channel via an individual charge readout channel region (24); and a plurality of transfer electrodes (16, 17) formed via an insulating film (11) on said semiconductor body and extending across said charge transfer channels so that said photoelectric conversion elements are surrounded by said transfer electrodes which cover the charge readout channel regions; wherein each of said photoelectric conversion elements comprises a charge storage impurity layer (22) of a first conductivity type formed in a well region (9) of said semiconductor body of the second conductivity type, the edges of said charge storage impurity layer substantially coinciding with its surrounding transfer electrodes in the charge readout channel region, but being spaced apart with a fixed spacing from the remaining portions of said surrounding transfer electrodes; and a surface impurity layer (21) of the second conductivity type formed in said well region to cover the surface portion of said charge storage impurity layer, said surface impurity layer substantially coinciding with the edges of the surrounding transfer electrodes to form highly doped isolation regions (23) of the second conductivity type in said spacing. A solid state image sensor device according to claim 1, characterized in that potential barriers (44) are formed between said charge storage layers (34) and said charge transfer channels (37) by extending the surface impurity layers (35) into the charge readout channel regions (40) below the associated portions of the surrounding transfer electrodes (17) to electrically separate said charge storage impurity layers from said charge transfer channels when the absolute value of a potential of the transfer electrodes is at a low level, and to electrically couple said charge storage impurity layers to said charge transfer channels when the absolute value of a potential of the transfer electrodes is at a high level. A method of manufacturing a solid state image sensor device comprising the steps of forming first and second well regions (52, 53) of a second conductivity type on a semiconductor substrate (51) of the first conductivity type by ion implantation and thermal diffusion and forming, in said second well regions (53) by ion implementation, charge transfer channel layers (55) of the first conductivity type to be associated with respective photoelectric conversion elements for transferring signal charges stored in said photoelectric conversion elements and read out from said photoelectric conversion elements via charge readout channel regions; forming transfer electrodes (56) via an insulating film (61) using vapor deposition and a selective etching process, said transfer electrodes extending across said charge transfer channels and surrounding regions for said photoelectric conversion elements; forming insulating films (63) on said transfer electrodes (56) by using an oxidation step and a selective etching process; forming charge storage impurity layers (57) of the first conductivity type in said regions for the photoelectric conversion elements by using partly a self-alignment technique using the insulating films (63) as part of a mask in an ion implantation step, wherein the edges of said charge storage impurity layers are self-aligned with the associated surrounding edges of the insulating films in said charge readout channel regions and the other edges of said charge storage impurity layers are defined by a mask, wherein the mask extends from the remaining surrounding edges of the insulating films by a predetermined distance, whereby said other edges of said charge storage impurity layers are spaced apart from said remaining surrounding edges of the insulating films with a fixed spacing; forming surface impurity layers (58) of the second conductivity type in said semiconductor body by a self-alignment technique in an ion implantation step using the insulating films (63) as a mask, so that said surface impurity layers substantially coincide with the edges of the transfer electrodes surrounding said photoelectric conversion elements and form highly doped isolation regions (59) of the second conductivity type in said spacing; removing the insulating films (63) and thermally diffusing impurities, wherein potential barriers are formed in said charge readout channel regions by diffusion in the lateral direction of the impurities from the surface impurity layers to semiconductor regions (60) below the associated portions of the transfer electrodes, whereby a predetermined threshold voltage between the charge storage impurity layers and the charge transfer channels is created; and forming wiring layers by using vapor deposition and selective etching.

Inventors: YAMADA TETSUO, YAMADA, TETSUO, YAMADA, TETSUO, C/O INTEL. PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L27