Cmos latch circuit

Abstract: A high performance latch circuit having complemented isolation means that selectively maintain the state of the latch at a given logic state or input a new logic state thereto. The latch is made up of several legs of series connected transistors, the legs being connected in parallel. Selective gating is provided by the transistors directly coupled to the output node. The latch circuit comprises first and second potential terminals (VDD, GROUND); first and second MOS transistors (T1, T2) of a first type connected in series to form a first pair of transistors; third and fourth MOS transistors (T3, T4) of the first type connected in series to form a second pair of tran­ sistors, said first and second pairs of transistors being connected in parallel with each other between the first potential terminal (VDD) and a first node (NL1); fifth and sixth MOS transistors (T5, T6) of a second type which is different from the first type, said fifth and sixth transistors being connected in series to form a third pair of transistors; and seventh and eighth MOS transistors (T7, T8) of the second type connected in series to form a fourth pair of transistors, said third and fourth pairs of tran­ sistors being connected in parallel between the first node (NL1) and the second potential terminal (GROUND). The gates of said first and sixth transistors (T1, T6) receive the inverse of the voltage on the first node (NL1), the gates of said third and eighth transistors (T3, T8) are connected to receive a first logic signal (D0), the gates of said second and seventh transistors (T2, T7) are connected to receive a first clock signal (Co), and the gates of said fourth and fifth transistors (T4, T5) are connected to receive a second clock signal (Co′) having a phase opposite to the phase of the first clock signal (Co).

Description: The present invention relates to a high speed CMOS latch circuit. Many conventional CMOS latch circuits use a pass-gate to clock data into cross-coupled inverters. The term "pass-gate" refers to the function of passing an input signal in response to a control signal applied to the gate of a device. The pass-gate may be either a single NFET device, a single PFET device, or a parallel NFET-PFET pair. In such a conventional latch, the feedback inverter of the cross-coupled inverters must be smaller than the data input inverter so that the data inverter can overdrive the feedback inverter in order to change the state of the latch. The requirement of different sizes for the inverters makes it difficult to implement the latch in a gate array design where only one device size is available. There are many latch designs available in the prior art. Examples of such prior art latch circuit designs are discussed below. In L. Kitajewski: "Design of CMOS/SOS circuits for space applications", IEEE Transactions on Nuclear Science, NS-28 (1981), pp. 3569-3574, a D-type Flip-Flop design was presented which was optimized for the lowest cosmic ray induced error rate without jeopardizing the circuit speed and size. With respect to the specific application and technology (SOS, s ilicon o n s aphire) the layout was designed for high supply voltages. The latch circuit shown in Fig 3 of this article forms the basis for the preamble portion of Claim 1. The possible conversion of an S/R Flip-Flop into a D Flip-Flop by adding an inverter between S and R input is known, e.g. by B.S. Sonde, "Introduction to SYSTEM DESIGN USING INTEGRATED CIRCUITS", Wiley Eastern Limited, 1980, p. 114. U.S. Patent No. 4,277,699 discloses a shift register latch circuit including a polarity hold latch and a set/reset latch. The latches can be clocked with separate non-overlapping clock trains and therefore conform to the so-called Level Sensitive Scan Design (LSSD) rules which enable logic networks embodied in large scale integrated semiconductors to be adequately tested. Fig. 4 of the patent shows how the shift register latch may be implemented with AND/OR/INVERT circuits. IBM Technical Disclosure Bulletin, Vol. 27, No. 7B, December 1984, pp. 4538-4539 discloses a CMOS LSSD shift register latch which can be implemented in a master slice design without transfer or pass gates to thereby enhance testability. In particular, this reference discloses a two-stage polarity-hold version in which the memory function of the latch is performed by standard CMOS cross-coupled pairs. IBM Technical Disclosure Bulletin Vol. 27, No. 1B, June 1984, pp. 663-664 discloses a high speed CMOS latch circuit in which clock and data pulses are directly available to the output buffer (CMOS inverter) without first setting the latch. IBM Technical Bulletin Vol. 27, No. 10B, March 1985, pp. 6098-6099 discloses a LSSD-compatible latch. The latch circuit includes two stages of AND/OR/INVERT circuits controlled by two sets of input controls. U.S. Patent No. 4,568,842 discloses a D-Latch CMOS circuit for holding a logic signal in response to a control pulse. IBM Technical Bulletin Vol. 16, No. 7, December 1973, pp. 2289-2290 discloses a gated inverter using CMOS transistors. U.S. Patent No. 3,619,644 discloses a frequency dividing circuit having a logic structure satisfying specified Boolean relationships. PATENT ABSTRACTS OF JAPAN, Vol. 12, No. 342 (E-658) [3189], 14 September 1988 discloses a Flip-Flop with an additional FET which is controlled by a clock signal. IBM Technical Disclosure Bulletin, Vol. 30, No. 11, 11 April 1988, pp. 47-50 discloses a "Data Selector Latch and Clock Gating Network", including a 7-way multiplexer. Although various latch circuits are known in the art, it is important to decrease, as much as possible, the amount of current required to change the state of the latch. As discussed above, many latch designs employ data inverters which can overdrive the feedback inverter to change the latch state. With this process a significant amount of device current is needed to force the feedback loop from a first state to a second opposite state. Since the switching speed is proportional to the load provided between the inverter nodes of the latch, a large load will decrease the switching speed of the latch. With increasing levels of integration, this is becoming increasingly important. More particularly, as levels of integration increase, so does the number of latches required to switch in a given cycle. In view of the above, the primary object of the present invention is to provide a high speed CMOS latch, having reduced switching current requirements and which can be easily implemented in a gate array design. The present invention accomplishes these and other objects by providing a latch circuit which isolates the latch nodes during the clocking cycle so that all of the device current is available to charge the node capacitance. None of the device current is needed to overcome the current drain from other devices in the feedback loop, and therefore the latch requires less current when changing states. Ways of carrying out the invention are described in detail below with reference to the drawings in which: Fig. 1 is a general block diagram of the latch circuit according to the present invention; Fig. 2 is a circuit schematic diagram of the latch circuit of Fig. 1; Figs. 3A-3E are timing diagrams for explaining the operation of the latch circuit of Fig. 2; Fig. 4 is a circuit schematic diagram of a Master/Slave implementation of the latch circuit of Fig. 2; Fig. 5 is a circuit diagram of an embodiment of a latch circuit according to the invention which can reset the latch without the use of a clock signal; Fig. 6 is a circuit schematic diagram of a Set-Reset Set Dominant Latch according to the present invention; Fig. 7 is a circuit schematic diagram of Set-Reset Double Clock latch according to an embodiment of the present invention; Fig. 8 is a circuit schematic diagram of an inverter I2′ that can be substituted for the inverter I2 of the latch L2 of Fig. 4; Fig. 9 is circuit schematic diagram of an embodiment of a two-data latch according to the invention. Fig. 1 shows a general block diagram of a CMOS latch circuit L₁ according to the present invention and, in particular, a polarity hold latch circuit implementation of the invention. The latch circuit L₁ includes a Data Port, a Scan-in Port and an Inverter I₁. The Data Port receives a data clock signal Co, an inverted data clock signal Co′, a data signal Do and the output PL₁ of the Scan-in Port. The Scan-in Port receives the output signal (node NL1) of the Data Port, a scan-in clock signal Ao, the inverse Ao′ of the scan-in clock signal, and the inverse Io′ of the scan-in signal. The latch circuit L₁ also includes an inverter I₁ connected to the output node NL₁ of the Data Port. The output +L₁ of the inverter I₁ represents the output of the CMOS Latch L₁. Fig. 2 shows the circuit diagram of the latch circuit L₁ of Fig. 1. As shown in Fig. 2, transistors T1-T8 form the Data Port, and transistors T9-T16 form the Scan-in Port. In this implementation, the Data Port and the Scan-in Port each includes eight MOS transistors, four of which are N-type and four of which are P-type. The transistors T1-T4 and T9-T12 of the Data Port and the Scan-in Port, respectively, are N-type. The transistors T5-T8 and T13-T16 of the Data Port and the Scan-in Port, respectively, are N-type. The gates of transistors T1 and T6 of the Data Port receive the output signal PL1 of the Scan-in Port. The gates of transistors T2 and T7 receive the clock signal Co, the gates of transistors T4 and T5 receive the inverted clock signal Co′, and the gates of transistors T3 and T8 receive the data signal Do. The P-type transistors T1 and T2 are connected in series between a voltage source terminal V DD and the output node NL1 of the Data Port. The N-type transistors T5 and T6 are connected in series between the output node NL1 and ground GND. The P-type transistors T3-T4 are connected in the series between source V DD and the output node NL1, and are connected in parallel with the P-type transistors T1-T2 between source V DD and node NL1. The N-type transistors T7-T8 are connected in series between output node NL1 and ground terminal GND, and are connected in parallel with N-type transistors T5-T6 between node NL1 and ground GND. The gates of transistors T9 and T14 of the Scan-in Port are each connected to the output node NL1 of the Data Port. The gates of transistors T10 and T15 receive the scan-in clock signal Ao, and transistors T12-T13 receive the inverted scan-in clock signal Ao′. The gates of transistors T11 and T16 receive the inverted scan-in data Io′. The transistors T9-T16 of the Scan-in Port are connected in a similar manner as the transistors T1-T8 of the Data Port. As shown in Fig. 2, the output note PL1 of the Scan-in Port is connected to the gates of transistors T1 and T6, and the output node NL1 of the Data Port is also connected to the input of the inverter I₁. The operation of the latch circuit of Fig. 2 will now be described with reference to the timing diagram of Fig. 3. In particular, the operation will be described with the example of latching a "1" through the Data Port into the Latch L1. In this example, it is assumed that the initial conditions of the latch is such that the latch is in a "0" state (i.e., node NL1 is HIGH and node PL1 is LOW). In the initial condition, both the Ao and Co clock signals are set LOW, and therefore the inverted clock signals Ao′ and Co′ are both HIGH. With node PL1 and clock signal Co both LOW, P-type transistors T1 and T2 are both on, T5 is on, but T7 is off. As a result, transistors T2 and T5 serve to gate the inversion of PL1 to node NL1, while transistors T4 and T7 are OFF, thereby blocking the input of the data input signal Do. Similarly, with Ao LOW and Ao′ HIGH, transistors T10 and T13 of the Scan-in Port are both on which serves to gate the inversion of node NL1 to the PL1 node, while transistors T12 and T15 are OFF, thereby blocking the Io′ input. Thus, the Data Port and the Scan-in Port form a cross-coupled inverter pair which serves to hold the L1 latch data. In order to set the L1 Latch to a "1" state, first the data input Do is set HIGH and then the clock signal is set HIGH, as shown in Figs. 3A and 3B. By setting clock signal Co HIGH, transistors T2 and T5 are turned OFF and transistors T4 and T7 are turned ON, which allows the inversion of the data signal Do′ to be gated to node NL1, as shown in Fig. 3C. Since data signal Do is HIGH, transistor T8 is on and transistor T3 is off. Further, since clock signal Co is HIGH, transistor T7 is on. As a result, the voltage at node NL1 is discharged from a HIGH level to a LOW level through the path created by transistors T7 and T8 being on. As shown in Fig. 3, the same result occurs when inputting scan-in data Io and scan-in clock signal Ao (except that signal PL1 will change state before signal NL1). The Scan-in Port acts like an inverter to invert the voltage level at the node NL1, and feed the inverted level back to the Data Port. In particular, the Scan-in Port will invert the low level voltage at node NL1 to a HIGH level at node PL1, as shown in Fig. 3D. The inverter I₁ receives the voltage at node NL1 and outputs signal +L1 which represents the output of the latch. Accordingly, when the voltage at node NL1 goes LOW, the output +L1 will go HIGH, as shown in Fig. 3E. As a result, transistors T4 and T7 are off, such that node NL1 is isolated from transistors T3 and T8. At the same time, transistors T2 and T5 are on, such that the voltage on NL1 is controlled by the voltage on PL1, thereby maintaining the state of the L1 latch. In order to reset the Latch L1 to a "0" state, it is necessary to make the voltage level at node NL1 HIGH. By applying a HIGH or active clock signal Co with a LOW data signal Do, transistors T3-T4 will be turned on, and transistor T5 will be turned OFF. This will cause node NL1 to be charged to a HIGH voltage level because of the path created from source V DD to node NL1 through transistors T3 and T4. As a result of node NL1 going HIGH, the output +L1 will go LOW (i.e., the "0" or reset state). Fig. 4 shows a latch used in level sensitive scan design (LSSD) testing, which is a master/slave implementation of the latch circuit L1 of Fig. 2. In particular, Fig. 4 includes a second latch L2 which acts as a slave to the master latch L1. Latch L2 includes a Slave Port which is similar in construction to the Data Port and Scan-in Port of latch L1, and inverters I2 and I3. Inverter I2 is connected to receive the output (node PL2) of the Slave Port, and inverter I3 is connected to receive the output of the inverter I2. The output +L2 of inverter I3 serves as the output of Latch L2. The Slave Port of Fig. 4 includes eight MOS transistor T17-T24, with transistors T17-T20 being P-type, and transistors T21-T24 being N-type. The gates of transistors T17 and T22 of the Slave Port receive the output NL2 of the inverter I2, and the gates of transistors T18 and T23 receive a clock signal Bo for clocking data from latch L1 to latch L2. The gates of transistors T20 and T21 receive the inverse of this clock signal Bo′, and the gates of transistors T19 and T24 are connected to node NL1 of the Data Port of latch L1. The operation of latch L2 will now be described in connection with the example of latching a "1" from latch L1 to latch L2. In this example, the output +L1 of latch L1 is HIGH, and therefore the node NL1 of latch L1 is LOW. Since the gate of P-type transistor T19 is connected to node NL1, transistor T19 is turned on. In order to latch the output of latch L1 to latch L2, the clock Bo is set HIGH or active, which causes the P-type transistor T20 to turn on since its gate receives the inverse of the latch L2 clock signal Bo′. As a result of transistors T19 and T20 being on, a path is created from voltage source V DD to node PL2 through transistors T19-T20, and node PL2 is charged to a HIGH voltage level. Accordingly, the output of inverter I2 will go LOW and the output +L2 of inverter I3 (i.e., the output of latch L2) goes HIGH (the data of latch L1). As shown in Fig. 4, the gate of transistor T17 is connected to the output of inverter I2. Accordingly, when the output of inverter I2 is LOW, the P-type transistor T17 is turned on. In order to maintain the data in latch L2, clock Bo is turned off (i.e., clock Bo goes LOW). When clock Bo is LOW, P-type transistor T18 turns on. As a result of transistors T17 and T18 being on, node PL2 is maintained at a HIGH voltage level, and therefore the output +L2 of latch L2 is maintained at a HIGH or "1" level. Fig. 5 shows another embodiment of the latch circuit according to the invention. The latch circuit according to this embodiment can reset the L1 latch to a "0" state without the use of a clock signal. The L1 latch shown in Fig. 5 is identical to the L1 latch shown in Fig. 2, except that the Data Port shown in Fig. 5 includes an additional P-type transistor T30 and an additional N-type transistor T40. The P-type transistor T30 is connected between voltage supply V DD and node NL1, and its gate is connected to receive signal Ro. The gate of N-type transistor T40 is also connected to receive signal Ro and this transistor is connected between transistor T6 and ground GND. As indicated above, the embodiment of Fig. 5 allows the latch L1 to be reset to the "0" state without the use of a clock signal. In particular, this is accomplished by making signal Ro LOW. When signal Ro is LOW, N-type transistor T40 is turned off and P-type transistor T30 is turned on. Since transistor T30 is on, node NL1 will be charged to a HIGH voltage level, thereby causing the output of inverter I1 (i.e., the output +L of latch L1) to be reset to a LOW or "0" state. Accordingly, the embodiment shown in Fig. 5 allows the L1 latch to be reset to a "0" state without the use of a clock signal. Fig. 6 shows another embodiment of the latch circuit according to the invention. The latch shown in Fig. 6 may be termed a Set-Reset Set Dominant latch since the latch will be set by a set signal So and reset by a reset signal Ro; however, when both the set and reset signals are applied, the latch will be set. The latch L1 of Fig. 6 is identical to the latch of Fig. 2, except that transistor T3B of the P-type has been connected between the third and fourth with two P-type MOS transistors T3 and T4, and transistor T8 now receives the set signal So. The gate of transistor T3 receives the set signal So, and the gate of additional transistor T3B receives the inverse of the reset signal Ro′. The operation of the latch shown in Fig. 6 will now be described. The latch shown in Fig. 6 is set (i.e., the output of the latch will be set to a "1" or HIGH level) by applying a set signal So and the clock signal Co. In this regard, the setting of the latch shown in Fig. 6 is similar to the operation of latching data signal Do, as discussed in connection with the embodiment of Fig. 2. More particularly, with set signal So and clock signal Co both HIGH, transistor T3 is off, and transistors T7 and T8 are on. As a result, transistor T3 acts as a "blocking transistor" for blocking power from voltage supply V DD to node NL1. Further, because transistors T7 and T8 are both on, a discharge path is created from node NL1 to ground GND. Accordingly, the voltage at NL1 will discharge to ground through transistors T7 and T8, thereby causing inverter I1 to output a "1" or set state. As discussed, the Scan-in Port will act as an inverter to maintain the voltage at node PL1 HIGH, thereby maintaining the voltage at node NL1 LOW and the output +L1 of latch L1 set to a "1" or set condition. The operation of the resetting reset latch is similar to the operation of setting the latch discussed above. In order to reset the latch, an active (HIGH) reset signal Ro is applied to the latch, along with an active clock signal Co. As will be discussed below, in order to reset the latch, it is necessary for the set signal So to be LOW. With the set signal LOW, and the reset Ro and clock Co signals HIGH, transistors T3, T3B and T4 are all on. Further, transistors T5 and T8 are off. Accordingly, node NL1 would be charged to a HIGH voltage level, thereby causing the output of inverter L₁ (i.e., the output of the latch) to be reset to "0" condition. The latch of Fig. 6 is set dominant in that when both an active set So signal and an active reset Ro signal are applied to latch L1, the latch will be set, not reset. This is because with an active set signal So, transistor T3 will be off, thereby blocking the path between voltage source V DD and node NL1. Fig. 7 shows another embodiment of the latch circuit according to the invention. More particularly, Fig. 7 shows the circuit schematic of a Set-Reset Double Clock Latch. This latch uses separate clock signals for setting and resetting the latch. The latch circuit shown in Fig. 7 is identical in construction to the latch circuit shown in Fig. 2, except that the gate of transistor T3 of the Data Port receives the inverse of a reset signal Ro′, and the gate of transistor T8 receives a set signal So. The clock signals CS and CR correspond to a set clock signal and a reset clock signal, respectively. The operation of this embodiment will now be described, first in connection with setting the latch, and then with resetting the latch. In order to set the latch (i.e., to a "1" condition or state), first a HIGH or active set signal So is applied, and then a HIGH clock signal Cs is applied. This is similar to the data signal Do and the clock signal Co of Fig. 3. Since the gates of the N-type transistors T7 and T8 receive the clock set signal CS and the set signal So, respectively, both of these transistors will be turned on, thereby forming a discharge path from node NL1 to ground GND. As a result, the voltage at node NL1 will become LOW. Accordingly, the output +L1 of the inverter I₁ will become HIGH or at a set condition. The operation of resetting the latch is similar to the operation of setting the latch. More particularly, to reset the latch, an active or HIGH reset signal RO and then an active clock reset signal CR is applied. Since the gates of P-type transistors T3 and T4 receive the inverse of the reset signal RO′ and the inverse of the reset clock signal CR′, respectively, both of these transistors will be on, thereby forming a path from voltage source V DD to node NL1. As a result, the voltage at node NL1 will become HIGH, and the output of the inverter I₁ will become LOW. Accordingly, the latch will be reset to a "0" condition. Fig. 8 shows an inverter I2′ that can be substituted for the inverter I2 of the latch circuit L2 of Fig. 4. The inverter I2′ of Fig. 8 adds a Data Port between the output node PL2 of the Slave Port and the input NL2. The configuration of the latch circuit shown in Fig. 8 allows for data D2 to be directly inputted into latch L2. This is because the second Data Port acts like an inverter. The operation of the second Data Port is identical to the operation of the Data Port shown in Fig. 2 and therefore will not be described. Fig. 9 shows an embodiment of a dual port latch circuit according to the invention. In this embodiment, either data D1 or data D2 can be applied to the latch L1. As shown in Fig. 9, the Data Port according to this embodiment includes fourteen transistors T1-T8 and T1A-T6A. The transistors T1-T4 and T2A, T3A and T4A are P-type, and transistors T5-T8 and T5A, T7A and T8A are N-type. The operation of applying data D1 with clock signal C1 and of applying data D2 with clock C2 is identical to the operation of applying data Do with clock Co as discussed above in connection with Figs. 2-3, and therefore this operation will not be described.

Claims: A latch circuit, comprising first and second potential terminals (VDD, GROUND); first and second MOS transistors (T1, T2) of a first type connected in series to form a first pair of transistors; third and fourth MOS transistors (T3, T4) of the first type connected in series to form a second pair of transistors, said first and second pairs of transistors being connected in parallel with each other between the first potential terminal (VDD) and a first node (NL1); fifth and sixth MOS transistors (T5, T6) of a second type which is different from the first type, said fifth and sixth transistors being connected in series to form a third pair of transistors; seventh and eighth MOS transistors (T7, T8) of the second type connected in series to form a fourth pair of transistors, said third and fourth pairs of transistors being connected in parallel between the first node (NL1) and the second potential terminal (GROUND); the gates of the third and eighth transistor being connected to receive logic signals (D⊘, R⊘′, S⊘); inverse logic means for receiving a logic voltage at the first node (NL1), and for outputting a logic voltage (L1) at a second node (PL1) which is the complement of the logic voltage at the first node (NL1); the gates of said first and sixth transistors (T1, T6) being connected to the second node (PL1), the gates of said second and seventh transistors (T2, T7) being connected to receive a first clock signal (Co, CS), and the gates of said fourth and fifth transistors (T4, T5) being connected to receive a second clock signal (Co′, CR′) having a phase opposite to the phase of the first clock signal (Co, CS), characterized in that said inverse logic means comprises: ninth and tenth MOS transistors (T9, T10) of the first type connected in series to form a fifth pair of transistors; eleventh and twelfth MOS transistors (T11, T12) of the first type connected in series to form a sixth pair of transistors, said fifth and sixth pairs of transistors being connected in parallel with each other between the first potential terminal (VDD) and the second node (PL1); thirteenth and fourteenth MOS transistors (T13, T14) of the second type, said thirteenth and fourteenth transistors being connected in series to form a seventh pair of transistors; and fifteenth and sixteenth MOS transistors (T15, T16) of the second type connected in series to form an eighth pair of transistors, said seventh and eighth pairs of transistors being connected in parallel between the second node (PL1) and the second potential terminal (GROUND); the gates of said ninth and fourteenth transistors (T9, T14) being connected to the first node (NL1), the gates of said eleventh and sixteenth transistors (T11, T16) being connected to receive the complement (Io′) of a second logic signal (Io), the gates of said tenth and fifteenth transistors (T10, T15) being connected to receive a third clock signal (Ao), and the gates of the twelfth and thirteenth transistors (T12, T13) being connected to receive a fourth clock signal (Ao′) having a phase opposite to the phase of the third clock signal (Ao). The latch circuit of claim 1, wherein the gates of said third and eighth transistors (T3, T8) being connected to receive a first logic signal (D0) which is the data signal to be latched. The latch circuit of claim 1 or 2, further comprising an additional MOS transistor (T30) of the first type connected between the first potential terminal (VDD) and the first node (NL1), and an additional transistor (T40) of the second type connected between the sixth transistor (T6) and the second potential terminal (GROUND), the gates of both additional transistors being connected to receive a reset signal (Ro) for resetting the latch circuit. The latch circuit as defined in any one of the claims 1 to 3, further comprising first, second and third additional MOS transistors (T2A, T3A, T4A) of the first type, and fourth, fifth and sixth additional MOS transistors (T5A, T7A, T8A) of the second type, the first additional transistor (T2A) being connected between said first and second transistors (T1, T2), said second and third additional transistors (T3A, T4A) being connected in series between the first potential terminal (VDD) and the first node (NL1), the fourth additional transistor (T5A) being connected between said fifth and sixth transistors (T5, T6), the fifth and sixth additional transistors (T7A, T8A) being connected in series between the first node (NL1) and the second potential terminal (GROUND), the gates of the first and fifth additional transistors (T2A, T7A) being connected to receive a third clock signal (C2), the gates of said second and sixth additional transistors (T3A, T8A) being connected to receive a second logic signal (D2), and the gates of said third and fourth additional transistors (T4A, T5A) being connected to receive a fourth clock signal (C2′) having a phase opposite to the phase of the third clock signal (C2). The latch circuit as defined in any one of the claims 1 to 4, further comprising an additional MOS transistor (T3B) of the first type connected between said third and fourth transistors (T3, T4), the gate of said additional transistor (T3B) being connected to receive the complement of a reset signal (Ro′) for the latch circuit, wherein said first logic signal is a set signal (So) for setting the latch circuit, and wherein the latch circuit is operable for setting the latch when applying active set and clock signals, for resetting the latch when applying active reset and clock signals, and for setting the latch when applying active set, reset and clock signals. The latch circuit as defined in any one of the claims 1 and 3 to 5, wherein the gate of said third transistor (T3) being connected to receive an inverse (Ro′) of a reset signal (Ro), the gate of said eighth transistor (T8) being connected to receive a set signal (So). The latch circuit as defined in any one of the claims 1 to 6, further including a second inverse logic means (L2) comprising: seventeenth and eighteenth MOS transistors (T17, T18) of the first type connected in series to form a ninth pair of transistors; nineteenth and twentieth MOS transistors (T19, T20) of the first type connected in series to form a tenth pair of transistors, said ninth and tenth pairs of transistors being connected in parallel with each other between the first potential terminal (VDD) and the fourth node; twenty-first and twenty-second MOS transistors (T21, T22) of the second type, said twenty-first and twenty-second transistors being connected in series to form an eleventh pair of transistors; and twenty-third and twenty-fourth MOS transistors (T23, T24) of the second type connected in series to form a twelfth pair of transistors, said eleventh and twelfth pairs of transistors being connected in parallel between the fourth node and the second potential terminal (GROUND); the gates of said seventeenth and twenty-second transistors (T17, T22) being connected to the third node (NL2), the gates of said nineteenth and twenty-fourth transistors (T19, T24) being connected to receive a second logic signal, the gates of said eighteenth and twenty-third transistors (T18, T23) being connected to receive a fifth clock signal (Bo), and the gates of said twentieth and twenty-first transistors (T20, T21) being connected to receive a sixth clock signal (Bo′) having a phase opposite to the phase of the fifth clock signal (Bo).

Inventors: CHU ALBERT M, CHU, ALBERT M.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: H03K3
IPC codes: H03K17, H03K3