Personal computer for disabling resume mode upon replacement of HDD

Abstract: When a hard disk pack (20) is removed from a com­ puter main body in a power-OFF state, a signal level of a specific pin of a connector (61) is set at high level, and a signal of high level representing replacement of the hard disk pack (20) is set in a flip-flop (F/F) 67. When a power switch is turned on, a CPU (11) determines from information set in the F/F (67) that the hard disk pack (20) has been replaced. The CPU (11) disables a resume flag. As a result, upon a power-ON operation, resume processing is not performed, and damage to the hard disk pack and overrun of a program can be prevented.

Description: The present invention relates to a personal computer using a replaceable hard disk as an external storage medium. In the field of personal computers in recent years, compact, lightweight, portable laptop personal computers have been very popular in place of conventional desk-top personal computers. Demand has increasingly arisen for more compact, lightweight, portable laptop personal computers. The most advanced laptop personal computer employs a low-profile floppy disk drive (FDD), and a display and a hard disk pack are detachably mounted in this personal computer. In order to improve user operability, a laptop personal computer has a resume mode as a standard mode. In the resume mode, a state (i.e., a content of a memory and contents of various types of register) in the system is saved in a nonvolatile memory in a power-OFF state, and a state immediately before the power-OFF timing is restored upon power-ON. Therefore, jobs can be continued regardless of a power-ON/OFF state. A hard disk pack is generally replaced in a power-OFF state to prevent attachment/detachment of the hard disk pack while signal lines are kept active. In the above personal computer, however, if a hard disk pack is detachable and when it is replaced in a power-OFF state, a change in content of the hard disk pack is not detected and a job is resumed in a resume mode. Therefore, the content of the hard disk pack is broken, and a system may overrun. Prior art document EP-A-230 351 discloses an information processing system which maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at that same point at a later time. More specifically, at the time the system is powered off, the contents of all active registers as well as the states of all I/O devices in the system are stored in a special save area of a system memory. This special save area is provided with power during the suspended time in order to retain the state of the system at the time it was powered down. By using this special save area, the main memory area of the system is available to any application programs independently of the system save memory requirements. Additionally, the system may be powered on and off under software control, thereby providing the capability for unattended system operation using an alarm function. It is an object of the present invention to provide a computer system, wherein replacement of a hard disk pack in a power-OFF state is detected, and a resume mode is disabled to prevent the content of the hard disk pack from damage and a program from overrun. To solve this object the present invention provides a computer system as specified in claim 1. A hard disk pack replacement detector (powered from a backup power source) detects replacement of a hard disk pack in a power-OFF state, and this information is stored as status information in a memory backed up by a battery. When the power switch is turned on, a CPU checks the status information, detects replacement of the hard disk unit, releases the resume mode, and causes a display to display an alarm message to an operator. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a system block diagram showing an overall arrangement of a personal computer according to the present invention; Fig. 2 is a block diagram showing a main part of the present invention; Fig. 3 is a circuit diagram showing a detailed arrangement of a hard disk pack replacement detector shown in Fig. 2; Fig. 4 is a flow chart showing a power-ON control program executed by a CPU 11; Fig. 5 is a flow chart showing SETUP processing for setting a resume flag; and Figs. 6 and 7 are flow charts showing resume processing. Fig. 1 is a system block diagram showing an overall arrangement of a personal computer according to the present invention. Referring to Fig. 1, components 11 to 28, 51, and 53 are connected to a system bus 10. The central processing unit (CPU) 11 controls the overall system and executes flow charts shown in Figs. 4 to 7. The CPU 11 serves as a host CPU when viewed from a power control CPU 306 in a power supply 30 (to be described later). The read only memory (ROM) 12 stores a basic input and output program (BIOS). The BIOS includes programs shown in Figs. 4 to 7 and is executed in response to a system power supply. Setup information stored in a specific area (or register) of the RAM 13 is loaded, and a system atmosphere is judged. A boot block is loaded from the HDD 20A, and an operating system (OS) program stored in the HDD 20A is loaded in the RAM 13 by this boot block. The random access memory (RAM) 13 stores the operating system (OS), application programs, and various data. A backup power supply voltage VBK is supplied from the power supply 30 to the RAM 13. Even if a system power switch is turned off, the memory contents are not lost. The direct memory access (DMA) controller 14 performs direct memory access control. The controller (PIC) 15 is a programmable interrupt controller which can be set by a program. The timer (PIT) 16 is an interval timer which can be set by a program. When the interval timer 16 counts a time set by a program, the timer 16 supplies a time-out signal as an interrupt signal to the CPU 11 under the control of the programmable interrupt controller 15. The CPU 11 executes a vector interrupt routine in response to this interrupt signal. The real-time clock (RTC) 17 is a timepiece module having its own operation battery to display current time. The extending RAM 18 is a large-capacity memory detachably mounted in an extending RAM card slot in a main body, and a backup power (VBK) is supplied to the extending RAM 18. The backup RAM 19 constitutes a data storage area for realizing the resume function and is supplied with the backup power (VBK). The hard disk interface 51 interfaces the CPU 11 with the hard disk pack 20. The hard disk pack 20 is detachably mounted in a hard disk pack section of the main body. The hard disk pack 20 consists of, e.g., a 2.5″ hard disk drive (HDD) 20A and a hard disk controller (HDC) 20B for controlling access of this drive. The hard disk pack replacement detector 53 detects that a hard disk pack is replaced in a power-OFF state. The hard disk pack replacement detector 53 stores this detection information. The detection information is read by the CPU 11 when a power switch is turned on. The floppy disk controller (FDC) 20F controls a 3.5″ optional floppy disk drive (external FDD) 32 and a 5″ optional external floppy disk (external FDD) 33. The printer controller 21 is connected to an external printer 34. The input/output interface 22 is a universal asynchronous receiver/transmitter (UART). An RS-232C interface equipment 35 is connected to the interface 22, as needed. The keyboard controller (KBC) 23 controls a keyboard 36. The display controller (DISP-CONT) 24 controls a liquid crystal display (LCD) 37. The video RAM 25 is supplied with the backup power (VBK) and stores video data. The kanji ROM 26 stores kanji character patterns corresponding to kanji character codes. The dictionary ROM 27 stores a correspondence between kana and kanji characters and a kanji conversion dictionary. The power supply control interface (PS-IF) 28 connects a power supply 30 to the CPU 11 through the system bus 10. A power supply adapter (AC adapter) 29 is plugged in the personal computer main body to rectify and smooth a commercial AC power and obtain a DC operating power having a predetermined voltage. An expansion unit is selectively connected to an expansion connector 40. The intelligent power supply (power controller) 30 comprises the power control CPU 306 and supplies power to each unit described above. A battery (M-BATT) 31A is a detachable main battery pack constituted by a rechargeable battery. A battery (S-BATT) 31B is a sub-battery incorporated in the main body and constituted by a rechargeable battery. Fig. 2 is a block diagram showing a relationship between the hard disk pack 20, the hard disk pack replacement detector 53, and the CPU 11. When the hard disk pack 20 is replaced in the power-OFF state, the hard disk pack replacement detector 53 detects it and registers it as status information. Upon a power-ON operation, the CPU 11 reads the status information stored in the hard disk pack replacement detector 53 and determines whether the hard disk pack is replaced in the power-OFF state. Fig. 3 is a circuit diagram showing a detailed arrangement of the hard disk pack replacement detector 53. The hard disk pack 20 is detachably connected to the personal computer main body through a connector 61. A specific connector pin on the hard disk pack 20 side, e.g., the first pin, is connected to the ground potential. The first connector pin on the computer main body side is connected to a backup power supply 65 through a pull-up resistor. The first pin of the connector 61 on the computer main body side is connected to a clock input terminal CK of a flip-flop (F/F) 67 through a signal line 66. When the hard disk pack 20 is kept connected to the computer main body, a signal of logic "0" level is supplied to the clock input terminal CK of the F/F 67. When the hard disk pack 20 is detached from the computer main body, a signal of logic "1" level is supplied to the clock input terminal CK of the F/F 67. Therefore, the signal of logic "1" level from the power supply 65 is supplied to the D input terminal of the F/F 67, and a signal of logic "1" level representing replacement of the hard disk pack 20 is set in the F/F 67. The Q output terminal of the F/F 67 is connected to an open collector type gate 69. The output terminal of the gate 69 is normally pulled up to the power supply (+5 V) through a pull-up resistor 71. An output signal HDCHG from the gate 69 is supplied to the CPU 11 through a signal line 73. A normally voltage detector 75 monitors the power supply (+5 V) and outputs a signal of logic "1" level to an AND gate 77 in a normal voltage state (i.e., +5 V, 10%). When this power supply is set at low level, the voltage detector 75 outputs a signal of logic "0" level to the AND gate 77. A clear signal is supplied from the CPU 11 to the other input terminal of the AND gate 77 through a signal line 79. When the power supply voltage is normal and a high-level (active high) signal is supplied from the CPU 11, the AND gate 77 supplies a signal for clearing the F/F 67 to a clear terminal CLR of the F/F 67. The AND gate 77 is arranged to prevent the content of the F/F 67 from being broken upon power-ON/OFF. An operation of the embodiment having the above arrangement will be described with reference to a flow chart in Fig. 4. When an operator turns off the switch of the computer main body and removes the hard disk pack 20, the level of the signal line 66 is changed from low level (logic "0") to high level (logic "1") by the backup power supply 65 and a pull-up resistor 63. As a result, a signal of logic "1" level is set in the F/F 67. Then, an HDCHG signal as a low-level (logic "0") output signal from the gate 69 is output. The operator connects a desired hard disk pack 20 to the computer main body through the connector 61 and turns on the system switch. In response to this power-ON operation, the CPU 11 executes the flow chart in Fig. 4. More specifically, the HDCHG signal is read in step 81. The CPU 11 determines an HDCHG level in step 83. If the CPU 11 determines level "0" of the HDCHG signal, i.e., determines that the hard disk pack 20 has been replaced, a resume mode flag set in a register (not shown) is cleared in step 85. In step 87, the CPU 11 clears the F/F 67 through the AND gate 77. In step 87, a message representing that no resume processing is performed due to replacement of the hard disk pack is displayed on the LCD 37, as needed. Resume operations from step 85 are not performed, and system initialization processing is executed. Therefore, damage to the content of the hard disk pack by execution of the resume processing can be prevented. Fig. 5 is a flow chart showing SETUP processing for setting a resume flag shown in step 85 of Fig. 4. The operator depresses a function key or inputs a predetermined command to start a setup program. The setup program contains various contents and is used to execute various processing operations (step S11). When the current operation reaches enable/disable setup of the resume function, a menu inquiring whether the resume function is enabled is displayed on the LCD 37 (step S12). In response to this inquiry, the operator inputs from the keyboard 36 an instruction whether the resume function is enabled. The input instruction is determined in step S13. When the input instruction represents enabling of the resume function, a resume flag is set (step S15). Fig. 6 shows save processing of resume processing. In response to a power-OFF operation, the CPU 11 saves system data such as contents of registers of the CPU 11, contents of various registers, and the content of the program counter in the RAM 13 in step S31. In step S32, the CPU 11 sets a system data save flag. Fig. 7 shows restore processing of the resume processing. That is, in response to a power-ON operation, the CPU 11 determines in step S51 whether the system data save flag is ON. If YES in step S51, the CPU 11 restores, in step S52, various system data saved in the RAM 13. In step S53, the system data save flag is reset.

Claims: A computer system provided with a removable storage device (20) removably connected to the computer through a connector (61) and having a restarting function for restarting an operation at a state of the computer existing immediately preceding a power off operation in response to a power on operation, characterized by further comprising a latch circuit (67) latching a change of level of a signal from the connector (61) when the removable storage device is removed from the computer during a time when the computer is in a power off state, and outputting a result signal; and control means (11, 12) for determining whether or not the signal level from the connector (61) has changed based on the result signal when the computer is powered on, and for inhibiting an execution of the restarting function when the result signal designates that the signal level has changed so that the computer does not restart at a state of the computer existing immediately preceding a power off operation. The computer system according to claim 1, characterized in that the removable storage device comprises a disk drive. The computer system according to claim 2, characterized in that the disk drive comprises a hard disk drive. The computer system according to claim 1, characterized in that the control means reads the result signal every time the computer is powered on, and inhibits the execution of the restarting function when the result signal indicates that the signal level from the connector (61) has changed. The computer system according to claim 1, characterized by further comprising means (11, 12) for clearing a content of the latch circuit (67) after said control means (11, 12) inhibits the execution of the restarting function. The computer system according to claim 1, characterized in that said control means (11, 12) comprises flag means for signaling inhibiting the execution of the restarting function. The computer system according to claim 1, characterized in that the connector (61) has a specific pin assigned to output a specific signal in response to attachment or detachment of the removable storage device (20) .

Inventors: HIBI KENJI, HIBI, KENJI, HIBI, KENJI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F13
IPC codes: G06F13, G06F1, G06F3