A burst mode digital data receiver

Abstract: A burst mode digital data receiver automatically adjusts its logic reference voltage to be equal to one-half of the sum of the minimum and maximum excursions of a received data signal. The receiver includes a differential amplifier circuit which has a first input for receiving the data signal and a second input connected to a voltage reference circuit. The voltage reference circuit is responsive to an output signal from the amplifier circuit to produce the required logic reference voltage at the second input to the amplifier circuit by generating a feedback signal which causes the amplifier circuit to have a first gain value during the absence of the data signal and while the data signal is less than its peak amplitude and a second gain value approximately twice the first gain value for a predetermined time after the peak amplitude of the data signal is reached.

Description: This invention relates to burst mode digital data receivers. Inter computer and intra-computer communications are often characterized by burst mode data transmissions. Conventional ac-coupled optical receivers, intended for continuous data transmission, are usually employed. Undesirably, however, data encoding increases system complexity and reduces the effective data transmission speed. By contrast, high-speed, dc-coupled receivers, while ideally suited for burst mode operation, have proven difficult to implement because of the necessity of establishing a logic reference voltage V REF level within a few millivolts of the dc center (one-half of the sum of the minimum and maximum excursions of the data signal) of the received data pulse. When a digital data signal from a data link is received by a preamplifier of a dc-coupled receiver the signal has been degraded to an analog-type signal with uncertain amplitude and non-zero transition times between the logic ZERO and logic ONE levels. Ideally, the dc center of the preamp output should match the logic threshold of the decision circuit so that the decision circuit can restore the analog-type signal to a clean digital signal. When the dc center at the preamp output does not match the logic threshold, the decision circuit causes pulse-width distortion (PWD) or may not be able to detect a logic transition. This PWD is undesirable because it reduces the sensitivity and maximum bandwidth of the system. The problem is additionally complicated by the fact that input data amplitudes can vary by factors of 100 or more. One type of dc-coupled optical receiver is described in the article by M.Aiki et al., entitled "446 Mbit/s Integrated Optical Repeater," Journal of Lightwave Technology, Vol. LT-3, No. 2, April 1985, pp.392-394. This article describes an optical repeater (Fig. 2) including an automatic gain-control feedback system which includes a peak detector (a) which controls the optical gain of an optical detector G c -APD and a peak detector (b) which controls the gain of an AGC amplifier. Another dc-coupled optical receiver is described in the article by Y. Mochida et al., entitled "Hardware Design Concepts of LSI Optical Data Link," IEEE Global Telecommunications Conference, Vol. 1, November 1982, pp. 404-408. This article describes an optical receiver (Fig. 7) which includes current feedback for controlling the dc level of the output signal and an AGC circuit for providing optical dynamic signal range. It is a continuing problem to design a burst mode digital data receiver with minimized PWD and increased sensitivity. According to this invention there is provided a burst mode digital data receiver as claimed in claim 1. A burst mode digital data receiver embodying the invention adapts to the amplitude of the incoming burst data packet and automatically adjusts the logic threshold voltage to the dc center of the input data pulse. The receiver includes a balanced differential input transimpedance circuit having a first input for receiving an input burst data signal and a second input connected to a voltage reference circuit that sets the logic threshold voltage. The voltage reference circuit is connected in a feedback loop between both the output of and the second input of the transimpedance circuit for generating a feedback signal to the transimpedance circuit, resulting in the receiver having a) a first gain value both during the absence of the input data signal and while the input data signal is less than its peak amplitude, and b) a second gain value approximately equal to two times the first gain value for a predetermined time after the peak amplitude of the input data signal is reached. In a disclosed embodiment, the voltage reference circuit and the transimpedance circuit have substantially the same maximum data transmission rate and the feedback loop is stable at the maximum data rate of the transimpedance circuit. As a result, the logic threshold voltage is adjusted to be substantially equal to the dc center of the input data pulse within one bit time following the beginning of the incoming burst data packet. Brief Description of the Drawing In the drawing, FIG. 1 shows one prior art dc-coupled burst mode receiver; FIGS 2 to 5 show, for the receiver of FIG. 1, the resulting PWD when the logic reference voltage V REF does not track the dc-center voltage of different received signal levels; FIG. 6 shows another prior art dc-coupled burst mode receiver; FIGS. 7 to 10 show, for the receiver of FIG. 6, the PWD at different received signal levels; FIG. 11 shows a burst mode receiver embodying the present invention; and FIG. 12 shows a detailed specific embodiment of the present invention. Detailed Description FIG. 1 is illustrative of a prior art dc-coupled burst-mode-operated optical receiver. In FIG. 1, a photodetector 101 delivers an optical input current I IN proportional to the optical power input received by photodetector 101 from lightwave signal 100. This current is converted to a voltage by the transimpedance preamplifier (preamp) 102 and delivered to an input of a "decision" circuit 103. The decision circuit 103 may be a high gain amplifier or a clocked regenerative latch, and its purpose is to restore a received analog signal with uncertain amplitude to a clean digital ZERO or ONE. When implemented as a clocked latch, it also serves to re-time the logic transitions at its output so as to remove phase noise arising from such factors as dispersion, pulse-width distortion, and timing jitter. The other input of decision circuit 103 is connected to a reference voltage V REF that sets the logic threshold. The problem to which the present invention is directed is better understood with reference to FIGS. 2 to 5 which show, for the receiver of FIG. 1, the resulting PWD when the V REF does not track the dc center voltage of different received signal levels (e.g. V1, V2 and V3). The preamp 102 output V 0 should, in an ideal case, swing symmetrically above and below V REF , depending, respectively, on the presence or absence of an optical input current (photocurrent) I IN . This occurs when the dc center voltage equals V REF , where the dc center voltage is defined herein as one-half the sum of the minimum and maximum excursions of output signal V 0 . This condition is illustrated in FIG. 2 which illustrates the voltage V 0 for a repeating 010101, etc., data sequence. Specifically, note that, when the dc center voltage V2 equals V REF then output signal V 0 swings symmetrically around V2. Hence, the output V D of decision circuit 103, shown in FIG. 3, is of uniform width during the logic ZERO and ONE bits. Since the width of the logic ZERO (T2″-T2) and logic ONE (T2-T2′) bits are equal, no pulse-width distortion (PWD) results. When the optical input current I IN is very small, however, the corresponding voltage swing of preamp output signal-denoted V 0S in FIG. 2 will be small and the resulting dc center voltage at the preamp output (V1 of FIG. 2 ) will also be small. Under such a condition, V REF would be larger than dc center voltage V1. The result is that decision circuit output V 0 has a widened logic ZERO level (T1″-T1) and a narrowed logic ONE level (T1-T1′), as shown in FIG. 4. This asymmetric output that V D exhibits is, in fact, PWD, which results because V REF is not centered in the pulse (i.e., V REF does not equal dc center voltage V1). FIG. 5 shows the effects when V REF is less than the dc center voltage (e.g., V3), which results when the input current I IN is very large and hence output V 0 is large (see V 0L of FIG. 2 ). The decision circuit 103 output V D exhibits a narrow logic ZERO (T3″-T3) and wide logic ONE (T3-T3′). The PWD of FIGS. 4 and 5 is undesirable because it reduces the maximum data transmission rate and sensitivity of the receiver of FIG. 1. To minimize PWD as the amplitude of the input current I IN changes, the voltage V REF must also change by a corresponding amount. Figure 6 illustrates a prior art receiver designed to reduce the severity of the PWD. In FIG. 6,use is made of the differential inputs to the decision circuit 303 by converting the preamp 302 to a differential output configuration. In this circuit, because the preamp output voltages are Q and Q , the difference voltage Q - Q determines the decision circuit 303 logic state, and the precise value of V REF is unimportant Thus, having V REF at a level which is not equal to the dc center voltage has no effect on PWD. This approach introduces a new problem, however, in that when the optical input current I IN is absent (e.g. a logic ZERO input), identical dc voltages at the Q and Q outputs leave the decision circuit in an undefined logic state. Accordingly, a large enough "logic ZERO offset" must be established at the inputs to ensure that the decision circuit 303 is in a well-defined logic ZERO state when the optical input is absent. The required magnitude of LZO is chosen based on the input sensitivity of the decision circuit 303 at the maximum bit rate, and on the maximum tolerable PWD. Shown in FIG. 7 are the Q and Q complementary outputs of preamp 302 as a function of time in response to a 0101010, etc. input data sequence with realistic rise and fall times. In the ideal case, with the LZO chosen to be exactly one-half of the preamp 302 output swing, the widths of the logic ZERO and logic ONE pulses output by decision circuit 303 are equal, as shown in FIG. 8, and there is no PWD. FIG. 9, however, shows that when the input current I IN is doubled, the preamp 302 output swing is doubled in amplitude while LZO is fixed at the previous level. Consequently, the logic ONE pulse width is much larger than that of the logic ZERO, as shown in FIG. 10, and the PWD is large. In fact, for any preamp 302 output amplitude swing other than 2 x LZO, PWD will be present Moreover, as the amplitude of the input current I IN increases, the PWD will increase until at some input level, determined by rise and fall times, the logic ZERO pulse will vanish altogether. This is because a long sequence of ONEs may cause the differential output to ramp to a larger voltage than the voltage for a single logic ONE, leaving insufficient time for a single ZERO pulse to effect a logic state reversal. An alternative statement for minimum PWD is (from FIG. 7 ) that (Q - Q ) ZERO = - (Q - Q ) ONE . Thus, the prior art dc-coupled receiver circuits of FIGS. 1 and 6 have not been able to detect input data signals having large dynamic ranges without exhibiting undesirable amounts of PWD. An adaptive voltage reference circuit measures the amplitude of an incoming burst data packet and, within (in the present embodiment) a few nanoseconds of its arrival, automatically adjusts the logic threshold voltage to the dc center voltage of the input signal. Consequently, PWD is minimized, and overall system sensitivity is maximized. An embodiment of the invention is illustrated in FIG.11 where the receiver circuit 500 includes two circuit units 501 and 502. The first unit 501 is, illustratively, a well-known differential input/output transimpedance amplifier with a nominal transimpedance value of Z T , as determined by the feedback resistor Z T . The second unit 502 is a voltage reference circuit, illustratively implemented as a peak detector, for generating a reference voltage V REF that sets the logic threshold voltage for the first unit 501. In the remainder of the text, the terms voltage reference circuit 502 and peak detector 502 are used interchangeably. The peak detector 502 comprises a differential amplifier A 2 , blocking transistor T X , peak voltage holding capacitor C PD , and buffer transistor T Y . The peak detector 502 has the positive input of differential amplifier A 2 connected to the positive output lead (V + / 0) of transimpedance amplifier A 1 and its output 503 connected to the resistor Z T1 (Z T1 = Z T ) connected to the negative input of transimpedance amplifier A 1 . This connection forms a negative feedback loop for generating the reference dc-voltage on lead 503 from the voltage on lead V + / 0 of amplifier A 1 . Another feedback loop 504, comprising amplifier A 2 and transistors T X and T Y , controls the voltage gain of peak detector 502. The operation of the present invention is best understood by analyzing the differential transfer function of transimpedance amplifier A 1 as a result of the connection of peak detector 502. For transimpedance amplifier A 1 , the low-frequency, differential transfer function is ΔV 0 = V + / 0- V - / 0 = + Z T I IN , where I IN is the input current. The peak detector 502 samples only one of amplifier A 1 outputs, and therefore stores the peak value of the single-ended transfer function, ΔV + / 0 = Z T I IN / 2. Thus, a V REF with amplitude exactly equal to one-half the peak differential signal swing is generated by peak detector 502 and applied to the negative input of the transimpedance amplifier A 1 . Preferred embodiments of the present invention advantageously utilize the inherent signal-splitting characteristic of a differential amplifier (i.e., A 1 ) to develop a V REF that scales ideally with input signal amplitude. Consider the following sequence of events in order to better understand the operation of the circuit. Suppose that at time t=0, there is no data present and, therefore, I IN = 0. The peak detector capacitor C PD is discharged. When the data burst arrives, and under the condition that ΔV + / 0 = -ΔV - / 0, the transfer equation for the circuit in FIG.11 is ΔV + / 0 = I IN Z T / 2. (Here "Δ" signifies the change in voltage level after arrival of the data burst.) The peak detector amplifier A 2 charges capacitor C PD until the voltage at amplifier A 2 's plus and minus nodes are equalized. Turn-on voltage offsets (V BE ) in T X and T Y are reduced in amplitude by a factor proportional to the open loop gain of amplifier A 2 . The voltage stored on capacitor C PD , proportional to I IN Z T / 2, is equal to the desired V REF . Alternatively, one may understand the present invention conceptually by recognizing that the decision circuit function (i.e., the function performed by circuit 103 of FIG. 1) has effectively been incorporated into the differential input transimpedance amplifier 501; and the reference threshold voltage (i.e., V REF of FIG. 1) establishes a reference dc current through resistor Z T1 equal to the midpoint of the input current I IN . Thus, peak detector 502 dynamically generates a dc reference voltage V REF on lead 503 which is equal to the required dc center voltage. This ensures that the input current I IN will vary symmetrically around the reference current V REF /Z T1 and consequently minimize PWD in a manner similar to that discussed in FIGS 2 to 5 when V2 = V REF . Thus, when input current I IN increases, V REF increases; and when I N decreases, V REF decreases. This enables receiver 500 to have improved sensitivity (for low I IN ) and large dynamic input range (ratio of high I IN to low I IN ). When the data burst has passed, the voltage stored on the peak detector capacitor C PD decays with a discharge rate determined by the amplitude of the base current of buffer transistor T Y . This suggests that the frequency response characteristics of receiver 500 may be sub-divided into three domains of interest. In the first, low-frequency domain, the peak detector capacitor C PD is approximated by an open circuit, so that the peak detector 502 becomes simply a unity gain amplifier, and the overall small signal gain function is ΔV 0 = I IN Z T . In the second, high-frequency domain, the peak detector capacitor C PD is charged to a fixed value proportional to the half-amplitude of the input current I IN , and the small signal gain function becomes ΔV 0 = + 2 I IN Z T . In the third, very high-frequency domain, gain function rolls off with a dominant pole determined by the product of Z T and the capacitance at amplifier A 1 's positive input, divided (approximately) by the gain of amplifier A 1 . A detailed analysis of the transimpedance of amplifier A 1 in the low- and high-frequency domains of interest is provided in a later section. Two additional requirements imposed on the receiver 500 may be noted. First, the peak detector capacitor C PD must charge very rapidly--ideally, in a time comparable to the width of a single ONE pulse--so that the "cold" system can go to a "warm" state in time for the second bit of data in the burst. At a data transmission rate of 200 Mb/s, this allows 5 ns for acquisition of the pulse amplitude information. Second, because output ΔV 0 is as small as a few millivolts, all circuit offsets must be self-cancelling to first order. To satisfy these requirements, amplifiers A 1 and A 2 are, in prefefred embodiments, designed to have substantially identical operating characteristics (i.e., A1 and A2 are "twins" of each other). For any given data rate, amplifier A 1 must (by definition) be designed with enough bandwidth to accommodate that data rate. Therefore, by selecting amplifier A 2 as the twin of amplifier A 1 , we guarantee that amplifier A 2 is inherently endowed with sufficient bandwidth to perform the amplitude sampling function in a single bit period (providing C PD is not too large). Furthermore, because amplifier A 2 (here defined to include T X and T Y ) is the twin of amplifier A 1 , most structural offsets (e.g., transistor V BE drops) within A 2 are balanced to first order by the same offsets within amplifier A 1 . Small residual offsets are further reduced by the feedback around amplifier A 2 . Thus, assuming that component mismatches can be controlled in the IC fabrication technology, high-speed, high-accuracy pulse amplitude acquisition is assured. The following paragraphs describe the operation modes of receiver 500 of FIG.11 in the low- and high-frequency domains of interest: (1) Low frequency, or at the very beginning of a data burst: the peak detector amplifier A 2 acts simply as a unity gain feedback amplifier. (2) High frequency: peak detector amplifier A 2 has sampled the data amplitude and provides only a "reference" voltage to the negative input terminal of transimpedance amplifier A 1 . Mode 1 Operation During Mode 1 operation (low frequency or during peak detection), peak detector amplifier A 2 acts like a unity gain amplifier. This is because we here define "low" to mean frequencies where the discharging and charging of capacitor C PD allow the peak detector circuit 502 to track the amplifier 501 Q output. The following equations define the operation of the circuit during Mode 1: V + IN = V - 0 + I IN Z T V - IN = - V + 0 and where V offset is the inherent amplifier offset voltage and G is the voltage gain of transimpedance amplifier A 1 (G>>0). (A) Suppose that there is no input photocurrent present, i.e., I IN = 0. Then substituting equation (1) and (2) into (3) yields ΔV 0 = G ( V - 0 - V + 0 ) + V offset ΔV 0 = V offset 1 + G Therefore, receiver 500 has improved sensitivity or accuracy because it reduces the inherent voltage offset by the open-loop gain G of amplifier A 1 . Henceforth, in the following analysis we therefore ignore V offset . (B) At the beginning of the data burst, current I IN is not zero. Then substituting equation (1) and (2) into (3) yields ΔV 0 = G (-ΔV 0 + I IN Z T ) solving: ΔV 0 = G 1 + G I IN Z T ≈ I IN Z T The difference in the output voltage when a data pulse is present (I IN ≠ 0) , i.e., a logic ONE signal, and when a data pulse is not present (I IN = 0) , i.e., a logic ZERO signal, is equation (5) minus equation (4) or Δ (ΔV 0 ) = G 1 + G I IN Z T Thus, the low frequency differential transimpedance is GZ T 1 + G ≈ Z T Mode 2 Operation During Mode 2 (high frequency: peak detector has charged to a fixed "reference" level), then V I N = V REF output by peak detector amplifier A 2 . V REF is calculated as follows: As calculated previously from equation (4), with no data pulse (I IN = 0) present, ΔV 0 = V offset 1 + G . As previously noted, for simplicity of analysis V offset is small and its effects ignored. Thus, equation (4) becomes ΔV 0 ≈ 0, i.e., Correspondingly, V + 0 + V - 0 = 2V 0 (dc) Equation (9) is always true, whether photocurrent I IN is present or not, because of conservation of current in the output stage of differential amplifier A 1 . Now, by definition, V REF is the peak value of V + / 0 when current pulse is present, i.e. V REF = V + 0 (peak) Adding equation (5) V + 0 - V - 0 = G 1 + G · I IN Z T to equation (9) V + 0 + V - 0 = 2V 0 (dc) we solve for V + 0 (peak) = V REF = V 0 (dc) + G 2 1+G · I IN Z T With V REF calculated, we can now proceed to a calculation of ΔV 0 with and without data present (I IN ≠ 0 and I IN = 0, respectively). (C) With current pulse I IN present and again ignoring V offset , then using equations (3), (11) and V + IN = V - 0 + I IN Z T we obtain Also, V + 0 - V - 0 = Δ V 0 V + 0 + V - 0 = 2V 0 (dc) Then, V - 0 = V 0 (dc) - ΔV 0 2 Substituting equation (13) for V - / 0 in equation (12) yields (D) When current pulse goes away (I IN = 0), V REF does not change (in high-frequency case) because of peak detector. Therefore: For the high-frequency case, the difference in the output voltage when a data pulse is present (I IN ≠ 0) and when a data pulse is absent (I IN = 0) is And the high-frequency differential transimpedance is, therefore, 2G · Z T 2 + G ≈ 2Z T , for G>>1 Therefore, the ratio of high-frequency gain to low-frequency gain is for open loop gain "G" large (>>2). Summarizing, the receiver 500 is described by the following characteristics: I. With no current pulse present, i.e., at dc, intrinsic offsets are greatly reduced by open loop gain G of amplifier A 1 (equation 4). II. At low frequency (extending to dc), or at the beginning of a data burst, the differential transimpedance (equation 7) equals III. At high frequency, after the peak of the first data pulse of a data burst, differential transimpedance is (from equation 17) equal to IV. Receiver circuit 500 is self-adjusting so that during a data burst the following relationship exists: ΔV 0 (pulse present) ≈ - ΔV 0 (pulse absent) for G>>1. As illustrated in FIG. 7, and described previously, this is the necessary condition for minimum pulse-width distortion (PWD), i.e., (Q - Q ) ZERO = - (Q - Q ) ONE . Specific Embodiment A detailed illustrative schematic diagram of an embodiment of the present invention is shown in FIG.12. FIG.12 will be discussed with joint reference to FIG. 11. The amplifier A 1 of FIG.11 is composed of differential pair Q1 - Q2; follower/level shifter stages Q3 - Q4, Q5 - Q6; and current sources Q7 - Q9. The transimpedance resistors Z T and Z T1 are R2 and R3, respectively. Resistors R5, R6 and R7 are bias current resistors and resistors R1 and R4 are gain-setting resistors. Q1, Q3, and Q4 together comprise a conventional single-ended transimpedance amplifier, and Q2, Q5, and Q6 comprise another single-ended transimpedance amplifier. Amplifier A 1 is comprised of two such single-ended amplifiers tied together at the emitters of Q1 and Q2 into a differential amplifier configuration. The amplifier A 2 of peak detector 502 of FIG.11 is the "twin" of amplifier A 1 . Amplifier A 2 of FIG.11 includes transistors Q16 - Q21, and its bias current resistors (R18, R19) and gain-setting resistors (R16, R17) match those in A 1 . The transistors T X and T Y of FIG.11 are, respectively, transistors Q19 and Q20 of FIG.12. The peak detector capacitor C PD serves two functions: It stores the sampled input pulse amplitude, as described earlier, and also establishes a "low-frequency" dominant node in the peak detector feedback loop, thus stabilizing the circuit. Note that the twin matching amplifier concept is modified by omitting the current source transistor at the emitter of Q19 (corresponding to Q8 or Q9 in A 1 ). While helping to prolong the discharge time of C PD , it also introduces an offset in base-emitter voltage between Q19 and Q3 (or Q5). This corresponds to an input-referred offset current which the gain of amplifier A 2 reduces to a level required for the particular receiver. Shunt capacitor C1 located in parallel with R3 improves the transient response of receiver 500 by adding a zero to balance the pole at the base of Q2. Voltage V BIAS sets the transistor bias currents using resistors R5, R6, R7, R18 and R19. Amplifiers A 1 and A 2 are each constructed of circuit implementations similar to emitter-coupled-logic (ECL) gates. The feedback combination of A 1 and A 2 , therefore, is equivalent to a 2-gate delay circuit, with both the A 1 and A 2 amplifiers having comparable bandwidth. Moreover, such a feedback circuit is conveniently stabilized by a single dominant node capacitor (C PD ) at a bandwidth close to that of either amplifier alone. It is this configuration that allows setting V REF to the dc center of the logic pulse in a time substantially similar to the duration of a single logic pulse at the maximum data rate of amplifier A 1 . In an alternative implementation, the number of gain stages of amplifier A 2 may be increased. This has the beneficial effect of increasing the overall gain of A 2 , thereby further reducing voltage offsets and peak detector capacitor charging time. Additional stabilization methods may then be required, however, to assure the stability of the combined transimpedance and V REF circuit feedback loop. The low-frequency transfer function for the combination of differential amplifier 501 and peak detector 502 is given by ΔV 0 = R1 R2 I IN R1 + R2 β + 2 V T I 0 and the "high-frequency" transfer function is given by ΔV 0 = R1 R2 I IN R1 2 + R2 β + 2 V T I 0 The gain, G, of amplifier A 1 is G = R1 R2 β + 2V T I 0 In these expressions V T = k T / q: I 0 is the differential input stage (Q1, Q2) bias current; and R2 corresponds to the transimpedance Z T referred to previously. We have also required that R1 = R4 and R2 = R3. The term β is the current gain of transistors Q1 and Q2. The low-frequency transfer function defines the amplitude-tracking characteristic of the peak detector, whereas the high-frequency transfer function indicates the net transimpedance when the peak detector is charged to V REF , the half-amplitude reference voltage. As described previously, with no data present, there must be a known offset at the amplifier outputs to assure that the decision circuit is in a well-defined logic ZERO state. This offset and component mismatch trimming are programmed by off-chip resistors R15 or R20, which inject offset currents directly via resistors R21 and R22, respectively, into the base of one side or the other of the input differential pair (i.e., Q1, Q2), depending on the polarity of the necessary voltage offset. Capacitors C2 and C3 are bypass capacitors. The differential logic ZERO offset voltage should be tuned to the minimum needed to guarantee a logic ZERO decision when there is no data present. This maximizes system sensitivity and minimizes PWD. Since the peak detector charge (attack) and discharge (decay) characteristics are designed to minimize the probability of error in the first few bits of a data burst, the peak detector capacitor C PD charges as rapidly as possible. To maximize system sensitivity, the capacitor C PD maintains its charge for as long as possible once acquired. Charging time is determined by how much current transistor Q19 can source to C PD , and this current, in turn, depends on the extent of the voltage swing on the base emitter junction of Q19. Thus, the larger the amplitude of the input current I IN , the faster C PD will charge. C PD is discharged by the base current of Q20 at an appropriate linear rate. The charging time can be controlled by selecting C PD so that a data burst arrives and the peak detector reaches full charge during the first bit of the data burst. While the disclosed embodiment of the present invention is implemented in a fully differential form using complementary bipolar integrated circuit (CBIC) linear array technology, it should be noted that other circuit technologies could be utilized, including integrated bipolar or FET. The circuit can be implemented using, for example, silicon, gallium arsenide or other appropriate semiconductor materials. Moreover, it is contemplated that other well-known circuits can be used to implement the differential amplifier unit 501 or voltage reference circuit 502 shown in FIG.12. Additionally, while the present invention has been described for use with optical signals, it should be understood that the present invention can be utilized in non-optical signals as well. Finally, the present invention could be used with voltage input signals (rather than current input signals) by changing unit 501 from a transimpedance amplifier to a voltage amplifier. This is accomplished by replacing photodetector 101 with a voltage signal source of specified output impedance. What has been described is merely illustrative of the present invention. Other circuits embodying the invention can be implemented by those skilled in the art.

Claims: A burst-mode digital data receiver (500) which includes a balanced differential input transimpedance amplifier circuit (501) having a first input for receiving an input burst data signal and a second input connected to a voltage reference circuit (502) for setting a reference voltage (V REF ), the voltage reference circuit being connected in a feedback loop between both the output and the second input of the transimpedance circuit for generating a feedback signal to the transimpedance circuit, CHARACTERIZED IN THAT said voltage reference circuit includes means (502), responsive to said output, for detecting a peak amplitude of said data input signal and for generating said reference signal (V REF ) in such a way that said amplifier circuit (501) has a first gain value during the absence of said data input signal and while the data input signal is less than its peak amplitude, and has a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached, said generated reference signal (V REF ) being substantially equal to the dc centre of the data input signal. A receiver as claimed in claim 1 wherein said reference signal generating means (502) is connected in a feedback loop between said data output and said second input of said amplifier circuit (501). A receiver as claimed in claim 2 wherein said reference signal generating means (502) includes a peak detector circuit for detecting said peak amplitude of said data input signal. A receiver as claimed in claim 3 wherein said amplifier circuit (501) and said reference signal generating means (502) each include an amplifier means (A1, A2) having operating characteristics which are substantially matched to each other. A receiver as claimed in claim 3 or 4 wherein said amplifier circuit (501) and said reference signal generating means (502) are implemented as part of an integrated circuit. A receiver as claimed in claim 3, 4 or 5, wherein said amplifier circuit (501) has a first feedback loop (Z T ) to regulate the magnitude of the input current to voltage output characteristic of said amplifier circuit, and said reference signal generating means (502) has a first feedback loop (504) to control the gain of the peak detector circuit. A receiver as claimed in claim 3, 4 or 5 wherein said reference signal generating means includes means (C PD ) for storing the peak amplitude of data input signal, and amplifier means for controlling the discharge rate of said means for storing. A receiver as claimed in claim 7 wherein said means for storing (C PD ) is connected in said feedback loop (504) and is connected in another feedback loop (504) which controls the gain of said peak detector circuit. A receiver as claimed in any one of claims 2 to 8 wherein said feedback loop (504) includes a parallel resistor and capacitor network (C1,R3) connected in series to said second input of said amplifier circuit (501) to cancel an impedance pole at the second input of said amplifier circuit. A receiver as claimed in any one of claims 2 to 9 wherein said reference signal generating means (502) and said amplifier circuit (501) are adapted to operate at substantially the same maximum data rate, said feedback loop (504) is stable at the maximum data rate of said amplifier circuit, and the resulting voltage on said second input is substantially equal to the dc centre of the input signal within a single bit period following the beginning of a received data burst. A receiver as claimed in any preceding claim wherein said amplifier circuit (501) includes means (R15,R20) for selecting a dc offset current between said first and said second inputs of the amplifier circuit.

Inventors: OTA YUSUKE, SWARTZ ROBERT GERALD, OTA, YUSUKE, SWARTZ, ROBERT GERALD
Applicants: AT & T CORP, AT&T CORP.
Application year: 1990
Main classification: H04B10
IPC codes: H04B10, H03K5, H04L25