Nonvolatile semiconductor memory

Abstract: A nonvolatile semiconductor memory is a pro­ grammable and erasable nonvolatile semiconductor memory including a semiconductor substrate (10) of a first conductivity type, source and drain diffusion layers (11, 12) formed in the semiconductor substrate, and a channel region (14) provided between the source and drain diffusion layers. A first insulation film (15) is continuously formed on the channel region and the drain diffusion layer adjacent to the channel region, and a floating gate layer (16) is formed on the first insulation film. Further, a second insulation film (17) having a thin film portion (18) which is formed thinner than the first insulation film is formed on the floating gate layer, and a control gate layer (19) is formed on the second insulation film.

Description: This invention relates to a nonvolatile semiconductor memory comprising a semiconductor substrate of a first conductivity type; source and drain diffusion layers formed in said substrate; a channel region provided between said source and drain diffusion layers; a first insulation film continuously formed on said channel region and said drain diffusion layer; a floating gate layer formed on said first insulation film; a second insulation film formed on said floating gate layer; and a control gate layer formed on said second insulation film. Such a memory is described in EP-A-0 280 883. Another memory device is shown in JP-A-57-130473. A nonvolatile semiconductor memory in which data can be electrically programmed is well known in the art as an electrically erasable and programmable read only memory (E²PROM). Memory cells used for constituting the E²PROM can be formed with various types of constructions, and the memory cells are generally formed with a construction in which a floating gate is partly overlapped with a drain diffusion layer with a thin insulation film disposed therebetween. Fig. 1 is a cross sectional view of a conventional memory cell with the above construction. In Fig. 1, 50 denotes a p-type semiconductor substrate. N-type diffusion layers 51, 52 and 53 are separately formed in the surface area of the substrate 50, and a channel region 54 is provided between the diffusion layers 51 and 52. A floating gate 56 formed of polysilicon is disposed over the channel region 54 with a relatively thick insulation film 55 disposed therebetween. The floating gate 56 is also formed over the diffusion layer 52 with a thin film portion 57 thinner than the insulation film 55 disposed therebetween. Further, a control gate 59 formed of polysilicon is disposed over the floating gate 56 with a relatively thick insulation film 58 disposed therebetween. A channel region 60 is provided between the diffusion layers 52 and 53, and a select gate 62 formed of polysilicon is disposed over the channel region 60 with a relatively thick insulation film 61 disposed therebetween. With the above construction, the diffusion layer 51 is connected to a source line S and the diffusion layer 53 is connected to a bit line BL. Further, the control gate 59 and select gate 62 are respectively connected to control gate line CG and select gate line SG. Fig. 2 is a circuit diagram of an equivalent circuit of the element shown in Fig. 1. In Fig. 2, a transistor Q11 is a floating gate type MOS transistor having the diffusion layers as the source and drain thereof and constituting a memory cell transistor for storing data. Further, a transistor Q12 is an ordinary type MOS transistor having the diffusion layers 52 and 53 as the source and drain thereof and constituting a selection transistor for selecting the memory cell transistor Q11. The MOS transistors Q11 and Q12 are serially connected between the source line S and the bit line BL. The memory cell with the above construction has a data erasing mode, data programming mode and data readout mode. Fig. 3 shows voltages applied to the source line S, control gate line CG, select gate line SG and bit line BL in the respective operation modes. In this case, three types of power sources of ground voltage GND, V CC and V PP are used in an integrated circuit containing an E²PROM, and in an ordinary case, GND is 0 V, V CC is +5 V and V PP is +20 V. In general, the voltage V PP is not supplied as an exterior power source voltage, but is obtained by stepping up the voltage V CC in the integrated circuit. The data erasing mode is also called an electron injection mode in which the threshold voltage Vth of the memory cell transistor Q11 is raised by injecting electrons into the floating gate 56 of the transistor Q11. In this case, voltages of 0 V, +20 V, +20 V and 0 V are respectively applied to the bit line BL, select gate line SG, control gate line CG and source line S. When a voltage of +20 V is applied to the select gate line SG, the selection transistor Q12 is turned on and the diffusion layer 52 is set to 0 V by the voltage of the bit line BL. At this time, the floating gate 56 is held at a high potential by the voltage applied to the control gate line CG. Therefore, an intense electric field is applied across the thin film portion 57 of the insulation film 52 lying between the floating gate 56 and diffusion layer 52 so that a tunnel current may flow from the diffusion layer 52 towards the floating gate 56, thus injecting electrons into the floating gate 56. As a result, the threshold voltage Vth of the memory cell transistor Q11 is raised to approx. 8 V, for example. The data programming mode is also called an electron emitting mode in which the threshold voltage Vth of the memory cell transistor Q11 is lowered by emitting electrons injected into the floating gate 56 of the transistor Q11. In this case, voltages of +20 V, +20 V and 0 V are respectively applied to the bit line BL, select gate line SG and control gate line CG, and the source line S is applied with a voltage of +5 V or set in the electrically floating state. When a voltage of +20 V is applied to the select gate line SG, the selection transistor Q12 is turned on and the diffusion layer 52 is set to +20 V by the voltage of the bit line BL. Therefore, an intense electric field is applied across the thin film portion 57 in a direction opposite to that set in the case of the erasing mode so that a tunnel current may flow from the floating gate 56 towards the diffusion layer 52, thereby emitting electrons from the floating gate 56. As a result, the threshold voltage Vth of the memory cell transistor Q11 is lowered and set to approx. -5 V, for example. In the data readout mode, voltages of +1 V, +5 V, 0 V and 0 V are respectively applied to the bit line BL, select gate line SG, control gate line CG and source line S. When a voltage of 5 V is applied to the select gate line SG, the selection transistor Q12 is turned on and the diffusion layer 52 is set to +1 V by the voltage of the bit line BL. At this time, if electrons are previously injected into the floating gate 56 and the threshold voltage Vth is raised, then the memory cell transistor Q11 is not turned on. Therefore, no current flows between the bit line BL and source line S, thereby keeping the voltage of the bit line BL at +1 V. In contrast, if electrons are previously emitted from the floating gate 56 and the threshold voltage Vth is lowered, the memory cell transistor Q11 is turned on. Therefore, a current flows between the bit line BL and source line S, causing the bit line BL to be set to 0 V which is equal to the voltage of the source line S. That is, in the data readout mode, the voltage of the bit line BL is set to a voltage of 1 V or 0 V depending on the data storing state of the selected memory cell transistor Q11. Then, data detection of logic value "1" or "0" is effected by amplifying the voltage of the bit line BL by means of a sense circuit (not shown) connected to the bit line BL. A problem occurring in this case is to amplify a potential difference between 1 V and 0 V on the bit line BL by means of a sense circuit. That is, in the sense circuit, it is necessary to determine the level by amplifying a potential difference which is as low as 1 V. Now, the reason why the voltage of the bit line BL must be suppressed to approx. 1 V in the readout mode instead of setting the same to +5 V which is the normal power source voltage is explained. If a voltage of the bit line BL is set to +5 V in the readout mode, the potential of the diffusion layer 52 is also set to 5 V. Then, an electric field between the voltage of 0 V of the control gate line CG and the voltage of +5 V of the diffusion layer 52 is applied across the thin film portion 57 via the floating gate 56. That is, the electric field is applied to the thin film portion 57 in the same direction as in the case of the programming mode (electron emitting mode) and the different point is that the intensity of the electric field is weaker than in the case of the programming mode. Therefore, if the memory cell transistor is kept in the programming mode for a long period of time, electrons which have been previously injected will be gradually emitted by the tunnel effect. As a result, the threshold voltage Vth is gradually lowered and a logically erroneous operation may be caused when a certain length of time has passed. Such a phenomenon is called a soft write (weak write) phenomenon, and the resistance to the soft write phenomenon relating to the length of sustaining time thereof is called a read retention characteristic (data holding characteristic in the readout mode). The soft write phenomenon is explained with reference to Fig. 4. Fig. 4 is a characteristic diagram showing the relation between the threshold voltage Vth of a memory cell transistor in which electrons are injected into the floating gate and total time t BL in which a voltage is applied to the bit line with a voltage V BL of the bit line set as a parameter. As is clearly seen from Fig. 4, in order to prevent electrons from being emitted from the floating gate or suppress the electron emission to a minimum, it is necessary to set the bit line voltage V BL as low as possible. Therefore, in order to suppress occurrence of the soft error phenomenon, the bit line voltage in the readout mode may be set to a low level. However, if the voltage is lowered, a voltage difference between the bit line voltage set when an electron injected cell is selected and that set when an electron emitted cell is selected becomes smaller reducing the voltage margin at the time of determining the logic level of "1" or "0" by means of the sense circuit. For this reason, in the prior art, a voltage of approx. +1 V is applied to the bit line in the data readout mode to take the sufficiently effective measure for the read retention characteristic, and at the same time, the sense circuit is formed with a high performance to cope with the problem that the voltage margin becomes small, and thus a severe load is imposed on the sense circuit itself. As described above, in the prior art, an extremely heavy load is imposed on the sense circuit and various problems as described below have occurred. The first problem is that the construction of the sense circuit becomes complicated and the chip area may be increased in the case of forming the circuit in the integrated form. Increase in the chip area causes rise in the manufacturing cost. The second problem is that the operable power source voltage margin in the readout mode becomes small and particularly the operation on a low voltage becomes unstable. The third problem is that it becomes necessary to use a constant voltage source for supplying an intermediate voltage of +1 V to the bit line. If a circuit for producing the intermediate voltage is contained in the sense circuit, the current consumption increases, thereby making it difficult to attain low power consumption. The fourth problem is that the access time will become longer as the sense circuit becomes complex in construction. As described above, the conventional nonvolatile semiconductor memory has problems that the chip area increases, the low voltage operation becomes unstable, it is difficult to attain the low power consumption and the access time becomes longer. An object of this invention is to provide a non-volatile semiconductor memory which can attain a low voltage operation and low power consumption and permits peripheral circuits including a sense circuit to be formed simple in construction and operated at a high speed. According to one aspect of the invention, the semiconductor memory device initially defined is characterised in that: said first insulation film has a first thickness; said second insulation film has a thin film portion having a second thickness less than the first thickness; said thin film portion is arranged above said drain diffusion layer; and said second thickness is set to such a value that a tunnel current may flow in said thin film portion when an electric field of a predetermined intensity is applied between said control gate layer and drain diffusion layer. Preferably, the semiconductor memory further comprises: a third diffusion layer of the second conductivity type formed in said substrate; a second channel region provided between said drain and third diffusion layers; a third insulation film formed on said second channel region; a selection gate layer formed on said third insulation film; a control gate line for applying preset voltage to said control gate layer in the data programming, erasing and readout modes; a selection gate line for applying preset voltage to said selection gate layer in the data programming, erasing and readout modes; a source line for applying preset voltage to said source diffusion layer; and a bit line for applying preset voltage to said third diffusion layer in the data programming, erasing and readout modes. The semiconductor memory may further comprise: a power source node supplied with a power source potential; a load circuit connected between said bit line and power source node; and a sense circuit connected to said bit line, for detecting the potential of said bit line. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross sectional view showing the element structure of the conventional memory cell; Fig. 2 is a diagram showing an equivalent circuit of the element shown in Fig. 1; Fig. 3 shows voltages in the various operation modes of the memory cell shown in Fig. 1; Fig. 4 is a characteristic diagram showing the relation between the threshold voltage of the memory cell transistor shown in Fig. 1 and the total time in which a voltage is applied to the bit line; Fig. 5 is a cross sectional view showing the element structure of a memory cell used in a nonvolatile semiconductor memory according to this invention; Fig. 6 is a pattern plan view of the memory cell shown in Fig. 5; Fig. 7 is a diagram showing an equivalent circuit of the element shown in Fig. 5; Fig. 8 is a diagram showing voltages in the various operation modes of the memory cell shown in Fig. 5; Fig. 9 is a circuit diagram showing the schematic construction of a readout-side circuit of a nonvolatile semiconductor memory of this invention using the memory cell shown in Fig. 5; Fig. 10 shows another schematic construction of the above readout-side circuit; Fig. 11 shows still another schematic construction of the above readout-sice circuit; Fig. 12 is a timing chart of the circuit shown in Fig. 10; Fig. 13 is a circuit diagram showing the schematic construction of a readout-side circuit of a nonvolatile semiconductor memory of this invention using the memory cell shown in Fig. 5; and Fig. 14 is a circuit diagram showing the construction of a memory cell array portion of a memory of this invention using a large number of memory cells having the same construction as the memory cell shown in Fig. 5. Now, the embodiment of this invention this explained with reference to the accompanying drawings. Fig. 5 is a cross sectional view showing the element structure of a memory cell used in a nonvolatile semiconductor memory according to this invention and Fig. 6 is a pattern plan view thereof. 10 denotes a P-type silicon semiconductor substrate. N-type diffusion layers 11, 12 and 13 are formed in the surface area of the substrate 10, and a channel region 14 is provided between the diffusion layers 11 and 12. An insulation film 15 formed of a silicon oxide film, for example, is continuously formed to a thickness of 40nm (400 Å) on the channel region 14 and the diffusion layer 12 adjacent to the region 14. A floating gate 16 of polysilicon is formed on the insulation film 15. Further, an insulation film 17 formed of a silicon oxide film which has an approx. 40nm (400Å) thickness in a large portion thereof is disposed on the floating gate 16, and a thin film portion 18 having a film thickness of approx. 15nm (150 Å) is formed in part of the insulation film 17 or in position corresponding to the diffusion layer 12. Further, a control gate 19 formed of polysilicon is disposed on the insulation film 17. A channel region 20 is provided between the diffusion layers 12 and 13. A select gate 22 formed of polysilicon is formed over the channel region 20 with an insulation film 21 disposed therebetween. The insulation film 21 is formed of a silicon oxide film with a film thickness of approx. 40nm (400 Å), for example. The diffusion layers 11 and 13 are respectively connected to a source line S and a bit line BL, and the control gate 19 and select gate 22 are respectively connected to a control gate line CG and a select gate line SG. The memory cell shown in Figs. 5 and 6 is constructed by two series-connected MOS transistors Q1 and Q2 as shown by the equivalent circuit of Fig. 7. The transistor Q1 is a floating gate type transistor having the diffusion layers 11 and 12 as the source and drain thereof and constitutes a memory cell transistor for storing data. The other transistor Q2 is an ordinary type MOS transistor having the diffusion layers 12 and 13 as the source and drain thereof and constitutes a selection transistor for selecting the memory cell transistor Q1. Like the conventional memory cell, the memory cell with the above construction has three different operation modes, that is, electron injection, electron emission and readout modes. Fig. 8 shows voltages applied to the source line S, control gate line CG, select gate line SG and bit line BL in the respective operation modes, and the operation in each operation mode is explained below. In the electron injection mode, voltages of +20 V, +20 V and 0 V are respectively applied to the bit line BL, select gate line SG and control gate line CG, and the source line S is set in the electrically floating state (indicated by FL in Fig. 8). When a voltage of +20 V is applied to the select gate line SG, the selection transistor Q2 is turned on and a voltage of +20 V of the bit line BL is transmitted to the diffusion layer 12. At this time, a voltage of 0 V of the control gate line CG is applied to the control gate 19. In this case, the potential of the floating gate 16 is determined by dividing a voltage of +20 V of the diffusion layer 12 according to the capacitance ratio of a capacitance between the control gate 19 and floating gate 16 to a capacitance between the floating gate 16 and diffusion layer 12. The potential of the floating gate 16 is lower than 20 V but is sufficiently higher than 0 V. Therefore, an intense electric field is applied between the control gate 19 and floating gate 16 via the thin film portion 18 of the insulation film 17 so that a tunnel current may flow from the floating gate 16 towards the control gate 19, thus injecting electrons into the floating gate 16. As a result, the threshold voltage Vth of the memory cell transistor Q1 is raised. In the case of electron emitting mode, voltages of 0 V, +20 V, +20 V and 0 V are respectively applied to the bit line BL, select gate line SG, control gate line CG and source line S. When a voltage of +20 V is applied to the select gate line SG, the selection transistor Q2 is turned on and a voltage of 0 V of the bit line BL is transmitted to the diffusion layer 12. At this time, the potential of the floating gate 16 is determined by dividing a voltage of the control gate 19 according to the capacitance ratio of a capacitance between the control gate 19 and floating gate 16 to a capacitance between the floating gate 16 and diffusion layer 12. The potential of the floating gate 16 is higher than 0 V but is sufficiently lower than +20 V. Therefore, in this case, an intense electric field is applied between the control gate 19 and floating gate 16 via the thin film portion 18 of the insulation film 17 in a direction opposite to that set in the case of the electron injection mode so that a tunnel current may flow from the control gate 19 towards the floating gate 16, thereby causing electrons to be emitted from the floating gate 16. As a result, the threshold voltage Vth of the memory cell transistor Q1 is lowered. In the data readout mode, voltages of +5 V, +5 V and 0 V are respectively applied to the bit line BL, select gate line SG and source line S, and the control gate line CG is set in the electrically floating state (FL). When a voltage of 5 V is applied to the select gate line SG, the selection transistor Q2 is turned on and a voltage of +5 V of the bit line BL is transmitted to the diffusion layer 12. At this time, if electrons are previously injected into the floating gate 16 and the threshold voltage Vth is raised, then the memory cell transistor Q1 is not turned on. Therefore, no current flows in the transistors Q1 and Q2, thereby keeping the voltage of the bit line BL at +5 V. In contrast, if electrons are previously emitted from the floating gate 16 and the threshold voltage Vth is lowered, the value of the threshold voltage Vth may be negative. At this time, the memory cell transistor Q1 is turned on. Therefore, a current flows from the bit line BL to the source line S through the transistors Q1 and Q2, causing a voltage of the bit line BL to be lowered to the voltage of 0 V of the source line S. Then, in the data readout mode, data determination of logic value "1" or "0" is effected by amplifying the voltage of the bit line BL by means of a sense circuit (not shown) connected to the bit line BL. It should be noted here that an ordinary power source voltage of +5 V can be applied to the bit line BL as it is. Further, even if a voltage of +5 V is applied to the bit line BL, occurrence of the soft error phenomenon can be suppressed and the read retention characteristic can be significantly improved. This is because the control gate 19 is set in the electrically floating state in the readout mode and no electric field is applied across the thin film portion 18 of the gate insulation film 17 disposed between the floating gate 16 and control gate 19 so that injection and emission of electrons due to the tunnel effect will not occur. Next, a nonvolatile semiconductor memory of this invention using the memory cell with the construction shown in Fig. 5 is explained. Fig. 9 is a circuit diagram showing the schematic construction of a readout-side circuit of the nonvolatile semiconductor memory of this invention using the memory cell of Fig. 5. For clarifying the explanation, only one memory cell 30 which is constructed by the memory cell transistor Q1 and selection transistor Q2 is shown in Fig. 9. A resistor 31 acting as a load is connected between an ordinary readout power source Vcc of +5 V and the bit line BL, and an input terminal of a sense circuit (sense amplifier circuit) 32 is connected to the bit line BL. In the circuit of Fig. 9, the potential of the bit line BL is fully swung or changed between 5 V and 0 V when the data readout operation is effected in the electron injected and emitted states of the memory cell 30. That is, when a voltage of +5 V is applied to the select gate line SG and the transistor Q2 is turned on, the transistor Q1 is turned off if electrons are previously injected into the transistor Q1, thereby permitting the potential of the bit line BL to be kept at 5 V. In contrast, if electrons have been emitted from the transistor Q1, the transistor Q1 is turned on, thereby setting the potential of the bit line BL to 0 V. Then, the potential of the bit line BL is detected by the sense circuit 32 and output as data. At this time, even if the level of the power source voltage Vcc is lowered, the potential of the bit line BL will be substantially fully swung between Vcc and 0 V. Therefore, a sufficiently large operation margin can be attained even in the low voltage operation in which the operation is effected with the level of the power source voltage Vcc lowered. Further, since an intermediate voltage of +1 V which is required in the prior art is not necessary, it is not necessary to form a circuit for creating such an intermediate voltage and the current consumption can be reduced. Fig. 10 is a circuit diagram showing the schematic construction of another readout-side circuit of the memory of this invention using the memory cell of Fig. 5. In this memory, a P-channel MOS transistor 33 is used instead of the resistor 31 as the load circuit of the bit line BL. A ground voltage of 0 V is applied to the gate of the transistor 33 to normally set the transistor 33 in the conductive state. In this way, it is possible to use a MOS transistor as the load circuit of the bit line BL. Fig. 11 is a circuit diagram showing the schematic construction of still another readout-side circuit of the memory of this invention using the memory cell of Fig. 5. In this memory, a clock signal p is supplied instead of the ground voltage to the gate of the P-channel MOS transistor 33 which is used as the load circuit of the bit line BL and the transistor 33 is turned on when required. Further, the select gate line SG of the selection transistor Q2 in the memory cell 30 is connected to an output terminal of a decoder circuit 34 acting as a combination circuit for supplying a selection signal in response to an input address. The operation of the decoder circuit 34 is also controlled by the clock signal p. That is, in this circuit, the clock signal p is set to "0" level in the precharging period as shown in the timing chart of Fig. 12 so as to turn on the transistor 33. As a result, the potential of the bit line BL is precharged to Vcc. In the next logically enabling period (in which p="1"), the transistor 33 is turned off to complete the operation of precharging the bit line BL. Further, in this period, the decoder circuit 34 becomes operative and sets the select gate line SG to 5 V or 0 V in response to the input address. When the select gate is set to a voltage of 5 V, the selection transistor Q2 in the memory cell 30 is turned on to select the memory cell 30. Fig. 13 is a circuit diagram concretely showing the sense circuit 32 available in each of the circuits of Figs. 10 and 11 together with the memory cell 30. In this case, a load circuit 35 connected between the power source terminal Vcc and bit line BL corresponds to the resistor 31 in Fig. 9, and the P-channel MOS transistor 33 in Figs. 10 and 11. In other words, since the potential of the bit line BL is fully swung between 5 V and 0 V when any type of load is connected between the power source terminal Vcc and bit line BL, it is not necessary to use a sense circuit with a complicated structure which has been required in the prior art for amplifying a small potential difference. For example, as shown in Fig. 13, it is possible to use a simple inverter 36 constituted by MOS transistors as the sense circuit. Therefore, the sense circuit can be simplified and the access time can be shortened. Fig. 14 shows the construction of a memory cell array of a memory of this invention using a large number of memory cells having the same construction as shown in Fig. 5. In this memory cell array, (n+1) groups each of which includes eight memory cells each constituted by two MOS transistors Q1 and Q2 are arranged in a lateral direction and a preset number of memory cells 30 are arranged in a vertical direction. Row address decoding signals ADRi, ADRi-1, ADRi-2, ADRi-3, --- output from a row address decoder (not shown) are supplied to the respective select gate lines SG of the memory cells 30. Further, a voltage of a program line PL is applied to the respective control gate lines CG of the memory cells 30 via respective depletion type MOS transistors Q3. The program line PL is applied with a voltage of 0 V and +20 V in the data erasing mode and programming mode, respectively and set into the electrically floating state in the data reading mode. The eight bit lines BL of each group are selected by eight column selection MOS transistors Q4. The gates of the eight column selection MOS transistors Q4 are commonly connected to a corresponding one of column select lines CSL and the conduction states of the transistors Q4 are controlled by column address decoding signals ADC0 to ADCn output from a column address decoder (not shown). Data read out and supplied to the eight bit lines BL selected by the eight column selection MOS transistors Q4 of one group are sensed by means of eight inverters 36-1 to 36-8. In Fig. 14, 35-1 to 35-8 denote load circuits which correspond to the resistor 31 in Fig. 9, and the P-channel MOS transistor 33 of Figs. 10 and 11. As described above, according to this invention, it is possible to provide a nonvolatile semiconductor memory which can attain a low voltage operation and low power consumption, simplify the construction of peripheral circuits such as sense circuits and enhance the operation speed thereof. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A nonvolatile semiconductor memory comprising: a semiconductor substrate (10) of a first conductivity type; source and drain diffusion layers (11,12) formed in said substrate; a channel region (14) provided between said source and drain diffusion layers; a first insulation film (15) continuously formed on said channel region (14) and said drain diffusion layer (12); a floating gate layer (16) formed on said first insulation film; a second insulation film (17) formed on said floating gate layer; and a control gate layer (19) formed on said second insulation film, characterized in that: said first insulation film (15) has a first thickness; said second insulation film (17) has a thin film portion (18) having a second thickness less than the first thickness; said thin film portion (18) is arranged above said drain diffusion layer (12); and said second thickness is set to such a value that a tunnel current may flow in said thin film portion (18) when an electric field of a predetermined intensity is applied between said control gate layer and drain diffusion layer. A nonvolatile semiconductor memory according to claim 1, further comprising: a third diffusion layer (13) of the second conductivity type formed in said substrate; a second channel region (20) provided between said drain and third diffusion layers; a third insulation film (21) formed on said second channel region; a selection gate layer (22) formed on said third insulation film; a control gate line (CG) for applying preset voltage to said control gate layer in the data programming, erasing and readout modes; a selection gate line (SG) for applying preset voltage to said selection gate layer in the data programming, erasing and readout modes; a source line (S) for applying preset voltage to said source diffusion layer; and a bit line (BL) for applying preset voltage to said third diffusion layer in the data programming, erasing and readout modes. A nonvolatile semiconductor memory according to claim 2 and further comprising: a power source node (Vcc) supplied with a power source potential; a load circuit (31,33,35) connected between said bit line and power source node; and a sense circuit (32,36) connected to said bit line, for detecting the potential of said bit line. A nonvolatile semiconductor memory according to claim 3, characterized in that said load circuit (31) is a resistor. A nonvolatile semiconductor memory according to claim 3, characterized in that said load circuit (33) is constituted by a MOS transistor which is normally set conductive. A nonvolatile semiconductor memory according to claim 3, characterized in that said load circuit (33) is constituted by a MOS transistor which is controlled to be temporarily rendered conductive in response to a clock pulse signal (p). A nonvolatile semiconductor memory according to claim 3, characterized by further comprising a combination circuit (34) which is controlled by the clock pulse signal (p) and is supplied with an address signal and which supplies an output signal to said selection gate line (SG). A nonvolatile semiconductor memory according to claim 3, characterized in that said sense circuit (36) is an inverter circuit.

Inventors: MARUYAMA TADASHI C O INTELLECT, MOHRI KATSUAKI C O INTELLECTUA, NAKASHIRO TAKESHI C O INTELLEC, YOSHIZAWA MAKOTO C O INTELLECT, MARUYAMA, TADASHI, C/O INTELLECTUAL PROPERTY DIV., MOHRI, KATSUAKI, C/O INTELLECTUAL PROPERTY DIV., NAKASHIRO, TAKESHI, C/O INTELLECTUAL PROPERTY DIV., YOSHIZAWA, MAKOTO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, G11C16, G11C17, H01L21