Memory access methods and apparatus

Abstract: A memory access method convolutes plural data using maximal-sequence codes having individual phase shifting quantities and writes the convoluted data into a cyclic memory (1, 12, 13, 14, 21). The memory access apparatus reads out a desired data from the cyclic memory (1, 12, 13, 14, 21) using corresponding maximal-sequence code. A memory access method convolutes plural data using sequence codes which is obtained weighting factoes and maximal-sequence codes having individual phase shifting quantities and writes the convoluted data into a cyclic memory (1, 12, 13, 14, 21). The memory access apparatus reads out a desired data from the cyclic memory (1, 12, 13, 14, 21) using corresponding maximal-sequence code. A memory access method convolutes plural data using maximal-sequence codes having individual phase shifting quantities and writes the convoluted data into a cyclic memory (1, 12, 13, 14, 21). The memory access apparatus reads out a desired data from the cyclic memory (1, 12, 13, 14, 21) using sequence codes which is obtained weighting factoes and maximal-sequence codes having individual phase shifting quantities.

Description: The present invention relates to memory access methods and apparatus. With conventional systems, for example computer systems, robot control systems and the like, a memory and a memory access apparatus are widely employed to suit the demand for storing a very large quantity of data. A magnetic memory device such as a magnetic tape, magnetic disc and bubble memory and a semiconductor memory device such as a bucket brigade device and a charge coupled device are widely employed as the memory because these devices have the advantages that a large memory capacity can easily be obtained and that writing into, reading out and erasing of data can easily be performed, and the like. A data storing system for the memory devices stores specific data at a specific address of the memory device. The disadvantages that arise are that an average retrieval time for reading desired data out from the memory is lengthened, and processing speed of the system as a whole is lowered further as a result of increasing quantities of data which are storted in the memory device. The disadvantage that also arises is that data in a partial region of the memory device cannot be regenerated when the partial region of the memory device is destroyed because specific data is stored at a specific address of the memory device. It is known that an error correction code is added to a series of data for regenerating partial data when the partial data are damaged. When the number of bits which are to be corrected is increased, the error correction code is lengthened. As a result, the disadvantage that arises is that the quantity of data which are stored in the memory is decreased. When the number of bits which are to be corrected is increased, the error correction processing becomes complicated. As a result, the disadvantage that also arises is that the processing speed of the system as a whole is lowered. A hologram memory is proposed which stores a large quantity of data as holograms by applying Fourier transformation, optically. When the hologram memory is employed, redundancy of the stored information can be increased so as to regenerate the original data with fairly high accuracy when the stored information is partially damaged. But the disadvantage that arises is that not only a laser beam source having strong output power is required, but also transforming circuitry for transforming light signals to electric signals and vice versa are needed so as to complicate the arrangement of the system as a whole, and to result in a higher cost. From US-A-4 567 588 a synchronization system for use in direct sequence spread spectrum signal receiver is known. Different signals are multiplexed and convoluted by different kinds of codes. The different kinds of codes have a very low cross-correlation at the whole. Thus, an independent synchronized detecting circuit is necessary for every channel for transmission. From Tjidschrift Van Het Nederlands Electronica- en Radiogenootschap, vol. 49, No. 2, 1984, E.F. Defrettere, P. Kroon "Compression and Quantization of Speech", pp. 33-38, it is known that compression and quantization of signals may be applied to efficient storage and/or transmission. It is an object of the present invention to store plural data in a predetermined region of a memory device in an electrically diffused and convoluted manner, using a simple apparatus in a quick way. This object is solved by a memory access method comprising the steps of claim 1. When this memory access method is employed, each data is electrically diffused by modulating the pseudo noise having phase shifting applied with a corresponding quantity based upon the data. And all data are written into the cyclic memory means, which has the capacity corresponding to the code length of the pseudo noise, by convoluting all modulated pseudo noises. Thereafter, the original data is regenerated by obtaining a cross correlation value between the modulated pseudo noises read out from the cyclic memory means and a pseudo noise having phase shifting applied with a corresponding quantity. As is apparent from the foregoing, all data are stored in the cyclic memory means in an electrically diffused condition to the entire extent of the cyclic memory means by the pseudo noises, thereby data is maintained with high secrecy of and data are regenerated despite of damage to the cyclic memory means to some degree. When the memory access method of claim 2 is employed, the weighted data is obtained by obtaining a cross correlation value between the modulated pseudo noises read out from the cyclic memory means and the time sequence code which is obtained based upon the weighting factors and the plural pseudo noises. This memory access method easily obtains cross-correlation results for the original data stored therein with weighting factors. When the memory access method of claim 3 is employed, each weighted data is electrically diffused by modulating the time sequence code which is obtained based upon weighting factors for each data and the plural pseudo noises with each data, then all weighted data are written into the cyclic memory means having the capacity corresponding to the code length of the pseudo noise by convoluting all modulated time sequence codes. Thereafter, the modulated time sequence codes are read out from the cyclic memory means and the weighted data is obtained by obtaining cross-correlation value of the modulated time sequence codes with the pseudo noise having phase shifting applied with a corresponding quantity. This memory access method stores convolution data which are obtained by convoluting weighting factors with the original data. It is preferable (claim 4) that the plural data to be rewritten are differences between new writing data and data already written in the cyclic memory means when the new writing data are to be written into the cyclic memory means. When this memory access method is employed, it is sufficient to establish the differences as writing data merely, renewal of data is easily performed. It is also preferable (claim 3) that the pseudo noise is a maximal-sequence code. In this case, the maximal-sequence code must have a code length longer than a total length of the plural data. When a maximal-sequence code is employed as a pseudo noise, a pseudo noise having a code length corresponding to a number of stages of the cyclic memory means can easily be obtained. Therefore, a change in the number of stages of the cyclic memory means can easily be dealt with. It is further preferable that the plural data include a standard data and intermediate value data and the original data with the standard data removed is regenerated based upon the regenerated standard data. When this method is employed, intermediate value data are regenerated based upon the regenerated standard data. The object is also solved by a memory access apparatus with the features of claim 8. When this memory access apparatus is employed, each pseudo noise is modulated by the modulation means with each data, each pseudo noise having phase shifting applied with a corresponding quantity, then all modulated pseudo noises are convoluted by the convolution means and the convoluted signal data is stored in the cyclic memory means. Thereafter, the convoluted signal data is read out from the cyclic memory means by the read out means, then the original data is regenerated and output therefrom by obtaining cross-correlation value between the convoluted signal data read out from the cyclic memory means and a pseudo noise having phase shifting applied with a corresponding quantity. As is apparent from the foregoing, data are maintained with high secrecy because all data are electrically diffused by the pseudo noises and stored within the whole stage of the cyclic memory means, and the original data can be regenerated despite of damage to the cyclic memory means, to some degree. Preferred apparatus can be taken from the corresponding subclaims. When the memory access apparatus of claim 9 is employed, the weighted data is obtained by obtaining the cross correlation value between the convoluted signal data read out from the cyclic memory means and the time sequence code which is obtained based upon the weighting factors and the plural pseudo noises. This memory access apparatus easily obtains correlation results for the original data stored therein with weighting factors. When the memory access apparatus of claim 10 is employed, each weighted data is electrically diffused by modulating the time sequence code which is obtained based upon weighting factors for each data and the plural pseudo noises with each data, then all weighted data are written into the cyclic memory means having the capacity corresponding to the code length of the pseudo noise by convoluting all modulated time sequence codes. Thereafter, the convoluted signal data are read out from the cyclic memory means and the weighted data is obtained by obtaining the cross-correlation value between the convoluted signal data and the pseudo noise having phase shifting applied with a corresponding quantity. This memory access apparatus stores convolution data which are obtained by convoluting weighting factors to the original data. It is preferable (claim 11) that the convolution means convolutes new writing data and data already written in the cyclic memory means. When this memory access apparatus is employed, renewal of data is easily performed. It is also preferable (claim 12) that the pseudo noise is a maximal-sequence code. In this case, the maximal-sequence code must have a code length longer than a total length of the plural data. When a maximal-sequence code is employed as a pseudo noise, a pseudo noise having a code length corresponding to the number of stages of the cyclic memory means can easily be obtained. Therefore, a change in the number of stages of the cyclic memory means can easily be dealt with. It is further preferable (claim 13) that the plural data include a standard data and intermediate value data and the regeneration means includes restoration means for restoring data with the standard data removed based upon the regenerated standard data. When this apparatus is employed, intermediate value data are regenerated based upon the regenerated standard data. It is still further preferable (claim 14) that the cyclic memory means includes two stages of registers, an adder interposed therebetween and plural stages of first-in first-out memory. It is also preferable (claim 15) that the cross-correlation means includes a register, an operational amplifier for performing predetermined operations based upon the content of the register, the received data and a maximal-sequence code to obtain operation results and for supplying the operation result to the register, and the regeneration means is an inverter for outputting regeneration data based upon the uppermost digit of the register. It is further preferable (claim 16) that the cross-correlation means includes a multiplier for multiplying the pseudo noise phase shifted by quantities corresponding to the individual quantities with read out pseudo noise, an adder and a register, wherein output data from the adder is supplied to the register and output data from the register is output as regeneration data and is supplied to the adder together with output data from the multiplier. It is of course possible that pseudo noises having significant auto-correlation characteristics other than the maximal-sequence code are employed. More specifically, a maximal-sequence code is the longest code sequence which can be generated by shift registers having a predetermined number of stages or a feedback code generator made of delay devices, and is so called the maximal periodic sequence or the longest sequence. The maximal-sequence code may be in the form of a modulo-j code where j is an arbitrary number; a binary system code is used in the following explanation. The binary system code has the following characteristics: (1) The difference between the number of appearances of "0" and the number of appearances of "1" within one period of a series is only 1 bit. That is, when a binary system code having a bit length of 2 n -1 is employed, the number of appearances of "1" is 2 n-1 , while the number of appearances of "0" is 2 n-1 -1. Concretely, when n=3, the binary system code is "1 0 1 1 1 0 0" for example, and the number of appearances of "1" is greater than that of "0" by 1. (2) The statistical distribution of "0" and "1" is constant. The relative position of strings of "0" and "1" vary depending on the binary system code, but the number of appearances of a string having a predetermined length is constant for all binary system codes which have the same bit length. (3) Referring to Fig. 9, the auto-correlation value of the binary system code is 2 n -1 (which is equal to the bit length) for 0 bit shift, while the auto-correlation value of the binary system code is -1 for an arbitrary number of bit shifts other than the bit shift range of 0±1. The auto-correlation value of -1 is obtained by counting the number of coincidence portions, and the value of -1 indicates that the number of dissonances is greater than the number of coincidences by 1. Further, the auto-correlation value varies linearly from -1 to 2 n -1 within the bit shift range of 0±1. (4) Summation with a modulo-2 of an original binary system code and a phase shifted original binary system code with a predetermined phase shifting quantity is another phase shifted original binary system code which phase shifting quantity is different from the predetermined phase shifting quantity. (5) All inner states which are able to be obtained by an n-step shift register generator appear in a binary system code at a predetermined clock time within one period. That is, each inner state appears only one time, and within only one clock time. It is widely known that noise has significant auto-correlation characteristics and the auto-correlation values of noise are negligible when noise is shifted slightly. The maximal-sequence code can be used as a pseudo noise because the maximal-sequence code has a characteristic similar to the characteristic mentioned above, following the lengthening of the bit length. The inventor advanced the research for pseudo noises represented by maximal-sequence codes and found new characteristics as follows: When the code of "0" in maximal-sequence codes is replaced with the code of "-1", cross-correlation of a standard maximal-sequence code with a serial code which is obtained by adding plural maximal-sequence codes, each maximal-sequence code being obtained by phase shifting the standard maximal-sequence code by an individual phase, is the same as a sum of cross-correlations of the standard maximal-sequence code with an individual maximal-sequence code. The difference between the peak value and the lowest value of the cross-correlation is a constant value which is determined based upon the bit length of the maximal-sequence code, despite the varying of the peak value and the lowest value of the cross-correlation in correspondance with the addition number of the maximal-sequence codes. The inventor worked out this present invention based on the findings. When a standard maximal-sequence code "1 0 1 1 1 0 0" having a bit length of 2³-1, shown in Fig. 8-A1, is taken into consideration for example, maximal-sequence codes which are phase shifted with +1 bit, +2 bits and +4 bits are "0 1 0 1 1 1 0", "0 0 1 0 1 1 1" and "1 1 0 0 1 0 1" (refer to Figs. 8-B1, 8-C1 and 8-D1). A sequence code which is obtained by adding the maximal-sequence codes phase shifted with +1 bit, +2 bits and +4 bits respectively, is shown in Fig. 8-E1. When cross-correlation of these sequence codes with the standard maximal-sequence code is obtained, peaks having the same value as the peak of the auto-correlation (refer to Fig. 8-A2) are obtained respectively at the phase shifted position with +1 bit, +2 bits and +4 bits (refer to Figs. 8-B2, 8-C2 and 8-D2) with respect to the auto-correlation for the maximal-sequence codes which are phase shifted with +1 bit, +2 bits and +4 bits. Furthermore, peaks having a lower value than the peak of the auto-correlation shown in Fig. 8-A2 are obtained at every phase shifted position with +1 bit, +2 bits and +4 bits (refer to Fig. 8-E2) with respect to the auto-correlation for the convoluted sequence codes when the cross-correlation of the sequence code shown in Fig. 8-E1 with the standard maximal-sequence code is obtained. The peak value of the cross-correlation shown in Fig. 8-E2 is 5, and is lower than the peak values 7 (= 2³-1) of the cross-correlation shown in Figs. 8-B2, 8-C2 and 8-D2 by 2. The value at a position apart from the peak by more than 1 bit is -3 in Fig. 8-E2, while each value at positions apart from the peak by more than 1 bit is -1, as shown in Fig. 8-B2, 8-C2 and 8-D2. The former value - 3 is lower than the latter values -1 by 2. That is, cross-correlation which is the same as the cross-correlation shown in Fig. 8-E2 is obtained by simply adding the cross-correlations shown in Figs. 8-B2, 8-C2 and 8-D2. The difference between the maximum value and the minimum value is 8 (=2³) for all cross-correlations. Furthermore, when maximal-sequence codes which are phase shifted with 0 bit to +6 bits respectively are added, the peak value of the cross-correlation is 1. The peak value never becomes negative despite varying of the peak value in correspondance with the number of maximal sequence codes to be added. This present invention is made based on the findings mentioned above. Each data is used to modulate the pseudo noise which is obtained by applying phase shifting with predetermined phase to a pseudo noise having significant auto-correlation characteristics and the modulated pseudo noises are convoluted and written into the cyclic memory means, thereby all data are electrically diffused and stored in the cyclic memory means. When desired data are to be regenerated, the convoluted signal is read out from the cyclic memory means, then the cross-correlation value is obtained based upon the read out convoluted signal and the pseudo noise corresponding to the desired data, thereafter, the original data is regenerated based upon the cross-correlation value. Also, data applying weighting to each data may be stored in the cyclic memory means and the weighted data may be regenerated or obtained. The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read with the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of an embodiment of the memory access apparatus in accordance with the present invention; Figure 2 is a block diagram showing an arrangement of an apparatus for generating a maximal-sequence code; Figure 3 is a block diagram of another embodiment of the memory access apparatus in accordance with the present invention; Figures 4, 5, 6(A), 6(B), 6(C), 7(A), 7(B), and 7(C) are block diagrams of further embodiments of the memory access apparatus in accordance with the present invention, respectively; Figures 8(A1) through 8(E1) and 8(A2) through 8(E2) are diagrams useful for explaining newly found characteristics of a maximal-sequence code; and Figure 9 is a diagram useful for explaining widely known characteristics of a maximal-sequence code. Detailed Description of the Preferred Embodiments Figure 1 is a block diagram of an embodiment of the memory access apparatus in accordance with the present invention. This memory access apparatus is arranged to store data in a diffused condition in a cyclic memory 1 and to read out data therefrom. The cyclic memory 1 has two stages of registers 12 and 13, an adder 11 interposed therebetween and (2 n -3) stages of FIFO-memory (first-in first-out memory) 14. The reference numeral 15 indicates a bus buffer and the reference numeral 16 indicates a convolution bus. The registers 12 and 13 and the FIFO-memory 14 are supplied by a common timing clock. Writing data and a maximal-sequence code m(t+jΔT) (where j is an integer less than the number of bits of the maximal-sequence code) as a pseudo noise for writing are supplied to a multiplier 2. The output data from the multiplier 2 is supplied to the adder 11. The output data from the register 12 is supplied to one input terminal A of an operation amplifier 31 while contents of a register 32 are supplied to another input terminal I of the operation amplifier 31 which also is supplied with a maximal-sequence code m(t+jΔT) as a pseudo noise for reading, which code acts as a control signal. The operation result output from the output terminal OP of the operation amplifier 31 is fed back to the register 32. The uppermost digit from the register 32 is output as a regenerated signal through an inverter 33. The operation amplifier 31 is arranged to output the operation result in the form of a compliment of 2 and to perform an operation of OP=I+A when the maximal-sequence code is "1" otherwise to perform an operation of OP=I-A. The register 32 is arranged to output the uppermost digit and to be cleared to 0 at every clock signal supplying timing, the number of clock signals being equal to the number of bits of the maximal-sequence code. Figure 2 is a block diagram showing an arrangement of an apparatus 9 for generating a maximal-sequence code. A number j of shift registers 91, 92...9j are serially connected, and the output data from the shift register 9j of the output stage and output data from the shift register of a predetermined stage are applied to an exclusively logical add operation to obtain an exclusively logical add result. The exclusively logical add result is then supplied to the shift register 91 of the first stage. The number j of stages of the shift registers is determined as 2 j -1≧L (where L is a number of writing data), and the exclusively logical add result based upon the shift register of the predetermined stage (predetermined tap position) is fed back to the shift register of the first stage so as to repeat the same bit pattern with a cycle of 2 j -1 times. Further, a conversion circuit (not shown) is provided for converting the "0" level of the binary data output from the shift register 9j of the output stage to the "-1" level. Operations of the memory access apparatus are as follows. (1) Operations for writing data in the cyclic memory 1: When data is to be written into the cyclic memory 1 having two stages of registers 12 and 13 and (2 n -3) stages of FIFO-memory 14, it is sufficient that writing data and the maximal-sequence code m(t+jΔT) as a pseudo noise for writing are supplied to the multiplier 2. Then, the output data from the multiplier 2 and the output data from the register 12 are added by the adder 11 and the addition result is supplied to the register 13. At this timing, data held by the register 13 is supplied to the first stage of the FIFO-memory 14, data held by the FIFO-memory 14 are shifted by every one stage and data held by the output stage of the FIFO-memory 14 are supplied to the register 12 through the bus buffer 15. Data is then written into the cyclic memory in a diffused condition to (2 n -1) bits by repeating the above mentioned operations by 1 period of the maximal-sequence code. When plural data are to be written into the cyclic memory 1, it is sufficient that operations similar to the above mentioned operations are performed using a maximal-sequence code having phase shifting applied with different phase shifting quantities, thereby plural data are written into the cyclic memory 1 in a diffused to (2 n -1) bits and convoluted condition. It is supposed that the binary logic input data "1", "1", "0" and "1" are to be sequentially written into the cyclic memory 1. Maximal-sequence codes "-1 1 -1 1 1 1 -1", "-1 - 1 1 -1 1 1 1", "1 -1 -1 1 -1 1 1" and "1 1 -1 -1 1 -1 1" which are sequentially phase shifted from a standard maximal-sequence code "1 -1 1 1 1 -1 -1" by 1 bit are supplied to the multiplier 2 in correspondance with each binary logic input data. The multiplier 2 first outputs a sequence code "-1 1 -1 1 1 1 -1" so as to write the sequence code into the registers 12 and 13 and the FIFO-memory 14. The multiplier 2 then outputs a sequence code "-1 -1 1 -1 1 1 1" so as to write the sequence code into the registers 12 and 13 and the FIFO-memory 14, thereby the content of the registers 12 and 13 and the FIFO-memory 14 becomes "-2 0 0 0 2 2 0". The multiplier 2 then outputs a sequence code "0 0 0 0 0 0 0" so as to write the sequence code into the registers 12 and 13 and the FIFO-memory 14, thereby the content of the registers 12 and 13 and the FIFO-memory 14 is "-2 0 0 0 2 2 0". The multiplier 2 finally outputs a sequence code "1 1 -1 -1 1 -1 1" so as to write the sequence code into the registers 12 and 13 and the FIFO-memory 14, thereby the content of the registers 12 and 13 and the FIFO-memory 14 becomes "-1 1 -1 -1 3 1 1". (2) Operations for reading data out from the cyclic memory 1: When data is to be read out from the cyclic memory 1 having two stages of registers 12 and 13 and (2 n -3) stages FIFO-memory 14, only the corresponding data is regenerated by supplying the maximal-sequence code m(t+jΔT) to the operation amplifier 31 as a control signal, the maximal-sequence code having phase shifting applied with the phase shifting quantity corresponding to the data to be read out, because the output data from the register 12 is supplied to the operation amplifier 31. It is supposed that the content of the registers 12 and 13 and the FIFO-memory 14 is "-1 1 -1 -1 3 1 1" as shown in the above mentioned specific example. The maximal-sequence code "0 1 0 1 1 1 0" which is phase shifted a standard maximal-sequence code with 1 bit is supplied to the operation amplifier 31 as the control signal. Then the following operations are sequentially performed. 0-(-1)=1 1+1=2 2-(-1)=3 3+(-1)=2 2+3=5 5+1=6 6-1=5 The uppermost bit "0" of the finally obtained value 5 is output from the register 32. The uppermost bit is supplied to the inverter 33 so as to convert to "1", thereby the original binery logic input data "1" is regenerated. The other binary logic input data are also regenerated by performing the similar operations based upon maximal-sequence codes which are phase shifted with 2 bits, 3 bits and 4 bits respectively. In this embodiment, data can be input through the convolution bus 16 by controlling the bus buffer 15 disenable state. The bus buffer 15 can be provided at an outer side position with respect to the branch for feedback when the bus buffer 15 is a bidirectional bus buffer. Second Embodiment Figure 3 is a block diagram of another embodiment of the memory access apparatus in accordance with the present invention. This embodiment differs from the first embodiment in that the standard maximal-sequence code modulated based upon standard data having a known value is convoluted to other modulated maximal-sequence codes and written into the registers 12 and 13 and the FIFO-memory 14. An operation amplifier 34 which is supplied with the standard maximal-sequence code as a control signal and a corresponding register 35 are provided. The inverter 33 is omitted and a regeneration section 37 to which contents of the registers 32 and 35 are supplied is provided. The regeneration section 37 receives the cross-correlation value T output from the register 32 and the standard cross-correlation value output from the register 35 and performs predetermined operations. When the standard data is "0", the standard cross-correlation value becomes the minimum cross-correlation value min, then it is sufficient that operation of 2⁻³ (T-min) is performed. The data which is obtained by modulating the standard maximal-sequence code by the standard data is not actually required to be convoluted. Otherwise when the standard data is "1", the standard cross-correlation value becomes the maximum cross-correlation value max, then it is sufficient that operation of 2⁻³(max-T) is performed. It is supposed that the standard data is "0", intermediate value data for writing are "0.5", "0.8" and "1" and maximal-sequence codes "-1 1 -1 1 1 1 -1", "-1 -1 1 -1 1 1 1", "1 -1 -1 1 -1 1 1" and "1 1 -1 -1 1 -1 1" which are sequentially phase shifted a standard maximal-sequence code "1 -1 1 1 1 -1 -1" by 1 bit are assigned to each intermediate value data. A sequence code "-0.5 0.5 -0.5 0.5 0.5 0.5 -0.5" is first written into the registers 12 and 13 and the FIFO-memory 14 based upon the first intermediate value data "0.5" and the maximal-sequence code "-1 1 -1 1 1 1 -1". A sequence code "-0.8 -0.8 0.8 -0.8 0.8 0.8 0.8" is then overwritten based upon the next intermediate value data "0.8" thereby a sequence code "-1.3 -0.3 0.3 - 0.3 1.3 1.3 0.3" is held by the registers 12 and 13 and the FIFO-memory 14. A sequence code "1 -1 -1 1 -1 1 1" is further overwritten based upon the data "1" thereby a sequence code "-0.3 -1.3 -0.7 0.7 0.3 2.3 1.3" is held by the registers 12 and 13 and the FIFO-memory 14. The maximal-sequence code "0 1 0 1 1 1 0" is supplied to the operation amplifier 31 as the control signal. Then the following operations are sequentially performed based upon the data which are sequentially output from the register 12. 0-(-0.3)=0.3 0.3+(-1.3)=-1.0 -1.0-(-0.7)=-0.3 -0.3+0.7=0.4 0.4+0.3=0.7 0.7+2.3=3.0 3.0-1.3=1.7 The finally obtained value 1.7 is supplied to the regeneration section 37 as the cross-correlation value T. The maximal-sequence code "1 0 1 1 1 0 0" is supplied to the operation amplifier 34 as the control signal. Then the following operations are sequentially performed. 0+(-0.3)=-0.3 -0.3-(-1.3)=1.0 1.0+(-0.7)=0.3 0.3+0.7=1.0 1.0+0.3=1.3 1.3-2.3=-1.0 -1.0-1.3=-2.3 The finally obtained value -2.3 is supplied to the regeneration section 37 as the minimum cross-correlation value min. Then the regeneration section 37 performs the operation 2⁻³{1.7-(-2.3)} and obtains the original intermediate value "0.5". The other intermediate values are also regenerated by performing the similar operations based upon maximal-sequence codes, each maximal-sequence code corresponding to each intermediate value. When the data held in the registers 12 and 13 and the FIFO-memory 14 is to be renewed, for example the above intermediate value "0.5" is to be renewed, it is sufficient that the difference value "0.2" and the same maximal-sequence code "-1 1 -1 1 1 1 -1" are supplied to the multiplier 2. As is apparent from the foregoing, the original data is not required to be erased, thereby the renewal of data can be simplified. Third Embodiment Figure 4 is a block diagram of a further embodiment of the memory access apparatus in accordance with the present invention. This embodiment differs from the second embodiment in that a (2 n -1)-number of memory elements 21 are connected to a data bus 22 instead of serially connecting the registers 12 and 13 and the FIFO-memory 14, data is read out from and written into the memory elements 21 through the data bus 22, read out data through the data bus 22 is supplied to the adder 11 which also is supplied with the output data from the multiplier 2, and the output data from the adder 11 is written into the memory elements 21 by means of the data bus 22. The memory elements 21 substantially constitute a cyclic memory because read out access and write into access are sequentially performed for each individual memory element 21 through the data bus 22. In this embodiment, when any one or more of the memory elements are destroyed, only the destroyed memory elements are impossible to access while the other memory elements are accessable. And one data is not held in only one memory element but is held in the plural memory element in a diffused manner. As a result, when the memory elements are partially destroyed, data can be written into the memory elements and data can be read out from the memory elements with fairly high accuracy. Fourth Embodiment Figure 5 is a block diagram of still another embodiment of the memory access apparatus in accordance with the present invention. This embodiment differs from the second embodiment in that a read out access apparatus consists of a multipler 41, an adder 42 and a register 43. The output data from the register 12 and a sequence code which is obtained based upon the difference of a maximal-sequence code corresponding to reading out data and the standard maximal-sequence code are supplied to the multiplier 41. The output data from the multiplier 41 are output to an exterior apparatus through the adder 42 and the register 43. The output data from the register 43 are also fed back to the adder 42. As is apparent from the foregoing, the arrangement of the memory access apparatus is more simplified. Operations of the read out access apparatus are as follows. It is supposed that the standard maximal-sequence code is "-1 1 1 1 -1 -1 1", a standard data Z1 and multiple value data Z2, Z3 and Z4 which are already written are "0", "0.5", "0.8" and "1" respectively. Convoluted data Sj (where j=1, 2,...7) of "2.3 0.3 -1.3 -0.3 -0.7 0.7 1.3" are sequentially output from the register 12. As to the regeneration data R2, R3 and R4 to be regenerated based upon the convoluted data and maximal-sequence codes m1j, m2j, m3j and m4j corresponding to the standard data R1 and the regeneration data R2, R3 and R4 respectively, the regeneration data R2, R3 and R4 are unknown, the standard data R1 is 0 and the maximal-sequence codes m1j, m2j, m3j and m4j are represented as follows. m1j="-1 1 1 1 -1 -1 1" m2j="1 1 1 -1 -1 1 -1" m3j="1 1 -1 -1 1 -1 1" m4j="1 -1 -1 1 -1 1 1" The unknown regeneration data Ri are represented by the equation The code m2j-m1j is "2 0 0 -2 0 2 -2", the code m3j-m1j is "2 0 -2 -2 2 0 0", the code m4j-m1j is "2 -2 -2 0 0 2 0", the code Sj(m2j-m1j) is "4.6 0.0 0.0 0.6 0.0 1.4 -2.6", the code Sj(m3j-m1j) is "4.6 0.0 2.6 0.6 -1.4 0.0 0.0", the code Sj(m4j-m1j) is "4.6 -0.6 2.6 0.0 0.0 1.4 0.0". Then the regeneration data R2, R3 and R4 are obtained by the following equations. R2=(4.6+0.6+1.4-2.6)/8=0.5 R3=(4.6+2.6+0.6-1.4)/8=0.8 R4=(4.6-0.6+2.6+1.4)/8=1.0 As a result, the regeneration data R2, R3 and R4 coincide with the multiple value data Z2, Z3 and Z4. Fifth Embodiment Figures 6-A, 6-B and 6-C are block diagrams of yet other embodiments of the memory access apparatus in accordance with the present invention. These block diagrams correspond to the embodiments shown in Figs. 3, 4 and 5 respectively. The embodiments shown in Figs. 6-A, 6-B and 6-C differ from the embodiments shown in Figs. 3, 4 and 5 in that a sequence code for writing is supplied to the multiplier 2 instead of the maximal-sequence code m(t+jΔT), the sequence code for writing being obtained based upon desired weighting factors wj and the maximal-sequence code m(t+jΔT). The weighting factor w0 is determined to 0. In these embodiments, when plural data X1, x2,...xL are written into the cyclic memory 1 based upon the maximal-sequence codes having the phase shifting quantities which are the same as the foregoing embodiments, the plural data are written into the cyclic memory 1 in a form of w1x1+w2x2+...+wLxL instead of the form x1+x2+...+xL. As is apparent from the foregoing, previously multiplying the weighting factors and the plural data is not needed, thereby memory access for writing is simplified. These embodiments are applicable to an input layer of a studying type neural network. In the studying type neural network, it is necessary that weighting factors change based upon the results of studying, therefore these embodimenta are applicable to store sequence codes and bus output of each layer which are obtained by studying and the like. Sixth Embodiment Figures 7-A, 7-B and 7-C are block diagrams of still further embodiments of the memory access apparatus in accordance with the present invention. These block diagrams correspond to embodiments shown in Figs. 3, 4 and 5 respectively. The embodiments shown in Figs. 7-A, 7-B and 7-C differ from the embodiments shown in Figs. 3, 4 and 5 in that a sequence code for reading or a sequence code for reading is supplied to the operation amplifier 31 and the multiplier 41 instead of the maximal-sequence code m(t+jΔT) or the sequence code (mij-m1j), the sequence code for writing being obtained based upon desired weighting factors wj and the maximal-sequence code m(t+jΔT) and the sequence code for writing being obtained based upon desired weighting factors wj and the sequence code (mij-m1j). The weighting factor w0 is determined to 0. When the sequence code for writing C(t) is supplied, the cross-correlation value C(t+kΔT) is obtained based upon the convoluted read out data and the sequence code for reading C(t) and the cross-correlation value min corresponding to the "0" level is also obtained. Then, the output value X which is equivalent to each data includes the weighting factor therein by performing, for example, the operation of with the regeneration section 37. When the sequence code for writing Ci′(t) is supplied, that is a sum δ=w2Z2+w3Z3+w4Z4 of signals which are obtained by multiplying the weighting factors w2, w3 and w4 to the multiple value data Z2, Z3 and Z4 is to be obtained, the sum δ is obtained by obtaining the cross-correlation value based upon a previously obtained sequence code because the sum δ is generally represented by the equation The weighting factor w1 always has a value 0 corresponding to a standard signal channel. It is supposed that the weighting factors w2, w3 and w4 are 1.0, 2.5 and -1.5 respectively, a code w1(m1j-m1j) is "0 0 0 0 0 0 0", a code w2(m2j-m1j) is "2 0 0 -2 0 2 -2", a code w3(m3j-m1j) is "5 0 -5 -5 5 0 0" and a code w4(m4j-m1j) is "-3 3 3 0 0 -3 0", then the sequence code is "0.5 0.375 -0.25 -0.875 0.625 -0.125 -0.25". Further, the code Sj·Cj is "1.15 0.1125 0.325 0.2625 -0.4375 -0.0875 -0.325", then the sum is 1.0. The sum δ coincides with a sum calculated by the equation of δ=w2R2+w3R3+w4R4 . As is apparent from the foregoing, the sum δ including the weighting factors wi is easily obtained without calculating the minimum cross-correlation value min by previously obtaining the sequence code and supplying the sequence code Cj to the operation amplifier 34. These embodiments are also applicable to the studying type neural network. The memory access apparatus according to the present invention is not limited to the embodiments mentioned above. The memory access apparatus may perform writing and reading data using pseudo noise having significant auto-correlation characteristics other than the maximal-sequence code, for example random numbers, a balowa-sequence code and the like. Further, a sequence code for writing and for reading may be obtained using these sequence codes. Furthermore, when the memory access apparatus is applied to writing and reading multiple value data, an arbitrary value within the range of 0-1 may be employed as a standard data. The terms and expressions which have been employed are used as terms of description and not of limitations, and there is no intention, in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention as claimed.

Claims: A memory access method comprising the steps of: (a) obtaining plural pseudo noises for writing by applying phase shifting to a pseudo noise which has significant auto-correlation characteristics, each pseudo noise for writing being phase shifted by an individual quantity; (b) modulating each pseudo noise for writing based upon plural data to obtain modulated pseudo noises; (c) writing modulated pseudo noises into a cyclic memory means (1, 12, 13, 14, 21) which has a capacity corresponding to a code length of the pseudo noises; (d) reading out the modulated pseudo noises from said cyclic memory means (1, 12, 13, 14, 21); and (e) regenerating original data by obtaining a cross-correlation value between the modulated pseudo noises read out from said cyclic memory means (1, 12, 13, 14, 21) and a pseudo noise phase shifted by a quantity corresponding to the individual quantity. A memory access method as set forth in claim 1, wherein step (e) is replaced by: (f) obtaining weighted data by obtaining pseudo noises read out from said cyclic memory means (1, 12, 13, 14, 21) and a time sequence code C(t) which is obtained based upon weighting factors for the data and the plural pseudo noises. A memory access method as set forth in claim 2, comprising the steps of: modulating the time sequence code based upon the plural data to obtain modulated time sequence codes; (g) writing the modulated time sequence codes into a cyclic memory means (1, 12, 13, 14, 21) which has a capacity corresponding to a code length of the pseudo noise; (h) reading out the modulated time sequence codes from said cyclic memory means (1, 12, 13, 14, 21); and (i) obtaining weighted data by obtaining a cross-correlation value of the modulated time sequence codes read out from said cyclic memory means (1, 12, 13, 14, 21) and a pseudo noise phase shifted by a quantity corresponding to the individual quantity. A memory access method as set forth in one of claims 1 to 3, wherein the plural data to be rewritten are differences between new writing data and data already written in said cyclic memory means (1, 12, 13, 14, 21) when the new writing data are to be written into said cyclic memory means (1, 12, 13, 14, 21). A memory access method as set forth in one of claims 1 to 4, wherein the pseudo noise is a maximal-sequence code which has a code length longer than a total length of the plural data. A memory access method as set forth in one of claims 1 to 5, wherein the plural data include a standard data and intermediate value data and the weighted data with the standard data removed is obtained based upon the regenerated standard data. A memory access method as set forth in one of claims 1 to 5, wherein the plural data include a standard data and intermediate value data and the weighted data with the weighted standard data removed is obtained based upon the obtained weighted standard data. A memory access apparatus comprising: (i) pseudo noise generating means (9, 91, 92, ...9j) for generating plural pseudo noises for writing based upon a pseudo noise having significant auto-correlation characteristics, said plural pseudo noises for writing being phase shifted by individual quantities; (ii) modulation means (2) for modulating said plural pseudo noises for writing based upon plural data to provide modulated pseudo noises; (iii) convolution means (11) for convoluting said modulated pseudo noises to provide convoluted signal data; (iv) cyclic memory means (1, 12, 13, 14, 21) for sequentially storing said convoluted signal data, said cyclic memory means (1, 12, 13, 14, 21) having a capacity corresponding to a code length of said pseudo noise; (v) read out means (31, 34, 41) for reading out said convoluted signal data from said cyclic memory means (1, 12, 13, 14, 21); (vi) cross-correlation means (31, 32, 33, 34, 35, 41, 42, 43) for obtaining a cross-correlation value between said convoluted signal data read out from said cyclic memory means (1, 12, 13, 14, 21) and said pseudo noise phase shifted by quantities corresponding to said individual quantities; and (vii) regeneration means (33) for regenerating said plural data based upon said cross-correlation value. A memory access apparatus as set forth in claim 8, wherein (viii) said cross-correlation means (31, 32, 33, 34, 35, 41, 42, 43) obtaining a cross-correlation value between said convoluted signal data read out from said cyclic memory means (1, 12, 13, 14, 21) and a time sequence code which is obtained based upon weighting factors for data and said plural pseudo noises; and (ix) comprising generation means (9, 91, 92, ... 9j) for generating plural weighted data based upon said cross-correlation value. A memory access apparatus as set forth in claim 8 or 9, comprising; (x) time sequence code generating means (9, 91, 92, ... 9j) for generating said time sequence code based upon weighting factors for data which is to be stored and said pseudo noises; (xi) said modulation means (2) modulating said time sequence code based upon plural data which are to be stored to provide modulated time sequence codes; and (xii) said convolution means (11) convoluting said modulated time sequence codes to provide convoluted signal data. A memory access apparatus as set forth in one of claims 8 to 10, wherein said convolution means (11) convolutes data to the signal data already written in said cyclic memory means (1, 12, 13, 14, 21). A memory access apparatus as set forth in one of claims 8 to 11, wherein said pseudo noise is a maximal-sequence code which has a code length longer than a total length of said plural data. A memory access apparatus as set forth in one of claims 8 to 12, wherein said plural data include a standard data and intermediate value data and said generation means (9, 91, 92, ... 9j) includes restoration means (37) for restoring data with the standard data being removed based upon the regenerated standard data. A memory access apparatus as set forth in one of claims 8 to 13, wherein said cyclic memory means (1, 12, 13, 14, 21) includes two stages of registers, an adder interposed therebetween and plural stages of first-in first-out memory. A memory access apparatus as set forth in one of claims 8 to 14, wherein said cross-correlation means (31, 32, 33, 34, 35, 41, 42, 43) includes a register (32, 35), and an operational amplifier (31, 34) for performing predetermined operations based on the content of said register (32, 35), the received data and a maximal-sequence code to obtain operation results and for supplying the operation result to said register (32, 35), and said regeneration means is an inverter (33) for outputting regeneration data based upon the uppermost digit of said register (32). A memory access apparatus as set forth in one of claims 8 to 15, wherein said cross correlation means (31, 32, 33, 34, 35, 41, 42, 43) includes a multiplier (41) for multiplying said pseudo noise phase shifted by quantities corresponding to said individual quantities with read out pseudo noise, an adder (42) and a register (43), wherein output data from said adder (42) is supplied to said register (43) and output data from said register (43) is output as regeneration data and is supplied to said adder (42) together with output data from said multiplier (41).

Inventors: UEDA TOMOAKI, UEDA, TOMOAKI
Applicants: DAIKIN IND LTD, DAIKIN INDUSTRIES, LIMITED
Application year: 1990
Main classification: G06F11
IPC codes: G06F12, G06F11