A dual channel A/D and D/A converter

Abstract: A dual channel A/D and D/A converter includes a first channel converter, a second channel converter, and a reference generator all formed on a single semi­ conductor substrate. The reference generator is disposed intermediate the first channel converter and the second channel converter for effecting crosstalk isolation therebetween. The dual channel converter is formed of a unique differential structure having "coaxial" isolation of bus lines and interconnections, thereby achieving a higher degree of unwanted channel-­ to-channel crosstalk.

Description: This invention relates generally to telecommunication systems employing A/D and D/A converters and more particularly, it relates to a dual channel A/D and D/A converter for use in a dual subscriber line audio-processing circuit (DSLAC) which performs the functions of converting an analog voice signal into digital PCM samples and converting digital PCM samples back into an analog signal as well as the filtering functions, all associated with the four-wire section of the subscriber line circuitry in a digital switch. In view of the large number of analog/digital interfaces used in telecommunication systems, there has been a great demand for developing low cost integrated circuits to perform the A/D and D/A functions in the subscriber loop. One of the prior art techniques employs an oversampled multi-channel coder which incorporates four A/D converters with transmit low pass filters on one single chip. This prior art technique is disclosed in a research paper written by Bosco Leung entitled "Multi-Channel TCM A/D Interface Using Over-sampling Techniques." It is generally known that A/D converters which have a single ended structure are sensitive to crosstalk from other circuits on a chip. Since there are four converters used on the same chip, there will exist a certain amount of crosstalk between the different channels. Thus, in order to overcome this crosstalk problem the research paper to Leung utilizes a fully differential architecture consisting of a MOS switched-capacitor integrator. The chip with four channels was reported to have a crosstalk of -83 db. However, the use of switched-capacitor techniques for constructing such A/D converters suffers from the limitation of exposing the switching node to a high impedance state and to clock feed-through digital noise. Since the high impedance node takes a long time to settle down, this may in turn cause crosstalk errors and undesirable noise. Further, this approach has the disadvantage of requiring the use of precisely matched capacitances. Therefore, it has been counted in the fabrication of such switched-capacitor integrator devices on a chip using CMOS technology the need of performing an additional masking step which increases manufacturing costs. JP-A-111357 (27/06/84) describes the use of isolation between digital and analog parts of a circuit, and JP-A-73757 (20/03/89) describes a separation layer which separates analog and digital parts of a circuit. The dual channel A/D and D/A converter of the present invention operates in a differential mode and provides an improved crosstalk isolation by a factor of 7 between the two channels without the use of any switched-capacitor technique. The dual channel converter of the present invention is provided as a part of a dual subscriber line audio-processing circuit (DSLAC) manufactured and sold by AMD, Inc., Sunnyvale, California, part No. Am 79C02/A. The DSLAC is an integrated circuit formed of a single-chip package which integrates the key factors of an analog linecard into one programmable, high performance dual CODEC-filter device for two telephone lines via a transformer or a subscriber line interface circuit (SLIC). We will describe a dual channel A/D and D/A converter formed on one silicon substrate, which has traditionally been unavailable. We will describe a dual channel A/D and D/a converter having improved crosstalk isolation. We will describe a dual channel A/D and D/A converter which is formed on a single chip without the use of any switch capacitance techniques or precision capacitors. We will describe a dual channel A/D and D/A converter which includes a first channel converter, a second channel converter, and a reference generator all formed on a single semiconductor substrate, the reference generator being disposed intermediate the first channel converter and the second channel converter for effecting crosstalk isolation therebetween. The present invention provides a dual channel A/D and D/A differential mode converter formed on a single semiconductor substrate and comprising, first channel means for converting analog signals to digital signals and digital signals to analog signals; second channel means formed at a predetermined distance from said first channel means for converting analog to digital signals and digital signals to analog signals; reference voltage generator means connected to the first and second channel means and disposed intermediate said first channel means and said second channel means for effecting crosstalk isolation therebetween; clock logic means connected to said first and second channel means for generating clock signals on clock connection means; and, separate analog and digital ground lines connected to each of said two channel means. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein: Figure 1 is a schematic circuit diagram, partly in block form, of a dual channel A/D and D/A converter of the present invention, illustrating its physical lay-out on a single chip substrate; Figure 2 is a top plan view of the dual channel converter of the present invention, illustrating the physical lay-out of the reference generator block having a barrier; Figure 3 is a cross-sectional view, illustrating isolation utilizing a shield plate; and Figure 4 is a top plan lay-out view, illustrating isolation utilizing a shield plate. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now in detail to the drawings, there is shown in Figure 1 a schematic circuit diagram and physical lay-out of a dual channel A/D (analog-to-digital) and D/A (digital-to-analog) converter 10 of the present invention, which is formed on a single semiconductor integrated circuit chip 12. Each channel of the converter 10 is comprised of a linear, time continuous, oversampling A/D and D/A converter 14a (14b) which operates in a differential mode and is implemented without any switched-capacitor architecture. The converter 10 is formed of a unique differential structure having "coaxial" isolation of bus lines and interconnections, thereby achieving a higher degree of unwanted channel-to-channel crosstalk. In practice, the converter 10 of the present invention was found to produce an improvement by a factor of 7 over the -83 db of crosstalk in the prior art structures. The converter 10 achieved crosstalk isolation of as much as -100 db. The first channel converter 14a is formed of an A/D converter (ADC) circuit 16a and a D/A converter (DAC) circuit 18a. The ADC circuit 16a includes a split input stage 20a formed of two operational amplifiers 22a and 24a which receives an analog voltage input via line 26a. This analog voltage is converted to differential analog current signals by a pair of resistors R1, R2 connected respectively to the outputs of the operational amplifiers 22a, 24a. A differential, time continuous integrator stage 28a receives these current signals via lines 30a and 32a. A six-bit + sign current DAC 34a supplies differential reference currents to the integrator stage 28a via lines 36a and 38a. The respective analog current signals and reference currents are combined at nodes 40a and 42a. The integrator stage 28a may be of the type similar to AMD Model No. 7949TC1 which is formed of several GM and high gain stages, and a common mode stage for maintaining the differential integrator output centered about a zero at all times. A detailed circuit diagram of the integrator stage 28a is shown in Figure 3 of the earlier European application EP-A-0 375 195 that forms part of the state of the art according to Art. 54 (3) EPC. The combined currents are integrated by capacitors C1 and C2 whose voltages are fed to the inputs of a comparator 44a. The comparator 44a may be of the type similar to AMD Model No. 7910 which digitizes the signals by comparing the analog current signals with the reference currents generated by the DAC 34a. A clocked, binary counter 46a is used to increment and decrement the comparison signals from the output of the comparator 44a. The binary counter 46a may be similar to the one commercially available from Texas Instruments under their Part No. 74AS169. The comparator 44a and the counter 46a are driven by a shared clock generator 48 having a frequency 2.048 MHz. The DAC circuit 18a includes operational amplifier 50a and a six-bit current DAC 52a for converting digitized current signals into an analog voltage output at the output of the operational amplifier 50a on line 54a. Similarly, the second channel converter 14b is formed of an A/D converter (ADC) circuit 16b and aD/A converter (DAC) circuit 18b. The ADC circuit 16b includes a split input stage 20b formed of two operational amplifiers 22b and 24b which receives an analog voltage input via line 26b. This analog voltage is again converted to differential analog current signals by a pair of resistors R1, R2 connected respectively to the output of the operational amplifiers 22b, 24b. A differential , time continuous integrator stage 28b similar to the integrator stage 28a receives these current signals via lines 3Db and 32b. A six-bit + sign current DAC 34b supplies differential reference currents to the integrator stage 28b via lines 36b and 38b. The respective analog current signals and reference currents are combined at nodes 40b and 42b. The combined currents are integrated by capacitors C1 and C2 whose voltages are fed to the inputs of a comparator 44b. The comparator 44b digitizes the signals by comparing the analog current signals with the reference currents generated by the DAC 34b. A clocked, binary counter 46b is used to increment and decrement the comparison signals from the output of the comparator 44b. The comparator 44b and the counter 46b both driven by the shared clock generator 48. The DAC circuit 18b includes operational amplifier 50b and a six-bit current DAC 52b for converting digitized current signals into an analog voltage output at the output of the operational amplifier 50b on line 54b. In order to provide isolation between the first channel converter 14a and the second channel converter 14b, a shared reference generator 56 is located substantially in the intermediate area of the chip 12 with the converters 14a and 14b disposed symmetrically on either side of the generator 56. It will be noted that an analog ground bus connection line 58 is fed from a pad AGND1 to both the first channel converter 14a and the reference generator 56. A separate digital ground bus connection line 60, which is susceptible to switching noise, is fed from a pad DGND1 to the current DAC 34a associated with the first channel converter 14a. Thus, this leaves the analog ground bus connection line 58 to be used as a "quiet ground" only for reference and for gate biasing. Further, a first supply voltage connection line 62 is fed from a pad VCC1 to the first channel converter 14a and a second supply voltage line 64 is fed from a pad VSS1 to the first channel converter 14a. As a result, the "high current" flowing in the supply voltage connection lines are separated from the analog ground bus connection line 58, thereby isolating the negative injected noise or IR drops from the common reference generator 56. A first pair of bias connection lines 66, 68 are fed from the reference generator 56 to the first channel converter 14a. Similarly, an analog ground bus connection line 70 is routed from a pad AGND2 to the second channel converter 14b. A separate digital ground bus connection line 72, which is susceptible to switching noise, is routed from a pad DGND2 to the current DAC 34b associated with the second channel converter 14b. A third supply voltage connection line 74 is fed from a pad VCC2 to the second channel converter 14b, and a fourth supply voltage connection line 76 is fed from a pad VSS2 to the second channel converter 14b. A second pair of bias connection lines 78, 80 are routed independently of the bias line 66, 68 from the reference generator 56 to the second channel converter 14b. With reference to Figure 2, it can be seen that the reference generator 56 functions as a distance barrier between the first channel converter 14a and the second channel converter 14b. As a result, the bias connection lines 66, 68 and 70, 80 are split independently to each channel converter for the respective A/D converters 16a (16b) and D/A converters 18a (18b). In order to further isolate the analog reference generator 56 from the high switching digital clocks in the clocked logic block 82, a p⁻-type well region 84 having a depth of approximately 4 µm (microns) is formed by diffusion in an n-type silicon substrate 86. The reference generator 56 is completely fenced with the analog ground bus connection line 58a defining a "quiet ground" connection line. The well region 84 surrounds a substantial portion of the reference generator 56 and functions as a barrier to prevent substrate induced noise from either of the channel converters 14a, 14b. For achieving a higher degree of isolation between the channel converters, the bias connection lines 66, 68 and 78, 80 are "coaxially" shielded. As can be seen from Figures 2 and 3, a shield plate 88 formed of a piece of almosi material is inserted between, for example, the bias connection line 68 and the noisy clock signal lines 89 of the clock logic block 82 and is then grounded by tying the same to the "quiet ground" connection line 58a. Further a p⁻-type well region 90 is formed under the bias connection line 68 so as to ensure isolation from substrate noise. The well region 90 is also tied to the "quiet ground" connection line 58a. In Figure 4, there is shown a plan lay-out view of an exemplary shielding. Area A corresponds to the p⁻-type well region 90 of Figure 3 which is formed in the silicon substrate 86. Area B represents the bias connection line 68 to be protected of Figure 3, which is formed in the well region 90. Area C represents the shield plate 88 which is disposed above the bias connection line 68. Areas D represent the noisy clock signal lines 89 of Figure 3, which have been isolated from the bias connection line 68 via the shield plate 88. Area E represents the "quiet ground" connection line 58a of Figure 3. The connecting area X is a metal layer where contact is made between the "quiet ground" connection line 58a and the p⁻-type well region 90. The connecting area Y is a metal layer where contact is made between the shield plate 88 and the well region 90. From the foregoing detailed description, it can thus be seen that the present invention provides a dual channel A/D and D/A converter which includes a first channel converter, a second channel converter and a reference generator all formed on a single semiconductor substrate. The reference generator is disposed on the substrate intermediate the first channel converter and the second channel converter for effecting crosstalk isolation therebetween. Further, the dual channel converter is formed of a unique differential structure having "coaxial" isolation of bus lines and inter-connections, thereby achieving a higher degree of crosstalk isolation which is on the order of -100 db.

Claims: A dual channel A/D and D/A differential mode converter formed on a single semiconductor substrate (12) and comprising: first channel means (14a) for converting analog signals to digital signals and digital signals to analog signals; second channel means (14b) formed at a predetermined distance from said first channel means (14a) for converting analog to digital signals and digital signals to analog signals; reference voltage generator means (56) connected to the first and second channel means (14a,14b) and disposed intermediate said first channel means (14a) and said second channel means (14b) for effecting crosstalk isolation therebetween; clock logic means (82) for generating clock signals connected to said first and second channel means (14a,14b) by clock connection means (89); and, separate analog and digital ground lines (58,60,70,72) connected to each of said two channel means (14a,14b). A dual channel A/D and D/A converter as claimed in claim 1 characterised in that said ground lines comprise a first analogue ground connection means (AGND1,58) coupled to said first channel means (14a) and defining a quiet analogue ground bus line (58a) which is disposed around said reference voltage generator means (56) to provide isolation from said clock signals. A dual channel A/D and D/A converter as claimed in claim 2, characterised in that said ground lines further comprise a second analogue ground connection means (70) coupled to said second channel means (14b) and separate from said first analogue ground connection means (58). A dual channel A/D and D/A converter as claimed in claim 3 characterised by barrier means (84) formed around said quiet ground bus line (58a) and said reference voltage generator means to provide further isolation between said first and second channel means due to said clock signals. A dual channel A/D and D/A converter as claimed in claim 4, characterised in that said ground lines further comprise a third ground connection means (DGND1,60) coupled to said first channel means (14a) and defining a first separate digital ground bus connection line. A dual channel A/D and D/A converter as claimed in claim 5, characterised in that said ground lines further comprise a fourth ground connection means (72) coupled to said second channel means (14b) and defining a second separate digital ground bus connection line (DGND2). A dual channel A/D and D/A converter as claimed in claim 6, characterised by first and second power supply bus connection means (62,64) for supplying separately first and second power supply voltages to said first channel means (14b). A dual channel A/D and D/A converter as claimed in claim 7, characterised by third and fourth power supply bus connection means (74,76) for supplying separately third and fourth power supply voltages to said second channel means (14b). A dual channel A/D and D/A converter as claimed in claim 8, characterised in that said reference voltage generator means (56) includes first bias connection means (66,68) for supplying bias voltages to said first channel means (14a) and second bias connecting means (78,80) for supplying bias voltages to said second channel means (14b). A dual channel A/D and D/A converter as claimed in claim 9, characterised by electrical shielding means (88) disposed between each of said first and second bias connection means (66,68,78,80) and said clock connection means (89) to provide isolation between said first and second channel means (14a,14b). A dual channel A/D and D/A converter as claimed in claim 10, characterised in that said shielding means (88) is connected to said quiet analogue ground bus line (58a). A dual channel A/D and D/A converter as claimed in claim 11, characterised by a doped well region (90) formed in said semiconductor substrate below each of said first and second bias connection means (66,68,78,80) so as to ensure isolation from substrate noise. A dual channel A/D and D/A converter as claimed in claim 4, characterised in that said barrier means (84) comprises a doped well region in said semiconductor substrate having a depth of approximately 4 µm.

Inventors: MOYAL MIKI
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1990
Main classification: H01L23
IPC codes: H04Q3, H03M1, H01L21, H04M3, H04B3, H01L27