Image processing device

Abstract: An image processing device comprises input means (103) for inputting a plurality of image data of colour components successively and repeatedly as synchronized with a predetermined clock (102) while memory means (104) memorise the image data following a given address. Address generating means (105) generate addresses in synchronization with the predetermined clock and a bit of the colour components as an upper bit of the address.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to an image processing device. Related Background Art In the prior art, in a recording device of the dot recording system, recording scanning is generally performed with a recording head capable of dot recording of about 24 dots. When the recording dot number in one row is made a number exceeding 100 for enhancing recording speed, the driving circuits for driving the recording sections corresponding to these dots are also required in number corresponding to the dots. As the result, the drive circuit as a whole becomes larger, leading to elevation in cost, enlargement of machines. For solving this problem, it may be conceivable to divide the recording head section into blocks, driving the respective recording sections divided into blocks by time division, thereby reducing the dot number driven at the same time by the drive circuit. Fig. 1A shows the block division contents of a liquid jet recording head of the prior art. In Fig. 1A, 128 discharge openings are divided into 16 blocks and the recording sections 101 to 116 of 16 blocks are arrayed in one row. Accordingly, each recording section has ink discharge openings corresponding to 8 dots as shown in Fig. 1B. Such recording sections 101 - 116 are driven by time division, and 8 dots are dot recorded at the same time. When ink is discharged through all the discharge openings by moving the recording in the main scanning direction at a constant speed, the interval from the recorded image of the first block to the recorded image of the 16th block becomes approximate to 60 µm when the recording density is set at 400 DPI (dot/inch) (Fig. 1C). Further, the dot interval between adjacent blocks is 4 µm which is as large as corresponding to the size of about one picture element. Accordingly, for making smaller the slippage of recording dots by such time division recording, the recording head is located obliquely as shown in Fig. 2A for carrying out recording scanning. And, as shown in Fig. 2B, it has been proposed to perform recording of the respective dot rows in one row by tolerating only slanting of the dot rows of the respective blocks. The block actuation order at this time is shown in Fig. 3. The arrowhead A shows the main scanning direction (going way direction) of the recording head and the arrowhead B slanted angle. However, in the recording device of this kind of the prior art, for increasing the speed of recording or obtaining mirror image, returning way recording may be sometimes practiced. In this case, in the recording device of the prior art, since the block driving order is the same as in the going way when the recording head is mainly scanned in the direction by the arrowhead A in Fig. 4A (returning way recording), there was the task to be solved that the slippage of the recorded image became further greater as shown in Fig. 4B. The arrowhead C indicates the sub-scanning direction. There was the task to be solved as described below. For example, in a heat-transfer color printer, the actuation of scanning thermal head by changing the ink ribbons in necessary number is repeated. In such constitution, since there is no simultaneous driving of a plurality of colors (writing heads), no much result can be expected even if printing speed may be desired to be increased. Whereas, in a carriage having the respective writing heads of cyan, magenta, yellow and black mounted thereon, image recording becomes possible while performing writing simultaneously, namely corresponding to one scanning by one movement. In this case, since there are physical intervals between the respective writing heads, the corresponding delay processing is required. Presence of intervals mutually between the heads is because it cannot be avoided in constitution. Besides, the head interval, in the case of a printer having a printing density of 400 dpi, will result in color slippage of 1.5 picture elements or more by 100 µm slippage. In recording natural picture, this is evidently a vital trouble. In the prior art, for the purpose of correcting such physical interval, RAM has been employed to form time difference between writing and reading of data. However, in this case, there ensue the problems as shown below. (1) Independent RAM's for respective colors must be provided. (2) Since in RAM with large capacity of low cost has many byte units, the circuit becomes complicated for converting one bit serial data of multi-color to byte data of separate colors. And, from these problems, the troubles of enlargement and increased cost of the device have been caused to occur. Further, there has been the task to be solved as described below. Ordinarily, for example, in a color ink jet printer, there is no substantial difference in printing speed between color printing and monocolor printing. For increasing the speed, the image clock rate may be increased, but since the driving speed of the writing head for ink jet is limited, no such measure can be taken. If the driving speed of the writing head for ink jet is increased to a certain value or higher, there will ensue such troubles that the life of the writing head becomes markedly short or that the printing quality is deteriorated. However, on the other hand, there is in fact a great need that printing speed or copying speed is desired to be made more rapid in monochromatic printing or monochromatic copying (e.g. conventional black color printing). This may be said to be a requirement as a matter of course in view of high speed printer such as plain paper copying machine under the present situation and LBP (laser beam printer). The US-A-4 528 576 discloses a recording apparatus which includes a plurality of recorders each of which is provided for a color to be recorded. This apparatus further includes separate page memories for each color. SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing device which enables memorizing color image data inputted with a simple constitution in an area different in memorizing means. This object is achieved by an image processing device according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view showing the arrangement of a recording head of a prior art example; Fig. 1B is a plan view showing the appearance of a recording section of a prior art example; Fig. 1C is an illustration showing a recording example of a prior art example; Fig. 2A is an illustration showing the going way recording direction and the slanted angle of a recording head of a prior art example; Fig. 2B is an illustration showing a recording example of going way recording of a prior art example; Fig. 3 is a timing chart showing the actuation timing of a prior art example; Fig. 4A is an illustration showing the going way recording direction and the slanted angle of a prior art example; Fig. 4B is an illustration showing a recording example of the returning way recording of a prior art example; Fig. 5 is a sectional view showing the principal constitution of the recording device of the first unclaimed explanatory example; Fig. 6 is an illustration showing the discharge principle of bubble jet of the first explanatory example of the present invention; Fig. 7A is a block diagram showing the circuit constitution of the first unclaimed explanatory example and Fig. 7B its flow chart; Fig. 8 is a timing chart showing the actuation timing of the going way recording of the first unclaimed explanatory example; Fig. 9 is a timing chart showing the actuation timing of the returning way recording of the first unclaimed explanatory example; Fig. 10 is a block diagram showing the circuit constitution of the second unclaimed explanatory example; Fig. 11 is a block diagram showing the circuit constitution of the third unclaimed explanatory example; Fig. 12 is an illustration showing the constitution of the carriage of another example to which the present invention is applied; Fig. 13 is an illustration showing the circuit constitutions from inputting of image data to writing into memory according to the preferred embodiment of the present invention; Fig. 14 is a timing chart for illustration of the actuation of the respective circuit constitutions in Fig. 13; Fig. 15 is an illustration showing the memory space of RAM and memory regions for respective colors in Fig. 13; Fig. 16 is a block diagram of the control system of the bubble jet printer in another example to which the present invention is applied; Fig. 17 is a timing chart showing the printing timing of the respective recording heads; Figs. 18A to 18E are illustrations for explaining the outline of printing during monochromatic printing; Fig. 19 is an illustration showing an example of the data allotment circuit of the memory control circuit of an example; Fig. 20 is a timing chart for illustration of the allotment processing when developing the multi-color image data into RAM; Fig. 21 is a timing chart for illustration of the allotment processing when developing the monochromatic image data into RAM; Fig. 22 is an illustration showing an example of the circuit according to the data output (reading) of the memory control circuit of an example; Fig. 23 is a block diagram of the control system of the bubble jet printer in another example; Fig. 24 is a timing chart for illustration of the data allotment processing in another example; Fig. 25 is the whole block diagram of another example to which the present invention is applied; Fig. 26 is a timing chart showing the actuation of Fig. 25; Fig. 27 is an illustration showing the blank discharge data generating circuit of another unclaimed example; Fig. 28 is an illustration of a blank discharge printing example; Fig. 29 is a timing chart of blank discharge signal; Fig. 30 is an illustration showing another unclaimed example; Fig. 31 is an illustration showing another unclaimed example; Fig. 32 is an illustration showing another unclaimed example. DETAILED DESCRIPTION First, the modes of the respective unclaimed examples as described below are to be described. In the first place, the first mode is a recording device having a recording head with a plurality of recording elements for performing dot recording corresponding to image data arrayed in a row, which drives each block of the plurality of recording elements divided into a plurality of blocks by time division and has the array of the plurality of recording elements fixed as slanted with respect to the direction vertical to the relative moving direction of the recording head for correcting recording slippage of dots which occurs by time division driving, wherein it is provided with a memory means which memories temporarily by corresponding the image data to the recording position, a designation means which designates successively the blocks to be driven in the order opposite to that of going way recording during returning way recording, and an image data reading means which reads the image data corresponding to the block designated by the designation means and supplies the data to said designated block. In the second mode the image data reading means has an address counter which generates address signals in a certain order and a logic circuit, which sets the output of the address counter as the reading address corresponding to the memory means during going way recording and sets the reversed signal of the output of the address counter as the reading address corresponding to the memory means during returning way recording. In the third mode the above-mentioned designation means has an up-down counter capable of counting in the ascending order and the descending order, and the counting order of the up-down counter is changed over depending on whether the recording is going way recording or returning way recording. In the fourth mode the above-mentioned designation means and the above-mentioned reading means share a counter, the designation means designates the block by use of the counting result of the counter, and the reading means sets the reading address of the memory means by use of the counting result of the counter. Next, the fifth mode is a recording method, having a recording head with a plurality of recording elements for performing dot recording corresponding to image data arrayed in a row, which drives each block of the plurality of recording elements divided into a plurality of blocks by time division and has the array of the plurality of recording elements fixed as slanted with respect to the direction vertical to the relative moving direction of the recording head for correcting recording slippage of dots which occurs by time division driving, wherein the image data are temporarily memoried in the memory means corresponding to the recording position, the blocks to be driven are successively designated in the order opposite to going way recording during returning way recording, and the image data corresponding to said designated block are read from the memory means and supplied to said designated block. Referring now to the drawings, the examples and the preferred embodiment of the present invention are to be described in detail. First, the outline of a bubble jet recording device to which the present invention has been specifically applied is to be described. Fig. 5 shows the principal constitution of the recording device of the first unclaimed explanatory example. In Fig. 5, 901 is a carriage for mounting a recording head, and scanned in the direction shown by the arrowhead S in the Figure. 902 is a wire on which the carriage 901 is secured and also spanned by the pulleys 903 provided at the both ends of the moving range of the carriage 901. 904 is a motor as the carriage driving source which is joined to one of the pulleys 903 and scans the carriage 901 in the S direction in the Figure by rotating the pulley 903. 905 and 906 are the first and second guard rails for guiding the carriage 901 by extending toward the above-mentioned S direction. 907 is a platen roller for regulating the face to be recorded of a recording medium such as paper, film, etc. and also conveying the recording medium. 908 is a motor which is combined with the platen roller 907 and rotates the platen roller 907 during conveying of the recording medium. 909 is a cable for transmission of control signal, of which one end is mounted on the carriage 901, the other end connected to the control circuit as described below, and performs transmission of image data, control signals and other signals between the control circuit and the carriage 901. The cable 909 is made to have a form of a flexible cable so as to follow the displacement of the carriage 909. X is the position where the head performs blank discharge, and generally provided at the position away from the image region 9. Next, the discharge principle of bubble jet is described briefly by referring to Fig. 6. In Fig. 6, under the state (1), the meniscus position of ink exists at around the discharge opening. On one surface of the ink discharge pathway is arranged a heater, and during recording, current is passed through the heater to heat the ink by an abrupt temperature elevation exceeding nucleus boiling to effect film boiling. Then, as shown in the state from (3) to (7), bubble is formed within the ink and the ink is discharged to outside through the expansion force of the bubble. Next, the constitution of the control circuit which performs recording control of recording head is shown in Fig. 7A. In Fig. 7A, 1 is image data which designates whether dot recording is performed or not corresponding to the respective dot positions, and is inputted as synchronized with the image clock 2 of a certain period. VE (video enable) 3 is an information signal which designates the effective region of image. 4 is a change-over signal, which a signal designating the change-over between going way recording and returning way recording which is the key point of the example to which the present invention has been applied. 5 is an address counter which forms reading and writing addresses of the memory 6 by counting the image clock 2. The output of the address counter 5 is address inputted into the memory 6 after the logic operation of EXCLUSIVE·OR with the change-over signal 4. 6 is a memory as the memory means for memorying temporarily the image data to be recorded and is constituted of imaged data of 8 bits per one address. In this example, one block is constituted of 8 recording elements (heaters), and performs time division driving with 16 blocks, and image data corresponding to 8 per one block are housed in one memory address. 7 is a latch circuit for holding the output data of the memory 6 at a timing of a data latch pulse 8. 9 is a segment circuit which generates driving currents corresponding to the heaters 13-1 to 13-128 by amplification of the output signals of the latch circuit 7, and a transistor array is used therefor. 10 is a counter as the designation means which designates the heater heating order at the block unit, counts the clock signals 14 and designates the block to be heated depending on the counting result. For the counter 10, an up-down counter of 4 bit capable of counting the 4 bit output in ascending order and descending order, and counting in ascending order or descending order is determined depending on the change-over signal 4 as described above. 12 is a digit circuit which earths selectively the 8 current passage wires to which the respective heaters within the block are connected in parallel for each block, and passes current through the heater within the block selected, and successively select the block to be passed with current in the counting order of the 4 bit counter 10. 11 is a decoder which decodes the counted value of the 4 bit counter 10, thereby converting it to the designation signal for the digit circuit 12. 13 is a group of heaters consisting of 128 heaters, and these heaters are arranged in a row so as to assume a constant angle relative to the main scanning direction as shown in Fig. 2A. The respective signals 1, 3, 4, 8, 14 inputted into the main control circuit are well employed in the device of the prior art and detailed description thereof is omitted here. Next, the actuation in recording in the circuit shown in Fig. 7 is described by referring to Fig. 8 and Fig. 9. Fig. 8 shows an actuation timing during going way recording, and Fig. 9 an actuation timing during returning way recording. When the change-over signal 4 of the bit "0" indicating going way recording by central processing unit (CPU) which controls the whole control of the recording device is generated, the gate of the EXCLUSIVE·OR circuit 5A is opened, and the output of the address counter 5 is inputted as such into the memory 6. At the same time, the counter 10 is set with up-count (ascending order count) by the change-over signal 4. At this time, it is supposed that, in the memory 6, image data to the 128 heaters 13-1 to 13-128 are successively memoried with, for example, the image data of the first block being as the address "00H". Both of the address counter 5 and the counter 10 initiate counting in the order of "0", "1" (decimal number) ...... at the same timing. When the above counting number is "0", the circuits of the heaters 13-1 to 13-8 of the first block becomes the state capable of current passage (on) by the digit circuit 12, whereby the image data stored in the address "00H" of the memory 6, namely the image data whether heaters 13-1 to 13-8 are to be subjected to current passage or not, are outputted into the segment circuit 9. In the segment circuit 9, driving current corresponding to the image data is heaters applied to the first to the eighth within the first block to heat the predetermined heaters, thereby effecting dot recording. Subsequently, every time when the counting values of the address counter 5 and the counter 10 become "1", "2" (decimal number) ... ..., the heaters of the second block, the third block correspond thereto to effect heating. When all dot recording of one row is completed, the 4 bit counter 10 is reset. When dot recording corresponding to two rows is completed, the memory contents in the memory 6 are renewed to the image data corresponding to the next two rows, and recording is performed according to the same procedure as described above. Next, during returning way recording, when the change-over signal is set at the bit "1" by CPU, the output of the address counter 5 is reversed by the EXCLUSIVE-OR circuit 5A in the next step to be inputted into the memory 6. For example, when the output value "0" (decimal number) of the address counter is reversed, the input value of the memory becomes "31" (decimal number). At the same time, down-count is selected for the counter 10. In the memory 6, it is supposed that dot data corresponding to 2 rows for returning way recording are housed at the addresses "00H" - "1FH" made correspondent to the positions of the first to the 16th blocks. The counter 10 initiates counting from "15" (decimal number). Accordingly, the heaters of the 16th block become possible to be passed with current, and into the segment circuit 9 are outputted the image data stored in the address "1FH" of the memory 6. Next, by renewal of the counting values of the counters 5, 10, the image data of the address "1EH" of the memory 6 are outputted into the segment circuit 9. When the image data is outputted into the segment circuit 9, the digit 15 of the digit circuit 12 is turned on, whereby current passage through the heaters of the 15th block becomes possible, and the predetermined heaters are heated based on the image data. As described above, by permitting time division recording of a plurality of recording elements (heaters) arrayed in a row in the block order opposite to going way recording to be performed, the recording result becomes such that the dot images for each block are arrayed in a row similarly as going way recording as shown in Fig. 2B. Here, by use of Fig. 7B, the recording sequence of this example is described. First, in the step S1, it is judged whether recording is going way or returning way recording. If it is going way recording, "0" is outputted as the change-over signal 4 (step S2), or if it is returning way recording, "1" is outputted as the change-over signal 4 (step S3). Next, in the step S4, recording is initiated by receiving the image signal 1 and the image clock 2. Next, judging whether one scan recording has been completed or not (step S5), and whether the whole recording has been completed or not (step S6), and if the whole recording has been completed, the recording completion sequence is performed to complete recording (step S7). In addition to the first example as described above, the following application examples may be conceivable. 1) In the first example, separate counters 10, 5 are used for the digit circuit 12 and the memory 6, but one counter can be also commonly used. In this case, as shown in Fig. 10, the lower 4 bits of the EXCLUSIVE-OR circuit 5A are inputted into the decoder 11. As the merit of this example, miniaturization and cost-down of the instrument due to circuit reduction can be obtained. On the other hand, the demerit of this example although not shown is limited in expansion of the function which enables setting of the start position for driving the digit freely by addition of a preset function on the counter 10 shown in Fig. 7. Therefore, the first example and the second example may be used distinguishedly as desired. 2) In the above second explanatory example, an example of performing image recording only of black color has been shown, but when a color recording device is present, further the following merit can be brought about. That is, since a plural number of recording sections exist for the respective colors, a memory for storing temporarily image data is provided for correcting the time slippages of color recording for separate colors. By reversing the order of reading of image data in going way and returning way by use of this memory, memory can be saved. In this case, preparing an address counter 5' of 15 (5x3) bits is prepared as shown in Fig. 11, the address is inputted into the memory 6' through EXCLUSIVE-OR circuit 5A which performs operation of exclusive logic sum of the lower 5 bits and the change-over signal within the address space, and the upper 10 bits are address inputted as such into the memory 6'. As described above, the above first mode calls attention on the fact that no recording slippage occurs if recording is performed in returning way recording in the block order opposite to going way recording, sets the designation means so that the designation order of the blocks for performing recording in returning way recording, and also reversing the reading order of the image data of the memory means, whereby the image data to be recorded can be also supplied to the recording section of the above blocks in correspondence to the above block positions. As the result, returning way returning in the block order opposite to going way can be accomplished. Also, in the above-described second mode, since the address designation order of returning way recording is reversed by reversing the generated address of the address counter by a logic circuit, the number of the counter can be made one without preparation of address counters which generate addresses of ascending order and descending order, respectively. Further, in the above-described third mode, since an up-down counter is used as the designation means, the block designation of ascending order and descending order can be done with one counter, it can contribute to miniaturization of the device. In the above-described fourth mode, since the block designation and the reading address of memory means are set on the basis of the counting result of the counter by calling attention on the fact that the designated blocks and the housing addresses of the image data of the recording means are in corresponding relationship, the number of the counter may be only one, which can contribute to miniaturization of the device. Further, in the above-described fifth mode, since recording is performed in the block order opposite to going way in returning way recording, the recording order of the image data memoried in the memory means and the order of driving block are made reversible, whereby returning recording is rendered possible and the recording results become also of the same quality as going way recording. Further, the preferred embodiment is to be described. The preferred embodiment as described in the following is an image processing device, having an input means for inputting successively and repeatedly image data of color component as synchronized with a predetermined clock, a memory means which memories the above image data following a given address, a generation means for generating the above address as synchronized with the above predetermined clock, said address generating means being a means for generating the bit exhibiting the above color component as the upper bit of the above address. Further, an image recording device is described which reads the recorded image data for respective colors from the memory memorizing recorded image data and recording the image with a carriage mounted with recording heads for respective colors at predetermined intervals in the main scanning direction, which is equipped with an input means which inputs successively the image data for the respective color components as synchronized with a predetermined clock, an address generation means which generates an address with a bit number corresponding to the address space of the above memory, an address converting means which exchanges at least the bit number corresponding to the recorded color number from the lower position of the address generated at said address generation means with the remaining upper address bit group to supply it to the above memory, and a writing means for writing the image data inputted by the above input means at the address position of the above memory supplied by said address converting means. In describing the preferred embodiment, Fig. 5 and Fig. 6 as described above are employed. However, in the preferred embodiment, the above-described carriage 901 has heads (901A - 901D) corresponding to the respective colors of cyan (hereinafter C), magenta (hereinafter M), yellow (hereinafter Y) and black (hereinafter K) mounted thereon. Here, the structure of the carriage 901 is shown in Fig. 12. As shown in the Figure, in the carriage 901 are assembled writing heads (901A - 901D) of the total four colors of C, M, Y, K. In the case of this example, each head has ink projection openings corresponding to 128 dots, which are arrayed in a row with the intervals L 1 , L 2 , L 3 between the respective heads. That is, it is shown that the respective 128 dots of the four colors can be printed by one scanning movement in the S direction (scanning direction). Now, when a printer having a printing density of 400 dpi is considered, in the example of a printing head having 128 dots as one line, its printing width L 0 becomes about 8 mm. In the preferred embodiment, ink projection openings as shown in Fig. 6 are arranged in number of 128 for each head of C, M, Y, K in the constitution of Fig. 5. Referring now to Figs. 13 - 15, the outline of the processing according to housing of the image data of the preferred embodiment in the constitution of the recording system as described above is to be described. In the preferred embodiment it is supposed that the data for the respective data are sent serially one bit by one bit in the order of C, M, Y, K, C, M... . Also, description of the operations by use of known techniques about driving of practical recording heads is omitted. Now, in Fig. 13, the serial data 101 sent in the form as mentioned above is incorporated in a 29-bit shift register 103. Of the outputs of the 29-bit shift register 103, those corresponding to the total 8 bits of Q 0 , Q 4 , Q 8 , Q 12 ...Q 28 are outputted to the writing data bus to SRAM 104 (in the example, the capacity is 32 KB = 32 x 1024 bite). That is, for SRAM 104, since the bits of the serial data for every four bits are inputted into the data input terminals D 0 - D 7 , the data under the state separated for respective colors are inputted. On the other hand, the counter values Q 0 - Q 14 of 15 bits formed in the address counter 105 are, as shown in the Figure, have Q 0 connected to the SRAM address bit A 13 , Q 1 to A 14 , and sequentially from Q 2 to Q 14 to the address bits A 0 to A 12 . Although the description is not in order, the 29-bit shift register 103, SRAM 104 and the 15-bit address counter 105 are actuated as synchronized with the clock outputted from the timing formation circuit 106. In the following, actuations of these respective elements are to be described on the basis of the timing chart shown in Fig. 14. The image data 101 are inputted in the order of C, M, Y, K as synchronized with start-up of the image clock 102 as described previously. Now, suppose that the initial image data are made C 0 , M 0 , Y 0 and K 0 , then when the eighth picture elements C 7 , M 7 , Y 7 , K 7 , namely the data corresponding to 8 bits for the respective colors are inputted, the address counter, the shift register, WE (write enable) become active, whereby the data are written into. SRAM 104. The written data and the address thereof for the SRAM 104 at this time are as shown in 10 - 18 in Fig. 14. To describe in more detail, the outputs Q 0 - Q 14 of the 15 bit address counter 105 at the respective timings when WE signals become active are 0001 H , 0002 H , 0003 H , 0004 H (H shows hexadecimal number). However, since the connection between the 5-bit address counter 105 and the address of SRAM 104 is in the relationship as previously described (shown in Fig. 13), the address for SRAM 104 becomes 2000 H , 4000 H , 6000 H and 0001 H . In other words, to describe in the memory space of SRAM 104, as shown in Fig. 15, the region of the address of 32 KB space "0000 H - 1FFF H " becomes the K region, the address "2000 H - 3FFF H " the C region, the address "4000 H - 5FFF H " the M region, and the address "6000 H - 7FFF H " the Y region. Thus, the data of picture elements of the respective colors sent as the serial data can be housed in byte units in SRAM 104. When the memory has become full of data, for example, when Y data is written in 7FFF H address, next writing is newly done from the address 6000 H . As described above, according to the preferred embodiment, it becomes possible that multi-color serial data are converted to byte data separately for respective colors with a simple constitution, and the byte data of the respective colors are housed while being allotted in one memory. In the preferred embodiment, description has been made about the case when the serial data are received, they are converted to byte data and memoried by allotment into one RAM, but the present invention is not limited only to this case. This is because, for example, the input interface may not be serial but parallel. Of course, in this case, it is required to receive the parallel data for the respective colors. Also, in the preferred embodiment, the memory capacity allotted for the respective colors is made 8 Kbyte, but also the present invention is not limited thereby. For example, when the recording density with the recording head is high and a RAM having large capacity is required, for example, a RAM of about 64 Kbyte is employed, by connecting the lower 2 bits of the address counter (16 bit output) to the upper position of the address of RAM, the memory capacity allotted for the respective colors can be increased to two-fold of 16 Kbyte. As described above, according to the preferred embodiment, the color image data inputted repeatedly are memoried in the different areas of the recording means for the respective color components. Further, for such memory, the bits exhibiting the color component are generated as the upper bits of the memory means and therefore the above-described function can be realized with a simple constitution. Further, according to the preferred embodiment, since the circuit constitution from image data receiving to housing of memory becomes simple, enlargement of the device can be suppressed, and also cost-down can be effected. Also, when the picture element data for the respective colors are sent serially, they are converted into bit unit data for the respective colors, and address and writing signals are generated in effecting the conversion. By this, even when serial data may be inputted, it becomes possible to allot the data of bit units for the respective colors in the memory with a simple constitution and surely. Still another example is described below. The device constitution in this example is the same as in the preferred embodiment described above by use of Fig. 12 - Fig. 15, and Fig. 5, Fig. 6 and Fig. 12 are employed here. The outline of the control system in color printing of this example in the constitution of the recording system as mentioned above is described. First, in Fig. 16, the image data 201 sent to this device are separated by a memory control circuit 202 for respective colors and respective signals and written in RAM 203 - 206. Here, RAM 203 - 206 correspond to the respective colors of C, M, Y, K as a matter of course. And, the data developed within RAM 203 are sent through a head driver 207 to a cyan head 208. Also, the data of RAM 204 are sent to a magenta head 209, the data of RAM 205 to a yellow head 210 and data of RAM 206 to a black head 211, respectively, through the head driver 207. Writing and reading of the data into the respective RAM are all performed in the memory control circuit 202. The memory control circuit 202 is controlled by the image data 201 and the signals from CPU 212, and may be also formed into one chip of LSI such as gate array, etc. From CPU 212, in addition to data bus, address bus shown in the Figure, are connected control wires such as read, write signals, etc. (although not shown here). This can be also said similarly for the head driver 207. However, since the head driver 207 drives ink jet head, it includes a power circuit, but this is not directly related to the present invention and its description is omitted. Now, having described about the printing carriage 901 (having the cyan head 208, the magenta head 209, the yellow head 210 and the black head 211 mounted thereon) in this example, if the data of C, M, Y, K are printed at the same time, the color slippages between C-M, C-Y, C-K are formed with the respective sizes of L 1 , L 1 +L 2 and L 1 +L 2 +L 3 . Accordingly, color slippage is correctted by varying the timing for reading of the data of RAM 208 - 206. The timing is shown in Fig. 17, and from the start-up of the start signal, the printing timing of the respective colors is varied from t 1 to t 4 . Here, the printing timings for the respective colors are portions of t 5 - t 8 shown by slash lines. Generally, it is controlled so that they may be: t 5 = t 6 = t 7 = t 8 , t 2 - t 1 = L 1 /V, t 3 - t 2 = L 2 /V, t 4 - t 3 = L 3 /V. "V" is the speed of the carriage 901 when moving in the S direction. Whereas, in this example, when monochromatic printing, for example, printing is performed with only black, the ink cartridges connected to the printing heads 208 - 211 are all exchanged with those for exclusive use of black (when head and ink cartridge are integrated, it may be exchanged). And, the monochromatic image data 201 are divided by the memory control circuit 202 into the respective data of 128, and the first 128 data are housed into RAM 203, the next 128 data into RAM 204, the next 128 data into RAM 205, the next 128 data into RAM 206 and again the next 128 RAM into RAM 203. Here, "128" is the dot number in the sub-scanning direction which can be printed by one carriage direction shown in Fig. 5 as described above. On the basis of such constitution, in this example, printing is performed with the scanning speed of the carriage 901 being made to 4-fold of that during multi-color printing at the maximum. That is, while the period of outputting the applied signal to the respective printing heads is the same as during multi-color printing, the four heads perform printing under divided allotments. The outline of this monochromatic printing is described by referring to Figs. 18A to 18E. Now, the case of printing the letter "A" in Fig. 18A is considered. For brevity of explanation, it is supposed to take one second for one line in this example. Then, in the example shown in Fig. 18A, it will take 8 seconds because there are 8 lines in all. However, in this example, by performing printing under divided allotments with 4 heads, printing can be done substantially within 2 seconds. This is shown in Figs. 18B - 18E. For example, Fig. 18B shows images dots printed with a head replaced for the C head 8, and Figs. 18C - 18E the image dots printed with the heads replaced for M, Y, K heads 9 - 11. After printing of the first one line in one second by each head, since the scanning speed of 901 is 4-fold of that of conventional one, the next dot row will be printed at 4 dot intervals. Here, allotment of the image data into RAM 203 - 206 during color printing and monochromatic printing are described. Fig. 19 shows a circuit constitution according to the data allotment within the memory control circuit 202 in this example. In the Figure, 214 is a 29-bit shift registor (for example, FIFO memory). Although the description is not in order, it is supposed that during color printing, the image data are sent in respective dot informations in the order of C, M, Y, K. Now, when the level of the change-over signal (outputted from CPU 212) is "0", to the output lines D 0 - D 7 (forming data bus) are outputted 8-bit data (Q 0 , Q 4 , ...Q 28 ) separated for respective colors. The timing chart at this time is shown in Fig. 20. The byte data for the respective colors are taken out according to the timing shown in the Figure and written in the respective RAM 203 - 206. At this time, as described previously, C data are written in RAM 203, M data in RAM 204, Y data in RAM 205 and K data in RAM 206. When monochromatic recording is performed with the respective printing heads of the carriage 901 being all made the heads of the same color, the change-over signal is made "1". The timing chart at this time is shown in Fig. 21. As shown in the Figure, to the output lines D 0 - D 7 are outputted continuous 8-bit data (Q 0 , Q 1 , ···, Q 7 ). When 8-bit data are written into the desired RAM for 16 times, it becomes 128-bit, whereby the chip select signal (CS signal) is changed over to be transferred to the next RAM. Next, the outline of data outputting in monochromatic printing is to be described. Next, as described previously, in RAM 203 - 206 are respectively housed at 4 line intervals (with 3 lines in between). However, by only making the scanning speed of the carriage 901 4-fold of that during color printing, printing is done on the same site with the respective heads to ensue a problem. That is, for performing printing as shown in Fig. 18A, it is necessary to vary the printing timing with the respective heads by one dot. To describe more specifically, in monochromatic printing, t 1 - t 4 in Fig. 17 must be changeable to the scanning time unit corresponding to one dot. Accordingly, in this example, the circuit is constructed as shown in Fig. 22. This circuit forms a part of the memory control circuit 2, and each RAM is equipped with the same circuit. In the Figure shown, 240 and 241 are JK-flip-flops, 242 and 243 are counters, 244 and 245 ... are coincident circuits, 246 and 247 are registers. The register 246 and the register 247 are connected to the data bus, and CPU 212 can write desired data by enabling gate signals to the respective registers. Now, CPU 212 houses the data indicating the driving initiation timing of the desired head in the register 246 and the data indicating the completion time in the register 247. Therefore, with the JK-flip-flop 240, the counter 242, the coincident circuit 244 and the register 246, for example t 1 (or t 1 - t 4 ) in Fig. 17 is counted. When the video clock number counted by the counter 242 and the data housed in the register 246 are coincident, the output Q of the JK-flip-flop becomes "1". Similarly with the JK-flip-flop 241, the counter 243, the coincident circuit 245 and the register 247, t 1 + t 5 (or t 2 + t 6 - t 4 + t 8 ) are counted. When the count value of the counter 243 and the value of the register 247 are coincident, the output of the JK-flip-flop becomes "0". Therefore, it can be understood that the output from the AND gate 248 becomes the slash line region shown in Fig. 17. Practically, the signal from the AND gate 248 may be also made the enable signal when reading the data from the respective RAM, but in this example, correction in finer precision is rendered possible by equipment of the register 249, the counter 250 and NAND circuit 251. N-mal counter is constituted with the register 249, the counter 250 and the NAND circuit 251 as a matter of course. With the N-mal counter as the clock, by striking with the D-flip-flop 252, finer control can be done. To summarize the above description, it can be understood that it becomes possible to form timing at least during monochromatic printing by changing the writing data in the registers 246, 247. Then, the moving speed of the carriage 901 may be made to 4-fold of that during color printing. In the example as described above, description has been described about a color ink jet printer with 4 heads, but in the case of 2-head printer, the printing speed can be made 2-fold with the same principle. Fig. 23 shows a block concentration of the control system in this example. Increase of printing speed leads to greater loading on the motor which moves the carriage corresponding thereto, and therefore driving a motor at too high speed may result in enlargement or cost-up of instrument. For this reason, in this example, an example which makes the printing speed 2-fold is shown. Since the constitution and the actuation shown in the Figure are redundant with the example as described above, and therefore detailed description thereof is omitted. Although it is conceivable to form 3 heads, thereby making the speed 3-fold as a matter of course, two or four heads are preferable in constitution of the circuit. Also, writing into the memory and driving of the head are done by dividing the input data each into 128 bits which is the bit number possessed by the head. Division each into one line (128 bits) has been done merely for easiness in thinking, and therefore other formats may be also available without any problem. An example of the timing chart is shown in Fig. 24. In the case shown in the Figure, the chip select signal is changed over every 8 bits, showing the case in which the first 8 bits are housed in RAM 203, the next 8 bits in RAM 204, the next 8 bits in RAM 205, the next 8 bits in RAM 206, and the next 8 bits in RAM 203. Ordinarily, the head is not driven dividedly and, for example, even when there may be data of 128 bits, driving is done in 16 divisions each of 8 bits, and therefore the driving frequency is not substantially changed as in the example shown in Fig. 24. As described above, in this example, as shown in Fig. 18, the interval toward the scanning direction recorded by the four respective recording heads of cyan, yellow, magenta, black is made the distance of 4 dots interval corresponding to the number of the recording heads, and the recording positions with the individual recording heads are made so as not to overlap each other. Therefore, high speed printing can be performed. As described above, according to this example, since printing is performed with N colors, in a device which performs recording of images by scanning movement of a carriage having N recording heads mounted at predetermined intervals, in the case of performing monochromatic printing, it becomes possible to perform recording at a speed of N-fold of that during color printing at the maximum. In the case of change from multi-color printing to monochromatic printing (or vice versa), it becomes necessary to inform CPU 12 of such change by some means, and various means may be conceivable as such means. For example, an operational panel may be provided on the main device and direction made from the panel, or alternatively a sensor, etc. for discriminating the kind of the cartridge mounted on the carriage may be provided for automatic judgement. Shortly speaking, it is only sufficient to inform the CPU 12 of whether multi-color printing or monochromatic printing is to be performed, and therefore the present invention is not limited by this. Although, in this example, description has been made by taking an example of ink jet, particularly bubble jet printer, the same principle is applicable if the device is required to have predetermined head driving intervals or more. As described above, recording is performed by mutual divided allotments of the respective recording heads, whereby it becomes possible to perform image recording at high speed without increasing the driving intervals of the recording heads. Still another example to which the present invention is applied is described below. Also, in the example described below, Fig. 5, Fig. 6 and Fig. 12 as described above are employed. Under the constitution shown in Fig. 5, Fig. 6 and Fig. 12, another specific example to which the present invention has been applied is described on the basis of Fig. 25 through Fig. 30. First, the block diagram is shown in Fig. 25. The data 311 sent to the printer are separated for respective colors or respective predetermined signals by a memory control circuit 312 and written in a memory (RAM) 313 or 316. In the case of color printer, signals of cyan, magenta, yellow and black are inputted serially, and cyan allotted to the memory 313, magenta to the memory 314, yellow to the memory 315 and black to the memory 316. The data in the memory 313 are sent through the head driver 317 to the cyan head 318, the data in the memory 314 through the head driver 317 to the magenta head 319, the data in the memory 315 through the head driver 317 to the yellow head 320 and the data in the memory 316 through the head driver 317 to the black head 321. The heads 318 - 321 are mounted on the carriage 901 as described above. The memories from 313 to 316 are all controlled by the memory control circuit 312. The memory control circuit 312 is controlled by the image signal 311 and the control signals delivered from CPU 322. Ordinarily, the control system is made into one chip of LSI such as gate array, etc. From CPU 322, in addition to 1 CPU data bus 341 and the address bath 342, are connected control lines such as read signals or write signals, etc., although not shown here. Similarly as CPU 322, to the head driver 317 are also connected control lines. Also, the head driver 317 includes a power circuit for driving ink jet head. However, here, it is not relevant with the present invention and therefore its detailed description is omitted. In Fig. 25, 343 is data bus, 344 address bus and 345 timing clock. Fig. 26 shows the recording timings of the respective heads. As shown in the Figure, recording is initiated in the order of cyan, magenta, yellow, black. These timings are generated by the circuits assembled in the memory control circuit in Fig. 25, but detailed description is omitted. By managing the times of t 1 to t 4 in Fig. 26, the recording timings of the respective heads can be determined to correct the so called regi-slippages. Next, the blank discharge data generating section is described. Fig. 27 shows the block diagram of the blank discharge data generating section of another unclaimed explanatory example. The image signal 311 and the image clock 323 are the same as in Fig. 25. Based on the image clock 323, the clock of the shift register 325 is made by the counter circuit 324. The shift register 325 has the set value of the register 326 preset by the load signal 327. The shift register 325 is constituted of a ring shape so that the data of the register 326 may be turned around. 328 is a selector circuit, which selects one of the image signal 311 or the blank discharge data with the select signal 329 and passes it over to the next step 330. Ordinarily, the next step 330 becomes the image data 311 in Fig. 25. To describe in more detail based on practical data, now suppose formation of the black discharge data as shown in Fig. 28. In the example shown in Fig. 28, the head having 128 nozzles are under blank actuation at a rate of once per 4 times. Now, under such specification, suppose that CPU writes blank discharge data of 1000 shots for every nozzle in RAM. When, as a premise, RAM is constituted of 4 BIT, write time of CPU 5 µsec, heads are 4 heads (4-color constitution) each constituted of 128 nozzles, a time as long as 1000 x 4(DOT/nozzle) x 128(nozzle/head) x 4(head)/ 4(BIT) x 10µsec = 5.12 sec is consumed. This time is a great problem when the throughput of the printer is considered. Accordingly, an attempt to realize high speed blank discharge actuation in a hardware circuit is the circuit shown in Fig. 27. When the blank discharge is realized by the circuit constitution shown in Fig. 27, the timing chart becomes as shown in Fig. 29. In Fig. 29, VE are video enable signals corresponding to 128 nozzles, BVE is block video enable signal showing effective range of image data, 325A is an example of shift register data, and in this case, timing change occurs as shown in Fig. 29 with 4 bit constitution. In this example, the clock of the shift register data not be constituted of a counter circuit but the signal VE as such may be employed. Fig. 30 shows another unclaimed explanatory example. In Fig. 30, the same sites as in Fig. 27 are affixed with the same symbols. This example, in place of forming a shift register clock with the counter circuit 324 as shown in Fig. 27, utilizes the signal of the writing address formation counter of RAM. The writing address formation counter of RAM is included in the memory control circuit 312 shown in Fig. 25, but not described here in detail. Fig. 31 shows another unclaimed explanatory example. In this example, not CPU setting, but blank discharge data pattern is determined in an externally fixed SW circuit 331. Fig. 32 shows another unclaimed explanatory example. In this example, an oscillation circuit for driving blank discharge data formation circuit and a clock formation circuit 333 are independently provided. In this case, while there is the demerit that cost-up is effected by provision of the circuit 333, by use of a clock with higher speed than image clock, there is the merit that writing of blank discharge data into RAM can be done at higher speed. As described above, in this example, the constitution is made such that: (1) the connecting memory for head interval correction is utilized as the accumulation means of blank discharge data; (2) the circuit for connecting memory is to be used commonly with the image signal processing circuit; (3) writing of blank discharge data into connecting memory is constituted of a hardware rather than CPU; (4) the pattern of blank discharge data is made a selectable form, taking CPU set or an externally fixed system; (5) the driving of blank discharge data formation section it to be utilized commonly with image clock, whereby a blank discharge data formation of high speed and low cost can be realized. The respective examples as described above will bring about excellent effects in recording devices to which the ink jet recording system, above all the bubble jet recording system has been applied. As for its representative constitution and principle, for example, it is most preferable to perform the system by use of the basic principle disclosed in U.S. Patents No. 4,723,129 and No.4,740,796. This system is applicable to either the so called on-demand type or the continuous type, but particularly in the case of the on-demand type, it is effective because by applying at least one driving signal which gives abrupt temperature elevation exceeding nucleus boiling corresponding to recording information to the electrothermal transducer arranged corresponding to the sheet or liquid pathway in which liquid (ink) is held, heat energy can be generated in the electrothermal transducer to effect film boiling on the heat acting surface of the recording head, consequently forming bubbles in the liquid (ink) corresponding one by one to the driving signal. By growth and shrinkage of the bubbles, the liquid (ink) is discharged through opening for discharge to form at least one droplet. When the driving signal is made in pulse form, growth and shrinkage of bubbles can be effected instantly and adequately, whereby discharge of the liquid (ink) particularly excellent in response can be accomplished more preferably. As the driving signal for such pulse shape, those as described in U.S. Patents 4,463,359, 4,345,262 are suitable. By employment of the conditions described in U.S. Patent 4,313,124 of the invention concerning the temperature elevation rate of the above-mentioned heat-acting surface, further excellent recording can be performed. As the constitution of the recording head, in addition to the combined constitution of discharge opening, liquid pathway, electrothermal transducer (linear liquid pathway or right angle liquid pathway), the constitution by use of U.S. Patents 4,558,333, 4,459,600 disclosing the constitution having the heat-acting section arranged in flexed portion is also applicable to the above-described examples. In addition, the above-described examples are also effective when the constitution may be made on the basis of Japanese Patent Laid-open Application No. 59-123670 disclosing the constitution in which the common slit is made the discharge section of electrothermal transducer or Japanese Patent Laid-open Application No. 59-138461 disclosing the constitution in which the opening for absorbing the pressure liquid of heat energy is made correspondent to the discharge section. Additionally, the above-described respective examples are also effective when a recording head of the chip type freely exchangeable which enables electrical connection with the main device and feeding of ink from the main device by being mounted on the main device, or a recording head of the cartridge type which is provided integrally on the recording head itself is used. Also, addition of restoration means for the recording head, preliminary auxiliary means, etc. as the constitution of the recording device of the above-described examples is also preferable because the effects of the above-described examples can be further stabilized. To mention these specifically, capping means, cleaning means, pressurization or aspiration means for recording heads, electrothermal transducer or heating elements separate from this or preliminary heating means in combination of these, and preliminary discharge mode which practices discharge separate from recording are also effective for performing stable recording. Further, as the recording mode of the recording device, not only for the recording only of the main color such as black color, etc., but also for a device equipped with at least one full-color by plural colors of different colors or color mixing, the above-described examples are extremely effective. In the examples of the ink jet recording devices as described above, descriptions have been made about ink as liquid, but, for example, an ink which is solidified at room temperature or lower and is softened or becomes liquid at room temperature or higher may be also employed. In the above-described ink jet, it is generally practiced to control temperature within the range of 30°C to 70°C so that the viscosity of the ink may be within stable discharge range, and therefore any ink which becomes liquid during imparting recording signals may be available. In addition, use of an ink with the property liquefied for the first time by heat energy is also applicable to the present examples, such as an ink which is prevented from temperature elevation by heat energy by using it as the energy for phase change from solid state to liquid state of ink, or solidified under the state left to stand for the purpose of preventing vaporation of ink, anyway an ink which is liquefied by imparting heat energy corresponding to recording signals or begins to be solidified when reaching the recording medium. In such case, the ink may be made in the form as opposed to the electrothermal transducer under the state held as liquid or solid substance in porous sheet concavity or thru-hole as described in Japanese Patent Laid-open Patent Applications Nos. 54-56847 or 60-71260. In the above-described examples, the most effective one for the respective inks as described above is one which performs the film boiling system as described above. However, as the energy generating means which generates ink discharge energy, the electrothermal transducer as mentioned above is not limitative of the present invention, but an electromechanical transducer such as piezoelectric element, etc. or a system of irradiating electromagnetic wave such as laser, etc. to be absorbed in a liquid to generate heat and discharging ink by the heat-generating action may be also employed.

Claims: An image processing device comprising input means (103) for inputting a plurality of image data comprising a predetermined number of color components 2 n successively and repeatedly in synchronism with a predetermined clock (102), memory means (104) for memorizing said image data following a given address, and address generating means (105) for generating addresses (A0-A14) in synchronism with said predetermined clock (102) by counting counter values (Q0-Q14), wherein said address generating means (105) generates the n uppermost bits of said addresses in accordance with the predetermined n lowermost bits of the respective counter values. The image processing device according to claim 1, wherein the image data comprises four color components (n=2) and wherein the two lowermost bits (Q0, Q1) of the counter values define the two uppermost bits (A13, A14) of the addresses. The image processing device according to claim 1, wherein said input means (103) is a shift register for retaining a predetermined number of bits of image data of eacn color component inputted in a predetermined order and outputting the retained image data to said memory means (104) as parallel data for each color component by outputting said image data into an address position of said memory means (104) generated by said address generating means.

Inventors: TAKAHASHI KAZUYOSHI, TAKAHASHI, KAZUYOSHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: B41J2
IPC codes: B41J2