Manufacturing method of a bipolar transistor

Abstract: The invention is to form an intrinsic base layer (16) by doping an impurity in the emitter polysilicon electrode (15) into the intrinsic base region (16) of the surface of a semiconductor substrate (1) by heat treatment through the emitter lead-out part hole (14) self-aligned to the base lead-out electrode (7). Thus, beneath the insulation film of the substrate surface between the base lead-out part hole and emitter lead-out part hole (14), the outer marginal part of the intrinsic base layer (16) and the inner marginal part of the extrinsic base layer (11) overlap uniformly. Still more, since the diffusion of the impurity by heat treatment is very fast in the polysilicon emitter electrode as compared with that in the silicon substrate, an extremely shallow intrinsic base layer (16) may be formed.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device reduced in dimension and raised in speed of bipolar transistor, and the manufacturing method thereof. The bipolar transistors are recently reduced in dimension beyond the limit of photolithographic technology by the self-aligned technology as disclosed, for example, in the Japanese Patent Publication No. 55-27469, the Japanese Laid-open Patent No. 56-1556. the Japanese Patent Publication No. 57-32511 and the Japanese Laid-open Patent No. 60-164356, and characteristics of extremely high speed and high performance are realized. To illustrate a semiconductor device by a prior art and its manufacturing method, an example of manufacturing method of NPN transistor is shown in Figs. 3a to d. Documents reflecting this prior art are as follows:- S. Konaka et al., "A 30ps Si Bipolar IC using Super Self-Aligned Process Technology", Extended Abstract of the 16th 1984 International Conference on Solid State Device and Materials, Kobe, p. 209,1984. Y. Okita et al., "A novel Base-Emitter Self-Alignment Process for High Speed Bipolar LSIS", Proceedings of the IEE 1988 Custom Integrated Circuits Conference, 22. 4, 1988. M.C.Wilson et al., "The Effect of Emitter Sidewall Isolation of the Emitter Junction in a Double Layer Polysilicon Bipolar Process", Proceedings of the IEEE 1988 Bipolar Circuits and Technology Meeting, p128, 1988. First, as shown in Fig. 3a, after forming an N-type collector buried layer 19 on the surface of a p-type silicon substrate 18, an N-type epitaxial layer 20 is formed on the surface of the N-type collector buried layer 19. Next, after forming a LOCOS film 21 for device isolation in a specific region on the surface of the N-type epitaxial layer 20, a P+ polysilicon 22 to be used as a base lead-out electrode and a CVE oxide film 23 are sequentially grown on the entire surface of the N-type epitaxial layer 20 and LOCOS film 21. Consequently, the CVD oxide film 23 and then P+polysilicon 22 are selectively removed by etching, using the photoresist by photolithography as the mask, and an intrinsic base region 24 on the surface of the N-type epitaxial layer 20 is exposed. Furthermore, as shown in Fig. 3b, after growing a nitride film 25 on the entire surface of the CVD oxide film 23 and intrinsic base region 24, impurities are diffused into the N-type epitaxial layer 20 from the P+ polysilicon 22 by heat treatment, thereby forming a P-type extrinsic base layer 26. Afterwards, using the P+ polysilicon 22 and CVD oxide film 23 as the mask, P-type impurity ions are implanted into the intrinsic base region 24, and a P-type intrinsic base layer 27 is formed. Next, as shown in Fig. 3c, the polysilicon grown on the entire surface of the nitride film 25 is anisotropically etched, and a polysilicon side wall 28 is formed. Using this polysilicon side wall 28 as the mask, the nitride film 25 other than the side wall of the P+ polysilicon base electrode 22 and the peripheral part 29 of the intrinsic base region 24 is etched, and an emitter lead-out part hole 30 is self-aligned to the P+ polysilicon base electrode 22. Finally, as shown in Fig. 3d, the N+ polysilicon grown on the entire surface of the CVD oxide film 23 and intrinsic base region 24 is selectively etched by using the photoresist by photolithography as the mask, and an emitter electrode 31 is formed, and N-type impurities are diffused into the N-type epitaxial layer 20 from the N+ polysilicon emitter electrode 31 through the emitter lead-out part hole 30 by heat treatment, thereby forming an N-type emitter layer 32. According to this manufacturing method of semiconductor device, all of the extrinsic base region, emitter region, base electrode lead-out part and emitter electrode lead-out part can be formed by self-aligned process, and the bipolar transistor may be reduced in dimension and raised in speed. In this prior art, using the P+ polysilicon base electrode 22 as the mask, P-type impurity ions are implanted into the intrinsic base region 24 to form the P-type intrinsic base layer 27. When forming the intrinsic base layer 27 by ion implantation, the junction depth of the intrinsic base layer 27 cannot be set less than 0.2 µm due to channeling at the time of ion implantation. If the intrinsic base layer 27 is deep, the transistor cut-off frequency becomes lowered, which is disadvantageous for raising the operating speed of the bipolar transistor. In the prior art, channeling is decreased by inclining the tilt angle by about 7 degrees to vertical to the semiconductor substrate at the time of ion implantation, but when the tilt angle is inclined, as shown in Fig. 3b the tilt pass is shaded by, the P+ polysilicon base lead-out electrode 22, and the overlap quantity does not become uniform between the outer marginal part of the intrinsic base layer 27 and the inner marginal part of the extrinsic base layer 26 surrounding the intrinsic base layer 27. As a result, the leak current between collector and emitter increases in the insufficient overlap portion, or the base resistance increases to induce reduction of high frequency characteristics. Or when the intrinsic base layer 27 is formed on the entire base region before the step of forming the polysilicon base lead-out electrode 22 and extrinsic base layer 26, the insufficient overlap of the extrinsic base layer 26 and intrinsic base layer 27 may be avoided. In this case, however, by the heat treatment in the step of forming the extrinsic base layer 26, the intrinsic base layer 27 becomes deeper, which also leads to lowering of high frequency characteristics. US Patent A-4,431,460 discloses a method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices. Although this method has many of the features of the present invention, significant differences exist in the implementation of an insulator film side wall spacer, the present invention being of different composition and lower thickness reducing both stress and leakage current. Shinsuke Konaka et al "A 30ps Bipolar IC Using Super Self-Aligned Process Technology" discloses a technique for decreasing the necessary tolerances in the dimensions of the active transistor regions. A single photolithographical mask is needed to fabricate all the regions, removing the need for tolerance areas for misalignment. This process discloses nothing about the function of base/emitter regions by double diffusion through polysilicon. It is hence a first object of the invention to present a manufacture method of a semiconductor device capable of preventing increase of leak current and lowering of high frequency characteristics by making uniform the overlap amount between the outer marginal part of the intrinsic base layer and the inner marginal part of the extrinsic base layer surrounding the intrinsic base layer, and it manufacturing method. The manufacturing method for a bipolar transistor device, which is the object of the present invention, is defined in claim 1. DETAILED DESCRIPTION OF THE INVENTION Figs. 1a to e show an embodiment of the invention in the process sequential sectional views. An example of NPN transistor is described below. First, as shown in Fig. 1a, a window is opened in a specified region of a photoresist by employing photolithography on the surface of a (111) P-type silicon substrate 1 with the boron concentration of about 1 x 10 14 to 2 x 10 15 cm -3 . Using this photoresist pattern as the mask, a dose of 1 to 4 × 10 15 cm -2 of antimony ions are implanted into the P-type silicon substrate 1 at an acceleration energy of 40 to 100 KeV. Afterwards, by performing heat treatment in an oxygen atmosphere for about 30 minutes at 1200°C, an N-type buried collector layer 2 with junction depth of about 1 to 2 µm and surface concentration of about 1 to 3 × 10 19 cm -3 is formed. Heat treatment in the oxygen atmosphere, instead of nitrogen atmosphere, is intended to prevent nitriding of the surface of the silicon substrate 1, because nitriding causes crystal defects and induces deterioration of device characteristics. The substrate of (111) is used in this example, but the crystal direction of the substrate is not particularly limited. The oxide film on the surface of the P-type silicon substrate 1 formed at the time of heat treatment is removed by etching in a mixed solution of NH 4 F and HF, and an epitaxial layer with an arsenic concentration of 5 × 10 15 to 3 × 10 16 cm -3 is formed in a thickness of about 0.8 to 1.5 µm, by using SiH 2 Cℓ 2 and AsH gas, in the conditions of approximately 1000 to 1100°C, 10 to 100 Torr. Using antimony of which diffusion coefficient is smaller than that of arsenic, by performing epitaxial growth by the CVD method at a relatively low temperature of about 1100°C or less and a reduced pressure of about 100 Torr, the up-diffusion of the N-type buried collector layer 2 of high surface concentration of 1 to 3 × 10 19 cm -3 into the epitaxial layer 3 can be controlled without about 0.3 µm at the time of expitaxial growth and of the subsequent heat treatment step. The thickness of the low impurity concentration portion of the epitaxial layer 3 may be a factor to determine the breakdown voltage of the device, and by controlling the up-diffusion, the thickness of the expitaxial layer 3 may be reduced while maintaining a sufficient thickness of the low impurity concentration portion of the epitaxial layer 3 necessary for guaranteeing the breakdown voltage of 7V or more between the collector and emitter, and collector and base. The film thickness of the epitaxial layer 3 is one of the factors to determine the operating speed of the device, and by reducing the thickness of the epitaxial layer 3 to 1.5 µm or less, the collector transit time of the carrier in transistor operation can be shortened, so that a device capable of operating at high speed may be realized. Furthermore, by reducing the thickness of the epitaxial layer 3 to 1.5 µm or less, the thickness of the LOCOS film for device isolation formed in a subsequent process may be also reduced, and the oxidation time for forming the LOCOS film may be shortened. Incidentally, when the silicon is oxidized, the volume expands, and undulations are formed on the silicon substrate surface when selectively oxidizing as in the case of formation of LOCOS film for device isolation, and therefore the step differences due to undulations of the LOCOS film may be decreased while reducing the thickness of the LOCOS film for device isolation. If the antimony dose is increased from the prescribed condition, the breakdown voltage of the device is lowered as mentioned above the to up-diffusion of the N-type buried collector layer 2 into the epitaxial layer 3 by heat treatment. To the contrary, when the antimony dose is decreased from the specified amount, the sheet resistance of the N-type buried collector layer 2 increases and the collector resistance grows, thereby lowering the transistor characteristics. The impurity concentration of the epitaxial layer 3 is an important factor for determining the transistor breakdown voltage and the capacity due to the depletion layer width of collector-base junction. Meanwhile, spreading of the effective base width due to excessive carriers in the base region when the transistor operates at high current density is called the Kirk effect, and the impurity concentration of the epitaxial layer 3 is one of the factors to determine this base spreading. The arsenic concentration of the epitaxial layer 3 is defined within 5 × 10 15 to 3 × 10 16 cm -3 in order to maintain a sufficient transistor breakdown voltage, reduce the junction capacity between collector and base, and avoid lowering of high frequency characteristics due to the Kirk effect when the transistor operates at high current density. The advantages of using antimony as the impurity for forming the N-type buried collector layer 2 are mentioned herein, but it is not required to limit to the antimony, but by using arsenic, for example, it is possible to form a device possessing characteristics close to the case of using antimony. However, the optimum conditions are different in the impurity concentration of the N-type buried collector layer 2, impurity concentration of epitaxial layer 3, and film thickness. In this embodiment, assuming an integrated circuit, the N-type buried collector layer 2 is formed in the P-type silicon substrate 1 for device isolation, but where the device isolation is not necessary, such as the discrete semiconductor devices, without forming the buried collector layer 2, an epitaxial layer 3 may be directly formed on the N-type silicon substrate 1 with an impurity concentration of 3 × 10 17 to 3 × 10 19 cm -3 approximately. Succeedingly, by the low pressure CVD method using SiH 2 Cℓ 2 , NH 3 , a silicon nitride film 4 is grown in a thickness of 70 to 150 nm on the entire surface of the epitaxial layer 3, and then the nitride film 3 in the device isolation region is removed by RF dry etching in a mixed gas of CF 4 , CH 3 Br, O 2 , by using the photoresist pattern exposed and developed so as to open the device isolation region as the mask. Furthermore, the N-type epitaxial layer 3 is removed by a depth of about 0.4 to 0.8 µm by RF dry etching, using SF 6 gas, and a silicon groove 5 in a depth of about half of film thickness of the epitaxial layer 3 is formed, and the photoresist is removed by O 2 plasma ashing. Next, as shown in Fig. 1b, using the nitride film 4 as the mask, a LOCOS film 6 for device isolation is formed in a thickness of 1 to 1.8 µm as a first insulation film by selective oxidation by the high pressure pyro-oxidation method at 5 to 10 atmospheric pressures at 950 to 1050°C. To form the silicon groove 5 in a depth of about half of the thickness of the LOCOS film 6 for device isolation before forming the LOCOS film 6 is intended to reduce the film thickness of the LOCOS film 6 reaching the P-type silicon substrate 1 to about half that without the silicon groove 5, and to decrease the undulation formed on the surface due to formation of the LOCOS film 6 for by filling the silicon groove 5 with the LOCOS film which nearly coincides with the principal plane of the epitaxial layer due to expansion of the oxidized silicon. By employing, moreover, the high pressures pyro-oxidation method of 5 to 10 atmospheric pressures in this step, oxidation rate equivalent to that at high temperature of about 1200°C is realized, and at low temperature of 1050°C or less and by shortening the oxidation time, up-diffusion of the N-type buried collector layer 2 into epitaxial layer 3 due to heat treatment for oxidation may be decreased. After etching and removing the nitride film 4 by using phosphoric acid solution, a polysilicon 7 to be used as a base lead-out electrode is formed in a thickness of about 300 to 500 nm by low pressure CVD method in SiH 4 gas, and sequentially an oxide film 8 is grown on the entire surface of the polysilicon 7 in a thickness of about 150 to 300 nm by the low pressure CVD method by SiH 2 Cℓ 2 , N 2 O. For the purpose of lowering the resistance of the polysilicon 7 as the base lead-out electrode, boron of P-type impurity as first impurity is doped by ion implantation into the polysilicon 7 in the conditions of implantation energy of 40 to 80 KeV and dose of 5 × 10 15 to 2 × 10 16 cm -2 . Then the oxide film 8 is removed by RF dry etching in a mixed gas of CHF 3 , NH 3 , and O 2 . Consequently, in SF 6 , C 2 CℓF 5 gas, the polysilicon 7 is removed by anisotropic dry etching. Removal of both oxide film 8 and polysilicon 7 is effected by using, as the mask, the photoresist pattern in a width of about 1.0 to 1.5 µm exposed and developed so as to open, excluding the base polysilicon electrode region, and an intrinsic base region 9 is exposed on the surface of the N-type epitaxial layer 3. Afterwards, the photoresist is removed by O 2 plasma ashing. Herein the conditions are defined such as the film thickness of polysilicon 7 to be used as the base lead-out electrode in a range of 300 to 500 nm, the film thickness of oxide film 8 about 150 to 300 nm and boron ion implantation energy in 40 to 80 KeV, which is intended to dope the boron sufficiently into the polysilicon 7 even in ion implantation across the oxide film 8, and to prevent the boron ions from reaching the intrinsic base region 9 on the surface of the N-type epitaxial layer 3, penetrating through the polysilicon 7. In orher words, if the boron penetrates through the polysilicon 7 and reaches the intrinsic base region 9 on the surface of the epitaxial layer 3, the current gain of the transistor and operating frequency are lowered, and the device characteristics deteriorate. The reason why the oxide film 8 is not grown by the low pressure CVD method after ion implantation is to prevent the boron from entering the intrinsic base region 9 on the surface of the N-type epitaxial layer 3 due to solid state diffusion of boron impurities in the polysilicon 7 by heat treatment, usually at about 800°C, at the time of low pressure CVD growth. At the boron dose of about 5 × 10 15 to 2 × 10 16 cm -2 , a polysilicon base lead-out electrode with sheet resistance of about 60 to 120 Ω/square may be formed. If the dose is larger than in this condition, the P-type external base layer 11 described below becomes deeper. Moreover, along with the increase of the base-collector junction capacity, the high frequency characteristics of the transistor deteriorate. Or if the dose is smaller than in this condition, the base resistance increases, and the overlap between the P-type extrinsic base layer 11 and the intrinsic base layer 16 becomes insufficient, which may also lead to lowering of characteristics. In sequence, as shown in Fig. 1c, by the low pressure CVD method with SiH 2 Cℓ 2 , NH 3 , a nitride film 10 is grown on the entire surface of the oxide film 8, polysilicon 7 and epitaxial layer 3 in a thickness of 50 to 120 nm, and boron is diffused in the N-type epitaxial layer 3 from the P+ polysilicon 7 by heat treatment, thereby forming the P-type extrinsic base layer 11. At this time, when the heat treatment condition is specified as N 2 atmosphere, about 1000°C and about 30 to 60 minutes, the extrinsic base layer 11 by boron is formed at a junction depth of about 0.25 to 0.35 µm and a surface concentration of about 1 to 3 × 10 20 cm -3 . Incidentally, the nitride film 10 becomes an electrical insulator between the base lead-out electrode 7 or extrinsic base layer 11 and the emitter electrode. Therefore, it is necessary to have a sufficient reliability as insulation film. Besides, if the nitride film 10 is too thick, the characteristic deterioration of the transistor due to stress of the nitride film 10 is predicted. Accordingly, a proper thickness of the nitride film 10 is about 50 to 120 nm. Consequently, as shown in Fig. 1d, the polysilicon grown on the entire surface of the nitride film 10 in a thickness of about 250 to 350 nm by the low pressure CVD method of SiH 4 is subjected to anisotropic etching in a mixed gas of SF 6 and CCℓ 4 which is a gas condition capable of etching at an extremely high degree of anisotropy, thereby forming a polysilicon side wall 12. Using this polysilicon side wall 12 as the mask, the nitride film 10 in other areas than the side wall of the base lead-out electrode 7 and peripheral part 13 of the intrinsic base region 9 is subjected to RF etching in CF 4 , CHBr 3 , O 2 gas, so that the emitter lead-out part hole 14 is self-aligned so as to be of equal distance to the base lead-out electrode 7 at any position around the hole. Thus, self-aligned forming of the base lead out electrode 7 and the emitter lead-out part hole 14 is intended to open a fine emitter lead-out part beyond the limit of the photolithographic technology, and to form extremely finely the extrinsic base layer 11 which is a parasitic region impeding the high speed operation of the device without having to consider the mask alignment margin photolithography or other conditions. Finally, as shown in Fig. 1e, the polysilicon grown in 200 to 300 nm by the low pressure CVD method of SiH 4 is subjected to RF etching with SF 6 , C 2 CℓF 5 gas selectively, using as the mask the photoresist pattern exposed and developed so as to open only the emitter polysilicon electrode region, and a polysilicon emitter electrode 15 is formed. In consequence, by O 2 plasma ashing, the photoresist is removed. Then boron of P-type impurity as a second impurity is doped in the polysilicon emitter electrode 15 by ion implantation selectively, by using as the mask the photoresist pattern exposed and developed so as to open the emitter polysilicon electrode region, and after removing the photoresist by O 2 plasma ashing, boron is diffused into the intrinsic base region 9 from the polysilicon emitter electrode 15 through the emitter lead-out part hole 14 by heat treatment in N 2 atmosphere, thereby forming a P-type intrinsic base layer 16. Furthermore, in the polysilicon emitter electrode 15, arsenic of N-type impurity as a third impurity is doped by ion implantation at 40 to 80 KeV, by about 5 × 10 15 to 2 × 10 16 cm -2 , selectively by using as the mask the photoresist pattern exposed and developed so as to open the emitter polysilicon electrode region, and after removing the photoresist by O 2 plasma ashing, arsenic is diffused into an intrinsic base layer 16 from the polysilicon emitter electrode 15 through the emitter lead-out part opening 14 by heat treatment in N 2 atmosphere, thereby forming an N-type emitter layer 17. In the process of forming the intrinsic base layer 16, when the boron ion implantation into the polysilicon of the emitter electrode 15, if the boron ions penetrate through the emitter electrode 15 to reach the epitaxial layer 3, the junction of the intrinsic base layer 16 becomes deep, and the base transit time of the transistor becomes long, which leads to lowering of the high frequency characteristics of the transistor, and therefore the polysilicon film thickness and ion implantation conditions are determined so that the boron ions may not penetrate through the polysilicon of the emitter electrode 15. Therefore, if the polysilicon film thickness of the emitter electrode 15 is excessive, the emitter resistance increases and the high frequency characteristics of the transistor deteriorate, and hence the maximum thickness is around 300 nm, but when the polysilicon film thickness is 300 nm and the boron ion is implanted, the implantation energy should be 30 KeV or less. By the drive-in heat treatment of the intrinsic base layer 16 of the ion implantation dose of about 2 to 4 × 10 14 cm -2 , 900 to 950°C, and about 30 to 60 minutes, the intrinsic base layer 16 of about 0.1 to 0.15 µm is formed at the surface concentration of 5 × 10 18 to 2 × 10 19 cm -2 is formed. The emitter layer 17 is formed as an extremely shallow layer at a depth of 0.05 µm or less, with a surface concentration of about 3 × 10 20 cm -3 , if the heat treatment is done for about 30 minutes at 900°C. The diffusion length in the lateral direction of each diffusion layer is about 80 to 85% of the depthwise direction, and at any position around the emitter lead-out part hole 14, a sufficient and uniform overlap of the extrinsic base layer 11 and intrinsic base layer 16 must be obtained under the nitride film 13 between the base lead-out part hole and emitter lead-out part hole 14, while the overlap between heavily doped diffused layers between the P-type extrinsic base layer 11 and N-type emitter layer 17 must be minimized and the problems of reliability and others due to tunneling currents and the like must be avoided, and hence for these purposes it is desired to set the following conditions. That is, the junction depth of the extrinsic base layer 11 is about 0.25 to 0.35 µm, and by forming a side wall 12 by polisilicon in a thickness of 250 to 350 nm, the spacing between the emitter lead-out part hole 14 and the base lead-out part opening which consists of the inner marginal part of the LOCOS film 6 for device isolation and the nitride film 13 of the side wall of the polysilicon base electrode 7 should be set at about 0.25 to 0.35 µm. Thus, the boron of P-type impurity is doped by ion implantation into the polysilicon emitter electrode 15, the boron is introduced into the intrinsic base region 9 from the polysilicon emitter electrode 15 through the emitter lead-out part hole 14 by heat treatment, and the P-type intrinsic base layer 16 is formed, which is intended to form the intrinsic base layer 16 of about 0.10 to 0.15 µm in junction depth without having to restrict channeling by inclining the ion implantation angle by about 7 degrees as in the prior art since the diffusion of impurity is very fast in the polysilicon as compared with that in the silicon substrated, and to avoid the crystal defect of the surface of the intrinsic base region 9 accompanying damage at the time of ion implantation. In particular, polysilicon is used in the base electrode because, in the self-aligned transistor, the damage on the surface of the intrinsic base region 9 when etching the polysilicon and exposing the intrinsic base region at the time of forming the base lead-out electrode 7 may induce defects to seriously influence the transistor characteristics at the time of ion implantation into the intrinsic base region 9 in a subsequent process. This problem, on the other hand, may be avoided by the method of forming the P-type intrinsic base layer 16 by introducing boron into the intrinsic base region 9 from the polysilicon emitter electrode 15 through the emitter lead-out part hole 14 by heat treatment. Besides, the side wall part is in double structure of polysilicon 12 and nitride film 13 as shown in the embodiment in Fig. 1, which is because the base-emitter junction around the emitter most seriously influencing in the bipolar transistor is covered by the nitride film 13 and its effect as the passivative film is expected, so that a reliable transistor may be formed. Besides, considering smaller stress of the polysilicon than of the nitride and the reduction of stress due to decrease of nitride film thickness, lowering of the transistor characteristics due to stress may be prevented. Figs. 2 is a plotting of the characteristics such as reverse bias punch-through leak current (a) between collector and emitter of a transistor having the structure of the invention, reverse bias tunneling current (b) between emitter and base, cut-off frequency (c) and base resistance (d), with respect to the spacing between the base lead-out part hole and emitter lead-out part hole, shown in comparison with the conventional structure. When the spacing between the holes becomes short until the lateral diffusion part of the P-type extrinsic base layer 11 enters the N-type emitter layer 17, the tunneling current increases between the emitter and base, and the junction capacity between emitter and base increases and the base Gummel number in the emitter periphery increases, so that the cut-off frequency drops. To the contrary, when the hole interval is longer, the overlap between the P-type extrinsic base layer 11 and the intrinsic base layer 16 in the peripheral part of the emitter region is not sufficient, and the punch-through leak between collector and emitter and the base resistance increase may occur. In the transistor having the structure by self-aligned technology, it is important to optimize the emitter-base hole interval from the viewpoint of the trade-off as described above. As shown in Fig. 2, in the prior art, if the hole interval is wide, in particular, the problem of the uneven and insufficient overlap of the P-type extrinsic base layer 11 and intrinsic base layer 16 becomes more serious. Comparing the manufacturing method of the invention with the prior art, this invention is advantageous when optimizing the emitter-base hole interval, and there is a high margin against unevenness in the process. The example of NPN transistor is described so far, and the invention may be similarly applied to the PNP transistor as well. As described herein, according to the manufacturing method of the invention, the overlap between the extrinsic base and intrinsic base layer is sufficient, and a self-aligned bipolar transistor having an extremely shallow intrinsic base layer may be formed. Therefore, without having to increase the leak current between the collector and emitter or the base resistance, the cut-off frequency of transistor and high frequency characteristics of the integrated circuit may be greatly enhanced.

Claims: A manufacturing method for a bipolar transistor device comprising the steps of: forming an intrinsic base region (9) in an epitaxial layer on the surface of a semiconductor layer (2) of a first conductivity type by forming a first insulation film (6) in other areas than an intrinsic base region (9) around said intrinsic base region (9), forming a first semiconductor film (7) of a second conductivity type on said intrinsic base region (9) and said first insulation film (6), forming a second insulation film (8) on the surface of said first semiconductor film (7), forming an opening by selectively etching and removing said second insulation film (8) and said first semiconductor film in order to expose a first portion of said intrinsic base region (9), said opening leaving a portion of said first semiconductor film (7) on a peripheral area of said intrinsic base region (9) around the opening, forming a third insulation film (10) on said second insulation film (8), the side surface of said first semiconductor film (7) exposed at the opening (7) and said first exposed portion of said intrinsic base region (9), forming an extrinsic base layer (11) by doping a first impurity in said intrinsic base region (9) from said portion of the first semiconductor film (7) on the peripheral area of the intrinsic base region, forming a second semiconductor film on the surface of said third insulation film (10), said second semiconductor film is subjected to an anisotropic etching thereby forming sidewall (12) on the side surface of said first semiconductor film (7) exposed at the opening, using said sidewall (12) to etch said third insulation film (10) from all areas other than a portion (13) between said side surface of said first semiconductor film and the sidewall (12), so that an emitter window (14) is formed at the centre of said opening, thereby exposing a second portion of the intrinsic base region (9) smaller than said first portion, forming an emitter lead-out electrode (15) by forming a third semiconductor film in said emitter window (14) and forming an intrinsic base layer (16) of said second conductivity type and emitter layer (17) of said first conductivity type by introducing second and third impurities into said intrinsic base region (9) from said emitter lead-out electrode (15). A manufacturing method of semiconductor device of claim 1, wherein said epitaxial layer has an arsenic concentration of 5 x 10 15 to 3 x 10 16 cm -3 . A manufacturing method of semiconductor device of claim 1 or 2, wherein said semiconductor layer is composed of an N-type buried collector layer by ion implantation of antimony into a P-type silicon substrate at a dose of 1 to 4 x 10 15 cm -2 . A manufacturing method of semiconductor device of claim 2, wherein a groove is formed in said semiconductor layer, and then said first insulation film is formed in said groove. A manufacturing method of semiconductor device of claim 1, wherein said first insulation film (6) is formed by high pressure pyro-oxidation method at 5 to 10 atmospheric pressures. A manufacturing method of semiconductor device of claim 1, wherein said first semiconductor film (7) is formed in a thickness of 300 to 500 nm, said second insulation film (10) is formed on the surface of said first semiconductor film in a thickness of 150 to 300 nm, and then the impurity is doped in said first semiconductor film across said second insulation film. A manufacturing method of semiconductor device of claim 1, wherein the thickness of said third insulation film is 50 to 120 nm. A manufacturing method of semiconductor device of claim 1, wherein the thickness of said third semiconductor film is 300 nm or less, said second and third impurities are implanted into said third semiconductor film at an implantation energy 30 keV or less, and thereby said intrinsic base layer is formed.

Inventors: SAWADA SHIGEKI, SAWADA, SHIGEKI
Applicants: MATSUSHITA ELECTRONICS CORP, MATSUSHITA ELECTRONICS CORPORATION
Application year: 1990
Main classification: H01L29
IPC codes: H01L27, H01L21, H01L29