MOS-type integrated circuit

Abstract: In a MOS-type integrated circuit, a source and a gate of a double diffusion MOSFET of an n-channel type and a drain and a gate of a double diffusion MOSFET of a p-channel type are formed in an island region sur­ rounded by an n-type annular contact region (8) having high impurity concentration. An n epitaxial layer (4), formed in each island region, is used for the sources and drains of both MOSFETs. The drain (11) electrode of the p-channel MOSFET is connected to the gate (14) electrode of the n-channel MOSFET. With this structure, the power consumption of the circuit is decreased, and the operating speed thereof is increased.

Description: This invention relates to a MOS-type integrated circuit for use as an output circuit element of a high breakdown-voltage integrated circuit. In the conventional output circuit of a high breakdown-voltage integrated circuit, a p-channel MOSFET having high breakdown voltage and serving as a level shifter, and an n-channel D-MOSFET having high breakdown voltage, are formed in different island regions of a silicon semiconductor substrate, and are electrically isolated from each other. The structure of this output circuit will be explained, with reference to Fig. 1 showing an essential part thereof. After an oxide (not shown) is deposited on a surface of a p-type silicon semiconductor substrate 50 having boron-concentration of about 5 × 10 14 /cm 3 , openings are formed in the oxide film at predetermined locations by means of photo lithography. Through the openings, antimony (Sb) is doped in the substrate 50. Then, a layer 51, having a phosphorus concentration of 1 × 15 15 /cm 3 , is epitaxially formed on the substrate, thus forming buried regions 52 having an antimony concentration of about 10 18 /cm 3 . p-isolating regions 53, having a surface impurity-concentration of about 1 × 10 19 /cm 3 , are formed in the n - -epitaxial layer 51, defining island regions. Further, deep n-regions 54, having a surface impurity-concentration of about 1 × 10 19 /cm 3 , are formed at the both sides of the buried regions 52. In the upper end portion of the deep n-region 54 of one of the buried regions 52, n-region 55, having a surface arsenic(As)-concentration of about 1 × 10 20 /cm 3 , is formed such that it is in ohmic contact with an electrode to be formed later. A p - -region 56, having a surface boron-concentration of about 1 × 10 17 /cm 3 , is formed in one of the island regions of the n - -epitaxial layer 51. In the p-region 56, n + -regions 57, having a surface As-concentration of about 1 × 10 20 /cm 3 , are formed. A p + -region 58 is formed between the regions 57. The region 58 has a surface boron-concentration of about 1 × 10 20 /cm 3 . On the other hand, in the other island region, an n - -region 59, having a phosphorus concentration of about 1 × 10 17 /cm 3 , is formed such that it contacts one of the deep n-regions 54. In the region 59, a p + -region 60 and an n + -region 61 are formed such that they contact each other. The region 60 has a surface boron-concentration of about 1 × 10 20 /cm 3 , and the region 61 has a surface arsenic-concentration of about 1 × 10 20 /cm 3 . Moreover, a p-region 62 is formed such that it contacts the region 59. The region 62 is formed by doping boron about 5 × 10 16 /cm 3 , and has a large Xj. In the region 62, a p-region 63 is formed which has a surface boron-concentration of about 1 × 10 20 /cm 3 . The pn junctions formed of the above-described various impurity regions are exposed in the surface of the layer 51, and are protected by an insulating layer 64. While the layer 64 is shown as one layer in Fig. 1, it is formed of a CVD oxide layer and a thermally oxidized film. Polycrystal silicon layers 65 are buried in the insulating layer 64. A gate electrode 66, a source electrode 67 and a drain electrode 68 made of Aℓ or Aℓ alloy are provided at related openings. Each opening is formed by removing part of the insulating layer 64 above the polycrystal silicon layer 65. A resistor 69 made of polycrystal silicon is formed on the insulating layer 64, and connected to the source and drain electrodes 67 and 68. As is described above, the p-channel MOSFET and n-channel MOSFET are formed in different island regions of the conventional MOS-type integrated circuit. This structure makes the circuit have a large total parasitic capacitance as much as that of two MOSFETs, since parasitic capacitance is proportional to the area of an element. This being so, an extra amount of current is charged or discharged for the parasitic capacitance during the operation of the circuit, inevitably increasing the power consumption, and also increasing the time required for the charge/discharge and hence decreasing the operation speed. This invention has been made to overcome the above-described disadvantages, and therefore intends to save the power consumption of an output circuit having high breakdown voltage and comprising a MOS-type integrated circuit, and also to increase the operation speed of the circuit. According to the present invention, there is provided a MOS-type integrated circuit comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type, on the semiconductor substrate; a buried region of the second conductivity type, having high impurity concentration and formed between the semiconductor substrate and semiconductor layer; an annular contact region of the second conductivity type, extending from the buried region to the surface of the semiconductor layer, surrounding the semiconductor layer and having high impurity concentration; a first region of the second conductivity type formed in contact with the second conductivity-type annular contact region, having low impurity concentration and extending into the semiconductor layer; a third region of the first conductivity type and a second region of the second conductivity type, which have high impurity concentration and which are formed in contact with each other in the first region of the second conductivity type; a first region of the first conductivity type, formed in the semiconductor layer, having low impurity concentration and being in contact with the first region of the second conductivity type; a fourth region of the first conductivity type having high impurity concentration and formed in the first region of the first conductivity type; a second region of the first conductivity type having low impurity concentration and formed in the upper surface of the semiconductor layer of the second conductivity type surrounded by the annular contact region and laterally spaced from the first region of the second conductivity type and laterally spaced from the first region of the first conductivity type; a third region of the second conductivity type, a fifth region of the first conductivity type, and a fourth region of the second conductivity type, which have high impurity concentration, and are formed in the second region of the first conductivity type, whereby said fifth region is located between and in contact with the third and fourth regions of the second conductivity type; an insulating layer covering junctions which are formed by the regions of different conductivity types and formed on the semiconductor layer of the second conductivity type and the annular contact region; a first polycrystal silicon layer buried in the insulating layer at a location corresponding to the first region of the second conductivity type, and between the first region of the first conductivity type, and the third region of the first conductivity type; a second polycrystal silicon layer buried in the insulating layer at a location corresponding to the second region of the first conductivity type, and surrounding the third region of the second conductivity type, the fifth region of the first conductivity type, and -the fourth region of the second conductivity type; a drain electrode electrically connected to the third region of the first conductivity type and to the second region of the second conductivity type through the insulating layer and projecting from the surface of the insulating layer; a source electrode electrically connected to the fifth region of the first conductivity type, and to the third and fourth regions of the second conductivity type through the insulating layer and projecting from the surface of the insulating layer; first and second gate electrodes electrically connected to the first and second polycrystal layers through the insulating layer and projecting from the surface of the insulating layer. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a sectional view of an essential part of a conventional MOS-type integrated circuit; Fig. 2 is a sectional view of an essential part of a MOS-type integrated circuit according to the present invention; Fig. 3 is a circuit diagram of an output circuit having high breakdown voltage, useful in comparing the structure of the present invention to that of the conventional circuit; and Figs. 4A through 4M show sectional views explaining the manufacturing process of the MOS-type integrated circuit in order, according to the invention. This invention will now be explained with reference to Figs. 2 to 4 showing an embodiment thereof. The structure shown in Fig. 2 is manufactured by the process shown in Figs. 4A to 4M. An oxide film 2 having a thickness of 0.1 µm is laminated on a p-type silicon semiconductor substrate 1, which has a boron (B) concentration of 5 × 10 14 /cm 3 , by steam oxidization at 1100°C (Fig. 4A). An opening is formed in a predetermined portion of the oxide film 2 by photoetching (Fig. 4B). Subsequently, a predetermined amount of antimony (Sb) is doped and diffused in the surface of the exposed portion of the p-type silicon semiconductor substrate, to thereby form a base of a buried region 3, which has an Sb concentration of 10 18 /cm 3 , as is shown in Fig. 4C. Then, as is shown in Fig. 4D, an n - -layer 4, having a phosphorus (P) concentration of about 1 × 10 15 /cm 3 , is deposited on the substrate 1 and base 3 by means of epitaxial growth method until it has a thickness of 1.5 µm. Further, an oxide film 5 having a thickness of 0.1 µm is formed on the n - -layer 4 by steam oxidization at about 1000 °C, which film is to be used as a mask in ion-implantation step, hereinafter referred to. As a result the buried region 3, having the above-described surface impurity-concentration and a thickness of about 3 µm, is formed between the p-type silicon semiconductor substrate 1 and n - -layer 4. As is shown in Fig. 4E, a photo-resist pattern 6 is deposited on the mask oxide film 5, which pattern has an annular opening formed therein at a location corresponding to an annular deep diffusion layer 8 and 8 (hereinafter referred to), to be formed as contacts of the buried region 3. Thereafter, phosphorus is doped in the n - -layer 4 by ion-implantation method. Further, after the photo-resist pattern 6 is removed from the layer 4, another photo-resist pattern 7 having opening, for forming isolating region by diffusion, is deposited on the same, through which opening boron is doped in the layer 4 by the ion-implantation method, as is shown in Fig. 4F. The photo-resist pattern 7 is then removed, and the chip is heated in the atmosphere of nitrogen at 1200°C for an hour, thus making the ion-diffused layer reach the buried region 3 and the boundary between the n - -layer 4 and p-type silicon substrate 1, thereby forming the annular deep n-region (i.e., annular contact region) 8 and 8 and isolating region 9 and 9. The deep n-region 8 and isolating region 9 have a surface impurity-concentration of about 1 × 10 19 /cm 3 . Subsequently, a photo-resist pattern 10 having an opening for forming a high-resist drain region for a p-channel MOSFET, and boron is doped in the layer 4, as is shown in Fig. 4G. Thereafter, the photoresist pattern is removed, and the chip is subjected to slumping process, in which it is heated in the atmosphere of nitrogen at 1200°C. In this process, a drain high-resistance region (i.e., a first region of the first conductivity type) 11, having a low surface impurity-concentration of 5 × 10 16 /cm 3 and a thickness of 4 µm, is formed and a thermal oxide film 12 having a thickness of 1 µm is formed by a known method, after the mask oxide film 5 is removed, as is shown in Fig. 4H. A new photo-resist pattern is formed on the oxide film 12, and predetermined portions of the film is removed therefrom by isotropic or aerotropic etching, thereby exposing the n - -layer 4 (Fig. 4I). Subsequently, a gate oxide film 13 having a thickness of 0.1 µm is formed on the layer 4 by oxidization with the use of steam of 1000°C. First and second polycrystal silicon layers 14 and 15 having a thickness of 5 µm are deposited by CVD (Chemical Vapor Deposition), and patterned. As is shown in Fig. 4J, the polycrystal silicon layer 14 is patterned by photo etching, such that it is provided at a location corresponding to a p-type region 16 (i.e., a second region of a first conductivity type) having low impurity concentration, hereinafter referred to. The size of the layer 14 in contact with gate oxide film 13 is substantially equal to the diameter of the p-type region 16 to be formed 1.5 µm thick by implanting and diffusing boron in the n - -layer 4. Similarly, the other polycrystal silicon layer 15 is patterned by photoetching such that it is provided at a location corresponding to an n-type region 17, hereinafter referred to. The size of the layer 15 is substantially equal to the diameter of the n-type region 17 to be formed 1.5 µm thick by implanting and diffusing phosphorus in the n - -layer 4. The region 17 functions as a back gate, and has an Xj smaller than the drain high-resistance region 11. To dope boron using the layer 14 as a mask, boron is ion implanted after a photo-resist pattern, made such that only a portion indicated by A (Fig. 4J) is open, covers the chip. Then the photo-resist is removed. To dope phosphorus using the layer 15 as a mask, phosphorus is ion implanted after a photo-resist pattern, formed such that only a portion indicated by B (Fig. 4J) is open, covers the chip. Then, the photo-resist is removed and the doped materials are diffused for half an hour at 1200°C in the atmosphere of nitrogen, as is shown in Fig. 4K. Subsequently, another photo-resist pattern is provided thereon, which has openings formed at locations corresponding to an n + (i.e., the second conductivity type) region 18, a first region 21 (corresponding to the region indicated by B in Fig. 4J), a second region 19, and a third region 20, which are to be formed 0.5 µm thick. Then, arsenic As is doped through the openings by ion implantation, and the chip is subjected to slumping for half an hour at 1000°C in the atmosphere of nitrogen. Further, to form a third region 22, a second region 23, and a first region 24, which are the first conductivity or p + -type and have a thickness of 0.5 µm, another photo-resist pattern is provided on the chip after the previous pattern is removed, which has openings corresponding to the respective regions, then doping boron by ion implantation method, performing thirty-minute slumping at 1000°C in the atmosphere of nitrogen, and thus obtaining the chip shown in Fig. 4L. Subsequently, as is shown in Fig. 4M, a silicon oxide layer 25, made of e.g. SiO 2 , is deposited by the CVD, until the layer has a thickness of 1 µm, thereafter forming a contact hole by photo etching, further depositing an Aℓ or Aℓ alloy (Aℓ-Si; Aℓ-Si-Cu) layer about 1 µm thick by the CVD or sputtering, and finally patterning the chip by photo etching to form an electrode 26, as is shown in the completed circuit of Fig. 2. In sintering process, the chip is heated for half an hour at 450°C in the nitrogen atmosphere. Further, a passivation layer, consisting of a single layer or of a plurality of layers and made of PSG (Phosphor Silicate Glass), silicon nitride or the like, is formed on the surface of the chip in the final process, which process is not shown in the figures. Moreover, it is needless to say that the other semiconductor elements, required for the MOS-type integrated circuit, are incorporated in the other island regions (not explained in the above) of the circuit. The MOS-type integrated circuit, constructed as above, does not require the conventional resistance 69, as can be understood from Fig. 3, and incorporates the n-channel MOSFET having high breakdown voltage and the level-shifting p-channel MOSFET having high breakdown voltage, which are formed in the same island region. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A MOS-type integrated circuit comprising: a semiconductor substrate (1) of a first conductivity type; a semiconductor layer (4) of a second conductivity type, on the semiconductor substrate; a buried region (3) of the second conductivity type, having high impurity concentration and formed between the semiconductor substrate (1) and semiconductor layer (4); an annular contact region (8) of the second conductivity type, extending from the buried region (3) to the surface of the semiconductor layer (4), surrounding the semiconductor layer (4) and having high impurity concentration; a first region (17) of the second conductivity type formed in contact with the second conductivity-type annular contact region (8), having low impurity concentration and extending into the semiconductor layer (4); a third region (24) of the first conductivity type and a second region (21) of the second conductivity type, which have high impurity concentration and which are formed in contact with each other in the first region (17) of the second conductivity type; a first region (11) of the first conductivity type, formed in the semiconductor layer (4), having low impurity concentration and being in contact with the first region of the second conductivity type; a fourth region (23) of the first conductivity type having high impurity concentration and formed in the first region (11) of the first conductivity type; a second region (16) of the first conductivity type having low impurity concentration and formed in the upper surface of the semiconductor layer (4) of the second conductivity type surrounded by the annular contact region (8) and laterally spaced from the first region (17) of the second conductivity type and laterally spaced from the first region (11) of the first conductivity type; a third region (19) of the second conductivity type, a fifth region (22) of the first conductivity type, and a fourth region (20) of the second conductivity type, which have high impurity concentration, and are formed in the second region (16) of the first conductivity type, whereby said fifth region (22) is located between and in contact with the third (19) and fourth (20) regions of the second conductivity type; an insulating layer (25) covering junctions which are formed by the regions of different conductivity types and formed on the semiconductor layer of the second conductivity type and the annular contact region; a first polycrystal silicon layer (15) buried in the insulating layer (25) at a location corresponding to the first region (17) of the second conductivity type, and between the first region (11) of the first conductivity type, and the third region (24) of the first conductivity type; a second polycrystal silicon layer (14) buried in the insulating layer (25) at a location corresponding to the second region (16) of the first conductivity type, and surrounding the third region (18) of the second conductivity type, the fifth region (22) of the first conductivity type, and the fourth region (20) of the second conductivity type; a drain electrode electrically connected to the third region (24) of the first conductivity type and to the second region (21) of the second conductivity type through the insulating layer, and projecting from the surface of the insulating layer (25); a source electrode electrically connected to the fifth region (22) of the first conductivity type, and to the third (19) and fourth (20) regions of the second conductivity type through the insulating layer and projecting from the surface of the insulating layer (25); first and second gate electrodes electrically connected to the first and second polycrystal layers through the insulating layer and projecting from the surface of the insulating layer (25). The MOS-type integrated circuit according to claim 1, wherein the first conductivity type is a p-type, and the second conductivity type is an n-type. The MOS-type integrated circuit according to claim 2, wherein the first and second gate electrodes are parts of a level-shifting p-channel MOSFET having high breakdown voltage, and an n-channel MOSFET having high breakdown voltage respectively. A MOS-type integrated circuit comprising: a common semiconductor substrate (1) of a first conductivity type; an island region, including a MOS-type integrated circuit according to any preceding claim; and other island regions incorporating other semiconductor elements.

Inventors: SHIRAI KOJI, SHIRAI, KOJI, SHIRAI, KOJI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21