Semiconductor memory

Abstract: In a semiconductor memory having word lines (12) and power source lines (13) such as bit lines, two word lines extending on both sides of each contact hole (14) of one of the power source lines (13) extending adjacent to each other extend between two adjacent contact holes (14) of the other power source line, which are staggered from the contact hole of the one power source line. A peripheral circuit of the semiconductor memory can be simplified although the memory is suitable for high-speed operation and high integration.

Description: BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to a semiconductor memory wherein contact holes which connect active regions of a semiconductor substrate and power source lines on said semiconductor substrate are staggered from each other in two adjacent power source lines, and two word lines extending on both sides of each contact hole of one of said two adjacent power source lines extend between two adjacent contact holes of the other power source line, which are staggered from the contact hole of the one power source line. Such a semiconductor memory is known from US-A-4,384,349. Fig. 1 is a conventional mask ROM invented by the present inventor. In this mask ROM, a plurality of strip-like active regions 11 extend parallel to each other in a semiconductor substrate, and a plurality of stripe-like word lines 12 consisting of a conductive film of the first layer on the semiconductor substrate extend parallel to each other and obliquely with respect to the active regions 11. A plurality of stripe-like power source lines 13 constituted by conductive film of the second layer on the semiconductor substrate are formed parallel to each other and extend obliquely with respect to the active regions 11. Of the two power source lines 13 adjacent to each other, when one power source line serves as a bit line, i.e., the Vcc line, the other power source line serves as a common line, i.e., the Vss line. Contact holes 14 are formed at intersections between the active regions 11 and the power source lines 13. In this case, the positional relationship between the active regions 11 and the power source lines 13 is determined so that the contact holes 14 are staggered in the adjacent power source lines 13. A half of the bit line contact hole 14 and a half of the common line contact hole 14 are present in a unit cell 15. Each contact hole 14 is shared by two unit cells 15 adjacent to each other on the active region 11. In the mask ROM described above, since the power source lines 13 are not formed by an impurity diffused region in the semiconductor substrate, it is possible to use low-resistance power source lines consisting of a polycide film or the like. Therefore, the mask ROM is suitable for high-speed access. Since the contact holes 14 are staggered in two adjacent power source lines 13, it is possible to locate the power source lines 13 closer to each other than a structure in which contact holes 14 are adjacent to each other. Therefore, the mask ROM described above is suitable for high integration. In addition, when an EPROM is formed by the layout shown in Fig. 1, floating gates (not shown) corresponding to two adjacent power source lines 13 are also staggered from each other. Therefore, it is possible to locate the power source lines 13 close to each other. Therefore, this structure is suitable for high integration. In the layout shown in Fig. 1, although the contact holes 14 are staggered from each other in two adjacent power source lines 13, as described above, the two word lines 12 extending on both sides of each contact hole 14 of one of the power source lines 13 extend on both sides of a corresponding contact hole 14 of the other power source line 13. For this reason, the word lines 12 and the power source lines 13 inevitably extend obliquely to each other. As a result, whole cell array has a shape of parallelogram. When the cell array of a parallelogram is cut and is bonded to form a rectangular shape for application convenience, peripheral circuits such as a decoder and wiring patterns are undesirably complicated. In US-A-4,384,349 mentioned above, one contact hole is connected to four transistors, which are arranged in X-shape around a contact hole. Word lines are arranged in zigzag shape and not in linear. Because four transistors of US-A-4,384,349 are arranged in X-shape, columns are selected electrically by decoder means to form the virtual ground for adjacent memory cells. OBJECT AND SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory which is suitable for high-speed access due to capability of use of low-resistance power source lines and for high integration due to capability of locating power source lines close to each other, and wherein peripheral circuits can be simple. The above object is solved by a semiconductor memory in accordance with the features of the independent claim 1. Depending claims 2 and 3 specify advantageous developments thereof. In a semiconductor memory according to the present invention, since power source lines 13 are not formed by an impurity diffused region in a semiconductor substrate, low-resistance power source lines 13 can be used. As contact holes in two adjacent power source lines are staggered from each other, the power source lines are located closer to each other than a structure in which the contact holes are formed adjacent to each other. As floating gates corresponding to two adjacent power source lines are staggered from each other, the power source lines can be located closer to each other. As the two word lines extending in parallel on both sides of each contact hole of one of two adjacent power source lines extend between two adjacent contact holes of the other Dower source line, which are staggered from the contact hole of the one power source line, the word lines are formed to be perpendicular to the power source lines. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a conventional mask ROM invented by the present inventor; and Figs. 2 and 3 are plan views showing semiconductor memories according to the first and second embodiments of the present invention, respectively. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described in detail with reference to Figs. 2 and 3, respectively. Fig. 2 shows the first embodiment which exemplifies a mask ROM. In the first embodiment, a plurality of stripe-like active regions 11 extend parallel to each other in a semiconductor substrate. A plurality of stripe-like word lines 12 consisting of a poly-Si film of the first layer on the semiconductor substrate extend parallel to each other and obliquely with respect to the active regions 11. A plurality of stripe-like power source lines 13 consisting of a poly-Si film of the second layer on the semiconductor substrate or Al film extend parallel to each other, obliquely with respect to the active regions 11, and perpendicularly to the word lines 12. In the first embodiment, of two power source lines 13, one power source line serves as a bit line, i.e., the Vcc line, and the other power source line serves as a common line, i.e., the Vss line. Contact holes 14 are formed at intersections between the active regions 11 and the power source lines 13. In this case, the contact holes 14 in two adjacent power source lines 13 are staggered from each other. A positional relationship between the active regions 11, the ward lines 12, and the power source lines 13 is determined so that the two word lines 12 extending on both sides of each contact hole 14 of one of the power source lines 13 extend between two adjacent contact holes 14 formed in the other power source line 13, which are staggered from the contact hole 14 of the one power source line 13. In the first embodiment, a half of the bit line contact hole 14 and a half of the common line contact hole 14 are located within each unit cell 15. One contact hole 14 is shared by two adjacent unit cells 15 on the active region 11. In the first embodiment having the above positional relationship between the active regions 11, the word lines 12, and the power source lines 13, as is also apparent from Fig. 2, the word lines 12 can be perpendicular to the power source lines 13. The cell array can have a rectangular shape. Cutting and bonding as in those of the conventional mask ROM in Fig. 1 need not be performed. Peripheral circuits such as a decoder and wiring patterns can be simplified in the first embodiment. Fig. 3 shows the second embodiment exemplifying an EPROM. In the second embodiment, floating gates 16 made of a poly-Si film or the like of the first layer on a semiconductor substrate are formed in intersection regions of parallelograms between active regions 11 and word lines 12. Word lines 12, i.e., control gates, are formed of a poly-Si layer or the like of the second layer on the semiconductor substrate, and power source lines 13 are made of a poly-Si film of the third layer on the semiconductor substrate or Al film. Therefore, a planar layout of the second embodiment is the same as that of the first embodiment.

Claims: A semiconductor memory, wherein contact holes (14) which connect active regions (11) of a semiconductor substrate and linear power source lines (13) on said semiconductor substrate are staggered from each other in two adjacent power source lines, and two word lines (12) extending on both sides of each contact hole of one of said two adjacent power source lines extend between two adjacent contact holes of the other power source line, which are staggered from the contact hole of the one power source line (13). characterized in that said word lines (12) are linear and extend parallel to each other and obliquely with respect to said active regions (11), each contact hole (14) is connected to two adjacent unit cells (15) of said active regions (11) which are arranged in linear obliquely with respect to said power source lines (13). A memory according to claim 1, wherein plurality of said power source lines (13) are parallel to each other, oblique with respect to said active regions (11) and perpendicular to said word lines. A memory according to claim 1 or 2, wherein an intermediate layer between said active region and said word line at an intersection between said active region and said word line constitutes a floating gate.

Inventors: NODA MASANORI, NODA, MASANORI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: G11C16
IPC codes: H01L27, G11C17, H01L21, G11C16