IMPROVEMENTS IN VARIABLE-VOLTAGE & VARIABLE-FREQUENCY POWER CONVERTER

Abstract: A power converter for supplying an AC load (LOAD) with a sum of an output voltage of multiplexed PWM inverters (INV-1 ∼ INV-4) each having an output trans­ former (TR1 ∼ TR4), and an output voltage from a direct-connection PWM inverter (INV-5) having no output transformer. One or a plurality of PWM inverters (INV-1 ∼ INV-4) constituting the multiplexed PWM inverters (INV-1 ∼ INV-4) comprise a circuit (A1, C1-C4, G1-G4) for controlling primary or exciting currents of corresponding output transformers connected thereto, and the direct-connection PWM inverter (INV-5) comprises a circuit (C5, GL) for controlling a current to be sup­ plied to the AC load.

Description: The present invention relates to a variable-voltage and variable-frequency electric power converter for a load such as a motor, and a method of controlling the same. A conventional power converter comprises a DC smoothing capacitor serving as a DC voltage source, a first inverter, a second inverter, an output transformer, a load device, a load current detector, a comparator, a current control/compensation circuit, a proportional amplifier, pulse-width modulation (PWM) controllers, etc. The first and second inverters are PWM control inverters for converting a DC voltage into a variable-voltage and variable-frequency AC voltage. The first inverter generates output voltage V L1 through the output transformer. The second inverter directly generates output voltage V L ₂. The load device is applied with a voltage of V L = V L1 + V L2 . Voltage V L is adjusted to control load current I L . When output frequency f₀ is zero, since no voltage V L1 can be generated from the output transformer, the second inverter controls load current I L , and when frequency f₀ is increased to a certain level, the first inverter controls load current I L in turn. Figs. 17 and 18 show load terminal voltage V L and input signals V₁* and V₂* of the PWM controllers of the first and second inverters as a function of output frequency f₀ in the conventional power converter. When load current I L is assumed to be constant, load terminal voltage V L is expressed by output frequency f₀ as follows: V L = V C + I L ·R L + jω₀L L I L V C : counter electromotive force of load (for motor) R L : resistance of load L L : inductance of load ω₀: 2πf₀ A broken line in Fig. 17 indicates a voltage drop caused by resistance R L of the load. A broken line in Fig. 18 indicates input signal V₁* of the PWM controller of the first inverter. V₁* = 0 is established for f₀ ≦ f min , and V₁* is proportional to f₀ in a region of f₀ > f min . A solid line in Fig. 18 indicates input signal V₂* of the PWM controller of the second inverter. Signal V₂* is controlled to output voltage V L given by equation (1) for f₀ < f min , and V₂* = I L *·R L = constant in a region of f₀ > f min . In this manner, in the conventional power converter, the second inverter need only generate required voltage V L up to minimum frequency f min at which the output transformer can be operated, and can have a smaller capacity than the first inverter. Since the first inverter generates voltage V L1 through output transformer, serial or parallel multiplexed operations of this inverter can be easily performed, and its capacity can be easily increased. Therefore, the converter is convenient for one for driving a large-capacity AC motor. According to the above conventional power converter, when output frequency f₀ becomes high and load current I L is to be controlled by the first inverter, the following problems are posed. In general, secondary voltage V L1 of the output transformer is proportional to output voltage V₁ of the first inverter. However, when a DC component is included in load current I L due to, e.g., drift of the current detector, the output transformer gradually suffers from DC polarized magnetization, and soon, its iron core is magnetically saturated to one side. As a result, secondary voltage V L1 of the output transformer is decreased, and load current I L is decreased to be lower than instruction value I L *. Then, the inverter operates to increase voltage V₁ and further saturate the iron core. Therefore, primary current I₁ of the output transformer is abruptly increased, and may become an overcurrent to destroy elements of the first inverter. In order to prevent polarized magnetization of the output transformer, the sectional area of the iron core may be increased and an air gap is provided. In this case, the weight and dimensions of the output transformer are increased, resulting in an uneconomical system. Prior art document US-A-4 698 739 discloses a 12-pulse motor drive which comprises two inverter bridges. The output of the first inverter bridge is connected to the primary winding of a transformer, and the output of the second inverter bridge is connected to the secondary winding of the same transformer. With such an arrangement, the overall output requires only one transformer of half-rating capacity, compared with the rating of the overall pair of inverter bridges. It is an object of the present invention to provide a power converter which can correct polarized magnetization of an output transformer, and can accurately control a load current, and a method of controlling the same. To solve this object the present invention provides a power converter as specified in claims 1 and 9 and a method of controlling a power converter as specified in claim 7. A power converter supplies an AC load with a sum of an output voltage from a first PWM inverter having an output transformer, and an output voltage from a second PWM inverter having no output transformer, wherein the first PWM inverter comprises a means for controlling a primary current or an exciting current of the output transformer connected to the first PWM inverter, and a means for controlling a current supplied to the AC load. The second PWM inverter controls a current to be supplied to the load regardless of output frequency f₀. The first PWM inverter can be constituted by one or a plurality of PWM inverters. Each inverter controls a primary current or an exciting current of a corresponding output transformer. An instruction value of the primary current of the transformer is given by a sum of an instruction value of the load current control, and an instruction value of the exciting current of the transformer. When the instruction value of the exciting current is given to have an almost constant effective value, the output voltage of each output transformer is increased/decreased almost in proportion to the output frequency. A sum of the output voltages of the transformers and the output voltage of the second PWM inverter is applied to the AC load, and the output voltage of the second PWM inverter is adjusted to control the load current. As a result, the first PWM inverter bears a voltage proportional to the output frequency, i.e., a voltage drop caused by a counter electromotive force (velocity electromotive force) and an inductance, and the second PWM inverter bears the remaining necessary voltage, i.e., a voltage drop caused by a resistance of the load and a transient voltage upon load current control. The capacity of the second PWM inverter can be considerably smaller than that of the first PWM inverter. When the exciting current of each output transformer is controlled to be almost constant, the output voltage of the transformer is increased/decreased in proportional to the output frequency, and an iron core is never saturated even if the frequency is lowered. Even when a DC component is included in an output voltage due to a variation of switching characteristics of self extinction elements constituting the first PWM inverter, and this causes DC polarized magnetization of the output transformers, since the exciting current of each transformer is controlled by the inverter, the DC voltage component can be automatically compensated for, and the transformers can always be operated in a state free from polarized magnetization. Therefore, the primary current of each transformer can be prevented from being increased too much, and elements can also be prevented from being destroyed by polarized magnetization of the transformers. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing an embodiment of a power converter according to the present invention; Figs. 2A to 2D are timing charts for explaining a PWM control operation of the converter shown in Fig. 1; Fig. 3 is a vector chart for explaining the operation of the converter shown in Fig. 1; Figs. 4 and 5 are graphs showing frequency-voltage characteristics for explaining the operation of the converter shown in Fig. 1; Fig. 6 is a circuit diagram showing another embodiment of a power converter according to the present invention; Fig. 7 is a circuit diagram showing still another embodiment of a power converter according to the present invention; Fig. 8 is a circuit diagram of a controller for the converter shown in Fig. 7; Figs. 9 and 11 are partial circuit diagrams of the converter shown in Fig. 7; Figs. 10A - 10D and Figs. 12A - 12B are timing charts for explaining the operation of the converter shown in Fig. 7; Fig. 13 is a circuit diagram showing another arrangement of the controller for the converter shown in Fig. 7; Figs. 14A - 14N are timing charts for explaining the operation of the controller shown in Fig. 13; Figs. 15A - 15C are views showing computer simulation results which demonstrate the effect of the control method of the present invention; Figs. 16A - 16H are timing charts for explaining a control method of the present invention; and Fig. 17 and 18 are graphs for explaining an operation of the converter shown in Fig. 8. Fig. 1 is a circuit diagram showing an embodiment of a power converter according to the present invention. In Fig. 1, reference symbol C d denotes a DC smoothing capacitor serving as a DC voltage source; INV-1, a first PWM inverter; INV-2, a second PWM inverter; and LOAD, a AC load. First PWM inverter INV-1 is a so-called voltage type PWM inverter, and comprises self-extinction elements (e.g., gate turn-off thyristors, and the like) S₁₁ to S₁₄, and diodes D₁₁ to D₁₄. Second PWM inverter INV-2 is also a voltage type PWM inverter, and comprises self-extinction elements S21 to S24 and diodes D21 to D24. AC load LOAD includes inductance L L , resistance R L , and counter electromotive force V C . As a controller, current detectors CT₁ and CT L , calculation circuit CAL, comparators C₁ and C₂, current control/compensation circuits G0(S) and G L (S), adder AD, and PWM controllers PWM₁ and PWM₂ are included. The PWM control operation of first PWM inverter INV-1 will be briefly described below. Figs. 2A to 2D are timing charts for explaining the PWM control operation of the converter shown in Fig. 1. In Fig. 2A, reference symbols X and Y denote PWM control carrier signals, and Y is an inverted value of X (in other words, having a 180° phase difference). V₁* denotes an input signal of PWM controller PWM₁ of first PWM inverter INV-1. Upon comparison between V₁* and carrier signals X and Y, gate signals g₁₁ and g₂₂ for elements S₁₁ to S₁₄ constituting first inverter INV-1 are generated. More specifically, When V₁* ≧ X, g₁₁ = "1", and S₁₁: ON, S₁₂: OFF When V₁* < X, g₁₁ = "0", and S₁₁: OFF, S₁₂: ON When V₁* ≧ Y, g₁₂ = "1"' and S₁₃: OFF, S₁₄: ON When V₁* < Y, g₁₂ = "0" and S₁₃: ON, S₁₄: OFF When the voltage of smoothing capacitor C d is given by V d , output voltage V₁ of first inverter INV-1 is given by: V₁ = +V d when S₁₁ and S₁₄ are ON V₁ = -V d when S₁₂ and S₁₃ are ON V₁ = 0 in other modes More specifically, when the phases of carrier signal X for determining a firing signal of elements S₁₁ and S₁₂, and carrier signal Y for determining a firing signal of elements S₁₃ and S₁₄ are shifted by 180°, output voltage V₁* of first PWM inverter INV-1 has a waveform controlled by a frequency twice a switching frequency of the elements. Average value V ₁ (indicated by broken lines) of the waveform of V₁ is proportional to input signal V₁* of PWM₁. The PWM control operation of second PWM inverter INV-2 is similarly executed. A load current control operation will be described below. Load current I L is controlled by second PWM inverter INV-2. First, current I L supplied to load LOAD is detected by current detector CT L , and the detected current is input to comparator C₂. Comparator C₂ compares load current instruction value I L * with detected value I L , and supplies its deviation ε L = I L * - I L to the next current control/compensation circuit G L (S). Circuit G L (S) amplifies deviation ε L , and supplies V₂* = G L (S)·ε L to PWM controller PWM₂ of the second inverter. Second inverter INV-2 generates voltage V L2 proportional to input voltage V₂* of the PWM controller. When I L * > I L , deviation ε L becomes a positive value, and increases input signal V₂* of PWM₂. Thus, control is made so that output voltage V L2 of second inverter INV-2 is increased and load current I L is increased to establish I L ≒ I L *. Contrary to this, when I L * < I L , deviation ε L becomes a negative value, and decreases output voltage V L2 of second inverter INV-2 and load current I L . In this case, control is balanced when I L ≒ I L *. When load current instruction value I L * is sinusoidally changed, actual load current I L is sinusoidally controlled to follow the change. When output frequency f₀ is zero, load current control can be performed without any problem. The control operation of first PWM inverter INV-1 will be described below. First PWM inverter INV-1 generates voltage V L1 almost proportional to output frequency f₀ through output transformer TR. Inverter INV-1 is basically not related to load current control. First PWM inverter INV-1 controls exciting current I₀₁ of output transformer TR. Voltage V L applied to load LOAD is expressed by: p: differential operator When load current I L is sinusoidally controlled as follow: I L = I Lm ·sinω₀t I Lm : current peak value ω₀ = 2πf₀ equation (2) is rewritten as: V L = V C + R L ·I L + jω₀L L ·I L and, coincides with equation (1). First PWM converter INV-1 generates a component proportional to output frequency f₀ in equation (4), and given by: V L1 = V C + jω₀L L I L where V C is the counter electromotive force of an AC motor, and is proportional to a rotational speed of the motor, i.e., output frequency f₀ of the inverter. In order to cause first PWM inverter INV-1 to generate voltage V L1 given by equation (5), an instruction value given by the following equation is input to PWM controller PWM₁ through adder AD: V L1 * = V C * + jω₀·L L ·I L * When the ratio of the numbers of turns of the primary winding to secondary winding of output transformer TR is 1 : 1, output voltage V₁ of first PWM inverter INV-1 is directly output from output transformer TR as V L1 in a normal operation mode, and becomes a voltage complementary to a sum of counter electromotive force V C of the motor and voltage drop jω₀L L I L by inductance L L . As a result, second PWM inverter INV-2 need only generate output voltage V L2 corresponding to voltage drop I L ·R L caused by resistance R L , and load current I L can also be easily controlled. However, when output transformer TR suffers from DC polarized magnetization, an iron core may be saturated, and an exciting current of transformer TR may become too high. In order to prevent this, the first PWM inverter controls exciting current I₀₁. The control operation of the exciting current will be described below. Primary current I₁ and secondary current (load current) I L are respectively detected by current detectors CT₁ and CT L , and a difference between the two currents is calculated to obtain exciting current I₀₁ of the transformer. That is, I₀₁ = I₁ - I L In this case, the ratio of the numbers of turns of the primary and secondary windings of transformer TR is assumed to be 1. On the other hand, exciting current instruction value I₀₁* is obtained by the following calculation by calculation circuit CAL using the above-mentioned output voltage instruction value V L1 *. where M is the exciting inductance of the transformer. In a synchronous motor load, when load current I L is sinusoidally controlled to be in phase with counter electromotive force V C , V C * and I L * are respectively given by: V C * = V Cm *·sinω₀t I L * = I L M*·sinω₀t V Cm *: voltage peak instruction value I Lm *: current peak instruction value Thus, exciting current instruction value I01* given by equation (8) is expressed by: Fig. 3 is a vector chart of these values. More specifically, vector V L1 * of the secondary voltage of output transformer TR is equal to a sum of counter electromotive force vector V C * and vector jω₀L L I L * of a voltage drop caused by inductance L L of the load, and, hence, exciting current I₀₁* is necessary for generating secondary voltage V L1 *. Comparator C₁ compares exciting current instruction value I₀₁* with detection value I, , and deviation ε₀₁ = I₀₁* - I₀₁ therebetween is amplified by the next current control/compensation circuit G₀(S). The output signal of G₀(S) is added to output voltage instruction value V L1 * by adder AD, and V₁* = V L1 * + G₀(S)·ε₀₁ is input to PWM controller PWM₁ of first PWM inverter INV-1. When I₀₁* > I₀₁, deviation ε₀₁ becomes a positive value, and is amplified by G₀(S), thus increasing input signal V₁* of PWM₁. Therefore, output voltage V₁ of the first inverter is increased, and exciting voltage of the transformer is increased. In this case, although secondary voltage V L1 of output transformer TR is also slightly increased, output voltage V L2 of second inverter INV-2 which performs load current control is decreased by a value corresponding to an increase in V L1 , and voltage V L = V L1 + V L2 to be applied to load LOAD is left unchanged. Therefore, control is balanced to yield I₀₁ ≒ I₀₁*. In contrast to this, when I₀₁* < I₀₁, deviation ε01 becomes a negative value, and decreases output voltage V₁ of first inverter INV-1 and exciting current I₀₁ of transformer TR. Thus, control is balanced when I₀₁ ≒ I₀₁*. In this case, load current I L is also controlled by second inverter INV-2 to satisfy I L ≒ I L *. When exciting current instruction value I₀₁* is sinusoidally changed, as expressed by equation (11), actual exciting current I₀₁ is sinusoidally controlled to follow it. In equation (11), since peak value V Cm * of the counter electromotive force is proportional to output frequency ω₀, when peak value I Lm * of the load current is constant, the peak value of exciting current I₀₁* becomes constant regardless of output frequency f₀. In the vector chart of Fig. 3, when load current instruction value I L * is increased, inductance drop jω₀L L I L * of the load is increased accordingly, and secondary voltage V L1 * of output transformer TR is also increased. As a result, the magnitude of exciting current vector I₀₁* is also increased. Fig. 4 shows the relationship between output frequency f₀ and the magnitude of load terminal voltage V L . First PWM inverter INV-1 bears component V C + jω₀L L I L proportional to output frequency f₀, and second PWM inverter INV-2 bears voltage drop I L ·R L by the resistance. Fig. 5 shows the relationship between secondary voltage V L1 of output transformer TR of first PWM inverter INV-1 and output frequency f₀. When exciting current I₀₁ of the transformer is assumed to be constant, the magnitude of secondary voltage V L1 is proportional to output frequency f₀. When excitation current I₀₁ is decreased like I'₀₁, the magnitude of V L1 is also decreased as indicated by a broken line. A case will be considered below wherein a DC component is superposed on load current I L due to, e.g., drift of current detector CT L in the converter shown in Fig. 1, and output transformer TR suffers from DC polarized magnetization. Due to the DC polarized magnetization, the iron core of transformer TR is saturated to one side. For this reason, mutual inductance M of transformer TR is decreased, and causes exciting current I₀₁ to increase. However, in the converter of the present invention, since first PWM inverter INV-1 controls exciting current I₀₁ of transformer TR to coincide with instruction value I₀₁*, output voltage V₁ of first inverter INV-1 is automatically decreased, and an increase in exciting current I₀₁ is prevented. As a result, primary current I₁ of transformer TR, i.e., the output current of inverter INV-1 is no longer increased. As a result, elements can be prevented from being destroyed by an overcurrent caused by polarized magnetization as a conventional problem. Fig. 6 is a circuit diagram showing another embodiment of a power converter according to the present invention. A difference from the converter shown in Fig. 1 will be described below. More specifically, two stages of inverters INV-11 and INV-12 having output transformers are stacked and multiplexed, and direct-connection inverter (having no output transformer) INV-2a bridge-connects three phases. Neutral point N of a load is connected to an intermediate tap of DC voltage V d . In this manner, the number of multiplexed stages of inverters having output transformers can be increased to increase an output capacity of the power converter. Since neutral point N of the load is connected to the intermediate tap of DC voltage V d , an electrical power can be supplied to a three-phase, four-line type load. In the converter shown in Fig. 7, load current I L can be controlled by direct-connection inverter INV-2, and exciting currents of corresponding output transformers TR U1 and TR U2 can be respectively controlled by inverters INV-11 and INV-12 with the output transformers. Thus, the same effect as in the converter shown in Fig. 1 can be provided. According to the power converter of the present invention, even when DC polarized magnetization occurs in an output transformer, the primary current (output current of the first PWM inverter) of the transformer is prevented from being increased, and elements can be prevented from being destroyed by an overcurrent. Fig. 7 is a circuit diagram showing still another embodiment of a power converter according to the present invention, and Fig. 8 is a circuit diagram showing an embodiment of a controller of the converter shown in Fig. 7. In Fig. 7, reference symbol V d denotes a DC voltage source; INV-1 to INV-4, multiplexed PWM inverters; INV-5, a direct-connection PWM inverter; TR₁ to TR₄, output transformers; and LOAD, an AC load (U phase). Fig. 7 illustrates a circuit corresponding to only one output phase of the converter. However, circuits corresponding to V and W phases have the same arrangements. In Fig. 8, reference numerals A₁ to A₆ denote adders; C₁ to C₅, comparators; G₁ to G₄ and G L , current control/compensation circuits; K N , an operational amplifier; PWM₁ to PWM₅, PWM controllers; and TRG, a carrier (triangular wave) generator. Note that CT₁ to CT₅ in Fig. 7 designate current detectors. Fig. 9 shows a detailed arrangement of PWM inverter INV-1 shown in Fig. 7. Inverter INV-1 comprises self-extinction elements S₁₁ to S₁₄ and free-wheeling diodes D₁₁ to D₁₄. Figs. 10A to 10D are timing charts for explaining the PWM control operation of the inverters shown in Fig. 9. Reference numerals X₁ and Y₁ denote PWM control carrier signals. Y₁ has an inverted value (or a signal having a phase difference of 180°) of X₁. Control input signals e₁ and X₁ are compared to generate gate signal g₁ for elements S₁₁ and S₁₂ of inverter INV-1. When e₁ ≧ X₁, g₁ = 1, and S₁₁: ON, S₁₂: OFF When e₁ < X₁, g₁ = 0, and S₁₁: OFF, S₁₂: ON Control input signals e₁ and Y₁ are compared to generate gate signal g₁' for elements S₁₃ and S₁₄. When e₁ ≧ Y₁, g₁' = 1, and S₁₃: OFF, S₁₄: ON When e₁ < Y₁, g₁' = 0, and S₁₃: ON, S₁₄: OFF When the ratio of the numbers of turns of primary to secondary windings is assumed to be 1, output voltage V₁ of inverter INV-1 is given by: V₁ = +V d when S₁₁ and S₁₄ are ON V₁ = -V d when S₁₂ and S₁₃ are ON V₁ = 0 in other modes Thus, a waveform shown in Fig. 10D is obtained. Average value V 1 (indicated by a broken curve) is proportional to control input signal e₁. In this manner, output voltage V₁ of inverter INV-1 is controlled by a frequency twice the PWM control carrier frequency. The three remaining PWM inverters INV-2 to INV-4 are similarly controlled. In this case, carrier signals X₂ to X₄ have a phase difference of 45° (electrical angle) from each other (Y₂ to Y₄ are inverted values of X₂ to X₄, respectively). As a result, a sum V₁ + V₂ + V₃ + V₄ of voltages generated through output transformers TR₁ to TR₄ becomes a multiplexed voltage, and has a voltage waveform controlled by 8·f C with respect to PWM control carrier frequency f C . A lower-order harmonic component upon PWM control is canceled, and only a higher-order harmonic component appears in output voltage V₁ + V₂ + V₃ + V₄. This higher-order harmonic component can be easily canceled by a filter, e.g., a reactor. Direct-connection inverter INV-5 has an arrangement as shown in Fig. 11. Fig. 11 shows a circuit corresponding to a U phase of a three-phase Graetz connection, which comprises self-extinction elements S₅₁ and S₅₂ and free-wheeling diodes D₅₁ and D₅₂. A neutral line of a load is connected to an intermediate line of DC voltage V d . Figs. 12A and 12B are timing charts for explaining the PWM control operation of inverter INV-5. Carrier signal X₅ and control input signal e₅ are compared to generate gate signal g₅ for elements S₅₁ and S₅₂. When e₅ ≧ X₅, g₅ = 1, and S₅₁: ON, S₅₂: OFF When e₅ < X₅, g₅ = -1, and S₅₁: OFF, S₅₂: ON Output voltage V₅ of inverter INV-5 is given by: V₅ = +(V d /2) when S₅₁ is ON V₅ = -(V d /2) when S₅₂ is ON Average value V 5 is proportional to control input signal e₅. In this manner, output voltage V₅ of direct-connection inverter INV-5 is controlled by the PWM control carrier frequency. The control operation of the converter of the present invention will be described below with reference to Figs. 7 to 12. Load current I U is controlled by direct-connection inverter INV-5. More specifically, load current I U is detected by current detector CT₅, and the detected current is input to comparator C₅. Comparator C₅ compares load current instruction value I U * with detected value I U to obtain deviation ε U = I U * - I U . Deviation ε U is amplified by the next current control/compensation circuit G L , and the amplified deviation is supplied, as input signal e₅, to PWM controller PWM₅ of direct-connection inverter INV-5 through adder A6. Direct-connection inverter INV-5 generates voltage V ₅ proportional to input signal e₅, as described above. When I U * > I U , deviation ε U has a positive value, and increases output voltage V₅ of direct-connection inverter INV-5, thus increasing load current I U so to establish I U = I U *. In contrast to this, when I U * < I U , deviation ε U has a negative value, and decreases output voltage V₅, thus decreasing load current I U . Thus, the load current is balanced when I U = I U *. When current instruction value I U * is sinusoidally changed, actual current I U is sinusoidally controlled to follow the change. Direct-connection inverter INV-5 basically generates voltage R L ·I U corresponding to a voltage drop caused by resistance R L of the load. Thus, added A₆ receives a signal obtained by multiplying load resistance R L with current instruction value I U *. Input signal e₅ to PWM₅ is given by: e5 = R L ·I U * + ε U ·G L More specifically, direct-connection inverter INV-5 always generates a voltage corresponding to a voltage drop caused by the load resistance, and additionally generates a voltage according to current deviation ε U to control the load current. Since a voltage drop caused by the resistance dies not depend on output frequency f₀, when f₀ = 0, multiplexed inverters INV-1 to INV-4 having output transformers cannot generate a voltage, and a voltage must be supplied from the direct-connection inverter. Multiplexed PWM inverters INV-1 to INV-4 generate voltages proportional to output frequency f₀. More specifically, for a motor load, these inverters supply a voltage corresponding to a sum of a voltage of counter electromotive force V CU and voltage drop jωL L ·I U caused by inductance L L of the load. In Fig. 8, compensation signal V CU * + jωL L ·I U * obtained by counter electromotive force compensation value V CU * and load current instruction value I U * is input to operational amplifier K N and adder A₂ to supply input signal e₁ to PWM controller PWM₁ of inverter INV-1. Similarly, input signals e2 to e4 are input to controllers PWM₂ to PWM₄. For the sake of simplicity, if other signals are assumed to be zero, where n is the number of stages of inverters constituting a multiplexed inverter, and n = 4 in this case. As a result, output voltage V₁ + V₂ + V₃ + V₄ of the multiplexed inverter is proportional to the sum of input signals e₁ to e₄, and a voltage proportional to V CU * + jωL L I U * is generated. Counter electromotive force V CU * is proportional to output frequency f₀, and second term jωL L I U * is also proportional to output frequency f₀ second term jωL L I U *. Therefore, output voltage V₁ + V₂ + V₃ + V₄ of the multiplexed inverter is proportional to output frequency f₀, and effective values of exciting currents IOU₁ to IOU₄ of output transformers TR₁ to TR₄ become almost constant. In practice, however, a DC bias or the like may be slightly applied to the output transformers due to drift of the controller or unbalanced switching characteristics of elements. When a DC bias voltage is applied to a transformer, the transformer gradually undergoes polarized magnetization, and finally, its iron core is saturated, so that an excessive exciting current flows through the transformer. As a result, not only the transformer is burnt, but also elements constituting the inverter are destroyed by an overcurrent. In the converter of the present invention, four inverters INV-1 to INV-4 constituting the multiplexed PWM inverter respectively control primary currents I U1 to I U4 of their output transformers. The control operation of primary current I U1 of inverter INV-1 will be described below. Current detector CT₁ detects primary current I U1 of transformer TR₁, and the detected current is input to comparator C₁. Comparator C₁ compares primary current instruction value I U1 * with current detection value I U1 to obtain deviation ε₁ = I U1 * - I U1 . Deviation ε₁ is amplified by the next current control/compensation circuit G₁, and is then input to adder A₂ to supply input signal e₁ of PWM controller PWM₁. Thus, e₁ given by equation (12B) is rewritten as: e₁ = (V CU * + jωL L ·I U *)/4 + ε₁·G₁ Primary current instruction value I U1 * is given by the sum of load current instruction value I U * and instruction value I OU1 * of exciting current I OU1 of transformer TR₁. If the four transformers have the same capacity and rated value, I OU1 * = I OU2 * = I OU3 * = I OU4 *. Therefore, When I U1 * > I U1 , deviation ε₁ has a positive value, and increases input signal e₁ given by equation (13), thus increasing primary current I U1 to establish I U1 = I U1 *. In this case, load current I U is controlled by direct-connection inverter INV-5 to I U ≒ I U *. As a result, exciting current I OU1 of transformer TR₁ is controlled to coincide with instruction value I OU * described above. In contrast to this, when I U1 * < I U1 , deviation ε₁ has a negative value, and decreases input signal e₁, i.e., the output voltage of inverter INV-1 to satisfy I U1 ≒ I U1 *. In this manner, primary current I U1 of transformer TR₁ is controlled to coincide with instruction value I U1 *, and exciting current I OU1 of transformer TR₁ consequently coincides with instruction value I OU *. Even when a DC bias is applied to transformer TR₁ due to, e.g., unbalanced characteristics of elements, exciting current I OU1 ≒ I OU * is established, and the control system is operated to finally cancel the DC bias. Other inverters INV-2a to INV-4 are similarly controlled. As described above, the multiplexed PWM inverter must basically generate a sum voltage of counter electromotive force V CU and voltage drop jωL L I U caused by inductance L L of the load. Therefore, exciting currents I OU1 to I OU4 of transformers TR₁ to TR₄ must be adjusted to corresponding values. When a mutual inductance upon a rated output of each transformer is represented by M, instruction value I OU * of the exciting current input to adder A₁ is given by: In this manner, the multiplexed PWM inverter generates a voltage corresponding to counter electromotive force V CU and voltage drop jωL L I U caused by the inductance of the load, and the direct-connection inverter generates a voltage corresponding to a voltage drop caused by the resistance of the load and a transient voltage necessary for load current control, thereby controlling load current I U to coincide with its instruction value I U *. In this case, even when a DC bias voltage is applied to the output transformer due to unbalanced characteristics of elements, since primary current control (in other words, exciting current control) of the transformer is executed, no DC polarized magnetization occurs. Thus, no overcurrent caused by polarized magnetization flows through the transformer, and elements constituting the inverter can be prevented from being destroyed. However, the power converter shown in Fig. 7 poses the following problems. That is, output voltage V₁ + V₂ + V₃ + V₄ generated by the multiplexed PWM inverter can be a sinusoidal voltage free from distortion. However, since the direct-connection inverter cannot execute multiplexed PWM control, the waveform distortion of its output voltage V₅ is increased. In particular, in a region of low output frequencies f₀, a current to be supplied to AC load LOAD includes many pulsation components, and causes torque pulsation for a motor load. If the carrier frequency of direct-connection inverter INV-5 can be increased up to about 8 times those of multiplexed inverters INV-1 to INV-4, the above-mentioned voltage distortion can be decreased, and a balanced power converter as a whole can be realized. However, the switching frequency of a GTO (gate turn-off thyristor) as a typical self-extinction element is at most about 500 Hz, and it is impossible to increase only the carrier frequency of direct-connection inverter INV-5. As the power converter has higher-voltage, larger-capacity specifications, elements constituting an inverter must be serially connected. In order to reduce a switching loss and snubber circuit loss, a carrier frequency is preferably reduced as much as possible during an operation. Thus, the present invention also provides a power converter which can always supply a sinusoidal current free from distortion to an AC load regardless of an output frequency level without increasing a carrier frequency of a direct-connection inverter, and a method of controlling the same. Fig. 13 is a circuit diagram showing another embodiment of a controller of the converter according to the present invention. In Fig. 13, reference numerals SW₁ and SW₂ denote switch circuits; C₁ to C₆, comparators; A₁ to A₈, adders; SH, a Schmitt circuit; G₁ to G₄ and G L , current control/compensation circuits; K N1 , K N2 , and K N , operational amplifiers; PWM₁ to PWM₅, PWM controllers; and TRG₁ and TRG₂, carrier generators. A difference between the embodiment shown in Fig. 13 and the controller shown in Fig. 8 is as follows. In the controller shown in Fig. 8, four PWM inverters INV-1 to INV-4 constituting the multiplexed inverter control primary currents I U1 to I U4 of their output transformers. In this embodiment, these inverters control exciting currents I OU1 to I OU4 of the transformers. If the four transformers are assumed to have the same capacity and rated value, instruction value IOU* of its exciting current is given by equation (15). Exciting currents I OU1 to I OU4 of the transformers can be obtained by calculations from the detection values of primary currents I U1 to I U4 of the transformers, and the detection value of load current I U as follows: Comparator C₁ compares exciting current detection value I OU1 and its instruction value I OU *, and control/compensation circuit G₁ amplifies deviation ε₁ = IOU* - I OU1 . Inverter INV-1 is controlled under PWM control to satisfy I OU1 ≒ I OU *. Exciting currents I OU2 to I OU4 of other transformers are also controlled to coincide with instruction value I OU *. As a result, polarized magnetization of the output transformer can be eliminated, and element destruction can be prevented as in the controller shown in Fig. 8. The next difference is as follows. That is, when output frequency f₀ of the inverter is lower than minimum frequency f min (e.g., f min = 1 Hz is selected as a minimum frequency at which the output transformer can be operated), a fundamental wave (output frequency component) voltage generated from the multiplexed PWM inverter is controlled to be zero. More specifically, comparator C₆ compares output frequency f₀ and setup value f min of the minimum frequency, and the Schmitt circuit switches the contacts of switch circuits SW₁ and SW₂. When f₀ < f min , circuits SW₁ and SW₂ are connected to contacts a . Thus, exciting current instruction value I OU * of the transformer becomes zero, and a voltage of the fundamental wave generated from the multiplexed PWM inverter also becomes zero. When f₀ > f min , switch circuits SW₁ and SW₂ are switched to contacts b , and the multiplexed PWM inverter generates counter electromotive force V CU of the load and voltage drop jωL L I U caused by the inductance. Meanwhile, when f₀ < f min , direct-connection PWM inverter INV-5 bears a total of counter electromotive force V CU of the load, voltage drop jωL L I U caused by the inductance, and voltage drop R L ·I U caused by the resistance, and controls load current I U . In this manner, in a region of f₀ < f min , output transformers TR₁ to TR₄ are controlled not to flow wasteful exciting currents. In the embodiment shown in Fig. 13, compensation control is executed so that a harmonic voltage generated by direct-connection inverter INV-5 is canceled by multiplexed inverters INV-1 to INV-4. More specifically, pulsation component ΔV₅ of voltage V₅ generated from inverter INV-5 is predicted from PWM control input signal e₅ of direct-connection inverter INV-5 and output signal g₅ of PWM controller PWM₅, and multiplexed PWM inverters INV-1 to INV-4 are caused to generate its inverted value -ΔV₅. As has been described with reference to Figs. 12A and 12B for explaining the PWM control operation of the direct-connection inverter, carrier signal X₅ and control input signal e₅ are compared to generate gate signal g₅. Output voltage V₅ is determined as follows. When e₅ ≧ X₅, g₅ = 1, and S₅₁: ON, S₅₂: OFF When e₅ < X₅, g₅ = -1, and S₅₁: OFF, S₅₂: ON Output voltage V₅ is separated into fundamental wave component V ₅ and harmonic component ΔV₅. More specifically, ΔV₅ = V₅ - V ₅. This can be converted to the level of PWM control input signal e₅ as follows. Peak values of carrier signals X₁ to X₅ are represented by E max , and gate signal g₅ is multiplied with E max by operational amplifier K H . Output g₅·E max of amplifier K H is a voltage proportional to output voltage V₅, and input signal e₅ proportional to V₅ is subtracted from the output: Δe₅ = g₅·E max - e₅∝ΔV₅ The output from adder A₇ corresponds to an inverted value of a value given by equation (17), and is multiplied with (1/2n) by operational amplifier K N2 to obtain compensation control signal H OU *. H OU * = -(g₅·E max - e₅)/(2n) where n is the number of series-connected multiplexed inverters, and n = 4 in this case. Compensation signal H OU * is input to controllers PWM₁ to PWM₄ through adder A₅ and adders A₁ to A₄. In the following description, other signals are assumed to be zero for the sake of simplicity. Figs. 14A to 14N are timing charts for explaining the operation of the multiplexed PWM inverter when e₁ = e₂ = e₃ = e₄ = H OU *. Reference numerals X₁ to X₄ and Y₁ to Y₄ denote PWM control carrier signals. Signals Y₁ to Y₄ are inverted signals of signals X₁ to X₄. Signals X₁, X₂, X₃, and X₄ have a phase difference of 45° from each other. The principal circuit arrangement of inverter INV-1 is as shown in Fig. 9 described above. Input control signal H OU * is compared with carrier (triangular wave) X₁ to generate gate signal g₁, thereby firing-control elements S₁₁ and S₁₂ of inverter INV-1. That is, When H OU * ≧ X₁, g₁ = "1", and S₁₁: ON, S₁₂: OFF When H OU * < X₁, g₁ = "0", and S₁₁: OFF, S₁₂: ON H OU * and Y₁ are compared with each other to generate gate signal g₁', thereby firing-control elements S₁₃ and S₁₄. That is, When H OU * ≧ Y₁, g₁' = "1", and S₁₃: OFF, S₁₄: ON When H OU * < Y₁, g₁' = "0", and S₁₃: ON, S₁₄: OFF As a result, output voltage V₁ of inverter INV-1 becomes V₁ = +V d when elements S₁₁ and S₁₄ are ON; V₁ = -V d when S₁₂ and S₁₃ are ON; and V₁ = 0 in other modes. Thus, output signal V₁ has a waveform, as shown in Fig. 14D. Similarly, input control signal H OU * is compared with triangular waves X₂ and Y₂ to generate gate signals g₂ and g₂' for inverter INV-2. H OU * is compared with X₃ and Y₃ to generate gate signals g₃ and g₃' for inverter INV-3. H OU * is compared with X₄ and Y₄ to generate gate signals g₄ and g₄' for inverter INV-4. As a result, output voltages V₂, V₃, and V₄ of inverters INV-2 to INV-4 are as shown in Figs. 14G, 14J, and 14M. A sum of output voltages V₁ to V₄ of inverters INV-1 to INV-4 has a waveform as shown in Fig. 14N, and is proportional to input signal H OU *. Sum voltage V₁ + V₂ + V₃ + V₄ = -ΔV₅ cancels harmonic component ΔV₅ of voltage V₅ generated by direct-connection inverter INV-5. When compensation control signal H OU * expressed by equation (18) is input as PWM control input signal e₁ = e₂ = e₃ = e₄ = H OU * of inverters INV-1 to INV-4, average values of output voltages V₁ to V₄ of the inverters are proportional to corresponding input signals e₁ to e₄, and their sum voltage V₁ + V₂ + V₃ + V₄ is proportional to 4·H OU *. V₁ + V₂ + V₃ + V₄ = V d E max ·4·H OU * When equations (17) and (18) are substituted in equation (19) for n = 4, equation (19) is rewritten as: In this manner, harmonic voltage V₅ generated by direct-connection inverter INV-5 can be compensation-controlled to be canceled by multiplexed inverters INV-1 to INV-4. As a result, the carrier frequency of the direct-connection inverter can be lowered, and a switching loss and a snubber circuit loss can be reduced. Figs. 15A to 15C show computer simulation results of the converter of the present invention, and illustrate three-phase output currents I U , I V , and I W , U-phase output voltage V U , counter electromotive force V CU , output voltage V₁ of one multiplexed PWM inverter, and output voltage V₄ of the direct-connection inverter when an output frequency is 30 Hz. Note that the load comprises an AC motor, the multiplexed inverter has a three-stage structure, the PWM control carrier frequency of the multiplexed inverter is 350 Hz, and the PWM control carrier frequency of the direct-connection inverter is 120 Hz. Although the carrier frequency of the direct-connection inverter is lowered, load currents I U , I V , and I W of its component are free from pulsation, and are controlled to be sinusoidal currents free from distortion. In this manner, load current I U is controlled according to its instruction value I U *. In this case, one problem is posed. More specifically, when PWM control carrier frequency f CA of the multiplexed inverter is set to be the same as PWM control carrier frequency f CB of the direct-connection inverter, voltages generated by inverters constituting the multiplexed inverter are deviated to the positive or negative side when a harmonic voltage component generated by the direct-connection inverter is to be compensated for. Figs. 16A to 16H are timing charts when compensation voltage H OU * as a PWM control input signal is perfectly synchronous with carrier signals X₁ to X₄ and Y₁ to Y₄ of the multiplexed inverter. Since compensation voltage H OU * is synchronous with carrier signal X5 of the direct-connection inverter, the above-mentioned state occurs when carrier signals X₁ to X₄ or Y₁ to Y₄ have the same frequency and PWM control input signal e₅ of direct-connection inverter INV-5 is constant. H OU * and X₁ are compared with each other to generate gate signal g₁, and H OU * and Y₁ are compared with each other to generate gate signal g₁', as described above. As a result, output voltage V₁ of inverter INV-1 becomes as shown in Fig. 16D. Similarly, output voltages V₂ to V₄ of inverters INV-2 to INV-4 become as shown in Figs. 16E to 16G, and output voltage V₁ + V₂ + V₃ + V₄ of the multiplexed inverter has a waveform shown in Fig. 16H. This voltage is proportional to compensation voltage H OU *, and corresponds to an inverted value of harmonic component V₅ of output voltage V₅ of direct-connection inverter INV-5. In this case, in output voltages V₁ to V₄ of the inverters constituting the multiplexed inverter, integrated values of positive voltage components do not coincide with those of negative voltage components. For example, in output voltage V₁, negative voltage components are larger than positive voltage components. The same applies to V₂. Contrary to this, in V₃ and V₄' positive voltage components are larger than negative voltage components. In the multiplexed inverter as a whole, V₁ + V₂ + V₃ + V₄ is balanced between the positive and negative sides. When carrier signals X₁ to X₄ (Y₁ to Y₄) are synchronous with compensation voltage H OU *, this state permanently continues. For example, this is equivalent to a state that a negative DC bias voltage is applied to output transformer TR1, and DC polarized magnetization occurs in the iron core. The same applies to other output transformers TR₂ to TR₄. DC polarized magnetization is finally corrected since inverters INV-1 to INV-4 control primary or exciting currents of their transformers, as described above. However, it is not preferable to create a cause of DC polarized magnetization, and this may disturb current control. When the DC polarized magnetization is corrected, a compensation control operation of a harmonic voltage component of the direct-connection inverter is disturbed, and proper compensation may become impossible. In the controller shown in Fig. 13, therefore, carrier generators TRG₁ and TRG₂ respectively generate carrier signals X₁ to X₄ (Y₁ to Y₄) to be supplied to PWM controllers PWM₁ to PWM4 of the multiplexed inverter, and carrier signal X5 to be supplied to PWM controller PWM5 of the direct-connection inverter so as to have different frequencies f CA and f CB . In this manner, for example, voltage V₁ generated by one multiplexed inverter INV-1 may instantaneously have a large positive or negative voltage level. However, in terms of an average value, voltage V₁ is proportional to input signal H OU * (assuming that e₁ = H OU *), and will never cause DC polarized magnetization of output transformer TR₁. The same applies to other output transformers TR₂ to TR₄. As a result, primary current control (or excitation current control) of the output transformers by the corresponding inverters will not be disturbed, and a current free from waveform distortion can be supplied. A harmonic voltage component generated by the direct-connection inverter can be accurately compensated for by the multiplexed inverter. The inverter output corresponding to one phase (U phase) has been described above. However, the same applies to V and W phases. Compensation signal H OU * for canceling harmonic voltage component ΔV₅ generated by direct-connection inverter INV-5 is directly obtained from gate signal g₅ and PWM control input signal e₅, thereby canceling all the harmonic components. Alternatively, signal g₅ may be frequency-analyzed to extract and compensate for a specific harmonic component therefrom. As described above, according to the power converter of the present invention, DC polarized magnetization of the output transformers of the multiplexed PWM inverter can be prevented, and elements constituting the inverter can be prevented from being destroyed by an overcurrent. At the same time, the load current can be accurately controlled by the direct-connection inverter, and a sinusoidal current free from a waveform distortion can be supplied to an AC load.

Claims: A power converter for supplying an AC load with a sum of an output voltage (V₁) of a first PWM inverter (INV-1) including an output transformer (TR1), and an output voltage (V₅) from a second PWM inverter (INV-5) having no output transformer, wherein said second PWM inverter (INV-5) comprises first means (C5, G5) for controlling a current (I L ) to be supplied to said AC load, characterized in that said first PWM inverter (INV-1) comprises second means (C1, G1) for controlling a primary or exciting current (I U1 ) of the output transformer (TR1) connected thereto, said second means (C1, G1) having a controlling effect for preventing the polarised magnetisation of the output transformer (TR1) caused by the DC component of the output voltage (V₁). A power converter according to claim 1, characterized in that said first PWM inverter (INV-1) having the output transformer (TR) comprises means (CAL, C1, G0(5), AD) for performing compensation control to generate, for said AC load, a voltage (VL1) corresponding to a counter electromotive force (VC) of said AC load and a voltage drop (jω0L L ·I L ) caused by an inductance (L L ) of said AC load. A power converter according to claim 1 or 2, characterized in that said second PWM inverter (INV-2) having no output transformer comprises means (C2, GL(S)) for performing compensation control to generate a voltage (VL2) corresponding to a voltage drop (I L ·R L ) caused by a resistance (R L ) of said AC load. A power converter according to claim 1, characterized in that said first PWM inverter (INV-1) having the output transformer (TR) comprises means (C1, G1) for performing control so that an exciting current (I OU1 ) of the output transformer (TR1) becomes zero when an output frequency of said inverter is not more than a certain minimum frequency (f min ). A power converter according to claim 2, characterized in that said first PWM inverter (INV-1) having the output transformer (TR1) sets a counter electromotive force compensation value (V CU *) of said AC load and a voltage drop compensation value (jωL L I N *)of the inductance (L L ) to be zero when an output frequency of said inverter (INV-1) is not more than a certain minimum frequency (f min ). A power converter according to claim 1, characterized in that said first PWM inverter (INV-1) having the output transformer (TR1) comprises means (A5, A7, KN1, KN2) for performing compensation control to cancel a harmonic component of an output voltage (V5) generated by said second PWM inverter (INV-5) having no output transformer. A method of controlling a power converter having a first PWM inverter (INV-1) with an output transformer (TR1) and a second PWM inverter (INV-5) without an output transformer, comprising steps of: supplying a sum of an output voltage of said transformer (TR1) of the first PWM inverter (INV-1) and an output from the second PWM inverter (INV-5) to an AC load; and controlling (a) a primary or exciting current of the output tansforme (TR1) of said first PWM inverter (INV-1) for preventing the polarised magnetisation of the output transformer (TR1) caused by the DC component of the output voltage (V₁), and (b) a current to be supplied to said AC load, so that said first PWM inverter (INV-1) cancels a harmonic component of an output voltage generated by said second PWM inverter (INV-5). A method according to claim 7, characterized in that PWM control is performed so that a carrier frequency of said first PWM control inverter having the output transformer is different from a carrier frequency of said second PWM converter having no output transformer. A power converter comprising: at least one first PWM inverter (INV-1) operated with a first carrier frequency, said first PWM inverter having an output transformer (TR1) which couples the first PWM inverter to an AC load; a second PWM inverter (INV-5) operated with a second carrier frequency; means comprising transformers (TR1-TR4) and pulse-width-modulation controllers (PWM1-PWM5) for supplying said AC load with a sum of a first voltage from the output transformer (TR1) of said first PWM inverter (INV-1) and a second voltage (V5) from said second PWM inverter (INV-5); and means comprising adders (A5, A7) and operational amplifiers (KN1, KN2) for reducing or cancelling out higher harmonic components contained in the second voltage (V5) from said second PWM inverter (INV-5), using an operation of said first PWM inverter (INV-1). A power converter according to claim 9, further comprising: means (TRG1, TRG2) for differing said first carrier frequency from said second carrier frequency.

Inventors: TANAKA, SHIGERU, TANAKA, SHIGERU, C/O INTELLECTUAL PROPERTY DIV.
Applicants: KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H02M7
IPC codes: H02M7, H02P27