Maximum swing cascode circuit for a bipolar charge pump

Abstract: A maximum swing bipolar charge pump retains a cascode switching configuration for high breakdown. The charge pump includes a charge pump capacitor with a first plate connected to supply in the conventional manner. A first cascode-connected NPN transistor is utilized to switch the second plate of the pump capacitor to the supply. A second cascode-connected NPN transistor is utilized to switch the second plate of the pump capacitor close to ground. An additional bipolar biasing network holds the second NPN transistor out of heavy saturation when the second plate of the pump capacitor is switched close to ground, thereby preserving fast turn-off time and maximum voltage swing with the constraint of a bipolar cascode configuration.

Description: The present invention relates generally to electronic circuits and, in particular, to a bipolar charge pump switching circuit that transfers the maximum possible charge to the charge pump capacitor while retaining a cascode configuration for high breakdown. Electronic systems often include circuits that require an operating voltage higher than the available supply. For example, some circuits in an automotive system require an input voltage that is higher than the 12 volts available from a standard automobile battery. In these applications, a dedicated circuit is needed to "pump" the supply to the desired voltage level. A simple schematic of a conventional charge pump circuit 10 is shown in Fig. 1. The circuit 10 consists, essentially, of a charge pump capacitor 12 that has one of its plates connected to the supply V+, shown as 12V in Fig. 1, and its other plate connectable to either ground or to the supply by switch 14. Initially, the switch 14 is in Position 1 which connects the bottom plate of the capacitor 12 to ground, causing the top plate of capacitor 12 to charge to the supply, i.e., 12V in the Fig. 1 example. Actually, the top plate of capacitor 12 may charge to slightly less than supply because of the 1 V BE drop across diode 16. After the top plate of capacitor 12 is fully charged, switch 14 is repositioned to Position 2, connecting the bottom plate of capacitor 12 to the supply. With the bottom plate of capacitor 12 now connected to the supply, the potential of the top plate increases by an additional V+. That is, nearly twice the supply is now available to be drawn upon by load 18 as needed, with diode 16 providing isolation for capacitor 12. Typically, switch 14 is implemented in so-called MOS (metal-oxide-semiconductor) technology which provides crisp on-off switching capability and rail-to-rail voltage swing for charging the pump capacitor 12. One simple and widely implemented CMOS (complimentary-metal-oxide-semiconductor) circuit configuration utilized in realizing switch 14 is the inverter 20 shown in Fig. 2. A square wave input to the gates of n-channel transistor 22 and p-channel transistor 24 causes the transistors 22 and 24 to alternately turn on to provide the switching action described above in conjunction with Fig. 1. The period of the square wave input may be chosen to provide a charging frequency for capacitor 12 sufficient to satisfy the demands of the load 18. However, a major deficiency of these MOS switches is that, in some harsh operating environments, the breakdown voltages of the MOS transistors are insufficient for the transistors to withstand the high voltage transients. For example, in automotive systems, the possibility of inadvertent reverse battery conditions or loose battery cables has caused some automobile manufacturers to specify that integrated circuits utilized in these applications be capable of standing off up to 60V, well above the breakdown voltage of commonly available MOS transistors. Thus, additional protective circuitry is required to shield the MOS switching transistors from the transient voltage levels. Lateral PNP bipolar transistors, as commonly constructed utilizing conventional integrated circuit fabrication processes, are rugged enough to withstand the high transients described above, and when combined with complementary vertical NPN bipolar transistors form a desirable switching technology for charge pumps. While NPN transistors typically cannot stand off sufficiently high voltages individually, it is well known that high breakdown NPN structures can be obtained by stacking the NPN transistors in a so-called cascode configuration. NPN transistors tend to easily saturate, however, causing them to turn off slowly. This is inconsistent with the need for the high switching speeds required to maintain the desired charge level on the pump capacitor, which typically can only be as large as 20-40 pF given present integrated circuit fabrication technology. To realize the high switching speeds, the invention provides to keep the NPN transistors out of saturation, as defined in the claims. EP-A-292 148 discloses a charge pump circuitry in integrated form and including a dual emitter transistor switch having low saturation voltage. The low saturation voltage for the transistor is provided by deriving a base bias voltage from the doubled voltage and a collector voltage from the voltage supply. Current limiting for the transistor is provided by connecting one emitter to the base bias circuitry whereby the second emitter acts as a collector when the transistor saturates, thereby limiting the base drive and causing current limiting. The present invention permits to provide a maximum swing bipolar charge pump with high speed switching that retains a cascode switching configuration for high breakdown. The charge pump includes a charge pump capacitor with a first plate connected to the supply in the conventional manner. Preferably, a first cascode-connected NPN transistor and PNP current mirror is utilized to switch the second plate of the charge pump capacitor to the supply. A second cascode-connected NPN transistor is utilized to switch the second plate of the charge pump capacitor close to ground. An additional biasing network holds the second NPN transistor out of heavy saturation when the second plate of the charge pump capacitor is switched close to ground, thereby preserving a fast turn-off time. Thus, the bipolar charge pump exhibits high switching speeds and the voltage swing available on the pump capacitor is maximized, all within the constraint of the bipolar cascode configuration. The foregoing and additional features and advantages of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of the invention, which should be considered in conjunction with the accompanying drawings. Fig. 1 is a simple schematic diagram illustrating a conventional charge pump circuit. Fig. 2 is a schematic diagram illustrating a CMOS inverter circuit utilizable as a switch in the Fig. 1 charge pump circuit. Fig. 3 is a schematic diagram illustrating a maximum swing cascode bipolar charge pump circuit in accordance with the present invention. Fig. 3 provides a schematic diagram of an embodiment of a maximum swing cascode circuit for a bipolar charge pump in accordance with the present invention. The illustrated circuit can be implemented in integrated form using well known manufacturing processes. As shown in Fig. 3, NPN transistors Q27 and Q31, each of Which has a 4X emitter, are connected to circuit ground via 600 ohm resistors R10 and R11, respectively. The collectors of input transistors Q27 and Q31 are respectively connected to the 4X emitters of cascode NPN transistors Q28 and Q32. The collectors of transistors Q28 and Q32 are connected to a current mirror comprising PNP transistors Q29 and Q30. Base drive for transistors Q28 and Q32 is provided by one of the matched emitters of dual emitter PNP transistor Q24. NPN bias transitors Q25 and Q26 receive their base drive from a 4.8V supply via 10 Kohm resistor R8. A PNP clamping transistor Q33 is connected between the emitter of bias transistor Q26 and the collector of cascode transistor Q32. 20 pF pump capacitor C4 has its bottom side connected between the collectors of transistors Q30 and Q32; the top side of capacitor C4 is connected to isolating diodes D1 and D2 which are connected between the supply and the charge pump output. As shown in Fig. 3, NPN transistors Q27 and Q31 are driven with opposing square waves, creating currents which alternately flow through cascode transistors Q28 and Q32 to current mirror Q29, Q30. The collectors of transistors Q30 and Q32 switch the bottom side of the pump capacitor C4 between a low potential when cascode transistor Q32 is turned on and supply when cascode transistor Q28 and current mirror Q29, Q30 are turned on. The base regions of transistors Q28 and Q32 are biased, via 13 Kohm resistor R4 and 1 Kohm resistor R5 and transistors Q11 and Q24, to as low a voltage as possible while still maintaining sufficient operating voltage for input transistors Q27 and Q31, thus maximizing the voltage swing on pump capacitor C4. If, however, cascode transistor Q32 is allowed to saturate while switching pump capacitor C4 is low, both an undesirable increase in current and a slow turn-off time would result due to the parasitic PNP action associated with the collector-base junction of cascode transistor Q32 turning on. In accordance with the present invention, to hold NPN transistor Q32 just out of heavy saturation, so that pump capacitor C4 can swing to maximum low, an additional biasing network that includes NPN bias transistors Q25 and Q26 and PNP clamping transistor Q33 has been added. Due to the matching between the two emitters of transistor Q24 and between the 3X emitters of transistors Q25 and Q26, a well-defined ΔV BE is present across 1 Kohm resistor R9. clamp transistor Q33 is offset by this ΔV BE voltage above the base of transistor Q32, thus increasing the collector voltage of transistor Q32 by ΔV BE during clamping. Since the base-emitter junction of transistor Q33 and the collector-base junction of transistor Q32 have similar characteristics, the forward bias of the collector of transistor Q32 can be precisely maintained in a "soft saturation" region. Transistors Q24 and Q26 provide low impedances in the desired directions; that is, dual emitter transistor Q24 sinks any leakage current from transistors Q28 or Q32, thus providing high breakdowns, while transistor Q26 sources the required clamping current through transistor Q33 to keep transistor Q32 out of heavy saturation. Until transistor Q32 saturates, it drains low base current, thus not affecting the voltage drop across resistor R9. If the collector/base junction of transistor Q32 begins to go into saturation, negative feedback via resistor R9 holds it out of saturation. Thus, the swing available on pump capacitor C4 has been maximized within the constraint of the bipolar cascode circuitry. It is intended that the following claims define the scope of the invention and that devices within the scope of these claims be covered thereby.

Claims: A bipolar charge pump that generates an output voltage greater than its supply voltage, the charge pump comprising: a) a pump capacitor (C4) having a first plate connected to the supply voltage (V+) via a first diode (D1) and a second plate selectively connectable to the supply voltage or to ground; b) a first NPN cascode transistor (Q28); c) a first NPN input transistor (Q27), the collector of the first input transistor connected to the emitter of the first cascode transistor to form a cascode connection therebetween, the emitter of the first input transistor connected to ground via a first resistive element (R10); d) a second NPN cascode transistor (Q32), the collector of the second cascade transistor connected to the second plate of the pump capacitor; e) a second NPN input transistor (Q31), the collector of the second input transistor connected to the emitter of the second cascode transistor to form a cascode connection therebetween, the emitter of the second input transistor connected to ground via a second resistive element (R11), f) a current mirror comprising first (Q29) and second (Q30) PNP current mirror transistors, the base of the first current mirror transistor connected to the base of the second current mirror transistor, the base of the first current mirror transistor connected to the collector of the first current mirror transistor, the emitter of the first current mirror transistor connected to the supply voltage, the collector of the second current mirror transistor connected to the second plate of the pump capacitor, the emitter of the second current mirror transistor connected to the supply voltage, the base of the first input transistor and the base of the second input transistor being responsive to first and second opposing square waves, respectively, for causing current to alternately flow through the first cascode transistor and the second cascode transistor to the current mirror thereby switching the second plate of the pump capacitor between a low potential when the second cascode transistor is turned on and the supply voltage when the first cascode transistor and the current mirror are turned on; and g) a biasing network connected to the collector of the second cascode transistor for preventing the second cascode transistor from saturating when the second plate of the pump capacitor is switched to the low potential. A bipolar charge pump as in claim 1 wherein the biasing network comprises: a) a dual emitter transistor (Q24) having matched first and second emitters, and connected to provide base drive to the first and second cascode transistors (Q28, Q32) from one of its matched first and second emitters; b) first (Q26) and second (Q25) bias transistors, the emitters of the first and second bias transistors being matched, the base of the first bias transistor connected to the base of the second bias transistor, the emitter of the first bias transistor connected to the base of the second cascode transistor via a fourth resistive element (R9); and c) a clamping transistor (Q33) connected between the emitter of the first bias transistor and the collector of the second cascode transistor. A bipolar charge pump as in claim 2 and further including: a) a fifth resistive element (R4) connected between a bias source and the base of the dual emitter transistor (Q24); and b) a third bias transistor (Q11), the base of the third bias transistor connected to the collector of the third bias transistor and its emitter being connected to ground; and c) a sixth resistive element (R5) connected between the base of the dual emitter transistor and the collector of the third bias transistor.

Inventors: WILCOX MILTON, WILCOX, MILTON
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1990
Main classification: H02M3
IPC codes: H02M3, H03K17