Dynamic memory with a refresh control circuit

Abstract: The dynamic memory of the present invention allows refresh operations with low power consumption and with easy control. The dynamic memory includes a detection circuit which detects a decrease in the power voltage source and a control circuit to automatically refresh a memory cell in response to the detected signal.

Description: BACKGROUND OF THE INVENTION The present invention relates to a dynamic memory, and more particularly to a dynamic random access memory having a built-in refresh address counter. Dynamic random access memories (DRAM) are extensively used as a high speed, large capacity memory. The mainstream of DRAMs currently in use is of an address multiplex type. The address multiplex type DRAM is so structured that row address signals are taken in as an active level of a row address strobe signal ( RAS ) via a pair of address input terminals, and then column address signals are taken in as an active level of a column address strobe signal ( CAS ) via said pair of address input terminals. This construction reduces the number of address terminals to one half and the size of package. As one method of refreshing an address multiplex type DRAM, contrary to the use of the row address strobe signal at the time of normal accessing as an active level and then using the column address strobe signal as an active level, the column address strobe signal is used first as an active level and then the row address strobe signal as an active level to refresh the memory cell of the row designated by the built-in refresh address counter as the internal refresh mode of the DRAM. This technique has been proposed as CAS Before RAS (CBR) refreshing and is now employed in large capacity DRAMs. In order to refresh all of the memory cells, said CBR refresning operation must be repeated for the entire rows of the memory array. With the prior art DRAM as mentioned above, the refreshing operation is carried out using a power source at a voltage level similar to that used during the normal accessing operation at a disadvantage of consuming a large amount of power during the refreshing operation. Said CBR refreshing requires a controlling operation by a unit outside DRAM to successively activate a column address strobe signal and then a row address strobe signal each time DRAM is in the CBR refreshing cycle, complicating the control of refreshing operation and deteriorating the efficiency. SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic semiconductor memory with reduced power consumption at the time of refreshing operation. Another object of the present invention is to provide a dynamic semiconductor memory which is capable of simple refreshing operation without requiring an additional control for external control signals. The dynamic semiconductor memory according to this invention is set out in claim 1. According to the present invention, the internal address information of the refresh address counter is supplied to the refresh means by a simple operation of lowering the supply voltage from the first level to the second level, thereby performing automatic refreshing inside the memory. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram to show the construction of a prior art dynamic memory; Fig. 2 is a block diagram of a refresh mode detection circuit; Figs. 3A and 3B show the waveforms to explain the operation of CBR generation circuit; Fig. 4 is a block diagram to show a refresh control circuit of the first embodiment according to the present invention; Fig. 5 is a block diagram to show a refresh control circuit of the second embodiment according to the present invention; Fig. 6 is a block diagram to show a refresh control circuit of the third embodiment according to the present invention; and Fig. 7 is a block diagram to show a refresh control circuit of the fourth embodiment according to the present invention: DETAILED DESCRIPTION OF THE INVENTION (Description of the Prior Art) Referring to Figs. 1 through 3, the dynamic memory of the prior art will now be explained. Fig. 1 shows the overall construction of the dynamic memory. The memory cell array 1 comprises plural dynamic memory cells MC arranged in rows and columns, word lines WL arranged in each row and bit lines BL arranged in each column. A sense amplifier block 2 has plural refresh sense amplifiers SA which are provided in each column. A row address buffer 3 latches information at address terminals AT₁ - AT n as row address information in response to a timing signal ₁. An address switch circuit 5 is inputted with row address signals Ar₁ - Ar n from the row address buffer 3 and with count signals R₁ - R n from the refresh address counter 9, supplies row address signals Ar₁ - Ar n to a row address decoder 4 when an internal refresh mode signal  CBR is at an inactive level and supplies count outputs R₁ - R n to the row address decoder 4 when the signal  CBR is at an active level. The row address decoder 4 selects one word line which is designated by the signals Ar₁ - Ar n or R₁ - R n in response to a timing signal ₂. Information stored in the memory cell MC which is connected with the word line WL thus selected is read out in parallel at bit lines BL and also amplified and refreshed by the sense amplifier 2 which is energized in response to a timing signal ₃. A column address buffer 6 latches information of address terminals AT₁ - AT n as column address information in response to a timing signal ₄. A column address decoder 7 establishes a signal path between one of the bit lines BL and a bus line DB in response to a timing signal ₅. The bus line DB is connected to input/output terminals via an input/output circuit 8. A timing signal generator 10 receives a row address strobe signal RAS, a column address strobe signal CAS , and a signal  CBR , and generates timing signals ₁, ₂ and ₃ in this order upon activation of the signal RAS when the signal  CBR is at an inactive level. By realizing an active level for CAS after RAS reaches an active level, the timing signal generator 10 also generates signals ₄ and ₅ in this order. These steps are routinely conducted during an access operation. An example of a detection circuit 11 is shown in Fig. 2. NAND gates AG₁, AG₂ constitute a flip-flop and inverters IV₃, IV₄ a delay circuit. As shown in Fig. 3A, the circuit 11 outputs an inactive signal  CBR when the signal RAS is at an active (low) level and when the signal CAS reaches an active level or during a normal access cycle. In the meantime, as shown in Fig. 3B, when the signal RAS is activated after the signal CAS is brought to an active (low) level, the signal  CBR at an active level is outputted after a delay time of the inverters IV₃, IV₄ elapsed following said activation of the signal RAS . CBR refreshing operation will now be explained. The signal CAS is first brought to an active (low) level, and then the signal RAS is detected to be at an active (low) level. The refresh mode detection circuit 11 then outputs a signal  CBR , which is supplied to the timing signal generator 10 to successively activate the signals ₂ and ₃. Signals ₁, ₄ and ₅ remain inactive during this time. Because of the active (high) level of the signal  CBR , the count outputs R₁ - R n of the refresh address counter 9 are supplied to the row address decoder 4 via the address switch circuit 5 to select one of the word lines depending on the content of the counter 9 and to refresh the memory cell which is connected to the word line thus selected. The signal  CBR subsequently returns to an inactive level, and the internal refreshing operation is completed. By conducting the CBR refreshing operation for all of the word lines in the array 1, all the memory cells are refreshed. In other words, as the steps of activating the signal CAS and of subsequently activating the signal RAS are repeated for the number of times corresponding to the total number of the word lines WL in the memory array, the entire memory cells in the array are refreshed. The above procedure involves complex operation of the signals RAS and CAS and requires a complicated external system. It is also noted that during the internal (CBR) refreshing operation, the source voltage is maintained at the level routinely employed for the normal access operation and the power consumption during the internal refreshing operation is considerable. An embodiment of the present invention will now be explained referring to Fig. 4. The memory of this embodiment is realized by replacing the inverters IV₁, IV₂ and the detection circuit 11 shown in Fig. 1 with a refresh control circuit of Fig. 4. The rest of the structure is identical to that shown in Fig. 1. The following description will therefore refer only to the control circuit. In the embodiment, a source voltage detection circuit 21 is provided with MOS transistors of an N-channel enhancement type, T₁ - T N , T₁₁ and inverters IV₁₁, IV₁₂, and outputs a signal V pd for detecting the source at a low level when the source voltage Vcc drops below the lower limit of the recommended operating voltage (hereinafter referred to as rated voltage). An oscillation circuit 22 is provided with inverters IV₁₃, IV₁₄, IV₁₅ and a NOR gate OG₁, and outputs an oscillation signal V OSC of a predetermined frequency when the source voltage detection signal V pd is at a high level. A CBR signal generator circuit 23 is provided with a delay element D1, and is inputted with the oscillation signal V OSC to generate first trigger signal V C without delay as well as the second trigger signal V R with a delay of a prescribed time from the first trigger signal V C . The second trigger signal V R is inputted at a NOR gate OG₂ together with a row address strobe signal RAS , while the first trigger signal V C is inputted at a NOR gate OG₃ together with a column address strobe signal CAS . Outputs from the NOR gates OG₂ and OG₃ are inputted at the detection circuit 11 which outputs a signal  CBR . The structure of the detection circuit 11 is shown in Fig. 2. The operations of the embodiment will now be explained. The MOS transistors T₁ - T N of the voltage detection circuit 21 with the input of source voltage Vcc are in diode connection, the number of stages is so selected that when the source voltage Vcc is within the rated operating voltage range (e.g. 5.5 - 3.5 V), an output node N2 of the Inverter IV₁₁ with the input of an output node N1 comes to a low level and when the voltage Vcc is lower than the lower limit of the recommended operating voltage, the output node N2 of the inverter IV₁₁ comes to a high level. The voltage level when the source voltage Vcc is within the rated operating voltage or the level of the source voltage, detection signal V pd is high which is an inactive level, and the level at a node N7 which is the output (V OSC ) of the NOR gate OG₁ having the voltage detection signal V pd as the gate input becomes low. Since the level at the nodes N9 and N10 varies in synchronization with the row address strobe signal RAS and the column address strobe signal CAS that are inputted from the outside, the normal access operation becomes possible. When the source voltage Vcc drops below the lower limit of the recommended operating voltage, the source voltage detection signal V pd reaches a low or active level, and an oscillation signal V OSC of the output node N5 of the ring oscillator comprising the inverters IV₁₂ - IV₁₅ is outputted at the output node N7 of the NOR gate OG₁. At the node N8, the second trigger signal V R in the same phase but slightly delayed from the oscillation signal V OSC by the delay element D1 is outputted. And the detection circuit 11 is held in a state identical to the state when the gate input of the NOR gates OG₂ and OG₃ is in the CBR refresh cycle, or when the row address strobe signal RAS is activated after the column address strobe signal CAS is activated. In other words, the detection circuit 11 is inputted via the gate circuits OG₂ and OG₃ with signals that are identical to the row address strobe signal RAS and the column address strobe signal CAS during the CBR refresh cycle. The detection circuit 11 judges the level and the timing of these signals and outputs the refresh control signal  CBR to effect CBR refresh operation. A refresh control circuit according to the second embodiment is shown in Fig. 5. According to the second embodiment, the CBR signal generator 23′ comprises an inverter IV₁₆ and a delay element D1 and the gate circuits OG₂ and OG₃ are replaced by NAND gates AG₄ and AG₅ respectively. The operation is substantially the same as that in the first embodiment. A refresh control circuit according to the third embodiment is shown in Fig. 6. According to this embodiment, the ring oscillation circuit 22′ comprises a NOR gate OG1′ and inverters IV₁₄ and IV₁₅, the NOR gate OG1′ being incorporated in the loop of the ring oscillator. The CBR signal generator 23′ comprises as inverter IV₁₆ and a delay element D1. A refresh control circuit according to the fourth embodiment is shown in Fig. 7. According to this embodiment, the ring oscillation circuit 22′ is identical in construction to the third embodiment, while the CBR signal generator 3 comprises a delay element D1 alone, and the NAND gates AG₄ and AG₅ are employed. The operations of these third and fourth embodiments are also the same as that in the first embodiment. As has been described in the foregoing, the present invention is to structured that when the source voltage drops below the lower limit of the recommended operating voltage, signals identical to the row address strobe signal RAS and the column address strobe signal CAS in the CBR refresh cycle are generated and supplied to the detection circuit 7 to thereby automatically switch to a refresh mode whenever the voltage drops below the lower limit of the recommended operating voltage. This not only prevents loss of data but saves the voltage consumption during the refresh operations as the voltage can be maintained at a low level.

Claims: A dynamic memory comprising a memory array (1) having a plurality of dynamic memory cells arranged in rows and columns; an address input means (3) for receiving row address information; a refresh address counter (9) generating an internal refresh address; a switching circuit (5) connected to said address input means (3) and said refresh address counter (9) and selecting and outputting said row address information when in a first state and an internal refresh address when in a second state; refresh means for refreshing at least one of memory cells; and a control circuit (11), when activated, causing said switching circuit to change into the second state to select and output said internal refresh address and causing said refresh means to refresh memory cells in one of said rows in said memory array (1) in response to said internal refresh address outputted by said switching circuit, and when not activated, causing said switching circuit to change into the first state; a detection circuit (21) configured so as to detect a decrease in a voltage of a power source voltage terminal (Vcc) and so as to output a detection signal (VPD) when said voltage has decreased, characterized in that an activation circuit (22, 23, OG2, OG3, 11) is operatively connected to said detection circuit (21) and activates said control circuit (11) in response to said detection signal (VPD).

Inventors: HOSHI KATSUJI, HOSHI, KATSUJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G11C11
IPC codes: G11C11