Method of fabricating a structure having self-aligned diffused junctions

Abstract: A method of fabricating a semiconductor structure having self-aligned diffused junctions (44) is provided wherein a first dielectric layer (12), a doped semiconductor layer (18) and a second dielectric layer (20) are formed on a semiconductor substrate (10). An opening (26,34) extending to the semiconductor substrate (10) is then formed through these layers. Undoped semiconductor spacers (38) are formed in the opening (26) adjacent to the exposed ends of the doped semiconductor layer (18) and dopant is diffused from the doped semiconductor layer (18) through the undoped semiconductor spacers (38) and into the semiconductor substrate (10) to form junctions (44) therein. This provides for integrated contacts through the doped semiconductor layer (18).

Description: Background of the Invention This invention relates, in general, to semiconductor structures, and more particularly to a method of fabricating a semiconductor structure having self-aligned diffused junctions. In an article entitled "A Novel CMOS Structure With a Reduced Drain-Substrate Capacitance", IEEE Transactions on Electron Devices, Vol. 36, No. 3, page 598, March 1989, Sagara et al. describe a CMOS structure and method of fabrication. To fabricate the structure, junctions are formed by the lateral diffusion of impurities from imbedded doped polysilicon films into mesas of the silicon substrate. The method employs no spacer technology. This method has relatively limited scalability because the total junction area is defined by a photolithographic etch and diffusion which require that lithographic parameters be maintained. U. S. Patent 4,569,701 entitled "Technique for Doping from a Polysilicon Transfer Layer" issued to Oh on February 11, 1986 teaches that it is necessary to controllably dope trench sidewalls for trench isolation technology or trench capacitor type memory cells. The technique disclosed includes depositing a transfer layer of polysilicon to conformally coat the trench bottom, sidewalls and the top surface surrounding the trench. An impurity is implanted into the polysilicon at the bottom of the trench and around the top surface. The impurity is diffused throughout the sidewalls by heating and may then be diffused into the substrate. U. S. Patent 4,209,350, entitled "Method for Forming Diffusions Having Narrow Dimensions Utilizing Reactive Ion Etching" issued to Ho et al. on June 24, 1980, is also related to the present invention. Diffusions having submicrometer dimensions are formed in a silicon body by forming insulator regions having substantially horizontal and vertical surfaces and then forming a layer having a desired dopant concentration thereon. The layer is then reactive ion etched to remove only the horizontally disposed portions of the layer. The dopant is then diffused into the silicon body by heating. European patent application No. 83305971.0 having publication No. 107 416 applied for by Fujitsu Limited discloses a method of producing a bipolar or MOS semiconductor device. The device is formed by forming an insulating film on a semiconductor substrate, forming a first conductive film on the insulating film, forming a first masking film having a window, isotropically etching the conductive film to form an opening, and transversely etching the conductive file to form a protruding portion of the masking film. A second masking film is then formed on the insulating film through the window and a uncovered portion of the insulating film is etched beneath the protruding portion. A second conductive film connecting the first conductive film and the exposed portion of the semiconductor substrate is then formed. Dopant may then be diffused into the substrate from the first conductive film through the second conductive film. European patent application no. 83816 discloses a method of producing bipolar or unipolar transistors. The device is formed by forming an insulating film on a semiconductor substrate, forming a doped semiconductor layer and an insulating film, opening a window through said layers, depositing a film of undoped semiconductor, removing said film of undoped semiconductor by anisotropic etching, thereby leaving undoped sidewalls in the window, and heat-treating to diffuse dopants from the doped semiconductor layer to the semiconductor substrate through the undoped sidewalls. There is a need for an improved method of fabricating a semiconductor structure having self-aligned diffusion junctions and allowing precise control and increased scalability and giving rise to semiconductor devices of increased speed. Summary of the Invention According to one aspect of the invention, there is provided a method of fabricating a semiconductor structure having self-aligned diffused junctions comprising the steps of: providing a semiconductor substrate; forming a first dielectric layer on said substrate; forming a doped semiconductor layer on said first dielectric layer; forming a second dielectric layer on said doped semiconductor layer; and forming an opening through said second dielectric layer extending to said doped semiconductor layer. This aspect of the invention is characterized by: forming a conformal nitride layer over the doped semiconductor layer, etching said conformal nitride layer, wherein the etching forms nitride dielectric spacers, adjacent exposed sidewalls in said opening; forming dielectric material by thermal oxidation of said doped semiconductor layer in said opening between said dielectric spacers; removing said dielectric spacers; forming openings through said doped semiconductor layer and said first dielectric layer at the regions where said dielectric spacers were formerly disposed, said dielectric material also being removed; forming undoped semiconductor spacers in said openings, said spacers being adjacent to the exposed ends of said doped semiconductor layer, wherein the doped semiconductor layer in the opening is removed; and diffusing dopant from said doped semiconductor layer, through said undoped semiconductor spacers and into said substrate to form junctions in said substrate. Accordingly the invention provides for precise control of the junction area, increased scalability and submicrometer dimensions. The invention enables integrated contacts to be provided through a horizontal semiconductor layer and it avoids the need for an etch of polysilicon over monosilicon in active device regions. This method of forming junctions provides integrated contacts through the doped horizontal semiconductor layer. Brief Description of the Drawings Figs. 1-16 illustrate highly enlarged cross-sectional views of a portion of a semiconductor structure embodying the present invention during various stages of processing. Detailed Description of the Invention Figs. 1-16 illustrate highly enlarged cross-sectional views of a portion of a semiconductor structure during various stages of processing. In Fig. 1, a semiconductor substrate 10 is provided. In this embodiment, semiconductor substrate 10 comprises monocrystalline silicon and may include a buried layer (not shown) therein. A first dielectric layer 12 is then formed on semiconductor substrate 10. First dielectric layer 12 includes a first oxide layer 14 which is formed by the thermal oxidation of monocrystalline silicon substrate 10 and a first nitride layer 16 which is formed on first oxide layer 14. First nitride layer 16 is formed by CVD in this embodiment. A polysilicon layer 18 is formed on first nitride layer 16. Polysilicon layer 18 is formed by CVD and is undoped at its formation in this embodiment although polysilicon layer 18 may be doped during formation by methods well known in the art. However, in this embodiment, polysilicon layer 18 is doped after its formation by methods well known in the art. After the formation of polysilicon layer 18, a second dielectric layer 20 is formed thereon. Second dielectric layer 20 may be comprised of second nitride layer 22 and second oxide layer 24 as shown in FIG. 1 or only of second oxide layer 24 as shown in FIG. 2. Second nitride layer 22 and second oxide layer 24 are both formed by methods well known in the art. Following the formation of second dielectric layer 20, a mask (not shown) is formed on second oxide layer 24 and reactive ion etching is used to form a device opening 26 through second dielectric layer 20 that extends to doped polysilicon layer 18. FIG. 3 depicts the formation of a conformal nitride layer 28 on the semiconductor structure. Conformal nitride layer 28 may be formed by CVD, PECVD or one of many other nitride formation methods well known in the art. As shown, conformal nitride layer 28 is disposed along the sidewalls and bottom of device opening 26. FIG. 4 shows the formation of nitride spacers 30 from conformal nitride layer 28. Essentially, conformal nitride layer 28 is completely removed excepting nitride spacers 30 which are formed along the sidewalls of device opening 26. Nitride spacers 30 are formed by the reactive ion etching of conformal nitride layer 28. Further, nitride spacers 30 are variable in that they may be deposited to different thicknesses depending upon the intended applications. In FIG. 5, an oxide lens 32 is formed in device opening 26 between nitride spacers 30. Oxide lens 32 is formed by the thermal oxidation of doped polysilicon layer 18 between nitride spacers 30. Depending upon the application for which the structure will be used, oxide lens 32 may be formed to different thicknesses. Following the formation of oxide lens 32 in device opening 26, nitride spacers 30 are removed as shown in FIG. 6 to leave portions of doped polysilicon layer 18 exposed. Nitride spacers 30 are removed in this embodiment by a wet etch employing an etchant of hot phosphoric and sulfuric acids that has excellent nitride/oxide selectivity. FIG. 7 depicts the formation of openings 34 in device opening 26 at the regions where nitride spacers 30 were formerly disposed. In this embodiment, openings 34 are formed using a multiple part etch. Initially, openings 34 are etched through doped polysilicon layer 18 by anisotropic reactive ion etching. It can be seen that this part of the etch also reduces the thickness of oxide lens 32. In FIG. 8, openings 34 are etched through first nitride layer 16 and first oxide layer 14 to semiconductor substrate 10. Anisotropic reactive ion etching is also employed here. This etch is also designed to remove oxide lens 32 from doped polysilicon layer 18 in device opening 26. Depending upon the application for which this structure will be employed, openings 34 may further be etched into semiconductor substrate 10 as shown in FIG. 9. An isotropic silicon etch may also be employed at this point. In FIG. 10, a conformal polysilicon layer 36 is formed on the structure. Conformal polysilicon layer 36 is formed on second oxide layer 24 as well as in device opening 26 and openings 34. Conformal polysilicon layer 36 is undoped and in this embodiment, is formed by LPCVD. FIG. 11 depicts the formation of polysilicon spacers 38 from conformal polysilicon layer 36. It should be understood that conformal polysilicon layer 36 is completely removed except for polysilicon spacers 38. The anisotropic reactive ion etch used to form polysilicon spacers 38 also removes the portion of doped polysilicon layer 18 which was disposed in device opening 26. In another embodiment depicted by FIGS. 12 and 13 , a screen oxide layer 40 is formed on polysilicon spacers 38. In this embodiment, screen oxide layer 40 is formed by thermally oxidizing polysilicon spacers 38 although it could be formed by other methods well known in the art. Once screen oxide layer 40 has been formed on polysilicon spacers 38, the portion of first nitride layer 16 disposed in device opening 26 is removed. This is done by a wet etch employing an etchant of hot phosphoric and sulfuric acid that insures good selectivity to the underlying first oxide layer 14. Another embodiment of forming a screen oxide layer is depicted by FIGS. 14 and 15. In FIG. 14, the portions of first nitride layer 16 and first oxide layer 14 that are disposed in device opening 26 are removed thereby exposing semiconductor substrate 10. Again, first nitride layer 16 is removed by a wet etch employing an etchant of hot phosphoric and sulfuric acids and first oxide layer 14 is removed by low bias reactive ion etching. In FIG. 15, screen oxide layer 40 is formed by thermally oxidizing polysilicon spacers 38 and semiconductor substrate 10 in device opening 26 between polysilicon spacers 38. It should be understood that the choice of oxidation conditions depends in part in what differential oxidation of polysilicon versus monosilicon is desired and the effectiveness of the monosilicon oxide as a sacrificial oxide for certain device applications. The formation and patterning of masks on screen oxide layer 40 for the implantation of dopants into semiconductor substrate 10 may now be employed depending upon the application for which the structure will be used. One skilled in the art will understand that the species, dose and energy will be application specific. FIG. 16 depicts the formation of dielectric spacers 42. In this embodiment, dielectric spacers 42 are comprised of oxide and are formed by CVD although other dielectric materials such as CVD nitride may be employed. It should be understood that dielectric spacers 42 should be formed of a thickness required to result in a spacer width tailored to a specific device application. Dielectric spacers 42 serve to limit the finished emitter width if the structure is to be used for a bipolar device or the finished gate length if the structure is to be used for an MOS device. This procedure is very useful in achieving deep, well controlled sub-micrometer device dimensions below those that can be obtained by employing state of the art photolithography techniques. Also shown in FIG. 16 are junctions 44. Junctions 44 are formed by diffusing dopant from doped polysilicon layer 18 through originally undoped polysilicon spacers 38 and into semiconductor substrates 10. Of course, polysilicon spacers 38 will become doped once dopant is diffused therethrough into semiconductor substrate 10 thereby establishing electrical connection between polysilicon layer 18 and substrate 10. One of skill in the art will understand that integrated contacts are automatically created to junctions 44 through polysilicon spacers 38 and polysilicon layer 18. It should be understood that the method disclosed herein will enable one of skill in the art to fabricate a wide spectrum of devices. This method may be used for bipolar devices as well as MOS devices with elevated electrodes and will allow for the fabrication of BICMOS circuits that employ only one basic semiconductor structure.

Claims: A method of fabricating a semiconductor structure having self-aligned diffused junctions (44) comprising the steps of: providing a semiconductor substrate (10); forming a first dielectric layer (12) on said substrate (10); forming a doped semiconductor layer (18) on said first dielectric layer (12); forming a second dielectric layer (20) on said doped semiconductor layer (18); forming an opening (26) through said second dielectric layer (20) extending to said doped semiconductor layer (18); the invention being characterized by: forming a conformal nitride layer (28) over said semiconductor structure; etching said conformal nitride layer (28), wherein said etching forms nitride dielectric spacers (30), adjacent exposed sidewalls in said opening (26); forming dielectric material (32) by thermal oxidation of said doped semiconductor layer (18) in said opening (26) between said dielectric spacers (30); removing said dielectric spacers (30); forming openings (34) through said doped semiconductor layer (18) and said first dielectric layer (12) at the regions where said dielectric spacers (30) were formerly disposed, said dielectric material (32) also being removed; forming undoped semiconductor spacers (38) in said openings (34), wherein said doped semiconductor layer (18) in said opening (26) is removed, said spacers (38) being adjacent to the exposed ends of said doped semiconductor layer (18); and diffusing dopant from said doped semiconductor layer (18), through said undoped semiconductor spacers (38) and into said substrate (10) to form junctions (44) in said substrate. The method of claim 1 wherein the first dielectric layer (12) further comprises first oxide layer (14) and first nitride layer (16). The method of claim 1 wherein second dielectric layer (20) comprises second nitride layer (22) and second oxide layer (24). The method of claim 1 wherein the forming openings (34) step comprises the steps of: etching through the doped semiconductor layer (18); etching through the first dielectric layer (12); and etching into the semiconductor substrate (10) if it is desired that said openings (24) extend into said semiconductor substrate (10). The method of claim 4 wherein said doped semiconductor layer (18) is comprised of doped polysilicon. The method of claim 4 wherein the openings (34) formed where the nitride dielectric spacers (30) were formerly disposed extend into the semiconductor substrate (10). The method of claim 6 further including the step of forming dielectric spacers (42) in the opening (26), said dielectric spacers (42) serving to limit finished emitter width in a bipolar device or finished gate length in an MOS device. The method of claim 1 wherein the forming undoped semiconductor spacers (38) step comprises: forming undoped semiconductor material (36) in the openings (34) formed where the nitride dielectric spacers (30) where formerly disposed; and removing the doped semiconductor layer (18) and the first dielectric layer (12) from between said undoped semiconductor material (36). The method of claim 1 further including the steps of: forming a screen oxide layer (40) on the undoped semiconductor spacers (38) and on the semiconductor substrate (10) in the opening (26); forming and patterning masks on said screen oxide layer (40); implanting dopants into said substrate (10); and forming oxide or nitride spacers (42) in said opening (26), said oxide or nitride spacers (42) serving to limit finished emitter width in a bipolar device or finished gate length in an MOS device.

Inventors: VASQUEZ BARBARA, ZDEBEL PETER J, VASQUEZ, BARBARA, ZDEBEL, PETER J.
Applicants: MOTOROLA INC, MOTOROLA INC.
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L29