Automatic signal parameter control

Abstract: A fast acting automatic gain control system comprising a single or serial multistage arrangement. In one multistage embodiment each stage (13) has a first state with a predetermined gain and a second state with unity gain. The output of each stage determines what state is finally adopted although initially when a signal is input it is in the first state due to the action of a sequence controller (14). The predetermined gain values may comprise a binary sequence which descends in the direction towards the output. If the level detector (17) threshold is exceeded, the stage is set to the second state. A particular use of the system is to ensure burst mode pulses reaching a receiver are of similar amplitude. A similar arrangement can be employed for phase alignment rather than gain control. In another multistage embodiment a sequence controller is not required and the input signal level is used to set the required state of an amplifier (17) before the input signal is applied to the amplifier, by means of a comparator (15) and a delay (16). An analogue equivalent of the Fig 2 embodiment is a single stage arrangement.

Description: This invention relates to automatic signal parameter control such as automatic gain-control and in particular, but not exclusively, to amplifier systems for burst mode transmission systems. In the case of an optical local area network such as a number of subscribers connected by optical fibre to a local exchange, each subscriber being allocated a respective time slot for transmission, for example as in a time division multiple access (TDMA) arrangement, then simply because of the distances involved and the number of fibre splits, there will be an optical signal level difference as seen at the exchange between the signal packets received from the various subscribers. In order to achieve a high efficiency network, the time slots need to be compressed as close together as possible, so that a receiver at the exchange will see significant variations in amplitude in a very short period of time. An object of the present invention is to compensate for these variations. Journal of the Audio Engineering Society: Vol 32; no 5, 1984, by G W McNally provides a number of amplifier circuits applicable to digital audio signals but concerns computational techniques rather than real analogue-like signals. GB 1036647 relates to seismology and provides a cascaded aplifier with each stage being controlled by a single external controller. According to the present invention there is provided a serial multistage arrangement serving to control a parameter of a signal automatically, which signal is applied in cascade to each stage, wherein each stage has a first state in which a first predetermined amount of change to the parameter of the signal as input thereto is provided and a second state in which a second predetermined amount of change to the parameter is provided, and including means such that initially each stage is in the first state but such that in dependence on the signal input at that stage, the stage can be set to the second state, wherein each stage includes means switchable between said first and second states and which perform said parameter control, means to measure said parameter of the signal as input to the stage and to switch the switchable means to the second state if appropriate, and delay means whereby the signal as input to the stage is applied to said switchable means for parameter control only after said measurement and any necessary switching has been performed. An embodiment of the invention will now be described with reference to the accompanying drawing which is a schematic diagram of an a.g.c. amplifier. In the arrangement shown each stage comprises a comparator such as 15, a latch 25, a delay such as 16 and amplifier 17. The gain state of the amplifier is switchable between a high gain state and a low gain state, for example, unity gain. Thus an incoming signal is differentiated, amplified at 18 and then applied to two signal paths 19 and 20. Path 19 leads to comparator 15 which has a threshold level set so as to prevent the amplifier 17 from saturating. The path 20 passes through the delay 16 to the amplifier 17. The delay is sufficient for the comparator 15 to have sampled the peak input signal amplitude and to have latched latch 25, for example an R-S flip-flop or similar device, and to have switched the gain stage of the amplifier 17, if necessary, before the data signal actually arrives at the amplifier's input. Because this is a truly sequential process any number of such stages can be cascaded. The amplifiers 17 are initially set to their high gain states, in the example illustrated successive stages have high gain states of 16dB, 8dB, 4dB, 2dB and 1dB, although these are not the only possIbilities, the number of stages and their gains being determined by the particular Application. Typically the delays 16 are comprised by 25ns delay lines and the overall delay between the signal input and the signal output is approximately 200ns. The main advantage of the arrangement illustrated is that no bits of data from an incoming "packet" are lost, and compared with fibre delays in the system, the receiver delay is negligible. At the end of a data packet the latches 25 and therefore the gain stages are reset into their high gain state, i.e. amplifiers 17 are reset, to be ready to detect the next incoming packet. The output of the last stage of the arrangement illustrated is applied to a low pass filter 21 whose output is split between two signal paths one of which is applied via a comparator referenced to logic "1", comparator 22, to the reset input of latch 23, and the other of which is applied via a comparator referenced to logic "0", comparator 24, to the set input of latch 23. The signal output from the arrangement is at the Q port of latch 23. Whereas the above arrangement is for amplitude control, this is not the only possibility. Alternatively, a similar arrangement could achieve phase control, in which case switchable phase shifters would replace the switchable amplifiers. Thus phase alignment can be achieved. The detectors would detect phase rather than level. The arrangement illustrated involves the simple principle of measuring the signal's amplitude (or alternatively its phase) and correcting for it before the signal actually arrives at the amplifier or other element of the stage. This may be of particular importance in burst-mode and TDMA (Time Division Multiple Access) systems for improving network efficiency by reducing the number of redundant bits required at the head of a packet of data.

Claims: A serial multistage arrangement serving to control a parameter of a signal automatically, which signal is applied in cascade to each stage, wherein each stage has a first state in which a first predetermined amount of change to the parameter of the signal as input thereto is provided and a second state in which a second predetermined amount of change to the parameter is provided, and including means such that initially each stage is in the first state but such that in dependence on the signal input at that stage, the stage can be set to the second state, wherein each stage includes means (17) switchable between said first and second states and which perform said parameter control, each stage includes means (15,25) to measure said parameter of the signal as input to the stage and to switch the switchable means (17) to the second state if appropriate, and each stage includes delay means (16) whereby the signal as input to the stage is applied to said switchable means (17) for parameter control only after said measurement and any necessary switching has been performed. An arrangement as claimed in claim 1 wherein said parameter is amplitude and comprising an automatic gain control system. An arrangement as claimed in claim 1 whereln said parameter is phase and comprising an automatic phase alignment system. An arrangement as claimed in claim 2 wherein each stage includes a delay element (16) and a switchable amplifier (17) in series between the stage input and output, which amplifiers (17) are switchable between first and second gain states and have respective predetermined values of gain in the first gain states. An arrangement as claimed in claim 2 or 4, wherein the predetermined values of gain of successive stages comprise a binary sequence which descends in the direction towards the output of the arrangement. A TDMA communications system including a serial multistage arrangement according to any one of claims 1 to 5.

Inventors: FRY DAVID WILLIAM, FRY, DAVID WILLIAM
Applicants: NORTHERN TELECOM LTD, NORTHERN TELECOM LIMITED
Application year: 1990
Main classification: H03G3
IPC codes: H03G7, H03G3