MOS switching circuit having gate enhanced lateral bipolar transistor

Abstract: Circuitry for implementing a gate enhanced lateral transistor (3l) to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into an FET providing essentially no voltage drop across the collector-emitter connections permitting the collector to reach a full power supply voltage.

Description: The present invention relates to integrated MOS circuits with gate enhanced lateral bipolar transistor devices. BiCMOS technology permits the integration in MOS circuit structures of both bipolar transistors and CMOS FET devices. In circuit applications which require driving a high capacitance load, bipolar output transistors are advantageous due to their high level current supply capability. BiCMOS circuits have been developed which include both lateral PNP transistors and vertical NPN transistors, at the cost of increased technological complexity. The lateral PNP transistor is formed inside the N-well of a BiCMOS or CMOS integrated circuit by a narrow field oxide. Typically, the width of the field oxide defining the lateral PNP transistor base region is at the minimum dimension which the lithographic technique for forming these devices permits. Recent developments have permitted these devices to be defined in ever decreasing dimensions. For instance, using finer lithographic printing, .4µm polysilicon gates can be printed in 1.0 µm CMOS technology. The disadvantage with bipolar devices is the voltage drop with which fully conducting saturated bipolar devices suffer. With FET devices, the fully conducting condition provides substantially zero voltage drop, thus permitting an output voltage swing between Vdd, the drain potential, and Vss, the source potential. In JP-A-61 274512 a buffer circuit is disclosed, using a bipolar transistor and a FET in parallel to suppress the output level reduction by an emitter-collector voltage at the ON-state. The prior art recognizes that lateral bipolar transistors may be implemented having a gate electrode of polysilicon which defines the base region of the lateral bipolar transistor. In U.S. Patent 4,089,022, a gate electrode is provided which is insulated from the base region of a lateral transistor. The gate electrode is biased to lower the surface potential of the minority carriers. The biasing is essentially a DC voltage which may be used to alter the device performance. The present invention as claimed utilizes such gate equipped lateral transistors to overcome the afore-mentioned disadvantage of a voltage drop which occurs between the emitter and collector terminals. The bipolar transistor performance therefore resembles an FET device without compromising load capacity or switching speed. This and other objects of this invention are provided by a circuit which includes as an output driving device a lateral bipolar transistor having a base region defined by a polysilicon gate. The device is operated as a merged device switching both the gate connection and base connection of the device. The application of a switching potential to both base and gate connection is effective in ensuring that carriers flow not only inside the device bulk but also along the surface of the silicon. Use of the conduction path provided by the FET channel of the device permits the output level of the device to reach full output equal to the potential on the emitter which also serves as a source connection. The resulting full power supply swing provides a higher noise margin than is realized with conventional CMOS-implemented bipolar devices. In a preferred embodiment of the invention, a lateral gate enhanced PNP transistor is implemented with a vertical NPN transistor in a BiCMOS integrated circuit. One or the other of said devices is enabled to conduct current by virtue of a CMOS logic state defined by a PFET and NFET network. The PNP transistor when enabled by the PFET network is driven with a voltage level so that the base connection and gate connection establish conduction between the emitter and collector connections: The gate voltage will result in the emitter collector connection becoming essentially a P channel with substantially zero voltage drop. Complementary P channel and N channel devices alternatively connect the respective base and emitter connection of each bipolar transistors together when the bipolar transistor is to be rendered non-conducting. The invention describes a gate controlled lateral bipolar transistor which provides the current drive capability of bipolar switching with the voltage drop of an MOS FET switching device. For a better understanding of the present invention, together with further objects and advantages, preferred embodiments of the invention are described in the following with reference to the accompanying drawings, in which: Figure 1A illustrates a gate enhanced lateral PNP transistor implemented in CMOS technology; Figure 1B schematically illustrates the gate enhanced lateral PNP transistor of Figure 1A; Figure 1C schematically illustrates the conducting switching state of the gate enhanced lateral PNP transistor of Figure 1A; Figure 2 illustrates an embodiment of the invention implemented in pure CMOS technology; Figure 3 illustrates a BiCMOS implemented drive circuit using the benefits of a gate switched lateral PNP transistor; Figure 4 illustrates a two input NAND logic circuit with a BiCMOS complementary drive circuit; and Figure 5 illustrates an SOI implemented lateral PNP transistor which may be adapted for use in the foregoing circuits. Referring now to Figures 1A, 1B and 1C, there is shown a gate enhanced lateral PNP transistor implemented in CMOS. A substrate 10 is shown which is doped to a P+ relative doping with respect to the layer 9, also part of the substrate. The gate enhanced lateral PNP transistor has an N-well 14 which connects to a base connection B through an N-type implant 13. A buried layer 12 is shown which also includes an N doping similar to the doping of N-type implant 13. The base connection is effected through the N-type base contact implant 17. Disposed on the surface of the N-well 14 are two P-doped regions 16 and 20 which define a collector and emitter of a bipolar device. Disposed laterally in the region between the collector 16 and emitter 20 is a polysilicon gate 19. The gate is insulated from the collector, base and emitter 16, 14 and 20 by insulating layer 18. The gate enhanced lateral PNP transistor may be implemented with state-of-the-art CMOS fabrication techniques to have a gate width in the region of 0.5 microns. The device switches faster as the width of the gate region narrows. To take advantage of the improved switching speed of devices having narrow base widths defined by a polysilicon gate 19, Figures 1B and 1C illustrate the effect of switching the lateral PNP from a non-conducting emitter collector circuit to a conducting emitter collector circuit. It can be seen that enabling the base and gate connection together will render the collector emitter circuit conducting. When the gate connection is also switched, the device appears as a MOS FET device as shown in Figure 1C. In this configuration, the emitter becomes a source, the collector a drain, and the base has essentially no participation in the conduction mode of the device. As will be evident in the following implementations of the lateral PNP in both pure CMOS fabrication and BiCMOS fabrication, the device of Figure 1C has essentially no voltage drop from source to drain. Thus, whereas a true bipolar device would always have a voltage drop from collector to emitter (VCE), which deprives the device of a full voltage swing up to the emitter voltage, the device of Figure 1C has no such voltage drop. Illustrated in Figure 2 is an inverter circuit using the lateral PNP transistor as a high current load driving device. The lateral PNP transistor provides enhanced load driving capabilities, increasing the current to a connected load. The inverter circuit comprises, along with the lateral PNP transistor 31, P channel devices 32 and 33, as well and an N channel device 34. The virtue of the implemented lateral transistor in the inverter circuit of Figure 2 is to take advantage of the pull-up feature. When lateral PNP transistor 31 is gated to conduct current through the collector emitter circuit, the gate connection permits the device to operate as a fully enabled MOS FET transistor, shown in Figure 1C. Thus, a full voltage pull-up to level Vdd is achieved, increasing the voltage swing for the inverter, avoiding the usually present VCE voltage drop of bipolar devices. The base connection of the lateral enhanced PNP transistor 31 is gated into conduction by the operation of P channel device 33 when the input 29 goes low. At this time, not only is the base device 31 conducting current, but the gate is also held at a low potential, thus providing the configuration of Figure 1C. During the opposite input condition for the inverter of Figure 2, a high level signal will gate device 34 on, bringing the collector to essentially Vss. Additionally, the P channel device 32 will connect the base and emitter together, bringing the device to its non-conducting state. This basic implementation of a pure CMOS inverter may be also implemented in BiCMOS devices as shown in Figure 3. The BiCMOS driver device provides bipolar drive capability for both states of the logic signal applied to input 37. A lateral PNP transistor 38 is shown for driving the output node 39 to the full Vdd voltage level during the first logic input condition to input 37. A vertical implemented NPN transistor 43 is shown for providing current sinking from node 39 to Vss during the second logic input condition applied to input 37. Switching the lateral PNP transistor gate as well as the base permits the junction 39, during the pull-up mode, to be brought essentially to Vdd, eliminating the disadvantage of bipolar device collector emitter voltage drop. During the opposite logic condition, node 39 will be brought to a potential which is essentially the voltage drop across NPN transistor 43, VCE, above the desired power supply voltage Vss. Switching of these two complementary bipolar devices is shown using a PFET network comprising a PFET 41, 45, as well as an NFET network comprising devices 42 and 44. During a first logic condition applied to input 37, device 41 is rendered conducting, thus enabling the base connection of the lateral PNP transistor 38. At the same time, the gate of this device is used to increase the hole diffusion through the base of lateral PNP transistor 38, rendering the device to a conducting configuration as shown in Figure 1C. During the opposite logic state, vertical NPN transistor 43 is rendered conducting by the operation of NFET 42. When the device 38 is returned to a non-conducting mode, the P channel device 45 assists in turning device 38 into the non-conducting mode of Figure 1B. Similarly, the N channel device 44 will tend to bias the NPN vertical bipolar transistor 43 in the off state. Figure 4 illustrates how the inverter circuits previously described may be used to implement standard logic circuitry. A two input NAND gate is shown in Figure 4, using a vertically implemented NPN transistor 50, and two lateral PNP transistors 51 and 52. The operation of the two input NAND circuits requires a PFET network and NFET network. The PFFT network shown has a pair of PFET devices 54 and 55 which are used to enable the bases of lateral PNP transistors 51 and 52. These gates of the PFET network are enabled by the logic state applied to inputs 48 and 49 representing logical values of X and Y. Additionally, the same logic inputs are applied to the gate connections for lateral PNP transistors 51 and 52. Thus, when the value of X is zero, both the gate and base of lateral PNP transistor 51 is rendered conducting. Additionally, when the logic state Y is zero, the gate and base of gate enhanced later PNP transistor 52 is rendered conducting by the voltage applied to the base and polysilicon gate connection. The NFET network comprises NFET devices 58 and 59, which conduct when both X and Y are at a logic 1 condition. Under this condition, the vertically implemented NPN transistor 50 is conducting through its collector emitter connection. Devices 60 and 62 participate in the turn-off of the vertical NPN transistor 50. Thus, when either of PNP devices 51 and 52 are conducting, NFET device 60 will effectively bias the vertical NPN device 50 to a non-conducting state, through the bipolar diode 62. Similarly, the PFET device 56 is used to hold devices 51 and 52 non-conducting when NPN device 50 is conducting. It is thus clear that the gate enhanced lateral PNP devices 51 and 52 will both provide an output node 63 the full Vdd level. When both X and Y are at the logic one ("1") state, the NPN device 50 will provide the logic NAND output zero on node 63. This logic zero will be equal to the potential drop across NPN transistor 50 in the fully conducting state, i.e. VCE. Thus, there are described several embodiments for either CMOS or BiCMOS implementation, including an improved switching circuit which uses a gate enhanced lateral PNP device as a merged bipolar and FET device. In switching the gate connection of the PNP device with a base switching signal, it is possible to derive the benefits of high current switching capability of a bipolar device with a zero voltage drop across the fully conducting merged FET device. Many logic circuits may include the basic implementation of the CMOS inverter as shown in Figure 3 by using the standard knowledge of a person skilled in the art. This has been shown in Figure 4 which illustrates how the inverter may be used to implement standard logic circuitry. The foregoing preferred embodiments were described with respect to gate enhanced lateral PNP devices. However, it should also be appreciated that such arrangements may be implemented in SOI technology. A gate enhanced lateral PNP transistor, in this technology, is shown generally in Figure 5. In this Figure, there is a bottom insulator 68 and a deep trench oxide 69 for device isolation, and a shallow trench oxide 70 for junction isolation. This implementation has a smaller base region and reduced parasitic PNP components. Base charge is minimized and downward or parasitic injection from the emitter is also suppressed. For a retrograde N substrate, the vertical injection is suppressed further and extrinsic base resistance is low. As a consequence, the device would have a lateral PNP current gain and frequency characteristics better than that implemented according to the previously described CMOS implemented devices. The use of a gate enhanced lateral NPN transistor may also be possible in accordance with the invention. Recent developments suggest that N doped substrates may form the basis of a lateral transistor having a P well. Such P well devices would permit the implementation of an insulated gate between collector and emitter N doped regions. These devices may therefore be utilized in applications which are analogous to the foregoing PNP implemented circuits.

Claims: An integrated MOS circuit comprising: at least one logic signal input-electrode (29), a gate enhanced lateral bipolar transistor (Fig. 1A) comprising a base electrode (17), a emitter electrode (20), a collector electrode (16), and a gate electrode (19), said emitter electrode (20) and said collector electrode (16) being separated by said gate electrode (19) defining the width of the base (14) of said gate enhanced lateral bipolar transistor (31 in Fig. 2), and a first MOS switching means (33) for connecting said base electrode and said collector electrode of said gate enhanced lateral bipolar transistor (31) in response to a first logic signal applied to said logic signal input-electrode (29), whereby a turn-on biasing signal is also present at said gate electrode of said gate enhanced lateral bipolar transistor (31) in response to said first logic signal applied to said logic signal input-electrode (29). The integrated MOS circuit of claim 1 further comprising: a second MOS switching means (32) for connecting said base electrode and said emitter electrode of said gate enhanced lateral bipolar transistor (31) in response to a second logic signal applied to said logic signal input-electrode (29), wherein said second logic signal is inverse to said first logic signal. The integrated MOS circuit of claim 1 or 2, wherein said gate enhanced lateral bipolar transistor is a pnp transistor (31), the emitter electrode of said pnp transistor (31) is connected to a supply potential electrode (Vdd) and the collector electrode of said pnp transistor (31) is connected to a load device (LOAD), and said first MOS switching means (33) is a first p-channel field effect transistor (first PFET, 33), said first PFET (33) being connected between said base electrode and said collector electrode of said pnp transistor (31), and said first PFET (33) having a gate electrode connected to said logic signal input-electrode (29). The integrated MOS circuit of claim 2 or 3, wherein said second MOS switching means is a second p-channel field effect transistor (second PFET, 32), said second PFET (32) being connected between said base electrode and said emitter electrode of said pnp transistor (31), and said second PFET (32) having a gate electrode connected to said collector electrode of said pnp transistor (31). The integrated MOS circuit of any one of claims 1 to 4, further comprising: a third MOS switching means (34) for connecting said collector of said gate enhanced lateral bipolar transistor (31) to a common potential electrode (Vss) in response to said second logic signal applied to said logic signal input-electrode (29). The integrated MOS circuit of claim 5, wherein said third MOS switching means is a first n-channel field effect transistor (first NFET, 34), said first NFET (34) being connected between said collector electrode of said gate enhanced lateral bipolar transistor (31) and said common potential electrode (Vss), and said first NFET (34) having a gate electrode connected to said logic signal input-electrode (29). The integrated MOS circuit of any one of claims 1 to 4, further comprising: a bipolar transistor (43) for connecting the collector electrode of said gate enhanced lateral bipolar transistor (38 in Fig.3) to a common potential electrode (Vss) in response to said second logic signal applied to said logic signal input-electrode (37 in Fig. 3). The integrated MOS circuit of claim 7, further comprising: a fourth MOS switching means (42) for connecting base and collector electrodes of said bipolar transistor (43) in response to said second logic signal applied to said logic signal input-electrode (37), and a fifth MOS switching means (44) for connecting base and emitter electrodes of said bipolar transistor (43) in response to said first logic signal applied to said logic signal input-electrode (37). The integrated MOS circuit of claim 8, wherein said bipolar transistor is a npn transistor (43), the collector electrode of said npn transistor (43) is connected to the collector electrode of said gate enhanced lateral bipolar transistor (38) forming a common collector electrode (39), the emitter electrode of said npn transistor (43) is connected to said common potential electrode (Vss), and the base electrode of said npn transistor (43) is connected to a common electrode of said fourth and fifth MOS switching means (42, 44). The integrated MOS circuit of claim 8 or 9, wherein said fourth MOS switching means is a second n-channel field effect transistor (second NFET, 42), said second NFET (42) being connected between collector and base electrodes of said bipolar transistor (43), and said second NFET (42) having a gate electrode connected to said logic signal input-electrode (37), said fifth MOS switching means (44) is a third n-channel field effect transistor (third NFET, 44), said third NFET (44) being connected between the base electrode of said bipolar transistor (43) and said common potential electrode (Vss), and said third NFET (44) having a gate electrode connected to said common collector electrode (39) of said bipolar transistor (43) and said gate enhanced lateral bipolar transistor (38).

Inventors: CHEN CHIH-LIANG, DHONG SANG HOO, SHIN HYUN JONG, CHEN, CHIH-LIANG, DHONG, SANG HOO, SHIN, HYUN JONG
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: H03K17
IPC codes: H01L21, H03K19, H01L29, H01L27, H03K17