Circuit for testability

Abstract: Disclosed is a circuit for testability which is incorporated in a system LSI comprising a plurality of master modules (1 and 2) and a plurality of slave modules (4 and 5), a common bus (40) for connecting the master modules (1 and 2) and the slave modules (4 and 5), and a bus arbiter (3) for adjusting use of the common bus (40), comprises: tri-state buffers (15 and 16) and control lines for prohibiting transmission of an acknowledgement signal to be transmitted from the bus arbiter (3) to a master module (1) to be tested among the plurality of master modules (1 and 2) in a test mode, which input an acknowledgement signal generated from the master module (1), and which output it to the slave modules (4 and 5); an AND gate (17) for masking acknowledgement signals to be transmitted from the bus arbiter (3) to master modules (2) other than the master module (1) to be tested; a test I/O bus (comprising control lines and data lines) for carrying out Initial setting to a memory portion (22, 26, and 28) in the master module (1) to be tested, and reading data stored in the memory portion (22, 26, and 28); and an ordinary operation control line for setting the master module (1) and the slave modules (4 and 5) into an ordinary operation mode.

Description: 1.Field of the Invention The present invention relates to a circuit for testability provided in a system LSI, and particularly to construction of a circuit for testability provided in a system LSI so constructed that a plurality of master modules access a plurality of slave modules thereof. 2.Description of the Prior Art When an operation test of a system LSI which is so constructed that a plurality of master modules, for example, Central Processing Units (CPU) or Direct Access Memory Controllers (DMAC) are connected with common bus to access a plurality of slave modules is carried out, it is necessary to set or read test data to each slave module (for example, a RAM as a memory element) which is dependent on each of the master modules. Conventionally, a parallel scan method or a serial scan method is used as a method of testability on logic circuits. Generally, in the parallel scan method, addresses of respective modules, for example memory circuits, in a logic circuit are selected as test data so as to carry out the operation test of the logic circuits. However, in such a method, a circuit for testability (for example, address buses, data buses, and selectors only used for the operation tests) must be provided to each of the modules. The scale of the system LSI therefore is inevitably increased. On the other hand, the serial scan method is used for operation tests of, for example, F/F and the like in the master modules. In this method, the number of circuits for the operation tests is smaller than that of the parallel scan method, however, the test time is longer than that of the other method. This problem becomes remarkable as the integration degree of LSI becomes large. In the light of efficiency of the test time, the parallel scan method is superior to the serial scan method. To the contrary, the parallel scan method is inferior to the serial scan method in that the former method requires a test circuit with a larger scale than that of the latter. SUMMARY OF THE INVENTION It is an object to provide a circuit for testability provided in a system LSI, having a relatively small circuit scale, and able to carry out operation tests with high efficiency. To achieve the above object, the circuit for testability according to the present invention is provided in a system LSI having the features of claim 1. Preferred embodiments are listed in the dependent claims. Namely, the circuit for testability according to the present invention, the transmission of acknowledgement signals from the adjusting means to the first master module is prohibited in the test mode. Then, the acknowledgement signals to be transmitted from the adjusting means to the master modules other than the first master module are masked by the mask means. Thereafter, the initial setting of test data to the memory portion in the first master module is carried out through the input-output means. Next, the system is operated by the ordinary operation means so as to set or read the test data to or from the slave modules. Thereby, the test of writing operation is finished completely. In addition, in the test of reading operation, the system is again in the test mode, and then the data stored in the slave modules is read out to finish the reading operation. Accordingly, since the circuit for testability of the present invention can be realized in a small-scale construction, it becomes possible to suppress increase of a circuit scale of a system LSI constructed with a plurality of master modules and a plurality of slave modules and reduce the period of test operation. Thus, it becomes possible to carry out tests with high efficiency. These and other objects, feature and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a schematic constructional diagram of a system LSI having a plurality of logic circuits, Fig.2 is a schematic constructional diagram to show a case where a test facilitating circuit of the present invention is provided in the system LSI shown in Fig. 1, Fig.3A is a flow chart to explain a writing operation of the circuit for testability in a test mode of the system LSI shown in Fig.2, and Fig. 3B is a flow chart to explain a reading operation of the circuit for testability in a test mode of the system LSI shown in Fig. 2. DETAILED DESCRIPTION OF THE EMBODIMENT Hereinafter, a preferred embodiment of a circuit for testability according to the present invention will be explained with reference to the drawings. Incidentally, in the embodiment, construction of logic circuits as an example of a system LSI is explained. Fig.1 shows a schematic constructional diagram of the system LSI having a plurality of logic circuits. The circuit for testability is not incorporated in the system LSI. In the same drawing, reference numerals 1 and 2 show a first and a second master module, 3 shows a bus arbiter as adjusting means for deciding which of the master modules 1 and 2 uses a common bus 40, further 4 and 5 show slave modules. For example, with respect to operation of the master module 1, when a request signal REQ1 is outputted from the master module 1 to the bus arbiter 3, the bus arbiter 3 outputs a acknowledgement signal ACK1 to the master module 1. Next, the master module 1 starts its ordinary input/output operation of data to the slave module 4 through the common bus 40. While, with respect to operation of the master module 2, when a request signal REQ2 is given from the master module 2 to the bus arbiter 3, the bus arbiter 3 outputs an acknowledgement signal ACK2 to the master module 2. Then, the master module 2 starts its ordinary input/output operation of data to the slave module 5 through the common bus 40. Next, an embodiment of a circuit for testability of according to the present invention will be described. Incidentally, to simplify the explanation, a case where the test facilitating circuit of the present invention is incorporated in the system LSI comprising a plurality of logic circuits as shown in Fig.1 is described. As described in the following explanation, it should be clearly understood that this case as shown in Fig.2 fully includes the essential constructional elements of the present invention. Fig.2 is a constructional diagram to show a case where the test facilitating circuit of an embodiment of the present invention is incorporated in the system LSI shown in Fig.1. In Fig. 2, reference numerals 1 and 2 respectively show a first and a second master module, for example CPU or DMAC. 3 shows a bus arbiter as adjusting means for deciding which of the master modules 1 and 2 uses common buses 40. Further, 4 and 5 are slave modules, for example RAM. In the slave modules 4 and 5, memory portions 4a and 4b for storing data are incorporated. While, in the master module 1, there are a state machine 20 and a bus interface 24 as a memory portion. The state machine 20 includes an instruction register (IR) 22 for storing instruction. While, the bus interface 24 includes a data register (DR) 26 and an address register (AR) 28. Namely, as the memory portion in the master module 1, IR22, DR26 and AR28 are provided. In such a logic circuit having the above-mentioned construction, the circuit for testability of the embodiment having such construction as described below is provided. Namely, as one of essential elements of the test facilitating circuit, a test mode control line LT for switching the operation mode of the logic circuit into a test mode is connected to the state machine 20 in the first master module 1 through an inverter 11 and an OR circuit 10. While, an ordinary operation mode control line LS for switching the operation mode of the logic circuit into an ordinary operation mode is connected to the state machine 20 in the first master module 1 through the OR circuit 10. Furthermore, a tri-state buffer 16 for stopping transmission of acknowledgement signals to be transmitted from the bus arbiter 3 to the master module 1 on the test mode is provided in the course of a control line LACK1. The tri-state buffer 16 is subjected to tri-state control through an inverter 12 on the test mode. The output side of a tri-state buffer 15 for controlling transmission of signals from the master module 1 to the slave modules 1 and 2 is connected to the control line LACK1. Accordingly, on the test mode, an acknowledgement signal is given from the master module 1, then transmitted to an input terminal of acknowledgement signals of the memory portion 4a through the tri-state buffer 15, the control line LACK1, and a control line L2, and also transmitted to an input terminal of acknowledgement signals of the memory portion 5a through the control line L2, a selector 14 and a control line L3. Incidentally, operation of the selector 14 is controlled by an inverter 13. Namely, on the test mode, the selector 14 selects an acknowledgement signal from the master module 1. On the ordinary mode, the selector 14 selects an acknowledgement signal from the bus arbiter 3, and outputs the signal to the slave module 5. Moreover, operation of an AND gate 17 is controlled by the inverter 13. On the test mode, the acknowledgement signal given from the bus arbiter 3 is masked by the AND gate under control of the inverter 13, so that the signal is not transmitted to the master module 2. Namely, in the embodiment, the acknowledgement means comprises the tri-state buffers 15 and 16, the inverter 12 and the selector 14. The mask means is made up of the AND gate 17 and the inverter 13. Moreover, the input-output means comprises a test I/O bus L1. Furthermore, the switching means for switching ordinary operation and test operation comprises the ordinary control line LS, inverter 11, test mode control line LT and OR circuit 10. Next, a procedure of the test operation in the circuit for testability of the embodiment having the above-mentioned construction is explained. Figs.3a and 3b are flow charts to respectively show the test operation procedure. Namely, Fig.3a is a flow chart to show a writing operation to the memory portions 4a and 5a, and Fig.3b is a flow chart to show a reading operation from the memory portions 4a and 5a. First, a data write test to the memory portions 4a and 5a is described. In the test mode control line LT, a TMOD is set at the level 1. At the time, an SICLK is at the level 0. As the result, the ordinary operation in the logic circuit is stopped and the operation mode is changed into the test mode. In the test mode, the tri-state buffer 16, AND gate 17, selector 14 and master module 2 are in the test mode respectively through the tri-state buffer 15, and inverters 12 and 13. The master module 1 is set to the test mode through the inverter 11 and OR gate 10. Moreover, the slave modules 4 and 5 are in the test mode respectively by inputting acknowledgement signals outputted from the master module 1 through the control lines L2 and L3. Moreover, the transmission of acknowledgement signals from the bus arbiter 3 to the first master module 1 is prohibited by the tri-state buffer 16. Furthermore, the acknowledgement signal to be transmitted from the bus arbiter 3 to other master modules than the master module 1, that is, the master module 2 in this embodiment, is masked by the AND gate 17 (Step S1). In this situation, common bus control data (write instructions to the common bus 40) is set to the IR22 through the test I/O control line L1 (Step S2). Then, addresses of the memory portions 4a and 5a in the slave modules 4 and 5 are written in the AR28 through the test I/O control line L1 (Step S3). Subsequently, data are written into the DR26 through the test I/O control line L1 (Step S4). Finally, the SICLK is set at the level 1 through the ordinary operation control line LS. As the result, the master module 1 and the memory portions 4a, 5a of the slave modules 4, 5 are respectively set in the ordinary operation mode, and acknowledgement signals are transmitted to the memory portions 4a and 5a through the tri-state buffer 15, control lines LACK1, and L2, selector 14 and control line L3. Thereafter, the test data in the DR26 are written in the memory portion designated by the address value written in the AR28 through the common buses 40. Then, the write test is ended (Step S5). Next, a data read test from the memory portions 4a and 5a will be explained. The TMOD is set at the level 1 through the test mode control line LT so as to set the test operation mode. As the result, the ordinary operation is stopped. Since the operation is the same as the write test mentioned above, the explanation is omitted here (Step S10). Then, common bus control data (read instructions from the common buses 40) are set to the IR22 through the I/O control line L1 (Step S11). Thereafter, the address of the data to be read out stored in the memory portion 4a or 5a are set in the AR28 through the test I/O control line L1 (Step S12). Next, the SICLK is set at the level 1 through the ordinary operation control line LS. Then, the memory portion designated by the address held in the AR28 is set in the ordinary operation mode. As the result, the data of the memory portion designated by the address in the AR28 are read in the DR26 through the common bus 40 (Step S13). Finally, the data of the DR26 are read from the test I/O control line L1. Then, the read test operation is ended (Step S14). In such a manner, the test mode operation is completed. Namely, according to this embodiment, in a logic circuit constructed by the plurality of master modules and the plurality of the slave modules, since it becomes possible to provide a circuit for testability to each of the master modules and the slave modules operated thereby. Accordingly, the construction of the logic circuit can be simplified as compared with the conventional art where the circuit for testability should be provided to every module. Moreover, with respect to the test operation, since the input-output of test data is carried out only with the master module 1 as the center, high efficiency of the operation can be realized. Furthermore, in this embodiment, a logic circuit as a system LSI is described, however, it is also applicable to multi-processor systems having a common bus and pipeline operation systems for carrying out matrix operations. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A circuit for testability incorporated in a system LSI having at least two master modules (1, 2) including a state machine, a plurality of slave modules (4, 5) to be tested including a memory portion, a common bus (40) for connecting the master modules (1, 2) with the slave modules (4, 5) and bus arbitration means (3) for adjusting use of the common bus (40), comprising: test mode setting means (12, 14, 15, 16) for prohibiting transmission of an acknowlegdement signal to be transmitted from the bus arbitration means (3) to a first master module (1) which controls a test operation in a test mode, inputting an acknowledgement signal generated from the first master module (1) to itself and to the slave modules (4, 5) in the test mode; mask means (13, 17) for masking the acknowledgement signal to be transmitted from the bus arbitration means (3) to at least another master module (2) other than the first master module (1) in the test mode; input-output means (L1) for carrying out inital setting to a memory portion (22, 26, 28) in the first master module (1) and reading data of the memory portion (22, 26, 28) in the test mode; and ordinary operation means (10, 11, L S , L T ) for setting the first master module (1) and the slave modules (4, 5) in an ordinary operation mode. A circuit for testability according to claim 1, wherein the test mode setting means (12, 14, 15, 16) comprises two tri-state buffers (15, 16) provided between the bus arbitration means (3) and the first master module (1), and a selector (14), one (15) of the tri-state buffers (15, 16) stops acknowledgement signals generated from the bus arbitration means (3) to the first master module (1) on the test mode, the other tri-state buffer (16) outputs said acknowledgement signal generated from the first master module (1) to itself and to the slave modules (4, 5) through the selector (14) in the test mode. A circuit for testability according to claim 1, wherein the mask means (13, 17) comprises an AND gate (17), the input terminals of the AND gate (17) are connected to a control line (L T ) for transmitting a state of the test mode and a control line for transmitting the acknowlegement signal outputted from the bus arbitration means (3) to the at least another master module (2), and the output terminal of the AND gate (17) is connected to the at least second master module (2) other than the first master module (1). A circuit for testability according to claim 1, wherein the ordinary operation means (10, 11, L S , L T ) comprise an ordinary operation mode control line (L S ) for designating start of an ordinary operation mode, and a line for inputting an inversion level of a test mode control line (L T ) inverted by an inverter (11) for designating start of the test mode, said lines being connected to an input of an OR gate (10). A circuit for testability according to claim 1, wherein said bus arbitration means (3) receives request signals (REQ1, REQ2) to request the use of the common bus (40) transferred from the first master module (1) and the at least second master module (2) and outputs said acknowledgement signal (ACK1, ACK2) to permit the use of the common bus (40) in the normal operation mode. A method for testing an LSI system according to claim 1, comprising the steps of: setting a test mode to an active level; allowing only the first master module (1) from among the master modules (1, 2) to use the common bus (40) by disabling acknowlegement signals (ACK1, ACK2) orignating in the arbitration means (3); supplying an acknowledgement signal generated from the first master module (1) to itself and the slave modules (4, 5); writing common bus control and address and data for the slave modules to a memory portion (22, 26, 28) of the first master module (1) via the input output means (L1); setting the first master module (1) and the slave modules (4, 5) into an ordinary operation mode; and testing the slave modules by writing and reading the slave modules from the first master module.

Inventors: YAGUCHI TOSHIYUKI, YAGUCHI, TOSHIYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F11
IPC codes: G11C29, G01R31, G06F11, H01L21, H01L27