CONTROL SYSTEM FOR ENCODING IMAGE

Abstract: A control system for encoding image which comprises an orthogonal conversion encoder (10) that effects the orthogonal conversion encoding for every block obtained by dividing a screen of input image signals into a plurality of blocks, an encode controller (14) output from the variable-length conversion encoder for every block, the variable-length encoder (12) that converts the conversion coefficient output from said encode controller into a variable-length encoded word for every block, and a buffer memory (13) that temporarily stores the variable-length encoded word output from said variable-length encoder for every block, and wherein the conversion coefficient is so controlled that the variable-length encoded word obtained for every block becomes smaller than a predetermined number.

Description: TECHNICAL FIELD The present invention relates to an image encoding control system which efficiently encodes an input image signal. In order to reduce the bit rate of an image signal of a dynamic image or the like, a highly efficient encoding method is known which carries out an orthogonal transform encoding for each block obtained by dividing one picture plane into a plurality of blocks. There is a need to reduce the size of a circuit which implements such a highly efficient encoding method. BACKGROUND ART FIG.1 is a block diagram showing an essential part of a conventional art. An image signal related to a dynamic image is applied to an orthogonal transform encoder 1. The orthogonal transform encoder 1 can be configured based on a Fourier transform, Hadamard transform, discrete cosine transform (DCT) or the like, and can also be configured based on a combination of a predictive encoding, such as an interframe encoding, and one of the above-mentioned transform procedures. Recently, the encoding structure based on the discrete cosine transform has been practically used. A processing block subjected to the orthogonal transform encoding has a size which consists of 8 - 16 pixels in one dimension, and a size which consists of 8 x 8 - 16 x 16 pixels in two dimensions. The image signal is subjected to the orthogonal transform encoding in the processing block unit by the orthogonal transform encoder 1. An encoded signal is input to a variable-length encoder 2, which converts the encoded signal into a variable-length code in which a short-length code is assigned to a signal having a high occurrence possibility. The variable-length codes are successively input to a buffer memory 3, which arranges them so that they have a data width equal to that of the buffer memory 3. Data read out from the buffer memory 3 is sent to a transmission line. On the receiving side of the variable-length code signal, the variable-length code is converted into a fixed length code by a variable-length decoder, and the original image signal is reproduced from the fixed length code by an orthogonal transform decoder which carries out a procedure reverse to the orthogonal transform encoding. In the above-mentioned conventional image encoding system, the orthogonal transform encoding is carried out in the processing block unit which consists of, for example, n x m pixels (where n and m are arbitrary numbers). Then, all effective coefficients other than transform coefficients of zero are converted into a variable-length code output by the variable-length encoder 2. Thus, it is necessary for the variable-length encoder 2 to have an ability to perform variable-length encoding of a maximum of n x m signals and arrange variable-length codes so that they have a data width equal to the data width of the buffer memory 3. As a result, it is necessary to use a large size variable-length encoder. Transform coefficients on the high-frequency component side obtained by the orthogonal transform encoding tend to become zero. From this point of view, it may be possible to process transform coefficients on the low-frequency component side in order to reduce the size of the variable-length encoder. However, in this case, the transform coefficients on the high-frequency components are completely lost. Thus, the quality of the reproduced image may deteriorate greatly. EP-A-0 414 074 is part of the state of the art only by virtue of Article 54(3) EPC. It shows a transform coding apparatus using quantization and run length coding processes. The number of consecutive zero coefficients is counted, and depending on how full the output buffer becomes, a threshold is set, which if exceeded, causes the value of the next non-zero coefficient to be made zero. There is no disclosure of counting significant coefficients rather than insignificant ones. US-A-4 922 273 shows altering the quantizing characteristics on the block base. However, there is no disclosure of intentionally setting coefficients to zero when a predetermined number of significant coefficients have been transmitted. IEEE Global Telecoms Conference, Nov. 1988, U.S.A., p. 997-1004 shows a system which also lacks this feature and does not show controlling the number of code words in a block. DISCLOSURE OF THE INVENTION An object of the present invention is to provide an image encoding control system in which the above-mentioned problems are eliminated. A more specific object of the present invention is to provide an image encoding control system which is capable of efficiently carrying out an encoding without deteriorating the encoding characteristics and which can be formed of a smaller-size circuit. The invention provides a system as set out in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a block diagram of a conventional image encoding control system; FIG.2 is a block diagram showing a primary structure of an image encoding control system according to the present invention; FIG.3 is a block diagram of an embodiment of the image encoding control system shown in FIG.2; FIG.4 is a block diagram showing the operation of a code controller shown in FIG.3 used in a case where a two-dimensional variable-length code is used; FIG.5A is a diagram showing a conventional image encoding procedure which is carried out when the two-dimensional variable-length code is used; FIG.5B is a diagram showing an image encoding procedure which is carried out when an image encoding procedure according to the present invention is used; FIG.6 is a diagram showing the operation of the code controller shown in FIG.4 which is carried out when the two-dimensional variable-length code is used; FIG.7 is a block diagram showing the structure of the variable-length encoder shown in FIG.3 used when the two-dimensional variable-length code is used; FIG.8 is a diagram showing the operation of a variable-length encoder shown in FIG.7; FIG.9A is a diagram showing the relationship between the input and output of a ROM shown in FIG.7; FIG.9B is a diagram showing the relationship between the input and output of an encoding table shown in FIG.7; FIG.10 is a block diagram of a rotator shown in FIG.7; FIG.11 is a diagram showing the structure of the encoding controller shown in FIG.3 used when a run-length code is used; FIG.12A is a diagram showing a conventional image encoding procedure carried out when the run-length code is used; FIG.12B is a diagram showing an image encoding procedure according to the present invention which is carried out when the run-length code is used; FIG.13 is a diagram showing the operation of a code controller shown in FIG.11; FIG.14 is a diagram showing the relationship between the input and output of a ROM shown in FIG.11; FIG.15 is a diagram showing the structure of the variable-length encoder used when the run-length code is used; FIG.16 is a diagram showing the relationship between the input and output of a ROM shown in FIG.15; FIG.17 is a diagram showing the operation of a variable-length encoder shown in FIG.15; FIG.18A is a diagram showing the relationship between the input and output of an encoding table shown in FIG.15 related to a string of zeros; FIG.18B is a diagram showing the relationship between the input and output of the encoding table shown in FIG.15 related to effective coefficients; FIG.19A is a block diagram of a conventional image encoding control system having a parallel structure; FIG.19B is a block diagram of an image encoding control system having a parallel structure according to a second embodiment of the present invention; FIG.20A is a block diagram of a transmission system having the conventional image encoding control system having the parallel structure shown in FIG.18A; FIG.20B is a block diagram of a transmission system having the image encoding control system having the parallel structure according to the second embodiment of the present invention shown in FIG.18B; FIG.21 is a block diagram of an image encoding control system according to a third embodiment of the present invention; FIG.22A is a diagram showing a problem which may occur in any of the first, second and third embodiments; FIG.22B is a diagram showing how to solve the problem shown in FIG.22A; and FIG.23 is a block diagram of an image encoding control system according to a fourth embodiment of the present invention. BEST MODE OF CARRYING OUT THE INVENTION The image coding control system according to the present invention controls the number of variable-length code word obtained in the block unit so that it is equal to or smaller than a predetermined number of variable length code words, and will now be described with reference to FIG.2. The image coding control system according to the present invention includes an orthogonal transform encoder 10, a variable-length encoder 12, a buffer memory 14 and a code controller 14. The orthogonal transform encoder 10 performs an orthogonal transform encoding for every block obtained by dividing one picture plane of an input image signal into blocks. The code controller 14 controls an output of the orthogonal transform encoder 10 so that the number of variable-length code words obtained in the block unit in the variable-length encoder 12 is equal to or smaller than a predetermined number of variable-length code words. The variable-length encoder 12 carries out a variable-length encoding for the output signal of the code controller 14 so that the length of the variable-length code becomes equal to the data width of the buffer memory 13. The buffer memory 13 temporarily stores the variable-length coding output generated by the variable-length encoder 12. The orthogonal transform encoding signal from the orthogonal transform encoder 10 is encoded by using a reproduced signal based on the output of the code controller 14. Normally, a plurality of effective coefficients are obtained for each processing block of the orthogonal transform encoder 10. The code controller 14 controls the output of the orthogonal transform encoder 10, that is, transform coefficients, so that the number of variable-length code words generated for each processing block by the variable-length encoder 12 becomes equal to or smaller than a predetermined number of variable-length code words. The above arrangement makes it possible for the variable-length encoder 12 to have an ability to process the predetermined number of variable-length code words, so that the size of the circuit realizing the variable-length encoder 12 can be reduced, as compared with the size of the conventional variable-length encoder. In addition, even if the number of low-frequency components obtained by the orthogonal transform encoding is smaller than that of high-frequency components, it is possible to process such high-frequency components and thus suppress a deterioration of the quality of reproduced images. FIG.3 is a block diagram showing the image encoding control system shown in FIG.2 in more detail. The image encoding control system shown in FIG.3 includes a discrete cosine transform (DCT) block 21, a subtracter 22, a quantizer 23, a code controller 24, a variable-length encoder 25, a buffer memory 26, a reverse quantizer 27, an adder 28, a frame memory 29 and a quantization controller 30. The orthogonal transform encoder 10 shown in FIG.2 is made up of the discrete cosine transform unit 21, the subtracter 22 which carries out an interframe encoding, the quantizer 23, the reverse quantizer 27, the adder 28 and the frame memory 29. The input image signal is subjected to the discrete cosine transforming for every processing block by the discrete cosine transform unit 21. The output of the discrete cosine transform unit 21 is input to the subtracter 22, which generates the difference between the transform coefficients of the block being processed and the transform coefficients of the previous block. The quantizer 23 quantizes the above-mentioned difference, and a quantized output is input to the code controller 24. The code controller 24 controls the quantized output received from the quantizer 23 for every block so that the number of variable-length code words generated by the variable-length encoder 25 becomes equal to or smaller than a predetermined number of words. It will be noted that the variable-length code words are classified into two-dimensional variable-length codes and run-length codes. The code controller 24 has different structures dependent on the types of variable-length code words. The structure of the code controller 24 will be described in detail later. The variable-length code output from the variable-length encoder 25 is temporarily stored in the buffer memory 26, and read out and sent to a transmission line by a means which will be described later. The quantization controller 30 monitors the buffer memory 26 to determine how much the buffer memory 26 has been filled with data, and controls quantizing steps of the quantizer 23 and the reverse quantizer 27 so that the buffer memory 26 is prevented from overflowing or underflowing. Control information about the quantizing steps is transmitted to the receiver side together with the variable-length code output. A reverse-quantized difference signal related to the transform coefficients, which is output by the reverse quantizer 27, is added to the content of the previous frame (block) by the adder 28, and the result of the addition is input to the frame memory 29. The content of the frame memory 29 is read out when the next frame is processed. FIG.4 is a block diagram showing the structure of the code controller 24 (first embodiment) using the two-dimensional variable-length codes. The code controller 24 includes a comparator 101, a counter 102, a comparator 103, a delay device 104 and a selector 105. The comparator 101 compares the quantized output (each transform coefficient) supplied from the quantizer 23 with zero, and outputs a signal (pulse signal) which indicates the up-count operation of the counter 102 when the quantized output is not zero. The counter 102 counts the pulse signals, each indicating the up-count operation, and is cleared by a block synchronizing signal which indicates the end of each block. That is, the counter 102 counts the pulse signals indicating the up-count operation for each block. The comparator 103 compares the count value in the counter 102 with a predetermined threshold value TH1, and outputs a select signal for making the selector 105 select zero when the count value in the counter 102 has become larger than the predetermined threshold value TH1. The delay device 104 delays the quantized output in order to synchronize the quantized output with the occurrence of the select signal. The selector selects zero during the time the select signal from the comparator 103 is being input, and selects the quantized output (transform coefficients) from the delay device 104 in cases other than the case where the select signal is being input to the selector 103. FIG.5A(a) shows a quantized output related to a block output by the quantizer 23 in a case where one block (obtained by dividing one picture plane) consists of 8 x 8 pixels. By zigzag scanning the 8x8 block shown in shown in FIG.5A(a), a combination (zero-run length, effective coefficient) forming the two-dimensional variable-length code is obtained. The first two-dimensional variable-length code is (5, 0) where 5 is the effective coefficient at the left top pixel of the block (D.C. component) and 0 is the number of consecutive zeros (zero-run). The next effective coefficient obtained by the zigzag scan is 7, and the zero-run length is equal to 10, so that two-dimensional variable-length code (10, 7) can be obtained. In the same way, (3, 2), (0, 5), (3, 2), (7, 15) and (10, 7) are obtained. All the high-frequency components after effective coefficient "7" are zero, and thus no two-dimensional variable-length code is generated. Variable-length code words shown in FIG.5A(b) related to the above-mentioned two-dimensional variable-length codes are obtained (EOB is an end-of-block signal indicating the end of the block and output in the state where the block synchronizing signal is active). FIG.5A relates to the conventional procedure. In the case shown in FIG.5A, seven variable-length code words are obtained. If it is statistically confirmed that the quality of an image reproduced by six variable-length code words (six effective coefficients) except for the EOB has a little deterioration, it is not necessary to transmit all the seven variable-length code words. The code controller 24 subjects the quantized output to a process which will be described below, so that the number of variable-length code words obtained for every block is equal to or smaller than a predetermined number of words (which can statistically ensure a little deterioration of the quality of the reproduced image). FIG.5B(a) shows the operation of the code controller 24 executed in the case where the number of variable-length code words is limited to six or smaller. The zigzag scan is carried out for the block shown in FIG.5A(a). When the number of effective coefficients has become equal to six, each effective coefficient following the sixth effective coefficient is replaced by zero, so that variable-length code words shown in FIG.5B(b) are obtained by the zigzag scan shown in FIG.5B(a). A description will now be given of the operation of the code controller shown in FIG.4 with reference to FIG.6. The quantized output shown in FIG.6(A) is input to the comparator 101. Data which is input to the comparator 101 for the first time is effective coefficient "5". In this case, the comparator 101 outputs the pulse signal which indicates the up-count operation. The counter 102 increments the count value by 1, so that the count value becomes 1 (before this operation, the counter 102 has been cleared by the EOB signal). Count value "1" is compared with the threshold value TH1 (for example, TH1 = 6) by the comparator 103. In this case, since the count value in the counter 102 is equal to 1, the comparator 103 does not output the select signal. Thus, the quantized output (effective coefficient "5") passes through the delay device 104 and the selector 105, and is input, as a code control output, to the variable-length encoder 25 (FIG.3) (FIG.6(B)). Next, "0" is input to the comparator 101. In this case, the comparator 101 does not generate the pulse signal. Thus, the count value in the counter 102 does not change and is equal to 1. After that, some zeros are successively input, and then effective coefficient "7" is input to the comparator 101. In this case, the counter 102 increments the count value by 1, so that it becomes equal to 2. In the same way, each time the effective coefficient is input, the count value in the counter 102 is incremented by 1. The comparator 103 outputs the select signal to the selector 105 when the count value in the counter 102 has become greater than six (TH1 = 6). In response to the select signal, the selector 105 selects "0" and outputs it. The selector 105 successively outputs "0" until the counter 102 is cleared by the block synchronizing signal (EOB signal) (FIG.6(B)). FIG.7 is a block diagram showing the structure of the variable-length encoder 25 shown in FIG.3 used when the two-dimensional variable codes are used. The variable-length encoder 25 includes a coefficient processing device 111, an encoding table 112 and a rotator 113. The coefficient processing device 111 includes a ROM 114, a delay device 115, a counter 116 and a memory 117. The ROM 114 outputs a write instruction signal which instructs the memory 117 to write data when the code control output from the code controller 24 is other than zero. When the code control output is zero, the ROM 114 instructs the counter 116 to increment its count value by 1. The delay device 115 delays the write instruction signal output from the ROM 114 in order to synchronize the operation. FIG.9A is a diagram showing the operation of the ROM 114. The block synchronizing signal and the code control signal are input to the ROM 114 as an address thereof, and outputs the write instruction signal and data to the counter 116. Symbol "*" means "don't care". The write instruction signal is a low active signal. Turning now to FIG.7, the memory 117 functions as a buffer, and inputs the block synchronizing signal, the count value (number of zeros) in the counter 116 and the effective coefficient when the write instruction signal is applied (it is low (0)). The encoding table 112 inputs the block synchronizing signal, the count value and the effective coefficient from the memory 117, and outputs a code length and a code word. FIG.9B is a diagram between the input and output of the encoding table 112. The last two bits of the code word, namely "10", obtained when the block synchronizing signal is zero (low level), form the EOB signal (the block signal maintained at the low level). Turning now to FIG.7, the rotator 113 generates a variable-length code output from the code word while referring to the code length obtained from the encoding table 112 in order to arrange the code words output from the encoding table 112 so that they have a data width of the buffer memory 26 (FIG.3). FIG.8 is a waveform diagram showing the operation of the variable-length encoder 25 which is carried out when the code control output shown in FIG.6(B) is input. The block synchronizing signal shown in FIG.8(A) becomes zero (EOB) at the end of one block. At this time, data shown in FIG.8(F) is written into the memory 117. As has been indicated, "*" means "don't care". First, code control output "5" is input to the ROM 114. At this time, the block synchronizing signal is equal to 1. Thus, as will be seen from FIG.9A, the low-active write instruction signal becomes "0", and the counter 116 is supplied with "0". Thus, as shown in FIG.8(F), the block synchronizing signal "1", count value "0" and effective coefficient "5" are written into the memory 117. After that, 10 zeros are successively input. The counter 116 increments its count value by 1 each time "0" is input starting from "0" subsequent to effective coefficient "5". When effective coefficient "7" is input to the ROM 114, it outputs the write instruction signal. The count value in the counter 116 obtained at this time is "10", which is written into the memory 117 together with block synchronizing signal "1" and effective coefficient "7". The above-mentioned write instruction signal is delayed by the delay device 115, and input to the counter 116. Thereby, the counter 116 is cleared. In the same way, subsequent data are written into the memory 117, as shown in FIG.8(F). The encoding table 112 refers to the table shown in FIG.9B, and outputs the code length and code word to the rotator 113. FIG.10 is a block diagram showing the structure of the rotator 113. The rotator 113 includes a shift circuit 121, an adder 122 and a delay device 123. The code length supplied from the encoding table 112 shown in FIG.7 is input to the adder 122. The output of the adder 122 is delayed by a unit time by the delay device 123, and added to the code length input thereto. When the result of the adding operation exceeds the predetermined data width of the buffer memory 26 (FIG.3), the adder 122 generates a carry. This carry is input to the buffer memory 26 as a write control signal. The code word from the encoding table 112 is shifted by the shift circuit 121 on the basis of the output signal of the delay device 123. The shifted code word is output to the buffer memory 26 as a variable-length code output. A description will now be given of the structures of the encode controller 24 and variable-length encoder 25 (second embodiment) used when the run-length codes are used. First, the structure of the encode controller 24 will be explained. FIG.11 is a block diagram showing the structure of the encode controller 24 used when the run-length codes are used. The encode controller 24 includes a ROM 131, a counter 132, a comparator 133, a delay device 134, a delay device 135 and a selector 136. The ROM 131 inputs a signal NZR which indicates whether or not the quantized output from the quantizer (FIG.3) and the quantized output which precedes the former quantized output by one coefficient are zero. When the quantized output is other than "0" or the beginning of a zero-run, the ROM 131 outputs a pulse signal which indicates the up-count operation to the counter 132. FIG.14 is a diagram showing the relationship between the input and output of the ROM 131. The signal NZR and the quantized output are input to the ROM 131 as an address, and sends respective outputs data to the counters 132 and 134. Turning now to FIG.11, each time the up-count operation is instructed, the counter 132 increments its count value by 1. The counter 132 is cleared by the block synchronizing signal. The comparator 133 compares the count value in the counter 132 with a predetermined threshold value TH2, and outputs a select signal to the selector 136 when the count value has become greater than the threshold value TH2. The threshold value TH2 is selected so that the number of variable-length code words obtained in the block unit becomes equal to or smaller than a predetermined number of words. The delay unit 134 is provided for synchronizing the entire operation. The delay device 134 is cleared by the block synchronizing signal, and outputs 1 (which means that the quantized output preceding by one coefficient is other than "0"). The delay device 135 is provided for synchronizing the quantized output with the select signal. The selector 136 selects "0" when the select signal is output, and selects the quantized output from the delay device 135 in other cases. The output of the selector 135 is input to the variable-length encoder 25 as the code control output. By zigzag scanning one block shown in FIG.12A(a), the effective coefficients and the numbers of consecutive zeros are obtained. In FIG.12A(b), 0 x 10 means that there are 10 consecutive zeros. According to the conventional method, all the effective coefficients and the number of zeros contained in each zero-run in one block are calculated, and the variable-length code words shown in FIG.12A(b) are obtained. On the other hand, according to the embodiment being considered, the number of quantized outputs becomes equal to or smaller than the predetermined number of quantized outputs due to the function of the encode controller 24. FIG.12B(a) shows the process carried out when the number of variable-length code outputs is limited to six or smaller. In this case, TH2 = 6. When the total number of effective coefficients and zero-runs becomes equal to six, each of the subsequent effective coefficients is set to zero. In the example shown in FIG.12B, each effective coefficient after effective coefficient "5" is omitted. FIG.13 is a diagram showing the operation of the encode controller 24 shown in FIG.11. When the ROM 131 inputs effective coefficient "5", it outputs the pulse signal indicating the up-count operation to the counter 132. Next, "0" is input to the ROM 131. This "0" is positioned at the beginning of a zero-run, and thus the ROM 131 outputs the pulse signal to the counter 132. In the above-mentioned way, each time the effective coefficient or "0" positioned at the beginning of the zero-run is input, the count value in the counter 132 is incremented by 1. When the count value in the counter 132 has become larger than the threshold value TH2, the comparator 133 outputs the select signal to the selector 136. In response to this select signal, the selector 136 successively outputs "0" until the block synchronizing signal is output. FIG.15 is a block diagram showing the structure of the variable-length encoder 25 used in the case where the run-length codes are used. The variable-length encoder 25 includes a coefficient processing device 141, an encoding table 142 and a rotator 143. The coefficient processing device 141 includes a delay device 144, a ROM 145, a counter 146, a delay device 148, a delay device 149, a memory 150 and a delay device 151. The ROM 145 inputs the block synchronizing signal, the code control output and the code control output preceding the former control output by one coefficient supplied from the delay device 144, and operates as follows. When the block synchronizing signal is low (EOB signal) or the code control output is other than "0", the counter 146 is cleared. When the output of the delay device 144 is other than "0", the output of the delay device 144 is "0" and the code control output is other than "0", or when the block synchronizing signal is low, the output of the ROM 145 instructs the writing of data into the memory 150 and outputs the select signal to the selector 149. FIG.16 is a diagram showing the above-mentioned operation of the ROM 145. After the counter 146 is supplied with the clear signal, the counter counts up its count value until the next clear signal is supplied thereto. The outputs of the delay devices 144 and 148 are input to the selector 149. The count value in the counter 146 indicates the number of zeros in the zero-run. In order to discriminate the number of zeros in the zero-run from any effective coefficient, the output of the delay device 148 is supplied to the selector 149 together with "0", and the output of the delay device 149 is supplied to the selector 149 together with "1". The selector selects the output of the delay device 148 (the number of zeros) together with "0" when there is no select signal (low level, "0"). On the other hand, when the select signal is output (high level, "1"), the selector 149 selects the output of the delay device 144 (effective coefficient) together with "1". The delay device 151 delays the block synchronizing signal and the write instruction signal in order to synchronize the entire operation. The memory 150 functions as a buffer, and inputs the block synchronizing signal from the delay device 151 and the output from the selector 149 in synchronism with the write instruction signal from the delay device 151. The encoding table 142 has an encoding table as shown in FIG.18A and FIG.18B. FIG.18A relates to the case wherein run-length codes are used. The encoding table 142 shown in FIG.18A inputs the block synchronizing signal and the output of the selector 149 as its address, and outputs a corresponding code length and code word. In this case, the output of the selector 149 is the output of the delay device 148 selected together with data "0" for use in the aforementioned discrimination. FIG.18B relates to the case where effective coefficients are used. The encoding table 142 shown in FIG.18B inputs the block synchronizing signal and the output of the selector 149 as its address, and outputs the code length and code word. In this case, the output of the selector 149 is the output of the delay device 144 selected together with data "1" for used in the above-mentioned discrimination. The rotator 143 has the same structure as the aforementioned rotator 113 (FIG.10), and generates the variable-length code output by shifting the code length on the basis of the code word, and generates a write control signal from the code length. FIG.17 is a timing chart showing the operation of the variable-length encoder 25 shown in FIG.15. FIG.17A and FIG.17B show the block synchronizing signal obtained on the output side of the delay device 151 and the write instruction signal. When code control output "5" is input to the ROM 145, the last coefficient (indicated by *) is written into the memory 141 together with data "1" for use in the data discrimination. Code control output "5" is delayed by a unit time by the delay device 144, and supplied to the selector 149 together with data "1" for use in the data discrimination. At this time, "0" subsequent to effective coefficient "5" is input to the ROM 145, and the count value in the counter 146 becomes "1". At this time, the low-active write instruction signal is supplied to the memory 150 from the delay device 151, and thus, the memory 150 inputs the output of the selector 149. At this time, the select signal is high, and thus, code control output "5" from the delay device 144 is written into the memory 150 together with discrimination data "1". Then, consecutive zeros are input to the ROM 145. Each time "0" is input, the count value in the counter 146 is incremented by +1. After ten consecutive zeros are input, code control output "7" is input to the ROM 145. At this time, the write instruction signal from the delay device 151 becomes active (low). The output of the delay device 148 obtained at this time is equal to 10, and the select signal is low. Thus, the output of the delay device 148, "10", selected together with discrimination data "0", is written into the memory 150. This "10" shows the number of consecutive zeros between effective coefficients "5" and "7". At the next timing, the write instruction signal is active, and the select signal changes from the low level to the high level. Thus, the output of the delay device 144, namely "7", is written into the memory 150 together with "1". As has been explained above, by providing the code controller 24, it is enough for the variable-length encoder 25 to have an ability to generate the predetermined number of variable-length code words. This advantage of the present invention will now be described with reference to FIGS.19A and 19B. FIG.19A is a block diagram of a conventional image encoder which transfers image data in an HDTV (High Definition Television). The following description related to a case where an analog image signal is digitized at a frequency of 64MHz. It is difficult to directly encode the 64MHz digital signal and generate variable-length encoding outputs in light of the processing speed. Thus, as shown in FIG.19A, the analog image signal is converted into a 64MHz digital signal by an A/D (analog-to-digital) converter 41, and the 64MHz digital signal is divided into four 16MHz digital signals by a demultiplexer 42. The four 16MHz digital signals are processed in parallel form. For this purpose, the image encoder shown in FIG.19A includes four source encoders 43a - 43d, a variable-length encoder having four systems, and four buffer memories 45a - 45d. Each of the buffer memories 45a - 45d is changed to a bit rate of a transmission path through a transmission path interface 46. Each of the source encoders 43a - 43d corresponds to the orthogonal transform encoder 1 shown in FIG.1. The variable-length encoder 44 includes four coefficient processing devices 47a - 47d, four encoding tables 48a - 48d, and four rotators 49a - 49d. As shown, in the conventional image encoding system, it is necessary to design the source encoders 43a - 43d and the variable-length encoders 44 so that they can process a 16MHz digital signal. This needs a large amount of hardware. On the other hand, the system can be configured as shown in FIG.19B when a maximum of 16 variable-length code words are used for the 8 x 8 block. The image encode control system shown in FIG.19B includes four source encoders 50a - 50d, four code controllers 51a - 51d, and a variable-length encoder 52. Each of the source encoders 50a - 50d corresponds to the variable-length encoder 10 shown in FIG.2, and the variable-length encoder 52 is composed of coefficient processing devices 54a - 54b, a single selector 55, a single encoding table 56 and a single rotator 57. Since it is enough to process 16 variable-length code words with respect to the 8 x 8 block, the output of each of the coefficient processing devices 54a - 54d is a digital signal having a frequency of 4MHz (= 16MHz/(64/16)). The selector 55 successively selects one of the coefficient processing devices 54a - 54d, and sends the output of the selected coefficient processing device to the encoding table 56. With this arrangement, it becomes possible to form the variable-length encoder 52 of the single selector 55, encoding table 56 and the rotator 57 and reduce the amount of hardware. Further, the present invention has an advantage in that it becomes possible to use a circuit in common for the transmission side and the reception side by time division. This will now be described with reference to FIGS.20A and 20B. FIG.20A is a block diagram of a conventional transmission/reception system. Although four systems are provided on the transmission side, as shown in FIG.19A, only one system is illustrated for the sake of simplicity, and each block on the transmission side is indicated by a reference numeral having no suffix shown in FIG.19A. Similarly, although four systems are provided on the reception side, only one system is illustrated. The reception-side system has a single transmission interface 61, four buffer memories 62 (only one of them is illustrated), a variable-length decoder 63, four source decoders 64 (only one of them is illustrated), and a D/A converter 65. The variable-length decoder 63 includes fourth rotators 66 (only one of them is illustrated), four decoding table 67 (only one of them is illustrated), and four coefficient processing devices 68 (only one of them is illustrated). FIG.20B is a block diagram of a transmission/reception system according to the present invention. Although the transmission/reception system includes four systems, as shown in FIG.19B, only one system is illustrated in FIG.20B for the sake of simplicity, and reference numerals having no suffixes are used. Further, the selector 55 in the variable-length encoder 52 is omitted. Similarly, one of the four systems on the reception side is illustrated. The reception system has the transmission interface 61, a single buffer memory 71, a variable-length decoder 73, four source decoders 74 (only one of them is illustrated), and the D/A converter 65. The variable-length decoder 73 has a single decoding table 77 and four coefficient processing devices 78 (only one of them is illustrated). A variable-length encoder/decoder common block (hereafter simply referred to as a common block) 72 is provided in common for the transmitter and the receiver. The common block 72 has a selector 75 and a rotator 76. The transmitter and receiver use the common block by time division. An output of the encoding table 56 of the transmitter is input to the rotator 76 through the selector 75. An output of the rotator 76 is applied to the buffer memory 53 of the transmitter through the selector 75. An output of the buffer memory 71 of the receiver is applied to the rotator 76 through the selector 75, and output of the rotator 76 is input to the decoding table 77 through the selector 75. In the above-mentioned way, the rotator 76 is used in common for the transmitter and the receiver, so that the scale of the entire transmission/reception system can be reduced. FIG.21 is a block diagram of an image encoding control system according to a third embodiment of the present invention. In FIG.21, those parts which are the same as those shown in FIG.3 are given the same reference numerals. The structure shown in FIG.21 is formed by adding a selector 80 to the structure shown in FIG.3. The selector 80 outputs either the output of the frame memory 29 or "0" in accordance with the select signal output by the comparator 103 (FIG.4) of the decode controller 24. While the select signal is not being output, the selector 80 selects the output of the frame memory 29. When the select signal is output, the selector 80 selects "0". FIG.22A is a diagram showing the operation of the structure shown in FIG.3, and FIG.22B is a diagram showing the operation of the structure shown in FIG.21. Dot areas of an X block shown in (a) of FIG.22A are inhibited from omitting transform coefficients (effective coefficients and "0") therefrom. That is, all the transform coefficients of the X block pass through the code controller 24 (FIG.3) without being omitted. In a subsequent X+1 block, only transform coefficients in an area A1 are allowed to pass through the code controller 24, and the remaining transform coefficients are omitted. In a subsequent X+2 block, only transform coefficients in an area A2 are allowed to pass through the code controller 24, and the remaining transform coefficients are omitted. The contents of the X block are output to the subtracter 22 via the frame memory 29, and the difference between the contents of the X block and X+1 block is calculated. Thus, the transform coefficients of the X block appear in an area of the X+1 block other than the area A1. Similarly, the area A2 of the X+2 block is partially affected by the transform coefficients of the X block, and the transform coefficients of the X block appear in an area of the X+2 block other has the area A2. Thus, the quality of the reproduced image will deteriorate. That is, the threshold values TH1 and TH2 used in the code controller 24 are set to small values, high-frequency components of some previous frames will remain in some subsequent frames. The selector 80 shown in FIG.21 is provided for overcoming the above-mentioned problem. As shown in (b) of FIG.22B, after the area A1 of the X+1 block is processed, the select signal output by the code controller 24 is applied to the selector 80. Thus, "0" is written into the area of the X+1 block other than the block A1 in place of the real transform coefficients of the X block. Thus, no high-frequency components of the previous block remain in the subsequent block. FIG.23 is a block diagram of an image encoding control system according to a fourth embodiment of the present invention. In FIG.23, those parts which are the same as those shown in the previous figures are given the same reference numerals. The embodiment shown in FIG.23 has an arrangement based on a predictive encoding having the orthogonal transforming function. The interframe difference between the image image signal and the content of the previous frame is calculated and subjected to the orthogonal transform encoding in processing block unit by the discrete cosine transform device 21. The output of the discrete cosine transform device 21 is quantized by the quantizer 23 and applied to the code controller 24, which sends a limited number of codes to the variable-length encoder not shown. In the embodiment being considered, a loop having the orthogonal transform is formed, and thus a reverse discrete cosine transform device 11A receiving the output signal of the reverse quantizer 27. The discrete cosine transform device 11A carries out a reverse discrete cosine transform encoding to the orthogonal transform codes output by the discrete cosine transform device 21. The output of the reverse cosine transform device 11A is added to the adder 28. The present invention is not limited to the embodiments described hereinbefore. The orthogonal transform encoder 21 may be formed of an encoder based on any of the orthogonal transform means, such as the Fourier transform and Hadamard transform, and may be combined with any of various predictive encoding means, such as an interframe encoding. Further, the aforementioned threshold values TH1 and TH2 can be selected on the basis of the size of the processing block and the type of the orthogonal transform means. INDUSTRIAL APPLICABILITY The present invention can be applied to a transfer system in which a large amount of image data is transferred, such as an HDTV, a TV congress and a TV telephone.

Claims: An image encoding control system comprising: orthogonal transform encoding means (10) for carrying out an orthogonal transform encoding for each block obtained by dividing one picture formed by an input image signal into a plurality of blocks, each said block including transform coefficients related to a plurality of pixels; and variable-length encoding means (12, 25) for converting said transform coefficients obtained for each block into variable-length code words; characterised by code control means (14,24) for processing said transform coefficients of each block in the order from low sequency to high sequency and transmitting said coefficients in said order, to said variable-length encoding means (12,25), until a predetermined number of significant coefficients has been transmitted so that a number of variable-length code words obtained for each block is equal to or smaller than a predetermined number of variable-length code words ; buffer memory means (13, 26) for temporarily storing said variable-length code words output by said variable-length encoding means for each block. An image encoding control system as claimed in claim 1, wherein said predetermined number of variable-length code words is smaller than a number of transform coefficients related to pixels in each block. An image encoding control system as claimed in claim 1, wherein said variable-length code words are two-dimensional variable-length codes, wherein said code control means comprises: count means (102) for counting a number of effective coefficients out of said transform coefficients for each block; comparing means (103) for comparing the number of effective coefficients counted by said count means with a predetermined threshold value; and select means (105), provided between said orthogonal transform encoding means and said variable-length encoding means, for selecting said transform coefficients output by said orthogonal transform encoding means when the number of effective coefficients is equal to or smaller than said predetermined threshold value and for selecting "0" when the number of effective coefficients exceeds said predetermined threshold value. An image encoding control system as claimed in claim 3, wherein said variable-length control means comprises: count means (116) for counting, for each block, a number of consecutive zeros out of said transform coefficients output by said code control means; and converting means (117) for generating said variable-length code words from said number of consecutive zeros and said effective coefficients output by said code control means. An image encoding control means as claimed in claim 1, wherein said variable-length code words are run-length codes, and wherein said code control means comprises: count means (132) for counting, for each block, a sum total of a number of effective coefficients out of said transform coefficients and a number of strings, each having consecutive zeros; comparing means (133) for comparing the sum total counted by said count means with a predetermined threshold value; and select means (136), provided between said orthogonal transform encoding means and said variable-length encoding means, for selecting said transform coefficients output by said orthogonal transform encoding means when the number of effective coefficients is equal to or smaller than said predetermined threshold value and for selecting "0" when the number of effective coefficients exceeds said predetermined threshold value. An image encoding control system as claimed in claim 5, wherein said variable-length encoding means comprises: count means (146) for counting, for each block, a number of consecutive zeros out of said transform coefficients output by said code control means; select means (149) for selecting, for each pixel, either the number of consecutive zeros counted by said count means or the effective coefficient output by said code control means; and converting means (142, 143) for generating said variable-length code words from the number of consecutive zeros or the effective coefficients selected by said select means for each pixel. An image encoding control system as claimed in claim 1, wherein: each of said transform coefficients is a residual signal between input image signals related to blocks of two consecutive frames; and said image encoding control system comprises quantizing means (23) for quantizing said residual signal and for outputting a quantization output corresponding to a corresponding one of said transform coefficients. An image encoding control system as claimed in claim 7, further comprising: reverse quantizing means (27) for reverse-quantizing, for each block, said transform coefficients supplied from said code control means and for generating a reverse-quantization output; frame memory means (29) for storing the reverse-quantization output related to a block which precedes a block being processed by said quantization means by one block; adding means (28) for adding the reverse-quantization output related to the block being processed and the reverse-quantization output related to the block preceding said block being processed by one block; and subtracting means (22) for obtaining a difference between the input image signal related to the block being processed and the reverse-quantization output related to the block preceding the block being processed by one block and for generating said residual signal. An image encoding control system as claimed in claim 8, further comprising select means (80) for selecting either the reverse-quantization output from the frame memory means or "0" and for outputting selected data to said adding means. An image encoding control as claimed in claim 8, wherein said variable-length code words are two-dimensional variable-length codes, wherein said code control means comprises: count means (102) for counting, for each block, a number of effective coefficients out of said transform coefficients; comparing means (103) for comparing the number of effective coefficients with a predetermined threshold value; and a selector (105) for selecting said transform coefficients output by said orthogonal transform encoding means when said number of effective coefficients is equal to or smaller than said predetermined threshold value and for selecting "0" when said number of effective coefficients exceeds said predetermined threshold value, and wherein said select means selects "0" when said selector selects "0", and selects the reverse-quantization output from said frame memory means when said selector selects the transform coefficients from said orthogonal transform encoding means. An image encoding control system as claimed in claim 8, wherein said variable-length code words are run-length codes, wherein said code control means comprises: count means (132) for counting, for each block, a sum total of a number of effective coefficients out of said transform coefficients and a number of strings, each having consecutive zeros; comparing means (133) for comparing said sum total counted by said count means with a predetermined threshold value; and select means (136), provided between said orthogonal transform encoding means and said variable-length encoding means, for selecting the reverse-quantization output from said frame memory means when said sum total is equal to or smaller than said predetermined threshold value and for selecting "0" when said sum total exceeds said predetermined threshold value. An image encoding control system as claimed in claim 8, wherein each of said blocks has n x n pixels (n is an arbitrary integer). An image encoding control system as claimed in claim 1, further comprises: subtracting means (22) for obtaining a difference between the input image signal being processed and the input image signal related to a block which precedes the block being processed by one block and for generating a residual signal supplied to said orthogonal transform encoding means; quantizing means (23) for quantizing an orthogonal-transform-encoded residual signal output by said orthogonal transform encoding means and for generating a quantization output corresponding to said transform coefficients; reverse-quantizing means (27) for reverse-quantizing, for each block, said transform coefficients output by said orthogonal transform encoding means and for generating a reverse-quantization output; reverse-orthogonal transform encoding means (11A) for reverse-orthogonally transforming said reverse-quantization output; adding means (28) for adding a reverse-orthogonally transformed code output related to the block being processed and a reverse-orthogonally transformed code output related to the block which precedes the block being considered by one block; and frame memory means (29) for storing an addition result from said adding means, said addition result read out from said frame memory means being a frame memory output supplied to said subtracting means. A divided image encoding control system comprising: means (41) for converting an analog image signal into a digital image signal; dividing means (42) for dividing said digital image signals into N (N is an arbitrary integer) input image signals by a time division, each of said N input image signals having a frequency lower than that of said digital image signal; N image encoding control systems according to claim 1 respectively provided for said N input image signals, select means (55) for selecting said data generated by said N coefficient processing means on a time-division base to thereby output a data string; converting means (56) for generating said variable-length code output from said data contained in said data strings; and buffer memory means (53) for temporarily storing said variable-length code output output by said converting means. An image encoding control system as claimed in claim 14, wherein said data defining said variable-length code output includes effective coefficients out of said transform coefficients and a number of consecutive zeros contained in said transform coefficients. An image encoding control system as claimed in claim 15, wherein said variable-length code words are two-dimensional variable-length codes; and wherein each of said N code control means comprises: count means (102) for counting, for each block, a number of effective coefficients out of said transform coefficients; comparing means (103) for comparing said number of effective coefficients with a predetermined threshold value; and select means (105), provided for said N orthogonal transform encoding means and said N code control means, for selecting said transform coefficients from said N orthogonal transform encoding means when said number of effective coefficients is equal to or smaller than said predetermined threshold value and for selecting "0" when said number of effective coefficients exceeds said predetermined threshold value. An image encoding control system as claimed in claim 14, wherein said variable-length code words are run-length codes, and each of said N code control means comprises: count means (132) for counting a sum total of a number of effective coefficients out of said transform coefficients and a number of strings, each having consecutive zeros; comparing means (133) for comparing said sum total with a predetermined threshold value; and select means (136), provided between said N orthogonal transform encoding means and said N code control means, for selecting said transform coefficients from said N orthogonal transform encoding means when said sum total is equal to or smaller than said predetermined threshold value and for selecting "0" when said sum total exceeds said predetermined threshold value. An image encoding control system as claimed in claim 3 or 5 or 16 or 17, wherein said predetermined threshold value is equal to said predetermined number of variable-length code words. An image encoding control system as claimed in claim 4 or 14, wherein said converting means comprises: memory means (56, 112) for having, as an address, the number of consecutive zeros and said effective coefficients and for storing code words and code lengths thereof corresponding to combinations of said number of consecutive zeros and said effective coefficients; and rotating means (57, 113) for generating said variable-length code outputs from said code words and code length thereof output from said memory means. An image encoding control system as claimed in claim 6 or 15, wherein said converting means comprises: memory means (142) for having a first table storing a code word and a code length corresponding to said number of consecutive zeros and for having a code word and a code length corresponding to the effective coefficient; and rotating means (143) for generating said variable-length code output from said code word and said code length output by said memory means. An image encoding control system as claimed in claim 19 or 20, wherein said rotating means is.used in common for a decoding side.

Inventors: HAMANO TAKASHI, MATSUDA KIICHI, SAKAI KIYOSHI, HAMANO, TAKASHI, MATSUDA, KIICHI, SAKAI, KIYOSHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H04N7
IPC codes: H04N7, H03M7, G06T9