Data processing system having dual arbiter for controlling access to a system bus

Abstract: Data processing system having dual arbiter for controlling access to a system bus, where two processors, each clocked by one of two timing signals having equal period but out phases of half a period, operate synchronously each to the other, but outphased of the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor, on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.

Description: The present invention relates to a data processing system having a dual arbiter for controlling access to a system bus. It is known that in modern data processing systems and in order to increase performance a plurality of processors is used. The processors have access to shared resources, for instance a working memory, through a system bus. In order to avoid conflicts and interference in system bus access, arbitration units are used. In case of concurrent bus access requests from a plurality of processors, the arbitration unit grants access to one processor at a time, on the basis of predetermined priority criteria. If the processors have the same features and functionality it is advisable that they receive the same access priority right. Therefore the arbitration unit operates according to a criteria known as "round robin". If a processor K among N ordered processor has just obtained access to the system bus, before granting access again to the same processor it is tested if processor K+1,...N. and 1,K-1 need access to the bus. If processor K+1 needs access to the bus, it receives access premission first. If processor K+1 does not need access to the bus, but processor K+2 does, then access is granted to processor K+2 and so on. If processor K needs again access to the bus, access is granted thereto only if no other processor needs access. In case of two processors competing for access to the bus the round robin criterion leads at the extreme, to the alternative granting of access to each of the two processors, neither of which is privileged. An arbitration unit which follows this criterion, may be, from a functional stand point of three kinds: 1) Sequential. The arbitration unit polls in timing sequence and according to a predetermined order the presence of access requests to the system bus, one at a time, with a scanning cycle which requires a long time. For this reason, this kind of approach is generally no more used. 2) Synchronous. The several processors operate in synchronism and are clocked by a periodical timing signal which defines operative cycles or time frames. The access requests from the several processors are generated at predetermined times with a predetermined leading or lagging as to the transitions of the timing signal. The arbitration unit, synchronously with the timing signal, samples the status of all the access requests and decides which of the processors has access right. The arbitration time comprises two parts: the time of decisional process required by the arbitration logic to grant one access since the sampling instant and the time elapsing from the generation of the access requests to the sampling instant. This kind of arbitration units has the disadvantage that the arbitration process is not started as soon as an access request is generated, but is deferred till a predetermined sampling instant, at which the status of the several access requests is stable. 3) Asynchronous. Even if the several processors may operate in synchronism, they generally works asynchronously from each to the other. Bus access requests are randomly generated at umpredictable time the one as to the others and to a possible periodic timing signal used by the arbitration unit. The arbitration unit may sample at high frequency the status of the several access requests. However, since they may change status at the sampling instant, they may cause instability in the sampling circuits. Therefore the decisional process must be delayed until the sampling circuits have taken a stable state. Examples of asynchronous arbitration units and a more detailed explainations of the problem faced with by such units may be found in COMPUTER DESIGN, Vol. 20, No. 6, June 1981, pages 149-155, Winchester, Ma, Us; AW BENTLEY "FPLA arbiter concepts adapts to application needs". In particular it is stressed that in order to avoid instability the synchronous requests must be latched first in a synchronizing register or sampling unit. Only once the register set up time has elapsed the requests are transferred to the arbitration logic (a gate array) in turn provided with an output latch register which is triggered by a clock with a further delay. Not dissimilar from this approach is the teaching provided by PATENT ABSTRACTS OF JAPAN, Vol. 13, No. 157 (P-857) [3505] 17th April 1989; & JP-A-63316153 where two asyncronous processors each having its own clock signal have access to a common bus by sending access request to an arbitration unit. The arbitration unit synchronizes the request of one of the processor to the clock of the other processor in order to perform arbitration and syncrhonizes the grant signal to the one processor clock or to the other processor clock. Another example is provided by PATENT ABSTRACTS OF JAPAN, Vol. 12, No. 259 (P-733) [3106] 21st July 1988, & JP-A-6347688 where a plurality of processors are divided in two sets, the processors in the same set being syncronous, the two sets being clocked at the same frequency byt with an 180° offset. An arbitration unit is clocked at twice the clock frequency of the sets. In this way access contention at each clock of the arbitration unit is reduced: only processors of the same set may compete in requesting access, because the processors of the other set have already raised their request at the previous clock or will raise their request at the next arbitration clock. Even in this case the arbitration must be performed by first latching in a sampling register (6) the possible access requests, and then allowing the arbitration logic (7) to take a stable state. The same problem occurs in those arbitration units where the sampling of the bus access request is performed as soon as an access request is detected. Other access requests, nearly simultaneous to the first one, may cause instability of the sampling circuits. The present invention overcomes this limitations, in case arbitration is to be performed between two processors and provides a data processing system having a dual arbiter for controlling access to a system bus where the arbitration time is reduced to the time required by the logical circuits for the decisional process, without need to wait for predetermined sampling instants or for circuit status stabilization. The dual arbiter of the invention grants access to the system bus (and to resources connected thereto) with an equitable criterion to either one of two processors which, in case of access competition, alternates in access to the system bus, with arbitration time reduced to a minimum, hence with an optimum exploitation of the shared resource formed by the system bus. According to the invention these advantages are achieved, in a system where the two processors operates in synchronous mode, on the basis of timing cycles equal for both processors, by the combination of a very simple arbitration unit and a timing unit which provides two timing signals of equal frequency but with an half period offset the one as to the other. In digital systems timing signals are roughly in form of square waves having either one or the other of two electrical/logical levels, corresponding to an asserted and deasserted logical state. The half period offset of the two timing signals implies that the asserted state of one timing signal is synchronous with the deasserted state of the timing signal. Even in case of non symmetrical timing signals where one phase has a longer duration than the other phase, the shorter phase of one timing signal will be time distinct and no time overlapped with the shorter phase of the other timing signal, whilst the longer phases will overlap at same extent. Each of the two signals is respectively used to clock the one and the other of the two processors so that they operate with a predetermined offset in the timing cycle and generate bus access requests in distinct, non overlapped phases of the two timing signals. In this way each of the access requests is asserted whem the access request signal of the other processor is in a stable state, being already asserted or deasserted. By this arrangement the arbitration unit may be implemented with very simple and fast logic gating circuits (conceptually a control gate for each of the processors) which have inputs for receiving bus access requests from the two processors, and which grant access to the processor which is first to request access. The logic operates as soon as an access request is asserted. In case of access competition, the arbitration leads automatically to access granting alternatively to the one and the other processor. The features and the advantages of the invention will appear more clearly from the following description of a preferred form of embodiment and from the enclosed drawings where: Figure 1 shows in timing diagram some signals exchanged by one processor with external units. Figure 2 shows in block diagram a preferred embodiment of data processing system having a dual arbiter for controlling access to a system bus, in accordance with the present invention. Figure 3 is a logic diagram of a preferred embodiment of dual arbiter for the system of Figure 2. For a better understanding of the invention the following description relates to an embodiment where the two processors which compete for access to a shared bus each comprise an integrated processor of the type 68030, manufactured by the US firm Motorola and well known to the man skilled in the art. This enables to limit the description of the processors to those aspects which are essential to the invention understanding. It is however clear that the invention may be used with other kinds of processors. Figure 1 shows in timing diagram the operation of the processors, with reference to the signal essential to the invention understanding. Microprocessor 68030 operates on the basis of machine timing cycles defined by a clock signal CK (diagram CK) which tipically has a period of 50 nsec. Each cycle comprises two equal duration phases, corresponding to an high level (or asserted state) of the clock signal and to a low level (or deasserted state) of the clock signal respectively. When the microprocessor has to perform external operations, for instance memory read/write operations, the operation is performed in a plurality of full timing cycles, with a minimum of three, which define six operative states S0,S1,S2,S3,S4,S5. States S0,S2,S4 correspond to the high level of clock signal CK, the other states to the low level of clock signal CK. When in state S0, the microprocessor outputs address and command signals which remain stable during all the subsequent states, tiil S5 included and are removed from the output in a following S0 state. During state S1 the microprocessor asserts a signal AS by dropping it at electrical level 0. As is a strobe and validation signal for the addresses and commands already output and remains asserted until state S5, during which it is deasserted. AS is the first usefull signal issued by the microprocessor indicating the activation of an external operation. Although the product specifications do not give any guarantee on the instant at which AS is asserted during state S1 and on the instant at which AS is deasserted (except indicating that AS is asserted or deasserted at least 3 nsec after the clock signal falling edge which immediately precedes) the assertion/deassertion of the signal occurs typically 10-15 nsec before the next following clock signal transition. In addition it is well known that the delay in assertion or deassertion of the signals relative to the clock signal transition immediately preceding, largely depends on the capacitive load which the signals have to drive. If the capacitive load is limited to few tens of pF it is possible to obtain the assertion and deassertion of signal AS (and other signals) 10 nsec at least before the transition of the next following clock signal. Signal AS may be used as enabling signal for address, command decoding operations and therefore for selecting resources and starting external operations. During states from S2 to S5 the microprocessor exchanges with external circuits other signals and data which are not relevant to the invention. If during state S2 the microprocessor receives a signal DSACK asserted, it will complete the external operation by deasserting AS during state S5. Otherwise the microprocessor enters anon operative, wait state lasting for one or more clock periods, until signal DSACK is received. Thereafter it enters state S3. Among signals generated during state S0 there is one which must be mentioned. It is signal RMC. If RMC is asserted, it indicates that a plurality of subsequent external operations must be performed in unseverable way, until signal RMC is deasserted. Thus if the processor has to perform a memory read operation followed by an unseverable write operation, it moves from state S0 to state S5 in order to perform the read operation, than from state S5 to state S0 and again from state S0 to state S5 in order to perform the write operation. During all these states signal RMC remains asserted even if signal AS may be deasserted during the intermediate states S5,S0. RMC is deasserted only in the state S0 which follows the last state S5. Having pointed out these features, it is very easy to understand the operation of the system which is the object of the present invention and which is shown in fig. 2. The system comprises two processors 1,2 or CPU1,CPU2, each consisting in a microprocessor MC 68030. The operation of the two processors is timed by an oscillator 3 which generates a signal CKO at a frequency of 40 MHz. This signal is input to a flip flop 4 which acts as a frequency divider and outputs, at its outputs Q and NQ, two square wave signals CK1,CK2 having a frequency of 20 MHz, the signals being in phase opposition. Here and in the following the letter N preceding the name of an element or a signal has the meaning of negation/inversion. CK1 and CK2 are used to respectively time processor 1 and processor 2. Therefore the two processors operate with cycles of equal duration but out of phase for a half period, so that an odd state (S1,S3,S5) of any one of the processors is synchronous with an even state (S0,S2,S4) of the other processor. Thus it may be said that operation of the two processor is synchronous, but with an half period offset. Processor 1 communicates with external units through an interface bus 5 and processor 2 communicates with external units through an interface bus 6. Through the interface bus, the two processors may exchange addresses, data, commands and signals (AS and RMC included) with external components. The two interface busses 5,6 are connected to a system bus 7 through bidirectional gates or "tranceivers" 8,9 respectively. A working memory 10, a register bank 11 and a decoder 12 are connected to the system bus. It is clear that within this architecture the CPU1, in order to have access to the memory 10 or to the register bank 11, has to put information on bus 5 and from there, on bus 7, through gates 8 and in competition with CP2, which in order to have access to memory 10, must put information on bus 6 and from there on bus 7, through gates 9. A dual arbitrator 13 resolves the conflicts between CPU1 and CPU2 and grants access to the CPUs in a mutually exclusive way. Dual arbiter 13 receives signals AS1,RMC1, generated by processor 1, from the bus 5, and signals AS2, RMC2, generated by processor 2, from bus 6. It outputs signals BE1,BE2 which respectively enable tranceivers 8,9. Transceivers 8,9 are normally open so as to insulate bus 5 and 6 from bus 7. If bus 7 is free, as soon as arbitrator 13 receives signal AS1 asserted, gates 8 are enabled for the whole time interval required to transfer information. This time interval is defined by the asserted duration of AS1, or, in case, by the asserted duration of RMC1. During this time interval the enabling of gates 9 is prevented, even if processor 2 asserts signal AS2. Therefore the external operation requested by processor 2 is held pending on bus 6 until system bus 7 is disconnected from bus 5. At this time signal AS2 is already present in input to arbitrator 13, which, before processor 1 can assert again a new access request (that is in state S1 of processor 1), enables gates 9 and prevents the enabling of gates 8 until completion of the operations between processor 2 and systems bus. Register bank 11 may be used as a fast memory and for interprocessor communication as well, by the known method of message mailboxing in selected memory areas and notification of message pending to the destination processor. For instance CPU1, after having stored a message for CPU2 in a "mailbox" of memory 10, may load a register in bank 11 with a predetermined information. Bank 11 outputs on a lead 14 a notification signal which is received by processor 2, through an interrupt input. In due time CPU2 may take in account the notification signal and by one or more memory access operation may read the message. Likewise CPU2 may notify CPU1 by means of bank 11 and a notification lead 15. These operations, unrelevant to the scope of the invention, are described together with a specific form of embodiment, in the European Patent Publication N. 0201020. Figure 3 shows a preferred embodiment for arbitrator 13. Arbitrator 13 comprises a fast PAL (Programmable Array Logic) 100, for instance the one manufactured by the US firm Monolithic Memories with code 16R4, and a fast flip flop 101. PAL 100 has a maximum signal propagation delay from input to output of 7,5 nsec. The minimum propagation delay is 3 nsec and the input capacitance is 5 pF. It is particularly suitable for obtaining, from processors such as 68030, very fast transitions of the output signals because, when driven by the processor outputs, it is seen by such outputs as a very small capacitive load. In this way when the two processors 1,2 are controlled with clock signals in phase opposition, a time interval of at least 10 nsec, if not more, is assured between transitions of signals AS1 and AS2. This interval suffices for the correct operation of the arbitrator. The circumstance that signals RMC1 and RMC2 are deasserted in a state other than S5, that is in state S0, causes a problem, as it will be seen later. This problem can be easily overcome and does not hamper the simplicity of the conceptual approach which is used. Pal 100 comprises a plurality of input drivers 16,17,18,19,20,21 each having inverting and non inverting output. The signals in output from the several drivers are distributed, through a plurality of connection columns, to a plurality of connection rows 22,23,24,25,26,27,28,29. By suitably programming the PAL, selective connections among rows and columns are formed. The connections are shown as dots located at the crossings. If a row is connected to more columns, it raises to a positive electrical level if all the columns to which it is connected are driven at positive level. Therefore any row and the columns connected thereto functionally perform as an AND gate. Rows from 22 to 25 are connected to the inputs of an OR gate 30 and rows from 26 to 29 are connected to the inputs of an OR gate 31. The output of gates 30,31 is respectively connected to the input of an inverting output driver 32,33 respectively. The output of drivers 32,33 is respectively connected to the PAL output terminal 34,35 and to the input of a feedback driver 36,37 each having inverting and non inverting output. The inverting and non inverting outputs of the feedback drivers are connected to selection columns, and through such columns, selectively to connection rows. The non inverting output of driver 18 is connected to the input of an OR gate 38, whose output is connected to the D input of a flip flop 39, clocked by the loading edge of a clock signal applied to the clock input. The non inverting output of driver 19 is connected to the clock input of flip flop 39. The inverting output of flip flop 39 is connected to the input of a feedback driver 40. A D type flip flop 101, external to PAL 100, receives signal RMC2, generated by processor 2, at the D input and signal CK2 at the clok input. Flip flop 101 outputs a signal RMC2D at the non inverting output Q. The input drivers from 16 to 21 of PAL 100 receive respectively at their input, and in the naming order, signals AS1,AS2,RMC1,CK1,RMC2D. Terminals 34,35 output signals BE1,BE2 respectively. BE1 and BE2 enable gates 8,9 respectively (Fig. 2). Keeping in mind what has been said with reference to figure 1 as to the timing of signals AS,RMC and as to the inversion of the logical level relative to the electrical one, and further considering the connections shown in figure 3, the operation of the dual arbitrator of figure 3 is readily apparent in its details. Row 22 generates the logical AND of signals NAS1.AS2.BE2=NBE1. It is therefore clear that if BE2 is deasserted (at electrical level 1), hence the gates 9 are disabled, and AS2 is deasserted too, the enabling signal BE1 becomes asserted with a maximum delay of 7 nsec as to the assertion of AS1, that is near the end of status S1 (of processor 1). Row 24 forms the logical AND of signals NAS1.NBE1=NBE1 and assures that once BE1 is asserted, it is not deasserted, even if AS2 is subsequently asserted, until the end of status S5 of processor 1. Row 23 forms the logical AND of signals NRMC1.NBE1=NBE1 and assures that in case of unseverable operation, once BE1 is asserted, it remains asserted until deassertion of RMC1. Completely equivalent is the function performed by rows 26,27,28 and by OR gate 31 in the generation of signal BE2 at terminal 35. It is clear that in the course of normal access operations to bus 7, the signals BE1,BE2 are deasserted at the end of status S5 of the related processor so that in the following S0 state (of the related processor) it is only the other processor which may assert or have already asserted its own AS signal. In case of unseverable operation the signal BE1, or BE2, is deasserted at the end of a new state S0 next following S5 (of the related processor. In this case a deadlock situation may occur. Assume that BE2 is deasserted at the end of state S0 of processor 2, this states S0 being synchronous with an odd state of processor 1 hence being possibly synchronous with state S1 of processor 1. In this case signal BE1 cannot be asserted during state S1 of processor 1, due to condition NBE2 false in the logical operation performed by row 22. Therefore the arbitration is performed at the beginning of state S2 (of processor 1) at which time however, even signal AS2 may be reasserted, which in turn prevents the assertion of BE1. This deadlock situation is removed by means of an auxiliary signal RMC2D which copies the state of signal RMC2 with a suitable delay. Whilst RMC2 is deasserted during state S0 (of processor 2) RMC2D is deasserted only with the clock transition between state S1 and state S2 (of processor 2). Row 25 performs the logical operation BE1=NAS1.BE2.NRMC2D and assures that processor 1 may take ownership of the bus 7 as soon as BE2 is deasserted, that is at the beginning of state S1 of processor 2 even if processor 2 attempts to have access to the bus by assertion of AS2. Row 29 performs a logical operation similar to the one performed by row 25, say BE2=NAS2.BE1.NRMC1D. It guarantees that processor 2 gets ownership over system bus, if requested by asserting AS2, at the end of an unseverable operation performed by processor 1. Signal RMC1D is generated by flip flop 39 internally to PAL 100. It is clear that the previous description is related to a preferred embodiment of the invention and that several changes can be made, depending on the processor and the working memory which are used. For instance in Fig. 2 access to the system bus 7 is granted to the one or the other processor based on signal AS which they assert. It is clear that other signals may be used. For instance the processors 1 and 2 may each have an external cache memory connected to bus 5,6 respectively, or a memory management unit MMU. In this case it is well known that access to a working memory is requested only in case of read/write operations resulting from a "cache miss" indication and only when the address generated by the memory management unit is available. Therefore the signal for requesting access to the system bus may result from the decoding of a plurality of signals present on the processor bus (for instance AS, and R/W, where R/W is a read/write signal) and others such as MISS from cache or PAS (Phisical Address Strobe) from MMU, provided the resulting access request, equivalent to AS is asserted and deasserted in a determined time phase. In this case, it may be given as certain that MISS and PAS will be generated in a state subsequent to S1 (usually S2) and any deadlock risk resulting from the late deassertion of signal RMC during state S0 is prevented The arbitrator of the invention is further compatible with other arbitration circuits of conventional nature so that its use is not limited to the case of data processing systems consistuted by two processors only. For instance it is known that microprocessor 68030 is provided with internal mechanism for arbitration of the interface bus. If the microprocessor receives, at a suitable input, an external signal BR (Bus Request) requesting access to the bus, it asserts as signal BG (Bus Grant) granting access to the bus after having completed possible external operations, hence not earlier than in state S0. Once BG is asserted and received by the external units the most prioritary external units (in case of plurality of external units) may have access to the bus. Figure 2 shows that in addition to CPU1,CPU2, there is a third processor IOP 50 (IOP for Input Output Processor) which controls peripheral units not shown but intended to be connected to the IOP interface bus 51. The IOP and peripheral units interface bus 50 is connected to the system bus 7 by means of bidirectional gates 52. It is further connected to the inputs of a decoder 53. The signals on bus 51 are decoded by decoder 53 to detect access requests to system bus 7 and to generate a corresponding request signal IOPR. This signal is forwarded, through a lead 55, to a conventional arbitration unit 54. When IOPR is asserted, the arbitration unit 54 asserts on a lead 56 a bus request signal BR and forwards it to processors 1,2. In due time the two processors answer by asserting signal BG1,BG2 respectively on leads 57,58. Leads 57,58 are connected to the input of an OR gate 59, which performs the role of logical operator AND on signals BG1,BG2 (at electrical level 0 when asserted) and outputs towards arbitrator 54 a signal BG asserted. On receipt of BG, the arbitrator 54 sends a signal BGACK on lead 60 to processors 1,2. Signal BGACK indicates that arbitrator 54 has taken ownership on the system bus. The same signal may be used to enable gates 52. Other possible changes may relate to the nature of the destination units connected to the system bus 7, such as memory 10. In the preceding description there is the implied assumption that memory 10 and register bank 11 operate asynchronously relative to CPU1 and CPU2. However it is possible to use destination units of synchronous type, which are synchronized every time with the processor which gets access to the system bus. In this case arbitrator 13 will have to provide through suitable logic circuits, either one or the other of signals CK1,CK2 to the units 10,11 and this in addition to the mutually exclusive enabling of gates 8,9.

Claims: Data processing system having dual arbiter for controlling access to a system bus (7), said system comprising a plurality of processors (1,2,50) connected to a system bus (7) for access to common resources (10,11), a timing unit (3,4) generating two periodic timing signals (CK1,CK2) having equal frequency but out of phase the one to the other, each period of said timing signals comprising two phases, one phase at low level, the other at high level, a phase at least of each one of said timing signals being time distinct and non overlapped to the phase at the same level of the other of said timing signals, a first (1) of said processors being clocked by one (CK1) of said periodic timing signals for generating a first signal (AS1) requesting access to said system bus (7) in said time distinct phase of said one periodic timing signal, a second (2) of said processors being clocked by the other (CK2) of said periodic timing signals for generating a second signal (AS2) requesting access to said system bus (7) in said time distinct phase of said other periodic timing signal, characterised in that it comprises: first logic gating means (16,17,22,30,32) having inputs for receiving said first access request signal (AS1) and said second access request signal (AS2) from said first (1) and second (2) processor and for further receiving from second logic gating means (16,17,26,31,36) a second bus access grant signal (BE2) granting access to said second processor (2), said first logic gating means asserting in output a first bus access grant signal (BE1) granting access to said first processor (1) in response to assertion of said first access request signal (AS1) if said second access request signal (AS2) and said second bus access grant signal (BE2) are deasserted, and second logic gating means (16,17,26,31,36) having inputs for receiving said first access request signal (AS1) and said second access request signal (AS2) from said first (1) and second (2) processor and for further receiving from said first logic gating means said first bus access gran signal (BE1) granting access to said first processor (1), said second logic granting means asserting in output a second bus access grant signal (BE2) granting access to said second processor (2) in response to assertion of said second access request signal (AS2) if said first access request signal (AS1) and said first bus access grant signal (BE1) are deasserted. Data processing system as in Claim, comprising at least a third processor (50) connected to said system bus (7), means (53) for generating a third signal (IOPR) requesting access to said system bus (7) by said third processor (50) and arbitration circuits (54,49) responsive to said third signal (IOPR) for requesting access (BR) to said system bus jointly to said first (1) and second processors (2) and for granting access to said third processor once permission (57,58) is received from both said first and second processor.

Inventors: BOZZETTI FABIO, GRASSI MAURIZIO, MANTELLINA CALOGERO, BOZZETTI, FABIO, GRASSI, MAURIZIO, MANTELLINA, CALOGERO
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS ITALIA S.P.A.
Application year: 1990
Main classification: G06F13
IPC codes: G06F13