Semiconductor light-emitting device

Abstract: A semiconductor light emitting device comprises a substrate, an n-type semiconductor layer formed on the substrate, a p-type semiconductor layer formed on a portion of a surface of the n-type semiconductor layer, an electrode for applying a reverse biasing voltage to the PN junction to cause an avalanche breakdown and an area formed in a portion of the PN junction. The p-type semiconductor layers forms a planar type PN junction with the n-type semiconductor layer. The area formed in a portion of the PN junction has a lower break down voltage than that of other area.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor light-emitting device which has a planar type PN junction or a Schottky junction and produces a light by applying a reverse bias to the junction to cause an avalanche breakdown. Photo-emission from avalanche breakdown has been reported by an article "Photo emission from avalanche breakdown" by A.G. Chynoweth and H.K. Mckey, Phys. Rev., Vol. 102, p.369, 1956. On the other hand, an application of the photo emission phenomenon to a light emitting semiconductor element is reported in "A study of the nature and characteristics of light radiation in reverse-biased silicon junctions" by C.B. Williams and K. Daneshver, Conf. Proc. IEEE, southeast con., p.161, 1988. In this article, it is reported that a photo emission intensity on a Si PN junction interface is 0.01 W/cm². The semiconductor devices in those articles comprise planar type PN junctions as described in "Physics of Semiconductor Devices" by S.M. Sze, John Wiley & Sons, p.73. Document JP-A-59 055 085 discloses a semiconductor light emitting device for obtaining a high quantum efficiency and high stability by arranging a striped semiconductor layer. Furthermore, a semiconductor light emitting device is described in "Applied Physics Letters, 55(4) 374 (1989)" by J. Chen et al. including an n-type semiconductor layer formed on a substrate and a p-type semiconductor layer formed on a portion of a surface of the n-type semiconductor layer. The p-type semiconductor layer forms a PN junction with the n-type semiconductor layer. Moreover, an electrode formed on an end portion of the p-type semiconductor layer applies a reverse biasing voltage to the PN junction to cause an avalanche breakdown. Document EP-A-0 359 329 which falls within the terms of Art. 54(3) EPC further discloses a semiconductor light emitting device comprising an n-type semiconductor substrate and a p-type semiconductor layer formed on the surface of the n-type semiconductor substrate, wherein the p-type semiconductor layer forms a PN junction with the n-type semiconductor substrate. Electrodes are connected to the n-type semiconductor substrate and the p-type semiconductor layer for applying a reverse biasing voltage to said PN junction to cause light emission by an avalanche breakdown. The PN junction includes a first area and a second area, wherein the first area has a lower breakdown voltage, due to a portion of the n-type semiconductor substrate having a higher impurity concentration, than that of said second area. In the prior art devices, because of the planar type PN junction, there usually exists a portion having a cylindrical radius of curvature or spherical radius of curvature around the junction. Since an electric field acting on the junction is higher in the portion having the cylindrical or spherical radius of curvature than in a planar junction portion, the photo emission by the avalanche breakdown occurs only in the high electric field zone, that is, only periphery of the junction, and it is not possible to uniformly emit light throughout the junction. In such a planar junction, there occurs photo emission by an electric field concentration due to non-uniformity of a patterning shape in the formation of the junction or photo emission by an electric field concentration due to defects. Thus, photo emission by inadvertent factors governs the light intensity of the photo emission or the position of the photo emission. Accordingly, it is not possible to form a light emitting device with a high control. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor light emitting device which solves the problems encountered in the prior art devices, can be manufactured with a high control and emits light uniformly. According to the present invention this object is accomplished by a semiconductor light emitting device comprising a substrate; an n-type semiconductor layer formed on said substrate; a p-type semiconductor layer formed on a portion of a surface of said n-type semiconductor layer, said p-type semiconductor layer forming a PN junction with said n-type semiconductor layer; and an electrode formed on an end portion of said p-type semiconductor layer for applying a reverse biasing voltage to said PN junction to cause light emission by an avalanche breakdown, wherein said PN junction includes a first area and a second area, said first area has a lower breakdown voltage, due to a portion of the n-type semiconductor layer having a higher impurity concentration, than that of said second area, said PN junction has at least a plane section parallel to a surface of said substrate and said first area is only at a part of a center portion of said plane section. Further, this object is achieved by a semiconductor light emitting device comprising a substrate; and an n-type semiconductor layer formed on said substrate; wherein a Schottky electrode layer is formed on said n-type semiconductor layer, said Schottky electrode layer forming a Schottky junction with said n-type semiconductor layer; a contact electrode is formed at an end portion of said Schottky electrode layer for applying a reverse biasing voltage to said Schottky junction to cause an avalanche breakdown; said Schottky junction includes a first area and a second area, said first area having a lower breakdown voltage due to a portion of the n-type semiconductor layer having a higher impurity concentration than that of said second area; and wherein said Schottky junction has at least a plane section parallel to a surface of said substrate and said first area is only at a part of a center portion of said plane section. The advantages of the invention will become apparent and obvious to those skilled in the pertinent art upon referring to the following description provided in connection with the accompanying drawings, of which: Figs. 1A and 1B show a plan view and a sectional view of a first embodiemnt of a semiconductor light emitting device of the present invention, Fig. 2 shows an energy band of the device shown in Fig. 1, Fig. 3 illustrates a light emission process in the device of the present invention, Fig. 4 shows a relation between a photon energy and a light intensity in the device shown in Fig. 1, Fig. 5 shows a sectional view of a second embodiment of the present invention, Figs. 6A and 6B show a plan view and a sectional view of a third embodiment of the present invention, Fig. 7 shows an energy band of the device shown in Fig. 6, and Fig. 8 shows a sectional view of a fourth embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figs. 1A and 1B show a plan view and an A-A′ sectional view of a first embodiment of the semiconductor light emitting device of the present invention. This device manufactured by the following process. An n-type semiconductor layer 2 having an impurity concentration of 3 x 10¹⁶ cm⁻³ was formed on an n-type semiconductor substrate 1 (GaAs (100) in the present embodiment) by molecule beam epitaxy (MBE) growth. Photoresist in an area 3 is cut by a photolithography resist process, and Si ions were injected therein at an acceleration voltage of 80 KeV. Further, photoresist in an area 5 was cut by a similar resist process and Zn ions were injected therein at an acceleration voltage of 40 KeV. It is then annealed in an arsine environment at 850°C for 30 seconds to activate the impurity atoms. The area 3 was rendered to a highly doped n-type area having a peak impurity concentration of approximately 1 x 10¹⁸ cm⁻³, and the area 5 to a p-type semiconductor layer having a peak impurity concentration of no smaller than approximately 1 x 10¹⁹ cm⁻³. The size of the highly doped n-type area 3 is preferably no larger than 5 µm in diameter. When it is larger than 5 µm, a uniform light emission is not attained and heat generation increases. The thickness of the p-type semiconductor layer 5 is preferably no larger than 0.1 µm. If it is larger than 0.1 µm, a light transmittance rapidly decreases. SiO₂ was sputtered on the semiconductor layer to form an insulation layer 9. Photoresist at a predetermined position was cut by the same resist process as that described above and a portion of the insulation layer 9 was etched off to form an opening. Cr/Au was vapor-deposited thereon and unnecessary portion was removed by etching, and an ohmic contact electrode 6 to the p-type semiconductor layer 5 was formed. An Aℓ contact electrode 11 was formed to be connected to the electrode 6. An ohmic contact electrode 8 was formed on a bottom surface of the substrate 1. A reverse biasing electric field was applied to the device thus formed from a power supply 7 through electrodes 6 and 8 so that a light hν was emitted from the top of the area 3. The operation of the device of the present invention is now explained. Fig. 2 shows an energy band of the semiconductor light emitting device of the present invention. As shown in Fig. 2, by jointing the p-type semiconductor layer 5 to the n-type semiconductor layer 2 and applying the reverse bias to cause the avalanche breakdown, a number of electrons and holes are generated in a depletion layer. The generated electrons and holes cause not only a normal inter-band transition shown by a in Fig. 3 but also a recombination of carriers having a high energy shown by b or an intra-band transition shown by c , and the light is emitted. In the present embodiment, the highly doped n-type area 3 which is distinctive from other area is formed in the n-type semiconductor layer 2 to form a depletion layer shown by a broken line 4 in Fig. 1B. An uniform and high electric field area is formed throughout the highly doped n-type area 3 so that the light emission uniformly occurs only in the highly doped area. In the present embodiment, by forming the highly doped n-type area 3, the high electric field is formed to increase an electron-hole pair generation efficiency to increase the light emission probability and attain a brightness control. Further, by applying a high energy to the electrons-holes, a light having a larger energy than a band gap Eg is emitted. In the present embodiment, the n-type semiconductor is used as the semiconductor substrate 1. Thus, a highest electric field is formed below the p-type semiconductor layer 5 which is exposed to the surface, and the electrons which are minority carriers in the p-type semiconductor layer 5 most act on the avalanche amplification. As a result, when using a semiconductor substrate 1 (for example, silicon) in which the electron-hole pair generation efficiency varies depending on the type of carriers and the probability of generation of the electron-hole pairs by the electron is larger than the probability of generation of the electron-hole pairs by the holes, the electron generation efficiency is improved by the present embodiment. In the present embodiment, it is necessary that the thickness of the p-type semiconductor layer 5 is very thin enough to fully transmit the light generated at the PN junction interface and reduce a light transmission loss. By the above arrangement, a light emitting device having a relation between the photon energy and the light intensity as shown in Fig. 4 is manufactured with a high control. Fig. 5 shows a second embodiment of the present invention. Fig. 5 shows a sectional view of the device as Fig. 1B does. In Fig. 5, the like elements to those shown in Fig. 1B are designated by the like numerals. The device was manufactured in the following process. An n-type semiconductor layer 2 having an impurity concentration of 5 x 10¹⁶ cm⁻³ was epitaxially grown on an n-type semiconductor substrate 1 (Si (100) in the present embodiment) by a vapor deposition (CVD) method. Then, SiO₂ was formed to a thickness of 400nm (4000 Å) by thermal diffusion, and resist at a predetermined position was cut by a resist process and SiO₂ was removed by fluoric acid etchant to form a donut-shaped opening on the top of the area 10. Then, B (boron) was thermal-diffused by appropriate dopant to form a p-type guard ring area 10. Then, the SiO₂ area at the top of the light emitting area 3 was removed by the resist process and the etchant. P ions (phosphorus) were injected into the area 3 and Ga (gallium) ions were injected into the area 5 to make the area 3 to the n-type semiconductor having a peak impurity concentration of approximately 8 x 10¹⁷ cm⁻³ and the area 5 to the p-type semiconductor layer having a peak impurity concentration of no smaller than approximately 1 x 10¹⁹. The ions were injected at a low acceleration so that the thickness of the p-type semiconductor layer 5 is no larger than 50nm (500 Å), and it was appropriately etched. Then, ohmic contact electrodes 6 and 8 were formed to complete the light emitting device. In the present embodiment, the guard ring area 10 is formed around the highly doped n-type area 3 to form the depletion layer shown by the broken line 4 so that the electric field is further concentrated to the area 3 to improve the light emission efficiency. Figs. 6A and 6B show a plan view and an A-A′ sectional view of a third embodiemnt of the semiconductor light emitting device of the present invention. This device was manufactured in the following process. First, an n-type semiconductor layer 12 having an impurity concentration of 3 x 10¹⁶ cm⁻³ was formed on an n-type semiconductor substrate 21 (GaAs (100) in the present embodiemnt) by molecule beam epitaxy (MBE) growth. Photoresist in an area 13 was cut by a photo-lithography resist process, and Si ions were injected therein at an acceleration voltage of 80 KeV. Then, it was annealed in an arsine environment at 850°C for 30 seconds to activate the impurity atoms. The area 13 was rendered to a highly doped semiconductor area having a peak impurity concentration of approximately 1 x 10¹⁸ cm⁻³. Then, SiO₂ was deposited by a sputtering method to a thickness of 400nm (4000 Å), and resist at a predetermined position was cut by the same resist process as that described above. The SiO₂ at a portion of the top of the device was removed by fluoric acid wet etching and an insulation layer 19 was formed. Then, Cr/Au was vapor-deposited and unnecessary portion was removed by etching. An ohmic contact electrode layer 16 was formed to contact to a Schottky electrode layer 15 to be formed later. An ohmic contact electrode 18 was also formed on the bottom surface of the substrate 21. W (tungsten) was deposited as a Schottky electrode layer 15 to a thickness of approximately 15nm (150 Å) by electron beam (EB) vapor deposition to form a Schottky junction. The n value was 1.05 at a barrier height  SB = 0.8 eV of the Schottky junction. Finally, an Aℓ contact electrode 31 was formed. A reverse biasing electric field was applied to the device thus manufactured from a power supply 17 through electrodes 16 and 18. The light hν was emitted from the top of the area 13. The operation of the device of the present invention is now explained. Fig. 7 shows an energy band of the semiconductor light emitting device of the present invention. As shown in Fig. 7, the Schottky electrode layer 15 is jointed to the n-type semiconductor layer 12 and the reverse bias is applied thereto to cause the avalanche breakdown so that a number of electrons and holes are generated in the depletion layers. The generated electrons and holes causes the inter-band transition, carrier recombination or intra-band transition as shown in Fig. 3 to emit a light. In the present embodiment, the highly doped n-type area 13 which is distinctive from other area is formed in the n-type semiconductor layer 12 to form the depletion layer as shown by the broken line 14 in Fig. 6B. By forming a uniform and high electric field area throughout the highly doped n-type area 13, the light emission occurs uniformly only in the highly doped area 13. In the present embodiment, the highly doped area 13 is formed as described above to form the high electric field and increase the electron-hole pair generation efficiency and increase the probability of light emission in order to attain the brightness control. Further, a large energy is applied to the electrons-holes so that a light having a larger energy than the band gap Eg is emitted. In the present embodiment, the n-type semiconductor is used as the semiconductor substrate 21. Thus, the highest electric field is formed below the Schottky electrode layer 15 on the surface and the electrons in the schottky electrode layer 15 most act on the avalanche amplification. Accordingly, when using a substrate 21 (for example, silicon) in which the electron-hole pair generation efficiency varies depending on the type of carrier and the probability of generation of the electron-hole pairs by the electrons is larger than the probability of generation of the electron-hole pairs by the holes, the electron generation efficiency is improved by the present embodiment. In the present embodiment, it is necessary that the thickness of the Schottky electrode layer 15 is very thin, enough to fully transmit the light generated at the PN junction interface and reduce the light transmission loss. In this connection, the thickness of the Schottky electrode layer 15 is preferably less than 0.1 µm. In the present embodiment, a relation between the photon energy and the light intensity is same as that shown in Fig. 4 for the first embodiment. Fig. 8 shows a fourth embodiment of the present invention. Fig. 8 shows a sectional view of the device as Fig. 6B does. In Fig. 8, the like elements to those shown in Fig. 6B are designated by the like numerals. This device was manufactured by the following process. First, an n-type semiconductor layer 12 having an impurity concentration of 5 x 10¹⁶ cm⁻³ was epitaxially grown on an n-type semiconductor substrate 21 (Si (100) in the present embodiment) by a vapor deposition (CVD) method. Then, SiO₂ was formed to a thickness of 400 nm (4000 Å) by thermal diffusion. Resist at a predetermined position was cut by the resist process, and the SiO₂ at that position was removed by fluoric acid etchant to form a donut-shaped opening on an area 30. Then, B (boron) was thermal-diffused by appropriate dopant to form a p-type guard ring area 30. The SiO₂ at the top of the light emission area was removed by the above-mentioned resist process and etchant, and P (phosphorus) ions were injected in the area 13 in the same manner as that of the third embodiment to form the n-type semiconductor having a peak impurity concentration of approximately 8 x 10¹⁷ cm⁻³ after annealing. Then, ohmic contact electrodes 16 and 18 were formed, and finally Au was vapor-deposited to a thickness of 15nm (150 Å) to form a Schottky electrode layer 15. In the present embodiment, Au is used as the material of the Schottky electrode layer 15 although it is not restrictive and any other material which forms a Schottky junction may be used. A material other than metal such as silicide, carbonide or boronide may be used. A material which has a low resistivity, a high light transmittance and exhibits uniformity even if it is thin is preferable. In the present embodiment, the guard ring area 30 is formed around the highly doped n-type area 13 to form the depletion layer shown by the broken line 14 and the electric field is concentrated thereto. Accordingly, the light emission efficiency is improved.

Claims: A semiconductor light emitting device comprising a substrate (1); an n-type semiconductor layer (2) formed on said substrate (1); a p-type semiconductor layer (5) formed on a portion of a surface of said n-type semiconductor layer (2), said p-type semiconductor layer (5) forming a PN junction with said n-type semiconductor layer (2); and an electrode (6) formed on an end portion of said p-type semiconductor layer (5) for applying a reverse biasing voltage to said PN junction to cause light emission by an avalanche breakdown, wherein said PN junction includes a first area and a second area, said first area has a lower breakdown voltage, due to a portion (3) of the n-type semiconductor layer having a higher impurity concentration, than that of said second area, said PN junction has at least a plane section parallel to a surface of said substrate (1) and said first area is only at a part of a center portion of said plane section. A semiconductor light emitting device according to claim 1, wherein the the portion (10) of p-type semiconductor layer (5) around said first area is thicker than other portions of said p-type semiconductor layer (5). A semiconductor light emitting device according to claim 1, wherein the size of said first area is no larger than 5 µm in diameter. A semiconductor light emitting device according to claim 1, wherein the thickness of the p-type semiconductor layer (5) in said first area is no larger than 0.1 µm. A semiconductor light emitting device comprising: a substrate (21); and an n-type semiconductor layer (12) formed on said substrate (21); wherein a Schottky electrode layer (15) is formed on said n-type semiconductor layer (12), said Schottky electrode layer (15) forming a Schottky junction with said n-type semiconductor layer (12); a contact electrode (16) is formed at an end portion of said Schottky electrode layer (15) for applying a reverse biasing voltage to said Schottky junction to cause an avalanche breakdown; said Schottky junction includes a first area and a second area, said first area having a lower breakdown voltage due to a portion (13) of the n-type semiconductor layer (12) having a higher impurity concentration than that of said second area; and wherein said Schottky junction has at least a plane section parallel to a surface of said substrate (21) and said first area is only at a part of a center portion of said plane section. A semiconductor light emitting device according to claim 5, wherein a ring-shaped p-type semiconductor layer (30) is formed around said first area. A semiconductor light emitting device according to claim 5, wherein the size of said first area is no larger than 5 µm in diameter. A semiconductor light emitting device according to claim 5, wherein the thickness of said Schottky electrode layer (15) in said first area is no larger than 0.1 µm.

Inventors: OKUNUKI MASAHIKO C O CANON KAB, TSUKAMOTO TAKEO C O CANON KABU, OKUNUKI, MASAHIKO, C/O CANON KABUSHIKI KAISHA, TSUKAMOTO, TAKEO C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H01L33
IPC codes: H01L33