Low-noise preamplifier stage, in particular for magnetic heads

Abstract: A low-noise preamplifier stage, in particular for magnetic heads, which comprises a differential circuit (T₅,T₆) and a single-transistor output stage (T₂). The differential stage has an intrinsic offset voltage, is ground-connectable and can be directly coupled to the magnetic head (L) , the two transistors forming the differential circuit (T₅,T₆) having different bias currents in order to reduce the input equivalent noise. The base terminal of the first transistor (T₅) of the differential circuit defines an input (IN) of the stage which can be connected directly to a terminal of the magnetic head (L); the other terminal of the head can be connected directly to the ground. The base terminal of the other transistor (T₆) of the differential circuit (T₅,T₆) is connected to the intermediate point of a pair of resistors (R₁,R₂) which are mutually connected in series between the single transistor of the output stage (T₂) and a line at reference voltage. In this manner the differential stage (T₅,T₆) biases the output with its offset voltage without requiring additional components for this purpose.

Description: The present invention relates to a low-noise preamplifier stage, in particular for magnetic heads. More in particular, the present invention relates to a preamplifier stage which has a ground-connectable input and can be directly coupled to the magnetic head. Generic preamplifier stages in various configurations are known. However, none of these configurations fully and simultaneously meets all the requirements of the specific application. For example, in the development of a preamplifier stage for the described application, a configuration which comprises an output stage provided via an NPN transistor driven by a single-transistor stage, also of the NPN type, has been studied. A possible circuital solution based on this configuration is shown in figure 1. In this figure, T 2 indicates the output transistor and T 1 indicates the input transistor, R 1 and R 2 are used to define the value of the total gain of the stage, and V REF is the bias voltage required to appropriately bias the output (due to the single-transistor structure of the output stage), such auxiliary voltage being applied to the base of the transistor T 1 via resistor R. The capacitor C provides an alternative-current path through which the input signal can be applied, and has therefore a terminal connected to the base of T 1 and the other terminal arranged so as to define the input IN of the stage. This stage meets the requirement of low noise, since the total noise of the stage is predominantly due to a single transistor, i.e. to T 1 , whereas the noise due to the transistor T 2 can be ignored, since it is returned to the input divided by the amplification of the first stage (which includes T 1 ). However, this stage is not ground-connectable, cannot be directly coupled and furthermore has additional problems related to the assignment of the values of R and C. R and C in fact must be given values so that the virtual high-pass filter which they form allows the passage of the audio signal V IN applied to the input, i.e. so that the time constant τ = R · C of said filter is large enough. However, R cannot have a high value in order to avoid deteriorating the stage input noise. For a given value of the time constant, it is therefore necessary to choose a high capacity value C, and this causes a considerable increase in the cost of the overall system. In order to overcome the above described problems, a different configuration, which uses a differential stage for the input stage, has been developed. The related circuital solution is shown in figure 2, in which T 1 again indicates the input transistor, R 1 and R 2 again indicate the resistors which set the gain of the stage, and the differential stage is formed by two identical PNP transistors indicated by T 3 , T 4 . In particular, the two coupled emitters of T 3 , T 4 are connected to a current source, indicated by 2I, and their collectors are connected to the ground via respective resistors R 3 , R 4 . The base of T 4 is connected to the intermediate point between R 1 and R 2 , whereas the base of T 3 is connected to an inductor L which represents the magnetic head, the other terminal whereof must be connected to a reference voltage V REF . A direct coupling is therefore obtained in this solution, but it is still necessary to provide for an auxiliary voltage source to obtain the voltage V REF required to bias the output to a value higher than that defined by the ground. This entails the known problems related to greater structural complication, to the presence of drifts, etc. Furthermore and most of all, this structure entails a considerable deterioration of the noise performance with respect to the circuit of figure 1. In fact, by setting T 3 and T 4 to an equal current level and optimizing the structure for the source resistance, indicating the input equivalent noise source of T 3 with e n1 , and assuming, for the sake of simplicity, that only the transistors produce noise, the total noise of the stage is: e ni = √(e n1 2 + e n2 2 ) = 1.4·e n1 Document JP-A-57 081 711 discloses a similar arrangement with the difference that the resistance corresponding to R1 is not connected to ground but to reference voltage generated by a Zener diode, a transistor and a resistor. Document JP-A-56 31210 disclose a circuit as defined in preamble of claim 1. Given this situation, the aim of the present invention is to provide a low-noise preamplifier stage, in particular for magnetic heads, which solves the disadvantages of the known art. Within the scope of this aim, a particular object of the present invention is to provide a preamplifier stage which has a ground-connectable input. An important object of the present invention is to provide a preamplifier stage of the indicated type which can be directly coupled. Not least object of the present invention is to provide a preamplifier stage of the indicated type which has a simple circuital structure, with a limited number of components, in particular it does not require the presence of a source of a reference voltage differing from the supply voltage and from the ground or high-value capacitors, and is consequently reliable and can be economically manufactured and even integrated. This aim, the objects mentioned and others which will become apparent hereinafter are achieved by a low-noise preamplifier stage, in particular for magnetic heads, as defined in the accompanying claims. The characteristics and advantages of the invention will become apparent from the description of a preferred embodiment, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a circuit diagram of a preamplifier with a single-transistor input stage; figure 2 is a circuit diagram of a preamplifier with an input stage which comprises a differential stage, and figure 3 is a circuit diagram of the preamplifier stage according to the invention. Figures 1 and 2 are not described hereinafter; reference is made to the above description for said figures. With reference to figure 3, the preamplifier stage according to the invention comprises an output transistor of the NPN type, again indicated by T 2 , and an input stage provided by means of a differential stage which comprises a pair of PNP transistors T 5 and T 6 . The output transistor T 2 is connected, as in the solutions according to figures 1 and 2, to the supply voltage V s with its collector, and to the ground with its emitter through the resistors R 1 , R 2 , which are mutually connected in series and determine the gain of the stage in this case as well. The base of T 2 is connected to a current source I which is connected to the power supply V s with its other terminal. The same terminal of the current source I which is connected to the base of T 2 is also connected to the collector of a NPN transistor T 7 , the emitter whereof is connected to the ground through the resistor R 6 and the base whereof is connected to the output of an operational amplifier 10. The inverting input of the amplifier 10 is connected to the emitter of T 7 (and therefore to the terminal of R 6 which is not connected to the ground), whereas its non-inverting input is connected to the collector of T 5 , which is also connected to a terminal of a resistor R 5 . The collector of T 6 is instead connected directly to the ground. The coupled emitters of T 5 , T 6 are connected to a current source of appropriate value, which delivers, in the specific embodiment, the current 4I and is arranged between the differential stage T 5 , T 6 and the power supply V s . The base of T 6 is connected to the intermediate point between R 1 and R 2 , so as to bias the output, whereas the base of T 5 is connected to a terminal of the head, which is schematically represented by the inductor L, whereas the other terminal of the head is connected directly to the ground. According to the invention, the transistors T 5 , T 6 are provided with different areas (and specifically the emitter area of T 6 is at least three times larger than that of T 5 , e.g. ten times larger), but in all other respects they are identical transistors, so that the bias current which flows through them is different. The resistors R 5 , R 6 are furthermore mutually identical. The operation of the circuit of figure 3 is as follows: assuming the amplifier 10 is ideal, its inputs are at the same voltage, i.e. V + = V - , so that the drop on R 5 is equal to the drop on R 6 . Since these two resistors are identical, the current which flows through R 5 (and therefore the collector current of T 5 ) is equal to the current I which is set by the source I and flows through R 6 . Consequently, T 6 is crossed by a current equal to 3I, i.e. to the difference between the current supplied by the source 4I and the current drawn by T 5 . Since T 5 and T 6 are identical apart from the emitter areas, the stage has an intrinsic offset voltage equal to V OFF = KT q ln I C6 I C5 where I C5 and I C6 are the collector currents of T 5 , T 6 respectively. This offset, multiplied by (R 1 + R 2 )/R 1 , which is the gain of the stage, provides the bias required by the non-zero output, without using auxiliary voltages. The head L can consequently be directly and continuously coupled to the base of T 5 with one of its terminals and directly to the ground with its other terminal. The circuit according to the invention has a lower equivalent noise than the circuit illustrated in figure 2. As is known, the equivalent noise voltage of a voltage-controlled transistor is in fact inversely proportional to the bias current. Therefore, by biasing T 6 with a current which is higher (and specifically three times higher) than the bias current of T 5 , its contribution to the equivalent noise voltage is smaller than that of T 5 . In particular, indicating the source of equivalent noise in input to T 5 again with e n1 , via the circuit according to the invention it is possible to obtain a total equivalent input noise which is significantly smaller that 1.4 e n1 . As can be seen from the above description, the invention fully achieves the intended aim and objects. A stage has in fact been provided which, as explained above, by virtue of the use of a differential stage the transistors whereof have different bias currents, has a noise level which is not excessive and in any case adequate for the use. The use of two transistors with different bias currents gives the differential stage an intrinsic offset which can be used to bias the output, without the need for specifically provided components, so that the stage according to the invention is simpler and more reliable. A further consequence of the absence of reference voltages is the fact that the head L can be connected directly between the input of the stage IN and the ground. The circuit is furthermore completely ground-connectable, since it can operate perfectly even when the input IN is at the ground voltage or even slightly below it (provided that it is within the linear operating range of the transistor T 5 ). Finally, components which require such dimensionings as to entail actual manufacturing problems are not required, and the stage can be easily integrated. The invention thus conceived is susceptible to numerous modifications and variations, all of which are within the scope of the inventive concept. In particular, the fact is stressed that the value of the bias source of the differential stage and the area ratio between T 5 and T 6 depend on the required bias of the output and can therefore vary according to the requirements. Similarly, the bias of the input transistor T 5 to the required value can be obtained in different manners, and the multiplication ratio between R 5 and R 6 , which is equal to one in this embodiment, can also be chosen differently. All the details may furthermore be replaced with other technically equivalent elements. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly, such reference signs do not have any limiting affect on the scope of each element identified by way of example by such reference signs.

Claims: Low-noise preamplifier stage, in particular for magnetic heads, comprising an input stage which comprises a differential circuit formed by a first transistor (T 5 ) and by a second transistor (T 6 ) with coupled emitters, and a single-transistor output stage (T 2 ), said first and second transistors having different emitter areas, the coupled emitters of said first and second transistors being connected to a first current source (4I), the base terminal of said first transistor (T 5 ) defining an input (IN) of the stage and the base terminal of said second transistor (T 6 ) being connected to the intermediate point of a pair of resistors (R 1 , R 2 ), said resistors (R 1 , R 2 ) being mutually connected in series between said single transistor (T 2 ) of the output stage and a line at reference voltage, characterized in that it comprises a second current source (I) which generates a submultiple current of the current generated by said first current source (4I), said second current source (I) being connected in series with a first current controlling resistor (R 6 ) and said first transistor (T 5 ) being connected in series with a second current controlling resistor (R 5 ), said first (R 6 ) and second (R 5 ) current controlling resistors being connected by voltage regulating means (10, T 7 ) which imposes an identical voltage value to said first (R 6 ) and second (R 5 ) current controlling resistors so that the current conducted by said first transistor (T 5 ) is identical to the current generated by said second current source (I), the difference in currents conducted by said first (T 5 ) and second (T 6 ) transistors generating an intrinsic offset voltage between the respective base terminals, so as to bias said output stage with said offset voltage. Stage according to claim 1, characterized in that the bias current of said second transistor (T 6 ) is higher than the bias current of said first transistor (T 5 ). Stage according to claims 1 and 2, characterized in that the emitter area of said second transistor (T 6 ) is a multiple of the emitter area of said first transistor (T 5 ). Stage according to claim 1, characterized in that said voltage regulating means comprise and operational amplifier (10) and a feedback transistor (T 7 ), the base of said feedback transistor (T 7 ) being connected to the output of said operational amplifier (10) and the emitter and collector terminal being interposed between said first current controlling resistor (R 6 ) and said second current source (I), the emitter being furthermore connected to the inverting input of said operational amplifier (10), the non-inverting input of said operational amplifier (10) being connected to said second current controlling resistor (R 5 ). and said further resistor (R 6 ). Stage according to one or more of the preceding claims, characterized in that the base of the single transistor (T 2 ) of said output stage is connected to the line connecting said feedback transistor (T 5 ), and said second current source (I). Stage according to one or more of the preceding claims, characterized in that said input (IN) of the stage can be connected to a terminal of an inductive element (L) which constitutes in particular said magnetic head and has its other terminal connected directly to said line at reference voltage. Stage according to one or more of the preceding claims, characterized in that said first transistor and said second transistor (T 5 , T 6 ) of the differential stage are of the PNP type, said single transistor (T 2 ) of the output stage and said feedback transistor (T 5 ), being of the NPN type.

Inventors: MURARI BRUNO, ROSSI DOMENICO, SAVINO PIERANTONIO, MURARI, BRUNO, ROSSI, DOMENICO, SAVINO, PIERANTONIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H03F3
IPC codes: G11B5, H03F3