Wafer-scale semiconductor device having fail-safe circuit

Abstract: A wafer-scale semiconductor memory device includes a wafer (1), and a plurality of memory chips (2) formed on the wafer. The memory chips contain a memory chip which includes a storage circuit (11, 21), and a switching transistor (QA) which selectively connects the storage circuit to a power supply line (Vcc) in response to a control signal (G, G1). The memory chip also includes a control logic circuit (12; 22, 24) which writes data into the storage circuit and reads out data from the storage circuit and which generates a logic signal used for controlling the transistor. Further, the memory chip includes a fail-safe circuit (13, 23, 23A) having a circuit element (F, G) having a status showing whether or not the control logic circuit is malfunctioning. The fail-safe circuit generates the control signal from the logic signal and the status of the circuit element so that when the circuit element has the status showing that the control logic circuit is malfunctioning, the fail-safe circuit outputs the control signal which instructs the switching element to disconnect the storage circuit from the power supply line irrespective of the logic signal.

Description: The present invention generally relates to a wafer-scale semiconductor device, and more particularly to an improvement in a system configuration directed to mutually connecting functional blocks such as memory chips on a wafer so as to avoid a defective functional block (memory chip) being connected. Recently, there has been considerable activity in the development of a wafer-scale semiconductor integrated memory device. A known such device, illustrated in Figure 1 of the accompanying drawings, may be considered to comprise a plurality of circuitry blocks formed on a wafer, each such circuitry block including: a data circuit; switching means, connected between the said data circuit and a power supply line of the device, and switchable, in response to a predetermined control signal, from a connecting state, in which the data circuit is connected by the switching means to that line, to an isolating state in which the data circuit is disconnected from the said power supply line; and control logic circuit means, connected to the said data circuit for controlling transfer of data to/from the said data circuit and operable, in response to an external control signal that can be applied thereto if the said data circuit is found to be malfunctioning, to produce a predetermined logic signal which causes the said predetermined control signal to be applied to the said switching means. Referring to FIG. 1, there is illustrated the entire structure of such a wafer-scale semiconductor memory device and one of the plurality of circuitry blocks (memory chips) 2 formed on the wafer 1. The memory chips (memory circuits) 2 are mutually connected through a communication path (interconnection line) 3 connected to a data input/output terminal 4 in such a way that defective memory chips 5 illustrated by blocks with crosses are not connected. Each of the memory chips 2 is made up of a storage circuit (data circuit) 2a formed of a DRAM (dynamic random access memory), a write/read control logic circuit 2b labelled GONLOG2, a configuration logic circuit 2c labelled CONLOG1 and a switching transistor (switching means) QA. Hereinafter, the configuration logic circuit 2c and the write/read control logic circuit 2b, which together constitute the above-mentioned control logic circuit means, are simply referred to as the first and second logic circuits 2c and 2b, respectively. A positive power supply line Vcc is connected to the DRAM 2a via the switching transistor QA, which is formed of, for example, a P-channel MOS transistor. The DRAM 2a is directly connected to negative power supply lines Vss and Vbb, respectively. The positive power supply line Vcc is also connected to the second logic circuit 2b via the switching transistor QA. The first logic circuit 2c inputs data and commands supplied from an adjacent memory chip via a bus and outputs data and commands thereto via the bus. The second logic circuit 2b mutually couples the DRAM 2a and the first logic circuit 2c. The source and drain of the switching transistor QA of the P-channel type are connected to the positive power supply line Vcc and the DRAM 2a, respectively, and the gate thereof is connected to an output terminal of the first logic circuit 2c. The first logic circuit 2c controls the gate of the switching transistor QA as follows. When the memory chip 2 is connected to the communication path 3, the first logic circuit 2c outputs a low-level gate control signal to the gate of the switching transistor QA in response to an external control signal S. On the other hand, when it is necessary to disconnect the DRAM 2a shown in FIG.1 due to the presence of a defect in the DRAM 2a, the first logic circuit 2c outputs a high-level gate control signal to the gate of the switching transistor QA in response to the external control signal S. Thus, the switching transistor QA is turned OFF so that the DRAM 2a is electrically disconnected from the positive power supply line Vcc. There is a possibility that even when the first logic circuit 2c is instructed to turn OFF the switching transistor QA by the external control signal S, the first logic circuit 2c may output the low-level gate control signal to the gate of the switching transistor QA due to a defect of the first logic circuit 2c. For example, a transistor of the first logic circuit 2c may be formed in a substrate containing a defective crystal, which forming may occur during a wafer process. Such a defective transistor may output a reverse logic signal. Another cause of malfunction of the first logic circuit 2c may be an interlayer short-circuit in which aluminum interconnection lines which are provided at the different layer levels are short-circuited, so that a reverse output logic signal is produced. In cases as described above, the switching transistor QA is maintained ON even if the external control signal S instructs the first logic circuit 2c to disconnect the DRAM 2a having a defect from the positive power supply line Vcc. As a result, a short current passes through the DRAM 2a. Such a short current decreases the power source voltage Vcc which is to be applied to other memory chips and increases the entire power consumption of the device when the device is in a standby mode. Conventionally, if the first logic circuit 2c is defective, a jump bonding is employed in which bonding wires are provided so as to jump the defective memory chip and connect normal adjacent memory chips which are arranged on both sides of the defective memory chip in the same column of the device. However, it is very difficult to mutually connect two normal memory chips located on both sides of a series of two or more defective memory chips aligned in the column direction. EP-A-0283186 discloses a large scale integrated circuit device (LSI IC) having a plurality of circuit blocks each of which is connected to a power supply line of the device by an associated switch. Each switch is controlled by its own switch control circuit which includes a fuse element. If during testing of the device it is found that a circuit block is malfunctioning, the fuse element in the switch control circuit for the block concerned can be blown, switching off the switch for the block so as to deactivate the malfunctioning circuit block. However, in this device, it may be impossible to deactivate the malfunctioning circuit block if the switch control circuit is itself malfunctioning. According to a first aspect of the present invention there is provided a wafer-scale semiconductor device comprising a plurality of circuitry blocks formed on a wafer, each such circuitry block including: a data circuit; switching means, connected between the said data circuit and a power supply line of the device, and switchable, in response to a predetermined control signal, from a connecting state, in which the data circuit is connected by the switching means to that line, to an isolating state in which the data circuit is disconnected from the said power supply line; and control logic circuit means, connected to the said data circuit for controlling transfer of data to/from the said data circuit and operable, in response to an external control signal that can be applied thereto if the said data circuit is found to be malfunctioning, to produce a predetermined logic signal which causes the said predetermined control signal to be applied to the said switching means; characterised in that each circuitry block further includes fail-safe means, interposed between the control logic circuit means and the said switching means and including auxiliary circuitry which has a first condition, permitting such operation of the control logic circuit means, and which is selectively changeable to a second condition such that the said predetermined control signal is applied to the said switching means by the said fail-safe means, thereby to overcome failure of the said control logic circuit means to produce the said predetermined logic signal. Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG.1 is a diagram illustrating a conventional wafer-scale semiconductor memory device; FIG.2 is a block diagram illustrating the outline of a memory chip formed on a wafer according to a first preferred embodiment of the present invention; FIG.3 is a more detailed block diagram of the structure shown in FIG.2; FIG.4 is a block diagram of a first logic circuit shown in FIG.3; FIG5.5A and 5B are block diagrams illustrating the operation of the memory chip shown in FIG.3; FIG.6 is a block diagram illustrating the outline of one memory chip formed on a wafer according to a second preferred embodiment of the present invention; FIG.7 is a more detailed block diagram illustrating the structure shown in FIG.6; and FIGS.8A and 8B are block diagrams illustrating the operation of the memory chip shown in FIG.7. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.2, there is illustrated the outline of a memory chip formed on a wafer of a wafer-scale semiconductor memory device according to a first preferred embodiment of the present invention. The memory chip is made up of a storage circuit 11, a control logic circuit 12, a fail-safe circuit 13 and the aforementioned switching transistor QA of, for example, the P-channel type. The storage circuit 11 corresponds to the DRAM 2a shown in FIG.1, and the logic circuit 12 corresponds to the combination of the first and second logic circuits 2c and 2b shown in FIG.1. The fail-safe circuit 13 is composed of a fuse element F, a resistor R and a logic output circuit 13a. The fuse element F and the resistor R are connected in series to provide a series circuit, which is interposed between the positive power supply line Vcc and ground GND. A connection node P of the fuse element F and the resistor R is connected to an input terminal of the logic output circuit 13a. The other end of the fuse element F opposite to the connection node P is connected to the positive power supply line Vcc. The gate of the switching transistor QA is controlled by the logic output circuit 13a of the fail-safe circuit 13. In a case where the control logic circuit 12 has no defect and operates correctly, the logic output circuit 13a generates the logic output of the control logic circuit 12 and the potential of the node P. When it is requested to connect the storage circuit 11 to the positive power source Vcc, the logic output circuit 13a outputs the low-level gate control signal G. When it is requested to disconnect the storage circuit 11 from the power supply line Vcc, the logic output circuit 13a outputs the high-level gate control signal G. On the other hand, when the control logic circuit 12 is defective and it is requested to disconnect the storage circuit 11 from the power supply line Vcc, the fuse element F is thermally severed so that the connection node P is set to the ground potential. At this time, the logic output circuit 13a sets the gate of the switching transistor QA to the high level irrespective of the status of the output signal of the control logic circuit 12. Thus, the storage circuit 11 is definitely disconnected from the power supply line Vcc even if the control logic circuit 12 malfunctions. In addition, it becomes possible to avoid wasteful power consumption due to a malfunction of the control logic circuit 12. If the switching transistor QA is formed of an N-channel MOS transistor, the logic output circuit 13a generates the reverse logic output. That is, when it is requested to disconnect the storage circuit 11 from the power supply line Vcc, the logic output circuit 13a outputs the low-level gate control signal G. In this case, if the control logic circuit 12 is defective, the fuse element F is melted. The drain and source of the N-channel MOS transistor forming the switching transistor QA are connected to the positive power supply lines Vcc and the storage circuit 11, respectively, and the gate thereof is connected to the output terminal of the logic output circuit 13a. Referring to FIG.3, there is illustrated a more detailed structure of one memory chip formed on a wafer according to the first preferred embodiment of the present invention. A memory chip 20 is made up of a DRAM 21, a first logic circuit 22, a fail-safe circuit 23, a second logic circuit 24 and the switching transistor QA of the P-channel type. The DRAM 21 shown in FIG.3 corresponds to the storage circuit 11 shown in FIG.2. The first and second logic circuits 22 and 24 correspond to the first and second logic circuits 2c and 2b shown in FIG.1, respectively, and also correspond to the control logic circuit 12 shown in FIG.2. The wafer-scale semiconductor memory device according to the first preferred embodiment of the present invention has about 200 memory chips formed on the wafer, each having the structure shown in FIG.3. The DRAM 21 has a storage capacity equal to, for example, a few Mbits. The fail-safe circuit 23 is composed of the fuse element F, the resistor R and a two-input NAND circuit 23a. The fuse element F is connected between the positive power supply line Vcc and one of the two input terminals of the NAND circuit 23a. This terminal of the NAND circuit 23a is connected to one of the two ends of the resistor R, and the other end of the resistor R is grounded. A letter P indicates the connection node of the fuse element F and the resistor R. The other input terminal of the NAND circuit 23a is connected to the output terminal of the first logic circuit 22 and controlled thereby. The output terminal of the NAND circuit 23a is connected to the gate of the switching transistor QA. Before the fuse element F is melted, the potential of the node P is logically high. On the other hand, after the fuse element F is melted, the potential of the node P is logically low. The fuse element F is formed of, for example, a polysilicon resistor. The fail-safe circuit 23 outputs the low-level gate control signal G when the first logic circuit 22 outputs the high-level signal to the NAND circuit 23a and the potential of the node P is at the high level. When the first logic circuit 22 outputs the low-level signal to the NAND circuit 23a with the potential of the node P equal to the high level, the fail-safe circuit 23 outputs the high-level control gate signal G to the gate of the switching transistor QA. When the first logic circuit 22 operates normally, it outputs the low-level signal when the external control signal S instructs that the DRAM 21 be disconnected from the positive power supply line Vcc. If the first logic circuit 22 is defective and outputs the high-level signal irrespective of the fact that the external control signal S instructs that the DRAM 21 be disconnected from the power supply line Vcc, it is determined that the fuse element F should be melted, so that the potential P at the connection node between the fuse element F and the resistor R is set to the low level. As a result, the gate control signal G output by the NAND gate 23a is set to the high level irrespective of the logic level of the output terminal of the first logic circuit 22. In this way, the DRAM 21 is definitely disconnected from the positive power supply line Vcc. The first logic circuit 22 inputs data and commands from an adjacent memory chip or an external terminal via the bus and outputs data and commands to an adjacent memory chip or an external terminal via the bus. More specifically, the first logic circuit 22 outputs data and commands supplied from the adjacent memory chip (or external terminal) to either the second logic circuit 24 or the adjacent memory device via the bus. The first logic circuit 22 is supplied with the positive power source voltage Vcc via the fuse element F. The first logic circuit 22 determines the potential of the input terminal of the NAND circuit 23a in response to the external control signal S. The second logic circuit 24 outputs data supplied from the first logic circuit 22 to the DRAM 21, and outputs data read out from the DRAM 21 to the first logic circuit 22. The positive power supply line Vcc is connected to the second logic circuit 24 via the switching transistor QA. FIG.4 is a block diagram of the first logic circuit 22a shown in FIG.3. The first logic circuit 22a is composed of a decoder 22a, a latch circuit 22b, an inverter 22c and an internal logic circuit 22d. The decoder 22a operates in synchronism with a clock signal supplied from an external device, decodes the external control signal S and outputs a signal to either the latch circuit 22b or the internal logic circuit 22d. For example, the external control signal S is a single pulse signal when it is related to the control of the gate of the switching transistor QA. The external control signal S is composed of a plurality of pulses when an instruction is to be supplied to the internal logic circuit 22d. The latch circuit 22b latches the output signal of the decoder 22a in synchronism with the clock signal CLK. The output signal of the latch circuit 22b is inverted by the inverter 22c and then sent to the NAND circuit 23a. The internal logic circuit 22d outputs data and commands supplied from an adjacent memory chip to the second logic circuit 24 and vice versa. Further, the internal logic circuit 22d functions as a bypass circuit which connects two adjacent memory chips. A description will now be given of the operation of the circuit shown in FIG.3 with reference to FIGS. 5A and 5B. FIG. 5A illustrates a case where the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc while the first logic circuit 22 operates correctly. In this case, the external control signal S is switched from the low level to the high level and soon returns to the low level. That is, the external control signal S is formed of a single high-level pulse. This is decoded by the decoder 22a (FIG.4) and latched by the latch circuit 22b. The high-level output of the latch circuit 22b is inverted by the inverter 22c and then applied to the NAND circuit 23a shown in FIG.3. Thus, the NAND circuit 23a outputs the high-level gate control signal G to the gate of the switching transistor QA. As a result, the P-channel switching transistor QA is turned OFF so that the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc. On the other hand, when it is requested to connect the DRAM 21 to the positive power source line Vcc, the first logic circuit 22 outputs the high-level signal. Since the potential of the node P is at the high level, the NAND circuit 23a outputs the low-level gate control signal G. FIG. 5B illustrates a case where the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc, and the first logic circuit 22 is malfunctioning so that it outputs the high-level signal irrespective of the fact that a high-level external control signal S has been received and latched thereby. In this case, the fuse element F is melted by, for example, a laser beam. Thereby, the potential of the node P is set to the low level, and thus the NAND gate 23a outputs the high-level gate control signal G. As a result, the switching transistor QA of the P-channel type is turned OFF so that the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc. Thus, it becomes possible to prevent the aforementioned shorting current from passing through the DRAM 21 and the second logic circuit 24. In addition, it becomes possible to prevent a wasteful current from passing through the first logic circuit 22. A description will now be given of a wafer-scale semiconductor memory device according to a second embodiment of the present invention. The second embodiment of the present invention is directed to improving the aforementioned first embodiment of the present invention. Referring to FIG.6, there is illustrated the outline of a memory chip formed on a wafer of the wafer-scale semiconductor memory device according to the second preferred embodiment of the present invention. Referring to FIG.6, a second switching transistor QB is added to the structure shown in FIG.2 and in the fail-safe circuit 13 shown in FIG.6 a logic output circuit 13b is substituted for the logic output circuit 13a shown in FIG.2. The gates of the first and second switching transistors QA and QB are controlled by the logic output circuit 13b. The second switching transistor QB is provided between the positive power supply line Vcc and the control logic circuit 12. That is, when the second switching transistor QB is ON, the control logic circuit 12 is continuously supplied with electric power. When it is requested to disconnect the storage circuit 11 from the positive power supply line Vcc while the control logic circuit 12 is malfunctioning, the fuse element F is melted so that the logic output circuit 13b outputs a gate control signal G1 which turns OFF the switching transistor QA, and a second gate control signal G2 which turns OFF the switching transistor QB. In the case where the first and second switching transistors QA and QB are formed of P-channel type MOS transistors, the first and second gate control signals G1 and G2 are set to the high level when it is requested to disconnect the storage circuit 11 from the positive power supply line Vcc while the control logic circuit 12 is malfunctioning. It will be noted that the control logic circuit 12 shown in FIG.3 is supplied with electric power through the fuse element F. Thus, there is a voltage drop occurring between the fuse element F. On the other hand, with the arrangement shown in FIG.6, electric power is supplied to the control logic circuit without passing through the fuse element F. Thus, the control logic circuit 12 shown in FIG.6 is supplied with a positive power source voltage which is almost the same as the positive power source voltage Vcc. FIG.7 is a more detailed block diagram of the structure shown in FIG.6. In FIG.7, those parts which are the same as those shown in the previous figures are given the same reference numerals. A fail-safe circuit 23A is composed of the fuse element F, the resistor R made of, for example polysilicon, a two-input OR circuit 23c and an inverter 23d. The connection node P between the fuse element F and the resistor R is connected to an input terminal of the inverter 23d. An output terminal of the inverter 23d is connected to one of the two input terminals of the OR circuit 23c. The other input terminal of the OR circuit 23c is connected to the output terminal of the first logic circuit 22. The output terminal of the OR circuit 23c is connected to the gate of the switching transistor QA. The output terminal of the inverter 23d is also connected to the gate of the second switching transistor QB. The OR circuit 23c and the inverter 23d are each connected between the positive power supply line Vcc and ground. The first logic circuit shown in FIG.7 has a buffer which is substituted for the inverter 22c shown in FIG.4. A description will now be given of the operation of the circuit shown in FIG.7 with reference to FIGS.8A and 8B. FIG.8A illustrates the case where the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc, and the first logic circuit 22 operates correctly. In this case, the external control signal S is switched from the low level to the high level and returns to the low level soon. That is, the external control signal S is formed of a single high-level pulse. This is decoded by the decoder 22a (FIG.4) and latched by the latch circuit 22b. The high-level output of the latch circuit 22b passes through the aforementioned buffer, which is provided instead of the inverter 22c (FIG.4), and is then applied to the OR circuit 23c shown in FIG.7. Thus, the OR circuit 23c outputs the high-level first gate control signal G1 to the gate of the switching transistor QA. As a result, the P-channel switching transistor QA is turned OFF so that the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc. On the other hand, the low-level second gate control signal G2 generated by the inverter 23d is applied to the gate of the second P-channel transistor QB. As a result, the second transistor QB is ON and the power supply line Vcc is connected to the first logic circuit 22 via the second transistor QB. Thus, the first logic circuit 22 functions as a bypass circuit which couples adjacent memory chips. FIG. 8B illustrates a case where the DRAM 21 and the second logic circuit 24 are disconnected from the positive power supply line Vcc because it is found that the first logic circuit 22 is malfunctioning in that it is outputting the low-level signal irrespective of the fact that a high-level external control signal S has been received and latched thereby. In this case, the fuse element F is melted by, for example, a laser beam. Thereby, the potential of the node P is set to the low level, and the OR circuit 23c is supplied with the high-level signal by the inverter 23d. Thus, the OR circuit 23c outputs the high-level first gate control signal G1. As a result, the first switching transistor QA of the P-channel type is turned OFF so that the DRAM 21 and the second logic circuits 24 are disconnected from the positive power supply line Vcc. Thus, it becomes possible to prevent the aforementioned shorting current from passing through the RAM 21 and the second logic circuit 24. Further, the high-level second gate control signal G2 generated by the inverter 23d is applied to the gate of the second switching transistor QB. Thus, the second switching transistor QB is turned OFF, so that it becomes possible to prevent a wasteful current from passing through the first logic circuit 22. In the above-mentioned first and second embodiments of the present invention, it is possible to use an N-channel MOS transistor in place of the P-channel MOS transistor. MOS transistors can be replaced by, for example, MIS transistors. An appropriate element can be used instead of the fuse element F. The configuration of the logic output circuit 13a (FIG.2) or 13b (FIG.6) is not limited to the specifically described structure. It is possible to replace the NAND circuit 23a shown in FIG.3 by the combination of the OR circuit 23c and the inverter 23d shown in FIG.7. It is also possible to add an inverter and a second switching transistor like the switching transistor QB to the structure shown in FIG.3 so that the added inverter inverts the potential of the node P and applies the inverted potential to the gate of the second switching transistor. It is also possible to use an active-low external control signal in place of the aforementioned active-high external control signal S. It is also possible to use a switching element other than the P-channel or the N-channel transistor. The present invention is not limited to wafer-scale semiconductor memory devices. The memory chips 2 may be replaced by functional blocks (circuitry blocks) which provide predetermined functions. The DRAM 21 may be replaced by an appropriate internal circuit (data circuit) which operates in a predetermined manner. In this case, the second logic circuit 24 supplies the internal circuit with data and reads out data therefrom. The present invention is not limited to the specifically described embodiments, and variations and modifications thereof may be made without departing from the scope of the present invention as defined by the appended claims.

Claims: A wafer-scale semiconductor device comprising a plurality of circuitry blocks (2) formed on a wafer (1), each such circuitry block (2) including: a data circuit (11; 21); switching means (QA), connected between the said data circuit and a power supply line (V cc ) of the device, and switchable, in response to a predetermined control signal (G; G1), from a connecting state, in which the data circuit is connected by the switching means to that line, to an isolating state in which the data circuit is disconnected from the said power supply line; and control logic circuit means (12; 22,24), connected to the said data circuit for controlling transfer of data to/from the said data circuit and operable, in response to an external control signal (S) that can be applied thereto if the said data circuit is found to be malfunctioning, to produce a predetermined logic signal which causes the said predetermined control signal to be applied to the said switching means; characterised in that each circuitry block (2) further includes fail-safe means (13; 23; 23A), interposed between the control logic circuit means and the said switching means and including auxiliary circuitry (F, R) which has a first condition, permitting such operation of the control logic circuit means, and which is selectively changeable to a second condition such that the said predetermined control signal is applied to the said switching means by the said fail-safe means, thereby to overcome failure of the said control logic circuit means to produce the said predetermined logic signal. A wafer-scale semiconductor device as claimed in claim 1, characterized in that said fail-safe means comprises logic output means (13a; 13b; 23a; 23b; 23c, 23d) for receiving a logic level defined by the condition of said auxiliary circuitry (F, R) and a logic level of said predetermined logic signal generated by said control logic circuit means, and for generating said predetermined control signal (G; G1) having a logic level based on a combination of the logic level defined by the condition of said auxiliary circuitry (F, R) and the logic level of said predetermined logic signal generated by said control logic circuit means. A wafer-scale semiconductor device as claimed in claim 2, characterized in that said logic output means comprises a NAND circuit (23a) having a first input terminal which receives the logic level defined by the condition of said auxiliary circuitry (F, R), a second input terminal which receives the logic level of said predetermined logic signal generated by said control logic circuit means (22, 24), and an output terminal which outputs said predetermined control signal which is applied to said switching means (QA). A wafer-scale semiconductor device as claimed in claim 2, characterized in that said logic output means comprises: an inverter (23d) having an input terminal which receives the logic level defined by the condition of said auxiliary circuitry (F, R) and also having an output terminal; and an OR circuit (23c) having a first input terminal coupled to the output terminal of said inverter, a second input terminal which receives said predetermined logic signal generated by said control logic circuit means (22, 24), and an output terminal which outputs said predetermined control signal (G1) which is applied to said switching means (QA). A wafer-scale semiconductor device as claimed in any one of claims 2 to 4, characterized in that: said auxiliary circuitry comprises a series circuit of a fuse element (F) and a resistor (R), said series circuit being coupled between said power supply line (Vcc) and a further power supply line (GND) of the device, such that when the device is in use the condition of said auxiliary circuitry determines the potential of a connection node (P) of said series circuit at which said fuse element and said resistor are connected together in series. A wafer-scale semiconductor device as claimed in any one of claims 1, 2, 3 and 5, characterized in that said auxiliary circuitry (F, R) is connected between said power supply line (Vcc) and said control logic circuit means (22, 24) so that said control circuit means is supplied with electric power via said auxiliary circuitry when that circuitry has its said first condition. A wafer-scale semiconductor device as claimed in claim 1, further comprising second switching means (QB) for selectively connecting said control logic circuit means (22, 24) to said power supply line (Vcc) in response to a second control signal (G2), wherein said fail-safe means (13; 23A) comprises means (13b; 23d) for generating said second control signal in dependence upon the condition of said auxiliary circuitry so that when said auxiliary circuitry has its said second condition said second control signal causes said second switching means to disconnect said control logic circuit means from said power supply line (Vcc). A wafer-scale semiconductor device as claimed in claim 7, characterized in that: said auxiliary circuitry comprises a series circuit of a fuse element (F) and a resistor (R), said series circuit being coupled between said power supply line (Vcc) and a further power supply line (GND) of the device, such that when the device is in use the condition of said auxiliary circuitry determines the potential of a connection node (P) of said series circuit at which said fuse element and said resistor are connected together in series. A wafer-scale semiconductor device as claimed in claim 8, characterized in that said fail-safe means (23A) comprises an inverter (23d) having an input terminal connected to said connection node (P), and an output terminal which outputs second control signal (G2) which is applied to said second switching means (QB). A wafer-scale semiconductor device as claimed in any preceding claim, characterized in that said control logic circuit means of each circuitry block comprises: first logic circuit means (22) for interfacing with an adjacent circuitry block of the said plurality; and second logic circuit means (24) for providing an interface between said data circuit (21) and said first logic circuit means (22) of the block concerned. A wafer-scale semiconductor device as claimed in claim 7, characterized in that said control logic circuit means of each circuitry block comprises: first logic circuit means (22) for interfacing with an adjacent circuitry block of the said plurality; and second logic circuit means (24) for providing an interface between said data circuit (21) and said first logic circuit means (22) of the block concerned, and in that: said switching means (QA) of claim 1 is provided between said power supply line (Vcc) and said second logic circuit means (24); and said second switching means (QB) is provided between said power supply line (Vcc) and said first logic circuit means (22). A wafer-scale semiconductor device as claimed in any preceding claim, characterized in that said switching means of claim 1 comprises a P-channel transistor (QA) having a source coupled to said power supply line (Vcc), a drain coupled to said data circuit (11; 21) and a gate which receives said predetermined control signal (G; G1). A wafer-scale semiconductor device as claimed in any preceding claim, characterized in that said switching means of claim 1 comprises an N-channel transistor (QA) having a drain coupled to said power supply line (Vcc), a source coupled to said data circuit (11; 21) and a gate which receives said predetermined control signal (G; G1). A wafer-scale semiconductor device as claimed in any one of claims 7, 8, 9 and 11, characterized in that said second switching means comprises a P-channel transistor (QB) having a source coupled to said power supply line (Vcc), a drain coupled to said control logic circuit means (12, 22) and a gate which receives said second control signal (G2). A wafer-scale semiconductor device as claimed in any preceding claim, characterized in that said data circuit (11, 21) comprises storage means for storing such data transferred to/from said data circuit. A wafer-scale semiconductor device as claimed in claim 15, characterized in that said storage means (11, 21) comprises a dynamic random access memory. A wafer-scale semiconductor device as claimed in any one of claims 1 to 14, characterized in that each of said circuitry blocks comprises memory chips (2). A wafer-scale semiconductor device as claimed in claim 5, 8 or 9, characterized in that said fuse element (F) comprises a polysilicon resistor.

Inventors: SUZUKI TAKAAKI, TATEMATSU TAKEO, SUZUKI, TAKAAKI, TATEMATSU, TAKEO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G06F11
IPC codes: G11C29