Integrator circuit

Abstract: A switched current integrator circuit is provided with a feedforward input (32) which is connected to the input of a first current memory cell (T31, T32, S31, C31) during a portion 1 of each sampling period and to the input of a second current memory cell (T33, T34, S32, C32) during a portion 2 of each sampling period. The signal to be integrated is fed to a second input (31) connected to the input (T33) of the second current memory cell and the output (T32) of the first current memory cell. A first output (T34) of the second current memory cell is fed back to the input (T31) of the first current memory cell. A second output (T35) if the second current memory cell is coupled to the integrator output (33).

Description: The invention relates to an integrator circuit for integrating input signals having the form of sampled electrical currents, the integrator having an input means for receiving an input signal and an output for making available an output signal and comprising first and second current memory cells, means for connecting the output of the first current memory cell to the input of the second current memory cell, means for connecting a first output of the second current memory cell to the input of the first current memory cell, means for connecting the input means of the integrator to the input of the first and/or second current memory cell, and means for connecting a second output of the second current memory cell to the output of the integrator, wherein the first current memory cell is arranged to produce at its output during a first portion of each sampling period a current related to that applied to its input during a second portion of the preceding sample period and the second current memory cell is arranged to produce at its outputs during a second portion of each sampling period currents related to the current applied to its input during the first portion of the sampling period. Such an integrator circuit has been disclosed in UK Patent Applications Nos. 8721758 (PHB33385), publication Ns: GB-A-2 213 011, 8721759 (PHB33386), 8729987 (PHB33426), 8815668.2 (PHB33477), 8828666.1 (PHB33512), and 8828667.9 (PHB33514). Further such an integrator circuit has been disclosed in a paper presented at the Institution of Electrical Engineers on 17th February, 1989 by J.B. Hughes, N.C. Bird, and I.C. Macbeth entitled "Switched Currents - A New Technique for Analogue Sampled Data Signal Processing". The integrator circuit is one of a number of modules which have been devised for use in circuits using the technique disclosed which has been called "switched current techniques" and the circuits using this technique have been called "switched current circuits" and will be referred to hereinafter by that name. As has been disclosed in the patent applications and paper referred to hereinbefore switched current circuits have certain advantages over other sampled data processing circuits such as switched capacitor circuits but are able to use many of the mathematical techniques used for the design of switched capacitor circuits. In the design of continuous time active R.C. filters and switched capacitor filters a feed forward facility is often required in biquadratic and lossless ladder filter synthesis. This is easily achieved in active R.C. filters and also in switched capacitor filters where it can utilise non-switched capacitors. However, in switched current circuits there is no provision for accurately defined linear capacitors and hence such capacitive feedforward facilities cannot be provided. It is an object of the invention to enable the provision of a facility for providing feedforward of signals through integrators in switched current circuits. The invention provides an integrator circuit as set forth in the opening paragraph characterised in that the integrator circuit comprises a further input for receiving a further input signal, the further input being coupled to the input of the first current memory cell during at least the second portion of each sampling period and to the input of the second current memory cell during at least the first portion of each sampling period. This enables a feedforward facility to be incorporated in switched current integrators so that biquadratic and lossless ladder filter synthesis can be achieved using switched current techniques. Consequently direct mapping from active RC and switched capacitor circuit implementations to switched circuit implementations become possible. The further input may be coupled to the first current memory cell via a first switch which is closed only during the second portion of each sampling period and coupled to the second current memory cell via a second switch which is closed only during the first portion of each sampling period, the first and second portions being non-overlapping. This enables a single feedforward current input to be provided and eliminates the requirement for two equal currents to be supplied to the feedforward input means. The current is supplied to the required parts of the integrator only at the times the integrator needs to act upon it. The first and/or second current memory cells may comprise a current mirror circuit having an input branch comprising a diode connected field effect transistor and an output branch comprising a second field effect transistor, switching of means connecting the gate electrodes of the diode connected and second field effect transistors, and voltage storage means associated with the second field effect transistor which maintains the current flow through the second field effect transistor when the switching means is open. This provides a convenient means for storing a current and has the advantage that the output current can be made available virtually throughout a sampling period and can have any desired relationship with the input current by appropriately choosing the channel width/length ratios of the transistors. Another form of memory cell uses a single transistor both for measuring the input current and providing the output current. This has the advantage of eliminating device mismatch but cannot of course be used where the input and output currents are not equal and in addition the output current is not available while the input current is being sampled. The input means may comprise first and second input terminals, the first input terminal being connected to the input of the first current memory cell and the second input terminal being connected to the input of the second current memory cell via switching means which is closed only during the first portion of each sampling period. This enables the provision of a bilinear integrator having an additional feedforward input. The integrator may comprise a first current source for providing a bias current to the input of the first current memory cell and a second current source providing a suitably scaled bias current for subtracting from the first and second outputs of the second current memory cell. This enables a bi-directional input current to be processed while preventing the input diodes of the current memory cells being reverse biassed. Thus the integrator can accept and process bi-directional input currents and produce a bi-directional output current. In this way the integrator becomes a self contained module within a signal processing system and bias currents do not need to be passed between modules. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:- Figure 1 shows a circuit diagram of a continous time RC active integrator having a feedforward input, Figure 2 shows a circuit diagram of a switched capacitor integrator having a feedforward input, Figure 3 shows a circuit diagram of a first embodiment of an integrator according to the invention, Figure 4 shows a circuit diagram of a second embodiment of an integrator according to the invention, and Figure 5 shows a circuit diagram of a third embodiment of an integrator according to the invention. Figure 1 shows a known continous time integrator having a signal feedforward connection. The integrator comprises a first input 1 which is connected via a resistor R to an inverting input of an amplifier A. A second input 2 is connected via a capacitor C1 to the inverting input of amplifier A while a capacitor C0 is connected between the output and the inverting input of amplifier A. The output of amplifier A is connected to an output terminal 3 while its non-inverting input is connected to ground. As is known to persons skilled in the art, the output voltage produced by the arrangement shown in Figure 1 is given by V o (s) = - v₁(s) sRC0 - v₂(s) C1 C0 where V o (s) is the output voltage at terminal 3, v₁(s) is the input voltage at terminal 1 and v₂(s) is the input voltage at terminal 2. The first term corresponds to ideal integration of the input voltage v₁ while the second term corresponds to the feedforward of the input voltage v₂. This feedforward is accompanied by scaling of v₂ by the factor C1/C0 and by a signal inversion. Figure 2 shows a known switched capacitor circuit which performs the same function as the circuit shown in Figure 1. The circuit shown in Figure 2 effectively replaces the resistor R by the combination of a capacitor C2 and four switches S1 to S4. The switches S1 and S3 are closed during a first phase ⊘1 of each sampling period while the switches S2 and S4 are closed during a second, non-overlapping, phase ⊘2 of each sampling period. As is known to persons skilled in the art the output voltage produced by the arrangement shown in Figure 2 is given by V o (z) = - C2 C0 1 1-z⁻¹ v₁(z) - v₂(z) C1 C0 Again the first term corresponds to ideal integration of the input voltage v₁ while the second term corresponds to the feedforward of the input voltage v₂. This feedforward is accompanied by scaling of v₂ by the factor C1/C0 and by a signal inversion. Such arrangements are used in biquadratic and lossless ladder filter synthesis to create transmission "zeros" in the transfer characteristic, for example see page 283 of the textbook "Analog MOS Integrated Circuits for Signal Processing" by R. Gregorian and G. Temes. Figure 3 shows an arrangement for performing a signal feedforward function in a switched current integrator. The arrangement in Figure 3 has a first input 31 which is connected to the junction of the drain electrode of an n-channel field effect transistor T32 and the drain and gate electrodes of a p-channel field effect transistor T33. A current source 34 is connected between a positive supply rail 35 and the drain and gate electrodes of an n-channel field effect transistor T31 whose source electrode is connected to a negative supply rail 36. The gate electrode of transistor T31 is connected via as switch S31 to the gate electrode of transistor T32. The gate electrode of transistor T33 is connected via a switch S32 to the gate electrode of two further p-channel field effect transistors T34 and T35. The source electrodes of transistors T33, T34, and T35 are connected to the positive supply rail 35. A capacitor C31 is connected between the gate electrode of transistor T32 and the negative supply rail 36 while a capacitor C32 is connected between the gate electrode of transistor T34 and the positive supply rail 35. In practice the capacitor C31 ad C32 may be formed by the inherent gate-source capacitance of transistors T32 and T34 rather than as separate entities. The drain electrode of transistor T34 is connected to the drain electrode of transistor T31 and to the drain electrode of a further n-channel field effect transistor T36 while the drain electrode of transistor T35 is connected to an output terminal 33 and to the drain electrode of an n-channel field effect transistor T37. A current source 37 is connected between the positive supply rail 35 and the gate and drain electrodes of an n-channel field effect transistor T38. The gate electrode of transistor T38 is connected to the gate electrodes of transistors T36 and T37 while the source electrodes of transistors T32, T36, T37, and T38 are connected to the negative supply rail 36. A further input terminal 32 is connected via a switch S33 to the junction of the drain electrodes of transistors T33 and T32 and via a switch S34 to the drain electrode of transistor T31. In Figure 3 the transistors T31 and T32, the switch S31 and the capacitor C31 form a first current memory cell. Input terminal 31 forms the integrator input means to which a current i, to be integrated is applied. Input terminal 32 forms the further input to which a signal B A i₂ to be fed forward is applied. The second current memory cell is formed by transistors T33, T34 and T35, switch S32, and capacitor C32. The first output of the second current memory cell is taken from the drain electrode of transistor T34 which for an ideal integrator will have the same gate width/length ratio as that of transistor T33. If a lossy integrator is required then the gate width/length ratio of transistor T34 will be appropriately chosen so that the current produced at the drain electrode of transistor T34 is a desired fraction of that applied to transistor T33. The second output of the second current memory cell is taken from the drain electrode of transistor T35 whose gate width/length ratio is chosen to give a desired gain factor. Transistors T36, T37 and T38 form a current mirror circuit which is arranged to subtract appropriate bias currents from the first and second outputs of the second current memory cell so that only signal currents are fed to the integrator output 33 and to the input of the first current memory cell. In operation let it be assumed that a current i₁ is applied to input 31, a current B A i₂ is applied to input 32 and an output current i o is produced at output 33. Let it also be assumed that the current sources 34 and 37 each produce a current j so that the input currents can be bi-directional without reverse biassing the input diodes of the current mirror and current memory circuits. Further let it be assumed that the current ratios produced by the current mirror and current memory circuits are as indicated in Figure 3 and that switches S32 and S33 are closed during a first phase ⊘1 of each sampling period while switches S31 and S34 are closed during a second, non-overlapping, phase ⊘2 of each sampling period. Then during phase ⊘2 of sampling period n-1 I₂ = j + B A i₂ (n-1) + 1 A i o (n-1) where I₂ is the current produced by transistor T32. During phase ⊘1 of sampling period n the current I₃ produced by transistor T34 is given by I₃ = I₂ - B A i₂(n) - i₁(n) Also Transforming to the z domain i o (z) (1-z⁻¹) = -A i₁(z) - B i₂(z)(1-z⁻¹) i₀(z) = - A 1-z⁻¹ i₁(z) - B i₂(z) Equation 3) maps directly onto equation 2) and consequently the first term corresponds to an ideal integration of the input current i₁ while the second term corresponds to the feedforward of the input current i₂. This feedforward is accompanied by scaling of i₂ by a factor B and by a signal inversion. As will be readily apparent to the person skilled in the art the integrator shown in Figure 3 is a Backward Euler Integrator. The arrangement shown in Figure 4 will give the transfer function between the input current i₁ applied to input 31 and the output current i o derived from output 33 of the Forward Euler Ideal Integrator. The arrangement differs from that shown in Figure 3 in that the input 31 is connected to the junction of the current source 34 and the drain electrode of transistor T31 instead of to the junction of the drain electrodes of transistors T32 and T33. Using the same assumptions as with respect to the arrangement of Figure 3 similar analysis can be performed. During phase ⊘2 of sampling period n-1 the current I₂ produced by transistor T32 is defined by the relationship I₂ = j + i₁(n-1) + 1 A i o (n-1) + B A i₂(n-1) During phase ⊘1 of sampling period n the current I₃ produced by transistor T34 is defined by the relationship I₃ = I₂ - B A i₂ (n) Also It can be seen that the first term corresponds to a Forward Euler Ideal Integrator transfer function while the second term is a feedforward of the input current i₂ applied to input 32 scaled by the factor B and inverted. Figure 5 shows an arrangement for performing an Ideal Bilinear Integration function as well as feedforward from input 32. The difference between the arrangement shown in Figure 4 and that shown in Figure 5 is in the addition of a further input terminal 38 which is connected via a further switch S35 to the junction of the drain electrodes of transistors T32 and T33. The operation of the arrangement can be analysed as follows on the assumption that switch S35 is closed during phase ⊘1 and input 38 is supplied with the current i, and input 31 is supplied with the current -i₁. During phase ⊘2 of sampling period n-1 the current I₂ produced by transistor T32 is defined by the relationship I₂ = j - i₁(n-1) + 1 A i o (n-1) + B A i₂ (n-1) During phase ⊘1 of sampling period n the current I₃ produced by transistor T34 is defined by the relationship I₃ = I₂ - i₁(n) - B A i₂(n) Also i o (n) = A(I₃-j) = A (-i₁(n-1) + B A i₂(n-1) + (n-1) - i₁(n)- B A i₂(n)) i o (z) = - A i₁(z) . 1+z⁻¹ 1-z⁻¹ - B i₂(z) It can be seen that the first term corresponds to an Ideal Bilinear Integrator transfer function while the second term is a feedforward of the input current i₂ applied to input 32 scaled by factor B and inverted. Various modifications can be made to the integrator circuits shown without departing from the scope of the invention. For example if two currents i₂ are available then the input 32 could be split eliminating the need for the switches S33 and S34. Two currents could be derived for example from multiple outputs of a current mirror circuit in the stage providing the input current i₂. The technique could be applied to the fully differential versions of integrators described in one or more of our co-pending applications referred to hereinbefore and to the versions using only one polarity device for conducting signal currents. Also versions of integrators using current conveyors are equally applicable to this invention. Other types of current memory cell may be used in appropriate designs of integrator, for example that shown in Figures 7 to 9 of UK Patent Application No. 8816072 (PHB33477). It should be noted that the current memory cells and current mirror circuits shown have been disclosed in their simplest basic form. If best performance is required a number of enhancements can be employed. This includes using cascoded current mirrors or current memories, using source degeneration resistors, using dynamic element matching, and using current conveyors or current conveyor type current memory cells particularly where current summing occurs at an input. These techniques are disclosed in one or more of our co-pending applications Nos. 8721758 (PHB33385), 8721759 (PHB33386), 8729987 (PHB333426), 8815668.2 (PHB33477), 8828666.1 (PHB33512), 8828668.7 (PHB33513), 8828667.9 (PHB33514), 8903705.5 (PHB33532), ad 8903704.8 (PHB33533). The contents of which are hereby incorporated by reference. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design and use of electrical or electronic circuits and component parts thereof and which may be used instead of or in addition to features already described herein.

Claims: An integrator circuit for integrating input signals having the form of sampled electrical currents, the integrator having an input means for receiving an input signal and an output for making available an output signal and comprising first and second current memory cells, means for connecting the output of the first current memory cell to the input of the second current memory cell, means for connecting a first output of the second current memory cell to the input of the first current memory cell, means for connecting the input means of the integrator to the input of the first and/or second current memory cell, and means for connecting a second output of the second current memory cell to the output of the integrator, wherein the first current memory cell is arranged to produce at its output during a first portion of each sampling period a current related to that applied to its input during a second portion of the preceding sample period and the second current memory cell is arranged to produce at its outputs during a second portion of each sampling period currents related to the current applied to its input during the first portion of the sampling period characterised in that the integrator circuit comprises a further input for receiving a further input signal, the further input being coupled to the input of the first current memory cell during at least the second portion of each sampling period and to the input of the second current memory cell during at least the first portion of each sampling period. An integrator circuit as claimed in Claim 1, in which the further input is coupled to the first current memory cell via a first switch which is closed only during the second portion of each sampling period and is coupled to the second current memory cell via a second switch which is closed only during the first portion of each sampling period, the first and second portions being non-overlapping. An integrator circuit as claimed in Claim 1 or Claim 2, in which the first and/or second current memory cells comprise a current mirror circuit having an input branch comprising a diode connected field effect transistor and an output branch comprising a second field effect transistor, switching means connecting the gate electrodes of the diode connected and second field effect transistors, and voltage storage means associated with the second field effect transistor which maintains the current flow through the second field effect transistor when the switching means is open. An integrator circuit as claimed in any of Claims 1 to 3, in which the input means comprises first and second input terminals, the first input terminal being connected to the input of the first current memory cell and the second input terminal being connected to the input of the second current memory cell via switching means which is closed only during the first portion of each sampling period. An integrator circuit as claimed in any preceding claim, comprising a first current source for providing a bias current to the input of the first current memory cell and a second current source providing a suitably scaled bias current for subtracting from the first and second outputs of the second current memory cell.

Inventors: HUGHES JOHN BARRY, HUGHES, JOHN BARRY
Applicants: PHILIPS ELECTRONICS UK LTD, PHILIPS NV, N.V. PHILIPS' GLOEILAMPENFABRIEKEN, PHILIPS ELECTRONICS UK LIMITED
Application year: 1990
Main classification: G06G7
IPC codes: H03H19, G06G7, G11C27