Photoelectric converting apparatus

Abstract: There is provided a photoelectric converting apparatus comprising: a photoelectric conversion unit; switching means; capacitor means; and an analog memory which stores a first signal from the photoelectric conversion unit and can be accessed at random, wherein the photoelectric conversion unit and the analog memory are formed on the same semiconductor substrate and the first signal is output from the analog memory in correspondence to a second signal which is output from the photoelectric conversion unit.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric converting apparatus and, more particularly, to a photoelectric converting apparatus in which a first signal output from a photoelectric conversion unit is stored and the first signal is output in correspondence to a second signal which is output from the photoelectric conversion unit. Related Background Art In recent years, a video camera using a solid-state image pickup device as an image input device has widely been used. It is considered that this is because the solid-state image pickup device has largely contributed to the realization of the small size, light weight, and low costs of the video camera. Although almost all of the video cameras for public use need colour images, the solid-state image pickup device of a single plate is a main stream from viewpoints of the realization of small size, light weight, and low costs. In the case of obtaining a colour image by using the single plate type solid state image pickup device, in many cases, a chrominance signal is obtained by adhering mosaic colour filters to the solid-state image pickup device. In the case of obtaining an image signal by using such colour filters, when considering only the signal of one horizontal line, all of the chrominance signals do not always exist. Therefore, colour information which does not exist on the horizontal line is obtained from the horizontal line which is one line before. Fig. 1 is a schematic constructional diagram showing an example of a construction of a conventional photoelectric converting apparatus. As shown in the diagram, by inputting R/Boutputs OR/OB of a solid-state image pickup device (photoelectric conversion unit) 7 to a delay element 8, a signal which is one horizontal period before a branch point a on the inputting side is always output to a branch point b on the outputting side of the delay element 8. Therefore, by switching means 10 and 11, signals of R, G, and B are always obtained. There is also a case where a CCD type is mainly used as a delay element 8 and the delay element 8 is formed together with the solid-state image pickup device 7 on the same chip. However, in the above conventional solid-state image pickup device, when a CCD type delay element is used as a delay element, if a sensor unit is constructed by an element other than of CCD type, manufacture becomes complicated, resulting in an increase in costs. On the other hand, in the case of the CCD type, since random access cannot be executed, it is a problem that outputs of the delay elements have to be extracted in the serial inputting order. A photoelectric converting apparatus which comprises a photoelectric converting unit producing serial output signals is known from IEE Transactions on Electron Devices Vol. ED-32 No. 8, August 1985, New York, U.S. pages 1541-1545; Yazuki et al "A 5732 - element linear CCD image sensor". This describes a unit incorporating first and second CCD registers and a storage buffer. The CCD registers are located each side of a bilinear array of photoelectric converting elements. Even number and odd numbered elements are arranged in parallel with a half of one pixel horizontal stagger. Even numbered and odd numbered elements are connected in parallel to the parallel stage inputs of the first and second CCD registers respectively, the storage buffer being interposed between the odd numbered elements and one of the registers. Photoelectrically converted signals are thus input into the registers in parallel and output serially. Signals may thus be output simultaneously and in parallel from the respective CCD registers. No provision is made however for correcting signals produced by defective converting elements. The output signals necessarily follow a predetermined order and are at a predetermined timing. SUMMARY OF THE INVENTION The photoelectric converting apparatus as described hereinbelow provides an alternative means of providing a delayed serial signal to that described with reference to figure 1. Apparatus in accordance with the present invention is defined in the appended claims. Conveniently, the photoelectric conversion unit and the analog memory can be formed on the same semiconductor substrate. For instance, if the photoelectric conversion unit and the analog memory are constructed by MOS type transistors or the like, they can be formed by the same process. Therefore, the apparatus can be easily manufactured and the apparatus in which the photoelectric conversion unit and the analog memory have the same characteristics can be obtained. While the switching means may be controlled solely by a shift-register, in the preferred construction of this apparatus the switching means is controlled by a shift-register and by a separate pulse generating circuit. The latter allows arbitrary selection of selected signals stored by the capacitor means at an arbitrary timing and thus affords flexibility in the processing which is available. While the analog memory of the aforesaid apparatus may comprise capacitors and pluralities of first and second switches it is mentioned that similar arrangements of capacitors and switches have been known in the circuit construction of sequential output photoelectric converting units, see for example U.S. Patent 4,831,451 and JP-A-57065074 (Patent Abstracts of Japan, vol. 6 No. 140 (E-121)(1028)). BRIEF DESCIRPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing an example of a construction of a conventional solid-state image pickup device; Fig. 2A is a schematic circuit constructional diagram of the first embodiment of a photoelectric converting apparatus according to the invention; Fig. 2B is a timing chart for explaining the operation of the photoelectric converting apparatus; Fig. 3 is an explanatory diagram showing a construction of pixels of the photoelectric conversion unit; Fig. 4 is a schematic constructional diagram of the second embodiment of a photoelectric converting apparatus of the invention; Fig. 5 is a schematic circuit constructional diagram of the third embodiment of a photoelectric converting apparatus of the invention; Fig. 6 is a timing chart for explaining the operation of the photoelectric converting apparatus of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 2A is a schematic circuit contructional diagram of the first embodiment of a photoelectric converting apparatus of the invention. In the diagram, reference numeral 1 denotes a photoelectric conversion unit to output an electric signal corresponding to the incident light. The unit 1 includes a plurality of photoelectric conversion elements. Reference numeral 2 indicates a shift register to drive the photoelectric conversion unit 1 and an analog memory 3; H 0 to H N represent output lines of the shift register 2; L 1 a signal output line of the photoelectric conversion unit 1; and L 2 a memory output line of the analog memory 3. In the analog memory 3, C 1 to C N denote accumulation capacitors each for temporarily holding and storing a signal which is output to the signal output line L 1 . T 11 to T 1N denote switches such as MOS transistors or the like for turning on/off the signal output line L 1 and the accumulation capacitors C 1 to C N by output pulses O 1 to O N which are output to the output lines H 1 to H N of the shift register 2. L 3 and L 4 indicate memory output lines to output memory outputs; T 21 and T 2N denote switches such as MOS transistors or the like to turn on/ off the accumulation capacitors C1 to CN and the memory output lines L 3 and L 4 by the output pulses O 0 to O N-1 which are output to the output lines to H 0 to H N-1 of the shift register 2; T 3 and T 4 sample and hold MOS transistors to sample and hold the signals on the memory output lines L 3 to L 4 ; Ø 3 and Ø 4 gate pulses to control the turn on/off operations of the sample and hold MOS transistors T 3 and T 4 ; T 1 and T 2 resetting MOS transistors to reset the memory output lines L 3 and L 4; Ø 1 and Ø 2 gate pulse to control the on/off operation of the resetting MOS transistors T 1 and T 2 . The operation of the photoelectric converting apparatus will now be described hereinbelow with reference to Figs. 2B and 3. Fig. 2B is a timing chart for explaining the operation of the photoelectric converting apparatus. Fig. 3 is an explanatory diagram showing a construction of pixels in the photoelectric conversion unit. In Fig. 3, reference numerals 41 to 4N and 51 to 5N indicate pixels of successive horizontal lines. It is now assumed that after the output signals corresponding to the incident light had been output to the output line L 1 from the pixels 41 to 4N in the photoelectric conversion unit 1, they were held and stored into the accumulation capacitors C 1 to C N in the analog memory 3. When the shift register 2 starts operating and the pulse O 0 is supplied to the output line H 0 , the switch T 21 is turned on and a signal O L3 corresponding to the pixel 41 accumulated in the capacitor C 1 is output to the output line L 3 . When the pulse O 1 is then supplied to the output line H 1 and the pulse ⊘ 3 is supplied to the sample and hold MOS transistor T 3 , a signal O L1 of the pixel 51 is output from the photoelectric conversion unit 1 to the output line L 1 , the switch T 11 is turned on, and the signal corresponding to the pixel 51 is accumulated into the capacitor C 1 . On the other hand, since the switch T 22 is also turned on, a signal O L4 corresponding to the pixel 42 accumulated in the capacitor C 2 is output to the output line L 4 . Since the sample and hold MOS transistor T 3 is ON, the signal O L3 corresponding to the pixel 41 which has been output to the output line L 3 is taken out as an output signal O L2 from the output line L 2 . Then, when the resetting pulse Ø 1 is supplied, the output line L 3 is reset. After that, when the pulse O 2 is supplied from the shift register 2 to the output line H 2 and the sampling and holding pulse Ø 4 is supplied, the signal O L1 corresponding to the pixel 52 is output from the output signal line L 1 and the signal corresponding to the pixel 52 is accumulated into the capacitor C 2 through the switch T 12 . At this time, the signal O L3 corresponding to the pixel 43 accumulated in the capacitor C 3 is output to the output line L 3 . The signal O L4 corresponding to the pixel 42 which has been output to the output line L 4 is transmitted through the sample and hold MOS transistor T 4 and is output as an output signal O L2 to the output line L 2 . Then, the resetting pulse Ø 2 is supplied and the output line L 4 is reset. By repeating the operations similar to the above hereinafter, the signals O L1 and O L2 which are shifted by one horizontal period are simultaneously continuously output from the output lines L 1 and L 2 . Fig. 4 is a schematic constructional diagram of the second embodiment of a photoelectric converting apparatus of the invention. The same parts and components as those shown in Fig. 2A are designated by the same reference numerals. Reference numeral 1 indicates a photoelectric conversion unit to output a signal corresponding to the input image and also simultaneously output an output signal in a state in which no incident light is irradiated. L 5 indicates an output line to output a dark output. After the photoelectric conversion unit 1 generated an output S+N (including a noise signal N) corresponding to image information S to the output line L 1 , the unit 1 resets the pixels for one horizontal period and drives so as to output a dark output N. The dark output (noise output) N is delayed by one horizontal period than the image output (signal + noise output) S+N. At this time, therefore, if the analog memory 3 is driven in a manner similar to the first embodiment, the image output (signal + noise output) S+N which was delayed by one horizontal period is output from the memory output line L 2 . Therefore, by executing an arithmetic operating process to subtract the dark output N from the image output S+N, fixed pattern noise of the photoelectric conversion unit 4 can be eliminated. Fig. 5 is a schematic circuit constructional diagram of the third embodiment of a photoelectric converting apparatus of the invention. The same parts and components as those shown in Fig. 2A are designated by the same reference numerals. In the diagram, reference numeral 3 denotes an analog memory; 6 indicates a memory control pulse generating circuit; and M 1 to M N memory control pulses outputs, Fig. 6 is a timing chart for explaining the operation of the photoelectric converting apparatus. It is now assumed that the photoelectric conversion unit 1 outputs the output signals corresponding to the incident light from the pixels 41 to 4N of one horizontal period to the output line L 1 and the signals 41 to 4N are simultaneously accumulated into the capacitors C 1 to C N and, thereafter, the output signals corresponding to the incident light are output from the pixels 51 to 5N of the next line including defective pixels 51 and 52. As shown in Fig. 6, before the signals corresponding to the defective pixels 51 and 52 are output from the photoelectric conversion unit 1 to the output line L 1 , the signals of the pixels 41 and 42 are read out of the accumulation capacitors C 1 and C 2 to the output lines L 3 and L 4 by output pulses O M1 and O M2 from output lines M 1 and M 2 of the memory control pulse generating circuit 6. When the signal of the pixel 51 is output to the output line L 1 , by turning on the sample and hold MOS transistor T 3 , the signal O L3 of the pixel 41 is output as an output signal O L2 to the output line L 2 . In a manner similar to the above, when the signal of the pixel 52 is output, the signal O L4 of the pixel 42 is also output as an output signal O L2 to the output line L 2 . In this manner, the defective pixel can be corrected at an arbitrary timing. As described in detail above, according to the photoelectric converting apparatus of the invention, the first signal which is output from the photoelectric conversion unit is stored in the analog memory and the first signal stored can be output from the analog memory at a desired timing in correspondence to the second signal which is output from the photoelectric conversion unit. On the other hand, by using the analog memory, the photoelectric conversion unit and the analog memory can be also formed onto the same semiconductor substrate. For instance, if the photoelectric conversion unit and the analog memory are constructed by MOS type transistors or the like, they can be formed by the same process. Therefore, the apparatus can be easily manufactured and the apparatus in which the sensor unit and the memory unit have the same characteristics can be obtained. There is a large effect such that a system in which the small size, low costs, and multifunctions are realized can be accomplished.

Claims: A photoelectric converting apparatus comprising: a photoelectric conversion unit (1) including a plurality of photoelectric conversion elements and means of sequentially outputting photoelectrically converted signals (41-4N, 51-5N), produced by said photoelectric conversion elements, on a first output line (L1); which apparatus is characterised by: an analog memory (3) including capacitor means (C 1 -C N ), and switching means (T 11 -T 1N, T 21 -T 2N ) responsive to address signals (0 1 -0 N , 0 o -0 N-1 ; 0 0 -0 N , 0 M1 -0 MN ), for receiving and storing a first plurality (41-4N) of the photoelectrically converted signals (41-4N, 51-5N) sequentially output on said first output line (L1), and for outputting selected signals (41-4N; 41,42) of said first plurality (41-4N) of the photoelectrically converted signals (41-4N, 51-5N); and control means (2; 2,6), co-operative with said switching means (T 11 -T 1N , T 21 -T 2N ), for supplying said address signals (0 1 -0 N , 0 0 -0 N-1 ; 0 1 -0 N , 0 M1 -0 MN ) to control the outputting of said selected signals (41-4N; 41,42) from said capacitor means (C 1 -C N ) while a second plurality (51-5N) of the photoelectrically converted signals (41-4N, 51-5N) are sequentially output from said photoelectric conversion unit (1) on said first output line (L 1 ), and received by said analog memory (3). An apparatus as claimed in claim 1 wherein said photoelectric conversion unit (1) and said analog memory (3) are provided on a common semiconductor substrate. An apparatus as claimed in either claim 1 or 2 wherein said first output line (L1) is connected to an output terminal of said apparatus. An apparatus as claimed in any preceding claim wherein said control means (2,6) is operable to supply address signals (0 M1 ,0 M2 ) to said switching means (T 21 ,T 22 ) to select and control the outputting of selected signals (41,42) for replacing defective element signals (51,52) amongst said second plurality (51-5N) of the photoelectrically converted signals (41-4N, 51-5N). An apparatus as claimed in either claim 1 or 2 wherein: said photoelectric conversion unit (1) is operable to provide a dark noise signal at an output (L5) thereof in a state when no light is incident thereupon; and said apparatus includes arithmetic operating means connected to said output (L5) of said photoelectric conversion unit (1) and to said analog memory (3) to subtract said dark noise signal output at said output (L5) of said photoelectric conversion unit (1) from said selected signals (41-4N; 41,42) output from said analog memory (3). An apparatus as claimed in claim 1 wherein said analog memory (3) comprises: first and second pluralities of capacitors (C 1 ,C 3 , .., C N-1 and C 2 , C 4 , .., C N ) each of which capacitors (C 1 -C N ) is connected to said first output line (L1) via a respective one of a plurality of first switches (T 11 -T 1N ); and output means (T 21 -T 2N , T 1 -T 4 , L 2 -L 4 ) including a second output line (L2), a plurality of second switches (T 21 -T 2N ) connected to said first and second pluralities of capacitors (C 1 , C 3 , ..., C N-1 and C 2 , C 4 , ..., C N ), and alternation means (T 1 -T 4 , L 3 , L 4 ), connected between said plurality of second switches (T 21 -T 2N ) and said second output line (L2), for alternately outputting said selected signals (41-4N; 41,42) stored by said first and second pluralities of capacitors (C 1 , C 3 , ..., C N-1 and C 2 , C 4 , ..., C N ) on said second output line (L2). An apparatus as claimed in claim 6 wherein said alternation means (T 1 -T 4 , L 3 , L 4 ) comprises: a third output line (L3) connected via respective odd ones of said second switches (T 21 , T 23 , ..) to said first plurality of capacitors (C 1 , C 3 , ..); a fourth output line (L4) connected via other respective even ones of said second switches (T 22 , T 24 , ..) to said second plurality of capacitors (C 2 , C 4 , ..); respective reset switches (T 1 , T 2 ) connected to said third and fourth output lines (L 3 , L 4 ); and respective, alternately operable, output switches (T 3 , T 4 ) connected between both third and fourth output lines (L 3 , L 4 ) and said second output line (L 2 ). An apparatus as claimed in claims 6 or 7 wherein said control means (2; 2,6) comprises a shift register (2) successive stage outputs (H 1 -H N ) of which are connected to respective control gates of successive ones of said plurality of first switches (T 11 -T 1N ), which successive first switches (T 11 , T 12 , ...) are connected to respective capacitors (C 1 , C 2 , ..) alternately of said first and second pluralities of capacitors (C 1 ,C 3 , and C 2 , C 4 ...). An apparatus as claimed in claim 8 wherein successive stage outputs (H 0 -H N-1 ) of said shift register (2) are connected to respective control gates of successive ones of said plurality of second switches (T 2 -T 2N ), which successive second switches (T 21 , T 22 , ..) are connected to respective capacitors (C 1 , C 2 , ...) alternately of said first and second pluralities of capacitors (C 1 , C 3 , ... & C 2 , C 4 , ...) so that the second and first switches (T 21 and T 11 ; ..., T 2N and T 1N ) connected to each respective capacitor (C 1 , .... C N ) are connected to successive stage outputs (H 0 & H 1 , ..., H N-1 , & H N ) of said shift register (2). An apparatus as claimed in claim 8 wherein said control means (2,6) comprises also a pulse generating circuit (6) having parallel outputs (M 1 -M N ) connected to respective control gates of successive ones of said plurality of second switches (T 21 -T 2N ).

Inventors: SHINOHARA MAHITO C O CANON K K, YUSHIYA AKIHIKO C O CANON K K, SHINOHARA, MAHITO, C/O CANON K.K., YUSHIYA, AKIHIKO, C/O CANON K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H04N5
IPC codes: H04N3, H04N5, H04N9