Signal processing device

Abstract: A signal processing device in which compressed encoded information obtained by encoding an input information signal based on use of correlation between components thereof is written in a memory capable of simultaneously performing write and read operations, and the encoded information read out from the memory is decoded to restore the information signal while signal processing is effected by using the information signal prior to the encoding and the decoded information signal.

Description: Background of the Invention: Field of the Invention: This invention relates generally to data processing devices and, more particularly, to a data processing device for effecting digital information processing by using a large-capacity memory. Description of the Related Art: Recently, the bit unit cost of memories is greatly reduced, and apparatus which are manufactured at comparatively low costs for home or personal use but which have large-capacity memories such as field or frame memories for video signal processing are therefore increasing. Fig. 1 schematically shows the arrangement of a conventional video signal processing circuit having such a large-capacity memory. This arrangement includes an analog video signal input terminal 100, an A/D converter 101 for digitizing an input analog video signal, a signal processing circuit 102 for processing the digitized video signal, a D/A converter 103 for converting the digital video signal processed by the signal processing circuit 102 into an analog signal, a field memory 104 for effecting digital signal exchange with the signal processing circuit 102, a sync separation circuit 105 for separating a sync signal from the digital video signal supplied from the A/D converter 101, and a memory control circuit 106 for controlling the timing of write and read operations of the field memory 104 by the timing in accordance with the sync signal separated by the sync separation circuit 105. In the arrangement shown in Fig. 1, various kinds of processing can be performed by selecting the construction of the signal processing circuit 102 and write/read patterns for the field memory 104. In a VTR system, for example, special reproduction such as still reproduction or slow reproduction can be performed based on intermittently writing and continuously reading. Also, noise reduction processing of a field cycle type or composition processing using the image corresponding to the output from the A/D converter 101 and the image corresponding to the output from the field memory 104 can be performed based on continuously performing both write and read. The composition processing is, for example, wipe or fade processing. Examples of systems for effecting these kinds of processing are known; an example of the above special reproduction is disclosed in JP-A-63 073 784, an example of noise reduction processing is disclosed in JP-A-1 194 578, and an example of composition processing is disclosed in JP-A-2 121 475. Details of these systems will not be described in this specification because the internal arrangement of the signal processing circuit 102 does not directly relate to the present invention. In the above-described arrangement, a capacity of 8 (bits) x 256 k (samples) = 2M (bits) is needed for storing television signals such as NTSC signals or PAL signals in the field memory 104 without substantial deterioration of the signal. Although the development of large-capacity memories is promoted recently which reducing the unit cost, the price of memories having a capacity of 2 Mbits is high and it is rather difficult to use such a memory for home or personal apparatus. Summary of the Invention: In view of these circumstances, an object of the present invention is to provide a data storage device which enables application of signal processing using a large-capacity memory to home or personal appliances. Another object of the present invention to provide a small and low-cost signal processing device having a memory capacity for one picture. To achieve these objects, the present invention provides a data processing device as set out in claim 1. Other objects and features of the present invention will become more clear upon reading the following description of embodiments of the present invention taken in conjunction with the accompanying drawings. Brief Description of the Drawings: Fig. 1 is a schematic diagram of the construction of a conventional video signal processing circuit using a large-capacity memory; Fig. 2 is a schematic diagram of the construction of an example of a video signal processing circuit in accordance with the present invention; Fig. 3 is a diagram of the construction of an encoding unit of a preceding value prediction encoding type; Fig. 4 is a diagram of the construction of a decoding unit mating with the encoding unit shown in Fig. 3; Fig. 5 is a diagram of the construction of another example of the video signal processing circuit in accordance with the present invention; Fig. 6 is a block diagram of the construction of an example of a data processing device in accordance with the present invention; and Fig. 7 is a block diagram of the construction of another example of the data processing device in accordance with the present invention. Detailed Description of the Preferred Embodiments: The present invention will be described below with respect to embodiments thereof. In accordance with the present invention, the amount of data to be stored in the field memory may be reduced by effecting data compression using correlation of the data to enable a reduction in the necessary capacity of the field memory. For example, if the amount of data is compressed into half, the capacity of the field memory can be limited to 1 Mbits. In this case, however, it is necessary to provide high-efficiency encoder and decoder circuits at the front and rear of the field memory. Fig. 2 schematically shows the construction of an example of a video signal processing circuit in accordance with the present invention in which the amount of data is reduced by such high-efficiency encoding and efficient-encoding codes are thereafter stored in the memory. In Fig. 2, components identical or corresponding to those shown in Fig. 1 are indicated by the same reference numerals and the description for them will not be repeated. In Fig. 2, reference numerals 110 and 111 denote a high-efficiency encoder and a high-efficiency decoder, respectively, which are provided at the front and rear of the field memory 104 as shown in the figure and which can be operated simultaneously. In a case where the amount of data is reduced based on high-efficiency encoding to reduce the capacity of the memory, the meaning of reducing the memory capacity is lost if devices or circuits having excessively complicated constructions are used as the encoder 110 and the decoder 11. For this reason, a coding method using a simple arrangement, e.g., differential predictive coding method (DPCM) is suitable for high-efficiency encoding using the arrangement shown in Fig. 2. DPCM is a data compression method based on utilization of a high degree of correlation between adjacent sampled values obtained by sampling a video or audio signal. The encoding operation of this method resides in a process in which a decoded value corresponding to a sampled value already transmitted is used to obtain a prediction value for a sampled value which is to be encoded next, and the value of the difference between the prediction value and the sampled value (prediction error) is quantized. The quantization characteristic may be made non-linear to limit the deterioration of the data to a minimum level even if the number of bits of the difference value is set to about 1/2 of the number of bits of the input sampled value. Various types of DPCM using different systems of producing the prediction value have been proposed. Fig. 3 shows the construction of an encoding unit having preceding value prediction encoding system which is the simplest among them. In the preceding value prediction encoding system, the decoded value corresponding to the sampled value one time previous is used as the prediction value. Referring to Fig. 3, a sampled value Xi input through a terminal 201 is applied to a subtracter 202, and a prediction value (decoded value of the preceding value) described later is subtracted therefrom. A quantizer 203 quantizes the difference value which is the output from the subtracter 202 and outputs an encoded code Yi through an output terminal 204. The encoded code Yi is also applied to a reverse quantizer 205. The reverse quantizer 205 converts the encoded code Yi into a difference value (quantized representative) and applies the same to an adder 206. The adder 206 adds the prediction value to this difference value to restore the input sampled value. Because the restored input sampled value contains a quantization error, it may be a value which is impossible in reality. Then, the amplitude of the output from the adder 206 is limited within the range of the original input sampled value by a limiter 207 and is applied as a locally decoded value to a D-flip-flop 208 serving as a predictor. Since in this example the preceding-value-decoded value is used as the prediction value, a D-flip-flop for simply effecting delay of data is used as the predictor. The D-flip-flop 208 applies the locally decoded value as the prediction value to the subtracter 202 and the adder 206 in the next clock cycle. Figs. 4 shows the construction of an example of a decoding unit mating with the encoding unit shown in Fig. 3. Referring to Fig. 4, the encoded code Yi obtained by the encoding unit is input through an input terminal 301 and is applied to a reverse quantizer 205. Each of this reverse quantizer 205, an adder 206, a limiter 207 and D-flip-flop 208 of this unit has the same function as the block of the encoding unit of Fig. 5 indicated by the corresponding reference numeral. The output from the limiter 207 of this decoding unit is output through an output terminal 302 as a decoded value. In the DPCM encoding system, the locally decoded value and the prediction value obtained in the encoding unit respectively coincide with the decoded value and the prediction value obtained in the decoding unit which correspond time-wise to the former. The reason for saying that these values correspond time-wise to each other is that the decoded value and the prediction value obtained in the decoding unit are delayed relative to the locally decoded value and the prediction value obtained in the encoding unit. If error occurs in the encoded code by the influence of noise of the like during transmission of this code, the decoded value and the prediction value obtained in the decoding unit deviate from the normal values and become different from the time-wise corresponding locally decoded value and prediction value in the encoding unit, thereby producing difference components. Even if no transmission error further occurs, the difference components are maintained (propagated) as errors. To cope with such transmission errors, the operations of the encoding unit and the decoding unit are periodically initialized to prevent, for the subsequent data, propagation of the difference components (errors) produced with code errors. For example, a method of transmitting data without prediction encoding or a method of setting the time-wise corresponding predictors used in the encoding and decoding devices are set to certain set values have been proposed. Fig. 5 shows the construction of an example of a processing circuit in accordance with the present invention in which an encoding unit and a decoding unit which performs operations for this initialization are provided at the front and the rear of the field memory. Referring to Fig. 5, this processing circuit has a digital data input terminal 401, a subtracter 403, a quantizer 405, reverse quantizers 409 and 423, predictors 413 and 249 constituted by limiters and D-flip-flops as described above in the case of preceding value prediction, adders 411 and 427, and another subtracter 403. These components function in the same manner as the corresponding components of the encoding and decoding units described with reference to Figs. 3 and 4. The circuit shown in Fig. 5 also has a field memory 421, a sync signal generator 415, a data selector 407, a timing signal generator 417 for initializing the operation of the predictor 413 and for controlling the selector 407, and a sync signal detector 425. Ordinarily, the selector 407 selects an encoded code output from the quantizer 405 and transmits the selected code to the field memory 421. Prior to the initialization of the operation of the predictor 413 in the encoding unit, the selector 407 selects the signal output from the sync signal generator 415 based on the control signal supplied from the timing signal generator 417, and transmits the selected signal to the field memory 421. After the transmission of this sync signal has been effected for a predetermined period of time, a reset signal is applied from the timing signal generator 417 to the predictor 413. In response to this signal, the predictor 413 sets the prediction value to a certain set value to effect the operation initialization. At this time, the subtracter 403 outputs the value of the difference (prediction error) between input data (hereinafter referred as "top data") from the terminal 401 and the set value, and the quantizer 405 outputs an encoded code (hereinafter referred to as "top code") obtained by quantizing this difference value. The selector 407 is then changed over by the control signal form the timing signal generator 417 to transmit this top code to the field memory 421 subsequently to the sync signal. Thereafter, encoded codes are successively transmitted. On the other hand, on the side of the decoding unit, the above-mentioned sync signal is detected with the sync signal detector 425 from the signal output from the field memory 421. In synchronism with the detection of the sync signal, the operation of the predictor 429 is initialized by a predetermined timing. That is, the prediction value is set to the above-mentioned set value. This predetermined timing corresponds to the timing by which the top code is input into the reverse quantizer 423. The output from the reverse quantizer 423 obtained at this time has a value obtained by reversely quantizing the value quantized form the value of difference between the top data and the set value. Accordingly, the top data is decoded by adding the set value to this output value with the adder 427. Once the top data is decoded, the subsequent data can be decoded. In the arrangement shown in Fig. 5, the sync signal generator 415 and the data selector 407 are required for circuit initialization on the side of the encoding unit, and the sync signal detector 425 is specially required for initialization of the predictor on the side of the decoding unit. This arrangement is ineffective in terms of circuit design. Also, there is a possibility of failure to correctly performing the above initializing operation owing to errors in the sync signal input to or output from the field memory. Fig. 6 is a block diagram of the construction of an example of a signal processing device in accordance with the present invention. This signal processing device has a digital video data input terminal 10, a subtracter 12, a quantizer 14, reverse quantizers 16 and 24, adders 18 and 26, predictors 20 and 28, a digital video data output terminal 30, an input terminal 32 for receiving horizontal and vertical sync signals in the input video signal, a memory control signal generator 34, a field memory 22 constituted by a first-in/first-out type image memory (hereinafter referred to simply as "FIFO"). Ordinarily, the FIFO is controlled by six types of control signal alone, which are write clock, read clock, write enable signal, read enable signal, write reset signal, and read reset signal. Of these signals, only the write reset signal and the read reset signal directly relate to the present invention, and the other signals are therefore not shown. If the write reset signal is applied to the FIFO 22, data thereafter input into the FIFO 22 is written from the top address in the memory. If the read reset signal is applied to the FIFO 22, data thereafter output is successively read out from the top address of the memory to be output. The write reset signal and the read reset signal are produced by the memory control signal generator 34 one time for each one field by the timing in accordance with the horizontal and vertical sync signals input through the terminal 32. In this embodiment, when the write reset signal is applied to the FIFO 22 via a write reset line 36, it is simultaneously applied to the predictor 20, and the output from the predictor 20 is set to the above-mentioned set value. Consequently, the encoded code output from this DPCM encoder (from the quantizer 14) becomes the code (top code) obtained by quantizing the value of the difference between this set value and the input data (top data) and is written in the top address of the FIFO 22. Similarly, when the read reset signal is applied to the FIFO 22 via a read reset line 38, it is simultaneously applied to the predictor 28, and the output from the predictor 28 is set to the above-mentioned present value. Accordingly, the output from the FIFO 22 is the above-mentioned top code. This code is reversely quantized by the reverse quantizer 24 to restore the difference value, and the restored difference value and the set value output from the predictor 28 are added to each other by the adder 26, thereby restoring the above-mentioned top data. Once this top data is restored, the whole of subsequent data can be decoded by the ordinary processing of the encoded codes thereafter output from the FIFO 22. Fig. 7 shows the construction of another example of the signal processing device in accordance with the present invention. In Fig. 7, components identical or corresponding to those shown in Fig. 6 are indicated by the same reference numerals and the description for them will not be repeated. The difference between the embodiment shown in Fig. 7 and the embodiment shown in Fig. 6 resides in that an image memory 23 of the former is not an FIFO but a random access type image memory (hereinafter referred to simply as "RAM"). Correspondingly, address information for controlling write/read addressing of the RAM 23 is required, and a write address generator 40 for designating the write address and a read address generator 41 for designating the read address are provided. Each address data is applied to the RAM 23 via a line 42 or 43. The write address generator 40 resets the output write address data to the data corresponding to the initial address by the write reset signal supplied from the memory control signal generator 34 as also described with respect to the embodiment shown in Fig. 6. Similarly, the read address generator 41 resets the output read address data to the data corresponding to the initial address by the read reset signal supplied from the memory control signal generator 34. As in the case of the embodiment shown in Fig. 6, the output from the predictor 20 is set to the above-mentioned set value by the application of the write reset signal, and the output from the predictor 28 is set to the above-mentioned set value by the application of the read reset signal. The operations of the other components are the same as the embodiment shown in Fig. 6. Consequently, the encoded code (top code) produced by the quantizer 14 immediately after the resetting of the predictor 20 is stored in the initial address of the RAM 23, and this top code is read out from the RAM 23 simultaneously with the resetting of the predictor 28 of the decoding unit. Thus, in the embodiment shown in Fig. 7, the top data can be decoded with reliability as in the case of the embodiment shown in Fig. 6, and sampled values corresponding to subsequent encoded codes can be decoded without failure. In the data storing devices in accordance with above described embodiments, the initialization of the write operation of the memory and the initialization of the operation of the DPCM encoding unit are synchronized, thereby enabling the decoding operation of the decoding unit to be initialized by the timing corresponding to that of the initialization of the encoding unit. Thus, the operation of the decoding unit can be initialized with improved reliability by the circuit arrangement is simplified. In the above-described embodiments, preceding-value-difference encoding is conducted as prediction coding. However, an arrangement such as that shown in Fig. 6 or 7 is very effective so long as it is used for a prediction coding circuit having a comparatively simple circuit arrangement and requiring initialization of the decoding operation on the decoding side. The field memories are used as the memories of the above-described embodiment and the prediction encoding unit and the decoding unit are provided at the front and rear of the memory. However, in a case where components such as a delay circuit and a data selector are provided between the memory and the encoding and decoding units for convenience of processing, the present invention can be applied in the same manner while considering the time delay owing to this circuit arrangement. For example, in a case where a one-horizontal-scanning-term delay line exists between the quantizer 14 and the FIFO 22 of the device shown in Fig. 6, the timing of initialization of the predictor 20 may be set so as to be faster than the timing of resetting of the FIFO 22 by one horizontal scanning term. As described above with respect to the signal processing devices shown in Figs. 6 and 7, initialization on the decoding side can be performed with improved reliability by using a simple circuit arrangement even if memory write errors occurs. A signal processing device in which compressed encoded information obtained by encoding an input information signal based on use of correlation between components thereof is written in a memory capable of simultaneously performing write and read operations, and the encoded information read out from the memory is decoded to restore the information signal while signal processing is effected by using the information signal prior to the encoding and the decoded information signal.

Claims: A data processing device comprising: (a) encoding means (110) for encoding an information signal by utilizing correlation between components thereof to output encoded information having a compressed information content; (b) a memory (104; 421; 22; 23) being used for write and read of the encoded information, said memory (104; 421; 22; 23) is capable of performing the read-out operation while performing the writing operation; (c) decoding means (111) for decoding the encoded information read out from said memory (104; 421; 22; 23) to restore the information signal; and (d) signal processing means (102) for effecting signal processing by simultaneously using the information signal input into said encoding means (110) and the information signal output from said decoding means (111). A device according to claim 1, wherein the information signal is a video signal, and said memory (104; 421; 22; 23) has a capacity for storing at least one picture of the video signal. A device according to claim 2, further comprising memory control means (105; 106; 34) including a separation circuit (105) for separating a synchronizing signal from the video signal input into said encoding means (110), said memory control means (105; 106; 34) controlling write and read with said memory (104; 421; 22; 23) by using the sync signal separated by said separation circuit. A device according to claim 1, wherein said encoding means (110) includes a predictive differential encoding circuit (208; 413; 20). A device according to claim 4, wherein said encoding means (110) further includes a timing circuit (417) for determining the timing of resetting of a predicting operation of said predictive differential encoding circuit (413). A device according to claim 5, wherein said encoding means (110) further includes a synchronizing signal addition circuit (407) for adding a synchronizing signal to the encoded information by the timing corresponding to the timing of resetting of the predicting operation of said timing circuit (417). A device according to claim 6, wherein said decoding means (111) includes a predictive differential decoding circuit (28) for decoding the encoded information read out from said memory (22), a separation circuit for separating the synchronizing signal from said encoded information input into said decoding circuit (28), and a timing circuit (34) for determining the timing of resetting of a predicting operation of the decoding circuit (28) by using the synchronizing signal separated by said separation circuit. A device according to claim 4, further comprising timing control means (34) for controlling the timing of resetting of write in said memory (22) and the timing of resetting of read from said memory (22). A device according to claim 8, wherein the information signal is a video signal, and said timing control means (34) includes a separation circuit for separating a synchronizing signal from the input video signal, said timing control means (34) controlling the write reset timing by using the synchronizing signal separated by said separation circuit. A device according to claim 8, wherein said timing control means (34) resets a predicting operation of said predictive differential encoding circuit (20) by the timing corresponding to the write reset timing. A device according to claim 10, wherein said decoding means includes a predictive differential decoding circuit (28) for decoding the encoded information read out from said memory (22; 23) and said timing control means (34) resets a predicting operation of said decoding circuit (28) by the timing corresponding to the read reset timing. A device according to any of the claims 8 to 11, wherein said timing control means (34) controls first timing for resetting a predicting operation of said encoding means (20), second timing for resetting a write operation of said memory (22; 23) third timing for resetting a predicting operation of said decoding means (28) and or fourth timing for resetting a read operation of said memory (22; 23), said first timing and said second timing being synchronized with each other, said third timing and said fourth timing being synchronized with each other. A device according to claim 12, wherein said timing control means (34) is arranged to equalize the number of times of resetting of the predicting operation of said encoding means (20) and the number of times of resetting of write in said memory (22; 23) and or to equalize the number of times of resetting of the predicting operation of said decoding means (28) and the number of times of resetting of read from said memory (22; 23). A device according to claim 12, wherein said memory is a first-in/first-out memory (22), the second timing is timing for resetting the operation of writing in said first-in/first-out memory (22), and the fourth timing is timing for resetting the operation of reading from said first-in/first-out memory (22). A device according to claim 12, wherein said memory is a random-access memory (23), the second timing is timing for resetting write addresses of said random-access memory (23), and the fourth timing is timing for resetting read addresses of said random-access memory (23).

Inventors: TADAYOSHI NAKAYAMA, TADAYOSHI, NAKAYAMA, TADAYOSHI, NAKAYAMA, C/O TAMAGAWA JIGYOSHO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H04N5
IPC codes: G06T9, H04N7, H04N5