Dram cell with trench capacitor and buried lateral contact

Abstract: A DRAM cell with a trench capacitor having a first plate (22,24) formed as a diffusion on the outside surface of a trench and a second plate (field plate 28) formed inside the trench is fabricated. The transfer transistor is in a self-aligned moat area that slightly overlaps the capacitor area and allows for increased misalignment tolerance. The field plate is used as implantation mask for the moat region. It has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers. The bitline contact is self-aligned. In another embodiment, a planar capacitor is used. In a third embodiment two conductive plates are formed inside a trench. A sidewall insulator technique using two selectively etchable materials is used to provide a less destructive fabrication technique for forming sidewall insulating layers and allowing the use of gate insulator layer to protect the surface of the substrate during the formation of the sidewall insulating layers.

Description: FIELD OF THE INVENTION The present invention relates to the field of integrated circuit design and fabrication. More specifically, the present invention relates to the field of dynamic random access memory arrays, cells and other structures and the methods for fabricating those structures. BACKGROUND OF THE INVENTION The quest to develop smaller and smaller dynamic random access memory (DRAM) cells and related structures is a well-known goal. In integrated circuit manufacturing, certain costs are relatively fixed no matter what integrated circuit is fabricated. Thus, the greater density of memory on a single integrated circuit provides greater economy on a per bit basis by spreading these fixed costs across more memory capacity. In addition, greater memory storage capacity allows greater memory capacity of the end user products, such as computers, in a smaller package. Therefore, the value to the customer is increased. Because 50% or more of the area of a DRAM is used for memory cells themselves, reduction of the memory cell size allows for far greater numbers of those memory cells to be placed on the DRAM. Several techniques have been developed to try to reduce the size of memory cells. For example, the fundamental dynamic random access memory cell has been reduced to a minimum of components, i.e. a transistor and a capacitor connected to the source of the transistor. The transistor allows access to the charge stored on the capacitor and the stored charge represents data The first step in reducing the size of DRAM cells was the effective integration of the transfer transistor and the capacitor. An example of this is found in Kuo, "Random Access Memory Cell with Different Capacitor and Transistor Oxide Thickness", U.S. Patent No. 4,240,092, issued December 16, 1980 and assigned to the assignee of this application. Kuo is an example of a "HyC" cell. As the density of DRAMs increased, limitations of the Hy-C cell became apparent. In order to provide accurate data storage and retrieval, the capacitance of the storage capacitor must be as large as possible. However, the capacitance of the storage capacitor is directly proportional to the area between the plates of the capacitor. In a planar capacitor cell, like the Hy-C cell, this creates a fundamental tradeoff between cell size and cell capacitance. In order to minimize the surface area occupied by the memory cell while maintaining adequate storage capacitor capacitance, vertical capacitor structures were developed. An example of such a structure is found in Sunami, "Cell Structures for Featured DRAMs", International Electron Devices Meeting Technical Digest (1985), Paper 29.1, pages 694-697. In some cases, the capacitor is formed on a trench etched into the surface of the substrate. An example of this can be found in Ishiuchi, et al., "Submicron CMOS Technologies for 4Megabit Dynamic RAM", International Electron Devices Meeting Technical Digest (1985), Paper 29.4, pages 706-709. In other cases, a stacked or multiple plate concept providing a vertically stacked capacitor was investigated. An example of this can be found in Sunami, et aL, supra. The difficulties of forming the storage capacitor in a trench have introduced a great deal of complexity into the fabrication of the DRAM cells. For example, see Baglee, et al., U.S. Patent No. 4,721,987, "Trench Capacitor Process for High Density Dynamic RAM", issued January 26, 1988 and assigned to the assignee of this application. Although the storage capacitor itself has been made smaller, the additional difficulties in connecting the transfer transistor to the capacitor have introduced requirements for spacing tolerances and increased complexity in leakage components. These have all necessitated complex processing steps and additional area occupied to fabricate the DRAM cells. In EP-A-0 264 858 a DRAM cell is described having a shared trench storage capacitor with sidewall defined bridge contacts, gate electrodes and an associated transistor. The structure includes a trench containing polysilicon defining capacitor plates and dielectric layers of the same material. The structure further includes an on surface sidewall contact to provide electrical contact between the capacitor plates of each cell of an associated transistor. There is no teaching of a lateral below surface contact in this document. Patent Abstracts of Japan, vol. 13, No. 468 and JP-A-1,183,152 teaches a subsurface conductor forming a buried lateral contact between N+ region and a capacitor plate. A P+ region acts as a second capacitor plate for the DRAM cell described in this document. The structure has a single conductive layer and a single insulating layer within the trench. There is no teaching of first and second insulating and first and second conductive layers. SUMMARY OF THE INVENTION The difficulties encountered in the prior art are overcome by a process for forming a DRAM cell as defined in claim 1. Advantageous features are specified in the dependent claims. DESCRIPTION OF THE DRAWING The present invention is best understood with regard to the following described embodiments read in conjunction with the drawings provided herewith wherein: Figure 1 is a side view schematic diagram of a DRAM cell as formed by a process according to the present invention; Figure 2 is an electrical schematic diagram showing the electical operation of the DRAM cell shown in Figure 1; Figures 3A through 3Q are schematic diagrams showing processing steps for fabricating the DRAM cell shown in Figure 1 where all but Figure 3 are side view schematic diagrams and Figure 3 is a plan view schematic diagram; and Figure 4 is a plan view diagram of an array of memory cells such as the DRAM cell shown in Figure 1. DETAILED DESCRIPTION Figure 1 is a side view schematic diagram of a DRAM cell including a poly to poly capacitor 213. Wordline 260 controls conduction between source/drains 268 thus comprising transfer transistor 211. Source/drain 268 and contact diffusion 248 are both N-type diffusions thus comprising a conductive unit. When data is applied via bitline 272 through transfer transistor 211 to contact point 248, current passes through polycrystalline silicon plug 246 to storage plate 228. Storage plate 228 forms the capacitor between storage plate 228 and field plate 238 across dielectric 232. Figure 2 is an electrical schematic diagram showing the electrical operation of the DRAM cell shown in Figure 1. Corresponding reference numbers in Figure 2 correspond to the components shown in Figure 1. Figures 3A through 3Q are schematic diagrams showing the processing steps for fabricating the memory cell shown in Figure 1. Substrate 210 is a crystalline silicon substrate doped to P-type to a conductivity of approximately 0.9 ohm centimeters. Silicon dioxide layer 212 is formed on the surface of substrate 210 by thermal oxidation in an oxygen ambient at a temperature of approximately 950°C for approximately 50 minutes to provide a silicon dioxide layer of approximately 350 Angstroms. (10 Angstroms = 1 nm) Silicon nitride layer 214 is formed by low pressure chemical vapor deposition to a thickness of approximately 1300 Angstroms. Silicon dioxide layer 216 is silicon dioxide deposited using chemical vapor deposition to a thickness of approximately 5000 Angstroms and hardened to provide a hardmask for etching of trenches 218 and 220 were indicated in Figure 3A. A photoresist pattern (not shown) is then formed on the surface of silicon dioxide layer 216 and used to etch silicon dioxide layer 216, silicon nitride layer 214 and silicon dioxide layer 212 to provide openings 218 and 220 as shown in Figure 3A. Trenches 218 and 220 are formed in substrate 210 using the etching techniques described in Douglas, et al., for example, "Trench Etch Process for a Single-wafer RIE Dry Etch Reactor," U.S. Patent No. 4,784,720 issued November 15, 1988 and assigned to the assignee of this application. A thin silicon dioxide layer is then formed on the walls of trenches 218 and 220 using thermal oxidation in a steam ambient at approximately 900°C for approximately 10 minutes to a thickness of 250 Angstroms. A layer of silicon dioxide is then deposited in silane to a thickness of approximately 750 Angstroms on the surface of the silicon dioxide layer to provide composite silicon dioxide layer 222 as shown in Figure 3B. A layer of in situ doped polycrystalline silicon 224 is then deposited using chemical vapor deposition to a thickness of approximately 1000 Angstroms. A layer of TEOS silicon dioxide 226 is then deposited using chemical vapor deposition to a thickness of approximately 500 Angstroms. A layer of photoresist 229 is then deposited to a thickness of approximately 10,000 Angstroms to provide the structure shown in Figure 3B. Photoresist layer 229 is then exposed to light overall, without the use of a mask. The wavelength, intensity and time of exposure are chosen so that the top layer of photoresist layer 229 is exposed while the portion of photoresist layer 229 in trenches 218 and 220 is unexposed. The exposed photoresist is then removed using common developing techniques to leave the remainder of photoresist layer 229 as shown in Figure 3C. Silicon dioxide layer 226 is then etched using C 2 F 6 /CHF 3 plasma. Polycrystalline silicon layer 224 is then etched using 3F 6 plasma. The remaining portions of polycrystalline silicon layer 224 form polycrystalline silicon plate 228 and polycrystalline silicon plate 230 as shown in Figure 3D. The remainder of photoresist 229 and silicon dioxide layer 226 are then removed using wet chemical etching techniques leaving the structure of Figure 3E. A layer of silicon mtride is then deposited using low chemical vapor deposition to provide silicon nitride layer 232 as shown in Figure 3F. A layer of polycrystalline silicon is then deposited having a thickness of approximately 6000 Angstroms to completely fill trenches 218 and 220 as shown in Figure 3G. Polycrystalline silicon layer 238 will form field plate 238 after etching as described with regard to Figure 3H. A layer of photoresist 239 is then deposited and patterned on the surface of polycrystalline silicon layer 238 as shown in Figure 3H. Polycrystalline silicon layer 238 is then etched using a combination anisotropic and isotropic etch to provide sloped sidewalls and thus to provide the structure shown in Figure 3H. Silicon nitride layer 232, silicon dioxide layer 222 and silicon nitride layer 214 are then removed using anisotropic etching techniques such as reactive ion etching in C 2 F 6 /CHF 3 plasma. Thus the structure of Figure 3H remains. The structure of Figure 3H is then subjected to an isotropic silicon dioxide etch such as wet chemical etching in hydrofluoric acid to remove the top portion of silicon dioxide layer 221 and to remove a portaon of the silicon dioxide layer 221 between substrate 210 and plates 228 and 230 to provide openings 240 as shown in Figure 3I. Photoresist layer 239 is then removed using common photoresist removal techniques. A layer of polycrystalline silicon 242 is then deposited on the structure of Figure 3I to provide a thin polycrystalline silicon layer overall and to fill openings 240 as shown in Figure 3J. The structure of Figure 3J is then subjected to an isotropic etch such as carbon tetrofluoride plasma to remove the top portion of polycrystalline silicon layer 242. A portion of polycrystalline silicon layer 242 in openings 240 will remain to form polycrystalline silicon plugs 246 as shown in Figure 3K Dopant atoms will diffuse from storage plates 228 and 230 to form diffusions 248. This technique for forming the contacts from diffusions 248 to plates 228 and 230 is shown in copending application Serial No. 122,604, now U.S. Patent No. 4,939,104 which is hereby incorporated by reference. The resulting structure is then thermally oxidized to form silicon dioxide layer 244 as shown in Figure 3K. In an alternative embodiment, silicon nitride layer 214 and silicon dioxide layer 212 remain at this step and are used as an oxidation mask to protect the moat region while polycrystalline silicon layer 238 is oxidized. Silicon nitride layer 214 and silicon dioxide layer 212 are then removed, and a second thermal oxidation step is used to form the portion of silicon dioxide layer 244 on the moat. This process allows greater control of the relative thickness of the two portions of silicon dioxide layer 244. A layer of silicon nitride (not shown) is then formed to a thickness of approximately 1000 Angstroms on the surface of the structure of Figure 3K and anisotropically etched to provide silicon nitride sidewall layers 250 as shown in Figure 3L. Silicon nitride sidewall layers 250 provide sealing of the corner of plates 232 and help prevent the formation of conductive filaments on the sides of silicon dioxide layer 244 during subsequent deposition and etching of conductive layers. A layer of polycrystalline silicon 252 is then formed on the surface of the structure of Figure 3L to a thickness of approximately 5000 Angstroms. Polycrystalline silicon layer 252 is doped to a conductivity of approximately 0.005 ohm-centimeters by in situ doping. A layer of TEOS silicon dioxide 254 is then formed on the surface of polycrystalline silicom layer 252 to a thickness of approximately 2500 Angstroms. A layer of patterned photoresist (not shown) is then used to etch polycrystalline silicon layer 252 and silicon dioxide layer 254 to provide wordlines 256, 258, 260, 262 and 264 as shown in Figure 3N. Figure 30 is a plan view of the resulting structure showing the moat region as substrate 210. Note that the opening extends onto the surface of the capacitors formed in trenches 218 and 220. This overlap allows for misalignments and allows for optimal spacing of the resulting transistor without the additional alignment spaces between trench 218 and wordline 260, for example. Because no alignment spacing is required between trench 218 and wordline 260, no additional diffusions are required and an absolute minimum spacing may be provide between wordline 260 and trench 218. The structure of Figure 3N is then subjected to an ion implantation of phosphorous or arsenic ions having an energy of approximately 60 kiloelectron volts and a density of approximately 4 x 10 13 ions per centimeter 2 . This forms lightly doped source/drain regions 266 as shown in Figure 3P. A layer of silicon dioxide is then deposited to a thickness of approximately 1500 Angstoms using chemical vapor deposition and is then etched using anisotropic etching to provide silicon dioxide sidewall layers 267 as shown in Figure 3Q. The structure of Figure 3Q is then subjected to an ion implantation of arsenic ions having an energy of approximately 160 kiloelectron volts and a density of approximately 3 x 10 15 ions per centimeter 2 . Alternatively, the lightly doped regions 266 may be omitted and a double implantation after the formation of sidewall oxide layers 267 may be used using an arsenic ion implantation of arsenic ions having an energy of approximately 150 kiloelectron volts and a density of approximately 3 x 10 15 ions per centimeter 2 plus a phosphorous ion implantation of phosphorous ions in an energy of approximately 85 kiloelectron volts in a density of approximately 4 x 10 14 ions per centimeter 2 . Because of the greater diffusivity of phosphorous atoms in silicon, lightly doped drain regions are formed surrounding source/drain regions 268 thus providing a substitute for lightly doped regions 266 as shown in Figure 3Q. Because the moat opening overlapped the capacitor region, source/drain region 268 between wordline 260 and diffused region 248 provides a conductive connection for transistor 211 as shown in Figure 1. Even with misalignment, a transistor using doped region 248 as a source/drain will be formed thus providing a functioning pass transistor. This structure allows for misalignment and thus alignment tolerances may be omitted between wordline 216 and capacitor 213. A layer of boron phosphorous silicon dioxide is then deposited to a thickness of approximately 2000 Angstroms. This layer remains in the undensified state and a resist pattern (not shown) is formed on the surface of silicon dioxide layer 270. Silicon dioxide layer 270 is then etched in a solution of 10% hydrofluoric acid for approximately 15 seconds. A quick reactive ion etch using carbon tetraflouride is used to remove silicon dioxide layer 251 above source/drain diffusion 268. A layer of polycrystalline silicon 272 is then deposited to a thickness of approximately 3500 Angstroms and doped in situ to provide a conductivity of approximately 40 ohms per centimeter 2 . Because TEOS silicon dioxide layers 234 and sidewall silicon dioxide layers 267 are resistant to the 10% hydrofluoric acid etch, the contact of polycrystalline silicon layer 272 is aligned to wordlines 262 and 260 and is automatically self-aligned. Thus, no alignment tolerance is required for the formation of the bitline contact 271 to source/drain diffusion 268. Because no alignment tolerances are required, a denser array may be formed. Figure 4 is a plan view of a memory array using the memory cell of Figure 1. The layout of Figure 4 is similar to that of Figure 2 and because of the use of similar self-aligning techniques and overlap between the moat region and the capacitor region, similar layout providing optimal density is provided. Therefore, memory cell 274 as shown in Figure 4 may be formed having an area of 1.5 microns x 2.6 microns using .6 micron rules with .1 micron alignment tolerances. Although a specific embodiment of a process according to the present invention is herein described, it is not to be construed as limiting the scope of the present invention. Other embodiments will become clear to those skilled in the art in light of the teachings of this specification. For example, although the embodiment shows the use of crystalline silicon, other semiconductor materials such as gallium arsenide may be used.

Claims: A process for forming a DRAM cell, comprising the steps of: forming a trench (218, 200) in a substrate (210); forming a first insulating layer (222) comprising a first insulating material on a surface of the trench; forming a first conductive layer (228) on said first insulating layer; forming a second insulating layer (232) on the first conductive layer, the second insulating layer comprising a second insulating material; forming a second conductive layer (238) on said second insulating layer so as to complete a capacitor (213); removing by selective etching in relation to the first conductive layer a portion of said first insulating layer between the surface of the trench and the first conductive layer to provide a cavity (240) extending into said trench; filling said cavity with a conductive material (242, 246); forming a field effect transistor (211) on the substrate adjacent to the trench, one source/drain (268) of the transistor being conductively connected to said conductive material. The process of claim 1, further comprising conductively connecting the transistor and said conductive material via a buried lateral contact. The process of claim 2, further comprising forming the buried lateral contact by forming a diffused region (218) in said substrate by diffusing dopant atoms from said first conductive layer, through said conductive material into said substrate. The process of any preceding claim, wherein the steps of forming the first and second layers comprise forming said layers from the group of materials consisting silicon dioxide, silicon nitride and tautalum oxide. The process of claim 4, further comprising selecting said first layer to be of silicon dioxide and selecting the second layer to be of silicon nitride. The process of any preceding claim, further comprising said second conductive layer connectable to a reference potential. The process of any preceding claim, further comprising former said first and second conductive layers and said conductive material from polycrytalline silicon.

Inventors: CHUNG GISHI, COLEMAN DONALD J JR, MCKEE RANDY, SHEN BING-WHEY, SHIRAI KIYOSHI, TENG CLARENCE, YASHIRO MASAAKI, CHUNG, GISHI, COLEMAN, DONALD J., JR., MCKEE, RANDY, SHEN, BING-WHEY, SHIRAI, KIYOSHI, TENG, CLARENCE, YASHIRO, MASAAKI
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, H01L21