Photoelectric converting device with improved resetting transistor and information processing apparatus utilizing the same

Abstract: In a photoelectric converting device provided with a phototransistor having at least two main electrode areas (101,104) of a semiconductor of a first conductive type and a control electrode area (103),(105) of a second conductive type different from the first conductive type; and a field effect transistor having the above-mentioned control electrode area, a channel area (116), a main electrode area (106) of the second conductive type and a gate electrode (108) provided above the channel area; the channel area is formed in a high impurity concentration area of the first conductive type with a depth larger than that of the control electric area and of the main electrode area of field effect transistor. Such improvement in the channel area achieves higher performance and reliability in the photoelectric converting device requiring formation of a large depletion layer.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric converting device for use in an image input apparatus such as video camera, facsimile apparatus, copying machine or image reader, or in an image information processing apparatus such as a range finder of a camera, and more particularly a photoelectric converting device integrally provided with a phototransistor and a transistor for refreshing or resetting said phototransistor. Related Background Art In the field of photoelectric converting devices having resetting transistors integrally with phototransistors on a same semiconductor substrate, there are already known structures as disclosed in the U.S. Patent No. 4,791,469 allowed to Tadahiro Ohmi et al., in the U.S. Patent No. 4,794,443 allowed to Nobuyoshi Tanaka et al., and in the U.S. Patent No. 4,866,293 allowed to Yoshio Nakamura et al. Fig. 1A is a schematic cross-sectional view of a conventional photoelectric converting device. Referring to Fig. 1A, an n - -layer 102 is formed by epitaxial growth on an n-type semiconductor substrate 101, and said layers 101 and 102 constitute a collector area in each cell. In each cell there is formed a p-base area 103, in which an n + -emitter area 104 is formed to constitute an npn bipolar transistor (BPT) serving as a phototransistor. In the p-base area 103 there is also formed a p + -source area 105. Also at a certain distance a p + -drain area 106 is formed in the n - -layer 102, and a gate electrode 108 is formed on an oxide film 107 to constitute a resetting p-channel MOS transistor (reset Tr). Above the bipolar transistor and the resetting transistor, there are formed an insulation film 109, a drain electrode 110 connected to the drain area 106, and an emitter electrode 111 connected to the n + -emitter area 104. On these components there is formed an insulation film 112, which is covered by an opaque film 113 except for an aperture. On the bottom side of the substrate 101 there is formed a collector electrode 114. Fig. 1B is an equivalent circuit diagram of the above-explained photoelectric converting device, in which shown are the collector 201 of the bipolar transistor; collector electrode 202; base 203 of the bipolar transistor; emitter 204 of the bipolar transistor; emitter electrode 205; resetting transistor 206; terminal 207 connected to the drain electrode; and terminal 208 connected to the gate electrode. In the following there will be explained the basic function, with reference to the equivalent circuit shown in Fig. 1B. It is assumed that the base 203 of the bipolar transistor is in an initial state with a predetermined potential. Then light enters the bipolar transistor, whereby carriers of an amount corresponding to the received amount of light are accumulated in the base 203 (accumulating operation). The potential of the base varies depending on the charge accumulated in the base, and the current between the emitter and collector is controlled by said potential change. Then an electrical signal corresponding to the amount of incident light is read from the emitter electrode 205 in the floating state (readout operation). The removal of the carriers accumulated in the base 203 (refreshing operation) is conducted by grounding the emitter electrode 205 and setting the base 203 at the initial base potential through the MOS transistor 206. The carriers in the base area can be dissipated by setting the terminal 207 in advance at a potential corresponding to said initial base potential and turning on the refreshing transistor 206 at the refreshing operation. Thereafter the operations of accumulation, readout and refreshing are repeated in a similar manner. As explained above, the photoelectric converting device shown in Figs. 1A and 1B accumulates the carriers, generated by light irradiation, in the base area and controls the current between the emitter and collector electrodes by the amount of accumulated charge. Such photoelectric converting device can achieve high output, high sensitivity and low noise because the accumulated carriers are read after charge amplification by the bipolar transistor. Also the potential V p of the base area generated by the photoexcited carriers accumulated therein is represented by Q/C, wherein Q is the amount of charge of the carriers accumulated in the base while C is the capacitance connected to the base. With a higher level of integration of the photoelectric converting device, both Q and C decrease with the reduction in cell size. Thus the potential V p generated by photoexcitation remains almost constant even when such photoelectric converting device is improved in the level of integration. Consequently such device is advantageous also for a higher level of resolving power in the future. In such conventional photoelectric converting device as explained above, the collector area of the bipolar transistor and the channel forming area of the resetting transistor are integrally formed as an n - -area 102. Consequently the impurity concentration of said collector area of the bipolar transistor is same as that of said channel forming area of the resetting transistor. More specifically, the impurity concentration in the collector area of the bipolar transistor is strongly related with the photosensitivity of the photoelectric converting device and with the KTC noise thereof, and is generally considered preferably within a range from 8 x 10 13 to 5 x 10 15 cm -3 . However such conventional photoelectric converting device has been associated with the following drawbacks: (1) During the accumulating operation, the resetting transistor has to be turned off, and, in order to avoid the leak current between the source and drain of the resetting transistor, there is required a sufficiently long gate, which leads to an increased chip size. This is presumably due to an excessively low impurity concentration in the channel forming area of the resetting transistor; (2) A BT stress test, applying a voltage to the gate of the resetting transistor, proves a larger fluctuation of the threshold voltage V th than in the ordinary MOS transistors. Although the reason for this phenomenon is not yet clear, it is presumably due to a fact that a Poole-Frenkel trap generated by inversion at the oxide film-silicon interface is filled with carriers, thus shifting the threshold voltage V th in a direction facilitating the flow of current; (3) Because of the low impurity concentration in the channel forming area of the resetting transistor, a concentration in the electric field easily induces a change in the form of PN junctions between the channel forming area and the source and drain areas and results in so-called walking phenomenon of increases in the voltage resistance and the threshold voltage V th with time, so that the performance of the resetting transistor is inevitably unstable. It is therefore conceivable, as described in the above-mentioned U.S. Patent No. 4,791,469, to prevent the leak current by impurity doping in a part, where the inversion layer is formed, of the channel. Such structure is shown in Fig. 1C, in which 102' indicates a channel portion doped with impurity. However such channel doping alone is unable to sufficiently solve the technical drawbacks, because of the following fact, as identified by many experiments conducted by the present inventors. Because the resetting MOS transistor is integrally constructed with the phototransistor, the usual parameters of gate length, gate width and threshold voltage in the isolated MOS transistor cannot be applied to such resetting transistor. More specifically, since the n - -layer 102 of low impurity concentration and the n-layer 102 under the application of the collector voltage are positioned below the channel, the depletion layers DL become mutually connected in a position PT deeper than the drain area 106 and the source (base) area 105 as shown in Fig. 1C, thus causing a punch-through phenomenon. SUMMARY OF THE INVENTION The present invention is addressed to a solution of the technical problems just mentioned. In the present invention, as also in U.S. Patent No. 4,791,469, there is provided a photoelectric converting device comprising: a bipolar phototransistor having: a collector comprised of a first semiconductor region of a first conductivity type, and a second semiconductor region of the same conductivity type but of lower dopant impurity concentration, provided on said first semiconductor region, a base of a second conductivity type disposed in said second semiconductor region; and an emitter of the first conductivity type disposed in said base; a field effect transistor adjacent to said bipolar phototransistor and having: source and drain regions of the second conductivity type, an insulated gate electrode, and a high dopant impurity concentration region, of the first conductivity type and of higher dopant impurity concentration than said second semiconductor region, disposed in said second semiconductor region, providing a channel region between said source and drain regions. The photoelectric converting device of the present invention is characterised in that: said source and drain regions are of higher dopant impurity concentration than said base; said source region is partially disposed in said base and overlaps said base; and said high dopant impurity concentration region extends to a level deeper than said source and drain regions and said base. The present invention thus can allow reduction in the size of the field effect transistor and yet a stable threshold voltage can be maintained. The accumulation and refreshing of photogenerated carriers is satisfactory. A large depletion layer can be formed without punch-through of the field effect transistor. Since the high dopant impurity concentration region extends to a level deeper than the source, drain,and base, higher performance and higher reliability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: Fig. 1A is a schematic cross-sectional view of a conventional photoelectric converting device; Fig. 1B is an equivalent circuit diagram of the photoelectric converting device shown in Fig. 1A; Fig. 1C is a magnified partial cross-sectional view of the photoelectric converting device shown in Fig. 1A; Fig. 2 is a schematic cross-sectional view of a photoelectric converting device constituting a first embodiment of the present invention; Fig. 3 is a schematic cross-sectional view of a photoelectric converting device constituting a second embodiment of the present invention; Fig. 4 is a schematic cross-sectional view of another embodiment of PMOS transistor; and Fig. 5 is a schematic cross-sectional view of an information processing apparatus of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the photoelectric converting device of the present invention, in a semiconductor area of the first conductive type for forming the collector area of the bipolar transistor and the channel forming area of the resetting transistor, a specified area including said channel forming area is given a higher impurity concentration whereby optimum impurity concentrations can be selected respectively for said collector area and said channel forming area. It is therefore rendered possible to reduce the gate width of the resetting transistor and to stabilize the threshold voltage thereof in the photoelectric converting device. Now the present invention will be clarified in detail by embodiments thereof shown in the attached drawings. [First Embodiment] Fig. 2 is a schematic cross-sectional view of a photoelectric converting device constituting a first embodiment, wherein same components as those in Fig. 1 are represented by same numbers. There are also shown a channel forming area 115 of the resetting transistor, and an n-well area 116 so formed as to include the channel area. As shown in Fig. 2, said n-well area 116 is formed deeper than the source and drain areas 105, 106, thereby completely separating a depletion layer, formed by the junction of the drain area 106 and the n - -layer 102, from a depletion layer, formed by the junction of the source (base) area 105 and the n - -layer 102. The impurity concentration of the n - -area serving as the collector area of the bipolar transistor is preferably in a range from 8 x 10 13 to 5 x 10 15 cm -3 , in consideration of the relation with the photosensitivity and KTC noises of the photoelectric converting device. On the other hand, the impurity concentration of the channel forming area 115 of the resetting transistor is determined in consideration of the impurity concentrations in the source and drain areas 105, 106 of the resetting transistor, the gate width and the voltage resistance thereof, but is generally selected equal to or higher than 1 x 10 15 cm -3 . Consequently the impurity concentration of the n-area 116 is preferably in a range from 1 x 10 15 to 10 17 cm -3 . As explained above, the present embodiment allows to reduce the gate length of the resetting transistor and to stabilize the threshold voltage, thereby providing a photoelectric converting device of a reduced chip size and with improved stability of operation. The formation of said n-well area 116 is possible in most cases within the manufacturing process. It is naturally possible to add a step for said formation of the n-well area. However, if simplification of the process is imperative, an area of higher impurity concentration is formed within the channel area of the resetting transistor preferably in a step for channel stop (n-type) formation or for contact (CN + ) formation in the bipolar process. [Second Embodiment] In the following there will be explained a second embodiment of the present invention with reference to Fig. 3, which is a schematic cross-sectional view of a photoelectric converting device of said embodiment, wherein the same components as those in Fig. 2 are represented by the same numbers. An element isolation area 120 of n + -type semiconductor is so formed as to surround a light-receiving cell, and is positioned under a field oxide film 121 formed by selective oxidation. Said area is so constructed as to receive a voltage Vcc same as that applied to the collector area outside the light-receiving area. A reference voltage source V BB is provided for fixing the potential of the base area. The channel area 116, positioned deeper than the source and drain areas 105, 106, is formed in the same step as that for formation of the isolation area 120 as explained above, and serves to avoid the mutual contact of depletion layers in a deep position. In the photoelectric converting device of the present embodiment, the source and drain areas 105, 106 are made particularly shallower than the base area 103. The n-well area 116, serving to avoid the mutual contact of depletion layers below the source and drain areas, may be formed only below an area between the source and drain as shown in Fig. 3, or it may also be so formed as to surround the source and drain areas 105, 106 as shown in Fig. 4. What is important is a fact that an area of higher impurity concentration than in the epitaxial layer extends deeper than at least either of the source and drain areas. The above-explained structure of the present invention is particularly effective in the present embodiment, as the device is operated with a reference voltage Vcc of about +5 V and with a reference voltage V BB , supplied to the drain of the PMOS transistor, of about 0 - +2 V smaller than Vcc. Consequently a photoelectric converting device with higher performance and higher reliability can be provided without sacrificing the advantages of reduction of fixed pattern noises and high photosensitivity. Also in order to minimize the undesirable influence of the n-well area 116 on the photosensitivity, an opaque layer 113 is formed on said area 116. Thus it is desirable to form the area 116 and the PMOS transistor (105, 116, 106, 108) outside the effective photoelectric conversion area. [Manufacturing process] At first, on an n-silicon substrate 101, the n - -layer 102 is epitaxially grown. Then phosphorus ions are implanted simultaneously into the areas where the isolation area 120 and the n-well area 116 are to be formed, and the field oxide film 121 is then formed by selective oxidation. Then boron ions are implanted to form the P-base area 103. After the formation of the gate insulation film 107, there is formed the gate electrode 108 composed of polysilicon. Then boron ions are again implanted to form the source and drain areas 105, 106. Subsequently the wirings are formed by repeating the formation of insulation film, formation of contact holes, formation of conductive layer and patterning. More specifically, there is employed an n-silicon substrate with an impurity concentration at least equal to 1 x 10 15 cm -3 . The epitaxial layer has a thickness within a range of 4 - 20 µm, and an impurity concentration within a range of 1 x 10 14 - 10 16 cm -3 . The ranges of thickness and impurity concentration of other areas are shown in the following table: Area Thickness Impurity concentration p-base area 103 0.6 - 2.5 µm 10 15 - 10 17 cm -3 n-well area 116 0.5 - 10 µm 10 15 - 10 17 cm -3 source/drain areas 105, 106 0.1 - 1.0 µm 10 15 - 10 20 cm -3 The thickness and impurity concentration of each area are selected suitably within the ranges shown in the table above, in consideration of the mutual relationship shown in Fig. 2 or 4. A sensor module is formed by arranging a plurality of the above-described photoelectric converting devices in a linear or staggered pattern, and a sensor unit is constructed by housing said sensor module in an aluminum casing, together with a light source such as an LED array and an optical system such as a short-focus imaging element array. Fig. 5 illustrates a facsimile apparatus as an example of the image information processing apparatus employing the sensor unit of the present embodiment. There are shown a feed roller 102 for feeding an original document 6 toward a reading position; a separating member 104 for securely separating the original documents 6 one by one; and a platen roller 106 positioned at the reading position opposed to the sensor unit, thereby defining the image reading plane of the original document 6 and also serving as means for transporting said original document 6. A recording medium P, composed of rolled paper in the illustrated example, is used for reproducing the image information read by the sensor unit or transmitted from the outside in case of facsimile function. A recording head 110, constituting recording means for image formation, can be of various types such as a thermal head, or an ink jet recording head. Said recording head can be of serial type or line type. A platen roller 112, positioned at the recording position opposed to the recording head, serves to transport the recording medium P and to define the recording plane thereof. An operation panel 120, serving input/output means, is provided with switches for entering instructions for operation and a display unit for displaying the status of the apparatus for example by messages. A system control board 130, serving as control means, is equipped with a controller for controlling various units of the apparatus, a driver circuit for the photoelectric converting device, an image information processing unit, a transmission/reception unit etc. 140 is a power supply unit of the apparatus. Preferred recording means for use in the information processing apparatus of the present invention is the one of which representative principle and structure are disclosed for example in the U.S. Patents Nos. 4,723,129 and 4,740,796. Said recording means is based on providing an electrothermal converting element, positioned corresponding to a sheet or a liquid path containing liquid (ink) therein, with at least a drive signal corresponding to the recording information and generating thermal energy for inducing a rapid temperature increase in said liquid enough for exceeding nucleus boiling phenomenon and causing membrane boiling on a thermal action plane of the recording head, thereby forming bubbles in said liquid, respectively corresponding to said drive signals. By the expansion and contraction of said bubble, the liquid (ink) is discharged from a discharge opening to form at least a liquid droplet. There may also be employed so-called full line type recording head, having a length corresponding to the maximum width of the recording medium recordable on the recording apparatus. Such recording head may be obtained by the combination of plural recording heads disclosed in the above-mentioned patents, or by an integral structure. The present invention is furthermore effective for a replaceable chip-type recording head which can receive electric and ink supply from the recording apparatus itself when mounted thereon, or a cartridge-type recording head integral with an ink cartridge. As explained in the foregoing, the present invention can provide a more compact photoelectric converting device of high performance. Such device is adapted for use in a compact copying machine or a compact facsimile apparatus, particularly in combination with an ink jet recording head utilizing thermal energy, which is also suitable for compactization.

Claims: A photoelectric converting device comprising: a bipolar phototransistor (101 to 104) having: a collector (101,102) comprised of a first semiconductor region (101) of a first conductivity type, and a second semiconductor region (102) of the same conductivity type but of lower dopant impurity concentration, provided on said first semiconductor region (101), a base (103) of a second conductivity type disposed in said second semiconductor region (102); and an emitter (104) of the first conductivity type disposed in said base (103); a field effect transistor (105 to 108, 115) adjacent to said bipolar phototransistor (101 to 104) and having: source and drain regions (105,106) of the second conductivity type, an insulated gate electrode (108), and a high dopant impurity concentration region (116), of the first conductivity type and of higher dopant impurity concentration than said second semiconductor region (102), disposed in said second semiconductor region (102), providing a channel region (115) between said source and drain regions; which photoelectric converting device is characterised in that: said source and drain regions (105,106) are of higher dopant impurity concentration than said base (103); said source region (105) is partially disposed in said base and overlaps said base (103); and said high dopant impurity concentration region (116) extends to a level deeper than said source and drain regions (105,106) and said base (103). A photoelectric converting device according to claim 1 further characterised by an opaque layer (113) disposed over said high dopant impurity concentration region (116). A device according to either one of claims 1 or 2, wherein said phototransistor (101 to 104) and said field effect transistor (105 to 108, 116) are surrounded by an element isolation area (120) of semiconductor of the first conductivity type. A device according to claim 3 wherein said drain region (106) is disposed in said high dopant impurity concentration region (116). A device according to claim 1, wherein said first semiconductor region (101) is connectable with a first reference voltage source (V CC ), and said drain region (106) is connectable with a second reference voltage source (V BB ). An apparatus comprising: a photoelectric converting device according to any preceding claim; and an optical system arranged for focusing an image on said photoelectric converting device. An apparatus comprising: a plurality of photoelectric converting devices each according to any preceding claim 1 to 5; a light source for illuminating an original (6), bearing image information, and an optical system arranged for focusing an image of the original (6) on said plurality of photoelectric converting devices. An apparatus according to claim 7, further comprising: means (106) for supporting the original (6), and means (110) for recording the image information read by said plurality of photoelectric converting devices. An apparatus according to claim 8, wherein said recording means (110) is an ink jet recording head. An apparatus according to claim 9, wherein said recording head (110) is a recording head adapted to discharge ink utilising thermal energy.

Inventors: MATSUMOTO SHIGEYUKI, MATSUMOTO, SHIGEYUKI, MATSUMOTO, SHIGEYUKI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H01L31
IPC codes: H01L31, H01L27