Silicide gate level runners

Abstract: Integrated circuits are fabricated with thick self-aligned silicide runners (17) on the field oxide (13) by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

Description: Technical Field This invention relates to integrated circuits using silicide interconnections between components. Background of the Invention Integrated circuits require low resistance electrical contacts to components, as well as low resistance interconnects or runners between components. Although polysilicon has a relatively low resistivity and has been widely and successfully used for both applications, alternative materials have been sought in an attempt to obtain even lower resistivities. As the dimensions of components continue to decrease, such lower resistivity alternatives become even more desirable because the resistance of the interconnect is inversely proportional to its cross-sectional area. At the present time, the most commonly used alternative to polysilicon is a transition metal silicide. Several techniques have been developed for fabricating such silicides. In one exemplary technique, fabrication of a silicide proceeds by depositing the transition metal, such as Ti or Co, on silicon and heating the resulting composite. The transition metal reacts with the silicon to form the silicide. In one common embodiment of this technique, the silicon is present only where the silicide is ultimately desired and there is no need to remove unwanted silicide, although the unreacted metal must be removed by, e.g., etching. The resulting silicide is self-aligned and is frequently referred to by those skilled in the art as salicide ( s elf- a ligned sili cide ). Salicides are used on gate electrodes, source/drain region electrical contacts, and interconnects. Another exemplary technique fabricates structures that are called polycides. Polysilicon and transition metal silicide layers are sequentially deposited and then simultaneously patterned. Both the gate and gate runner have a silicide on top. However, the gate etching may be difficult to control due to the silicide/polysilicon structure. The chemical reaction between silicon and the metal necessarily consumes some of the underlying silicon; i.e., the underlying silicon reacts with the metal to form the silicide. However, deposition of a thick metal layer, necessary to obtain a thick, low-resistance, silicide layer, is frequently undesirable on both the gate and the source/drain regions. A thick silicide layer in the gate may produce either a high stress which adversely affects the quality of both the gate oxide and the device characteristics, or some silicide which penetrates the gate oxide and also adversely affect the device characteristics. The likelihood of the latter problem becomes greater as gate oxides continue to become thinner. Silicides are desirable on the source/drain regions because they have low resistance as compared to other materials. However, the source/drain regions should be shallow in integrated circuit devices having submicron features, and a thick metal deposition on these regions might lead to a reaction that would consume all, or a substantial fraction, of these regions. Use of a silicide containing structure for both the source/drain regions and the runners is theoretically possible, but is difficult to implement in practice because of the conflicting requirements of a thick silicide on the runners and a thin silicide on the source and drain regions. Generally, there exist similar considerations to the use of materials other than polysilicon and silicides in the gate and for interconnects. In Journal of Vacuum Science and Technology, vol 17, no [4], pages 775-792 (1980), "Refractory silicides for integrated circuits", S.P.. Murarka et al. disclose a process in which metal is deposited on the oxidized and patterned wafers, sintered to form silicides only in selected areas where silicon is in contact with the metal, and finally etched in a selective etch leaving silicide in the desired areas. EP-A-0285410 discloses a method for forming vertical metal interconnects on a semiconductor substrate having an uneven surface which comprises first forming a laminated metal structure over the entire substrate. The laminated metal structure includes a first metallization sublayer, an intermediate etch stop barrier layer, and a second metallization sublayer. The laminated metal structure is then patterned into the desired vertical metal interconnects, which interconnects are at different elevations because of the uneven underlying surface. The vertical metal interconnects are then planarized by first applying a dielectric layer and a sacrificial layer, etching back the combined dielectric and sacrificial layers to expose only the higher vertical metal interconnects, and then selectively etching back the second metal sublayer component of the higher vertical metal interconnects. Summary of the Invention A method according to the invention is as set out in claim 1. Preferred forms are set out in the dependent claims Brief Description of the Drawing FIGS. 1 and 2 are sectional views of structures useful in explaining the method of this invention. For reasons of clarity, the elements depicted are not drawn to scale. Detailed Description The method of this invention will first be described by reference to a particular embodiment. Several modifications of this embodiment will also be described, and still others will be evident to those skilled in the art. FIG. 1 is a sectional view of a portion of an integrated circuit, i.e., a field-effect transistor, at an intermediate stage of fabrication according to this invention. Depicted are substrate 1; gate structure 3, which has insulating sidewalls 5, polysilicon conductor 7, and, optionally, dielectric layer 9 on top of the polysilicon; source/drain regions 11, field oxide 13, second dielectric layer 15; and polysilicon runners 17 on the field oxide. The area between the field oxide regions, which contains the gate structure and the source/drain regions, is termed a device region. Silicide layers 19 contact the source/drain regions 11. The runners also have insulating sidewalls 5. An integrated circuit will have many transistors; only a portion of a single transistor is depicted for clarity of exposition. The elements depicted are fabricated using well-known techniques which need not be described in detail, as the techniques are known to those skilled in the art. Some device elements, such as the gate oxide, are not depicted as they are not essential to the description of device fabrication. Several features of an exemplary fabrication sequence will, however, be briefly noted. The polysilicon is blanket deposited and lithographically patterned to form the runners 17 and gate structure 7. An oxidation step, or oxide deposition followed by anisotropic etching, produces the sidewall spacers 5. If desired, a salicidation step can be performed to fabricate the thin salicide regions 19. If the gate structure does not have a dielectric on top of the polysilicon, a salicide may be formed on top of the gate structure. A first dielectric layer 15, which covers the patterned polysilicon, is then deposited and deposition of a planarization photoresist follows. An etchback planarizes the first dielectric and leaves the top surfaces of the polysilicon runners 17 exposed. If a dielectric is initially present on top of the runners, it is removed by the planarization etch, as shown in FIG. 1. Etching is stopped as soon as the surfaces of the runners are cleared of dielectric material so that the device elements; i.e., source/drain regions and gate structure, are not exposed. Some over-etching is desirable to ensure that the top surfaces of all runners are clear. A silicide-forming transition metal, such as Ti or Co, is now blanket deposited and the structure heated to form a silicide on the exposed portions of the runners, which are, as previously mentioned, primarily the top surface of the runner. The thickness of the deposited metal is determined by the desired thickness of the silicide. Unreacted metal is removed and another, i.e., second, dielectric layer is deposited to the final desired thickness. The second dielectric layer is then patterned to form windows for the electrical contacts to the device elements; i.e., source, drain, and gate. The presence of a dielectric on top of the gate electrode structure is not essential to prevent overetching of the gate structure, will be further evident from consideration of FIG. 2, which is a sectional view at right angles to that of FIG. 1. Depicted are substrate 1, layer 9, field oxide regions 13, dielectric layer 15, patterned polysilicon layer 17; and device region 23, which is between the field oxide regions. Within device region 23 are the gate and source/drain regions; these elements are not depicted for reasons of clarity. The fabrication technique is that described with respect to FIG. 1. The dielectric layer 15 is generally thicker in the device region 23 than it is on the field oxide region 13 due to the presence of the field oxide. Accordingly, the planarizing etchback clears patterned polysilicon 17 on the field oxide regions but will not affect any of the device elements, including the gate, which are masked by dielectric 15. Layer 9 may be, e.g., a salicide or a dielectric. Other variations are contemplated. The source/drain regions need not be salicide regions 19, as the salicidation step for these regions may be omitted, if desired. If they are salicide regions, the dielectric on top of the gate structure is omitted if gate salicidation is desired. The salicide so formed will be thin. The presence of the dielectric on the gate structure prevents silicide formation on the polysilicon if gate salicidation is undesired. The described process leads to thin silicides for the source/drain regions and a thick silicide for the runners. Additionally, it will be readily appreciated that the second dielectric layer will have an essentially planar surface which may be used for patterned metallizations. Embodiments other than those mentioned, as well as modifications of the described embodiments, will be readily thought of by those skilled in the art. For example, the conducting gate material might comprise a conducting nitride, such as TiN. Additionally, the conductivity of the exposed conducting gate material, i.e., runner, might be increased by selective deposition of a metal such as tungsten.

Claims: A method of fabricating integrated circuits comprising the steps of: depositing a layer of a conducting gate material(17) on a substrate(1) which includes field oxide regions(13) and device regions comprising a gate structure(3); patterning said conducting gate material(17) on said field oxide regions(13); forming a first dielectric(15) over said substrate(1) which covers gate material(17); etching back said dielectric(15) to expose the top surfaces of said conducting gate material(17) on said field oxide regions(13) but not on said device regions; and increasing the conductivity of said exposed conducting gate material(17). A method as recited in claim 1 in which said conducting gate material(17) comprises polysilicon. A method as recited in claim 2 in which said increasing step comprises the steps of: depositing a silicide forming transition metal; and, heating to form a silicide. A method as recited in claim 1 comprising the further step of depositing and patterning a second dielectric to form windows which expose selected portions of said device regions. A method as recited in claim 4 comprising the further step of depositing a metal in said windows. A method as recited in claim 1 in which said increasing step comprises depositing tungsten selectively on said exposed conductive runners.

Inventors: HILLENIUS STEVEN JAMES, LEE KUO-HUA, LU CHIH-YUAN, SUNG JANMYE, HILLENIUS, STEVEN JAMES, LEE, KUO-HUA, LU, CHIH-YUAN, SUNG, JANMYE
Applicants: AT & T CORP, AT&T CORP.
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L29