Method of Driving a CCD Imager of Frame Interline Transfer Type

Abstract: A frame interline transfer CCD imager is so adapted that signal charges from the photosensor (4) are read into a vertical transfer unit (5) and are transferred at a high transfer rate from the vertical transfer unit (5) to a storage section (6). The charges from each photosensor (4) are drained during the high transfer rate transfer so that the photosensors (4) are unable to store the signal charges to prevent the occurrence of blooming.

Description: This invention relates to a method of driving a CCD imager of frame interline transfer (FIT) type in which signal charges are transferred from a plurality of photosensors to vertical transfer units so as to be transferred via a storage section to a horizontal transfer unit. The FIT type CCD imager is a solid state imager mainly included of an imaging section which is composed of photosensors arrayed in a matrix configuration and vertical transfer units, a storage unit for transiently storing electrical charges, and a horizontal transfer unit for transferring the electrical charges on a line-by-line basis. Such technology is disclosed in, for example, the Japanese Patent Laid Open Publication No. 56-8966(1981). With such FIT type CCD imager, after the signal charges in the photosensors are read out into the vertical transfer units, during a vertical blanking period, the signal charges are transferred at a high transfer rate corresponding to the number of register stages in the storage section. The signal charges thus transferred by such transfer at the high transfer rate to the storage section are output by the horizontal transfer unit at an output buffer on the line-by-line basis. From US-A-4,447,735 a CCD imager of the same type is known having a plurality of photosensors arranged in a matrix configuration and adapted for converting the incident light to produce signal charges, vertical transfer means arranged along vertical columns of said photosensors for transferring the signal charges in the vertical direction, storage means for transient storage of the signal charges, and horizontal transfer means for transferring the signal charges stored on said storage means in the horizontal direction on a line-by-line basis and wherein the diving method comprises a reading out step and a transfer step. In the CCD imager as disclosed in US-A-4,447,735, when excess carriers are generated at the photosensors during signal charge transfer from the vertical transfer units to the storage section at the high transfer rate the charges are caused to overflow from the photosensors into the vertical transfer units to produce so called blooming. As a result, white tinted vertical streaks are produced on a monitor or screen surface. Furthermore, WO-A-88/00759 discloses an electronic shutter for image sensors using photodiodes. From this document it is known to apply a constantly increased potential selectively at the substrate for removing a potential well in order to empty a diode of charge and thus to avoid blooming. However, it is only the charge detected by the photodiode during the read-out pulse, which is transferred to the read-out channel. It is therefore a principle object of the present invention to provide a method of driving a CCD imager in which blooming may be suppressed during the high transfer rate transfer period to output satisfactory video signals. This object is advantageously solved by the features of claim 1. During such high transfer rate transfer of the signal charges, each photosensor is adapted so as not to store the signal charges therein. As a result, there is no lowering in sensitivity, while electrical charges may be prevented from leaking from the photosensors into the vertical transfer units. To cause signal charges not to be stored in the photosensors may be accomplished by draining the electrical charges into the substrate or into the drain, or by electronic shuttering. Fig. 1 is a diagrammatic view showing an overall arrangement of a typical CCD imager to be driven according to the present invention. Fig. 2 is a chart showing a potential distribution along a line A-B-C in Fig. 4 in the charge storage state of the CCD imager shown in Fig. 1. Fig. 3 is a chart showing a potential distribution along a line A-B-C in Fig. 4 in the charge draining state of the CCD imager shown in Fig. 1. Fig. 4 is a fragmentary cross-sectional view showing an essential structure of the CCD imager shown in Fig. 1. Fig. 5 is a timing chart for illustrating the operation and thus the driving method of the CCD imager of the present invention. The present embodiment shows an example of an FIT type CCD imager in which the substrate voltage is raised to a high level during transfer at a high transfer rate to prevent the blooming from occurring. Fig. 1 shows the general arrangement of the FIT type CCD imager which is comprised of a plurality of photosensors 4 arranged in a matrix form and first vertical registers 5 functioning as the vertical transfer units and constituting an imaging section 2 along with the photosensors. The photosensors 4 are of the vertical overflow drain construction for draining unnecessary charges into the substrate, as will be described later. The first vertical registers 5 are formed along the respective vertical columns of the photosensors 4. A transfer gate is provided between each photosensor 4 and the associated first vertical register 5 for reading out the signal charges. Transfer signals IM1 to signal IM4 are supplied to the first vertical registers 5 so that the electrical charges in the first vertical registers 5 are transferred at a high transfer rate to a storage section 3 by these 4-phase transfer signals IM1 to IM4. With the CCD imager of the present illustrative embodiment, the storage unit 3 is provided in contiguity to these first vertical registers 5. The storage section 3 is comprised of second vertical registers 6 provided in association with the first vertical registers 5 associated with the respective vertical columns. The signal charges from the first vertical registers 5 are transferred at the high transfer rate to these second vertical registers 6 so as to be stored transiently therein. To these second vertical registers 6 are supplied 4-phase transfer signals ST1 to ST4 and it is by these 4-phase transfer signals ST1 to ST4 that the charges in the second vertical registers 6 are transferred further. A horizontal register section 7 is provided on the opposite sides of the second vertical registers 6 with respect to the first vertical registers 5. The horizontal register 7 is adapted for reading out the charge stored in each second vertical register 6 of the storage section 3 on the line-by-line basis. To this horizontal register section 7, the electrical charges corresponding to each horizontal line are transferred from the totality of the second vertical registers 6 so as to be output at an output circuit 8. To this horizontal register section 7, 2-phase transfer signals H1, H2 are supplied, so that the electrical charge transfer is performed by these transfer signals H1, H2. From this horizontal register section 7, signals are taken out to the output circuit 8 via a floating diffusion 10f provided at the terminal end of the horizontal register section 7. The output circuit 8 may have, for example, a source follower configuration. Resetting is performed by a reset transistor 10. The gate of the reset transistor 10 is provided between the floating diffusion 10f and a reset drain 10d being supplied with precharging voltage V PD . The on/off control operation of the reset transistor 10 is carried out by a precharging gate control voltage PG supplied to the gate of the reset transistor 10. A video signal V OUT of the CCD1 is output at an output terminal 9 of the output circuit 8. Fig. 4 shows the cross-section of the photosensors 4 and the first vertical registers 5. The CCD1 includes an n-type silicon substrate 11 provided with a p-type well region 12 in which the photosensors 4 and the first vertical registers 5 are formed. The photosensor 4 is constituted by a photodiode which is formed by an n-type impurity region 13 in the p-type well region 12 and into which the radiation light is incident via an opening 15 defined between polysilicon layers 14 formed on the substrate surface. A sensor gate 16 is also formed on the substrate surface. The CCD imager 1 has a vertical overflow drain structure as the structure for draining unnecessary electrical charges. More specifically, the n-type silicon substrate 11 represents an overflow drain and the p-type well region 12 an overflow barrier. Thus an electronic shuttering operation is achieved by raising the substrate voltage V sub applied to the n-type silicon substrate 11. Above all, it becomes possible to suppress the blooming by performing the electronic shuttering operation during the high transfer rate transfer operation, as will be described subsequently. The first register 5 is able to transfer electrical charges by a buried channel region 18 on the top of a second p-type well region 17, designed for preventing smearing, with the polysilicon layer 14 as the transfer electrode 14. The buried channel region 18 faces the substrate surface and is separated from the remaining vertical columns by channel stop regions 19. It is a region 20 which is disposed below the polysilicon layer 14 and which is spaced apart from the n-type impurity region 13 that acts as a readout gate. The electronic shuttering operation by the vertical overflow drain structure is hereinafter explained by referring to Figs. 2 and 3. Figs. 2 and 3 are charts showing the potential energies along a line A-B-C in Fig. 4, wherein Fig. 2 shows the state of electron storage and Fig. 3 the state of electron draining. In the charge storage state, shown in Fig. 2, a point P 3 by the n-type impurity region 13 represents a potential well. A potential barrier is formed at each of a point P 4 by the p-type well region 12 and a point P 2 by the readout gate and electrical charges are stored at the side of the point P 3 of the n-type impurity region 13. Reading is performed with the point P 2 at the readout gate being lowered by the high potential V H and with the electrical charges thus flowing from the point P 3 of the n-type impurity region 13 towards a point P 1 of the buried channel region 18. Meanwhile, charge transfer is effected by the potentials at the points P 2 and P 1 being changed at the required driving periods by the polysilicon layer 14 to which a low potential V L and an intermediate potential V M are supplied. Fig. 3 shows the potential state during draining, that is, during electronic shuttering. With the application of the high substrate voltage V sub , the potential at the point P 4 by the well region 12 as the potential barrier is lowered, such that the electrical charges stored at the side of the point P 3 are drained into the n-type semiconductor substrate 11. Under this condition, the photosensor 4 is not in the storage state. The CCD1 of the present illustrative embodiment is able to perform the electronic shuttering in the above described manner. The operation of the CCD1 of the present illustrative embodiment is hereinafter explained by referring to Fig. 5, wherein the signal (a) shows a vertical blanking period T BLK and an image period T VD , the signal (b) a vertical drive pulse of the CCD and the signal (c) a substrate voltage V sub . During the signal or video period T VD , signal charges are transferred by a line shift pulse  LS from the second vertical registers 6 to the horizontal register section 7 on the line-by-line basis. The video signal V OUT is output from the horizontal register section 7 via output circuit 8. Then, during the vertical blank period T BLK , unnecessary electrical charges are first drained during the period t 1 . This draining operation, which is performed for draining the unnecessary charges from the vertical registers 5, 6, is performed by transferring these unnecessary electrical charges in the same direction as the signal charge transfer direction or in the opposite direction thereto for draining these charges into predetermined charge absorbing sections or regions. After the above described draining and transfer of the unnecessary electrical charges, readout pulses  R are applied to read out the signal charges in the photosensor 4 into the first vertical register 5. After the readout operation, and within a period t 2 of the same vertical blanking period T BLK , a high transfer rate transfer of the signal charges read from the first vertical registers 5 into the second vertical registers 6 is performed. When the substrate voltage V sub is raised to a higher voltage during this period t 2 , the state of the photosensor 4 is changed from the potential state of storing the electrical charges as shown in Fig. 2 to the potential state of draining the electrical charges into the substrate as shown in Fig. 3. Thus the electrical charges are not stored in the photosensor 4 during the high transfer rate transfer period t 2 to prevent the occurrence of the blooming in which excess charges are allowed to overflow during transfer from the photosensor 4 into the vertical registers to produce white-tinted vertical streaks. After termination of the high transfer rate transfer period t 2 , the substrate voltage V sub is reset to its original voltage, so that the photosensor 4 is again in the charge storage state. Although the sensitivity is lowered by an amount corresponding to the failure to store the charges during the high transfer rate transfer period t 2 , such lowering in sensitivity is in the order only of several percent. With the above described CCD imager of the present embodiment, the photosensors 4 are brought to a state of not storing electrical charges during the high transfer rate transfer within the vertical blanking period to prevent the occurrence of flaws, such as white-tinted vertical streaks, due to the above mentioned blooming. It is noted that, although the vertical overflow drain is operated with the present CCD to prevent the charges from being stored in the photosensor, a transverse or horizontal overflow drain may also be operated during the high transfer rate transfer of the electrical charges. Or alternatively, the potential well of the photosensor may be increased in depth, and/or the barrier of the readout gate may also be increased in height to achieve the same effects.

Claims: Method of driving a CCD imager of frame interline transfer type, said imager being for receiving a radiation image and converting the same into electrical charges and said imager comprising a semiconductor substrate (11) of a first conductivity type; a plurality of photosensors (4, 13) arranged in a matrix confirguration on said semiconductor substrate (11) for photoelectrically converting the incident light to produce signal charges; a well region (12) of a second conductivity type formed on the semiconductor substrate (11), the well region (12) forming a potential barrier to the draining of the signal charges on the photosensors (4, 13); vertical transfer means (5, 14) arranged along vertical columns of said photosensors (4, 13) on said semiconductor substrate (11) for transferring the signal charges in the vertical direction; storage means (3, 6) provided on said semicondutor substrate (11) in contiguity to the vertical transfer means (5, 14) and electrically connected to said vertical transfer means (5, 14), said storage means (6) being adapted for transient storage of the signal charges; horizontal transfer means (7) provided on said semiconductor substrate (11) in contiguity to said storage means (3, 6) and electrically connected to the storage means (3, 6) for transferring the signal charges transiently stored in said storage means (3, 6) on a line-by-line basis, wherein said method comprises cyclically within each time period (T BLK + T VD ) of both the vertical blanking period (T BLK ) and the image period (T VD ) the following steps: reading out the signal charges in said photosensors (4, 13) during said vertical blanking period (T BLK ), transferring the read out signal charges at a high transfer rate into the storage means (3, 6) and lowering a potential barrier (P 4 ) of the well (P 3 , 12) during only a time period (t 2 ) following the reading out period ( R ) within the same vertical blanking period (T BLK ) to drain excess charges from said well. The method according to claim 1, wherein an overflow drain (11, 12) is provided at each photosensor (4) for draining electrical charges, wherein the electrical charges at each photosensor (4) are drained into that overflow drain (11, 12) during the transfer at the high transfer rate. The method according to claims 1 or 2, wherein unnecessary charges are firstly drained from the vertical transfer means (5, 14) during an other time period (t 1 ) of the vertical blanking period (T BLK ) prior to the reading out period ( R ). The method according to any one of the preceding claims, wherein an overflow drain (11, 12) is provided at each photosensor (4) for draining electrical charges during the time when the high transfer rate transfer is performed after the signal charge reading from said vertical transfer means (5) into said storage means (6), the charges in each photosensor (4) are drained into said overflow drain. The method according to any one of the preceding claims, wherein an impurity diffusion region (13) of the first conductivity type is arranged in a matrix configuration in said well region (12) on said substrate (11) and adapted for photoelectrically converting the incident light to produce signal charges, buried channel type vertical transfer means (17, 18) are formed in said well region (12) along vertical columns of said impurity diffusion region, read out means are provided between each vertical transfer means (17, 18) and each photosensor (4) and adapted to be controlled by a read out gate (20), and wherein during the transfer at the high transfer rate of the signal charges from the vertical transfer means (17, 18) to said storage means (6) and to lower the potential barrier of the well during said time period (t 2 ) following the reading out period a raised voltage (V sub ) is applied to said semiconductor substrate (11). The method according to any one of the preceding claims, wherein said first conductivity type is the n-type and said second conductivity type is the p-type.

Inventors: HIROTA ISAO, HIROTA, ISAO, HIROTA, ISAO, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H01L27
IPC codes: H04N3, H04N5, H01L27