A fast settling voltage to frequency converter for high speed analog to digital conversion

Abstract: A circuit arrangement reduces the time necessary for a voltage-to-frequency converter to provide a new output frequency in response to a change in input voltage levels. A current source (34) provides additional input current to the input integrating node of the v/f (22) before a conversion is requested. When a conversion is requested, the additional input current effectively provides operation of the v/f (22) at an increased frequency, thus speeding the settling process therefor. When the integrator of the v/f is at a predetermined voltage level in a predetermined operating cycle, the current source is removed, thus terminating the increased frequency of operation.

Description: TECHNICAL FIELD This invention relates to voltage-to-frequency converters, and more particularly to charge-balanced voltage-to-frequency converters wherein a circuit component is included for reducing the amount of time required for the converter to change from one frequency to another. BACKGROUND ART Voltage-to-frequency converters are known in the prior art for use in analog-to-digital converters. Thus, prior art analog-to-digital converters are known to include a multiplexer providing successive voltage levels to a signal conditioning and buffer amplifier for output to a voltage-to-frequency converter. A counter is connected to the output of the voltage-to-frequency converter to provide a digital output count, representing the input analog voltage level. Typically, auto-zeroing circuits may be included to determine, for each counting and measuring cycle, an output offset voltage from the signal conditioning and buffer amplifier. A synchronizing signal, referred hereinafter as a voltage convert request signal, requests performance of a conversion. A known analog-to-digital converter of this type performs 1200 conversions per second. Thus, in such a converter there is available a duration of approximately 800 microseconds for each cycle of measurement. Where 200-300 microseconds are required by the multiplexer to provide the next input level to the amplifier and buffer, as well as for the buffer to settle and provide a stable output, approximately 500 microseconds remain to digitize the signal output by the voltage-to-frequency converter. That is, approximately 500 microseconds are available for measurement of the frequency output by the voltage-to-frequency converter. For charge-balanced voltage-to-frequency converters as disclosed in E.D.N. Electrical Design News, vol. 30, No. 11, May 1985, pages 153-164, there is provided a two-cycle sequence of operation. In a first cycle of operation, the reset cycle, an input capacitance of an integrator is charged by a current derived from an input voltage source and from a current source for a fixed time interval. In a second cycle of operation, the integration cycle, the charge is dissipated by integrating the current derived from the input voltage source. During this discharge cycle, a comparator detects the output voltage level from the integrator and, upon matching a predetermined threshold, an output pulse is generated. Generation of the output pulse completes the conversion and initiates a new sequence. The frequency of the output pulses is determined by the sum of the time periods for both the reset and integration cycles. It is known that when the input voltage changes from one level to another the frequency of the output pulses changes from a value representing the first voltage level to a value representing the second voltage level. The time required for the frequency to stabilize to the value representing the second voltage level typically requires one complete cycle of operation. When the voltage-to-frequency converter operates at frequencies ranging from 10 kHz to 100 kHz, where 10 kHz represents a zero input voltage level, such a change may require passage of 100-200 microseconds prior to obtaining a stable output frequency. Thus, approximately 20% of the time available for frequency measurement and conversion is used in settling to the new frequency value. Loss of 100 microseconds out of a 500 microsecond available time period thus represents a loss of 20% of accuracy of measurement. There is accordingly a need in prior art circuits to reduce the amount of time consumed by voltage-to-frequency converters in settling from one frequency to another frequency upon changes in voltage levels input thereto. DISCLOSURE OF INVENTION It is accordingly an object of the present invention to improve operating characteristics by reducing the portion of the conversion time required for stabilizing the voltage-to-frequency converter output frequency to a new value. It is a primary object of the invention to provide a circuit for speeding up a transition of a voltage-to-frequency converter from one frequency to another frequency. It is a more specific object of the invention to provide a speed-up circuit for generating a speed-up current to reduce the time required for balancing the initial charge condition of a voltage-to-frequency converter. Yet another object of the invention is to provide a speed-up circuit for reducing the settling time required by a voltage-to-frequency converter in response to an input voltage level transition by causing the converter to operate at a high frequency during the settling time, thus reducing the time required to establish the new frequency value. Still another object of the invention is to provide a speed-up circuit responsive to a conversion request signal of an analog-to-digital converter for generating an increased current for one charge balancing cycle and for one integration cycle, and for providing an output control signal to enable a gating circuit to pass output pulses from the voltage-to-frequency converter only after removal of the speed-up current. A more detailed object of the invention is to provide a circuit for removal of initial conditions from a charged capacitor of a voltage-to-frequency converter in a shorter time than otherwise required by provision of an additional current to an integrating node thereof. It is another object of the invention to provide a speed-up current generator including a discriminating circuit for discriminating between a reset and an integrating cycles of operation of the voltage-to-frequency converter for enabling passage of output pulses from the converter upon termination of a high-speed integrating cycle. In accordance with the present invention, there is provided an improved charge balanced voltage-to-frequency converter. Such a converter outputs pulses at a frequency determined by a voltage level input thereto. The voltage-to-frequency converter has a first cycle for resetting or initializing an integrator thereof and a second integration cycle for balancing the charge condition in the integrator thereof. The improvement of the invention includes a settling time reducing apparatus for reducing a time required by the voltage-to-frequency converter to change the frequency of output pulses provided thereby from a first frequency to a second frequency in response to a change in voltage input thereto from a first voltage level to a second voltage level. The settling time reducing apparatus includes a speed-up current generating circuit for generating a speed-up current to reduce the time required for balancing the charge condition following a change in input voltage to the voltage-to-frequency converter, and a synchronizing circuit responsive to a voltage-conversion request signal for removing the speed-up current when the integrated input voltage is at a predetermined voltage level. Thus, initial conditions of the voltage-to-frequency converter caused by the first voltage level are removed in a shorter time than required for such removal in response to unaided integration of the input voltage. Preferably, a gating circuit is included, the gating circuit being responsive to the synchronizing circuit. The gating circuit is connected for receiving an output signal from the voltage-to-frequency converter and an enabling output from the synchronizing circuit to output the voltage-to-frequency converter output signal. The synchronizing circuit provides the enabling output to enable the gating circuit only when the integrated input voltage is at the predetermined voltage level and the speed-up current is removed. The synchronizing circuit may further include a cycle identifying circuit responsive to the request signal for differentiating between a resetting cycle and an integration cycle of operation of the voltage-to-frequency converter. Additionally, in the synchronizing circuit there may be provided a removing circuit, responsive to the identifying circuit and to an output voltage of the integrator, for removing the speed-up current from the voltage-to-frequency converter when the output voltage of the integrator is at a preselected threshold level during a predetermined cycle of operation of the voltage-to-frequency converter. The synchronizing circuit may include a circuit for activating the gating circuit when the predetermined voltage level is detected in an integrating cycle of operation of the voltage-to-frequency converter. Thus, the removing circuit is preferably operable to remove the speed-up current from the voltage-to-frequency converter when the output voltage of the integrator is at the preselected threshold level during an integrating cycle of operation of the voltage-to-frequency converter. The identifying circuit preferably includes a comparator, receiving first and second inputs, a threshold voltage selecting circuit, for providing the preselected threshold level to the first input of the comparator, and a first bistable circuit (flip flop) responsive to an output transition in a predetermined direction from the comparator. The comparator is responsive to the output voltage of the integrator at the second input thereof. The first bistable circuit is preferably arranged to be responsive to a transition during a balancing cycle of operation of the voltage-to-frequency converter. The removing circuit additionally includes a second bistable circuit, responsive to the first bistable circuit and to the comparator, for removing the speed-up current from the voltage-to-frequency converter at a next output transition of the comparator, during an integrating cycle next following the balancing cycle. An output gating circuit may be included, responsive to the removing circuit. In this arrangement, the gating circuit is connected for receiving an output signal from the voltage-to-frequency converter and an enabling output from the removing circuit. The removing circuit thus provides the enabling output to enable the gating circuit only when the integrated input voltage is at the predetermined voltage level and the speed-up current is removed. Other objects, features and advantages of the present invention will become readily apparent to those skilled in the art from the following description wherein there is shown and described a preferred embodiment of the invention, simply by way of illustration of one of the best modes suited to carry out the invention. As will be realized upon examination of the specification and from practice of the same, the present invention is capable of still other, different, embodiments and its several details are capable of modifications in various obvious aspects. Accordingly, the drawings and the descriptions provided herein are to be regarded as illustrative in nature and not as restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS In accordance with the above described objects and features of the invention, a preferred embodiment thereof is shown in the accompanying drawings, wherein: Figure 1 is a block diagram representation of a known analog-to-digital converter using a charge balanced voltage-to-frequency converter; Figure 2 shows a known voltage-to-frequency converter; Figures 3A, 3B and 3C show voltage waveforms at three points of the converter shown in Figure 2; Figure 4 shows a modification of the converter of Figure 2 in accordance with the present invention; Figure 5 is a block diagram showing the modification of Figure 4 in greater detail; Figure 6 is a detailed circuit diagram of the embodiment of the invention shown in Figure 5; and Figure 7A, 7B, 7C, 7D and 7E are waveforms at various points in the circuit of Figure 6. BEST MODE FOR CARRYING OUT THE INVENTION Referring now to Figure 1, there is shown in block diagram form a known analog-to-digital converter. Such a converter includes a multiplexer 10 receiving an input signal on input lead 12 and outputting signal samples at appropriate times to a signal conditioning and buffer amplifier 14. A measurement system controller 20, which cycles multiplexer 10 among its inputs, outputs a convert request signal on an output lead 16. The request signal is provided both to a counter 18 and to the multiplexer 10. Upon receipt of the convert request signal. The multiplexer 10 selects the appropriate input. Signal conditions and buffer amplifier 14 and voltage-to-frequency 22 settle, and the counting circuitry 18 provides a measurement of the input voltage. A voltage-to-frequency converter 22 receives the conditioned voltage levels and outputs sequences of pulses at frequencies corresponding to the input voltage levels. The sequences of pulses are counted by a counter 18 to provide the digital output count representing the analog input voltage level. Figure 2 represents in block diagram form the structure of a known voltage-to-frequency converter 22. Such a voltage-to-frequency converter typically may be a charge-balanced converter, wherein an input current derived from the input voltage is provided to a summing node 24. There is also a reset current source 32 which can be gated into node 24 by a one-shot circuit 30. The one-shot circuit, triggered by the output of comparator 28, generates a reset pulse. During the reset pulse, which is of fixed time duration, the sum of the input current and the reset current causes the integrator to be reset. After the reset cycle, there is an integrate cycle in which the input current alone causes the integrator to ramp back down to the threshold voltage of comparator 28. At that threshold the output of comparator 28 changes state, triggered, by one-shot 30, beginning the next reset cycle. Because the voltage on the capacitor is always returned to the same level, the net charge on it is zero, hence the charge is "balanced." Illustratively, when a positive input current derived from an input voltage level V₁ is applied to the integrator 26, integrator 26 provides an output ramp having a negative slope. When comparator 28 detects that the value of the ramp matches threshold value V t1 , which may be ground level, for example, an output transition is generated thereby causing one-shot circuit 30 to output a pulse having a duration T r determined by an RC time constant thereof. The positive pulse from the one-shot circuit 30 switches a reset current I r into the summing node of the integrator for the fixed length of time T r . As is appreciated by those skilled in the art, in an equilibrium, steady state, condition the average charge transfer into the integrating capacitance, is zero. Thus, charge input to the capacitance during the integrating cycle is balanced by charge drawn from the capacitance during the reset cycle. For a substantially constant input current to the integrator, the input charge is given by T int *I in , where T int is the duration of the integration cycle and I in is the input current to the integrating node, which remains substantially constant throughout the integration. Moreover, for the short time durations under consideration, so long as the input voltage does not change the input current remains substantially constant throughout the integration and reset cycles. The withdrawn charge is thus given by T r *(I r - I in ), where T r is the duration of the reset cycle and I r is the magnitude of the reset current drawn from the summing node. The output frequency is given by F = 1/(T r + T int ). To obtain the relationship between the output frequency and the input voltage, V in , at the summing node, it is recognized that the input current I in = V in / Ri, where Ri is the input resistance to the summing node of the integrator 26, which is at virtual ground. Thus, I in = V in /R i T int · I in = T r (I r - I in ) (T int + T r )I in = T r I r and F = 1 (T int + T r ) = I in T r I r = V in R i T r I r The above relationships may be appreciated from the various waveforms shown at Figure 3. In Figure 3A there is shown the input voltage to summing node resistor R i . At Figure 3B is shown the voltage waveform at the output of integrator 26, including the repetitive alternation of reset and integration cycles, seen as the respective rising and falling ramp segments of the waveform. Figure 3C illustrates the sequence of output pulses, generated by the one-shot circuit 30. When the input voltage V in provided to summing node 24 changes from V₁ to V₂, the frequency of the output pulses changes, as illustrated by the change occurring in input voltage V in at time t₁ in Figure 3A and the resultant change in repetition frequency of the waveform in Figure 3C. However, although the input voltage changes at time t₁, the earliest time at which the new frequency may begin to be determined accurately is t₂, i.e., only when at least one pulse has occurred at the new frequency. Since the transition from V₁ to V₂ may occur at any time during either of the reset or integrating cycles, the time to occurrence of the first pulse after the transition is not a reliable indicator of the new frequency. The period of the new frequency is first reliably indicated by the time between the first and second pulses following the transition in input voltage. Accordingly, the new frequency cannot accurately begin to be counted until detection of the first pulse following the transition in voltage levels. The settling time of known voltage-to-frequency converters is accordingly as long as a full cycle of the new frequency. As hereinabove noted, where the new voltage V₂ is at the low voltage represented by a frequency of 10 kHz, the time between t₁ and t₂ may thus be as much as 100 microseconds, significantly reducing the amount of time available for making the measurement. In order to reduce the settling time, the present invention modifies the structure of the voltage-to-frequency converter of the prior art as shown in Figure 4. More particularly, a circuit 34 is added to induce high frequency operation in the converter during the transition period. The high-frequency operation circuit 34 generates a speed-up current Is, for input to summing node 24 during the settling time following a transition in input voltage. Operation of the inventive modification may be understood upon reference to Figure 1, wherein it is recalled that a measurement system controller 20 provides a convert request signal at each sample input time. The convert request signal initiates a cycle of operation in known analog-to-digital converters wherein the new input voltage selected by the multiplexer 10 is allowed to settle and analog to digital conversion is performed. According to the invention, the same conversion request (timing) signal which is applied to the auto-zero and counting circuits is applied to trigger a speed-up current generating circuit and to trigger a synchronizing circuit within the high frequency operation circuit 34. The synchronizing circuit outputs a timing signal to a gating circuit 36 to enable the gating circuit to inhibit the passage of the output pulses of the voltage-to-frequency converter. As will be appreciated from the following description of operation of the circuit of Figure 5, the speed-up current applied by the present invention causes the voltage-to-frequency converter to operate at a high frequency which is not necessarily representative of the input voltage. Accordingly, gating circuit 36 blocks output pulses generated by the voltage-to-frequency converter from being counted by counter 18. Once the speed-up current is removed from the summing node, the timing signal output by the synchronizing circuit enables gating circuit 36 to pass the output pulses of the voltage-to-frequency converter, now produced at the appropriate output frequency, for counting by counter 18. Refering now to figure 5, the high frequency operation circuit 34 is shown as including a speed-up current source 38, which provides a speed-up current Is to summing node 24 during the time when the buffer amplifier is being allowed to settle or at other times when the voltage-to-frequency converter is not used for frequency conversion. During this time, the current source 38 applies an additional current Is to node 24. This current may be selected to be any value, but in the presently preferred embodiment a current equivalent to operation at the highest operating frequency, 100 kHz (corresponding to full scale input voltage), is applied. Since an input current I in is also provided by the input voltage V in , the voltage-to-frequency converter operates during the reduced settling time at a frequency equal to or greater than the high-frequency established by circuit 34. Thus, one to two full cycles of the increased frequency, which is at most 20 microseconds, is required for settling of the circuit modified in accordance with the invention. The present invention thus reduces the maximum settling time from 100 microseconds to less than 20 microseconds, a significant improvement. A synchronizing circuit 40 responds to the frequency conversion request signal by triggering the current source 38 and by disabling gating circuit 36. The synchronizing circuit 40 includes a comparator 42, which compares the integrated input voltage output by integrator 26 with a threshold level V t2 , which is slightly above level V t1 , the other known trip point for the voltage-to-frequency converter, where both thresholds are very close to zero. Synchronizing circuit 40 also includes a cycle identifying circuit 44 which removes the speed-up current Is and enables gating circuit 36, in response to detection of a match between the integrated voltage and the threshold voltage V t2 during the integration cycle of operation. This leaves the voltage to frequency converter ready to begin a full cycle at the new frequency. Referring now to Figure 6, there is illustrated a detailed circuit embodiment of the arrangement of Figure 5. More particularly, integrator 26 of the voltage-to-frequency converter 22 includes an operational amplifier 46, a resistor 48 forming the resistance Ri mentioned hereinabove, and a feedback capacitor 50. Comparator 28 compares the output voltage of integrator 26 with a ground level threshold voltage, and a pulse width adjusting RC circuit R2,C2 is shown for the one-shot circuit 30. A switched current source is symbolically shown at 32 and may be arranged in any well-known circuit structure. The comparator 42 of synchronizing circuit 40 is seen to compare the output of integrator 46 with a separately set threshold voltage, as determined by a resistive voltage divider 52. Cycle identifying circuit 44 includes first and second, negatively triggered, flip-flops 54 and 56. The frequency convert request signal is used to enable the two flip-flops, and a gate 58 is enabled by the output of comparator 42 to trigger flip-flop 56 in response to selected occurrences of the Q output of flip-flop 54. The Q output of flip-flop 56 is used as the timing signal output by the synchronizing circuit to enable gate 36. Operation of the circuit of Figure 6 is illustrated by the waveforms shown in Figures 7A-7E. As shown therein, the waveform of Figure 7A represents the output voltage of integrator 26 and comprises alternating reset and integration cycles 60 and 62. In that regard, it will be appreciated by those skilled in the art that the directions of the reset and integration cycles may be reversed. The voltage-to-frequency converter operates at a frequency represented by the repetition rate for the waveform of Figure 7A. A sequence of pulses is output from gate circuit 36, as shown at Figure 7E. At some time (not shown) the input voltage is presumed t c change. Some time thereafter, at a time to, the measurement system controller 20 generates the convert request signal, shown at Figure 7B. Between measurements the low convert request signal clears flip-flops 54 and 56, disabling gating circuit 36 and interrupting passage of pulses therethrough. During this time the Q-bar output of flip-flop 56, which becomes high by clearing of the flip-flop, switches ON the current source 38 causing the rapid charging of capacitor 50 to a predetermined, known, charge level causing the voltage to frequency converter to run at a maximum rate. The integration cycle of the voltage-to-frequency converter brings the converter to a known initial condition. Accordingly, it is desirable to apply the speed-up current through an integrating cycle and to remove the current source at the end of the integration cycle. Thus the speed up circuit quickly returns the integrator to a known state for the reaching of the next cycle. Flip-flops 54 and 56, together with gate 58, form the cycle identifying circuit 44 which removes the speed up current from the summing node 24. Flip-flops 54 and 56 are clocked and triggered by the falling edge of an input signal. The Q-output of flip-flop 54 is shown at Figure 7C. This convert request signal is normally low causing the high frequency operation circuit 34 to apply a speed up circuit to the voltage to frequency converter 22 while inhibiting any output pulses to the counting circuitry. When a reading is requested by the measurement system controller 20 the convert request signal goes high and remains high until the reading is complete. When the convert request signal goes high at time t c , flip-flops 54 and 56 have the initial conditions which were acquired when they were reset by the low convert request signal. During the reset cycle of operation, the output voltage from integrator 26 is rising. This voltage is input to the inverting input of comparator 42. Accordingly, the reset cycle of operation is identified by a falling transition at the output of comparator 42, occurring when the output of integrator 26 matches the threshold V t2 . This transition, occurring at a time tr, clocks flip-flop 54 to provide a high level Q output, as shown in Figure 7C. That is, the Q output of flip-flop 54 rises on the next reset cycle after the conversion request signal is generated. Gate 58 is enabled by the Q output of flip-flop 54 so that flip-flop 56 is triggered on the next rising output of comparator 42. This rising output occurs at time tt in the next integration cycle, when the output voltage of integrator 26 drops below the threshold voltage Vt. Accordingly, flip-flop 56 is triggered to a set condition at time tt, substantially upon completion of an integration cycle. Consequently, the Q-bar output level drops, thus removing the speed-up current from the summing node. Further, the Q output of flip-flop 56, which rises as shown at Figure 7D, enables gating circuit 36 to pass the next output pulses from voltage-to-frequency converter 22. These next pulses are seen in the output signal waveform, shown in Figure 7E. Once the speed-up current source 38 is removed, the only current entering the summing node is due to the input voltage provided thereto by the buffer amplifier. For low input voltages, the charging rate may be quite low, thus delaying the generation of the next pulse by one-shot circuit 30. The low charging rate is reflected by the reduced slope of the integration cycle in Figure 7A between time tt and the initiation of the next reset cycle. It is accordingly advantageous to choose a threshold voltage for comparator 42 which is as close as possible to zero, the threshold used in comparator 28 to initiate the output pulses of the one-shot. The first pulse which is passed by gating circuit 36 thus is used by the counter 18 of the analog-to-digital converter. The present invention thus reduces the time necessary to remove any initial conditions due to previous voltage levels input to a voltage-to-frequency converter. The reduction in settling time is attained by providing a speed-up current to the summing node of the converter, and by removing the speed-up current at a predetermined point in the operating cycle of the converter. The speed-up current provides operation at effectively higher frequencies, thus shortening the time required to obtain the first reliable pulse at a new frequency when a voltage level change is input to the converter. The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description and is not intended to be exhaustive, since many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order best to explain the principles of the invention and its practical application, thereby to enable others skilled in the art best to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated therefor.

Claims: A charge balanced voltage-to-frequency converter (22) outputting pulses at a frequency determined by a voltage level (V IN ) input thereto, the voltage-to-frequency converter (22) having a first cycle for resetting an integrator (26), and a second cycle for integrating an input voltage (V IN ) and balancing a charge condition in the integrator (26) thereof, this voltage-to-frequency converter providing output pulses during an ON state of a voltage-conversion request signal (CONVERT), characterized in that it comprises settling time reducing means (34) for reducing a time required by said voltage-to-frequency converter (22) to provide a first pulse corresponding to the instant input voltage level, said reducing means (34) including: speed-up current generating means (38) for generating a speed-up current (I S ) to reduce the time required for balancing said charge condition, said speed-up current being generated while said voltage-conversion request signal is in the OFF state and the integrator is in an integration cycle, and means (24) for applying said speed-up current to the integrator (26) of said voltage-to-frequency converter (22). A voltage-to-frequency converter as recited in claim 1, further comprising synchronizing means (40) responsive to a voltage-conversion request signal (CONVERT) for removing said speed-up current (I S ) when the integrated input voltage is at a predetermined voltage level. A voltage-to-frequency converter as recited in claim 2, further comprising gating means (36) responsive to said synchronizing means (40), said gating means (36) connected for receiving an output signal from said voltage-to-frequency converter (22) and an enabling output from said synchronizing means (40), said synchronizing means (40) providing said enabling output to enable said gating means (36) to output said voltage-to-frequency converter (22) output signal only when said integrated input voltage is at said predetermined voltage level (V t2 ) and said speed-up current (I S ) is removed. A voltage-to-frequency converter as recited in claim 3, wherein said synchronizing means (40) comprises means (42, 44) for activating said gating means (36) when said predetermined voltage level (V t2 ) is detected in an integrating cycle of operation of said voltage-to-frequency converter (22). A voltage-to-frequency converter as recited in claim 2, wherein said synchronizing means (40) comprises: cycle identifying means (42, 54) responsive to said request signal (CONVERT) for differentiating between an integrating cycle and a resetting cycle of operation of said voltage-to-frequency converter (22), and removing means (58, 56) responsive to said identifying means (42, 54) and to an output voltage of said integrator (26) for removing said speed-up current (I S ) from said voltage-to-frequency converter (22) when the output voltage of said integrator (26) is at a preselected threshold level during a predetermined cycle of operation of said voltage-to-frequency converter (22). A voltage-to-frequency converter as recited in claim 5, wherein said removing means (56, 58) is operable to remove said speed-up current from said voltage-to-frequency converter (22) when the output voltage of said integrator (26) is at said preselected threshold level during an integrating cycle of operation of said voltage-to-frequency converter (22). A voltage-to-frequency converter as recited in claim 5, wherein said cycle identifying means comprises: comparator means (42) receiving first and second inputs, threshold voltage selecting means (52) for providing said preselected threshold level (V t2 ) to said first input of said comparator means (42), said comparator means (42) responsive to the output voltage of said integrator (26) at said second input thereof, and first bistable circuit means (54) responsive to an output transition in a predetermined direction from said comparator means (42). A voltage-to-frequency converter as recited in claim 7, wherein said first bistable circuit means (54) is arranged to be responsive to a transition during a balancing cycle of operation of said voltage-to-frequency converter (22), said removing means (58, 56) comprising: second bistable circuit means (58, 56) responsive to said first bistable circuit means (54) and to said comparator means (42) for removing said speed-up current (I S ) from said voltage-to-frequency converter (22) at a next output transition of said comparator means (42) during an integrating cycle next following said balancing cycle. A voltage-to-frequency converter as recited in claim 8, further comprising output gating means (36) responsive to said removing means (58, 56), said gating means (36) connected for receiving an output signal from said voltage-to-frequency converter (22) and an enabling output from said removing means (58, 56), said removing means (58, 56) providing said enabling output to enable said gating means (36) to output said voltage-to-frequency converter (22) output signal only when said integrated input voltage is at said predetermined voltage level and said speed-up current (I S ) is removed. A voltage-to-frequency converter as recited in claim 7, wherein said removing means (58, 56) comprises: second bistable circuit means (56, 58) responsive to said first bistable circuit means (54) and to said comparator means (42) for removing said speed-up current (I S ) from said voltage-to-frequency converter (22) at a next output transition of said comparator means (42), during an operating cycle of said voltage-to-frequency converter (22) next following a cycle during which said first bistable circuit means (54) responds to said output transition in said predetermined direction from said comparator means (42).

Inventors: GESSAMAN BILL, LANTZ PAUL, PARLE JON, GESSAMAN, BILL, LANTZ, PAUL, PARLE, JON
Applicants: FLUKE MFG CO JOHN, JOHN FLUKE MFG. CO., INC.
Application year: 1990
Main classification: H03K7
IPC codes: H03K7, H03M1