Semiconductor device with self-aligned contact to buried subcollector

Abstract: A P- semiconductor material substrate (10) which has been ion-implanted with N-type dopants to form an N+ subcollector layer (12) is annealed in Argon to further remove implant damage and drive the dopant ions deeper into the P substrate (10). Next a lightly doped N- epitaxial layer (14) is grown on the N+ subcollector layer (12). This forms the blanket collector. A P- well region is formed by growing a pad oxide (15) of 10nm on the N- epi layer (14) and a 200nm layer of nitride (17) is then deposited on top of the layer oxide (15). A photoresist etch mask is used to pattern the P- well region. A reactive ion etch is performed through the dielectric oxide (15) and nitride layers (17), through the epitaxial layer (14) and stopping in the subcollector layer (12). By the end of a typical bipolar process, the N+ subcol­ lector can be as wide as 1.5 microns. The depth of the P well is limited to the thickness of the N- epi (14). A layer (16, 18) of low temperature expitaxial material is grown over the structure using ultra-high vacuum/­ chemical vapor depositions such that the epitaxial layer extends above the surface of the epitaxial layer (14) and includes a P+ heavily doped layer (16) and a lightly P- doped surface layer (18). The P+ doped layer (16) may also include a more lightly doped layer (14) directly in contact with the epitaxial layer (14) to improve yield from defects occurring due to im­ mediately growing a P+ epitaxial layer (16) on top of a heavily doped N+ layer (12). The heavily doped P+ layer (16) provides the low resistance contact to the collector region and the lightly doped P- layer (18) is the collector region and its thickness is determined by the diffusion of the heavily doped layer during the entire process.

Description: The present invention relates to complementary bipolar and MOS integrated circuit semiconductor devices and processes, and more particularly to a semiconductor device with a P- well, and a fabrication method for forming a buried P+ subcollector with a self-aligned reachthrough using a low temperature expitaxial and planarization technique. U.S. -A- 3,838,440 issued September 24, 1974 to McCaffrey et al entitled A MONOLITHIC MOS/BIPOLAR INTEGRATED CIRCUIT STRUCTURE describes an integrated circuit with a MOS device including an N+ region formed by a combination of epitaxial growth and ion implantation which provides a pocket filled with higher resistivity, lightly doped N type material. Over extended growth and etch back are not shown or discussed in the patent. The publication FORMATION OF PLANAR n+ POCKETS IN GaAs FOR MIXER DIODE FABRICATION, by James A. Griffin et al, IEEE Transactions on Electron Devices, Vol. Ed-31, No. 8, August 1984, pages 1096-1099 describes a technique to produce thick n+ "pockets" of highly conducting epitaxial material on the substrate surface in semi-insulating GaAs bulk material. The pockets are formed by the growth of a liquid-phase epitaxial (LPE) layer into holes which had been etched into the substrate and surface uniformity is obtained by chemo-mechanically polishing the substrate surface. An object of the present invention is to provide a buried P+ subcollector with a self-aligned reachthrough for an integrated circuit device. Another object of the present invention is to provide a fabrication method for forming a buried P+ subcollector with a self-aligned reachthrough using a low temperature epitaxial and planarization technique. A further object of the present invention is to provide a complementary bipolar or CMOS device having a P- well with a buried P+ layer with a free, self-aligned P+ reachthrough. Still another object of the present invention is to provide a UHV/CVD epitaxial process to form a buried P+ subcollector isolated P- well with a free, self-aligned P+ reachthrough at the edge of the well for formation of a subcollector contact. Another object of the present invention is to provide a bipolar vertical PNP transistor structure with a P- well and buried P+ layer. One way of carrying out the invention is described in more detail below with reference to the drawings in which: Fig. 1 is a schematic cross-sectional view of a semiconductor device structure according to the present invention including a substrate layer, a subcollector layer, an epitaxial layer and a well region disposed in said epitaxial and subcollector layers. Fig. 2 is a schematic cross-sectional view of the semiconductor device structure of Fig. 1 after subsequent deposition and etching of an epitaxial layer. Fig. 3 is a schematic cross-sectional view of the semiconductor device structure of Fig. 2 after subsequent planarization. Referring to Fig. 1, a P- semiconductor material substrate 10 has been ion-implanted with N-type dopants to form an N+ subcollector layer 12. A typical process used to do this would be to implant 1.5 x 10¹⁶ 1/cm² Arsenic ions through a screen oxide and then give the implant a long oxidizing anneal for 30 minutes at 1100°C in steam. This is followed by an anneal in Argon to further remove implant damage and drive the arsenic dopant ions deeper into the P substrate. Next a lightly doped N- epitaxial layer 14 is grown on the N+ subcollector layer 12. Typical thicknesses and doping concentrations are 1.2µm and 5 x 10¹⁵ 1/cm³. This forms the blanket collector which is the starting place for many bipolar processes. As such, it is well practiced and characterized. The objective of the present invention is to not alter this starting material and use epitaxial techniques to deposit a subcollector and collector layer for a complementary device. To form a P- well region, a pad oxide 15 of 10nm is grown on the N- epi layer 14 and a 200nm layer of nitride 17 is then deposited on top of the layer oxide. A photoresist etch mask is used to pattern the P- well region. A reactive ion etch is performed through the dielectric oxide and nitride layers, through the epitaxial layer 14 and stopping in sub-collector layer 12. The etched P- well region is shown in Fig. 1. By the end of a typical bipolar process, the N+ subcollector can be as wide as 1.5 micrometers. The depth of the P well is limited to the thickness of the N- epi (1.2 µm plus some percentage of the 1.5 µm wire N+ subcollector. Thus, the P well must be less than 2.7 µm in the present discussed embodiment. A total depth of 1.5 µm is selected. In Fig. 2, a layer of low temperature expitaxial material is grown over the structure of Fig. 1 using ultra-high vacuum/chemical vapor depositions such that the epitaxial layer extends above the surface of layer 14 and includes a P+ heavily doped layer 16 and a lightly P- doped surface layer 18. Layer 16 may also include a more lightly doped layer directly in contact with layer 14 to improve yield from defects occurring due to immediately growing a P+ epitaxial layer on top of a heavily doped N+ layer. The total thickness of layers 16 and 18 should be equal to the depth of the P- well to guarantee the most planar structure. Layer 16 provides the low resistance contact to the collector region and should be as heavily doped and wide as possible. Layer 18 is the collector region and its thickness is determined by the diffusion of layer 16 during the entire process. With low temperature processing, layer 18 can be less than 0.4 µm. The low temperature processing includes, 700°C high pressure oxidation for all oxidation steps, and RTA anneals for any defect annealing steps. With more standard and conventional processing, the thickness of layer 18 must be at least 1.2 µm. Using a mix of the two processing approaches, a 0.8 µm layer 18 thickness and a 0.7 µm layer 16 thickness is achieved in the embodiment. Several methods may be possible to establish layers 16 and 18. In the preferred method they should be deposited by the UHV/CVD technique. This method has achieved chemical concentrations of boron greater than 5 x 10²¹ 1/cm³. In addition very lightly doped levels of boron are also easily achievable. The UHV/CVD technique is also capable of incorporating Ge to compensate the strain produced by the heavily doped boron layers. For example, if the boron concentration was 2 x 10²¹ in layer 16, a desirable germanium concentration would be five times the boron concentration or approximately 20% Ge. This ability to dope films heavily with boron and compensate the stress makes it feasible to have a thin low resistance subcollector in layer 16. A second approach would be to use a reduced pressure selective epitaxial technology. Reduced pressure systems have achieved 1 x 10²⁰ 1/cm³ concentrations of boron at 900° which is adequate. The reduced pressure systems also have selective growth capability. The approach in the selective reduced pressure case would be to overgrow and planarize so that defects are reduced and final structure is planar. The selective approach is simpler in that the masking and etching step shown in Fig. 2 is not required. The preferred method is the UHV/CVD technique because of the control of dopant concentration over a wide range; which is non selective. The epitaxial layers 16 and 18 are patterned with a mask larger than the described P- well region and reactive ion etched to provide the structure of Fig. 2. The mask overlap is between 3-5 µm outside of the initial P- well mask. The purpose is to prevent "breaking" high aspect silicon structures during the polish. It is a well known procedure for those skilled in the art of chem-mech polish. The structure of Fig. 2 is planarized using chemical-mechanical techniques to provide the structure of Fig. 3 including a planar P- well region 18 with a P+ subcollector contact ring 16 around the vertical transistor device. The structure of Fig. 3 is particularly suited to complementary bipolar technology where a blanket subcollector for the NPN structure is used and where integrating the PNP structure is desired with as little modification of existing NPN processes. The present invention provides advantages over forming a P- well by Ion/Implant steps. Ion/Implant has several deficiencies, the most notable being that in the NPN process, the epi-thickness is selected to be as thin as possible. The P- well must be ion-implanted on top of the N+ subcollector and still leave room for the formation of the PNP base. If there is sufficient room to do this and achieve a low resistance subcollector, then the original epi-thickness was much too thick. The present invention does not have that problem. Because the N-epi and a large portion of the N+ subcollector can be removed by the etch step, the PNP profile and NPN profile are no longer tightly coupled. Each can be independently optimized. The NPN profile is optimized by the N- epitaxial layer thickness and the PNP profile is optimized by the thickness and doping concentrations of layer 18 and layer 16. Another advantage of the present invention is the non-critical nature of the junction quality at the N+ subcollector/P++ P- well layer. The devices are not isolated by that junction but by a deep trench in the usual bipolar process. As long as the epitaxial crystalline quality remains, there are no limits on the dopant concentrations. A further advantage of the described invention is the provision of reduced collector resistance by the self-aligned reachthrough.

Claims: A method for fabricating an integrated circuit device having a subcollector element (16), including a self-aligned subcollector reach-through contact and a well (18) comprising the steps of: Step A. Implanting a semiconductor substrate (10) surface with impurities to form a doped blanket subcollector region (12) on said substrate (10), Step B. Disposing a first layer (14) of epitaxial material on said doped substrate (10) surface to form a collector region, Step C. Masking, patterning and etching a well recess through said collector region and into said blanket subcollector region (14, 12), Step D. Forming a layer of low temperature epitaxial material (16, 18) over said collector region and blanket subcollector region (14, 12) to fill in said well recess, said low temperature epitaxial material extending above and over said surface level of first layer of epitaxial material (14) on said substrate (10), said low temperature epitaxial material including a first, heavily doped stratum (16) disposed beneath a second, lightly doped stratum (18) wherein said first heavily doped stratum (16) forms said subcollector element (16) and extends over and in contact with said doped blanket subcollector region (12) on said substrate (10) beneath said well recess, in contact with the sides of said well recess and over said surface level of said first layer of epitaxial material (14), Step E. Masking said layer of low temperature epitaxial material (16, 18) with a mask having an aperture larger than said well recess mask, then patterning and etching said low temperature expitaxial material (16, 18), and Step F. Mechanically polishing said structure surface to planarize said low temperature epitaxial layer (16, 18) and said first layer of epitaxial material (14) wherein said first heavily doped stratum (16) of said low temperature epitaxial layer forms a contact for said subcollector region (12) that extends to said planarized surface. The method for fabricating an integrated circuit device according to claim 1 wherein said Step A includes implanting a P- material semiconductor substrate (10) surface with arsenic ions and annealing said implanted substrate to form an N+ subcollector region (12). The method for fabricating an integrated circuit device according to claim 1 or 2 wherein Step B includes growing a layer of lightly doped N-epitaxial material (14) on said N+ subcollector layer (12) to form a collector region (14). The method for fabricating an integrated circuit device according to claim 3 wherein Step C includes growing an oxide layer (15) on said layer (14) of N- epitaxial material, depositing a nitride layer (17) on said oxide layer (15), depositing and patterning a layer of photoresist material to form a mask, and reactive ion etching said oxide layer (15) said nitride layer (17), said N- epitaxial collector (14) region and said N+ subcollector region (12) through said photo-resist mask to form said well recess. The method for fabricating an integrated circuit device according to anyone of the claims 1 to 4 wherein Step D includes depositing said low temperature epitaxial material (16, 18) with boron doping by ultra-high vacuum chemical vapor deposition. An integrated circuit device structure having a subcollector (12) and a well (18) with a self-aligned subcollector reachthrough contact (16) comprising a semiconductor substrate (10) of first conductivity type, a first doped, opposite conductivity type semiconductor layer having a first doping concentration disposed on said substrate to provide a blanket subcollector region (12), a second doped, opposite conductivity type semiconductor layer (14) disposed on said sub-collector layer to form a collector region (14), a well structure recessed through said second doped layer and into said first doped layer, said well structure including therein low temperature expitaxial material (16, 18) composed of a stratum (16) of heavily doped semiconductor material disposed as a subcollector on top of said blanket subcollector region (12) and extending up to the surface level of said collector region (14) and a stratum (18) of lightly doped semiconductor material in said well and disposed on said heavily doped stratum (16) and coplanar with said surface level of said collector region (14) to form a well wherein said heavily doped stratum (16) provides a contact from said subcollector region (12) to said surface of said collector region (14). The integrated circuit device structure according to claim 6 wherein said semiconductor substrate (10) is composed of P- material, said first doped layer (12) is an N+ subcollector and said second doped layer (14) is an N- collector for a CMOS device.

Inventors: HARAME DAVID L, MEYERSON BERNHARD S, STORK JOHANNES M C, HARAME, DAVID L., MEYERSON, BERNHARD S., STORK, JOHANNES M.C.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L27