RF transistor package with nickel oxide barrier

Abstract: An improved transistor package with superior stability to wave soldering, has a barrier of nickel oxide in proximity to, and encircling, the active region, thereby preventing solder from penetrating the epoxy/cap interface. This barrier is formed by placing a photoresist material over nickel or nickel-plated leads prior to gold plating. A narrow ring or annulus of nickel without gold plating then surrounds the active area. This unplated region is oxidized during assembly of the package, creating the nickel oxide barrier, and a cap sealed to the ring area with epoxy. The nickel oxide barrier resists migration of solder, thereby maintaining the integrity of the package.

Description: This invention provides a novel package for RF transistors which offers improved stability to wave and vapor phase soldering. Hybrid RF power, semiconductive devices, or packages, are well-known in the art. Typically such devices or packages include a transistor and an input capacitor mounted upon appropriately metallized surfaces of a beryllia substrate including a lead frame arrangement bonded to the metallized areas which includes input, output and ground portions or members. Appropriate wire bonds extend from the active portions of the transistor and capacitor to the various lead portions as is well understood. Such hybrid devices, or packages, may be characterized as having an input circuit and output circuit and a common circuit which includes common lead inductance. The beryllia substrate is electrically insulating but thermally conducting and is usually mounted upon a relatively massive metallic heat sink. Appropriate ground connections may be made to the grounded heat sink. Further, the input and output circuits usually comprise microstrip conductor means which include a metallic strip mounted on an insulating substrate whose impedances are matched to those of the input and output circuits of the transistor. In addition, the microstrip circuit devices may also be grounded to the metallic heat sink, for example, by wrap around metallizations. The RF transistor packages have protective caps sealed over the active silicon device with epoxy. Automated package assembly techniques, such as wave soldering and vapor phase soldering, employ temperatures and conditions which often caused breakdown of the epoxy and leakage of the solder into the active region of the device. In addition, when soldering onto a gold lead, the solder and solder flux may leach and travel along the gold underneath the epoxy. Equipment manufacturers must therefore rely on hand soldering of devices into boards after automatically inserting and soldering all other components. There remains a need, then, for an improved package which will permit total automation of the assembly process. Patent abstracts of Japan, vol. 6, No. 103 (E-112) and JP-A-57 035 354 disclose a sealing method for a semiconductor housing in which sealing is performed by a cap with bonding resin. Patent abstracts of Japan, vol. 9, No. 193 (E-334) and JP-A-60 060 742 disclose a lead frame having oxidized surfaces which are sealed with resin. However, neither of the above documents disclose gold-plated leads or the problems incurred thereby. EP-A-0 235 504 discloses a high-frequency package for solid state components with gold- and nickel-plated leads which is hermetically sealed using solder glass. According to one aspect of the present invention, there is provided a semiconductor device comprising in combination: a thermally and electrically conducting base member; a thermally conducting, electrically insulating support for an RF semiconductor die, said support having upper and lower surfaces, said lower surface coupled to said base member and said upper surface having an electrically conductive coating thereon; an RF semiconductor die mounted on and electrically coupled to said upper surface of said support; a plurality of gold-plated leads mounted on said upper surface of said support and electrically connected to said semiconductor die, each of said leads having a nickel oxide barrier strip arranged near the end of the lead proximate to said semiconductor die, said oxide barrier strip being of a size and shape adapted to accept the leading edge of a protective cap; and a protective cap covering said semiconductor die, said cap being non-hermetically sealed by epoxy to the leads and the support at the nickel oxide barrier strip, said nickel oxide strip providing a barrier to the migration of solder under the cap. Said base member may be a copper flange; Said semiconductor support may be a beryllium oxide pill having a thin gold coating thereon; and said die may be a transistor die. According to a further aspect of the present invention there is provided a process for preparing a semiconductor device comprising: mounting a plurality of nickel-plated leads on a thermally conducting, electrically insulating support having an electrically conductive coating thereon and mounted on a thermally and electrically conducting base member; covering a portion of the surface of the leads with a photoresist material to define a first exposed surface of the leads proximate said support and a second exposed surface remote from said support; gold plating the exposed surfaces of the leads; removing the photoresist material to expose the unplated nickel, thereby forming a surface susceptible to oxidation; mounting a semiconductor die on said support at a temperature sufficient to induce oxidation of the nickel, thereby forming a nickel oxide strip on the leads; covering the semiconductor die with a cap, said cap having dimensions of a size and shape to contact the mounting edges of said cap with the nickel oxide strips on the leads, said cap being non-hermetically sealed to the leads and the support with epoxy, said nickel oxide strip providing a barrier to the migration of solder under the cap. Thus an RF transistor package may be provided, exhibiting superior stability to wave and vapor phase soldering. The improved device has a barrier of nickel oxide in proximity to, and encircling, the active region, thereby preventing solder from penetrating the epoxy/cap interface. This barrier is formed by placing a photoresist material over nickel or nickel-plated leads prior to gold plating. A narrow ring or annulus of nickel without gold plating then surrounds the active area. This unplated region is oxidized during assembly of the package, creating the nickel oxide barrier, and a cap sealed to the ring area with epoxy. The nickel oxide barrier resists migration of solder, thereby maintaining the integrity of the package. A specific embodiment of the present invention will now be described with reference to the accompanying drawings, in which:- Figure 1 is a top view of a typical package of this invention. Figure 2 is a side view of the package of Figure 1. Figure 3 is an exploded view of the cap-to-lead junction shown in Figure 2. In Fig. 1, a package of this invention without its cap is viewed from above. Copper flange 10 and gold-plated leads 12 perform usual mounting and connecting functions. The active region 14 contains transistor and capacitor dies 16 and 18 respectively, joined to each other, and the leads 12 with suitable connectors 19, usually gold wire. Nickel oxide barrier strips 20 on the leads are shown as forming segments of a ring surrounding the active area. The unshaded regions 22 of the ring are beryllia which will be covered with epoxy prior to attachment of the cap. In Fig. 2, a representative package of the invention is shown from the side in outline form. Copper flange 10 acts as a mounting frame as well as a heat sink for the assembled device. Any thermally and electrically conductive material suitable for use as a base member may be substituted for the copper. The beryllium oxide pill 22 is mounted on the copper flange. The pill acts as support for the lead frame 12 and active area 14, including transistor die 16, capacitor die 18, and gold wire connnectors 19. The pill is generally a thermally conducting, electrically insulating support with its lower surface coupled to the base member and the upper surface having a thin conductive coating. The lead frame 12 is usually machined from kovar (iron/cobalt) or alloy 42 (nickel/iron). The base metal is then coated with a layer of nickel followed with a layer of gold. Typically, the plating layers are from about 3 (130) to about 8 microns (300 microinches) thick. These gold plated leads are mounted on the pill and electrically connected to the transistor die 16, optionally to additional electronic devices, such as capacitors, which are also mounted on the pill. A ceramic cap 24 covers the active area 14. The ceramic cap is bonded to the pill and leads as shown in region 26 of Fig. 2. An epoxy preform 28 is sited on top of the nickel oxide strip 20. The nickel oxide strip is present on each lead and serves as a barrier to the migration of solder under the cap during wave soldering. Referring now to Fig. 3, which is an exploded view of region 26 of Fig 2, the ceramic cap 24 is mounted on the epoxy preform 28. The epoxy preform is in turn mounted on the nickel oxide strip 20 of gold-plated lead 12. In this invention the gold-plated leads are not completely coated with gold, but have a narrow unplated region near the end proximate to the chip. The unplated region is made by masking the base metal lead during coating so that a narrow strip of nickel is left uncoated. This exposed strip is of sufficient width to accommodate the leading edges of the cap. During the mounting of the chip to the pill the exposed nickel of the leads is rapidly oxidized. Subsequently, the cap is epoxied over the nickel oxide strips. In forming the leads of this invention, it is only necessary to prevent the gold plating from covering a region of the leads sufficiently wide to afford some barrier. This may be achieved via negative resist with a clear field mask or positive resist with a dark field mask. Preferably, the gold plating is conducted on leads which have already been brazed to a pill by conventional methods.

Claims: A semiconductor device comprising in combination: a thermally and electrically conducting base member (10); a thermally conducting, electrically insulating support (22) for an RF semiconductor die, said support having upper and lower surfaces, said lower surface coupled to said base member and said upper surface having an electrically conductive coating thereon; an RF semiconductor die (16) mounted on and electrically coupled to said upper surface of said support; a plurality of gold-plated leads (12) mounted on said upper surface of said support and electrically connected to said semiconductor die, each of said leads having a nickel oxide barrier strip (20) arranged near the end of the lead proximate to said semiconductor die, said oxide barrier strip being of a size and shape adapted to accept the leading edge of a protective cap; and a protective cap (24) covering said semiconductor die, said cap being non-hermetically sealed by epoxy (28) to the leads and the support at the nickel oxide barrier strip, said nickel oxide strip providing a barrier to the migration of solder under the cap. A device according to claim 1 in which the nickel oxide barrier strip width is greater than the wall thickness of the cap. A device according to claim 1 in which the semiconductor support is a beryllium oxide support. A device according to claim 1 in which the base member is formed from copper. A device according to claim 1 in which the gold-plated leads are selected from the group consisting of gold-plated nickel, gold-plated kovar, and gold-plated alloy 42. A device according to claim 1 in which said base member (10) is a copper flange; said insulating support (22) is a beryllium oxide pill having a thin gold coating thereon; and said semiconductor die (16) is a transistor die. A process for preparing a semiconductor device, comprising: mounting a plurality of nickel-plated leads (20) on a thermally conducting, electrically insulating support (22) having an electrally conductive coating thereon and mounted on a thermally and electrically conducting base member (10); covering a portion of the surface of the leads, which at a later stage will accommodate the leading edges of a cap (24), with a photoresist material to define a first exposed surface of the leads proximate said support and a second exposed surface remote from said support; gold plating the exposed surfaces of the leads; removing the photoresist material to expose the unplated nickel, thereby forming a surface susceptible to oxidation; mounting a semiconductor die (16) on said support at a temperature sufficient to induce oxidation of the nickel, thereby forming a nickel oxide strip (20) on the leads; covering the semiconductor die with a cap (24), said cap having dimensions of a size and shape to contact the mounting edges of said cap with the nickel oxide strips on the leads, said cap being non-hermetically sealed to the leads and said support with epoxy (28), said nickel oxide strip providing a barrier to the migration of solder under the cap.

Inventors: BUTERA GASPAR A, BUTERA, GASPAR A.
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS, INC.
Application year: 1990
Main classification: H01L23
IPC codes: H01L23, H01L27, H01L21