Differential amplifier using voltage level shifting to achieve rail-to-rail input capability at very low power supply voltage

Abstract: A differential amplifier coupled between sources of a high supply voltage (V HH ) and a low supply voltage (V LL ) contains a pair of differential portions (30 and 32), that are used to amplify a differential input signal (V I1 and V I2 ). One of the differential portions is turned on when the common-mode voltage of the input signal is in a portion of the supply range extending up to the high supply voltage. The other is turned on when the input common-mode voltage is in a portion of the supply range extending down to the low supply voltage. A level-shift circuit (38, 40, 42, 44, and 46) selectively raises or lowers the voltages at input points (P1, P2, P3, and P4) to the differential portions. The level shifts extend the conductive ranges of the differential portions. This enables the amplifier to eahcieve rail-to-rail input capability down to 1 volt or slightlty less for the power supply voltage.

Description: The invention relates to an electronic circuit for amplifying a circuit input signal differentially provided between first and second input terminals as respective first and second input voltages, the circuit comprising: main supply means, coupled between respective sources of a high supply voltage V HH and a low supply voltage V LL whose difference is a power supply voltage V PS that defines a power supply range, for providing opposite first and second operating currents; first differential means for amplifying the voltage difference between first and second input points by largely dividing the first operating current into a pair of amplified first internal signals, the first and second points being respectively coupled to the first and second terminals, the first means being operatively conductive to so produce the first internal signals when the common-mode voltage V CM of the circuit input signal is in a portion of the supply range extending up to V HH ; second differential means for amplifying the voltage difference between third and fourth input points by largely dividing the second operating current into a pair of amplified second internal signals, the third and fourth points being respectively coupled to the first and second terminals, the second means being operatively conductive to so produce the second internal signals when V CM is in a portion of the supply range extending down to V LL such that at least one of the differential means is operatively conductive as V CM traverses substantially the entire supply range when V PS is greater than or equal to a specified minimum level; and summing means for combining the internal signals to generate at least one circuit output signal; Such a circuit is known from US Patent 4,555,673 and relates to a differential amplifier suitable for use in an operational amplifier ("op amp") made in semiconductor integrated circuit form and, more specifically, to a differential amplifier that employs complementary differential portions to attain rail-to-rail input capability. An integrated circuit often needs a lower power supply voltage to avoid heat-dissipation problems. Low supply voltage will be even more necessary in the future as integrated circuits become increasingly more dense. It thus becomes desirable that a differential amplifier used as an input stage in an op amp have rail-to-rail input capability. That is, the output signal of the amplifier should be representative of the differential input signal as its common-mode voltage travels the full range of the power supply voltage. As used here to describe the relationship between two signals, "representative" means that their amplitudes have a substantially one-to-one (typically linear) relationship as long as the amplitudes are not too great. Referring to the drawings, Fig.1 illustrates a general arrangement for a prior art differential amplifier that can achieve rail-to-rail input capability at moderately low power supply voltage. See U.S. Patent 4,555,673. Also see U.S. Patents 4,463,319 and 4,532,479. The amplifier in Fig. 1 employs a pair of complementarty differential input portions 10 and 12 to amplify a circuit input signal differentially supplied between input terminals T1 and T2 as input voltages V I1 and V I2 . Differential portion 10 consists of NPN transistors Q1 and Q2 whose bases receive the circuit input signal at input points P1 and P2 connected to terminals T1 and T2. The emitters of transistors Q1 and Q2 are connected together at a node N A to receive a first operating current I A . Differential portion 12 is formed with PNP transistors Q3 and Q4 whose bases receive the circuit input signal at input points P3 and P4 connected to terminals T1 and T2. The emitters of transistors Q3 and Q4 are connected together at a node N B to receive a second operating current I B . A main current supply 14 connected between sources for a high supply voltage V HH and a low supply voltage V LL provides currents I A and I B in opposite flow directions. Portion 10 supplies amplified internal currents I B1 and I B2 from the Q1 and Q2 collectors. Portion 12 similarly provides amplified internal currents I D3 and I D4 from the Q3 and Q4 collectors. A summing circuit 16 connected between the V HH and V LL supplies suitably combines currents I D1 - I D4 to generate a pair of complementary output currents I O and I O . In looking at amplifier operation, it is convenient to define several terms. Let "▴V" and "V CM " respectively represent the differential voltage V I1 - V I2 and the common-mode voltage (V I1 + V I2 )/2 of the circuit input signal. Let "V PS " represent the power supply voltage V HH - V LL . The prior art device in Fig.1 can be characterized by a pair of threshold voltages V TA and V TB that may vary with V PS . Fig.2 shows a general example of how V TA andV TB may appear. Fig. 3 shows the resulting operational regions for the amplifier. The horizontal axis in Fig.3 represents the condition where V CM equals V LL . Line 18 (at 45°) represents the condition where V CM equals V HH . The region between the horizontal axis and line 18 thereby encompasses the rail-to-rail operational range for the amplifier. Input portion 10 is operatively conductive (turned on) when V CM is sufficiently high. More specifically: V CM - V LL ≧ V TA . Eq. (1) basically corresponds to the portion of the V PS range between line 20A and line 18 in Fig. 3. The conductive region for portion 10 does, however, extend slightly above line 18 to a point where V CM is several tents of a volt more than V HH . When portion 10 is turned on, it amplifies the voltage difference between points P1 and P2 by splitting current I A between currents I D1 and I D2 at values whose difference is representative of ▴V. Input portion 12 is operatively conductive when V CM is sufficiently low. In particular: V HH - V CM ≧ V TB Eq. (2) basically corresponds to the portion of the V PS range between the horizontal axis and line 20B in Fig. 3. In addition, the conductive range for portion 10 extends slightly below the horizontal axis to a point where V CM is several tenths of a volt less than V LL . When portion 12 is turned on, it amplifies the voltage difference between points P3 and P4 by splitting current I B between current I P3 and I P4 at values whose difference is representative of V. Fig. 3 indicates that portion 10 is turned off in the space between the horizontal axis and line 20A -- i.e., when V CM - V LL is less than V TA . Likewise, Fig.3 shows portion 12 as being turned off in the area between line 20B and 18. This corresponds to the condition in which V HH - V CM is less than V TB . In actually, each of portions 10 and 12 usually switches between on and off over a spacing on the order of 100 millivolts. Lines 20A and 20B are thus idealizations of narrow voltage regions. When V PS is reduced, the amount of V CM space available for the non/conductive regions for portions 10 and 12 decreases. The two non-conductive regions start to overlap when V PS reaches a level V PSO . If V PS drops below V PSO , V CM passes through a "dead zone" indicated by thick line 22 in which neither of portions 10 and 12 is operatively conductive. V PSO is thus the value of the minimum V PS level at which the differential amplifier in Fig. 1 can achieve rail-to-rail input capability. Threshold V TA and V TB have respective minimum values V MA and V MB . See lines 24 and 26 in Fig. 3. In known embodiments of the amplifier in Fig. 1, V PSO is approximately equal to V MA + V MB . The numerical value of V PSO depends on the base-emitter voltages of transistors Q1 - Q4 and on the internal construction of current supply 14. Figs. 4a and 4b depict two ways, both described in U.S. Patent 4,555,673, for implementing supply 14. Figs. 5a and 5b graphically show the specific idealized operational regions for the amplifier of Fig. 1 as implemented with the main current supplies shown respectively in Figs. 4a and 4b. Starting with the embodiment of Fig.4a, supply 14 consists simply of a pair of current sources S L and S H . Current source S L supplies current I A at a constant value I L . Current source S H provides current I B at a constant value I H . For current source S L and S H to be conductive, the voltage across each of them must be at least equal to a minimum level V SAT . V CM exceeds the voltage at node N A by 1V BE when portion 10 is turned on. V BE is the magnitude of the standard voltage across the base-emitter junction of a bipolar transistor when it is just turned on. The voltage at node NB similarly exceeds V CM by 1V BE when portion 12 is turned on. In view of this, each of threshold minimums V MA and V MB equals V BE + V SAT . V PSO thereby equals 2V BE + 2V SAT . At a standard collector-emitter current of several microamperes, V BE is approximately 0.6 volt. V SAT can be as low as 0.1 volt. Using these values for V BE and V SAT (in the present computation and in all the additional ones below), V PSO is approximately 1.4 volts for the differential amplifier of Figs. 1 and 4a. A disadvantage of using the current supply in Fig. 4a is that the transconductance of the amplifier changes by a factor of approximately 2 whenever either of portions 10 and 12 turns on or off. The variation in transconductance makes it difficult to optimize the frequency compensation for the amplifier when it is used in an op amp with negative feedback. The implementation shown in Fig. 4b overcomes this problem. When the circuitry of Fig. 4b is used, supply 14 is formed with current source S H , a PNP steering transistor QP whose base receives a reference voltage V RP , and a current mirror 28 that supplies current I A at a value largely equal to the current I QP through transistor QP. Current steering through transistor QP enables the sum of I A and I B to approximately equal I H . As a result, the transconductance is nearly constant as V CM varies across the entire V PS range. The voltage across current mirror 28 between node N A and the V LL supply must be at least 1V SAT for mirror 28 to be conductive. Under optimum conditions, the current steering causes lines 20A and 20B in Fig. 3 to merge into a single line 20 separated from line 18 by a vertical displacement equal to V MB as depicted in Fig. 5B. V MA equals V BE + V SAT again. V MB may be as low as V BE + V SAT . Consequently, V PSO may again be equal to 1.4 Volts. As the above discussion indicates, the lowest tolerable value for V PS in the differential amplifier of Fig. 1 is approximately 1.4 volts. In practice, V PS may have to be a few tenths of a volt higher. While this is still relatively good, it would be quite useful to get down to 1.0 volt or less. For example, a single-cell battery having an unloaded rating of 1.5 volts typically drops down to about 1.0 volt under loaded conditions near the end of its life. The amplifier of Fig. 1 cannot operate efficiently from such a battery. It is the object of the invention to provide a differential amplifier that can achieve rail-to-rail input capability at a very low power supply voltage. In bipolar embodiments, the power supply voltage can be at or slightly below 1.0 volts. This makes the invention particularly attractive for future low-voltage op amp applications. The invention can be powered from a single-cell 1.5-volt battery during the entire battery life. According to the invention a circuit asset forth in the opening paragraph is characterize in that the circuit further comprises: level-shift means for selectively causing the voltages at the first and second points to be respectively higher than the first and second input voltages by respective first and second voltage level shifts and for selectively causing the voltages at the third and fourth points to be respectively lower than the first and second input voltages by respective third and fourth voltage level shifts. The level shift means extend the conductive operational ranges of the differential means so as to reduce the value of the minimum level of the power supply voltage at which the differential amplifier achieves rail-to-rail input capability. The circuit may be characterized further in that the level-shift means comprises: network means, coupled between the terminals and the points, for providing the level shifts; and level-shift supply means for providing current to the network means to control the values of the level shifts. The network means may be characterized in that the network means comprises a first level-shift element coupled between the first terminal and the first point, a second level-shift element coupled between the second terminal and the second point, a third level-shift element coupled between the first terminal and the third point, and a fourth level-shift element coupled between the second terminal and the fourth point. The level shift supply means may be characterized in that the level-shift supply means comprises a first current source coupled between the first point and the V HH source, a second current source coupled between the second point and the V HH source, a third current source coupled between the third point and the V LL source, a fourth current source coupled between the fourth point and the V LL source, and control means for controlling conduction of the current sources. The control means preferably operates in such a way as to gradually turn off the level-shift means as the power supply voltage rises to a point where level shifting is not needed. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 shows a block and circuit diagram of a prior art differential amplifier, Figs. 2 and 3 show graphs depicting operational features for the amplifier of Fig. 1, Figs. 4a and 4b show circuit diagrams of prior art embodiments of the main current supply in Fig. 1, Fig. 5a and 5b show graphs showing the primary operational regions for the amplifier of Fig. 1 as respectively embodied with the current supplies of Figs. 4a and 4b, Fig. 6 shows a block diagram of a general differential amplifier in accordance with the invention, Fig. 7a and 7b show graphs generally illustrating the operational regions for the amplifier of Fig. 6, Fig. 8 show a block diagram of an embodiment of the level-shift current supply in Fig. 6, Fig. 9a, 9b, and 10 show graphs generally showing operational aparameters for the amplifier of Fig. 6 as embodied with the circuitry of Fig. 8, Fig. 11 shows a block and circuit diagram of a general embodiment of the amplifier of Fig.6, Fig. 12 shows a block diagram of an embodiment of the level-shift current control in Fig. 11, Figs. 13a, 13b, and 13c show graphs illustrating how level-shift voltage preferably varies as a function of input common-mode voltage for the amplifier of Fig. 11, Figs. 14a and 14b show graphs showing the operational regions for the amplifier of Fig. 11 as respectively embodied with the currents supplies of Figs. 4a and 4b, Fig. 15 shows a circuit diagram of a preferred bipolar embodiment of the amplifier of Fig. 11, Fig. 16 shows a circuit diagram of a preferred embodiment of the reference voltage circuitry in Fig. 15, Fig. 17 shows a graph illustrating the operational regions for the amplifier of Fig. 15 as embodied with the complete reference voltage circuitry in Fig. 16, Figs. 18a and 18b show graphs showing an alternative variation for level-shift current as a function of input common-mode voltage for the amplifier of Fig.11, Fig. 19 shows a graph illustrating the operational regions for the amplifier of Fig.11 as embodied with the current supply of Fig.4a for the level-shift variation indicated in Figs. 18a and 18b and Fig. 20 shows a block and circuit diagram of another general embodiment of Fig. 6. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. Referring to Fig.6, it illustrates a general arrangement for a differential amplifier that amplifies a circuit input signal differentially supplied between input terminals T1 and T2 as input voltages V I1 and V I2 . This differential amplifier uses a level-shifting technique in accordance with the invention to attain rail-to-rail capability for the common-mode voltage V CM of the circuit input signal at very low power supply voltage. The amplifier is particularly suitable for use as an input stage of a low-voltage op amp fabricated in semiconductor integrated circuit form. The device in Fig. 6 centers around complementary differential input portions 30 and 32. Differential portion 30 consists of like-configured three-electrode input amplifiers A1 and A2. Differential portion 32 is formed with like-configured three-electrode input amplifiers A3 and A4 which are complementary to amplifiers A1 and A2. The term "complementary" means opposite polarity. Amplifiers A1 - A4 are referred to here as the "A" amplifiers. Each "A" amplifier has a first flow electrode (1E), a second flow electrode (2E), and a control electrode (CE) for controlling current flow between the flow electrodes (1E and 2E). Charge carriers, either electrons or holes, that move between the flow electrodes of each "A" amplifier originate at its first flow electrode and terminate at its second flow electrode. The current (if any) flowing in the control electrode is much smaller than that otherwise moving between the flow electrodes. Each "A" amplifier preferably consists of a single transistor. In the case of a bipolar transistor, its emitter, collector, and base are respectively the first, second, and control electrodes. These elements are respectively the source, drain, and gate for a field-effect transistor of either the insulated-gate or junction type. Although generally undesirable, each "A" amplifier could consist of more than one transistor. One example is a bipolar Darlington circuit in which the emitter of an input transistor is connected to the base of a trailing transistor. In this case, the control electrode of the "A" amplifier is (connected to) the base of the input transistor, while the first and second control electrodes are (connected to) the emitter and collector of the trailing transistor. As used in describing amplifiers A1 and A2 or A3 and A4, "like-configured" means that the two amplifiers in question have corresponding elements interconnected in the same way and that each set of corresponding elements is of the same semiconductor polarity. For example, amplifiers A1 and A2 are like-configured if both are NPN transistors but not if one is an NPN transistor while the other is a PNP transistor. Likewise, Darlington circuits are like-configured as long as the input transistors are of the same polarity and the trailing transistors are of the same polarity (even if different from that of the input transistors). Turning back to Fig.6, the first electrode of amplifiers A1 and A2 are connected together to receive operating current I A at node N A . Similarly, amplifiers A3 and A4 have their first electrodes connected together to receive operating current I B at node N B . A main current supply 34 connected between the V HH and V LL supplies provides oppositely directed currents I A and I B . Current supply 34 may be implemented using either of the circuits shown in Figs. 4a and 4b. Other embodiments described in U.S. Patent 4,555,673 may also be used. Differential portions 30 and 32 function in a complementary manner. When V CM is sufficiently high, portion 30 amplifies the voltage difference between input points P1 and P2 connected to the A1 and A2 control electrodes by dividing current I A into amplified internal currents I D1 and I D2 supplied from the A1 and A2 second electrodes. The difference between the currents ID1 and ID2 is representative of the voltage difference between points P1 and P2. When V CM is sufficiently low, portion 32 amplifies the voltage difference between input points P3 and P4 connected to the A3 and A4 control electrodes by dividing current I B into amplified internal currents I D3 and I D4 supplied from the A3 and A4 second electrode. The difference between currents I D3 and I D4 is representative of the voltage difference between points P3 and P4. A summing circuit 36 connected between the V HH and V LL supplies suitably combines curruents I D1 - I D ₄ to produce complementary circuit output currents I O and I O . Summing circuit 36 may be implemented in any of the ways shown in U.S. Patents 4,555,673 and 4,532,479. If desired, circuit 36 may provide only a single circuit output current. A level-shift circuit consisting of a network of level-shift elements 38, 40, 42, and 44 and a level-shift supply circuit 46 selectively enables voltages V P1 and V P2 at points P1 and P2 to exceed voltages V I1 and V I2 by controllable level shifts V LS1 and V LS2 . The level-shift circuit likewise selectively enables voltages V P3 and V P4 at points P3 and P4 to be less than voltages V I1 and V I2 by controllable level shifts V LS3 and V LS4 . Level-shift elements 38 - 44, which are connected between terminals T1 and T2 and points P1 - P4 in the manner shown in Fig. 6, directly provide level-shift voltages V LS1 - V LS4 . Level-shift current supply 46, which is connected between the V HH and V LL supplies, controls the operation of level shifts 38 - 44. Current supply 46 accomplishes the control by providing supply currents I S1 , I S2 , I S3 and I S4 along lines connected to points P1 - P4. Although not indicated in Fig. 6, supply 46 is typically connected to other points in the amplifier circuit. For example, supply 46 may provide current at terminals T1 and T2 in some embodiments of the invention. As indicated in Fig. 6, level-shift currents I LS1 , I LS1 , I LS3 , and I LS4 actually flow through elements 38 - 44. Currents I LS1 - I LS4 respectively differ from currents I S1 - I S4 by the currents (if any) flowing through the respective control electrodes of amplifiers A1 - A4. The control-electrode current normally can be neglected. As a result, each level-shift current I LSi is substantially equal to corresponding supply current I Si (where i is 1, 2, 3, or 4). To have a good common-mode rejection ratio, V LS1 and V LS2 are preferably equal. Consequently, I LS1 and I LS2 are preferably equal. Likewise, V LS3 and V LS4 are preferably equal so that I LS3 and I LS4 are also preferably equal. It is desirable to avoid loading the circuitry that supplies circuit inputs V I1 and V I2 . Except for the situation in which other internal current of significant magnitude is supplied at terminals T1 and T2, this objective can usually be reached by setting I LS3 equal to I LS1 . Likewise, I LS4 is usually chosen to equal I LS2 . The result is that currents I LS1 and I LS4 are typically all equal. Nonetheless, voltages V LS3 and V LS4 may still respectively differ from voltages V LS1 and V LS2 . Current supply 46 utilizes currents I2S₁ - I S4 to control the values of voltages V LS1 - V LS4 in a way that reduces the minimum rail-to-rail V CM level for the power supply voltage to a value lower than that which would be needed if (a) V P1 and V P3 always equalled V I1 and (b) V P2 and V P4 always equalled V I2 . An understanding of how the level-shift control is accomplished can be facilitated by first considering what would happen if components 38 - 46 were absent. In that case, the operation would proceed basically in the manner described above for the differential amplifier of Fig. 1. When power supply voltage V PS drops below prior art value V PS0 , V CM would pass through (at least part of) the dead zone in which neither of portions 30 and 32 is operatively conductive. With the level-shift circuit present, the operation can still be described in terms of thresholds V TA and V TB shown in Fig.2. However, V CM in Eq. (1) must be replaced with the common-mode voltage V CMA at points P1 and P2. Differential portion 30 is turned on when: V CMA - V LL ≧ V TA In view of Eq. (3), V LS1 and V LS2 must be related to V TA as follows in order to make portion 30 operatively conductive if V CM is not high enough in itself to turn portion 30 on: V LS1 , V LS2 ≧ V TA - V CM - V LL Because supply 46 operates from the V HH supply, Eq. (4) is at least subject to the limitation that: V LS1 , V LS2 < V HH - V CM V CM in Eq. (2) must similarly be replaced with the common-mode voltage V CMB at points P3 and P4. Portion 32 is turned on when: V HH - V CMB ≧ V TB Accordingly, V LS3 and V LS4 must satisfy the following relationship with V TB so as to make portion 32 operatively conductive if V CM itself is not low enough to turn portion 32 on: V LS3 , V LS4 ≧ V TB = V CM - V HH Since supply 46 also operates from the V LL supply, Eq. (7) is at least subject to the restriction that: V LS3 , V LS4 < V CM - V LL A level shift is usually not needed when V PS is greater than V PSO (since V CM will be sufficient in itself to cause one or both of portions 30 and 32 to turn on). When V PS is less than V PSO so that a level shift is needed, thresholds V TA and V TB are preferably at their respective minimum values V MA and V MB . As a result, V MA and V MB can be respectively substituted for V TA and V TB in Eq. (4) and (7). Let V SATH be the minimum voltage spacing that supply 46 allows between V HH and the highest of V P1 and V P2 . Likewise, let V SATL be the minimum voltage spacing that supply 46 permits between V LL and the lowest of V P3 and V P4 . When V CM is not adequate by itself to cause at least one of portions 30 and 32 to become conductive, supply 46 thereby normally provides currents I S1 - I S4 at values that enable level shifts V LS1 - V LS4 to satisfy the following relationships: V HH - V CM - V SATH ≧ V LS1 , V LS2 ≧ V MA - V CM + V LL V CM - V LL - V SATL ≧ V LS3 , V LS4 ≧ V MB + V CM - V HH For the situation in which V TA and V TB vary in the manner indicated in Fig. 2, Figs. 7a and 7b show the operational regions that result from using the level-shift circuit. Fig. 7b is a 3X magnification of a lower portion of Fig. 7a encompassing the V MA -to-V PSO part of the V PS range. Lines 18, 24, and 26 are the V HH , V MA , and V MB lines as in Fig. 3. Lines 20A, 20B, and 22 of Fig. 7a have the same meaning for the invention that lines 20A, 20B, and 22 have in Fig. 3 for the prior art circuit of Fig.1. The point where the non-conductive region for portion 30 starts to overlap with the non-conductive region for portion 32 occurs when V PS is at a value V PSF as indicated in Fig.7a. This is the lowest value of the power supply voltage at which the differential amplifier of Fig. 6 can achieve rail-to-rail input capability. Due to the level shift, V PSF is less than V PSO . For the usual case in which V PSO equals V MA + V MB , V PSF is thus less than V MA + V MB . The lower limit for V PSF is slightly greater than the larger of V MA and V MB in the normal situation. More specifically, V PSF usually equals (a) V MA + V SATH or (b) V MB + V SATL , whichever is larger. Turning briefly to Fig. 7b, the three different zones of the triangular operational region formed by lines 22, 24 and 26 are labeled with reference numbers 48, 50, and 52. If V CM is in zone 48, the level-shift circuit preferably adjusts V LS1 and V LS2 according to Eq. (9) so as to turn portion 30 on. If V CM is in zone 50, the level-shift circuit preferably adjusts V LS3 and V LS4 according to Eq. (10) in order to turn porton 32 on. Finally, the level-shift circuit adjusts V LS1 - V LS4 according to Eqs. (9) and (10) so as to turn on both of portions 30 and 32 when V CM is in zone 52. Fig. 8 illustrates in general functional embodiment for current supply 46 in Fig. 6. In this embodiment, a common-mode generator 54 responsive to circuit inputs V I1 and V I2 produces operating voltages V YA and V YB that bear specific relationships to V CM . For example, each of voltages V YA and V YB may differ from V CM by an amount that is largely constant at a given temperature. In response to signals V YA and V YB , a level-shift current control circuit 56 generates a pair of control voltages V CL and V CH that control the operation of a set of level-shift current sources 58 suitably connected between the V LL and V HH supplies. Sources 58 provide supply currents I S1 - I S4 . Turning back to current control 56, it consists of voltage reference sources 60 and 62, differential amplifiers 64 and 66, and a linear AND/NAND generator 68. Reference sources 60 and 62 provide reference voltages V RA and V RB at values respectively "referenced" to low supply voltage V LL and high supply voltage V HH . In particular, V RA typically exceeds V LL by an amount V KA that is largely constant at a given temperature. V RB is likewise lower than V HH by an amount V KB that is largely constant at a given temperature. Amplifier 64 amplifies the difference between voltages V YA and V RA to produce an amplified voltage V ZA that gradually changes from high level V ZD to low level V ZC as V YA passes V RA . Amplifier 66 amplifies the difference between voltage V YB and V RB to produce an amplified voltage V ZB that gradually changes from V ZC to V ZD as V YB passes V RB . Figs. 9a and 9b respectively show how voltages V ZA and V ZB basically vary. Transition zones 70 and 72 in Figs. 9a and 9b are typically 100 millivolts in width. Generator 68 supplies (a) control voltage V CL as the linear AND of voltages V ZA and V ZB and (b) control voltage V CH as the linear NAND of voltages V ZA and V ZB . Referring to Fig.10, the top curve depicts how voltage V CL varies between low level V CLC and high level V CLD as a function of V CM . Transition zones 70 and 72 for V ZA and V ZB are reflected in V CL as respective transition zones 74 and 76. The centres of zones 74 and 76 are respectively "referenced" to V LL and V HH . That is, the center of zone 74 is separated from V LL by a voltage spacing V CLL that is largely constant at a given temperature. The center of zone 76 is similarly separated from V HH by a voltage spacing that is largely constant at a given temperature. As a consequence, the separation between zones 74 and 76 varies inversely with V PS . Fig.10 indicates that the V CL curve has a flat portion 78 situated between zones 74 and 76. It is usually preferably that zones 74 and 76 meet so that portion 78 compresses to a point. If zones 74 and 76 do so meet, an increase in V PS causes zones 74 and 76 to merge into each other. High level V CLD decreases in value. Typical level shift V LSi vary when control voltage V CL (or V CH ) has the indicated variation. Zones 74 and 76 are reflected directly in the I Si and V LSi curves. If a sufficient increase in V PS causes zones 74 and 76 to merge, high levels I SM and V LSM for the I Si and V LSi curves usually decrease. In this way, the level-shift circuit gradually shuts off as V PS rises. Moving to Fig. 11, it shows an embodiment of Fig. 6 in which amplifiers A1 - A4 are formed with bipolar transistors Q1 - Q4 arranged the same as in Fig. 1. Level shifts 38 - 44 are embodied with resistors R1, R2, R3, and R4 in Fig.11. Common-mode generator 54 of Fig.8 is implemented with components 30, 32, 34, and R1 - R4 in Fig.11. These components in combination with current supply 56 form a level-shift feedback control loop. Finally, current sources 58 of Fig. 8 are implemented with variable current sources S1, S2, S3, and S4 in Fig.11. Signal V CH controls current sources S1 and S2, while signal V CL controls current sources S3 and S4. In Fig. 11, V MA equals V BE + V SAT when main supply 34 is implemented with the circuitry of Fig. 4a or 4b. For the optimum case in which V RP equals V HH - V MB in Fig. 4b, the same applies to V MB . The minimum voltage across each of current sources S1 - S4 when they are fully conductive is 1V SAT . Since each spacing V SATL or V SATH thereby equals 1V SAT , V PSS equals V BE + 2V SAT . Using the above values of 0.6 volt for V BE and 0.1 volt for V SAT , VPSF is approximately 0,8 volt. Fig. 12 depicts a preferred way for implementing current control 56 in Fig.11. The circuitry in Fig. 12 differs from current control 56 in Fig. 8 in that the circuit of Figh. 12 employs a differential amplifier 78 to perform the functions of components 66 and 68 in Fig. 8. Amplifier 78 amplifies the difference between voltages V YB and V RB just as amplifier 66 does in Fig. 8. However, amplifier 78 has a gain control terminal that receives voltage V ZA from amplifier 64. This allows amplifier 78 to produce control voltages V CL and V CH in much the same way as shown in Fig. 10. Figs. 13a - 13c indicate the manner in which level-shift voltage V LSi preferably varies as a function of V CM for the differential amplifier of Fig. 11 when implemented with current control 56 of Fig. 8 or 12. For the case illustrated in Figs. 13a - 13c, resistors R1 - R4 all have the same resistance. Fig. 13a depicts the basic situation at standard temperature and 1.0-volt V PS . Fig. 13b illustrates how the level-shift circuit gradually "turns off" as V PS increases. No level shifting is needed when V PS is at or above 1.4 volts. As indicated in Fig. 13c, the level-shift circuit also automatically increases V LSi with decreasing temperature, and vice versa, to provide temperature compensation. Figs. 14a and 14b graphically show the idealized operational regions that arise for the differential amplifier of Fig.11 when main current supply 34 is respectively embodied with the circuitry of Figs. 4a and 4b. In Fig. 14a, the merged portion of lines 20A and 20B lying between V PSO and V PSF is equally separated from V LL and V HH . The same applies to the portion of line 20 located between V PFO and V PSF in Fig. 14b. A preferred bipolar embodiment for the present differential amplifier is shown in Fig. 15. Subject to the following comments, the elements used in Fig. 15 to implement the components of the amplifier of Fig. 11 can be determined by inspection. Main supply 34 is implemented with the circuit of Fig. 4b. Consequently, the transconductance of the amplifier in Fig. 15 is largely constant. A voltage reference source 80 supplies reference voltage V RP at a value lower than voltage V HH by an amount V KP that is largely constant at a given temperature. For supply 34 to operate optimally, V KP equals V BE + V SAT . That is, V RP equals V HH - V BE - V SAT . Current control 56 in Fig. 15 uses the arrangement shown in Fig.12. Based on what has been said above about Fig. 12, a detailed understanding of the various circuit elements in control 56 should be evident to a skilled artisan. Resistors R1 - R4 introduce an extra frequency pole. Capacitors C1, C2, C3, and C4 provide frequency compensation by introducing a frequency zero at approximately the same location as the extra pole. Fig. 16 illustrates two ways for implementing voltage reference sources 60, 62, and 80. Using only the circuit elements shown in solid line, V RB and V RP are separated from V HH by relatively constant amounts at a given temperature. However, it is usually desirable to employ portion 30 over more of the V PS range than portion 32 because NPN transistors require less base current than PNP transistors. This objective can be reached by using the entire circuitry (both solid line and dashed line) shown in Fig. 16. The full circuitry in Fig. 16 also avoid Zener problems that NPN components 30 and 78 might otherwise encounter. In this case, Fig. 17 illustrates the resulting idealized operational regions. The level-shift circuit shuts off when V PS goes above 1.6 volts. As indicated above, the level-shift circuit normally shuts off when V PS rises. Nonetheless, there may be some applications in which the level-shift circuit should remain fully on as V PS is increased. Figs. 18a and 18b indicate how level shift V LSi would vary with V CM in such an application for the case in which main supply 34 is implemented with the circuit of Fig. 4a. The basic variation at a 1.0-volt V PS is shown in Fig. 18a. Fig. 18b illustrates what happens as V PS is raised. Fig. 19 shows the resulting idealized operational regions. In the embodiments of the invention variously illustrated in Figs. 8 - 19, supply currents I S1 - I S4 are all approximately equal. Consequently, portion 30 receives a level shift when portion 32 receives a level shift, and vice versa. The level shifts received by portions 30 and 32 are normally close to the same value. Fig. 20 depicts an embodiment of Fig. 6 in which the level shifts supplied to portions 30 and 32 are largely independent of each other. This is achieved by using four additional variable current sources S5, S6, S7, and S8 arranged as indicated in Fig. 20. Sources S1, S2, S7, and S8 fix the level shift for portion 30. Sources S3 - S6 similarly fix the level shift for portion 32. In addition to control voltages V CL and V CH , current control 56 in Fig. 20 supplies control voltages V CL′ and V CH ′. Signals V CH and V CL ′ are generated at complementary values to control the level shift for portion 30. Signals V CL and V CH′ are likewise supplied at complementary values to control the level shift for portion 32. However, signals V CL and V CH ′ do not necessarily track signals V CH and V CL ′. While the invention has been described with reference to particular embodiments, this is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, the level shifts might be implemented with Schottky diodes to improve the noise behavior. Thus, various modifications and applications may be made by those skilled in the art without departing from the true scope of the invention as defined in the appended claims.

Claims: An electronic circuit for amplifying a circuit input signal differentially provided between first (T1) and second (T2) input terminals as respective first (V I1 ) and second (V I2 ) input voltages, the circuit comprising: main supply means (34), coupled between respective sources of a high supply voltage V HH and a low supply voltage V LL whose difference is a power supply voltage V PS that defines a power supply range, for providing opposite first (I A ) and second (I B ) operating currents; first means (30) for amplifying the voltage difference between first (P1) and second (P2) input points by largely dividing the first operating current (I A ) into a pair of amplified first internal signals, the first (P1) and second (P2) input points being respectively coupled to the first (T1) and second (T2) input terminals, the first means (30) being operatively conductive to so produce the first internal signals when the common-mode voltage V CM of the circuit input signal is in a portion of the supply range extending up to V HH ; second means (32) for amplifying the voltage difference between third (P3) and fourth (P4) input points by largely dividing the second operating current (I B ) into a pair of amplified second internal signals, the third (P3) and fourth (P4) input points being respectively coupled to the first (T1) and second (T2) input terminals, the second means (32) being operatively conductive to so produce the second internal signals when V CM is in a portion of the supply range extending down to V LL such that at least one of the differential means is operatively conductive as V CM traverses substantially the entire supply range when V PS is greater than or equal to a specified minimum level; and summing means (36) for combining the internal signals to generate at least one circuit output signal (I O ); characterized in that the circuit further comprises: level-shift means (38,40,42,44) for selectively causing the voltages at the first (P1) and second (P2) input points to be respectively higher than the first and second input voltages by respective first (38) and second (40) voltage level shifts and for selectively causing the voltages at the third (P3) and fourth (P4) input points to be respectively lower than the first and second input voltages by respective third (42) and fourth (44) voltage level shifts. A circuit as claimed in Claim 1, characterized in that the level shifts (38,40,42,44) are provided at values adequate to reduce the specified minimum level of V PS to a value below that which would occur if (a) the voltages at the first (P1) and third (P3) input points were always substantially equal to the first input voltage and (b) the voltages at the second (P2) and fourth (P4) input points were always substantially equal to the second input voltage. A circuit as claimed in Claim 2, characterized in that the first means (30) is operatively conductive when the magnitude of the difference between V LL and the common-mode portion V CMA of the voltages at the first (P1) and second (P2) input points is greater than or equal to a first threshold voltage V TA which can vary with V PS ; and the second means (32) is operatively conductive when the magnitude of the difference between V HH and the common-mode portion V CMB of the voltages at the third (P3) and fourth (P4) input points is greater than or equal to a second threshold voltage VTB which can vary with V PS ; characterized in that (a) the first (38) and second (40) voltage level shifts are provided at values greater than or equal to V TA - V CM + V LL but less than V HH - V CM and (b) the third (42) and fourth (44) voltage level shifts are provided at values greater than or equal to V TB + V CM - V HH but less than V CM - V LL . A circuit as claimed in Claim 3, characterized in that V TA and V YB have respective minimum values V MA and V MB , characterized in that the value of the specified minimum level of V PS is less than V MA + V MB . A circuit as claimed in Claim 4, characterized in that the value of the specified minimum level for V PS is greater than the larger of V MA and V MB . A circuit as claimed in Claim 3, characterized in that (a) the first (38) and second (40) voltage level shifts are largely equal and (b) the third (42) and fourth (44) voltage level shifts are largely equal. A circuit as claimed in any of the preceeding Claims, characterized in that the level-shift means comprises: network means, coupled between the input terminals (T1, T2) and the input points, (P1,P2,P3,P4) for providing the level shifts; and level-shift supply means (46) for providing current to the network means to control the values of the level shifts. A circuit as claimed in Claim 7, characterized in that the network means comprises a first level-shift element (R1) coupled between the first input terminal (T1) and the first input point (P1), a second level-shift element (R2) coupled between the second input terminal (T2) and the second input point (P2), a third level-shift element (R3) coupled between the first input terminal (T1) and the third input point (P3), and a fourth level-shift element (R4) coupled between the second input terminal (T2) and the fourth input point (P4). A circuit as claimed in Claim 8, characterized in that each level-shift element comprises a resistor. A circuit as claimed in Claim 8, characterized in that the level-shift supply means comprises a first current source (S1) coupled between the first input point (P1) and the V HH source, a second current source (S2) coupled between the second input point (P2) and the V HH source, a third current source (S3) coupled between the third input point (P3) and the V LL source, a fourth current source (S4) coupled between the fourth input point (P4) and the V LL source, and control means (56) for controlling conduction of the current sources. A circuit as claimed in Claim 10, characterized in that the level-shift supply means (46) further includes a fifth current source (S5) coupled between the first input terminal (T1) and the V HH source, a sixth current source (S6) coupled between the second input terminal (T2) and the V HH source, a seventh current source (S7) coupled between the first input terminal (T1) and the V LL source, and an eighth current source (S8) coupled between the second input terminal (T2) and the V LL source. A circuit as claimed in Claim 10 or 11, characterized in that each current source (S1...S8) provides progressively less current as the power supply voltage V PS rises so as to gradually turn off the level-shift means. A circuit as claimed in Claim 10, characterized in that the control means (56) provides at least part of the current sources with a control signal (V CH ,V CL ) that, as a function of V CH when V PS is sufficiently low, gradually changes (a) from a first control level to a second control level in a first voltage transition zone referenced to V HH and (b) from the second control level back to the first control level in a second voltage transition zone referenced to V LL . A circuit as claimed in Claim 13, characterized in that the voltage transition zones meet each other. A circuit as claimed in Claim 14, characterized in that the voltage transition zones shrink in size as V PS increases so that the difference between the two control levels decreases. A circuit as claimed in Claim 13, characterized in that the control means (56) (a) supplies the first control signal (V CH ) to the first (S1) and second (S2) current sources, (b) generates a second control (V CL ) signal having largely the opposite variation as the first control signal, and (c) supplies the second control signal to the third (S3) and fourth (S4) current sources. A circuit as claimed in Claim 13, characterized in that the control means (56) comprises: generating means (54) responsive to the input voltages for producing first and second operating voltages that bear specific relationships to V CM ; first reference means (62) for supplying a first reference voltage that is referenced to V LL at least when VPS is sufficiently small; second reference means (64) for supplying a second reference voltage that is referenced to V HH at least when V PS is sufficiently small; and linear means (64,66) responsive to the operating voltages and the reference voltages for producing the first control signal. A circuit as claimed in Claim 17, characterized in that the linear means (64,66) comprises: a first amplifying section (66) for amplifying the difference between the first operating voltage and the first reference voltage to produce a first amplified voltage; a second amplifying section (64) for amplifying the difference between the second operating voltage and the second reference voltage to produce a second amplified voltage; and AND/NAND means (68) for generating the first control signal largely as either the linear AND of the amplified voltages or the linear NAND of the amplified voltages. A circuit as claimed in Claim 17, characterized in that the linear means comprises: a first amplifying section (64) for amplifying the difference between the first operating voltage and the first reference voltage to produce a first amplified voltage; and a second amplifying section (78) having a gain control terminal responsive to the first amplified voltage for amplifying the difference between the second operating voltage and the second reference voltage to produce the first control signal. A circuit as claimed in Claim 17, characterized in that the generating means (54) comprises the level-shift elements, both differential means (30,32), and the main supply means (34). A circuit as claimed in Claim 20, characterized in that the first and second operating voltages are largely the voltages at which the first and second operating currents are respectively supplied. A circuit as claimed in any preceding Claim, characterized in that the first internal signals are differentially representative of the circuit input signal when the first means (30) is operatively conductive; and the second internal signals are differentially representative of the circuit input signal when the second means (32) is operatively conductive. A circuit as claimed in any preceding Claim, characterized in that each of the first and second (30,32) means comprises a pair of like-configured amplifiers, each amplifier having a first flow electrode, a second flow electrode, and a control electrode for regulating current transmission between the flow electrodes, the amplifiers (Q1,Q2) in the first means (30) having (a) their control electrodes respectively coupled to the first (P1) and second (P2) input points, (b) their first electrodes coupled together to receive the first operating current (I A ), and (c) their second electrodes respectively coupled to the summing means (36) to supply the first internal currents, the amplifiers (Q3,Q4) in the second means (32) having (a) their control electrodes respectively coupled to the third (P3) and fourth (P4) input points (b) their first electrodes coupled together to receive the second operating current (I B ), and (c) their second electrodes coupled to the summing means (36) to supply the second internal current, the amplifiers (Q3,Q4) in the second means (32) being complementary to the amplifiers (Q1,Q2) in the first means (30). A circuit as in Claim 23, charactrized in that charge carriers that move between the flow electrodes of each amplifier originate at its first electrode and terminate at its second electrode. A circuit as in Claim 24, characterized in that each amplifier is a bipolar transistor having an emitter, a collector, and a base respectively coupled to the first, second, and control electrodes of that amplifier.

Inventors: HUIJSING JOHAN HENDRICK, MARIS MARIEN GEORGE, HUIJSING, JOHAN HENDRICK, MARIS, MARIEN GEORGE
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: H03F3
IPC codes: H03F3, H03G3