System and method for atomic access to an input/output device with direct memory access

Abstract: A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40). When the buffer (47) is full, the CPU (32) tells the graphics subsystem (45), via a read from an I/O address on the graphics subsystem (45), that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem (45) parses the packet and executes the appropriate operations atomically.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates generally to a system and method for data transfer to a direct memory access (DMA) input/output (I/O) device which allows a client to access atomically the I/O device. Accessing atomically means that an instruction consisting of more than one individual operation is carried out completely, without interruption for any other operation. More particularly, it relates to such a system and method in a multiprocessor system where multiple processors concurrently access a single I/O device. An I/O device typically receives data and instructions from the system's main computing resources in one of two ways: either through direct memory-mapped access of I/O registers, or through a DMA mechanism by which the I/O device transfers data directly to and from the main memory subsystem. In either scheme, if the size of the data transfer is larger than an atomic access on the system bus, there are multiple concurrent clients of the I/O device, and the I/O device has a single input stream, there must be a mechanism to synchronize the I/O device among the several clients. 2. Description of the Prior Art: Mutual exclusion of I/O devices, or other shared resources, is typically achieved through software interlocks. Some processor instruction sets contain interlocked instructions, which allow a processor of an I/O device client to perform multiple logical instructions as a single atomic instruction. For example, a processor may test a bit in memory, branch if it is clear, and then set the bit, all within a single instruction. This allows mutual exclusion on shared resources to be implemented through software locks. The I/O device or other shared resource is considered "locked" or unavailable if the bit is set. The process that set the bit "owns" the resource. Systems without interlocked instructions must go through some other atomic protocol, perhaps synchronizing through the operating system or some other unique process. In particular, graphic subsystems in a multiclient, multiprocessor environment have states maintained internally that are set up in a previous operation and stay for a subsequent operation by the same processor. With interruption by another processor, there is no assurance that those states have been maintained. A technique for executing atomic instructions in this environment is therefore required. In EP-0330425 there is described a system for synchronizing execution of shared critical regions in a digital data processing system. A plurality of processors share a common memory which contains a synchronization level table to control access of the various processors to critical regions. In order to minimize transfers to the memory from the processors to gain access to critical regions, each processor monitors its own cache memory which contains a copy of the synchronization level table rather than the main memory itself. When a synchronization level previously unavailable becomes accessible, the cache copy being monitored will be invalidated, and the waiting processor will then access the main memory table. SUMMARY OF THE INVENTION A system for atomic access to an I/O device with direct memory access in accordance with this invention has at least one host data processor. A memory is connected to the at least one host data processor by a bus. A graphics subsystem comprising the input/output device is connected to the bus. The memory has a locked-down buffer for storing a command packet including a plurality of instructions for the graphics subsystem. The at least one host data processor includes a first program for generating the command packet. The graphics subsystem includes a graphics processor addressable by the at least one host data processor under control of the first program to determine availability of the graphics processor. The graphics processor includes a second program for initiating transfer of the command packet to the graphics subsystem as an input/output read transaction when the graphics processor is available. The second program executes the plurality of instructions atomically. A method for atomic access to an I/O device with direct memory access in accordance with this invention includes generating a command packet including a plurality of instructions for the input/output device. The command packet is stored in a memory having a physically contiguous locked-down memory buffer. The input/output device is interrogated to determine availability of the input/output device. A transfer of the command packet to the input/output device as an input/output read transaction is initiated when the input/output device is available. The plurality of instructions is executed atomically. The attainment of the foregoing and related objects, advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention, taken together with the drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a system in accordance with the invention. Figure 2 is a block diagram of another embodiment of a system in accordance with the invention. Figure 3 is a diagram showing mapping from an address of an I/O read transaction to a base address of a command packet transfer in practice of the invention. DETAILED DESCRIPTION OF THE INVENTION Turning now to the drawings, more particularly to Figure 1, a block diagram of a system 30 for atomic access to an I/O device with DMA is shown. A CPU 32 is connected to a floating point processor (FPU) 34 by bus 36. The CPU 32 is connected by a 32-bit system bus 38 to a random access memory (RAM) 40, a cache 42 and an interface 44 in graphics subsystem 45. The interface 44 is connected by bus 46 to graphics processor 48. The graphics processor 48 is connected by 120-bit graphics bus 50 to frame buffer 52. The frame buffer 52 are connected to a video digital to analog converter (DAC) 54 by bus 56. The DAC 54 is connected to video display 58 by line 60. In this system, the graphics subsystem 45 is an I/O device, and atomic access to it is required. Command packet interface 44 to the graphics subsystem 45 transfers geometry and graphics context information from main memory 40 to the graphics subsystem 45. For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer 47 in its own address space. Since the system 30 has DMA, the buffer 47 resides in the main memory system 40. The system 30 has a write-back cache 42, so it moves the contents of the buffer 47 into cache 42, generating little or no traffic on bus 38 when writing to the buffer. On systems with no DMA, this buffer will reside locally on the graphics subsystem. When the buffer 47 is full, the CPU 32 tells the graphics subsystem 45, via a read from an I/O address on the graphics subsystem 45, that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem 45 parses the packet and executes the appropriate operations, finding the details of the transaction syntax encoded in the first longword of the command packet. Execution of the commands in the packet is atomic, implying that all commands in one packet are executed before any commands in the next packet. Furthermore, the execution order is guaranteed to be the order in which the commands appear in the packet. The following discussion describes the general framework of application software using the command packet interface 44. A discussion of the command protocol follows. Table 1 below shows the outline of a procedure that issues a command to draw a line in the frame buffer 52. The global variable, pPacket, is the virtual addresses of a physically contiguous locked-down memory buffer serving as the graphics subsystem 45 command buffer 47. To avoid synchronization problems concerning the command packet memory, two command packet buffers 47 are used alternately. The alternation of command packets is handled by the switchPacket() routine. The Line procedure must first fill in the command packet with header information and vertex data. It then does a read from the I/O address, stamp , and receives status over the system bus 38. Table II enumerates the status values that can be returned by the graphics subsystem 45 as a result of the I/O read. Value Status Description 0 GOOD Data was accepted 1 BUSY Subsystem 45 is unavailable; retry later As rectangular clipping is done in hardware, the line is clipped successively to each clipping rectangle in the window's clip list. The clip rectangle is placed in the command packet by the fillLinePacket() routine. The Line procedure checks the status of the I/O read transaction. If the status is GOOD, then the graphics subsystem 45 immediately initiates the transfer of the command packet. A BUSY status causes a software retry, since the procedure just spins on the status word. Neither the code of Table I nor the procedural interface of Table II is appropriate for high performance graphics. They are shown to give a trivial example of the framework of the command packet interface. The command packet interface provides atomic access for high level commands, such as drawing lines and triangles. Access to the graphics subsystem 45 is gained through the framework described above. In order to guarantee an atomic operation containing both the I/O read transaction issued by the application and the command packet transactions issued by the graphics subsystem 45, the physical address of the command packet is encoded in the address of the I/O read transaction. This encoding provides the packet address to the graphics subsystem 45 so that it can carry out the command packet transfer, while the application receives status as part of the same atomic operation. Figure 2 shows a multiprocessor form of a system 30a, in which a first CPU 32a is connected to a FPU 34a by bus 36a. A cache 42a is connected to the CPU 32a by bus 38a. A second CPU 32b is connected to a FPU 34b by bus 36b. A cache 42b is connected to the CPU 32b by bus 38a. Other than this construction and the fact that the system 30a operates in a multiprocessor mode, the construction and operation of the Figure 2 embodiment of the invention is the same as in the Figure 1 embodiment. As shown in Figure 3, bits 21:2 of the I/O read transaction address 70 contain bits 30:11 of the command packet address 72. In practice, the exact bit positions are dependent on the system bus employed. The positions specified are for a 32-bit system bus 38. If the available physical address space is less than 32 bits, then the high order bits are ignored. The remaining bits of the address of the I/O read transaction contain an implementation specific base address that is decoded by the graphics subsystem 45, indicating that a packet transfer should be initiated. The address of the command packet is created as follows: bits 10:0 of the command packet address 72 are zero, forcing the packet to be aligned on a 2048 byte boundary; bits 30:11 equal bits 21:2 of the I/O read transaction address 70; bit 31 of the command packet address is zero. Figure 3 shows the mapping from the address 70 of the I/O read transaction to the base address 72 of the command packet transfer. It should further be apparent to those skilled in the art that various changes in form and details of the invention as shown and described may be made which fall within the scope of the claims appended hereto.

Claims: A system for atomic access to an input/output device (45), comprising: at least one host data processor (32); a memory (40) connected to said at least one host data processor by a bus (38); the input/output device comprising a data processing subsystem connected to said bus (38); said memory having a lockable buffer (47); characterized by: said at least one host data processor (32) including a first program for generating a command packet having a plurality of instructions for said subsystem and for storing said command packet in said lockable buffer with said lockable buffer set to a locked state; said subsystem including a subsystem processor (48) connected to said bus and addressable by said at least one host data processor (32) under control of said first program to determine availability of said subsystem processor (48); means for transferring said command packet to said subsystem when said subsystem processor is available; said subsystem processor (48) including a second program for executing said plurality of instructions atomically. The system of claim 1, further characterized by: said memory having at least two lockable buffers (47) for storing command packets, each of said at least two buffers having a separate lock mechanism, said first program storing command packets in said at least two buffers in alternative succession. The system of claims 1 or 2, further characterized by: said subsystem comprising a graphics subsystem (45) that includes a graphics processor (48) connected to said bus. The system of claim 1, 2 or 3, further characterized by said transferring means being adapted to transfer said command packet to said subsystem as a direct memory access transaction. The system of claim 1, 2, 3 or 4, further characterized by: said at least one host data processor including a multiplicity of data processors (32a, 32b) that concurrently access said subsystem (45). A method for atomic access to an input/output device (45) comprising a data processing subsystem, the method comprising the steps of: in a host data processor (32), generating and storing a data packet in a memory (40); said host data processor (32) addressing the input/output device (45) to determine availability of the input/output device; transferring the packet to the input/output device when the input/output device is available; characterized by: said data packet comprising a command packet including a plurality of instructions for the subsystem (45); said host data processor (32) storing the command packet in a portion of said memory comprising a lockable buffer (47) with said lockable buffer set to a locked state; and said data processing subsystem (45) executing the plurality of instructions atomically. The method of claim 6, further characterized by: said memory (40) having at least two lockable buffers (47) for storing command packets, each of said at least two buffers having a separate lock mechanism; and said host data processor (32) storing command packets in said at least two buffers (47) in alternative succession. The method of claim 6 or 7, further characterized by: said subsystem comprising a graphics subsystem (45) that includes a graphics processor (48) connected to said bus. The method of claim 6, 7 or 8, further characterized by: said packet transferring step being performed as a direct memory access transaction. The method of claim 6, 7, 8 or 9, further characterized by: said at least one host data processor including a multiplicity of data processors (32a, 32b) that concurrently access said subsystem (45).

Inventors: CHOW SHU-SHIA, KELLEHER BRIAN MICHAEL, CHOW, SHU-SHIA, KELLEHER, BRIAN MICHAEL
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1990
Main classification: G06F15
IPC codes: G06F13, G06F3, G06F15