Character generator comprising a startstop oscillator

Abstract: A character generator comprises a phase-coupled clock signal generator which is implemented as a start-stop oscillator (1) to which a line signal is applied. The clock frequency is dependent on an adjusting value (F). For adjusting and monitoring the clock frequency, the clock signal generator is provided with a counter (2). This counter counts the number of clock pulses occurring during a predetermined period and thus supplies a counting value (C). A control circuit (3) compares the counting value (C) with a reference value and adapts the adjusting value (F) in such a way that the oscillator frequency is within a predetermined range. Such a character generator is suitable for On Screen Display applications in a television receiver.

Description: 1. FIELD OF THE INVENTION. The invention relates to a character generator for generating characters on a display screen, which character generator comprises a start-stop oscillator. The invention particularly relates to character generators for use in television receivers, CD video players, camera recorders and television monitors for displaying so-called On Screen Display information. 2. DESCRIPTION OF THE PRIOR ART. Character generators comprising a start-stop oscillator are generally known. In the known character generators the start-stop oscillator constitutes a clock signal generator to which an external periodical reference signal is applied, for example, the line-synchronizing signal in a television receiver. This reference signal will hereinafter be referred to as line signal. The start-stop oscillator oscillates at a predetermined frequency during the visible portion of a television line when the line signal has a first value and does not oscillate during the flyback period of the television line when the line signal has a second value. The clock signal generated by the start-stop oscillator is therefore discontinuous. The phase coupling of the clock signal, which determines the stability of the displayed characters, is established in that the oscillation starts under the same conditions whenever the first value of the line signal occurs. The frequency of the clock signal during the visible portion of the television line determines the width of the displayed characters. In the known character generators the frequency is independent of the line signal and is only determined by the dimensioning of components intended therefore. It has been found difficult to realise the frequency-determining components of a start-stop oscillator in an integrated circuit (IC) within required tolerance limits. The known clock signal generators therefor comprise external precision components or external adjustable components for adjusting the desired frequency. However, such components as well as the required connection pins on an IC raise the costprice of the character generator. Moreover, adjusting the components is a time-consuming and costly activity. European Patent Application EP-A-0 103 983 discloses a technically different solution for generating the clock frequency in a character generator. The system comprises a Phase Locked Loop (PLL) circuit. The clock frequency of a controlled oscillator is divided to generate a timing signal which is compared with the line signal. The frequency is controlled in response to the phase difference between said signals. PLL based oscillators are used in television receivers to provide a display clock which is phase locked and frequency locked to the horizontal line frequency. For simple applications such as On-Screen-Display of relatively large characters on a TV screen, where frequency locking is not necessary, the PLL solution is too complicated and expensive. European Patent Application EP-A-0 235 441 discloses a start-stop oscillator for use in a sampling oscilloscope. The oscillator is triggered by a reference signal. Once triggered, the clock frequency is adjusted such that a precise number of clock pulses is generated during a period derived from a further reference signal. 3. SUMMARY OF THE INVENTION. It is an object of the invention, inter alia, to further improve a character generator comprising a start-stop oscillator. According to the invention the start-stop oscillator is therefore of a type whose frequency is adjustable by means of an adjusting value and in that the character generator further comprises control means for adapting the adjusting value if the oscillator frequency has not a value between two predetermined limits. The invention is based on the recognition that it is sufficient if the frequency has a value between two predetermined limits and is further stable. In the character generator of the invention, the oscillator frequency is autonomously brought within predetermined limits without using external adjustments. Variations of the frequency due to, for example, temperature effects are accepted as long as the resulting display width remains within predetermined limits. The frequency is only adapted after it has varied for more than a predetermined value. The only requirement which is imposed is that at least one adjusting value yields a clock frequency within the desired range. Critical components are not required to achieve this. Therefore, components can be used which have such a tolerance that they can be realised in an IC. This renders the pins for connecting external components superfluous, thus also avoiding the problem that such pins, which convey signal variations with the generated frequency, generate electromagnetic radiation causing interference with other adjacent circuits. It is to be noted that it is known per se from United States Patent US 4,103,251 to compare an oscillator frequency of a start-stop oscillator with a desired frequency and to adapt an adjusting value in response thereto. However, in this circuit, which is not a character generator, the difference between actual and desired frequency is continuously accumulated in order that the oscillator frequency is a constant multiple of the frequency of the periodical reference signal. A favourable embodiment of the character generator is characterized in that the control means are adapted to count clock pulses of the oscillator during the period when the first value of the reference signal is available and to generate a counting value corresponding thereto. Said counting value is compared with a reference value which corresponds to a desired frequency, and the adjusting value is adapted if the difference between the counting value and the reference value exceeds a predetermined value. Such control means can be realised by means of simple digital components and integrated on an IC, together with other circuits. More particularly it is thereby achieved that the character generator can be completely accommodated in a microprocessor IC for controlling, for example television receivers. A character generator generally comprises, inter alia , a horizontal position counter to which the clock signal is applied for positioning the pixels of the characters to be displayed in a picture line. In one embodiment of the character generator this horizontal position counter is adapted to generate the counting value. This reduces the number of digital components and thus has a further cost-saving effect. A further embodiment of the character generator according to the invention is characterized in that the line signal is applied to the start-stop oscillator via delay means which are adapted to delay the transition from the first to the second value of the reference signal. This leads to the effect that the oscillator reaches its non-oscillating state only with a predetermined delay upon the transition to the second value of the line signal. This is particularly sensible if the absence of the clock signal during the flyback period of the television line is acceptable, but must be limited in duration. This occurs, for example, in character generators comprising a dynamic memory to which so-called refresh pulses must be applied during the flyback period. 4. BRIEF DESCRIPTION OF THE FIGURES. Fig. 1 shows diagrammatically a character generator according to the invention. Fig. 2 shows signal waveforms of some signals shown in Fig. 1. Fig. 3 shows an embodiment of the start-stop oscillator shown in Fig. 1. Fig. 4 shows signal waveforms of some signals shown in Fig. 3. Fig. 5 shows the flow chart of a control program for use in the character generator shown in Fig. 1. Fig. 6 shows a time diagram to explain the operation of the control program shown in Fig. 5. Fig. 7 shows the flow chart of another control program for use in the character generator shown in Fig. 1. Fig. 8 shows a time diagram to explain the operation of the control program shown in Fig. 7. Fig. 9 shows diagrammatically a further implementation of the character generator shown in Fig. 1. Fig. 10 shows signal waveforms of some signals shown in Fig. 9. 5. DESCRIPTION OF EMBODIMENTS. Fig. 1 shows diagrammatically the structure of a phase-coupled clock signal generator according to the invention. The clock signal generator comprises a start-stop oscillator 1 having a first input SS to which a periodical control signal REF is applied and a further input to which an adjusting value F is applied. The start-stop oscillator 1 supplies an output signal CLK which will be further referred to as clock signal. This clock signal is applied to a counter 2. The counter 2 generates a counting value C and applies it to a control circuit 3. The control circuit 3 is adapted to generate the adjusting value F in response to the received counting value C and a reference value R stored in the control circuit. The control circuit 3 further receives the line signal REF at an input IRQ and applies a reset signal CLR to the counter 2. In practice, the control circuit 3 may comprise a microprocessor, for example the type 84C640 of Philips. The input IRQ is then preferably a so-called "interrupt request" input. The counter 2 is further adapted to generate a column number COL indicating the horizontal position of the characters to be displayed. Moreover, the counter 2 supplies a line pulse H to a line and row counter 6. In response thereto, line and row counter 6 generates a row number ROW indicating the vertical position of the characters to be displayed, and a line number LIN corresponding to the picture line to be displayed within the row determined by row number ROW. The column number COL and the row number ROW constitute an address which is applied to a display memory (RAM) 7 in which a character code is stored for the characters to be displayed. The character code addressed by the column number COL and the row number ROW is applied to a character memory (ROM) 8 which comprises a matrix composed of pixels for each character. The character memory 8 further receives the line number LIN and generates the pixels for each character which must be displayed in the line with line number LIN. In a parallel-series converter 9 the pixels obtained are successively applied as a pixel signal Y to an output for display on a display screen. The microprocessor 3 is connected by means of an address and data bus ADB to display memory 7 of the character generator 10 in order to store the character codes of characters to be displayed in this memory. It is to be noted that it is possible to form the connections, shown in Fig. 1, between microprocessor 3 and the other circuits in a conventional manner as a single bidirectional bus connection. The microprocessor 3 can in a known way be adapted to control picture and sound functions as well as to tune to stations. To explain the character generator shown in Fig. 1, Fig. 2 shows time diagrams of some signals shown in Fig. 1. The line signal REF is shown in Fig. 2A. It has, for example a frequency of 15,625 Hz and comprises a display period of 60 µsec with the logic value "0" and a flyback period of 4 µsec with the logic value "1". The clock signal CLK of the start-stop oscillator 1 is shown in Fig.2B. It comprises a series of clock pulses at a frequency determined by the adjusting value F during the display period of the line signal REF and has a constant value during the flyback period of the line signal REF. The control circuit 3 generates the reset signal CLR shown in Fig. 2C during the flyback period. As a result, the counter 2 assumes a count 0. During the display period the count is raised by 1 at each clock pulse of the clock signal CLK. Fig. 2D shows a number of counts. After the display period has finished, the further supply of clock pulses to the counter 2 is discontinued. The count then reached is a counting value C which corresponds to the number of generated clock pulses during the display period of line signal REF. The counting value C is applied to the control circuit 3. This circuit is adapted, in a manner to be further described, to compare the counting value C with the reference value R and to adapt the adjusting value F, if necessary. Fig. 3 shows an embodiment of a start-stop oscillator 1 for use in the clock signal generator of Fig. 1. A current source 11 generates a charge current I, whose value is determined by an applied 6-bit adjusting value F. To this end the current source 11 comprises a plurality of separate current sources 11a-11f which are switched by means of switching elements 12a-12f by a bit of the adjusting value F. Such current sources may be realised, for example, by means of transistors arranged as current mirrors whose mutual ratios of their emitter surfaces determine the value of the current. The current source 11 further comprises a current source 13 determining a minimum value of the charge current I. The current sources 11a-11f are preferably dimensioned in such a way that the current source I is linearly dependent on the applied adjusting value F. The charge current I is applied to a capacitor 14. A voltage VC which is applied to a bistable threshold circuit 15 is produced across this capacitor 14. Such a threshold circuit is generally known by the name of Schmitt trigger. The output of the threshold circuit 15 is coupled to a discharge circuit 17 via a first input of an OR gate 16. A second input of this OR gate receives the line signal REF. Fig. 4 shows some time diagrams to explain the start-stop oscillator shown in Fig. 3. It will be provisionally assumed that the line signal REF shown in Fig. 4A has the logic value "1" (t<t0). The discharge circuit 17 is then activated by the output of OR gate 16 so that the charge current I flows through the discharge circuit 17 and the capacitor 14 is and remains discharged. The voltage VC shown in Fig. 4B is then zero and the output of the threshold circuit 15 (Fig. 4C) has the logic value "0". Subsequently it is assumed that the line signal REF has the logic value "0" (t0<t<t4). Both inputs of the OR gate 16 are now "0" and the discharge circuit 17 is no longer activated. The charge current I now flows through the capacitor 14 and generates a voltage VC increasing with time (t0<t<t1) across this capacitor. When a first threshold value (V1 in Fig. 4B) is reached, the output of the threshold circuit will acquire the logic value "1" and thereby activate the discharge circuit 17 via the OR gate 16. The capacitor 14 will now be discharged so that the voltage decreases (t1<t<t2). When a second, lower threshold value (V2 in Fig. 4B) is reached, the output of the threshold circuit acquires the logic value "0". As a result, the discharge circuit 17 is no longer activated so that the voltage across the capacitor will increase again (t2<t<t3). Said charging and discharging of the capacitor 14 is thus periodically maintained so that the clock signal CLK shown in Fig. 4C is produced at the output of the threshold circuit. Subsequently, the line signal REF assumes the logic value "1" again (t>t4) and capacitor 14 is discharged completely. Clock pulses are then no longer generated. The frequency of the clock signal, further referred to as clock frequency, is determined by the discharge time t1-t2 and the charge time t2-t3. The discharge time is substantially constant, whereas the charge time is dependent on the charge current I and hence on the adjusting value F. The clock frequency is thus adjusted by means of the adjusting value F. For F=0 the lowest frequency is generated, whereas for F=63 the frequency is maximum. At a constant adjusting value F the phase O¦ shown in Fig. 4 between clock signal and line signal is constant. The start-stop oscillator shown in Fig. 3 is very suitable for integration with a character generator. It will hereinafter be assumed by way of example that the desired clock frequency for this purpose is nominally 8 MHz with a tolerance of +_250 kHz. The start-stop oscillator shown in Fig. 3 is then dimensioned for a frequency range of, for example 4 to 16 MHz so as to guarantee that at least one of the possible adjusting values F (F=0...63) corresponds to the desired frequency, even in the case of a large spread of the capacitance. In practice it appears that the generated clock frequency is substantially linearly dependent on the adjusting value F. The frequency difference corresponding to two successive adjusting values is approximately 200 kHz. However, an exact linearity is not important for the invention. As already previously noted, the line circuit 3 shown in Fig. 1 is preferably constituted by a microprocessor. This processor is adapted to perform a control program for adapting the adjusting value F. Fig. 5 shows the flow chart of such a control program. In a step 20 a predetermined initial value is assigned to the adjusting value F. In the embodiment the value F=15 has been taken for this purpose. In a step 21 the control program waits for an "interrupt request" occurring at the input IRQ (see Fig. 1) of the control circuit 3. This request indicates that there is a transition from the logic value "0" to the logic value "1" in the line signal. This transition marks the start of the flyback period. In a step 22 the control program generates the reset signal CLR at, for example a line of an output port. Subsequently, the control program waits in a step 23 for another interrupt request at the input IRQ. Meanwhile the counter 2 receives clock pulses at a clock frequency which is determined by the initial adjusting value F. At this adjusting value the start-stop oscillator generates a clock frequency which may considerably deviate from the desired 8 MHz due to tolerances. The counter 2 counts the number of clock pulses during the display period of the line flyback signal (60 µsec) and reaches the counting value C. In a step 24 this counting value C is read by the control program. A reference value R corresponding to the desired clock frequency of 8 MHz is stored in the control circuit 3. This reference value is R=480 (60 µsec * 8 MHz). Since deviations of +_250 kHz (corresponding to +_ 15 clock pulses) are permitted, it is tested in a step 25 whether the counting value C is larger than R+15. If this is the case, the clock frequency is too high and the adjusting value F is lowered by 1 in a step 27. The clock frequency is thereby adjusted at a value which is approximately 200 kHz lower. If the clock frequency is not too high, it is tested in a step 26 whether the counting value C is smaller than R-15. If this is the case, the clock frequency is too low and the adjusting value F is raised by 1 in a step 28. The clock frequency is thereby raised by approximately 200 kHz. If the counting value C has a value between said two limits, the adjusting value is not adapted. The control program subsequently returns to step 22 in order to perform steps 22-28 again. In the control program shown in Fig. 5 the program loop comprising steps 22-28 is traversed whenever an interrupt request occurs, i.e. at every flyback period. This has the advantage that the frequency is adjusted rapidly. Successively traversing all possible 64 adjusting values even takes no more than 4 msec. However, such a high speed is not necessary in the assumed application as a clock signal generator for a character generator in a television receiver. It is therefore sensible to perform the steps of said program loop once per television frame or field. The control program can then be accommodated in the conventional microprocessor for controlling functions such as tuning, picture and sound control, and the like. Fig. 6A shows by way of example how the clock frequency is adjusted as a function of time by means of the control program shown in Fig. 5. In this example the adjusting value is ultimately F=18 at which the clock frequency is 7.76 MHz which corresponds to a counting value of C=466. Fig. 6B illustrates that the clock frequency is automatically corrected if it has increased, for example, due to temperature effects in the start-stop oscillator. An increase to 8.25 MHz (C=495) is permitted, and subsequently the control program lowers the adjusting value by 1 to F=17. The clock frequency corresponding thereto is 8.05 MHz and falls within the fixed limits again. A further embodiment of the control program is shown in Fig. 7. In this Figure the steps 21-26 are fully identical to the steps having the corresponding numerals in Fig. 5. The adjusting value is now obtained by a successive halving of an interval of adjusting values. In a step 27 an initial value 0 is assigned to a lower limit L of the interval and an initial value 63 is assigned to an upper limit H. Subsequently a value halfway the interval is assigned to the adjusting value F in a step 28 by means of the operation F=(L+H)/2. If this adjusting value is too large, a new interval is determined in a step 29 by rendering the upper limit H equal to the adjusting value. The lower limit remains unchanged in this case. If the adjusting value is too small, a new interval is determined in a step 30 by rendering the lower limit L equal to the adjusting value. In this case the upper limit remains unchanged. Subsequently a following adjusting value halfway the new interval is determined in a step 31. Fig. 8 shows an example of the clock frequency generated as a function of time by this embodiment. In this example the adjusting value F=19 is ultimately reached, which corresponds to a clock frequency of 7.97 MHz. On an average, the desired clock frequency is reached faster with the control program shown in Fig. 7 than with the control program shown in Fig. 5. However, if the clock frequency varies, for example due to temperature effects, it generally takes more iterations to reach the new adjusting value. At each iteration, the clock frequency varies shockwise, which causes unpleasant effects on the display screen when using a character generator. It is therefore sensible to use the control program shown in Fig. 7 only for adjusting the clock frequency when the television receiver is switched on and when changing stations (i.e. when the line flyback signal is disturbed temporarily) and subsequently to use the control program shown in Fig. 5 for further monitoring the adjusted clock frequency. It may be noted with respect to the character generator shown in Fig. 1 that clock signals are not generated during the flyback period of the line flyback signal. In some cases it may be a drawback that this period is relatively long. Fig. 1 shows by means of broken-line blocks 4 and 5 an extension of the character generator with which the clock signal generation is continued for a predetermined period at the start of the flyback period. Its operation will be explained with reference to Fig. 9 showing the relevant portion of the character generator of Fig. 1. Identical reference numerals denote identical blocks. The clock signal generator is now provided with a delay circuit 4 with which the start of the flyback period is delayed a predetermined number of clock pulses N. Its operation is explained with reference to some signal waveforms shown in Fig. 10. The line flyback signal REF (Fig. 10A) is applied to a delay element 41 and to a first input of an AND gate 42. The output signal RF1 of the delay element 41 (Fig. 10B) is applied to a second input of the AND gate 42. After the occurrence of the logic value "1" at the input of the delay element 41, its output signal RF1 maintains the logic value "0" for N clock pulses. The output signal RF2 of AND gate 42 (Fig. 10D) has the logic value "0" during this period so that start-stop oscillator 1 actually continues to generate the clock signal (Fig. 10C). After N clock pulses the output signal RF1 of the delay element acquires the logic value "1". The output signal RF2 of AND gate 42 then also acquires the logic value "1" so that the start-stop oscillator 1 no longer generates a clock signal. At the start of a new display period the line flyback signal REF assumes the logic value "0". This value is applied without any delay to the start-stop oscillator 1 by AND gate 42 so that clock signals are generated again. The delay element 41 can be realised by means of conventional counter means, for example an N-bit shift register. When using the delay circuit 4, the period in which the counter does not receive clock pulses (RF2="1" in Fig. 10D) has become shorter. It may then be necessary to relieve the control program from the task of reading the counting value within this period and of resetting the counter 2. To this end the clock signal generator shown in Fig. 9 has a reset circuit 5. This circuit comprises a flipflop 51 and an inverting OR gate 52 with which the reset signal CLR shown in Fig. 10E is generated. The counter 2 also comprises an output register 21 in which the counting value which has been reached is clocked in by the reset signal CLR. The control circuit 3 can now read the counting value at any arbitrary instant. It is to be noted that the counting value stored in the output register 21 is now C+N. This can be taken into account in the control program. Finally it is to be noted that the counting value C may be obtained in another manner. For example, it is possible to have a first counter, which receives the clock signal from the start-stop oscillator, count a predetermined number of clock pulses. Thus, this first counter generates a time interval whose duration is determined by the clock frequency. The duration of said time interval is subsequently measured by a second counter by means of a further clock signal having a known frequency. Such a further clock signal is, for example, a crystal-controlled clock signal, which is already available for driving the microprocessor.

Claims: A character generator for generating characters on a display screen, comprising an input for receiving a reference signal (REF), a start/stop oscillator (1) to which the reference signal is applied and which is adapted to oscillate in response to a first value of the reference signal and to refrain from oscillation in response to a second value of the reference signal, characterized in that the start/stop oscillator is of a type whose frequency is adjustable by means of an adjusting value (F) and in that the character generator further comprises control means (2,3) for adapting the adjusting value if the oscillator frequency has not a value between two predetermined limits. A character generator as claimed in Claim 1, wherein the control means are adapted to count (24) clock pulses of the oscillator during the period when the first value of the reference signal is available and to generate a counting value (C) corresponding thereto, compare (25,26) said counting value with a reference value (R) which corresponds to a desired frequency, adapt (27,28; 29-31) the adjusting value if the difference between the counting value and the reference value exceeds a predetermined value. A character generator as claimed in Claim 2, which comprises a horizontal position counter (2,6) to which the oscillator frequency is applied and which is adapted to position pixels of characters to be displayed in a picture line, wherein the horizontal position counter is further adapted to generate said counting value (C). A character generator as claimed in Claim 2, wherein the reference signal is applied to the start/stop oscillator via delay means (4) which are adapted to delay the transition from the first to the second value of the reference signal. A character generator as claimed in any one of the preceding Claims, wherein the start-stop oscillator comprises a capacitor (14), a current source (11) for charging the capacitor, in which the value of the current (I) corresponds to the applied adjusting value (F), a discharge circuit 917) for discharging the capacitor, a threshold circuit (15) for switching on the discharge circuit in response to reaching a predetermined first voltage (V1) across the capacitor and for switching off the discharge circuit in response to a second voltage (V2) across the capacitor, and a stop circuit (16) for switching on the discharge circuit in response to the second value of the applied reference signal (REF).

Inventors: DEN OUDEN JOSEPH ADRIANUS AUGU, DEN OUDEN, JOSEPH ADRIANUS AUGUSTINUS
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: H03L7
IPC codes: H03K4, G09G5, H03K3, H03L7, H04N5