Pulse compressing apparatus for a radar system using a long pulse

Abstract: In a radar system using a long pulse containing a modulated signal, the received signal is converted to a short pulse by circuitry including means (103) for generating weight coefficients, delay means (7) for delaying the weight coefficients so as to generate N weight coefficients differing in delay time and N arithmetic means (116,126,...,1N6) which receive a common input signal having the form of time series data sampled in a prescribed sampling period. The arithmetic means (116) multiply the input signal by the received weight coefficients and then add the multiplication results up to the prescribed number. The outputs from the arithmetic means (116) are added by adding circuit (107) to produce a compressed signal corresponding to the short pulse.

Description: The present invention relates to a radar system using a long pulse, and more particularly to a pulse compressing apparatus which is required when a received long pulse reflected from a target is to be converted into a radar video signal. In such a radar system, a long pulse, whose carrier frequency is subject to linear modulation or linearly changes with a chirp signal, is used, because the long pulse is more advantageous in range resolution and accuracy as well as providing greater transmit pulse energy while applying pulse compression operation. Where such long pulse is used, the pulse should be compressed as disclosed, for example, in Merrill I. Skolnik, Introduction to RADAR SYSTEMS, International student edition (McGraw-Hill KOGAKUSHA, LTD., 1962), 10.9 Pulse Compression in Chapter 10. This pulse compression can be represented by correlation processing indicated by Equation (1): Pulse compression output y(t) where x r (τ) is a received signal and ref (t), a reference signal. Whereas the reference signal is so determined as to maximize the compressed output, or as to result in a matched filter, the complex conjugate signal of the transmitted signal is used as the reference signal because the received signal is a reflection of the transmitted signal. It is known to those skilled in the art that the correlation processing in the time domain can be represented by a multiplication in the frequency domain, so that the Equation (1) can be represented by Equation (2) below in the frequency domain: Y(f) = X r (f)·X * t (f) where Y(f) is the Fourier transform of the compressed output y(t); X r (f), that of the received signal x r (t); and X * / t(f), that of the complex conjugate signal of the transmitted signal (i.e. the reference signal ref(t)). A digital pulse compressing apparatus according to the prior art is a materialization of Equation (2), and may have such a configuration as illustrated in FIG. 1, for instance. Referring to FIG. 1, a received signal and a transmitted signal (which are complex conjugate signals) are respectively sampled and converted into digital signals by analog-to-digital (A/D) converters 201a and 201b and, after the effects of the sampling are reduced by window function processors 202a and 202b, undergo the Fourier transform at high speed by fast Fourier transform (FFT) processors 203a and 203b. The outputs of the FFT processors 203a and 203b are multiplied by a multiplier 204, and the multiplied output undergoes inverse FFT processing by an inverse FFT processor 205 to give a pulse compressed signal on the time domain. Since the radar system which, because of its task to scan space, requires pulse compression on a real time basis, pipeline FFT processors are often utilized as the FFT processors 203a and 203b. Such pipeline FFT processors are described in detail, for instance, in the U.S. Patent No. 4,222,050, "Moving Target Indication Radar". In a radar system, conditions pertaining to the distance to the target to be tracked and the state of clutter are not constant but vary, so that the system should be adaptively responsive to such variations. A radar system using a long pulse can meet this requirement by adaptively altering the pulse compression ratio. As well known, the pulse compression ratio is defined by B × τ where τ is the duration of the long pulse and B = f₂ - f₁, the carrier frequency change from f₁ to f₂ over the pulse duration. Thus, in order to alter the pulse compression ratio, the number of sampled data points to be processed in the digital pulse compression processing, corresponding to the duration of the long pulse, should be altered. In the prior art digital pulse compressing apparatus described above which uses FFT processing, however, the number of sampled data points to be processed is fixed, and it is difficult to alter this number. In the pipeline FFT processor for real time continuous FFT processing in particular, in order to change the number of data points to be processed, the extent of delay by a delay means and the number of processing stages should be changed, entailing an extremely complex configuration. There would further be required window function processing to suppress the effects of sampling, and an inverse FFT processor to return the signal domain from the frequency domain to the time domain. A digital pulse compressing apparatus using conventional FFT processing therefore involves the problem that it is difficult to adaptively alter the pulse compression ratio while achieving real time continuous processing. In order to adaptively alter the pulse compression ratio while achieving pulse compression on a real-time basis, processing should be accomplished in the time domain instead of the FFT processing in the frequency domain as in the prior art of FIG. 1. Now, to make possible digital processing, Equation (1) is quantized to obtain Equation (3), which represents pulse compression for a discrete signal: where w(i) is a weight coefficient. The configuration to realize this Equation (3) is shown in FIG. 2, which is well known as a transversal filter, see e.g. Merrill I. Skolnik, Radar Handbook, McGraw-Hill Book Co., 1970, Section 20.5 Figure 19(a) on pages 20.21. In FIG. 2, this transversal filter has constituent units each comprising a combination of an arithmetic element 401 and a delay 402. Further, as many such units as the number of points to be processed are connected in cascade, and an adder 410 adds the outputs of the arithmetic elements 401 so as to realize Equation (3). If the value of the weight coefficient to be provided to each arithmetic element 401 is made by the product of a general weighting coefficient factor and a window function factor in advance, this transversal filter can achieve window function processing simultaneously with pulse compression processing. If the delivery or inhibition of the output of each arithmetic element to be supplied to the adder 410 is controlled and the weight coefficient is respectively varied, the pulse compression ratio can, in principle, be adaptively altered. However, in order to alter the pulse compression ratio in the transversal filter of FIG. 2, each arithmetic element should be individually given a weight coefficient and, moreover, a control signal itself should be individually provided to each arithmetic element, with due consideration for its operational timing, resulting in an extremely complex configuration, which is virtually impossible to realize. According to the present invention there is provided digital pulse compression apparatus for use in a radar system transmitting a long pulse containing a modulated signal, and adapted to convert a received signal into a short pulse, the apparatus comprising weight coefficient generating means for generating weight coefficients; N arithmetic means respectively receiving N weight coefficients; and adding means for adding outputs of said N arithmetic means to produce a compressed signal constituting said short pulse; characterized by delaying means for successively delaying said weight coefficients to generate said N weight coefficients differing in delay time; and in that said N arithmetic means receive in common an input signal consisting of time series data sampled in a predetermined sampling period, and multiply said input signal by the respectively received weight coefficients, and add a predetermined number of said multiplication results. A preferred digital pulse compression apparatus embodying the invention is described in more detail below and permits simple and ready adaptive alteration of the pulse compression ratio while performing real-time continuous processing. In the preferred pulse compression apparatus embodying the invention, the filter coefficient and the timing signal are transferred sequentially from the arithmetic unit of the first stage to that of the final stage while being delayed by a prescribed time period at each stage, but there is no need for individual control. Meanwhile, an input complex signal (a phase detected received signal), which has the form of a series of sampled values, is directly supplied in parallel to all of the arithmetic units. Each arithmetic unit performs a filtering operation on the input complex signal on the basis of the filter coefficients, and its arithmetic result in outputted in accordance with the entered timing signal. The outputs are added with the predetermined relationship of time delays therebetween. As a result, there is performed pulse compression processing in the time domain, and window function processing can also be executed at the same time. The pulse compression ratio can be readily altered simply by varying the number of arithmetic units at work. The invention will be described in more detail by way of example with reference to the drawings, in which: FIG. 1 is a block diagram illustrating a digital pulse compression apparatus according to the prior art; FIG. 2 illustrates a known configuration of a conventional transversal filter; FIG. 3 is a block diagram illustrating a preferred embodiment of the present invention; and FIG. 4 is a diagram for describing the arithmetic operation of the embodiment of FIG. 3. Referring to FIG. 3 illustrating a preferred embodiment of the present invention, a digital pulse compression apparatus is equipped with an input terminal 101 for receiving an input complex signal, an output terminal 102 for supplying a compressed pulse output, a weight coefficient generator 103 for generating a weight coefficient (or filter coefficient) modified by a window function factor, a timing controller 104 for supplying a timing signal to determine delivery of arithmetic result, an operating mode controller 105 for altering the pulse compression ratio according to the conditions of a radar system, a plurality of arithmetic units 116, 126 ... ..., 1N6 connected in cascade so that the filter coefficient and the timing signal can be serially supplied, and an adding circuit 107 for adding the outputs of the arithmetic units 116 to 1N6. In this figure, the input complex signal from the input terminal 101 is supplied in parallel to terminals 1 of all of the arithmetic units 116 to 1N6. The input complex signal, as is well known to those skilled in the art with respect to a coherent radar system, is obtained by phase-detecting a received signal with phase-reference having a 90° phase difference and by A/D-converting them in a predetermined sampling period. This is described in the U.S. Patent No. 4,222,050 referred to above, for example. The weight coefficient generator 103 generates the N filter coefficient W₀ to w N-1 each of which corresponds to N data from x₀ to x N-1 in the complex signal and is the product of a conventional weighting factor and a window function factor (to be described in detail below). These filter coefficients are entered to a filter coefficient input terminal 2 of the arithmetic unit 116 of the first stage. A plurality of kinds of the filter coefficients are stored in advance in the weight coefficient generator 103 in correspondence to different types of radar processing, and selection therebetween is performed in accordance with a control by the operating mode controller 105. Further, the number of filter coefficients is varied as the pulse compression ratio is altered. The timing signal from the timing controller 104 is supplied to a timing input terminal 3 of the arithmetic unit 116. The repeating cycle of the timing signal from the timing controller 104 can be altered with the control of the operating mode controller 105. Furthermore, each of the arithmetic units 116 to 1N6 has an output terminal 4 for supplying a delayed filter coefficient to the arithmetic unit of the next stage, another output terminal 5 for supplying a delayed timing signal to the arithmetic unit of the next stage, an arithmetic result output terminal 6, and an input terminal 13 for receiving a control signal from the operating mode controller 105. The arithmetic units 116 to 1N6 are connected in cascade such that the filter coefficient output terminal 4 and the timing control signal output terminal 5 of the arithmetic unit at a previous stage are connected to the filter coefficient input terminal 2 and the timing signal input terminal 3, respectively, of the arithmetic unit at the next stage. All these arithmetic units 116 to 1N6 are identically structured and, as illustrated with respect to the arithmetic unit 116, each comprises a filter coefficient delay 7 having a delay time corresponding to the data sampling period and disposed between the input and output terminals 2 and 4, a timing signal delay 8 having the same delay time as the delay 7 and disposed between the input and output terminals 3 and 5, a filtering circuit 15 including a multiplier 9, an adder 10 and a delay 11 having the same delay time as the delay 7, and a control circuit 14 responsive to the control signal from the operating mode controller 105 for activating or inactivating the corresponding arithmetic unit. Since the two delays 7 and 8 each of the arithmetic unit are connected in cascade over the N stages, the filter coefficient and the timing signal are successively transferred from the first arithmetic unit 116 to the final arithmetic unit 1N6. To describe hereupon the operation of the filtering circuit 15, the multiplier 9 multiplies the filter coefficient and the input complex signal, and the adder 10 adds the output of the multiplier 9 and that of the delay 11 to supply the sum of the delay 11 and an output gate 12. Therefore, the filtering circuit 15 successively adds the output of the multiplier 9 and, while the sum result is delivered via the output gate 12 at a timing determined by the timing signal and, by this timing, the stored data in the delay 11 is cleared. As a result, filtering operation is executed in each arithmetic unit at the processing timing for instance as shown in FIGS. 4 (a) to (e). Referring to FIGS. 4 (a) to (e), it is now considered a case in which N data x₀ to x N-1 among the input complex signal are processed as shown in FIG. 4 (a). The weight coefficient generator 103, as described above, generates N filter coefficients w₀ to w N-1 corresponding to the N data x₀ to x N-1 . They become the input filter coefficients for the arithmetic unit 116 at the first stage (FIG. 4 (d)). Thus in the arithmetic unit 116, the filter coefficient w i corresponds to the datum x i , and the arithmetic operation of is executed by using N time periods (FIG. 4 (b)). The output gate 12 is opened upon completion of the addition of N results to supply to the output terminal 6. Then, the input filter coefficients to the arithmetic unit 116 (FIG. 4 (d)) are delayed by the predetermined time period and become the input filter coefficients to the arithmetic unit 126 of the next stage (FIG. 4 (e)). There is a lag by one in the relationship between these input filter coefficients and the input data, with the filter coefficient w (i-1) corresponding to the input signal x i and so forth. The timing signal is also supplied with a lag of one each. Therefore, this arithmetic unit 126 executes the operation of (FIG. 4 (c)). Similarly, in the succeeding arithmetic units 136 to 1N6, the required filter coefficients are successively inputted and, thus, the corresponding arithmetic operations are performed. Continuous processing thus takes place on a real-time basis. These operational results are added by the adding circuit 107, and the pulse compressed output is delivered from the output terminal 102. To describe in further detail the operational timings of the arithmetic unit 116, the input state T of the delay 8, the output stage T′ of the delay 8, the filter coefficients w and w′ at the input and output of the delay 7 and the output y from the output gate 12 are as tabulated below, where x i is an input datum. Thus, when t is (N - 1), the output y of is supplied. Next, with respect to the arithmetic unit 126 of the next stage, the input datam x i , the input filter coefficient w (the filter coefficient w′ in the arithmetic unit 116), the output A of the multiplier 9, the output B of the adder 10, the output C of the delay 11, the input timing T, and the output y are as tabulated below. Therefore, the arithmetic unit 116 of the first stage performs the processing based on the input data x₀ to x N-1 , and the arithmetic unit 126 performs the processing based on the input data x₁ to x N . It is thus seen that convolutions are executed. Next, the filter coefficient (the weight coefficient) generator will be described. As shown by the Equation (3), the pulse compression can be represented by where i can be seen as i ·Δt (Δt: the unit of time quantization). Since the reference signal for the pulse compression here is its own complex conjugate signal x*(i·Δt), the weight coefficient w(i·Δt) can be represented, in terms of its relationship to the window function factor P(i·Δt), by: w(i·Δt) = P(i·Δt) ·x*(i·Δt) The window function factor P(i·Δt) referred to above, used to sample data on the time domain, is commonly known to those skilled in the art as, for instance, the Fourier coefficient for use in a sampling system. While the window function factor, as it is for processing on the time domain, should be converted for use in the frequency domain in the FFT processing as stated above, the processing according to the present system takes place in the time domain, and the window function factor can be multiplied by the reference signal to be treated as the weight coefficient. This is another significant advantage. As this reference signal is the complex conjugate signal of the transmitted signal in a radar system and accordingly is known in advance, the generation of the product of its multiplication by the window function factor as the weight coefficient can be readily accomplished. Next will be described how the pulse compression ratio is altered. When the alteration of the compression ratio, i.e. that of the number of points to be processed, is to be achieved, the operating mode controller 105 is actuated. Thus each of the plurality of arithmetic units 116 to 1N6 is provided with the control circuit 14, which is so structured as to control the inactivation of the filtering operation or to control the choice between transferring and not transferring the outputs of the delays 7 and 8 to the next stage. Therefore, the operating mode controller 105 can control the prescribed number of the arithmetic units to actuate through the control circuits 14. At the same time, corresponding to an increase or a decrease in the manner of the arithmetic units in operation, the number of filter coefficients delivered from the weight coefficient generator 103 is switched, and the output timing signal from the timing controller 104 is also altered. In short, the pulse compression ratio can be altered as desired merely by working the operating mode controller 105. As hitherto described, the digital pulse compressing apparatus embodying the present invention can be constructed in a simple manner with a plurality of arithmetic units each having the same configuration and sequentially transferring the filter coefficient and the timing signal to the next, and makes it possible to perform window function processing simultaneously with pulse compression processing in the time domain. Further, the pulse compression ratio can be adaptively altered by changing the number of the arithmetic units to be worked.

Claims: Digital pulse compression apparatus for use in a radar system transmitting a long pulse containing a modulated signal, and adapted to convert a received signal into a short pulse, the apparatus comprising: weight coefficient generating means (103) for generating weight coefficients; N arithmetic means (116 to 1N6) respectively receiving N weight coefficients; and adding means (107) for adding outputs of said N arithmetic means to produce a compressed signal constituting said short pulse; characterized by delaying means (7) for successively delaying said weight coefficients to generate said N weight coefficients differing in delay time; and in that said N arithmetic means (116 to 1N6) receive in common an input signal consisting of time series data sampled in a predetermined sampling period, and multiply said input signal by the respectively received weight coefficients, and add a predetermined number of said multiplication results. Digital pulse compression apparatus as claimed in claim 1, further comprising control means (105) for controlling the operation or non-operation of said N arithmetic means and for controlling the number M of the outputs to be applied to said adding means, where M≦N. Digital pulse compression apparatus as claimed in claim 2, wherein said coefficient generating means (103) generates M weight coefficients in response to said control means. Digital pulse compression apparatus as claimed in claim 3, wherein the number of the multiplied results added by said arithmetic means (116 to 1N6) is M. Digital pulse compression apparatus as claimed in claim 2, 3 or 4, further comprising timing generating means (104) responsive to said control means for generating a timing at which the added result in said arithmetic means (116 to 1N6) is delivered, and delaying means for successively delaying said timing and respectively supplying delayed timing to said N arithmetic means. Digital pulse compression apparatus as claimed in any preceding claim, wherein said weight coefficient is represented by the product of a complex conjugate signal of the transmitted pulse and a window function factor.

Inventors: KIUCHI EIICHI, NAKAMURA HIROSHI, KIUCHI, EIICHI, NAKAMURA, HIROSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G01S13
IPC codes: G01S7, G01S13