Improved external memory accessing system

Abstract: There is disclosed a new and improved external memory accessing system for use in a microprocessor. The system includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions. The system further includes means responsive to a current load instruction for determining if the address of the register specified in the load instruction is within the physical address cache and means for conveying to the external memory, at the beginning of the execution stage of the load instruction, a previously translated external memory physical address corresponding to a specified register stored in the physical address cache. Also disclosed is a new and improved address generator for generating a new translated external memory physical address which is conveyed to the external memory and to the physical address cache for updating the physical address cache.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to an improved external memory accessing system and more particularly to an external memory accessing system for a reduced instruction set (RISC) processor which employs register-indirect addressing and external memory. Microprocessors are well known in the art. One type of microprocessor is a reduced instruction set (RISC) processor having a pipelined architecture. Such processors process serial instructions through a series of stages including, for example, a fetch stage, a decode stage, an execute stage, and a write-back stage. Such processors operate at very high speeds and due to their pipelined architecture, are capable of efficiently executing instructions with a minimum of hardware. In such processors, each instruction is processed through the aforementioned stages. Hence, a first instruction may be in the decode stage while a second or next instruction is being fetched. In the next cycle, both instructions move down the pipeline by one stage wherein the first instruction is now being executed while the second instruction is being decoded. When a processor of this type is called upon by an instruction to perform an execution upon data, it does so by acting upon the operands contained in a register file. Hence, in order to execute such instructions, it is first necessary for the processor to load the data or operands into register file. As a result, load instructions are common in such processors for this purpose. In order to load data into a register file from an external memory, the external memory must first be accessed. In order to access external memory, prior art processors must first compute the address of the external memory and then translate the address into a physical address of the external memory. This process takes time and can adversely affect the efficiency of the processor. Other processors compute the external memory address before the load instruction and store the address for later use. However, such processors still must translate the address after the load instruction. While this type of processor exhibits improvement over the first-mentioned processor, improvement on this process is still desireable. A high-performance processor requires low latency access to an external memory in order to achieve its potential performance. Preferably, the memory should supply an item of data within one cycle after the processor requests it. The term "zero-wait-state" is commonly applied to a memory system with this capability. This refers to the fact that the processor does not have to wait for a memory access to complete, because the access is always completed quickly. Unfortunately, the technical requirements on a zero-wait-state memory make it very difficult and expensive to implement. This is particularly true at the very high operating frequencies that characterize RISC processors. The combined requirements for zero-wait-state memory and very high operating frequencies present a severe impediment to the performance of these types of processors. The present invention overcomes the aforementioned problems with respect to accessing an external memory. The present invention, while using a one-wait-state memory system is capable of achieving the performance of a zero-wait-state memory. The present invention is claimed in claim 1. There is provided an address generator for use in a processor for generating a multiple-bit translated external memory physical address responsive to a base address and an offset address. The address generator includes a plurality of tables, each table containing a plurality of external memory physical addresses and computing means for arithmetically processing the base address and the offset address to generate a multiple-bit virtual address. The computing means is arranged to generate the multiple-bit virtual address one bit at a time and to provide the tables with a given number of the bits first generated. The tables are responsive to the first generated bits to derive from each table one potential translated physical address while the computing means generates the other bits of the multiple-bit virtual address. The address generator further includes translation means coupled to the computing means and to each of the tables for comparing the generated multiple-bit virtual address to the potential translated physical addresses to determine which one of the potential translated physical addresses is the multiple-bit translated external memory physical address. In the accompanying drawing, by way of example only, the sole figure is a schematic block diagram of an external memory accessing system embodying the present invention. Referring to this drawing, the external memory accessing system generally includes an address generator 12, a physical address cache 14, a select circuit 16, and a scan means 26. The external memory accessing system 10 is adapted to access physical memory locations within an external memory 18 for a microprocessor including a first plurality of registers 20, herein referred to as load registers, a second plurality of registers 22, herein referred to as execution registers, and an instruction register 24 which includes the multiple-bit instructions to be executed by the processor. Although illustrated separately for purposes of explanation, load registers 20 and execution registers 22 could be one set of registers as will be appreciated by those skilled in the art. The external memory accessing system 10 responds to load instructions for accessing a specified physical memory location in the external memory 18 by conveying to the external memory, at the beginning of the execution stage of a load instruction, a translated physical address of the memory location to be accessed in the external memory. Once accessed, the external memory can then transfer the data stored in the particular physical memory location to one of the execution registers 22 as operand data to permit the processor to act upon the operand data. One such load instruction is illustrated in the instruction register 24. The load instruction includes a first set of bits 28 which identify the instruction as a load instruction, a second set of bit 30 which identify the execution register in which the operand data is to be loaded into, and a third set of bits 32 which identifies the load register which contains an untranslated memory address corresponding to the physical address location of the external memory 18 to be accessed. The load instruction may include further bits of information such as function information which are not important to the present invention. As will be seen hereinafter, the system 10 responds to the load instruction by accessing the physical memory location of the external memory 18 corresponding to the address contained in the register identified by the third set of bits 32 so that the operand data may be transferred to the execution register identified by the second set of bits 30. The address generator 12 includes an adder 34, an address translation logic 36, and a plurality of tables 37 and 38. The adder 34 includes a first input 40 and a second input 42. The first input 40 is coupled to a bus 44 for receiving a base address and input 42 is coupled to another bus 46 for receiving an offset address. The address generator 12 generates a translated external memory physical address responsive to receipt of the base address at input 40 and the offset address at input 42. As is well known in the art, such address generation can be provided in response to an add instruction wherein the offset address is added to the base address. The offset may represent a positive or negative number. The address generator therefore generates a translated external memory physical address when a new external memory physical address is required. The tables 37 and 38 each include a plurality of external memory physical addresses. As the adder 34 computes the new external memory virtual address, it provides the tables 37 and 38 with a given number of its first generated bits at output 43 referred to herein sa the table entry select bits. In accordance with the preferred embodiment, the adder 34 provides the tables 37 and 38 with the most significant five bits of the first ten bits that it generates. In response to receiving the entry select bits by the adder 34, each of the tables 37 and 38 provides a potential translated external memory physical address to the address translation logic. Since the system 10 includes two such tables, the address translation logic is provided with two such potential translated external memory physical addresses. While the tables 37 and 38 are accessed and provide the potential address to the address translation logic 36, the adder 34, in parallel, generates the remaining bits of the external memory virtual address. In accordance with this preferred embodiment, the remaining bits comprise 22 bits so that the complete external memory virtual address includes 32 bits. The remaining bits are provided at output 45. After the adder has computed all of the bits of the external memory virtual address, the address translation logic then compares the generated address to the two potential translated external memory physical addresses. In doing so, it selects the potential translated external memory physical address which corresponds to the address generated by the adder 34 and selects that address as the translated external memory physical address. It then conveys the translated external memory physical address to the select circuit 16. It also conveys the translated address to the physical address cache 14 which will be described in detail hereinafter. If a new address is not required to be generated by the address generator, in other words, the untranslated address resides in one of the load registers 20, the adder 34 will pass the address from the load register to the address translation logic without acting upon that address. The untranslated address is then translated in the translation logic which then provides the translated external memory physical address to the select circuit 16. The physical address cache 14 is a fully-associative cache which is accessed by absolute register-numbers. It includes a plurality of entries including load register numbers and corresponding translated external memory physical addresses which were previously translated in response to previous load instructions. When the address generator 12 generates a new translated external memory physical address, it conveys that address to the cache 14 for the purpose of updating the cache. The cache also stores the corresponding load register number. The cache 14 may also be updated by the translated external memory physical address resulting from the pass-through of an untranslated address from one of the load registers 20 through the adder 34 and which was then translated by the translation logic 36. If the processor fetches a load instruction which requires the external memory 18 to be accessed, the scan means 26 during the decode stage of the load instruction scans the physical address cache 14 for the load register number contained in the third set of bits 32 of the load instruction. If the scan means 26 locates the register number identified in the load instruction, it will cause the physical address cache 14 to convey the previously translated external memory physical address to the select circuit 16. In this manner, the translated external memory physical address can be provided to the external memory during the execution stage of the load instruction. As a result, the memory system is provided with an additional cycle to perform the memory access. If the scan means 26 does not locate the register number identified in the load instruction in the physical address cache 14, the physical address cache 14 is then updated using the address generator 12 previously described. Since the tables 37 and 38 are accessed while the adder 34 is in the process of completing the computation of the new physical address, the external memory accessing system 10 can still provide the external memory 18 with the appropriate physical memory address in an efficient manner. As previously mentioned, the new translated external memory physical address is also conveyed to the physical address cache 14 to update the physical address cache 14 so that the updated entry may be reused as necessary. Hence, if the physical address cache 14 requires updating, there are two associative searches in the physical address cache on every cycle. One search is for a possible load and the other is for a possible address update. As can be seen from the foregoing, the physical address cache is a fully-associative cache which is accessed by absolute register numbers. It stores the physical addresses and other information related to the translation. The cache incorporates a plurality of entries, for example, four entries, for containing physical addresses. The physical address cache thus contains a useful set of address translations for any loads which may be encountered in the instruction stream. The cache is searched during the decode of a load instruction. If the address register for the load has a valid translation in the cache, the address can appear at the external memory at the beginning of the execution stage of the load instruction. The physical address cache thus keeps a high fraction of useful translated addresses. As can also be seen from the foregoing, an address can be updated in a register, requiring the contents of the physical address cache to be correspondingly updated during normal instruction execution. During the execution of any instruction, the physical address cache is searched by the scan means 26 for an entry associated with the destination register of the instruction. If the destination register has a translation in the cache, and if the associated address is successfully translated, the current entry is updated to reflect the new address. As previously mentioned, the updating requirement requires two associative searches in the physical address cache of every cycle. One search is for a possible load (read) and the other for a possible address update (write). As can be further seen from the foregoing, the present invention provides early address generation by virtue of the adder 34 working in close conjunction with the address translation logic 36 and the tables 37 and 38. The adder 34 executes the computation of a new address by a small subset of instructions, as, for example, immediate loads and adds and subtracts with small displacements of, for example, 10 bits. The address generator is implemented so that any address it computes has been translated by the end of the address computation. Specifically, the table entry select bits which it generates allow the accessing of the tables 37 and 38 to proceed in the first half cycle while remaining bits of the new address are computed. The address generator operates during the execute stage of every instruction. It updates translated addresses in the physical address cache and/or provides the external memory with a translated address directly. Hence, it exhibits a distinct advantage over prior art address generators which operate only during the execution of a load instruction. Because the system utilizes register-indirect addressing, all address computations may be performed explicitly by instructions before a load is performed. As a result, a new address by an address computation is available to the external memory at the beginning of an execution of a load and can be used to improve the performance of the load. In addition, the physical address cache eliminates the penalty of address translation for loads that do not require address computation. Moreover, when address computation is required before a load instruction, the address may be computed when a load instruction is in the decode stage. Since the new address is computed during the decode stage of the load instruction, the new translated physical address may be available ahead of time instead of waiting on the execution of the load instruction to perform address translation so that the translated external memory physical address is still transmitted to the external memory at the beginning of the execute stage of the load instruction. The translated address is also placed into the physical address cache 14 for later reuse. This also allows an additional cycle for the memory access.

Claims: A processor including an address generator (10) for generating a multiple-bit translated external memory physical address responsive to a base address and an offset address, the address generator (10) comprising: a plurality of tables (37, 38) each table containing a plurality of external memory physical addresses; and computing means (34) for arithmetically processing the base address and offset address to generate a multiple-bit virtual address, characterised in that the computing means (34) is arranged to generate the multiple-bit virtual address with a given number of first generated bits; the tables (37, 38) being responsive to the said given number of first generated bits to derive from each table one potential translated physical address while the computing means (34) generates the other bits of the multiple-bit virtual address; and translation means (36) coupled to the computing means (34) and to each of the tables (37,38) for comparing the generated multiple-bit virtual address to the potential translated physical addresses to determine which one of the potential translated physical addresses is the said multiple-bit translated external memory physical address. A processor as defined in Claim 1 wherein the said plurality of tables (37, 38) comprise two tables. A processor as defined in Claim 1 or Claim 2 wherein the computing means (34) comprises an adder. A processor as defined in Claim 3 wherein the adder comprises a first input (40) for receiving the base address and a second input (42) for receiving the offset address. A processor as defined in any one of the Claims 1-4 wherein the said given number of first generated bits is five bits. A processor as defined in anyone of the Claims 1-5 wherein the computing means (34) comprises a first output (43) coupled to the said tables (37, 38) for providing the tables with the said given number of first generated bits, and a second output (45) coupled to the translation means (36) for providing the translation means with the said other bits of the multiple-bit virtual address. A processor as defined in Claim 6 wherein the translation means (36) is arranged to use the said other bits of the multiple-bit virtual address to determine which one of the potential translated physical addresses is the said multiple-bit translated external memory physical address. A processor as defined in Claim 7 wherein the multiple-bit translated external memory physical address comprises thirty-two bits.

Inventors: JOHNSON WILLIAM MICHAEL, JOHNSON, WILLIAM MICHAEL
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1990
Main classification: G06F12
IPC codes: G06F12, G06F9