Buffer circuit with an electrostatic protector

Abstract: A buffer circuit comprises an interface node (IN, OUT), a bipolar transistor (Q₁, Q₂) having a collector connected to a first power source (Vcc), an emitter con­ nected to a second power source (GND), and a base, for transferring a signal supplied to and from the interface node, and a diode structure (D) formed between the emit­ ter and base of the bipolar transistor (Q₁, Q₂), the diode structure containing a PN junction reversely cou­ pled across the emitter-base junction of the bipolar transistor (Q₁, Q₂).

Description: The present invention relates to an electrostatic protector for protecting an input circuit or an output circuit of a semiconductor integrated circuit, and more particularly, to a circuit for protecting a base-emitter junction of a transistor against an incoming surge voltage. An electrostatic protector is installed in an output circuit of a semiconductor integrated circuit, such as is shown in Fig. 5 or Fig. 6, or in an input circuit such as that shown in Fig. 7. In the output circuit of the integrated circuit (IC) of Fig. 5, a collector-emitter path of an output NPN transistor Q 1 and a resistor R are connected in series between a Vcc power source line (referred to as a Vcc line) and a ground potential line (referred to as a ground line). The emitter of the transistor Q 1 is connected to an output terminal OUT. A diode D 1 , for absorbing a positive surge current, is connected between the emitter of the transistor Q 1 and the Vcc line, while a diode D 2 , for absorbing a negative surge current, is connected between the emitter of the transistor Q 1 and the ground line. The diodes D 1 and D 2 of this protector respectively provide electrostatic protection for the junction between the base and emitter of the transistor Q 1 against positive and negative surge voltages coming in through the output terminal OUT. In the output circuit of Fig. 6, a collector-emitter path of an output NPN transistor Q 1 and a resistor R are connected in series between a Vcc power source line (referred to as a Vcc or power line) and a ground potential line (referred to as a ground line). In this circuit, resistor R is P type diffusion resistor, and formed in N type resistor island, and the voltage potential Vcc is supplied to the resistor island. Therefore, surge diode structure is equivalently formed between resistor R and Vcc. The emitter of the transistor Q 1 is connected to an output terminal OUT, and a diode D 2 , for absorbing a negative surge current, is connected between the emitter of the transistor Q 1 and the ground line. In the input circuit of Fig. 7, a resistor R is connected between the emitter of an input NPN transistor Q 2 and a ground line. The base of the transistor Q 2 is connected to an input terminal IN, and the collector thereof is connected to an internal circuit. A diode D 1 , for absorbing a positive surge current, is connected between the base of the NPN transistor Q 2 and an Vcc line, while a diode D 2 , for absorbing a negative surge current, is connected between the base of the transistor Q 2 and the ground line. In the case of the above protector, the diodes D 1 and D 2 respectively provide electrostatic protection for the junction between the base and emitter of the transistor Q 2 against positive and negative surge voltages coming in through the input terminal IN. Let us consider in detail a case where a surge voltage arrives at the output terminal OUT or the input terminal IN. If the surge voltage is negative, the ground line always exhibits a low impedance, and therefore a negative surge current caused by the negative surge voltage passes through the diode D 2 . In other words, the negative surge current is absorbed by the diode D 2 . If, on the other hand, the surge voltage is positive, the Vcc line exhibits a low impedance, a positive surge current caused by the positive surge voltage passes through the diode D 1 or an equivalent diode D 1-2 . In other words, the positive surge current is absorbed by the diode D 1 or D 1-2 . When the Vcc line is open, or in a high impedance state, a surge current absorbing path including the diode D 1 or D 1-2 is open, in which case the surge voltage, when positive, will destroy the base-emitter junction of the transistor Q 1 or Q 2 . Thus, in the case of a positive surge voltage, the electrostatic protecting circuit to which the present invention is not applied fails to absorb the positive surge current by the related diode, when the Vcc or power line is in a high impedance state. Accordingly, the base-emitter junction of the NPN transistor will be possibly destroyed. DE-A-33 43 201 shows an output buffer circuit having a bipolar transistor and a diode. However, the diode is not a parasitic diode and there is no area reduction advantage. JP-A-60 241 252 shows an input buffer including a bipolar transistor and a diode, but with no suggestion that the diode could be a parasitic diode. Accordingly, an object of the present invention is to provide a buffer circuit which is capable of protecting the base-emitter junction of an input or output bipolar transistor against a surge voltage coming in through an input node or an output node under any impedance state of the power line and/or ground line. According to the invention, there is provided a buffer circuit as set out in claim 1. Another aspect of the invention is set out in claim 8. With the buffer circuit arranged thus, a surge voltage coming in through the interface node (IN, OUT) is attenuated in the following way. A surge current caused by the surge voltage temporarily goes to a base-emitter path, but it is pulled to the diode structure (D) formed between the base and emitter, that is, it by-passes the bipolar transistor (Q 1 , Q 2 ) and is absorbed by a circuit preceding or succeeding the transistor. The reason for this is that the PN junction of the diode structure is inversely coupled with the PN junction in the transistor structure. Accordingly, the protector absorbs the surge current, thereby protecting the PN or base-emitter junction contained in the transistor structure against an impact by the surge voltage. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing an embodiment of an electrostatic protector according to the present invention; Fig. 2 is a pattern illustration of the electrostatic protector of Fig. 1; Figs. 3 and 4 are circuit diagrams showing other embodiments of an electrostatic protector according to the present invention; Figs. 5 to 7 are circuit diagrams of electrostatic protectors to which the present invention is not applied; Fig. 8 is a circuit diagram showing another embodiment of an electrostatic protector according to the present invention; Fig. 9 is a pattern illustration of the electrostatic protector of Fig. 8; Figs. 10 and 11 are circuit diagrams showing additional embodiments of an electrostatic protector according to the present invention; Fig. 12 is a circuit diagram showing an output circuit having a plurality of output terminals incorporating an electrostatic protector according to the present invention; Fig. 13 is a structural and schematic illustration of the protector of Fig. 12; Fig. 14 is a circuit diagram showing an input circuit having a plurality of input terminals incorporating an electrostatic protector according to the present invention; Fig. 15 is a circuit diagram showing another input circuit having a plurality of input terminals incorporating an electrostatic protector according to the present invention; and Figs. 16 and 17 are circuit diagrams showing differential amplifiers incorporating an electrostatic protector according to the present invention. Embodiments of the present invention will be described hereinafter, with reference to the accompanying drawings. Fig. 1 shows an emitter follower output circuit incorporating a static protector according to the present invention. As can be seen from this figure, a collector-emitter path of an output NPN transistor Q 1 and a resistor R are connected in series between a Vcc line and a ground line. The emitter of the transistor Q 1 is connected to an output terminal OUT, with a diode D 2 for absorbing a negative surge current being connected between the emitter of the transistor Q 1 and the ground line. The output circuit of Fig. 1 has a pattern as shown in Fig. 2, and, as can be seen from this figure, reference numeral 21 designates the Vcc line; 22, the ground line; C, B, and E, the collector, base, and emitter regions of the transistor Q 1 ; 23, a base interconnection wire; and 24, an emitter interconnection wire. A P type diffusion region 25 is in contact with the ground line 22, an N type region 26 within the P type diffusion region is in contact with the emitter interconnection 24, and a pn junction between the regions 25 and 26 forms the diode D 2 . An N type island (resistor island region) region 27 has an N type region of a high concentration formed therein, which is connected to the base interconnection wire 23. A resistor (resistor R) is also formed in the N type island 27, and has a P type diffusion region which is connected at one end to the emitter interconnection 24, and at the other end to the ground line 22. By virtue of this arrangement, the N type island 27 receives a potential equal to that of the base of the transistor Q 1 . When a negative surge voltage reaches the output terminal OUT of the output circuit of Fig. 1, the diode D 2 absorbs a negative surge current caused thereby, and protects the base-emitter junction of the transistor Q 1 . An equivalent diode D, serving as a PN junction between the P type diffusion resistor region 28 and the N type island 27, is inversely connected between across the base-emitter junction of the NPN transistor Q 1 . Thus, when a positive surge voltage comes in through the terminal OUT, the equivalent diode D is turned on before a voltage breakdown occurs at the junction between the base and emitter of the transistor Q 1 . Accordingly, the voltage between the emitter and base of the transistor Q 1 is always placed below the forward voltage across the diode D. This indicates that the surge current can be absorbed by the equivalent diode D, thereby to protect the base-emitter junction of the transistor Q 1 against being destroyed by the positive surge voltage applied. Thus, the equivalent diode D thus connected ensures protection of the base-emitter junction of the transistor Q 1 against the positive surge voltage, whatever the impedance state of the power line. Further, use of the equivalent diode D eliminates the diode D 1 connected between the emitter of the transistor Q 1 and the power line for absorbing the positive surge current in the protector to which the present invention is not applied. Turning now to Fig. 3, there is shown another out-put circuit incorporating an electrostatic protector according to the present invention. The output circuit of Fig. 3 is characterized in having a collector-emitter path of an NPN transistor Q 3 for emitter current control additionally inserted between the resistor R and the ground line of the output circuit of Fig. 1. For simplicity, like reference symbols are used in Fig. 3 to designate portions like or equivalent to those in Fig. 1. It is evident that the output circuit of Fig. 3, like the output circuit of Fig. 1, protects the base-emitter junction of the transistor Q 1 against a surge voltage. Fig. 4 shows another input circuit used in a semiconductor integrated circuit and which incorporates an electrostatic protector according to the present invention. As shown, a resistor R is connected between the emitter of an NPN transistor Q 2 and the ground line. The base of the transistor Q 2 is connected to the input terminal IN, and the collector of the transistor Q 2 is connected to an internal circuit. A diode D 1 for absorbing a positive surge current is inserted between the base of the transistor Q 2 and the power line. In the input circuit of Fig. 4, as in the Fig. 2 circuit, the N type island region containing the P type diffusion region of resistor is connected to the base interconnection wire, and is coupled for reception with a potential equal to that at the base of the input transistor Q 2 . The input circuit of Fig. 4 protects the base-emitter junction of the transistor Q 2 against a positive surge voltage applied by the diode D 1 . In the case of a negative surge voltage being applied, an equivalent diode D, located between the emitter and base of the transistor Q 2 , operates to absorb the negative surge current caused by the negative surge voltage. The base-emitter junction of the transistor Q 2 is protected against negative surge voltage enter through the input terminal IN. Thus, the base-emitter junction of the transistor Q 2 can be protected from the negative surge voltage, irrespective of the impedance state of the ground line. Further, there can be eliminated the diode D 2 for absorbing the negative surge current, which is connected between the base of the transistor Q 2 and the ground line in the Fig. 7 circuit. The resistor R used in each of the embodiments described above can be formed by use of a solid phase diffusion process or a thermal diffusion process, following ion implantation. In other words, any P type resistor region formed in the N type island region suffices for the resistor, even if any process to form the resistor is used. Fig. 8 is a circuit diagram of another embodiment of the present invention, while Fig. 9 is a structural and schematical illustration of the electrostatic protector shown in Fig. 8. In this embodiment, a PNP bipolar transistor Q 3 is used in place of the NPN transistor Q 1 utilized in the embodiment of Fig. 1, and a diode D is equivalently formed by P type resistor Rp formed in the N type resistor island. Further, a potential equal to that at the emitter of the transistor Q 3 is applied to the N type resistor island 102. With this, a parasitic diode D is formed between a P type region 101 serving as a resistor connecting to the base of the transistor Q 3 , and the N type resistor island 102. This diode D protects the emitter-base junction of the diode Q 3 against a negative serge voltage. In this instance, a diode D 1 is used for protecting the transistor from a positive surge voltage. Figs. 10 and 11 are circuit diagrams showing further embodiments of the present invention. In Fig. 10, a base of a PNP bipolar transistor Q 4 is connected at its base to a P type resistor formed in an N type resistor island. The N type resistor island and a P type resistor Rp together form a diode D situated between the base and emitter of the transistor Q 4 . The diode D functions to protect the base-emitter junction of the transistor against a positive surge voltage. Another diode D 2 is also provided as a protecting means against the negative surge voltage. In the circuit of Fig. 11, a P type resistor Rp is used as input resistor, is coupled with a second power source. As a matter of course, another measure may be taken for the nonuse resistor Rp. An equivalent diode D 2 is used for protecting the base-emitter junction of the transistor against a surge voltage. Fig. 12 shows an output circuit having a plurality of output terminals which incorporates electrostatic protectors according to the present invention, while Fig. 13 is a schematical and structural illustration of the output circuit of Fig. 12. In Fig. 12, Q 3-1 to Q 3-n designate bipolar transistors, and D-1 to D-n represent diode components formed between the emitter and base of the bipolar transistors, respectively. Resistors R 1 to Rn are P type resistors of "n" which are formed in line in an N type resistor island 110. A potential of common bases of transistor Q 3-1 to Q 3-n supplies the resistor island 110. Therefore, the N type resistor island 110 and the P type resistors R 1 to R n provide equivalent PN junctions to serve as the diodes D-1 to D-n. As described above, in the instant embodiment, a plurality of resistors are formed in the single N type resistor island. As a result, the chip area required for forming the circuit is less than in the case where the islands are respectively used for the resistors. Fig. 14 shows an input circuit having a plurality of input terminals which incorporates electrostatic protectors according to the present invention. In this figure, R designates a resistor of a given resistance; Q 4-1 to Q 4-n , bipolar transistors; and D-1 to D-n, diodes formed between the emitter and base of the transistors. In this embodiment also, a plurality of resistors R 1 to Rn are formed in line in an N type resistor island, thereby to reduce the chip area required for forming the circuit. The PN junctions between the resistors R 1 to Rn and the N type resistor island, respectively, serve as the diodes D-1 to D-n as the diodes for protecting the base-emitter junction of transistor against an incoming surge voltage. Fig. 15 shows another input circuit with a plurality of input terminals which incorporates electrostatic protectors according to the present invention. In the figure, resistors R 1 to Rn are used as input resistor, are coupled with another voltage V. Protective diodes D-1 to D-n, respectively, are constituted by the PN junctions between the resistors R 1 to Rn and the single N type resistor island. Figs. 16 and 17 are circuit diagrams showing differential amplifiers incorporating electrostatic protectors according to the present invention. In the differential amplifier of Fig. 16, P type resistors R 1 and R 2 are seriesly connected to the base of the transistors. In the amplifier of Fig. 17, the P type resistors are used as input resistors. To stabilize the circuit operation, those resistors are coupled with another power source V. Also in the embodiments, diodes D-1 and D-2 are used for protecting the bipolar transistors against a surge voltage. It is evident that, in the embodiments described above, the input circuit may be used as the output circuit if a circuit arrangement of an external circuit of the buffer circuit according to the present invention, and the converse is also true. As can be seen from the foregoing description, the electrostatic protector according to the present invention is capable of protecting the base-emitter junction of an input or an output NPN or PNP transistor against an incoming surge voltage, irrespective of the impedance state of the power line or the ground line. A P type resistor region formed in an N type island region of a semiconductor substrate is connected between the emitter of the NPN or PNP transistor and the ground line. The N type island is electrically coupled with the base region of the transistor. A parasitic element resulting from such an arrangement is used as a diode for absorbing a surge current. The arrangement is simple in construction and is suitable for IC fabrication. Use of the parasitic element as the surge current absorbing diode does not result in an increase in the number of circuit elements required. When comparing with the circuit arrangement, for one input or output terminal, the surge current absorbing diode can be saved by at least one. To ensure protection of the transistor against a surge voltage, the surge current absorbing diode is directly connected between the base and emitter of the NPN transistor to be protected. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A buffer circuit comprising: an interface node (IN, OUT); and a bipolar transistor (Q 1 , Q 2 ) on a substrate having a collector, an emitter connected to a resistor (R, R 1 ... R n ) formed by a P-type diffusion region (28) in an N-type island region (110) in the substrate, and a base, for transferring a signal supplied to and from the interface node; wherein the junction between the P-type diffusion region and the island region forms a diode structure (D) between the emitter and base of the bipolar transistor (Q 1 , Q 2 ), and wherein a cathode of the diode structure is connected to the base and an anode of the diode structure is connected to the emitter. A buffer circuit according to claim 1, characterized in that said buffer circuit is an input buffer circuit for receiving a signal from said interface node (IN), and the base of said bipolar transistor (Q 2 ) is connected to said interface node (IN). A buffer circuit according to claim 2, characterized by further comprising a second diode (D 1 ) connected between a first power source (Vcc), and the base of said bipolar transistor (Q 2 ). A buffer circuit according to claim 2, characterized in that said input buffer circuit consists of a plurality of buffer circuits, and a plurality of resistors are formed in the N-type island region. A buffer circuit according to claim 1, characterized in that said buffer circuit is an output buffer circuit for supplying a signal to said interface node (OUT), and the emitter of said bipolar transistor (Q 1 ) is connected to said interface node (OUT). A buffer circuit according to claim 5, characterized by further comprising a second diode (D 2 ) connected between a second power source (GND) and the emitter of said bipolar transistor (Q 1 ). A buffer circuit according to claim 5, characterized in that said output buffer circuit consists of a plurality of buffer circuits, and a plurality of resistors (R1∼Rn) are formed in the N-type island region (110). A buffer circuit comprising: an interface node (IN, OUT); and a bipolar transistor (Q 3 , Q 4 ) on a substrate having a collector, a base connected to a resistor (R p , R 1 ... R n ) formed by a P-type diffusion region (101) in an N-type island region (102, 110) in the substrate, and an emitter, for transferring a signal supplied to and from the interface node; wherein the junction between the P-type diffusion region and the island region forms a diode structure (D) between the emitter and base of the bipolar transistor (Q 3 , Q 4 ), and wherein a cathode of the diode structure is connected to the emitter and an anode of the diode structure is connected to the base. A buffer circuit according to claim 8, characterized in that said buffer circuit is an input buffer circuit for receiving a signal from said interface node (IN), and the base of said bipolar transistor (Q 4 ) is connected to said interface node (IN). A buffer circuit according to claim 9, characterized by further comprising a second diode (D 2 ) connected between a second power source (GND) and the base of said bipolar transistor (Q 4 ). A buffer circuit according to claim 9, characterized in that said input buffer circuit consists of a plurality of buffer circuits, and a plurality of resistors (R1∼Rn) are formed in the N-type island region. A buffer circuit according to claim 8, characterized in that said buffer circuit is an output buffer circuit for supplying a signal to said interface node (OUT), and the emitter of said bipolar transistor (Q 3 ) is connected to said interface node (OUT). A buffer circuit according to claim 12, characterized in that said output buffer circuit consists of a plurality of buffer circuits, and a plurality of resistors (R∼Rn) are formed in the N-type island region (102). A buffer circuit according to claim 12, characterized by further comprising a second diode (D 1 ) connected between a first power source (Vcc) and the emitter of said bipolar transistor (Q 3 ).

Inventors: ITOH MASASHI, ITOH, MASASHI, ITOH, MASASHI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H03K17
IPC codes: H03K17, H01L21, H01L27