MOS type semiconductor device with a multilayer gate electrode and method for manufacturing the same

Abstract: A MOS type semiconductor device and a method for the manufacture of the same are disclosed in which a gate electrode (16) is so formed over a semiconductor substrate (11) of a first conductivity type with a gate insulating film (12) formed therebetween as to provide a three-layered structure composed of a first high melting point metal silicide layer (13) formed on the gate insu­ lating film (12), high melting point metal layer (14) formed on the first high melting point metal silicide (13) and a second high melting point metal silicide layer (15) formed on the high melting point metal layer (14). In the gate electrode (16), a length of the first high melting point silicide layer (13) defined in the same direction as that in which a channel region extends is made smaller in length than the high melting point metal layer (14).

Description: The present invention relates to a MOS type semiconductor device comprising a semiconductor substrate of a first conductivity type ,source and drain regions of a second conductivity type formed in a surface portior of the semiconductor substrate, a channel region foimed in the surface portion of the semiconductor substrate such that it is situated between the source and drain regions, a gate insulating film formed at least on the channel region, and a gate electrode comprising a first high melting point metal silicide layer formed on said gate insulating film, a high melting metal layer formed on the first high melting point metal silicide layer and a second high melting point metal silicide layer formed on the high melting point metal layer. From JP-A-61 134072 there is known a MOS FET device having a cross-sectional structure as shown in Fig. 1 that is used so as to prevent the separation of the gate electrode as set out above, the oxidation of the gate electrode per se and so on. In Fig. 1, reference numeral 31 shows a p type silicon semiconductor substrate. A gate oxide film 32 is formed on the semiconductor substrate 31. A gate electrode 36 is formed over the substrate 31 and composed of a three-layered structure of a first high melting point metal silicide 33, a high melting point metal layer 34 and a second high melting point metal silicide layer 35. N+ type diffusion layers 37 and 38 are formed as source and drain regions in the surface portion of the substrate 31. Here, the widths of the layers oi the gate electrode 36 of a three-layered structure, that is a length (hereinafter referred to as a width) defined in a direction parallel to that in which tie channel of a MOS FET extends, are exactly equal to each other or are somewhat decreased toward a top layer as shown in Fig. 1 which is caused by a side etching at an etching step. In the MOS FET having a cross-sectional structure as set out above, a gate area is determined by the high melting point metal silicide layer 33 of a largest width. Stated in another way, a valuer of a gate capacitance in the MOS FET was determined by the width of the first high melting point metal silicide layer 33 situated near the substrate 31, so that a greater gate capacitance was involved in the conventional structure. Further, the resistive value of the gate electrode is determined by that of the high melting point metal layer 34 of a lowest resistivity. Since the width of the layer 34 is made smaller than that of the first high melting point silicide layer 33 by an effect of the side etching, etc., a gate's resistive valve is increased by that extent. As a result, an improved high frequency characteristic cannot be expected from the conventional MOS FET. Another MOS type field effect transistor known from JP-A-61 063 058 having source and drain regions of a second conductivity type formed in a surface portion of a semiconductor substrate of a first conductivity type comprises a double layer gate electrode formed on an oxide film covering the surface of the substrate in a channel region located between the source and drain regions. The gate electrode has a polysilicon layer formed on the oxide film and a MoSi 2 layer formed on the polysilicon layer. The width of polysilicon layer is shorter than the width of the MoSi 2 layer and the length of the channel region formed between the high impurity regions of the source and drain regions is shorter than the width of the polysilicon layer. This results from an oblique ion implantation step wherein the MoSi2 layer is used as a mask. Therefore, the source and drain region will abut against the ends of the polysilicon layer after the oblique implantation thus reducing the length of the channel region and increasing the capacitive coupling between the channel and gate of the MOS type field effect transistor. It is the object of the present invention to provide a MOS type semiconductor device which can withstand a high temperature step or steps and reveal an improved high frequency characteristic. In order to satisfy this object there is provided a semiconductor device of the type outlined above wherein a length of the first high melting point metal silicide layer defined in the same direction as that in which the channel regions extend is made shorter in length than that of the high melting point metal layer and the length of the channel region corresponds to the length of the high melting point metal layer and is therefore longer than the length of the first high melting point metal silicide layer. According to the present invention it is possible to decrease both the gate capacitance and the gate resistive value of the MOS type semiconductor device. Further, due to the second high melting point metal silicide layer it is possible to control the width of the underlying high melting metal layer. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross-sectional view showing a conventional MOS FET; Fig. 2 is a cross-sectional view showing a MOS type semiconductor device according to a first embodiment of the present invention; Figs. 3A and 3B are cross-sectional views showing the steps of manufacturing the MOS type semiconductor device; Fig. 4 is a cross-sectional view showing a MOS type semiconductor device according to a second embodiment of the present invention; Fig. 5 is a cross-sectional view showing a MOS type semiconductor device according to a third embodiment of the present invention; Fig. 6 is a plan view, partly broken away, showing a fourth embodiment of the present invention; Fig. 7 is a cross-sectional view showing a MOS type semiconductor device according to a fifth embodiment of the present invention; and Fig. 8 is a cross-sectional view showing a MOS type semiconductor device not forming part of the present invention. The embodiments of the present invention will be explained below with reference to the accompanying drawings. Fig. 2 is a view showing a MOS FET device's structure according to one embodiment of the present invention. In Fig. 2, reference numeral 11 shows a silicon semiconductor substrate of a P type A gate oxide film 12 is formed on the silicon semiconductor substrate 11. A gate electrode 16 of a three-layered structure is formed over a location corresponding to a channel region 19 with the gate oxide film 12 situated therebetween, the three-layered structure being composed of a first high melting point silicide layer, such as an MoSi layer 13, having, for example, 1000 Å in thickness, a high melting point metal layer, such as a metal Mo layer 14, having, for example, 2000 Å in thickness, and a second high melting point metal silicide layer, such as an MoSi layer 15, having, for example, 1000 Å in thickness. N+ type diffusion layers 17 and 18 are formed as source and drain regions in the surface portion of the substrate 11 such that they are located one at each side of the channel region 19. Here, the widths of the respective layers of the gate electrode 16, that is a length defined in a direction parallel to that in which the channel region of the MOS FET extends, are so set that the width of the MoSi layer 13 is made smaller than that of the metal Mo layer 14. In the MOS FET having such a structure as set out above, the first MoSi layer 13 is located between the metal Mo layer 14 and the gate oxide film 12. Therefore, there is no risk that the metal Mo layer 14 will be separated from the rest of the structure even at a high temperature step of forming the aforementioned N+ type diffusion layers 17 and 18. Further, the length of the channel region 19, that is a channel length, is determined by the width of the gate electrode 16 formed over the semiconductor substrate 11 and corresponds to a distance between the N+ type diffusion layers 17 and 18 corresponding to the source and drain regions. The aforementioned distance is such that, if the source and drain regions are formed by, for example, an ion implantation method, it corresponds to the width of the metal Mo layer 14 which substantially serves as a mask for ion implantation. Of the gate electrode 16 of the three-layered structure, the metal Mo layer 14 needs only to have a width corresponding to a channel length in which case the first MoSi layer 13 can be made smaller in width than the layer 14. Since, as set out above, the value of a gate capacitance in the MOS FET is determined in accordance with the width of the first MoSi layer 13, that is the lowest layer of the gate electrode 16, the embodiment of the MOS FET can adequately reduce the gate capacitance because the width of the layer 13 is made smaller. Further, the resistive value of the gate electrode is determined by the resistive value of the lowest-resistivity metal Mo layer 14. The MOS FET of the present embodiment can reduce a gate's resistive value since the layer 14 can be made larger. This leads to a reduced gate capacitance and an excellent high frequency characteristic. The present invention will be explained below in conjunction with the step for manufacturing a MOS FET of the aforementioned structure. After a gate oxide film 12 has been formed by an oxidation method on the surface of a substrate 11, a first MoSi layer 13, metal Mo layer 14 and second MoSi layer 15 are sequentially deposited by a vapor deposition method over the substrate 11 as shown in Fig. 3A. Then a photoresist film 19 is deposited over the whole surface of the resultant structure, followed by an exposure step and developing step. In this way, the photoresist film 19 is left on that surface corresponding to a gate area. As shown in Fig. 3B, the three-layered structure, that is the first MoSi layer 13, metal Mo layer 14 and second MoSi layer 15, is etched, by a CDE (chemical dry etching), with the photo-resist film 19 used as a mask. At the time of etching, a CF 4 gas and O 2 gas are flowed at a flow rate of 100 (SCCM) and 150 (SCCM), respectively, under a high frequency power of 280 to 350 (W). A gate electrode 16 of a configuration as shown in Fig. 3B is formed over the substrate by the aforementioned etching method and condition. It is to be noted that, at the time of etching, a gate electrode of a better configuration was able to be obtained in a gas stream of CF 4 and O 2 at SCCM of below 300 and below 250, respectively. A better result was also able to be obtained under a high frequency power of over 200 W. Then the photoresist film 19 as used at the etching step is separated, though not shown, from the rest of the structure and an N type impurity, such as arsenic (As), is ion implanted in the surface portion of the substrate 11 with the gate electrode 16 used as a mask. The N+ type diffusion layers 17 and 18 are formed in the surface portion of the substrate through an activation process at a heating step to provide source and drain regions with a channel region 19 defined therebetween as shown in Fig. 2. When a MOS FET was manufacture, by the aforementioned method, with a channel length designed to be 2 µm, the first MoSi layer 13, metal Mo layer 14 and second MoSi layer 15 were 1.82 µm, 2.21 µm and 1.47 µm in width, respectively, in which case these layers was set to be 100 nm, 200 nm and 100 nm in thickness, respectively. When, on the other hand, a MOS FET was manufactured by another method with a channel length designed to be 2 µm, a first high melting point metal silicide layer, high melting point metal layer and second high melting point metal silicide layer were 2.2 µm, 2.02 µm and 1.85 µm, respectively. In comparison with the MOS FET manufactured in the conventional method (another method), the MOS FET revealed a decrease of a gate capacitance by 17.3 % and decrease of a gate resistive valve. Further, in comparison with their output characteristic in a high frequency range, the output power and drain efficiency were improved to 1.3 times the conventional one and 1.1 times the conventional one. Since in the MOS FET as shown in Fig. 2, the second MoSi layer 15 is present over the substrate, it is possible to control the width of the underlying metal Mo layer 14 by observing the shape of the second MoSi layer 15 when the gate electrode is patterned by etching. Fig. 4 shows a MOS FET according to a second embodiment of the present embodiment. In this embodiment, a gate electrode 16 is so formed over a substrate 11 as to have a three-layered structure composed of an MoSi layer 13, metal Mo layer 14 and MoSi layer 15. An N - type diffusion layer 20 of a low concentration is formed between a channel region 19 and an N+ type diffusion layer 18 serving as a drain region, that is, the drain region is composed of the N+ type diffusion layer of a high concentration and N - type diffusion layer of a low concentration to provide an LDD transistor. Fig. 5 shows a MOS FET according to a third embodiment of the present invention. This embodiment is of a dual gate type having two gates. In the dual gate type MOS FET, the respective gate electrode 16 is so formed over a substrate as to have a three-layered structure composed of an MoSi layer 13, metal Mo layer 14 and MoSi layer 15 in which case the MoSi layer 13 has a smaller width than the metal Mo layer 14. In Fig. 5, reference numeral 21 shows an N+ type diffusion layer. Fig. 6 shows a MOS FET according to a fourth embodiment of the present invention. A gate electrode 16 has such a three-layered structure as shown in Fig. 2. As will be appreciated from the above, the gate electrode 16 is of an interdigital type having leg sections. Source and drain regions S and D are so formed as to be alternately inserted between the leg portions of the interdigital type gate electrode 16 as shown in Fig. 6. Fig. 7 shows a MOS FET according to a fifth embodiment of the present invention. This embodiment is different from the first embodiment shown in Fig. 2 except that a gate electrode 16 has a second MoSi layer (top layer) and underlying metal Mo layer 14 of the same width. This structure can be achieved by the aforementioned method for forming the first MoSi layer 13 and second Mosi layer 15 in a manner to be made different in composition from each other. Fig. 8 shows a MOS FET not forming part of the present invention. This example is similar to the embodiment shown in Fig. 2 except that a second MoSi layer (top layer) 15 of the second embodiment is not formed over a substrate 11. This gate structure can achieve the same advantage as that of the first embodiment of Fig. 2. Although, in the aforement oned embodiments, the high melting metal silicide layer and high melting metal layer have been explained as being an MoSi layer and metal Mo layer, use can be made, as the high melting metal silicide layer, of titanium silicide (Tisi) layer, tungsten silicide (WSi) layer, etc., and use can be made, as a high melting point metal layer, of titanium (Ti) layer, tungsten (W) layer, etc. As set out above, the present invention provides a MOS type semiconductor device which can withstand a high temperature step or steps and reveal an excellent high frequency characteristic and a method for manufacturing the same. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: MOS type semiconductor device comprising: a) a semiconductor substrate (11) of a first conductivity type (P), b) source and drain regions (17, 18) cf a second conductivity type (N+) formed in a surface portion of said semiconductor substrate (11), c) a channel region (19) formed in said surface portion of said semiconductor substrate (11) such that it is situated between the source and drain regions (17, 18), d) a gate insulating film (12) formed at least on said channel region (19), and e) a gate electrode (16) comprising a first high melting point metal silicide layer (13) formed on said gate insulating film (12), a high melting metal layer (14) formed on said first high melting point metal silicide layer (13) and a second high melting point metal silicide layer (15) formed or said high melting point metal layer (14), characterized in that f) a length of said first high melting point metal silicide layer (13) defined in said same direction as that in which said channel region 19) extends is made shorter in length than that of said high melting point metal layer (14), and g) said length of said channel region (19) corresponds to said length of said high melting point metal layer (14) and is therefore longer than said length of said first high melting point metal silicide layer (13). MOS type semiconductor device according to claim 1, characterized in that said first and second high melting point silicide layers (13, 15) are one selected from a group consisting of a molybdenum silicide layer (MoSi), a titanium silicide layer (TiSi) and tungsten silicide layer (WSi) and said high melting point metal layer (14) is formed of a material selected from a group consisting of molybdenum (Mo), titanium (Ti) and tungsten (W).

Inventors: MARAKAMI KOUJI, MATSUNAGA TAIRA, MARAKAMI, KOUJI, MATSUNAGA, TAIRA, MARAKAMI, KOUJI, C/O INTELLECTUAL PROPERTY DIV., MATSUNAGA, TAIRA, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, H01L23, H01L21