Charge pump having pull-up circuit operating with two clock pulse sequences

Abstract: A charge pump comprises a charge-up circuit (11) connected to a voltage source, and a clock generator (20). A pull-up circuit (12) is formed by an enhancement mode MOSFET (16) and a time constant circuit. The MOSFET has its drain coupled to the charge-up circuit (11) and its source connected to the output terminal of the charge pump. The clock generator (20) produces first and second clock pulse sequences, with the duration of the first clock pulse sequence being greater than the pulse duration of the second clock pulse sequence. The time constant circuit has two capacitors (18,19) and a resistor (17) connected therebetween to respond to the first and second clock pulse sequences by successively applying voltages to the drain and gate of the MOSFET (16). The charge-up circuit (11) is formed by a depletion mode or an enhancement mode MOSFET (13) which is responsive to one or more clock pulse sequences with pulses preceding those of the first and second clock sequences.

Description: BACKGROUND OF THE INVENTION The present invention relates to semiconductor circuits, and more specifically to a charge pump which is used in integrated circuits. As shown in Fig. 1, a prior art charge pump comprises a charge-up circuit 1 and a pull-up circuit 2. Charge-up circuit 1 is formed by an N-channel enhancement mode MOSFET (field effect transistor) 1 whose drain and gate are coupled to a voltage supply 4 at voltage V CC and whose source is coupled to the drain and gate of an N-channel enhancement mode MOSFET 5 of pull-up circuit 2 and thence to a clock source  through a capacitor 6. The source of MOSFET 5 is coupled to an output terminal 7 which is in turn connected to a suitable utilization circuit. When clock sequence  switches to low level, the drain of MOSFET 5 is driven by MOSFET 3 and its potential increases as indicated by a dotted line in Fig. 2 to a level V CC - V Te (where V Te is the threshold of MOSFET 3). On reaching this level, MOSFET 3 Is turned off. When clock sequence goes high, the voltage at the drain of MOSFET 5 rises sharply to a level V CC - V Te + V  (where V  is the voltage of the clock sequence) by the action of capacitor 6. This voltage is applied through MOSFET 5 to output terminal 7, producing an output voltage (V CC - V Te ) + (V  - V Te ) which it indicated by a solid line curve in Fig. 2. To obtain a higher output voltage, pull-up circuits 2- 1, 2-2 and 2-3 are cascaded as shown in Fig. 3 such that the second stage is supplied with clock sequence of opposite phase to those of clock sequences supplied to the odd-numbered stages. The voltage at the drain of MOSFET 5-2 is driven to a level equal to (V CC - V Te ) + (V - V Te ) when the opposite phase clock is at low level. When the opposite-phase clock goes high, the drain of MOSFET 5-2 Is driven to a level equal to (V CC - V Te ) + (V - V Te ) + V  which is applied through MOSFET 5-2 to the drain of MOSFET 5-3, which, as a result rises to a level (V CC - V Te ) + (V - V Te ) + (V - V Te ). The output voltage of this multi-stage circuit Is equal to (V CC - V Te ) + N(V  - V Te ), where N represents the number of cascaded pull-up circuits 2. Usually V  is set equal to V CC , and the output voltage is 2V CC - 2V Te . Since the threshold voltage V Te is of a substantial value in comparison with V CC the output voltage is too low for some applications. If source voltage V CC is equal to or lower than the threshold voltage V Te , the charge-up circuit becomes Inoperative, and if V  ≤ V Te the pull-up circuit becomes inoperative. In either case, the charge pump is inoperative. In addition, a large number of pull-up circuits would be required. For example, if V CC - V  - 1.5 volts, V Te = 1.0 volt, twenty-nine pull-up circuits are required to obtain an output voltage of 15 volts. WO-84/01659 discloses a charge pump wherein a first capacitive node controls a transistor to pass a charging voltage from an input line to charge a second capacitive node which is coupled to the first capacitive node by a transistor. Two out-of-phase clock pulses coupled to respective capacitors provide a charge pumping effect to raise the potential on the first capacitive node to a level such that a transistor coupled thereto passes the voltage on the input line to the output line without threshold losses. WO-84/01659 does not refer to the problem of how to obtain a charge pump for generating a high output voltage without requiring a reduced number of pull-up circuits. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a charge pump capable of generating a high output voltages which does not require a large number of pull-up circuit. The invention is defined in claim 1. Further embodiments are defined in the sub-claims. In particular, the invention also provides a charge pump comprising at least one further pull-up circuit, as defined in claim 6. B RIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a prior art charge pump; Fig. 2 is a waveform diagram associated with the prior art charge pump; fig. 3 is a circuit diagram of a prior art multi-stage charge pump; Fig. 4 is a circuit diagram of a charge pump according to an embodiment of the present invention; Fig. 5 is a waveform diagram associated with the embodiment of this invention; Fig. 6 is a circuit diagram of a multi-stage charge pump of this invention; and Fig. 7 is a circuit diagram of a modification of this invention DETAILED DESCRIPTION Referring now to Fig. 4, there is shown a charge pump according to an embodiment of the present invention. The charge pump shown at 10 comprises a charge-up circuit 11 and a pull-up circuit 12. Charge-up circuit 11 comprises an N-channel enhancement mode MOSFET 13 having a gate G 1 coupled through a resistor 14 to a clock source 20 to receive a fist clock pulse sequence  1 and through a capacitor 15 to receive a second clock sequence  2 . MOSFET 13 has its drain D 1 connected to a voltage supply 21 to receive source voltage V CC and its source S 1 coupled to the drain D 2 of an N-channel enhancement mode MOSFET 16 of charge-up circuit 12. MOSFET 16 has its gate G 2 and drain D 2 coupled together by a resistor 17, with the drain D 2 being further coupled through a capacitor 18 to clock source 20 to receive a third clock sequence  3 and the Gate G 2 being further coupled through a capacitor 19 to the clock source to receive a fourth clock sequence  4 . Resistor 14 and capacitor 15 form a series circuit across terminals  1 and  2 of clock source 20 with a time constant value R 1 ·C 1 (where R 1 and C 1 are the resistance and capacitance values of resistor 14 and capacitor 15, respectively). Likewise, resistor 17 and capacitor 19 present a series circuit between drain D 2 of MOSFET 16 and clock terminal  4 with a time constant value C 2 ·R 2 (where C 2 is the capacitance of capacitor 19 and R 2 is the resistance of resistor 17). The source S 2 of MOSFET 16 is coupled to the output terminal 22 of the charge pump 10 to which a utilization circuit is connected. The first to fourth clock sequences have the waveforms as shown in Fig. 5. The first and third clock sequences  1 and  3 are of opposite polarity of the same clock period which is twice the period of clock sequences  2 and  4 so that these clock sequences produce a unique combination of four different voltage levels respectively for periods T 1 , T 2 , T 3 and T 4 . Specifically, during period T 1 , clock sequence is at high voltage V  and all other clock sequences are at zero voltage. During period T 2 , clock sequences  1 and  2 are at voltage V  and other sequences are at zero voltage. During period T 3 , only clock sequence  3 is at high level, and during the last period T 4 ,  3 and  4 are at high level. Note that the time constant value C 1 ·R 1 is much smaller than period T 1 or T 2 and the time constant value C 2 ·R 2 is much smaller than period T 3 or T 4 . Assume that the voltage V  is equal to source voltage V CC . During period T 1 , a voltage difference V  develops across terminals  1 and  2 and capacitor 15 is charged through resistor 14, generating a potential which rises exponentially at the gate C 1 of MOSFET 13, following a curve V  (1 - e -t /C 1 . R 1 ) as indicated by a dotted line 30 in Fig. 5. Since T 1 is much greater than time constant C 1 ·R 1 , the voltage at gate C 1 will eventually reach V  (= V CC ) within period T 1 . During period T 2 , clock terminal  2 is driven to the same potential as at terminal  1 , This voltage adds up to the voltage developed across capacitor 15, presenting a voltage 2V  to gate C 1 . This voltage decays exponentially following a curve V  (1 + e -t /C 1 ·R 1 ) to the V  level within period T 2 as illustrated. At the instant the voltage at gate C 1 rises to the level 2V CC , the voltage at the drain D 2 of MOSFET 16 is driven to V CC as shown at 31 a if V CC is equal to or lower than 2V  - V Te (where V Te is the threshold voltage of enhancement mode MOSFET 13), or driven to 2V  , - V Te if V CC is higher than 2V  - V Te . During period T 3 in which the third clock sequence  3 is the only one that is driven to high level, the voltage V  of this clock sequence is supplied through capacitor 18 to the drain D 2 of MOSFET 16, so that the voltage at drain D 2 sharply rises to a level 2V  (= 2V CC ) as shown at 31b in Fig. 5, and capacitor 19 is charged through resistor 17. Since the time constant C 2 ·R 2 is smaller than T 3 , the voltage at the gate G 2 of MOSFET 16 rises exponentially as shown at 32a to the same level as at the drain D 2 of MOSFET 16 within period T 3 . During the successive periods T 1 through T 3 , the voltage at the output terminal 22 increases exponentially in a stepwise manner. Specifically, it exponentially increases to a level V  - 2V Te during T 1 , rises to a level V CC - V Te during T 2 , and jumps to a level V CC + V  - V Te during T 3 . During the next period T 4 In which the third and fourth clock sequences are at high level, the voltage at the gate G 2 of MOSFET 16 rapidly rises as shown at 32b to a level which is three times as high as the source voltage V CC . This voltage level is equal to the potential at the drain D 2 plus 2V  . Since the time constant C 2 ·R 2 is much smaller than period T 4 , the voltage at gate G 2 decays exponentially to the same voltage level as at the drain D 2 during period T 4 . During period T 4 , the voltage at the output terminal 22 further increases to the level 2V CC . When the potential at gate G 2 increased to 3V CC , the voltage V OUT at the output terminal 22 increases from the level (V CC + V  - V Te ) to 2V CC (= voltage at drain D 2 + V  ) if V  is equal to or higher than V Te , or increases to a level equal to the voltage at drain D 2 + 2V  - V To if V  is lower than V Te . It is seen that the voltage obtained by the use of a single pull-up circuit of this invention is equal to V  if V  ≥ V Te or 2V  - V Te if V  < V Te . It is seen from the foregoing that as long as a relation V  > V Te /2 holds both charge-up and pull-up circuits operate satisfactorily. Since the voltage V  of the clock sequences for MOS integrated circuitry is usually equal to the source voltage V CC , the charge pump of this invention can operate satisfactorily even when the source voltage is at very low level. For example, if V Te is 1.0 volt the charge pump will operate at a source voltage of 0.5 volts. A higher output voltage can be obtained by cascading pull-up circuits 12.1, 12-2 and 12.3 as shown in Fig. 6 such that the phases of clock sequences supplied to the even-numbered stage 12-2 are opposite to the phases of clock sequences supplied to the odd. numbered pull-up circuits 12.1, 12-3. Since the voltage at the drain D 2 of each pull-up circuit is either V  or 2V  - V Te , the output voltage V OUT is equal to the voltage at drain D 2 plus NV  if V  is equal to or higher than V Te or equal to the voltage at drain D 2 plus N(2V  - V Te ) if V  is lower than V Te (where N is the number of cascaded pull-up circuits). Therefore, the number of pull-up circuits necessary for a given application can be reduced In comparison with the prior art charge pump. For example, if V CC = V  = 1.5 volts and V Te = 1.0 volt nine pull-up circuits will be sufficient to obtain an output voltage of 15 volts. To reduce the amount of space for implementing the charge pump, resistors 14 and 17 are preferably replaced with N-channel depletion mode MOSFETs 40 and 41, respectively, as shown in Fig. 7. Each of these MOSFETs has Its gate and drain electrodes coupled together to form an equivalent resistance element. Alternativeiy the gate and source electrodes, may be coupled together to form a resistor.

Claims: A charge pump comprising: a charge-up circuit (11) connected to a voltage source (21); clock generator means (20) for generating third and fourth clock pulse sequences (Φ 3 , Φ 4 ) respectively at third and fourth output terminals of the clock generator means (20); a pull-up circuit (12; 12-1) including a first field-effect transistor (16) having a drain-source path connected between said charge-up circuit (11) and an output terminal (22) of the charge pump, and a gate electrode, and a first time constant circuit having first (18) and second (19) capacitive elements and a resistive element (17; 41) connected therebetween, said first time constant circuit being connected across said third and fourth output terminals of said clock generator means (20) for successively applying voltages to one end of the drain-source path and to the gate electrode of said transistor (16) in response to said third and fourth clock pulse sequences (Φ 3 , Φ 4 ), characterized in that the clock generator means (20) further generates first and second clock pulse sequences (Φ 1 , Φ 2 ) respectively at first and second output terminals of said clock generator means (20) and successively applies said first and second clock pulse sequences (Φ 1 , Φ 2 ) to said charge-up circuit (11), the first and third clock sequences (Φ 1 , Φ 3 ) are of opposite polarity and the second clock sequence (Φ 2 ) is generated after the beginning of the first pulse clock sequence (Φ 1 ) and before the beginning of the third clock sequence (Φ 3 ) and the fourth clock seqence (Φ 4 ) is generated after the beginning of the third clock sequence (Φ 3 ), said charge-up circuit (11) comprises a second field-effect transistor (13) having its source-drain path connected between said voltage source (21), and said pull-up circuit (12, 12-1) and a second time constant circuit having a capadtive element (15) and a resistive element (14; 40) connected across said first and second output terminals of said clock generator means (20) for successively applying voltages to one end of the drain-source path and to the gate electrode of said second field-effect transistor in response to said first and second clock pulse sequences (Φ 1 , Φ 2 ). A charge pump according to claim 1, characterized in that said first (16) and second (13) field-effect transistors are enhancement mode field-effect transistors. A charge pump as claimed in one of claims 1 or 2, characterized in that said first clock pulse sequence (Φ 1 ) has a pulse duration greater than a pulse duration of said second clock pulse sequence (Φ 2 ) and said third clock pulse sequence (Φ 3 ) has a pulse duration greater than a pulse duration of said fourth clock pulse sequence (Φ 4 ). A charge pump as claimed in one of the claims 1 to 3, characterized in that the resistive element of each of said first and second time constant circuits comprises a third field-effect transistor (40, 41) having a gate electrode and a drain-source path connected at one end to the gate electrode of the third field-effect transistor (40, 41). A charge pump according to claim 4, characterized in that said third field-effect transistor is a depletion-mode field-effect transistor. A charge pump as claimed in one of the claims 1 to 5, characterized in that it comprises at least one further pull-up circuit (12-2, 12-3), the field-effect transistor (16) of each further pull-up circuit (12-2, 12-3) having its drain-source path connected between the source electrode of the field-effect transistor (16) of the pull-up circuit (12-1) and said output terminal (22) of the charge pump, and the second time constant circuit of each successively disposed further pull-up circuit (12-2, 12-3) being connected across that pair of said first and second or third and fourth output terminals of said dock generator means (20) which is not connected with the second time constant circuit of the previously disposed pull-up circuit (12-1, 12-2).

Inventors: KOBATAKE HIROYUKI, KOBATAKE, HIROYUKI, KOBATAKE, HIROYUKI, C/O NEC CORPARATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: H03K17
IPC codes: H01L27, H01L21, H03K17, H03K5, H03K19, H02M3