Source-coupled FET logic type output circuit

Abstract: In a source-coupled FET logic type output circuit, the drain electrodes of first and second FETs (Q1, Q2) are coupled through a level shift element (LS1) to a high-voltage power source (V DD ) and load elements (LD1, LD2), the gate electrodes of the FETs are respec­ tively connected to first and second input terminals (IN, IN ), and the source electrodes of these transistors which are coupled together are coupled to a low-voltage power source (V SS ) by first constant-current power source (CC1). Furthermore, between the high-voltage power source (V DD ) and the low-voltage power source (V SS ) are connected, third FET (Q3) with its gate electrode coupled to the drain electrode of first FET (Q1), level shift elements (LS2, LS3), second constant- current power source (CC2), fourth FET (Q4) with its gate electrode coupled to the drain electrode of second FET (Q2), level shift element (LS4), third constant- current power source (CC3), fifth FET (Q5) with its gate electrode coupled between fourth FET (Q4) and level shift element (LS4), sixth FET (Q6) with its gate electrode coupled between third level shift element (LS3) and second constant-current power source (CC2), and fifth level shift element (LS5). An output signal with the potential corresponding to that of a com­ plementary signal inputted to the input terminal ( IN , IN) to cause the third through sixth FETs (Q3, Q4, Q5, Q6) to perform a push-pull function is obtained at an output terminal (OUT) expending from a connection point between the fifth and sixth FETs (Q5, Q6).

Description: The present invention relates to an output circuit comprising a first load element having one end coupled to a high-voltage source, a first field-effect transistor having one end of its current path coupled to the other end of said first load element and the other end of the current path connected to a corresponding end of the current path of a second field-effect transistor and to one end of a first constant-current power source, the other end of which is connected to a low-voltage power source, a third field-effect transistor having a current path connected, at one end, to said high-voltage power source, and having its control terminal coupled to the one end of the current path of said first field-effect transistor, a first level shift element having one end coupled to the other end of the current path of said third field-effect transistor, a second load element having one end coupled to said high-voltage power source and the other end connected to the one end of the current path of said second field-effect transistor, a second constant-current power source connected between the other end of said first level shift element and said low-voltage power source, a fourth field-effect transistor having a current path connected, at one end, to said high-voltage power source and a control terminal coupled to the one end of the current path of said second field-effect transistor, a second level shift element having one end coupled to the other end of the current path of said fourth field-effect transistor, a third level shift element coupled between said high-voltage power source and the one end of said first and second load elements, and a third constant-current power source connected between the other end of said second level shifting element and said low-voltage power source. Such an output circuit is described in PATENTS ABSTRACTS OF JAPAN vol. 13, no. 34(E-708)[3382], August 25, 1989; & JP-A-63 232 711. A conventional output circuit, using source-coupled FET logic (hereinafter called SCFL), is shown in Fig. 1. In the same Figure, one electrode of a level shift element LS1 is coupled to a high-voltage power source V DD , with another electrode connected to a one electrode of load element LD and the drain electrode an FET Q1, respectively. Further, the other electrode of the load element LD is coupled to the drain electrode of another FET Q2, and also to the gate electrode of second another FET Q3 of which drain electrode is connected to the high-voltage power source V DD . The FETs Q1 and Q2 have their gate electrodes applied as respective input terminals IN and IN, and their respective source electrodes connected together and also connected to a low-voltage power source V SS through a constant current power source CC1. The source electrode of the FET Q3 is connected to the power source V SS by a constant current source CC2. The source electrode of the FET Q3 is connected to the low-voltage power source V SS by a resistor R. The source electrode of the FET Q3 is used as an output terminal, and is connected to the low-voltage power source V SS by a capacitive load C L . In the SCFL type output circuit arranged such as the above, the input terminal IN and IN commonly have a complementary signal applied thereto, wherein if the input terminal IN and In are set to a low level and a high level, respectively, the FET Q1 is turned off and the FET Q2 is turned on. The potential difference V GS between the gate and source electrodes of the FET Q3 therefore decreases, whereby the FET Q3 subsequently is turned off. This results in that the charge thus far stored in the capacitive load C L is discharged via the resistor R, and thereby the output terminal OUT becomes to be of a low level. Now, application of an SCFL type output circuit configured such as the above for a high-speed integrated circuit involves the prerequisite that charging and discharging of the capacitor C L must be implemented quickly. However, generally, the capacitor C L is much larger than the gate capacity of each FET incorporated in the SCFL type output circuit. This means that much time is required to discharge the capacitive load C L . Therefore, to meet the above-noted prerequisite, it is necessary to lessen the time of discharging by decreasing the resistance of the resistor R. But the past attempts thus far undertaken to reduce the resistance of resistor R were hindered by the problem that the power consumption went up in response to the flow of an unnecessarily large current for charging the capacitive load C L . An output circuit using bipolar transistors is described in EP-A-0 309 063. An object of the present invention is to provide a source-coupled FET logic type output circuit of a high-speed design with low power consumption realised. According to the invention, the output circuit initially defined is characterised by: a fifth field-effect transistor having a current path connected, at one end, to said high-voltage power source, and, at the other end to a first output terminal, and a control terminal connected to the other end of said second level shift element; a sixth field-effect transistor having a current path connected, at one end, to the other end of the current path of said fifth field-effect transistor, the other end of the current path of said sixth field-effect transistor coupled to said low-voltage power source, and its control terminal connected to the other end of said first level shift element; and a fourth level shift element coupled between the other end of the current path of said sixth field-effect transistor and said low-voltage power source. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit configuration diagram showing how the SCFL type output circuit of the prior art is fabricated; Fig. 2 is a circuit configuration diagram showing how the source-coupled FET logic type output circuit in the first embodiment of the present invention is arranged; Fig. 3 is a circuit configuration diagram showing the SCFL type output circuit in the second embodiment of the present invention; Fig. 4 is a circuit configuration diagram showing the SCFL type output circuit in the third embodiment of the present invention; and Fig. 5 is a circuit configuration diagram showing the SCFL type output circuit in the fourth embodiment of the present invention. Now some embodiments of the present invention. As regards the embodiments to be described hereunder, the parts identical with those used in the SCFL type output circuit of the prior art have their description omitted, with the same reference numerals provided for such parts, which coincides with the reference numerals originally given to those in the output circuit. Presented in Fig. 2 is a circuit configuration diagram of the SCFL type output circuit in the first embodiment of the present invention. With reference to the same figure, one electrode of a level shift element LS1 is connected a high-voltage power source V DD , with the other electrode coupled to load elements LD1 and LD2. The drain electrodes respectively of the field effect transistors (FET) Q1 and Q2 are coupled to the load elements LD1 and LD2. Besides, the gate electrodes of FETS Q3 and Q4 are connected to the drain electrode of the FETs Q1 and Q2. It is noted that the drain electrodes respectively of the FETs are connected to the high-voltage power source V DD . The FETs Q1 and Q2 have their gate electrodes used as input terminals IN and IN , with their source electrodes coupled together and to a low-voltage power source V SS by a constant-current power source CC1. Further, the source electrode of the FET Q3 is grounded not only through respective level shift elements LS2 and LS3 which are serially coupled to each other, but also via a constant-current power source CC2. Likewise with the FET Q3, the source electrode of the FET Q4 is connected to the low-voltage power source V SS by a level shift element LS4 and a constant-current power source CC3. In addition, to the connecting point of the level shift element LS4, the gate electrode of an FET Q5 which has its drain electrode coupled to the high-voltage power source V DD , is connected. Similarly to the above, to the connecting point of the level shift element LS3 and the constant-current power source CC2, the gate electrode of an FET Q6 which has its drain electrode connected to the source electrode of the FET Q5. And the source electrode of the FET Q6 is connected to the low-voltage power source V SS by a level shift element LS5. Further, the connecting point of the FETs Q5 and Q6 is connected to not only the output terminal OUT, but also to one end of the capacitive load C L connected, at the other end, to the low-voltage power source V SS . It is noted that the level shift element LS3 is essential to secure a voltage V GS5 between the gate electrode and source electrode of the FET Q5, and a voltage V DG6 between the drain electrode and source electrode of FET Q6. In the following operation of the output circuit configured as in the foregoing is described. Again with reference to Fig. 2, the input terminal IN and IN are fed with complementary signals. In this case, the potential transitions respectively to a high level with the input terminal IN and a low level with the input terminal IN coincide with turning on the FET Q1 and turning off the FET Q2. As a consequence, the gate electrode of the FET Q3 is rendered to be of a low level, with the gate electrode of the FET Q4 getting into the state of a high level. Thus, the gate electrode of the FET Q5 which is controlled by the FET Q4 via the level shift element LS4 results in getting into the state of a high level. In the meanwhile, the potential level of the gate electrode of the FET Q6 which is controlled by the FET Q3 through the level shift elements LS2 and LS3 goes down low. This entails that the FET Q5 turns on and the FET Q6 is switched off, with a current starting to flow through the FET Q5. As a result, the capacitive load C L is charged with the current from the FET Q5, with a high-level output signal emerging simultaneously at the output terminal OUT. On the other hand, the potential transitions to a low level with the input terminal IN and a high level with the input terminal IN contrary to the above, entails turning off the FET Q1 and turning on the FET Q2, whereby the gate electrode of the FET Q3 goes into the state of a high level and the gate electrode of the FET Q4 has its potential decreased to a low level. The result is that the gate electrode of the FET Q5 gets into the state of a low level, with the gate electrode of the FET Q6 becoming to be of a high level; namely, the FET Q5 is switched off and the FET Q6 on, whereby the charge held in the capacitive load C L is let out via the FET Q6 and the level shift element LS5, with a low level output signal emerging at the output terminal OUT as a result. It is noted that, in the output circuit configured such as the above the level shift element LS4 provided therein lessens a voltage V GS6 between the gate electrode and source electrode of the FET Q6 lower than the forward directional voltage of a Schottky diode, thereby to prevent the current from the gate electrode from flowing into the Schottky diode. Additionally, with the level shift elements LS2 and LS3, their quantities are variable with output level requirements. In the above-remarked output circuit, the circuit configuration is such that charging the capacitive load C L coincides with working the FET Q5 as an active element while discharging the capacitive load concurs with working the transistor Q6 as an active element. Therefore, where the current flowing in the FET Q5 is equal to the current of the FET Q6, the times required respectively for charging and discharging are equalized, whereby it is rendered feasible to output a high-speed signal without flowing a surplus current in each of these transistors, thus resulting in being.practicable to fabricate the SCFL output circuit in a high-speed, low power consumption design. Fig. 3 is a circuit configuration diagram showing the second embodiment of the present invention. The second embodiment is realized with a SCFL output circuitry configured such as in Fig. 2. As regards the arrangement and operation of those other than the circuit elements referred to herein the second embodiment is identical with first embodiment, the description of such circuit elements as the above is omitted, accordingly. Namely, in the second embodiment, resistors R1, R2, and R3 are used for the level shift element LS1, and the load elements LD1 and LD2 shown in Fig. 2. Further for the level shift elements LS2, LS3, and LS4, Schottky diodes D1, D2, and D3 are installed. And also for a level shift element LS5, a serial circuit comprised of Schottky diodes D4 and D5 is provided. Moreover, the constant-current power sources CC1, CC2, and CC3 may comprise each of serial circuits made up of an FET Q7 and a resistor R4, and FET Q8 and a resistor R5, and an FET Q9 and a resistor R6. It is noted that V b in Fig. 2 stands for a given external bias power source. Fig. 4 is a circuit configuration diagram of the output circuit in the third embodiment which gives an instance wherein said Schottky diodes D4 and D5 incorporated in the circuit of such a configuration as specified in Fig. 3 are replaced with resistors R7 and R8. As regards the arrangement and operation of other circuit components, the third embodiment is identical with the above-mentioned first and second embodiments. Therefore, such circuit components are not described herein. Illustrated in Fig. 5 is a circuit configuration diagram showing the fourth embodiment wherein there is provided such an output circuit which enables to generate a complementary output signal, and of which configuration is an alteration from the second embodiment in Fig. 2. With regard to the fourth embodiment, only those parts which are different from the counterparts in the second embodiment, are described herein. No description is provided for other parts, for they are identical with those used in the second embodiment in Fig. 2. Precisely with the fourth embodiment in respect of circuit configuration, between the level shift element LS4 and the constant-current power source CC3, a level shift element LS6 is inserted and electrically connected therein as shown in Fig. 5. The gate electrode of the FET Q5 is coupled to the connecting point of the level shift elements LS4 and LS6. Further, to the connecting point of the level shift elements LS2 and LS3, the gate electrode of an FET Q10 of which drain electrode is connected to the high-voltage power source V DD , is coupled. Besides, to the connecting point of the level shift element LS6 and the constant-current power source CC3, the gate electrode of an FET Q11 whose drain electrode is connected to the source electrode of an FET Q10, is coupled. The source electrode of an FET Q11 is connected to the low-potential power supply via a level shift element LS8. The output terminal OUT due to be coupled between the FETs Q5 and Q6 is connected to the low-potential power supply through the capacitive load C L . Similarly, an output OUT to be coupled between FETs Q10 and Q11 is grounded via a capacitive load C L 2. Next, how the output circuit configured such as the above runs is described hereunder. For example, the potential transitions respectively to a high level with the input terminal IN and a low level with the input terminal IN coincide with turning on the FET Q1 and turning off the FET Q2. This results in bringing the potential at the gate electrode of the FET Q3 into the state of a low level, with the gate electrode of the FET Q4 getting into the state of a high level, whereby the gate electrode of the FET Q5 controlled by the FET Q4 via the level shift element LS4 has its potential raised to a high level. Further, both the gate electrode of an FET Q10 and the gate electrode of FET Q6 controlled by the FET Q3, respectively through the level shift elements LS2 and LS3 have their potential decreased to a low level. This results in turning on FETs Q5 and Q11, with the FETs Q10 and Q6 turning off, whereby a current flows both the FETs Q5 and Q11. Thus, a capacitive load C L 1 is charged with the current from FET Q5. As a consequence, there appears an output signal of a high level potential at the output terminal OUT. Meanwhile, the FET Q6 turns off and the FET Q11 at this stage, whereby the charge held in the capacitive load C L 2 is let out via the FET Q11 and a level shift element LS8, with an output signal of a low level potential emerging at the output terminal OUT as a results. Where the input terminal IN has its potential decreased to a low level, with the input terminal IN getting into the state of a high level, contrary to the above, the output circuit concerned counter-runs, with a low level potential output signal appearing at the output terminal OUT and a high-level potential output signal emerging at the output terminal OUT as a result. In such a circuit configuration, inputting a complementary signal to the input terminals IN and IN results in generating a complementary signal with the potential corresponding to the input complementary signal. Therefore, the fourth embodiment can be applied not only as an output circuit but also as an internal circuit in IC (integrated circuit) devices. As in the foregoing, according to the present invention, there can be provided a source-coupled FET logic type output circuit of a high-speed design with low power consumption realized. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: An output circuit comprising a first load element (LD1) having one end coupled to a high-voltage source (VDD), a first field-effect transistor (Q1) having one end of its current path coupled to the other end of said first load element (LD1) and the other end of the current path connected to a corresponding end of the current path of a second field-effect transistor (Q2) and to one end of a first constant-current power source (CC1), the other end of which is connected to a low-voltage power source (VSS), a third field-effect transistor (Q3) having a current path connected, at one end, to said high-voltage power source, and having its control terminal coupled to the one end of the current path of said first field-effect transistor (Q1), a first level shift element (LS2) having one end coupled to the other end of the current path of said third field-effect transistor (Q3), a second load element (LD2) having one end coupled to said high-voltage power source (VDD) and the other end connected to the one end of the current path of said second field-effect transistor (Q2), a second constant-current power source (CC2) connected between the other end of said first level shift element (LS2) and said low-voltage power source (VSS), a fourth field-effect transistor (Q4) having a current path connected, at one end, to said high-voltage power source (V DD ) and a control terminal coupled to the one end of the current path of said second field-effect transistor (Q2), a second level shift element (LS4) having one end coupled to the other end of the current path of said fourth field-effect transistor (Q4), a third level shift element (LS1) coupled between said high-voltage power source (V DD ) and the one end of said first and second load elements (LD1, LD2), and a third constant-current power source (CC3) connected between the other end of said second level shift element (LS4) and said low-voltage power source (V SS ); characterised by a fifth field-effect transistor (Q5) having a current path connected, at one end, to said high-voltage power source (V DD ), and, at the other end to a first output terminal (OUT), and a control terminal connected to the other end of said second level shift element (LS4); a sixth field-effect transistor (Q6) having a current path connected, at one end, to the other end of the current path of said fifth field-effect transistor (Q5), the other end of the current path of said sixth field-effect transistor (Q6) coupled to said low-voltage power source (V SS ), and its control terminal connected to the other end of said first level shift element (LS2); and a fourth level shift element (LS5) coupled between the other end of the current path of said sixth field-effect transistor (Q6) and said low-voltage power source (V SS ). An output circuit according to claim 1, wherein said first and second level shift elements (LS2, LS4) each comprise a Schottky diode (D1, D3). An output circuit according to claim 1 or 2, wherein said first, second and third constant-current power sources (CC1,CC2,CC3) each comprise a resistor (R4, R5, R6) and a field effect transistor (Q7, Q8, Q9). An output circuit according to any preceding claim, further comprising a seventh field-effect transistor (Q10) having a current path connected, at one end, to said high-voltage power source (V DD ) and, at the other end to a second output terminal ( OUT ), and a control terminal connected to the other end of said first level shift element (LS2), and an eighth field-effect transistor (Q11) having a current path connected, at one end, to the other end of the current path of said seventh field-effect transistor (Q10) and, at the other end, to said low-voltage power source (V SS ), and a control terminal connected to the other end of the current path of said fourth field-effect transistor (Q4). An output circuit according to claim 4, further comprising a fifth level shift element (LS8) coupled between the other end of the current path of said sixth field-effect transistor (Q11) and said low-voltage power source (V SS ).

Inventors: NAGASAWA HIRONORI, NAGASAWA, HIRONORI, NAGASAWA, HIRONORI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: H03K19
IPC codes: H03K19, H03K5