Circuit for activating print head of wire printer

Abstract: The invention provides a circuit for activating the print head of a wire printer, in which print levers are attracted by respective actuator coils (19, 70) for advancing print wires fixed to the lever ends to print dots. The activating circuit comprises a first switching device (13, 69) having an input connected to a terminal (V p ) of a DC power supply and an output connected to one terminal of each of the actuator coils, and a second switching device (41, 71) connected to the other terminal of each of the actuator coils and also to ground. Counter electro-motive force absorbing means (44, 73, 74) are coupled to the actuator coils. First driving signal generating means (7, 66) produce a first driving signal to control the first switching means in response to a print timing control signal, the first driving signal having a duration T₁. Second driving signal generating means (16, 75) produce a second driving signal to control the second switching means, the second driving signal having a duration T₂ which is longer than the duration T₁. Delaying means (15, 67) are also provided for delaying the second driving signal relative to the first driving signal such that the first switching device is switched on simultaneously with or earlier than the second switching device.

Description: The present invention relates to a circuit for activating the print head of a wire printer for printing character-like configurations of dots through the selection of wires from a matrix of print wires, wherein the wire ends are moved towards a platen by magnetic attraction generated by electro-magnets. A known print head for use in a wire printer, that is a form of dot matrix printer, comprises a casing acting also as a magnetic core. A number of actuator coils, and print levers arranged to be attracted by the coils, are housed in the casing. The levers are driven by the attractive force of the coils for impacting wires fixed to front ends of the levers against paper held on a platen. The print head is activated by a drive circuit, which delivers voltage pulses to each particular coil according to the characters to be printed. Since each coil included in the circuit has reactance, electric power builds up. Therefore, if a switching device for controlling a neighbouring coil is turned on, electric current I₀ flows through the particular coil as shown in Figure 14 due to the electro-motive force induced by a change in the residual magnetic flux stored in the magnetic circuit of the print head, even though a printing step may be complete and the associated wire on its way to its home position. Therefore, the wires may return to their home positions with accumulated delays. Eventually, wires may protrude so that printing becomes impossible. In an attempt to prevent electric current from flowing through the actuator coils during the return of the associated wires if a change in the residual magnetic flux stored in the magnetic circuit induces electro-motive force as described above, various drive circuits for activating dot matrix printer heads have been proposed. Japanese Published Utility Model No. 191032/1988 discloses a drive circuit for activating the print head of a wire printer, in which each actuator coil for driving a wire has one terminal connected to a first switching device and the other terminal connected to another switching device. The first switching device receives a first driving signal to synchronise the printing. The second switching device receives a second driving signal in connection with data concerning a character to be printed. The terminal of each actuator coil which is connected to the first switching device is grounded via a diode, while the other terminal is connected to a driving DC power supply via a counter electro-motive force absorbing circuit. In the circuit configuration described above, the first driving signal having a pulse duration T 1a is delivered to the first switching device in synchronism with a timing control signal. The second driving signal having a pulse duration T 1c , longer than that of the first driving signal, is delivered to the second switching device for a selected actuator coil. The driving DC power supply energises the actuator coil by supplying electric current which flows through the first switching device, the actuator coil, and the second switching device in this order. Then, the coil attracts the print lever to move the wire towards the platen. After elapse of the period T₁, the first switching device is turned off to de-energise the coil. The resulting counter electro-motive force keeps electric current flowing through the second switching device, the ground, the diode and the actuator coil, thus maintaining the coil energised. After elapse of the period T 1c , the second switching device is turned off. The resulting counter electro-motive force induces electric current flowing through ground, the diode, the actuator coil, and a Zener diode of the counter electro-motive force absorbing circuit in this order. In this way, electric current is fed to the driving power supply. As a result, when the voltage generated by the counter electro-motive force induced in the actuator coil drops below the sum of the voltage developed by the DC power supply and the Zener breakdown voltage of the Zener diode, the current is cut off. For this reason, if another actuator coil is energised at the next instant, no deleterious electric current is produced. Hence, the wire can be returned quickly to its home position by a spring. In this drive circuit, the deleterious current produced during the wire return process can be reduced to quite a small value, but magnetic flux still remains in the head actuating circuit including the actuator coils. If the second switching device is turned on earlier than the first switching device, an electrical path consisting of the diode, the actuator coil, and the second switching device is formed. The result is that electric current I₀' is generated in the coil before the print wire is actuated as shown in Figure 15. Where the print speed is low and the wires are driven at long intervals of time, this current I₀' due to the electro-motive force attributed to the residual magnetic flux poses no serious problems, because it is quite small. Document EP-A-0294288 discloses a circuit for activating the print head of a wire printer including means for activation of a second switching device in response to a second drive signal and means for activation of a first switching device in response to a first driving signal. Even though the first switching device is switched on no later than the second switching, there is no disclosure of a composite drive signal. Essentially, the arrangement is directed to providing a drive time correction for individual printing wires, rather than controlling the sequence of switching of the first and second switching means. There is a requirement for printers to print at higher speeds. To comply with this requirement, wires have been designed to be at rest for shorter intervals of time, and a higher voltage is applied to each actuator coil to supply a larger electric current in a shorter time. As the response period of the actuator coils is shorter in this situation, the next character must be printed before the residual magnetic flux created by the previous energisation disappears. Further, the margin between the instant at which one wire returns to its home position and the instant at which the next wire is started to be activated is reduced. To permit supply of a large electric current, the first switching device is a transistor connected to the DC power supply, which delivers a relatively high voltage, usually of the order of 35 V. The base of a PNP transistor that withstands 5 V cannot be driven directly by a TTL circuit. Therefore, it is common practice to connect an NPN transistor before the first switching device to convert the first driving signal into a higher voltage. On the other hand, the second switching device is a further transistor whose emitter is connected to the ground of the DC power supply and so the second switching device can be turned on simply by applying a signal exceeding a certain level, normally 0.6 V, to its base. Consequently, the second device can be driven directly by a driving signal from a TTL circuit. If the driving signals for the first and second switching devices are supplied simultaneously, the first device is turned on after a delay equal to the time taken to turn on the NPN transistor provided to convert the first driving signal to a higher level. Thus, in spite of the fact that the signals for driving both switching devices are supplied simultaneously in response to a timing signal, there exists a period in which only the second switching device conducts. The electro-motive force induced in the actuator coil due to the residual magnetic flux produced by the previous printing step thereby gives rise to a circulating electric current. The actuator coil for the next lever to be actuated is thus energised earlier than intended and the character is printed at incorrect timing. That is, because counter electro-motive force still remains in the actuator coil for the wire about to be driven, electric current flows through the coil earlier than intended as shown in Figure 14. The lever is attracted by unwanted electro-magnetic force. This effect builds up as the lever is repeatedly driven and so the amount by which the wire is returned decreases with time. Finally, the wire protrudes towards the platen. In the worst case, a print wire is caught by the ink ribbon and becomes damaged or some dots fail to be printed, which leads to a deterioration in the print quality. It is an object of the present invention to provide an improved circuit for activating the print head of a wire printer. According to the present invention, there is provided a circuit for activating the print head of a wire printer, in which print levers are attracted by respective actuator coils for advancing print wires fixed to the lever ends to print dots, the activating circuit comprising a plurality of actuator coils, a first switching device connectable to a DC power supply and connected to one terminal of each of the actuator coils, a second switching device connected to the other terminal of each of the actuator coils and also connectable to ground, counter electromotive force absorbing means coupled to the actuator coils, first driving signal generator means for producing a first driving signal to control the first switching device in response to a print timing control signal, the first driving signal having a duration T 1a , second driving signal generating means for producing a second driving signal to control the second switching device in response to the print timing control signal, the second driving signal having a duration T 1c that is longer than the duration T 1a , means for delaying switching on of the second switching device in response to the second driving signal such that the first switching device is switched on in response to the first driving signal no later than the second switching device is switched on, characterised in that the delaying means is arranged to supply the first driving signal with a delay to the second driving signal generating means for initiating the second driving signal. The counter electro-motive force produced immediately after the creation of a dot is absorbed by the counter electro-motive force absorbing means to return the lever and the wire as quickly as possible. The delay time of the delaying means is set such that the first switching device is turned on simultaneously with or earlier than the second switching device. This prevents the generation of electric current which would otherwise be produced by electro-motive force induced by the magnetic flux remaining immediately before the next activation. As a result, the levers and wires return quickly and accurately to their home positions. Consequently, it is possible to operate the printing wires at a correct timing as specified by a driving signal, and to print characters at a high speed and with a high print quality. High speed printing can thus be achieved. The present invention is described further, by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram showing a circuit according to the invention for activating the print head of a wire printer; Figures 2a to 2c are diagrams showing various examples of a delay circuit of the activating circuit shown in Figure 1; Figure 3 is a block diagram showing one example of a gate array of the activating circuit shown in Figure 1; Figures 4a to 4d are diagrams showing various examples of a counter electro-motive force absorbing circuit of the activating circuit shown in Figure 1; Figure 5 is a timing chart for illustrating the operation of the activating circuit shown in Figure 1; Figure 6 is a graph showing the relation between the electric current flowing through each actuator coil energised by the activating circuit shown in Figure 1, the magnetic flux and the displacement of the corresponding print wire; Figure 7 is a graph showing the relation between the displacement of a print wire and the electric current flowing through its actuator coil when activated by the circuit shown in Figure 1; Figure 8 is a block diagram showing another activating circuit according to the invention; Figure 9 is a timing chart for illustrating the operation of the activating circuit shown in Figure 8; Figures 10a and 10b are graphs showing the relation between actuator coil voltage and pulse width in the activating circuit shown in Figure 8; Figure 11 is a waveform diagram showing how a first driving signal of the activating circuit of Figure 1 or Figure 8 may be modified; Figure 12 is a block diagram showing another activating circuit according to the invention; Figure 13 is a timing chart for illustrating the operation of the activating circuit shown in Figure 12; Figure 14 is a graph showing the relation between electric current flowing through an actuator coil and displacement of a print wire that is activated by the coil, in a conventional print head activating circuit having no counter electro-motive force absorbing means; and Figure 15 is a graph showing the relation between electric current flowing through an actuator coil and displacement of a print wire in another conventional print head activating circuit having counter electro-motive force absorbing means. Referring to Figure 1, there is shown a circuit embodying the present invention for activating the print head of a wire printer. The circuit includes a central processing unit (CPU) 1, which is connected to a RAM 3, a ROM 4, and an I/O interface 5 via buses 2 to form a micro-computer for controlling a printing operation. The CPU 1 receives data concerning characters to be printed from an external device (not shown) via the I/O interface 5. In response to the incoming data, the CPU 1 produces at an output terminal a timing control signal S₁ for activating the print head. The CPU is also programmed to deliver a signal via the buses 2 to a gate array 18 (described later) for selecting each actuator coil. A first driving signal generating circuit 7, consisting of a TTL circuit, receives the timing control signal S₁ having a period T₁ from the CPU 1 and delivers a first driving signal S₂ having a pulse duration of T 1a in synchronism with the timing control signal S₁. A level converter 10, which comprises an NPN transistor, has a base of the transistor connected to an output terminal of the first driving signal generating circuit 7 via a resistor 11. The collector of this transistor is connected to the base of a first switching transistor 13 (described later) via a resistor 12, while the emitter is grounded. The first switching transistor 13 is a PNP transistor which can withstand sufficiently the output voltage from a driving DC power supply (not shown). The emitter of the first switching transistor 13 is connected to the output terminal V p of the DC power supply. The collector is connected to a respective first terminal of each of a plurality of actuator coils 19a, 19b, 19c, 19d forming a print head, and also to ground via a diode 14 whose anode is grounded. In this example, a delay circuit 15 is connected to the output terminal of the first driving signal generating circuit 7, and provides a delay time ΔT which is set such that second switching transistors 41a, 41b, 41c, 41d (described later) are turned on simultaneously with or later than the first switching transistor 13. Figure 2a, 2b and 2c show different examples of the delay circuit 15. In Figure 2a, a transistor 20 is employed, and positive use is made of the time taken to turn it on. In Figure 2b, an inverter 23 is connected in series with an integrator consisting of a resistor 21 and a capacitor 22. The time required for the integrated voltage to reach the operating voltage of the inverter 23 is utilised. In Figure 2c, inverters 24, 25, 26 are connected in series and the delay time of the inverter circuit is employed. In the example of Figure 2c, three inverters are used but the number may be selected according to the required delay time. Referring back to Figure 1, a second driving signal generating circuit 16 receives the output signal from the delay circuit 15 and produces a second driving signal S₃ having a pulse duration T 1c longer than the pulse duration T 1a of the first driving signal S₂. The gate array 18 has a plurality of output terminals S 3a , S 3b , S 3c , S 3d , etc. and delivers printing signals at these terminals according to data concerning characters to be printed, in synchronism with the second driving signal S₃. Figure 3a shows one specific example of the gate array 18. In this example, the gate array comprises latch circuits 31, 32, 33, a decoder 34, and a gate circuit 35 for selecting one of the latch circuits 31 to 33. The latch circuits 31 to 33 are connected to a data bus 2 via a buffer amplifier 30. The decoder 34 is connected to an address bus 2. Dot signals for effecting a printing operation are latched in the latch circuits 31, 32, 33 according to the address signal from the address bus 2. When the driving signal S₃ from the second driving signal generating circuit 16 arrives at the gate array 18, printing signals synchronised with this second driving signal appear at the terminals S 3a , S 3b , S 3c , S 3d etc. and are supplied to the actuator coils 19a, 19b, 19c, 19d etc., respectively, to which the dots to be printed are assigned. Referring again to Figure 1, the bases of the second switching transistors 41a, 41b, 41c, 41d are connected to the output terminals S 3a , S 3b , S 3c , S 3d respectively, of the gate array 18, each second switching transistor consisting of an NPN transistor. The collectors of the second switching transistors are connected to the second terminals of the actuator coils 19a, 19b, 19c, 19d, respectively, and the emitters are grounded. Junction points 42a, 42b, 42c, 42d between the second switching transistors 41a, 41b, 41c, 41d and the actuator coils 19a, 19b, 19c, 19d, respectively, are connected to an input terminal of a counter electro-motive force absorbing circuit 44 via diodes 43a, 43b, 43c, 43d, respectively, which are connected in the reverse direction as viewed from the power supply terminal V p . Figures 4a to 4d show different examples of the counter electro-motive force absorbing circuit 44. The example shown in Figure 4a features a Zener diode 50. In the example shown in Figure 4b, a Zener diode 51 having a relatively small current capacity is connected between the collector and the base of a switching transistor 52. In the example shown in Figure 4c, a switching transistor 53 is connected in parallel with a Zener diode 54, and the Zener breakdown voltage of the diode 54 and the conducting voltage of the transistor 53 are utilised. In the example shown in Figure 4d, a parallel combination of a transistor 56 and a Zener diode 57 is connected between the base and the collector of a transistor 55, which controls conduction. The conducting voltage of the transistor 55 is controlled by the Zener breakdown voltage of the diode 57 and the conducting voltage of the transistor 56. The operation of the print head activating circuit described above will now be described with reference to the waveform diagram of Figure 5. In the following description, it will be assumed that the actuator coils 19a and 19c control printing of odd numbered rows, while the actuator coils 19b and 19d control printing of even numbered rows. The CPU 1 delivers the timing control signal S₁ with the period T₁, the signal essentially determining the movement of the carriage (not shown) and the timing of printing. The first driving signal generating circuit 7 delivers the first driving signal S₂, having the pulse duration T 1a in response to the leading edge of the timing control signal S₁. The first driving signal S₂ is applied to the level converter 10 so as to turn on the first switching transistor 13 when the sum of the time required to turn on the transistor 10 and the time required to turn on the switching transistor 13 passes. The first driving signal S₂ from the first driving signal generating circuit 7 is also applied to the delay circuit 15, having the delay time ΔT, and thence is supplied to the second driving signal generating circuit 16 after the delay ΔT, thus initiating operation of the gate array 18. The gate array 18 receives data concerning printing characters from the CPU 1 and turns on the second switching transistor 41a or 41c connected to the corresponding actuator coil 19a or 19c of the print head. Since the first and second driving signal generating circuits 7, 16, and the gate array 18 are each composed of a TTL circuit, they respond at much higher speeds than the switching transistors and the level converter transistor. Therefore, the delays introduced by them can be neglected. Since the first driving signal S₂ applied to the second switching transistor 41a is delayed by the time ΔT by the delay circuit 15 as described above, the first switching transistor 13 is rendered conductive simultaneously with or earlier than the second switching transistor 41a. When the transistor 41a is biased into conduction, the actuator coil 19a or 19c is supplied with DC power from the driving DC power supply. The actuator coil 19a or 19c is energised with electric current I 1a which increases with a time constant determined by its reactance and internal resistance. When the time t 1a determined by the pulse duration T 1a of the first driving signal generating circuit 7 elapses, the first switching transistor 13 is turned off, so that the coil 19a or 19c is de-energised. The second driving signal generating circuit 16 then continues producing the second driving signal S₃ to keep the second switching transistor 41a conductive. The counter electro-motive force induced in the actuator coil 19a when the first switching transistor 41a is biased off produces circulating electric current I 1b , which passes through the second switching transistor 41a, ground, the diode 14, and the actuator coil 19a in this order. This causes the coil 19a to continue generating magnetic flux to attract the associated print lever. In this manner, when a time t 1b elapses since the first driving signal S₂ ceases, i.e. when the duration T 1c elapses, the driving signal S₃ from the second driving signal generating circuit 16 ceases. As a result, the second switching transistor 41a is turned off. The counter electro-motive force induced in the coil 19a then produces electric current I 1c which flows into the DC power supply after passing through the diode 43a, the counter electro-motive force absorbing circuit 44, and the power supply terminal V p . Thus, when the voltage generated by the counter electro-motive force drops below the sum of the voltage at the power terminal V p , the conducting voltage of the counter electro-motive force absorbing circuit, and the forward voltage of the diode 43a, the current ceases, while the residual magnetic flux decreases gradually. The relationship between current, magnetic flux and print wire displacement is shown in Figure 6. This assures that the electro-motive force arising from the magnetic flux remaining at the middle point of the period is prevented from producing the electric current I₀ generated in the prior art and illustrated in Figure 14. When the first printing step ends, the CPU 1 produces the next timing control signal S₁ to permit the actuator coils 19b and 19d, which were not activated in the first printing step, to be energised. Specifically, when the second timing control signal S₁ is produced, the first driving signal generating circuit 7 delivers a further first driving signal S₂ having a pulse duration T 2a . The first switching transistor 13 receives the next signal S₂ and is turned on after elapse of a time determined by the sum of the times required for the transistor 10 and the switching transistor 13 respectively to be made conductive. The first switching transistor 13 then supplies voltage to all the actuator coils 19a, 19b, 19c and 19d. Meanwhile, the first driving signal S₂ delivered from the first driving signal generating circuit 7 is applied to the delay circuit 15 and is thence fed to the second driving signal generating circuit 16 with the delay ΔT. The circuit 16 produces a further second driving signal S₃ having a pulse duration T 2c . Because the second driving signal S₃ is delayed by the time ΔT by the delay circuit 15, the first switching transistor 13 is biased into conduction simultaneously with or earlier than the second switching transistor 41b or 41d irrespective of the delay in the response of the transistor 13 itself and the transistor 10. Accordingly, the DC power supply applies a reverse voltage to the diode 14. The previously energised actuator coil 19a still has a residual magnetic flux and keeps producing electro-motive force. The voltage developed by the DC power supply maintains the diode 14 cut off. Therefore, if the second switching transistor 41b conducts, the counter electro-motive force induced in the actuator coil 19a is unable to energise the coil. For this reason, the coil 19a is not now energised with unwanted electric current, but is driven only at the timing specified by the second driving signal S₃ at the gate array 18. Consequently, the print lever and the print wire move merely as intended in the initial design. After the printing operation, they return to their home positions with certainty. In this way, when the first timing control signal S₁ is produced, the print levers which were driven by the actuator coils 19a and 19c in the previous printing step remain in their home positions. Hence, they can respond accurately to the next driving signal. The residual magnetic flux produced by the previous activation thus generates no electric current either during the present activation, as shown in Figure 7, or immediately before the previously selected wire is next driven. Consequently, every printing wire is returned to its home position in each printing step. In this way, the present activating circuit controls the movement of each print wire as desired and causes the print head of the wire printer to print with a high print quality. Referring next to Figure 8, there is shown another activating circuit according to the invention. This circuit includes a central processing unit 60 which is connected to a RAM 62, a ROM 63, and an I/O interface 64 via buses 61 to form a micro-computer for controlling a printing operation. The CPU receives data regarding characters to be printed from an external device (not shown) via the interface 64. The CPU is so programmed that it produces a timing control signal S₁ for driving a print head at an output terminal in response to the incoming data and it produces an output signal to a gate array 65 via the buses 61 to select each actuator coil. A first driving signal generating circuit 66, which comprises a TTL circuit, delivers a first driving signal S₂ having a pulse duration T 1a in synchronism with the timing control signal S₁ from the CPU 60. An output terminal of the circuit 66 is connected to a first input terminal of the gate array 65. A delay circuit 67 receives the first driving signal S₂ from the first driving signal generating circuit 66. The signal S₂ is delivered to a second driving signal generating circuit 75 with a delay time ΔT. This delay circuit 67 can be any one of the delay circuits shown in Figures 2a to 2c. The delay time is set in such a way that first and second switching transistors (described later) are biased into conduction at the same time. The second driving signal generating circuit 75 receives the output signal from the delay circuit 67 and produces a second driving signal S₃ having a pulse duration T 1c longer than that of the first driving signal S₂. NPN transistors 68a, 68b, 68c, 68d are provided for level conversion. Their bases are connected to output terminals S 1a , S 1b , S 1c , S 1d , respectively, of the gate array 65, which produce the first driving signal S₂. The transistors 68a to 68d function to turn on or off first switching transistors 69a, 69b, 69c, 69d, respectively, each of which is connected to a terminal V p of a driving DC power supply. The emitters of the first switching transistors 69a, 69b, 69c, 69d are connected to the terminal V p of the power supply, while their collectors are connected to respective first terminals of actuator coils 70a, 70b, 70c, 70d. The bases of the transistors 69a, 69b, 69c, 69d are connected to the level conversion transistors 68a, 68b, 68c, 68d, respectively. Second switching transistors 71a, 71b, 71c, 71d have their collectors connected to the other terminals of the coils 70a, 70b, 70c, 70d, respectively, and their emitters grounded. The bases of the transistor 71a to 71d are connected to terminals S 3a , S 3b , S 3c , S 3d , respectively, of the gate array 65, which deliver the second driving signal S₃. The coils 70a to 70d are further connected to the terminal V p of the power supply via first diodes 73a, 73b, 73c, 73d, respectively, and to ground via second diodes 74a, 74b, 74c, 74d, respectively, to form a counter electro-motive force circuit. The operation of the print head activating circuit shown in Figure 8 will next be described with reference to the waveform diagram of Figure 9. It is assumed in the following description that the actuator coils 70a and 70c are assigned to the odd numbered rows and the actuator coils 70b and 70d to the even numbered rows. The CPU 60 delivers the timing control signal S₁, which essentially determines the movement of the carriage (not shown) and the timing of the printing. The first driving signal generating circuit 66 delivers the first driving signal S₂ of pulse duration T 1a at the leading edge of the timing control signal S₁. The driving signal S₂ is supplied to the level conversion transistors 68a, 68b, 68c, 68d from the first terminals S 1a , S 1b , S 1c , S 1d of the gate array 65 to bias the first switching transistors 69a and 69c, for odd rows, into conduction after a lapse of time corresponding to the turn on characteristics of the devices. The first driving signal S₂ from the first driving signal generating circuit 66 is also applied to the delay circuit 67 and thence to the second driving signal generating circuit 75 with the delay time ΔT added by the delay circuit 67. Thus, the timing at which the gate array 65 operates is determined. The gate array 65 receives data concerning characters to be printed from the CPU 60 and produces the second driving signal S₃ from the terminal, for example S 3a , connected with the corresponding actuator coil, such as 70a. Since the first switching transistors 69a and 69c conduct concurrently with the second switching transistors 71a, 71b, 71c, 71d, as mentioned previously, the DC voltage from the DC power supply is applied to the actuator coil 70a or 70c when the second switching transistor 71a is rendered conductive. The actuator coil 70a or 70c is supplied with electric current I 1a which increases with a time constant determined by its reactance and internal resistance. When the time t 1a determined by the pulse duration T 1a of the first driving signal S₂ elapses, the first switching transistor 69a or 69c is switched off, so that the coil 70a or 70c no longer receives electric current from the driving DC power supply. Meanwhile, the second driving signal generating circuit 75 still produces the second driving signal S₃ to keep the second switching transistor 71a conductive. The counter electro-motive force induced in the actuator coil 70a due to cut off of the first switching transistor 69a produces a circulating current I 1b that flows through the second switching transistor 71a, the diode 74a, and the actuator coil 70a. This makes the coil 70a continue to produce magnetic flux, thus continuing to attract the print lever. When the duration T 1c elapses, the driving signal S₃ from the second driving signal generating circuit 75 ceases and the second switching transistor 71a is switched off. Then, the counter electro-motive force induced in the coil 70a produces electric current I 1c which flows through the coil 70a, the diode 73a, and the terminal V p of the DC power supply. When the voltage produced by the counter electro-motive force decreases below the sum of the voltage at the power supply terminal V p and the forward voltage of the diode 73a, the electric current ceases. The residual magnetic flux then decreases gradually. When the first printing step ends, the CPU 60 produces the next timing control signal S₁ to permit the actuator coil 68b and 68d not energised in the first printing step to be energised. More specifically, the second timing control signal S₁ is delivered to the first driving signal generating circuit 66, which produces a further first driving signal having a pulse duration T 2a . The first switching transistor 69b and 69d receive this signal and are biased into conduction after a lapse of time determined by the turn on characteristics of the level conversion transistors 68b, 68d, and the first switching transistors 69b and 69d. The conducting transistors 69b and 69d apply a voltage to the actuator coils 70b and 70d for the even rows. The first driving signal S₂ produced by the first driving signal generating circuit 66 is also applied to the delay circuit 67 and thence to the second driving signal generating circuit 75 with a delay ΔT. The circuit 75 thus delivers a further second driving signal S₃ of pulse duration T 2c . Because of the delay, the first switching transistor 69b and 69d are turned on simultaneously with or earlier than the second switching transistors 71b and 71d, irrespective of the delay introduced by the times required for the first transistors 68b and 68d and 69b and 69d to be biased on. Then, the voltage from the DC power supply is applied to the diodes 74b and 74d to bias them into cut off. At this time, the actuator coils 70a and 70c that were energised during the previous activation are still affected by the residual magnetic flux and keep producing electro-magnetic force. However, the voltage from the DC power supply keeps the diodes 74b and 74d cut off. Therefore, the counter electro-motive force induced in the actuator coils 70a and 70c is able to produce no electric current. In this way, the electro-motive force attributed to the residual magnetic flux develops no electric current. Hence, each print lever moves just as intended and returns to its home position. Thus, it is ready for the next activation. It is necessary that the pulse duration T 1a and T 1c each be selected to be a maximum in synchronism with the period of the response of the print head. Generally if the pulse durations are set long, the residual magnetic flux delays the restoring action, producing imperfect printing. Also it is difficult to print characters at a high speed. On the other hand, if the pulse durations are short, it is necessary to supply a substantial amount of energy to the actuator coils, thus increasing the eddy current loss. As a result, the actuator coils produce unwanted heat. Experiment has shown that if the optimum pulse durations T 1a and T 1c and the response period T₁ (period of the timing control signal S₁) satisfy the relations 0.25 ≦ T 1a + T 1c T₁ ≦ 0.5 and 0.5 ≦ T 1a T 1a + T 1c ≦ 0.9 then good results are obtained. Preferably, the pulse durations T 1a and T 1c are modified according to the thickness of the paper to be printed. If the paper is thick, they are altered to be longer than the initially set value. If the paper is thin, the pulse durations T 1a and T 1c are modified to be shorter. Also, it is desirable to change the pulse duration T 1a according to either the power supply voltage applied to each actuator coil or the voltage applied between the two terminals of each actuator coil. The modified pulse duration is obtained empirically and given by T 1a - A ln (1 - B V p ) where V p is the detected voltage applied to the actuator coil, and A and B are constants and assume values defined by 200 ≦ A ≦ 800, 3 ≦ B ≦ 30 As an example, the relation between the detected voltage applied to the actuator coil and the pulse durations T 1a , T 1c are shown in Figures 10a and 10b. In the above examples, each first switching transistor is driven with a single pulse signal. In an alternative chopping driving system, one stage of the first driving signal S₁ may be divided into plural pulses P₁, P₂, P₃ and P₄ as shown in Figure 11 so that the coil current may rise at a higher speed. The leading edge of the second driving signal S₃ is delayed by the time ΔT with respect to the leading edge of the first pulse P₁ of the first driving signal S₂. This yields the same advantages as described above. Of course, the second driving signal S₃ continues to be delivered after the end of the pulse P₁. At this time, the print wire is being accelerated and so the electric current arising from the counter electro-motive force contributes to the acceleration of the wire without adverse effect. In the above examples, it is possible for capacitors 100a to 100d to be connected, respectively, between both ends of the corresponding switching means to regulate the electric currents supplied to the actuator coils 70a to 70d when the print levers are driven, as shown in the activating circuit of Figure 12, which differs from that of Figure 8 only in the provision of the capacitors. The capacitors act as electrical power storing means when the coils 70a to 70d are not energised. The capacitances of the capacitors 100a to 100d are selected such that the relation C ΔV² = L Δi² is met, to prevent a drop Δi of the electric current during activation as shown in Figure 13. In the above equation, C is the capacitance of each capacitor, and L is the inductance of each actuator coil. In the example shown in Figure 12, a single capacitor is connected with each individual actuator coil. Obviously, a capacitor can be connected with plural actuator coils, provided that the relation C = L ( Δi ΔV )² is appropriately catered for.

Claims: A circuit for activating the print head of a wire printer, in which print levers are attracted by respective actuator coils for advancing print wires fixed to the lever ends to print dots, the activating circuit comprising a plurality of actuator coils (19, 70), a first switching device (13, 69) connectable to a DC power supply and connected to one terminal of each of the actuator coils, a second switching device (41, 71) connected to the other terminal of each of the actuator coils and also connectable to ground, counter electromotive force absorbing means (14, 43, 44, 73, 74) coupled to the actuator coils, first driving signal generator means (7, 66) for producing a first driving signal to control the first switching device in response to a print timing control signal, the first driving signal having a duration T 1a , second driving signal generating means (16, 75) for producing a second driving signal to control the second switching device in response to the print timing control signal, the second driving signal having a duration T 1c that is longer than the duration T 1a , means (15, 67) for delaying switching on of the second switching device in response to the second driving signal such that the first switching device is switched on in response to the first driving signal no later than the second switching device is switched on, characterised in that the delaying means (15, 67) is arranged to supply the first driving signal with a delay to the second driving signal generating means (16, 75) for initiating the second driving signal. An activating circuit according to claim 1, characterised in that the delaying means comprises a transistor (20), and provides a delay based on the time required for the transistor to be rendered conductive. An activating circuit according to claim 1 or claim 2, characterised in that the delaying means comprises an integrating circuit (21, 22). An activating circuit according to claim 1, 2 or 3, characterised in that the delaying means comprises at least one inverter (23, 24, 25, 26). An activating circuit according to any preceding claim, characterised in that the first switching device comprises a switching element (13) which is connected to the first terminals of a plurality of the actuator coils. An activating circuit according to any of claims 1 to 4, characterised in that the first switching device comprises a plurality of switching elements (69), each of which is connected to the first terminal of a respective actuator coil. An activating circuit according to any of the preceding claims, characterised in that the duration T 1a and the duration T 1c satisfy the conditions 0.25 ≦ T 1a + T 1c T₁ ≦ 0.5 and 0.5 ≦ T 1a T 1a + T 1c ≦ 0.9 where T₁ is the period of the print timing control signal. An activating circuit according to any of the preceding claims, characterised in that the duration T 1a is modified as follows: T 1a - Aln (1 - B V p ) where V p is the voltge of the power supply and A, B are constants such that 200 ≦ A ≦ 800 3 ≦ B ≦ 30. An activating circuit according to any of the preceding claims, characterised in that the first driving signal comprises a plurality of pulses (P₁, P₂, P₃, P₄), each having a pulse width less than T 1a . An activating circuit according to any of the preceding claims, characterised by a plurality of capacitors (100), each of which is connected between the connection of the first switching device to the DC power supply and the connection of the second switching device to ground. An activating circuit according to any of the preceding claims, characterised in that the first switching means (13, 69) receives its input signal via a level conversion means (10, 68). An activating circuit according to any of the preceding claims, characterised in that first diodes (14, 74) are connected between said one terminal of each actuator coil and ground in the reverse direction as viewed from the DC power supply. An activating circuit according to claim 12, characterised in that second diodes (73) are each connected between said other terminal of each actuator coil and the DC power supply in the reverse direction as viewed from the DC power supply.

Inventors: FUKANO TAKAKAZU C O SEIKO EPSO, NISHIZAWA KATSUHIKO C O SEIKO, FUKANO, TAKAKAZU, NISHIZAWA, KATSUHIKO, FUKANO, TAKAKAZU, C/O SEIKO EPSON CORPORATION, NISHIZAWA, KATSUHIKO, C/O SEIKO EPSON CORPORATION
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1990
Main classification: B41J2
IPC codes: B41J2