PROCESS AND DEVICE FOR THE DECODING OF A SHORTENED CYCLIC BINARY CODE USING ERROR CORRECTION

Abstract: Process and device to decode a shortened cyclic binary code, able to correct single errors bursts of given length t or shorter, specially for an F(n-b,k-b) shortened fire code. It is based on the calculation of two syndrome polynomials, s1(x) and s2(x), in two specific registers (SR1, SR2), on the shifting in a first direction of the polynomial s1(x) <SIGN> 1 times until the errors burst is trapped in the t less significant positions of the first (SR1) register and on the shifting of the syndrome polynomial s2(x) <SIGN> 2 times in an opposite second direction in a third (MEL) register until it becomes equal to the t less significant positions of the first (SR1) register. Alternatively the second register can be a bidirectional shift register (SRb) where the shifting takes place also in the second direction. Moreover all computations in the process are made as simple as possible.

Description: "PROCESS AND DEVICE FOR THE DECODING OF A SHORTENED CYCLIC BINAR CODE USING ERROR CORRECTION" DESCRIPTION This invention concerns the decoding of a binary code able t correct errors bursts, and, more precisely, a process for th decoding of a cyclic shortened binary Fire code. Moreover thi invention relates to a decoding device that tests the presence o such errors and corrects and decodes the received code word. The rate of digital transmission is getting more and more faster. Errors arising in the transmission channel, due to disturbance such as noise, fading, interferences, and so forth, make th transmission not reliable. Therefore, several techniques are use for the automatic correction of such errors on reception. This is usually obtained protecting the information to be sent b means of error correction codes. Considering such information as being divided in words of k bits each, the block code (n,k) follows a relationship law coupling each word of information to a n bit long code with n>k. The n-k difference is called redundancy. Cyclic codes are a class of such kind of codes, where all the words in the code can be obtained starting from a word in the code by means of a process of cyclic shifting. It is helpful to use polynomials to represent both the information and the code words. So, the information word, a k-pla (i 0, i,1,...i | ,-,l),iwill be represented by the polynomial i " 0 + i-1x + . . + i. .x ~ = i(x), and the code word, a n-pla (c , c,,...c ,), will be represented by c + c,x +...+C ,x n" c(x). The law of coding itself can be represented by a g(x) polynomial of degree (n-k), the so-called generator, such that the code polynomial c(x) is obtained multiplying the g(x) polynomial by the polynomial i(x). - important class of such codes, able to contrast errors bursts that are typical in memory channels (like radio channels affected by fading) is the class of the so-called Fire codes with GF(2), the above notation representing double value (0 and 1) Galois fields. The generator polynomial of such kind of codes can be expressed in a general form by: g(x) = (x 2 * "1 -l)p(x) (1) where p(x) is an m degree irreducible polynomial. Let ro be the period of p(x), i.e. the smallest integer such that p(x) divides (x +1) and t a positive integer, smaller or equal to m, such that (2t-l) is not divisible by ro. The code length (the number of bits in each code word) is the least common multiple of (2t-l) and ro, and the number of redundant bits is (m+2t-l). Further on, we shall indicate the Fire codes with the notation F(n,k), where n indicates the length of the coded word, k is the length of the information word and (n-k) is the redundancy. A code with generator polynomial g(x) given by (1), for which the above conditions expressed for m, ro and (2t-l) are verified, is able to correct any single errors burst (i.e. the sequence of bits included between the first and the last erroneus bit in the code word) shorter or equal to t, and also to detect the presence of errors burst longer than t. Fire codes can be decoded using decoders belonging to the family of "Error Trapping" decoders. In such devices, the time required for correcting the errors is equal to n cycles, n being the length of the code word. In technical literature, there are some known decoders studied "ad hoc" for the Fire codes, able to correct errors in a shorter time. One of such devices has been proposed by R. T. Chien in his paper "Burst-correcting codes with high-speed decoding", IEEE Trans, on Information Theory, Vol. IT-15, Nr. 1, January 1969. Once the code word has been inputted, Chien's decoder can correct errors in a number of cycles (this being the delay with which the correct code can be obtained) given at most by: (2t-2) + (ro - 1) (2) As for a Fire code, n is the least common multiple of (2t-l) and ro, and as (2t-l) is not divisible by ro, n can at most be equal to ro.(2t-l). A normal "Error Trapping" decoder would at most take ro.(2t-l) cycles to correct errors. Such value is much larger than the one given by expressione (2), and this justifies the given definition for Chien's device as a high speed one. The basic idea in Chien's decoder is that of using as syndrome a couple of polynomials, sl(x) and s2(x), where sl(x) is the remainder polynomial obtained by dividing the received polynomial ?t-i r(x) by the factor (x " + ' l) in the generator polynomial, and s2(x) is the remainder -polynomial obtained by dividing the received polynomial r(x) by the factor p(x) in the generator polynomial. Above we have used r(x) to represent the received code word that, eventually, conteins errors. Chien's decoder basically consists of two loop back shift registers. Both are fed by the bit sequence received in each generic code word. The first register, called "Error Pattern Register", consists of (2t-l) stages and is used to compute the polynomial sl(x). The second Register, called "Error Location Register" consists of m stages, and is used to calculate the polynomial s2(x). If both the polynomials sl(x) and s2(x) are null polynomials, no correction is applied, and the device only performs the decoding of the received code word which is error free. If just one of the two polynomials sl(x) and s2(x) is not a null polynomial, then the device does not decode but detects the presence of errors (the irror burst being greater than t) . Finally, if both polynomials sl(x) and s2(x) are not null polynomials, then the error correction process is started, at the end of which the decoding is performed (for errors bursts of length <=t). The correction algorithm is accomplished in four phases: - Phase 1. sl(x) is shifted 11 times in the Error Pattern Register to obtain all zeros in the most significant (t-1) positions. The remaining t positions will be occupied by the components of the polynomial b(x) of degree (t-1). The polynomial b(x) represents, unless an integer number of shifts, the burst to be corrected. - Phase 2. s2(x) is shifted 12 times into the Error Location Register until the polynomial b(x) is obtained in the less significant t positions. - Phase 3. There is only one integer q that, when divided by ro and by (2t-l) gives respectively I I and J 2. The value of q can be calculated using the formula: q = Λ.A2.ro + *2.Al.(2t-l) mod(n) (3) Al and A2 being integers that satisfy the condition: Al.(2t-1) + A2.ro = 1 (4) - Phase 4. The polynomial x^ " ^ .b(x) is the errors burst to be corrected. The correction is realized by adding modulo 2 the polynomial x .b(x) to the received polynomial r(x). As said, the length of a Fire code can be given at most by the expression: n = (2 - l).(2t-l) (5) which is verified if ro and (2t-l) are prime to each other. The formula (5) clearly shows that by an increase of t, m being >t, the length of the code increases at least of a factor equal to 2 m . For instance, a Fire code with m=t that corrects 10 bits bursts (t=10) is 19437 bits long. It is well known that to obtain smaller words, the code can be shortened by substracting b bits from both the information word and its related code word. As a result, a code (n-b,k-b) is obtained. The structural properties of such code will be the same of the initial code. In the following, we shall indicate with F(N=n-b,K=k-b) a shortened Fire code, obtained by substracting b bits to the information word, and the same amount of bits to the word in the code F(n,k). As an example, let consider the shortened code F(224,182) with t=12 specified by ETSI/GSM (Groupe Special Mobile), defined by the following generator polynomial: g(x) = (x 23 + l).(x 17 + x 3 + 1) (6) For this code: ro=131071, and n=3014633. It is exactly in such cases that a shortened code becomes interesting. Even more, in order not to handle words of big length, it is useful to use large values for the b factor. The result of such shortening operation can lead to a N=n-b value smaller than ro, like in the example shown in (6), where N is «ro. Let assume the following working hypotesis: - p(x) primitive on GF(2); - ro and (2t-l) prime to each other; - N = n-b<ro, and preferably <ro/2. If the Chien device is used for decoding and correcting errors, the above mentioned working conditions shall not influence the calculation of sl(x) and s2(x), so the correction algorithm for the errors burst starts when the polynomials sl(x) and s2(x) are not null. Moreover as far as the computation of J l is concerned, there are no comments to do. But the calculation of 12 belongs to a different case, where we can observe that: a) As the word in the shortened code is of length N, the constraint n-q<N applies to the generic component of the polynomial representing the received code word and to the burst x n"q b(χ) to be corrected. b) For n-q=ro-l, it results that T 2=1, for n-q=ro-2 it is 2=2,... for n-q=ro-k it is T*2=k. c) Being N<ro, let be D=ro-N, the constraint on (n-q) in item a) becomes n-q<ro-D-l. d) The constraint on n-q in item c), because of the remarks performed in item b), causes a constraint for Tl. e) The shift Register "Error Locator" is a sequential machine, reaching the state at which is 2=D+1 only after the s So, the burst x cycles, and the b ter D+ cycles. Therefore, even if there is a considerable shortening of the code length, Chien's decoder still y takes at least (ro-N+1) stages to correct the errors, making it useless to handle a shortened code. Coming back to the above mentioned example concerning ETSI/GSM, even if the code has a length n=224, the error correction process would consist of at least (ro-N+1)=130848 cycles. Furthermore, the error correction process proposed by Chien requires the computing of an expression like (3), which contains six multiplication and one sum, and must, therefore, be implemented by a dedicated real time fast logic, or by means of a quite extended memory table to supply precalculated values of q for each Pi and Vz couple. Therefore, one of the pourposes of this invention is to avoid the limitations shown above in the already known decoding technique, and specially, to decrease in a considerable way the correction delay in the decoding of shortened Fire codes. Another purpose of this invention is, to create a faster decoding device working with shortened Fire codes than the ones using the previous technique. One more aim of the invention is to simplify computation in the error correction process. All this results are reached using the invention, which consists of a process for decoding a shortened cyclic binary code, which is able to correct single errors bursts b(x) of given length t or shorter, and specially of a shortened F(n-b, -fa) Fire code, with 2t-l generator polynomial g(x)=(x +l).p(x), where p(x) is a prime polynomial over GF(2), and having period ro, satisfying the condition ro>(n-b), in which: the received r(x) code word is stored and the sl(x) and s2(x) syndrome polynomials are calculated in (n-b) cycles; the sl(x) polynomial is cyclically shifted a Tl number of times in a first direction until all zeros are obtained in the (t-1) positions of the higher order so to trap the burst b(x) of length t in the lower order positions; this procedure is characterized by: - shifting of the remainder polynomial s2(x), in an opposite direction to the above mentioned first one.until the pattern of .the t bits of the lowest order becomes the same as that of the already mentioned burst b(x) of length t, and to calculate a T z number equal to (ro-h), where h is the amount of shift operations performed; - calculate (n-q) by the relation: q = Tl.A2.ro + P2.Al.(2t-l) mod(n) where Al and A2 are two positive integers such that: Al.(2t-1) + A2.ro = 1; - perform the correction adding modulo 2 the polynomial (x n"c ').b(x) to the received vector. The invention also consists of a process for the decoding of a shortened cyclic binary code, able to correct single errors burst b(x) of stated length t or less, in particular of a shortened Fire code F(n-b,n-k) having a generator polynomial 2t-l g(x)=(x +l).p(x), where p(x) is a prime polynomial over GF(2) and having period ro, in which, by means of cyclic shift operations, the T Z number is calculated equal to (ro-h), with h given by the number of shifts occurred to trap the errors bursts b(x) in the t less significant positions of the syndrome polynomial s2(x). This way of proceeding being characterized by the fact of calculating (n-q) by the relation: n-q = 2 + 1 - ro and to perform the correction adding modulo 2 the polynomial (x n ~ q ).b(x) to the received vector. Moreover, the invention also consists of a decoder for binary shortened cyclic code and in particular a shortened F(n-b,k-b) Fire code able to correct single errors bursts of length t or 2f 1 less and having a generator polynomial g(x)=(x +l).p(x) where p(x) is a prime polynomial over GF(2) and with period ro satisfying the condition ro>(n-b). The decoder is characterized by the fact of including a combination of: a buffer register of (n-b) stages; a first shift register, wrth (2t-l) stages, shifting data in a first direction; a second shift register, with m stages, shifting data in the above mentioned first direction; said buffer, first and second register receiving as input the word r(x); first modulo (2t-l) counting means able to compute the number of shifting operations performed by said first register; a device for testing the content of the higher order (t-1) stages of said first register, said device being connected to said first counting means; a third shift register of m stages, capable of shifting data in a second direction, opposite to the first one, said third register being connected in parallel to the second register; a comparing device connected to the lowest order t stages of said first and third registers; second modulo ro counting mean, connected to said comparing device to compute the number of shifting operations performed by said third register; a computing circuit, connected to the outputs of said first and second counting means for computing a number (n-q), able to allow, in the case, the correction of errors burst in the received word. The invention finally consistsof a decoder for a shortened cyclic binary code, in particular a shortened F(n-b,k-b) Fire code, with a generator polynomial (g(x)= (x 21-1 +l).p(x), p(x) being a prime polynomial over GF(2) and of period ro, satisfying the condition ro>(n-b), and able to correct single errors bursts of length for less, characterized by the fact of being made of a combination of: a buffer register of (n-b) stages; a first shift register, with (2t-l) stages and shifting data in a first direction; a second shift register, with m stages and capable of shifting data in said first direction and in an opposite direction; said buffer, first and second registers receiving as input the word r(x); first modulo (2t-l) counting means able to compute the number of shifting operations performed by said first shift register; second modulo ro counting means able to compute the number of shifting operations performed by said second shift register; a device for testing the content of the higher order (t-1) stages of said first shift register and connected to said first counting means; a comparing device, connected trough the lowest order t stages of said first and second shift registers, and connected to said second comparing means; a computing circuit, connected to the output of said first and second counting means for computing a number (n-q), allowing the eventual correction of an errors burst in the received word. Further evolutions of the invention are stated in the included claims. The invention will now be described with more details with references to two realization schemes, shown in the joint drawings, in which: Fig. 1 shows a decoder that includes the invention; Fig. 2 shows a possible variation of the decoder according to the invention; Fig. 3 schematically shows an example of a loop back shift register. With reference to Fig. 1, the decoder, according to the invention, includes two loop back shift registers SRI and SR2, receiving as input the received code word r(x) and shifting data from left to right. More precisely, the SRI register is the "Error Pattern Register", and computes the syndrome polynomial sl(x) that is the remainder of the division of the r(x) 2t-l polynomial by the factor (x +1), while the SR2 register, called "Error Locator Register", computes the syndrome polynomial s2(x), which is the remainder of the division of the polynomial r(x) by the factor p(x). It's well known that the division of a polynomial z(x) of degree n and with coefficients in*GF(2) by the polynomial g(x) of degree (n-k) and with coefficients in GF(2) is accomplished in the GF(2) field by shift registers, like, for instance, the one shown in Fig. 3, consisting of (n-k) stages (memory cells) d. (j = l,...,n-k), and, at most, of (n-k) exclusive-OR gates W. supplying the stage d. with the content of the highest order cell d . , modulo 2 added to the content of the previous cell d. .. The generic exclusive-OR gate number j exists physically if the coefficient j of the polynomial g(x) is not zero. At each cycle, the content of each stage is shifted one position to the right. After n-cycles, the entire polynomial z(x) is processed, and the remainder of the division is available in the memory cells corresponding to the positions of the lowest order in the register. Now, coming back to Fig. 1, in which, not to make the drawing too complicated, a simplified notation is used for a generic realization, after n-b cycles needed to store the code word in the buffer register BF and to compute the two syndrome polynomials sl(x) and s2(x) in the SRI and SR2 shift registers respectively, the SW1, SW2 and SW3 gates are opened, insulating the registers from the further flow of data. This is performed by the device CM for the supervision and control of the decoder. Moreover, CM also supplies the clock signal CK to the different components. The register SRI consists of (2t-l) stages, subdivided in an part A of length t (the less order stages) and in a part B of length (t-1) (the higher order stages). The SR2 register consists of stages. The register BF consists of n-b stages. By means of conventional devices that, for semplifity, are not shown in Fig. 1, it's determined if both sl(x) and s2(x) are null and, in such case, the received word r(x) is without errors and is forwarded from the buffer BF to the following decoding and reception circuits, which are^ not shown, because they are of a known type, and however, they are not relevant for what this invention is concerned. If only one of the polynomials is not null, this means that a errors burst longer than t, which the device is not able to correct, has been detected. In this case the word r(x) is not decoded. If both sl(x) and s2(x) are different from null polynomial then the invention's correction process begins. The polynomial sl(x) is shifted rightwards / 1 times in the register SRI until the errors burst is trapped in the part A of the register SRI, which consists of t stages. This condition is verified when the (t-1) stages in the part B of the register SRI contain all zeros. For this pourpose, the part B of the register SRI is connected in parallel with a TS circuit, which tests the contents of the part B. The test circuit TS is furthermore connected to a modulo (2t-l) counting device CT1, which initially is set equal to zero, and that is increased of one unit each time a shift in SRI is performed. If the value in the counting device CT1 overcomes (2t-2), then the presence of errors is detected and the word is not decoded. The content of the stages in the register SR2 is transferred in parallel in the m stages of a third shift register MEL (capable of performing a leftwards shift) whose contents are compared to the ones in the t less significant stages of SRI in a comparing circuit MTC, connected in parallel to the t stages of the part A of the register SRI. If the t stages of the lowest order of such MEL register are recognized as already containing the burst b(x) trapped in the part A of the register SRI, then is set, and the computing of (n-q) is started as it will be shown further on. The MTC is connected in parallel to the MEL register, which may be of a substantially similar construction to the register SR2, but with an opposite shifting direction, i.e. from right to left. In all other cases, ; 2 is set equal to (ro-1) in a modulo ro counting device CT2. A shift^from left to right is performed in the MEL register until such burst b(x) is obtained in the t lowest order stages. At each new shift, Tl is decreased of one unit in the counter CT2, so the final value of 2 will be equal to (ro-k), being k the number of steps necessary to have the burst in the desired position. If the CT2 counter reaches a value lower than (ro-N+1), then the counting of I Z is suspended and the presence of errors is signalled, and the word is not decoded because this means that the errors burst is longer than t. If there results / 2>(ro-N+1) the correction is performed calculating a q integer following the relation: q = fl.Al.ro + *2.A2.(2t-l) mod(n) where Al and A2 are positive integers such that Al.(2t-1) + A2.ro = 1 and adding modulo 2 the polinomyal x^ n""c '^.b(x) to the received vector, which is present in the register BF. According to another characteristic of the invention, the exponent (n-q) can be easily calculated starting only by i value, and more precisely, following the relation: that can be implemented in a very simple and cheap way. In Fig. 1, only the COMP block, connected to the output of the CT1 and CT2 counting means and that performs the calculation of (n-q), is schematically shown, because the rest of the operation is done in a known way. The decoding is also performed in conventional way, depending of the kind of coding use (systematic or not systematic) and, therefore, is not shown. The invention is based on the fact that, given a loop back shif register capable to perform the division by the polynomial p(x of degree m and period ro, the shifting of p positions to th right of the m components of the stored remainder polynomial i equivalent to the leftwards shifting of (ro-p) positions of th same m components when the shifting direction of all th connections of the register are inverted. Specially, a shift t the right for p positions in the register SR2 of the component of the polynomial s2(x) is equivalent to a leftwards shift o (ro-p) positions of the components of the polynomial s2(x) in th register MEL, which is substantially similar to the register SR2 except that all shifting senses have been inverted. The leftword shifting of the components of the polynomial s2(x makes so that the state corresponding to / 2=D+1 is reached afte N steps, instead of (ro-N+1) = D+l, as in Chien's device, an having assumed N<ro/2, this means a lower number of cycles. As w pointed out, is r*2>D+l, and N is the maximum number of cycle required to obtain the burst b(x) in the t lower order stages i the register MEL. Specially, the device * according to the invention allows th correction to be performed in (n-b-l)+(2t-l) cycles maximum, e. for the already mentioned F(224 182), in 224 cycles maximum instead of the 130848 cycles expected according to the alread known technique. Fig. 2 shows a further application of the decoder according t the invention, where the SRb register is able to shift in bot senses and, therefore, no extra register to perform the leftwor shifting is needed. The circuit's working manner is alike to wha we wrote with reference to Fig. 1, and is not further described. Even more, in the circuit of Fig. 2 the same references have bee used to describe the same or equivalent parts that the ones i Fig. 1. According to the invention, it is therefore possible to obtain" ' a reduction of the amount of cycles needed to correct errors bursts, a reduction becoming remarkable when, as it practically happens, (n-b) «ro. The invention allows the advantageous use of shortened Fire codes in digital transmission systems, on memory channels, such as, for example, a digital mobile radio system.

Claims: CLAIMS 1. Process for the decoding of a shortened cyclic binary code, able to correct single errors bursts b(x) of given length t or shorter, specially a F(n-b,k-b) shortened Fire code, with 2t-l generator polynomial g(x)=(x +l).p(x), p(x) being a prime polynomial over GF(2) with period ro, satisfying the ro>(n-b), condition, where: the received code word r(x) is buffered in a shift register as a received vector and the syndrome polynomials sl(x) and s2(x) are calculated in (n-b) cycles; the polynomial sl(x) is cyclic shifted a i number of times in a first direction until all zeros are obtained in the (t-1) higher order positions, so to trap the burst b(x) of length t in the lowest order positions; such process is characterized by the fact of: - shifting of the remainder polynomial s2(x), in an opposite direction to the given first one, until the pattern of the t bits of the lower order is the same as the one in the said burst b(x) of length t, and determining a number f " * 2 equal to (ro-h), where h is the number of shifting operations performed; - calculating (n-q) by the relation: q = r*l.A2.ro + p2.Al.(2t-l) mod(n) where Al and A2 are two positive integers such that: Al.(2t-1) + A2.ro =- * 1; - performing the correction adding modulo 2 the polynomial (x n_c ').b(x) to the received vector. 2. Process according to claim 1, characterized by the fact that (n-b)<ro/2. 3. Process according to claim 1 or 2 , characterized by the fact that ro and (2t-l) are prime to each other. 4. Process according to claim 3, characterized by the fact that if Z is minor t .an ro - (n-b) +1, the process is stopped, because the errors burst is greater than t. 5. Process according to claim 4, characterized by the fact that if the pattern consisting of bits in the lowest order 'bf s2(x) is the same as the one in the trapped burst of length t with no need to shift the polynomial s2(x), then / 2 is set equal to zero and (n-q) = 0. 6. Process for the decoding of a shortened cyclic binary code, able to correct single errors bursts b(x) of given length t or ' shorter, specially for an F(n-b,k-b) shortened Fire code 2t-l having a generator polynomial g(x)=(x +l).p(x), p(x) being a prime polynomial over GF(2) and with period ro, in which, by means of cyclic shifting operations, the number P equal to (ro-h) is calculated, with h given by the amount of shifting operations required to obtain the errors burst b(x) in the t less significant positions of the syndrome s2(x) and such process being characterized by the fact of calculating (n-q) by the relation: n-q = / 2 + 1 - ro and to perform the correction by adding modulo 2 the polynomial (x n-c -).b(x) to the received vector. 7. Process according to claim 6, characterized by the fact that ro satisfies the relation: ' ro>(n-b). 8. A decoding device for a shortened cyclic binary code, specially for an F(n-b,k-b) shortened Fire code, having a 2t-l generator polynomial g(x)=(x +l).p(x) , p(x) being prime polynomial over GF(2) and with period ro, satisfying the condition ro>(n-b), and able to correct single errors burst of given length t or shorter, characterized by the fact of including in a combination: a buffer register (BF) of (n-b) stages; a first shift register (SRI), with (2t-l) stages and shifting data in a first direction; a second shift register (SR2), with m stages, shifting in said first direction; said buffer, first and second registers (BF, SRI, SR2) receiving as input the word r(X); first modulo (2t-l) counting means (CT1), able to compute the number of shifting operations performed by said first shift register (SRI); a (TS) device for testing the contents of the (t-1) higher order stages of said first shift register (SRI) and connected to said first counting means (CT1); a third shift register (MEL) with stages and capable of shifting data in a second direction opposite to the previous one; said third register being copnected in parallel to the second register (SR2); a comparing device (MTC), connected between the lowest order t stages of said first (SRI) and third (MEL) shift registers; second modulo ro counting means (CT2), connected to said comparing device (MTC) to compute the number of shifting operations performed by said third shift register (MEL); a computing circuit (COMP), connected to the outputs of said first (CT1) and second (CT2) counting means for computing a number (n-q) able to allow, in the case, the correction of the errors burst in the received word. 9. A decoding device for shortened cyclic binary code, specially for an F(n-b,k-b) shortened code, having a generator 2t-l polynomial g(x)=(x +l).p(x), p(x) being a prime polynomial over GF(2) with period ro, satisfying the ro>(n-b) condition, and able to correct single errors bursts of given length t or shorter, characterized by the fact of including, as a combination: a buffer register (BF) consisting of (n-b) stages; a first shift register (SRI) with (2t-l) stages, shifting data in a first direction; a second shift register (SRb), with m stages and shifting data in said first direction and in the opposite direction; said buffer, first and second registers (BF, SRI, SR2) receiving as input the word r(x); first modulo (2t-l) counting means (CT1), able to compute t -he number of shifting operations performed by said first shift register (SRI); second modulo ro counting means (CT2), able to compute the number of shifting operations performed by said second register (SRb); a device (TS) testing the contents of the (t-1) higher order stages of said first shift register (SRI) and connected in parallel to said first counting means (CT1); a comparing device (MTC)^ connected between the lowest order t stages of said first and second shift registers (S.Rl, SRb), and connected to the second counting means (CT2); a computing circuit (COMP), connected to the outputs of said first (CT1) and second (CT2) counting means for computing an (n-q) number able to allow, in the case, the correction of the errors burst in the received word.

Inventors: TURCO ERMANNO, TURCO, ERMANNO
Applicants: ITALTEL SPA, ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI S.P.A.
Application year: 1990
Main classification: H03M13
IPC codes: H03M13