Dynamic random access memory device

Abstract: A DRAM including a peripheral circuit (3) and a memory cell (2) has a fin structure capacitor (6) overlying and separated from a transfer gate transistor (6) by a silicon nitride layer (18). A conductive layer (13A) which forms an electrode (13) of the capacitor (6) the silicon nitride layer (18A) is removed from above the peripheral circuit (3) before contact windows (31,32) are opened up through insulating layers (16,17) to the surface of a semiconductor element (22) formed in the peripheral circuit (3). This improves the aspect ratio of the contact windows and prevents breakage of subsequently applied wiring.

Description: The present invention relates to a method of producing a semiconductor memory device, more particularly, to a method of producing a dynamic random access memory (hereafter, called a DRAM) having a fin structure type (lamination type) capacitor formed above a substrate. Furthermore, the present invention relates to a DRAM device, more particularly, to a DRAM device comprising a memory cell portion including a plurality of memory cells and a peripheral circuit. Note, the memory cell includes a transfer gate transistor and a fin structure type capacitor formed above the transfer gate transistor, and the peripheral circuit includes a transistor having a contact hole passing through an insulation layer and reaching to a drain or a source region of the transistor. Recently, a DRAM device having a fin structure type capacitor formed above a substrate has been developed. The fin structure type capacitor is suitable for a mass storage DRAM, for example, 4M bits, 16M bits and the like, as a part of the fin structure type capacitor can be formed on a transfer gate transistor. Therefore, recently, various DRAMs having such a fin structure type capacitor have been studied and proposed. In such a DRAM, it is required that a parasitic capacitance of a bit line be lowered to decrease power consumption and stabilize operation. Therefore, it is preferable that the thickness of an insulation layer above the bit line, which is provided in the memory cell portion, is thickly formed. Such a device is disclosed in EP-A-0,191,612. This document shows a semiconductor memory device having stacked capacitor type memory cells, and a method of manufacturing such devices. Nevertheless, when the insulation layer is thickly formed, an aspect ratio of the contact hole formed in the peripheral circuit becomes large. Therefore, coverage of an aluminium wiring layer becomes worse, and the aluminium wiring layer may be snapped or incomplete as will be described in more detail later. A concept of decreasing the thickness of the insulation layer in the peripheral circuit without decreasing the thickness of the insulation layer in the memory cell portion has been proposed in Unexamined Japanese Patent Publication (Kokai) No. 02-58866. According to a first aspect of this invention there is provided a method of producing a semiconductor memory device wherein the method comprises the steps of: forming a first transistor and a second transistor on the same semiconductor substrate, the first transistor constituting a memory cell and the second transistor constituting a peripheral circuit other than the memory cell; forming a first insulation layer onto the first transistor and the second transistor; forming an intermediate conductive layer over the substrate, the intermediate conductive layer being patterned in the shape of a bit line and electrically connected to the first transistor; forming a second insulation layer extending over the substrate; forming a conductive layer onto the second insulation layer the conductive layer constituting a cell plate of a capacitor; removing the conductive layer and the second insulation layer from above the second transistor; and, making a contact hole passing through the first insulation layer at a location where the second insulation layer and the conductive layer have been removed, and reaching to a surface of the second transistor. Thus, this invention provides a DRAM and producing method thereof for decreasing power consumption and stabilising the operation of the memory cell by decreasing the parasitic capacitance of a bit line, and improving the step coverage of the wiring by improving the aspect ratio and the shape of a contact hole in a peripheral circuit. The memory cell is constituted by the first transistor and a capacitor formed on the second insulation layer and above the first transistor. The second insulation layer is used to form the capacitor above the first transistor. The conductive layer may be constituted by a polycrystal silicon layer, the second insulation layer may be constituted by a Si 3 N 4 film layer, and the insulation film layers except the second layer may be constituted by SiO 2 film layers. The conductive layer of polycrystal silicon and second insulation layer of Si 3 N 4 formed on the second transistor may be removed by an etching method using mixed gas. The mixed gas may be made of sulfur hexafluoride and freon type gas. The method of producing a semiconductor memory device may further comprise a step of forming another insulation layer between the first insulation layer and the second insulation layer. According to a second aspect of the present invention, there is provided a semiconductor memory device having a memory cell portion including a plurality of memory cells and a peripheral circuit, wherein the device comprises: a first transistor, formed on a semiconductor substrate, constituting the memory cell; a second transistor, formed on the semiconductor substrate, constituting the peripheral circuit; a first insulation layer, formed onto the first transistor and the second transistor; a bit line formed on the first insulation layer and electrically connected to the first transistor; a second insulation layer, formed onto the first insulation film layer only in the area of the memory cell portion; a cell plate electrode of memory capacitor formed onto the second insulation layer only in the area of the memory cell portion, the cell plate electrode being isolated from the bit line by the second insulation layer; and a contact hole, provided on the second transistor, for constructing the peripheral circuit by wiring, the contact hole passing through at least the first insulation layer and reaching to a surface of the second transistor, without passing through the second insulation layer. The semiconductor memory device comprises a capacitor formed onto the second insulation layer and above the first transistor for constituting the memory cell; the capacitor may comprise a first polycrystal silicon layer for forming a storage electrode, a capacitor insulation film covering the storage electrode, and a second polycrystal silicon layer of the conductive layer. The capacitor may comprise a plurality of storage electrodes. The semiconductor memory device may further comprise a third insulation layer between the first insulation layer and the second insulation layer. The first and third insulation layers may be constituted by SiO 2 layers, and the second insulation layer may be constituted by a Si 3 N 4 layer. Examples of the present invention will now be described and contrasted with the prior art with reference to the accompanying drawings, in which:- Figures 1A to 1H are sectional diagrams for explaining a method of producing a DRAM of an example according to the prior art; Figures 2A to 2H are sectional diagrams for explaining in detail the producing steps between the steps of Fig. 1G and 1H; Figures 3A to 3H are sectional diagrams for explaining a method of production of a DRAM of an embodiment according to the present invention; Figures 4A to 4H are sectional diagrams for explaining in detail the production steps between the steps of Fig. 3G and 3H; Figures 5A to 5C are diagrams indicating another embodiment of the DRAM according to the present invention; Figure 6 is a circuit diagram indicating a typical memory cell of the DRAM applying the present invention; and Figure 7 is a block diagram indicating a typical DRAM chip applying the present invention. First, a DRAM device and a producing method thereof according to the prior art will be explained, with reference to Figs. 1A to 2H. Figures 1A to 1H are sectional diagrams for explaining a method of producing a DRAM of an example according to the prior art. Recently, a DRAM device having a fin structure type (lamination type) capacitor formed above a substrate is provided by shown in Fig. 1H which indicates a sectional view of an important portion in the DRAM device. In Fig. 1H, reference numeral 1 denotes a p-type silicon substrate as a base substance, 2 denotes a memory cell portion including a plurality of memory cells (DRAM-cells) MC, and 3 denotes a peripheral circuit (portion). Further, in the DRAM-cell portion 2, reference numeral 4 denotes a transfer gate transistor, 5 denotes a bit line, and 6 denotes a fin structure type capacitor. Note, the memory cell MC is constituted by the transfer gate transistor 4 which is constituted by an n-channel type MOS field effect transistor (nMOS FET) and the fin structure type capacitor 6 formed above the transfer gate transistor 4. In the transfer gate transistor 4 of the nMOS FET, reference numerals 7 and 8 denote n + diffusion layers, 9 denotes a gate insulation film of silicon dioxide (SiO 2 ), and 10 denotes a word line of polycrystal silicon. Furthermore, the bit line 5 is also made of polycrystal silicon, and connected to one n + diffusion layer 7 of the transfer gate transistor 4. The fin structure type capacitor 6 is constituted by a storage electrode 11 of polycrystal silicon, a capacitor insulation film 12 of SiO 2 formed over the storage electrode 11, and cell plate 13 of polycrystal silicon. The storage electrode 11 is connected to the other n + diffusion layer 8 of the transfer gate transistor 4. Furthermore, reference numeral 14 denotes a word line, 15 denotes a field oxide film, 16 and 17 denote SiO 2 filmlayers, 18 denotes a silicon nitride (Si 3 N 4 ) film layer, 19 denotes a phospho-silicate glass (PSG) layer, and 20 and 21 denote aluminium wiring layers. In the peripheral circuit 3, reference numeral 22 denotes an nMOS FET, 23 and 24 denote a drain region and source region made of n + diffusion layers, 25 denotes gate insulation film of SiO 2 , and 26 denotes a gate electrode of the nMOS FET 22 made of polycrystal silicon. Furthermore, reference numerals 27 and 28 denote aluminium wiring layers, and these aluminium wiring layers are connected to the drain region 23 and the source region 24 of the nMOS FET 22, respectively. The DRAM device described in the above is produced by the following steps, as shown in Figs. 1A to 1H. First, as shown in Fig. 1A, a p-type silicon substrate 1 is prepared, and a transfer gate transistor 4 and an nMOS FET 22 are formed on the substrate 1 after forming a field oxide film 15 therein. Next, as shown in Fig. 1B, a SiO 2 film layer 16, a bit line 5, a SiO 2 film layer 17, a Si 3 N 4 film layer 18 and a SiO 2 film layer 29 are formed in order. Note, for example, a thickness of the SiO 2 film layer 16 is determined to 0.10µm, a thickness of the bit line 5 is determined to 0.10µm, a thickness of the SiO 2 film layer 17 is determined to 0.05µm, a thickness of the Si 3 N 4 film layer 18 is determined to 0.15µm, and a thickness of the SiO 2 film layer 29 is determined to 0.10µm. Furthermore, as shown in Fig. 1C, a hole 30 having an opening width of 0.50 µm is formed on an n + diffusion layer 8 such that the hole 30 is passed through the SiO 2 film layers 16 and 17, the Si 3 N 4 film layer 18, and the SiO 2 film layer 29. Next, as shown in Fig. 1D, a storage electrode 11 of polycrystal silicon having a thickness of 0.10µm is formed. This storage electrode 11 is connected to the n + diffusion layer 8 through the hole 30. Note, the storage electrode 11 is formed as fin shape portions 11A and 11B on the SiO 2 film layer 29. Furthermore, as shown in Fig. 1E, the SiO 2 film layer 29 is removed by an etching method using a solution which includes hydrofluoric acid (HF), and then, a capacitor insulation film 12 of SiO 2 having, for example, a thickness of 100Å, is formed over a bare surface of the storage electrode 11 by a thermal oxidation method. Further, as shown in Fig. 1F, a cell plate 13 of polycrystal silicon having, for example, a thickness of 0.10∼0.15µm is formed over all of the surface. Namely, the polycrystal silicon layer 13 for forming the cell plate is formed over the surfaces in both the DRAM-cell portion 2 and the peripheral circuit 3. Furthermore, as shown in Fig. 1G, a polycrystal silicon layer 13A, which corresponds to the cell plate 13 in the area of the peripheral circuit 3, is removed by an etching method. Namely, in the peripheral circuit 3, the Si 3 N 4 film layer 18 appears as the top surface. Finally, as shown in Fig. 1H, a PSG film layer 19 having a thickness of 0.40 µm is formed over all of the surface, and then, contact holes 31 and 32 each having an opening width of 0.50 µm are formed on a drain region 23 and a source region 24 of the nMOS FET 22 in the peripheral circuit 3. Aluminium wirings 27 and 28 are formed through those contact holes 31 and 32 to connect the drain region 23 and the source region 24, and the aluminium wirings 20 and 21 of the the DRAM cell portion 2 are formed at the same time. Note, in this case, the problems, which will be described below with reference to Figs. 2A to 2H, arise. Figures 2A to 2H are sectional diagrams for explaining in detail the production steps between the steps of Fig. 1G and 1H. Note, Fig. 2A to 2H only indicate a portion of the contact hole 31 (or 32) in the peripheral circuit 3. First, as shown in Figs. 2A and 2B, a PSG layer 19 is formed onto the top surface of the Si 3 N 4 film layer 18, and a resist layer 40 (for example, a novolak type positive resist) is formed onto the PSG layer 19. Next, as shown in Fig. 2C, the resist layer 40 is exposed as a pattern corresponding to the contact hole 31 by using, for example, ultraviolet light UV and a mask 50 consisting of a quartz glass 51 and specific patterns 52 of chromium formed onto the quartz glass 51. Therefore, a portion 40a in the resist layer 40 corresponding to the contact hole 31 is exposed, and the other portions 40b are not exposed. Furthermore, as shown in Fig. 2D, the exposed portion 40a is removed by using an alkali solution, and then a hole 41 is formed in the resist layer 40. Next, as shown in Fig. 2E, the portions of the PSG layer 19, the Si 3 N 4 film layer 18, and the SiO 2 film layers 17 and 16 corresponding to the hole 41 in the resist layer 40 are removed by an RIE (Reactive Ion Etching) method using CHF 3 /He, so that a hole portion 42 (31, 32) is formed. Furthermore, as shown in Fig. 2F, the remaining resist layer 40 corresponding to the unexposed portions 40b is removed by using an O 2 -plasma method or an acid solution (for example, H 2 SO 4 /H 2 O,). Note, in this case, the resist layer 40 can be removed, and the surface 42a of the drain region 23 (or the source region 24) of n + diffusion layer becomes to be oxidized as SiO 2 . Namely, the surface 42a of the drain region 23, which may be called a native oxide, is produced at the step of removing the remaining resist layer 40. Note, the surface 42a made of SiO 2 is to be a barrier of an electrical connection when connecting the drain region 23 (or the source region 24) to construct the peripheral circuit by using aluminium wiring layer 27 (28), and thus, this insulation surface 42a must be removed. Consequently, as shown in Fig. 2G, the surface 42a of SiO 2 is removed by using HF. Note, in this case, the surface of an inside portion of the hole 42 is isotropically removed or etched, and the Si 3 N 4 film layer 18 is not etched to the same degree of that of the PSG layer 19 or the SiO 2 film layers 17 and 16. Namely, as clearly indicated in Fig. 2G, a degree of etching of the Si 3 N 4 film layer 18 is smaller than that of the PSG layer 19 or the SiO 2 film layers 17 and 16, and thus end portions 18a of the Si 3 N 4 film layer 18, which may be called overhang portions, protrude into the hole 42. Therefore, as shown in Fig. 2H, when sputtering aluminium for forming an aluminium wiring 27 (28), the aluminium wiring 27 may be cut at the end portions 18a of the Si 3 N 4 film layer 18, and an aluminium 27b (28b) at the bottom portion in the hole 42 can not be connected to aluminium wiring 27a (28a) at the surface portion on the PSG layer 19. As described above, a conventional DRAM having a fin structure type capacitor 6 can be obtained. Incidentally, in such a DRAM, it is required that a parasitic capacitance of the bit line 5 be made small to decrease power consumption and stabilize operation. Therefore, it is preferable that the thickness of an insulation layer above the bit line 5, that is, the thickness of the SiO 2 film layer 17 and the Si 3 N 4 film 18 layer are thickly formed. Neverthless, when the SiO 2 film layer 17 and the Si 3 N 4 film layer 18 are thickly formed, an aspect ratio (a depth of a hole / an opening width) of the contact hole 31 and 32 formed in the peripheral circuit 3 becomes large. Therefore, coverage of the aluminium wiring layers 27 and 28 becomes poor, and the aluminium wiring layers 27 and 28 may be snapped. Note, in the conventional example as shown in Figs. 1A to 1H, when assuming the thickness of the SiO 2 films 16 and 17 to be 0.10µm and 0.05µm, the thickness of the Si 3 N 4 film layer 18 to be 0.15µm, the thickness of the PSG film layer 19 to be 0.40µm, and the opening width of the contact holes 31 and 32 to be 0.50µm respectively, then the aspect ratio of each of the contact holes 31 and 32 is determined at 1.4 by the following formula. 0.10 + 0.05 + 0.15 + 0.40 0.5 = 1.4 This aspect ratio of 1.4 is a considerably large value, and in the contact holes 31 and 32 having the opening width of 0.50µm, the aluminium wirings 27 and 28 may be frequently snapped. As described with reference to Figs. 1A to 1H, when the SiO 2 film layer 17 and the Si 3 N 4 film layer 18 above the bit line 5 are thickly formed to decrease the power consumption and stabilize the cell operation, the aspect ratios of the contact holes 31 and 32 become large, and an inferior wiring coverage step is caused. Conversely, when the SiO 2 film layer 17 and the Si 3 N 4 film layer 18 above the bit line 5 are thinly formed, the aspect ratios of the contact holes 31 and 32 can be small, but the parasitic capacitance of the bit line 5 becomes large, so that the decrease of the power consumption and stabilization of the operation can not be realized. That is, in the conventional method of producing the semiconductor memory device as shown in Figs. 1A to 1H, one requirement of decreasing the power consumption and stabilizing the operation of the cell by decreasing the parasitic capacitance of the bit line 5, and the other requirement of improving the step coverage of the wiring by decreasing the aspect ratios of the contact holes 31 and 32 can not be simultaneously satisfied. Note, in this case, it can be considered to decrease the aspect ratio by enlarging the opening width of the contact hole. However, in enlarging the opening width of the contact hole the sizes of the drain region 23 and the source region 24 of the nMOS FET 22 must be enlarged so that development of the mass storage semiconductor memory device is prevented. Furthermore, it can be also considered to decrease the aspect ratio by decreasing the thickness of the PSG film layer 19. However, in decreasing the thickness of the PSG film layer 19, the parasitic capacitances of the aluminium wiring layers 20, 21, 27, and 28 are increased so that high speed operation cannot be realized and the insulation characteristic is decreased. Additionally, as described above with reference to Figs. 2A to 2H, when removing the surface 42a of SiO 2 in the hole 42, a degree of etching of the Si 3 N 4 film layer 18 is quite different from that of the SiO 2 film layers 17 and 16, and thus end portions 18a of the Si 3 N 4 film layer 18 protrude into the hole 42. Therefore, the aluminium wiring 27 (28) may be cut at the end portions 18a of the Si 3 N 4 film layer 18. Next, a principle of the present invention will be explained. In a method of producing a semiconductor memory device according to the present invention, with reference to Figs. 3A to 7, first, a first insulation film layer 16 is formed onto a first semiconductor element 4 and a second semiconductor element 22. Note, the first semiconductor element 4 is used to constitute a memory cell MC formed on a semiconductor substrate 1, and the second semiconductor element 22 is used to constitute a peripheral circuit 3 except the memory cell MC formed on the semiconductor substrate 1. Next, a first conductive layer 5 is formed onto the first insulation film layer 16, and the first conductive layer 5 is patterned in the shape of a bit line and is electrically connected to the first semiconductor element 4. Furthermore, a second insulation film layer 18 extending onto the first insulation film layer 16 and the first conductive layer 5 is formed. Next, a second conductive layer 13 is formed onto the second insulation film layer 18. Note, the second conductive layer 13 is used as a cell plate of a capacitor element 6 in a memory cell portion 2. Furthermore, at least the second conductive layer 13 (13A) and the second insulation film layer 18 formed on the second semiconductor element 22 are removed in order. Additionally, contact holes 31, 32 are formed. Note, the contact holes 31, 32 are formed to pass through at least the first insulation film layer 16 without passing through the second insulation film layer 18, and are formed to reach to a surface of the second semiconductor element 22. In the present invention, at least the second insulation film layer 18A formed above the second semiconductor element 22 in all the second insulation film layer 18 is removed, and the opening hole passing through the first insulation film layer 16 and reaching to a surface of the second semiconductor element 22 can be decreased, or aspect ratios of contact holes 31, 32 in peripheral circuit 3 can be small. Furthermore, the aspect ratios of the contact holes 31, 32 in the peripheral circuit 3 are not affected by the thickness of the second insulation film layer 18 for the same reasons, and the thickness of a memory cell portion 2, or the thickness of the second insulation film layer 18 at the memory cell portion 2 can be independently thickened so that a parasitic capacitance of the bit line 5 can be decreased. Additionally, when removing the surface 42a of SiO 2 in the contact holes 31, 32, protruded portions in the contact holes 31, 32 are not produced as the second insulation film layer 18 is already removed. Namely, the shape of the contact holes 31, 32 are improved, and thus aluminium wiring 27 (28) is not cut and an electrical connection of the aluminium wiring 27 (28) is improved. Below, the preferred embodiments of a DRAM device and a producing method thereof according to the present invention will be explained with reference to Figs. 3A to 7. Figures 3A to 3H are sectional diagrams for explaining a method of producing a DRAM of an embodiment according to the present invention. Note, in Figs. 3A to 3H, reference numerals corresponding to those shown in Figs. 1A to 1H indicate the same portions. In the present embodiment, firstly, as shown in Figs. 3A to 3F, the same steps as shown in Figs. 1A to 1F are carried out. Namely, first, as shown in Fig. 3A, a p-type silicon substrate 1 is prepared, and a transfer gate transistor 4 and an nMOS FET 22 are formed on the substrate 1 after forming a field oxide film 15 therein. Next, as shown in Fig. 3B, a SiO 2 film layer 16, a bit line 5, a SiO 2 film layer 17, a Si 3 N 4 film layer 18 and a SiO 2 film layer 29 are orderly formed. Note, for example, a thickness of the SiO 2 film layer 16 is determined to 0.10µm, a thickness of the bit line 5 is determined to 0.10µm, a thickness of the SiO 2 film layer 17 is determined to 0.05µm, a thickness of the Si 3 N 4 film layer 18 is determined to 0.15µm, and a thickness of the SiO 2 film layer 29 is determined to 0.10µm. Note, in the present embodiment, the SiO 2 film layer 16 corresponds to the first insulation film layer, and the Si 3 N 4 film layer 18 and the SiO 2 film layer 17 correspond to the second and third insulation film layer. Furthermore, as shown in Fig. 3C, a hole 30 having an opening width of 0.50µm is formed on an n + diffusion layer 8 such that the hole 30 is passed through the SiO 2 film layers 16 and 17, the Si 3 N 4 film layer 18, and the SiO 2 film layer 29. Next, as shown in Fig. 3D, a storage electrode 11 of polycrystal silicon having a thickness of 0.10µm is formed. This storage electrode 11 is connected to the n + diffusion layer 8 through the hole 30. Note, the storage electrode 11 is shaped as fin portions 11A and 11B formed on the SiO 2 film 29. Furthermore, as shown in Fig. 3E, the SiO 2 film layer 29 is removed by an etching method using a solution which includes hydrofluoric acid (HF), and then a capacitor insulation film 12 of SiO 2 having, for example, a thickness of 100Å, is formed over a bare surface of the storage electrode 11 by a thermal oxidation method. Further, as shown in Fig. 3F, a cell plate 13 of polycrystal silicon having, for example, a thickness of 0.10∼0.15µm is formed over all of the surface. The above steps until this are the same processes of the conventional example as shown in Figs. 1A to 1F. Note, in the present embodiment, a mixed gas made of sulfur hexafluoride (SF 6 ) and freon type gas, for example, freon (carbon tetrafluoride: CF 4 ), is used, and as shown in Fig. 3G, a polycrystal silicon layer 13A and a Si 3 N 4 film layer 18A, which correspond to the area of the peripheral circuit 3 in the cell plate 13 and the Si 3 N 4 film layer 18 formed all over the surface, are removed by an etching method. Namely, in the peripheral circuit 3, both polycrystal silicon layer 13A and the Si 3 N 4 film layer 18 are removed, and the SiO 2 insulation film layer 17 appears as the top surface. Finally, as shown in Fig. 3H, a PSG film layer 19 having a thickness of 0.40 µm is formed over all of the surface, and then, contact holes 31 and 32 are formed on a drain region 23 and a source region 24 of the nMOS FET 22 in the peripheral circuit 3. Aluminium wirings 27 and 28 are formed through those contact holes 31 and 32 to connect the drain region 23 and the source region 24, and the aluminium wirings 20 and 21 of the the DRAM cell portion 2 are formed at the same time. Figures 4A to 4H are sectional diagrams for explaining in detail the production steps between the steps of Figs. 3G and 3H. Note, Fig. 4A to 4H only indicate a portion of the contact hole 31 (or 32) in the peripheral circuit 3. Note also, in comparison with the prior example shown in Fig. 2G, the embodiment as shown in Fig. 4G does not include the Si 3 N 4 film layer 18 in the peripheral circuit 3. First, as shown in Figs. 4A and 4B, a PSG layer 19 is formed onto the top surface of the SiO 2 film layers 17, and a resist layer 40 (for example, a novolak type positive resist) is formed onto the PSG layer 19. Next, as shown in Fig. 4C, the resist layer 40 is exposed as a pattern corresponding to the contact hole 31 by using, for example, ultraviolet light UV and a mask 50 consisting of a quartz glass 51 and specific patterns 52 of chromium formed onto the quartz glass 51. Therefore, a portion 40a in the resist layer 40 corresponding to the contact hole 31 is exposed, and the other portions 40b are not exposed. Furthermore, as shown in Fig. 4D, the exposed portion 40a is removed by using an alkali solution, and then a hole 41 is formed in the resist layer 40. Next, as shown in Fig. 4E, the portions of the PSG layer 19 and the SiO 2 film layers 17 and 16 corresponding to the hole 41 in the resist layer 40 are removed by an RIE (Reactive Ion Etching) method using CHF 3 /He, so that a hole portion 42 (31, 32) is formed. Furthermore, as shown in Fig. 4F, the remaining resist layer 40 corresponding to the unexposed portions 40b is removed by using an O 2 -plasma method or an acid solution (for example, H 2 SO 4 /H 2 O 2 ). Note, in this case, the resist layer 40 can be removed, and the surface 42a of the drain region 23 (or the source region 24) of n + diffusion layer becomes oxidized as SiO 2 . Namely, the surface 42a of the drain region 23, which may be called a native oxide, is produced by the step of removing the remaining resist layer 40. Note, the surface 42a made of SiO 2 is to be a barrier of an electrical connection when connecting the drain region 23 (or the source region 24) to construct the peripheral circuit by using aluminium wiring layer 27 (28), and thus, this insulation surface 42a must be removed. Consequently, as shown in Fig. 4G, the surface 42a made of SiO 2 is removed by using HF. Note, in this case, the surface of an inside portion of the hole 42 is isotropically removed or etched, but the Si 3 N 4 film layer 18 is already removed and the hole 42 is constituted by the PSG layer 19 and the SiO 2 film layers 17 and 16. Note, a degree of etching of the PSG layer 19 is a little larger than (or almost the same as) that of the SiO 2 film layers 17 and 16, and thus the overhang portions are not produced. Namely, the opening width (19a) of the PSG layer 19 is almost equal to (or a little larger than) that (16a, 17a) of the SiO 2 film layers 17 and 16, and no end portions protrude into the hole 42. That is, the shape of the hole 42 (the contact hole 31, 32) is improved. Therefore, as shown in Fig. 4H, when sputtering aluminium for forming an aluminium wiring 27 (28), the aluminium wiring 27 is not cut and is securely connected to the surface of the drain region 23 of the n + diffusion layer. Therefore, a DRAM having a fin structure type capacitor 6 formed above the p-type silicon substrate 1 can be obtained. In the present embodiment, a parasitic capacitance of the bit line 5 can be decreased, the power consumption can be decreased and the operation of the cell can be stabilized, because the thicknesses of the SiO 2 film layer 17 and the Si 3 N 4 film layer 18 are determined to 0.05 µm and 0.15µm and the total thickness of the film layers is determined to 0.20 µm. Furthermore, in the present embodiment, as shown in Fig. 3G, the Si 3 N 4 film layer 18A corresponds to the area of the peripheral circuit 3 in the Si 3 N 4 film layer 18 formed over all of the surface, does not exist, so that the aspect ratios of the contact holes 31, 32 can be decreased and the coverage of the aluminium wiring layers 27 and 28 can be improved. Additionally, as shown in Figs. 4G and 4H, the hole 42 is constituted by the PSG layer 19 and the SiO 2 film layers 17, 16 without including the Si 3 N 4 film layer 18, the shape of the contact holes 31, 32 is improved, and thus the aluminium wirings 27, 28 are not cut and are securely connected to the surface of the drain region 23. Concretely, in the present embodiment, the thicknesses of the SiO 2 film layers 16 and 17 are determined to 0.10µm and 0.05µm, the thickness of the PSG film layer 19 is determined to 0.40µm, and the opening widths of the contact holes 31, 32 are determined to 0.50 µm, which are the same values as the conventional ones as shown in Figs. 1A to 1H, and the aspect ratios of the contact holes 31, 32 can be determined at 1.1. 0.10 + 0.05 + 0.40 0.5 = 1.1 This aspect ratio of 1.1 is smaller than that of the conventional one as shown in Figs. 1A to 1H, and the coverage of the aluminium wiring layers 27 and 28 can be improved. As described above, according to the present embodiment, one requirement of decreasing the power consumption and stabilizing the operation of the cell by decreasing the parasitic capacitance of the bit line 5, and the other requirement of improving the step coverage of the wiring by decreasing the aspect ratios of the contact holes 31 and 32 can be simultaneously satisfied. Furthermore, in the present embodiment, a process of removing the Si 3 N 4 film layer 18A and a process of removing the cell plate 13A are carried out by the same process, and thus an additional process is not necessary in comparison with the conventional example as shown in Figs. 1A to 1H. Note, the above described embodiment is explained for a case when the thickness of the Si 3 N 4 film layer 18 is determined to 0.15 µm, but the aspect ratios of the contact holes 31 and 32 at the peripheral circuit 3 are not influenced by the thickness of the Si 3 N 4 film layer 18. Consequently, the thickness of the Si 3 N 4 film layer 18 can be determined more thickly than 0.15µm to decrease the parasitic capacitance of the bit line 5, so that the consumption power can be further decreased and the operation of the cell can be more stabilized. Additionally, in the above embodiment, the first insulation film layer of the SiO 2 film layer 16, the second insulation film layer of the SiO 2 film 17 and the Si 3 N 4 film 18, are described, but the SiO 2 film layer 17 is not always required. When omitting the SiO 2 film layer 17, the aspect ratio can be further decreased. Namely, in the above example, the aspect ratio can be determined at 1.0. 0.10 + 0.40 0.5 = 1.0 Figures 5A to 5C are diagrams indicating another embodiment of the DRAM according to the present invention. As shown in Fig. 5A, in this embodiment, a storage electrode 11 is constituted by three stratiform polycrystal silicon layers (fin portions) 11a, 11b, and 11c. Note, capacitor insulation films 12a, 12b, and 12c made of SiO 2 are formed over the surfaces of these fin portions 11a, 11b, and 11c. Therefore, a capacitance of the capacitor 6, which is constituted by the storage electrode 11 (11a, 11b, and 11c), the capacitor insulation film 12 (12a, 12b, and 12c) and the cell plate 13, can be increased, and thus a large capacitor area can be obtained. As shown in Figs. 5B and 5C, bit lines are formed before the storage capacitor, so other patterning after the storage electrode 11 is not necessary, and thus good scalability can be obtained. Furthermore, bit line to bit line coupling can be reduced because cell plate 13 acts as a shield plate. Note, in this embodiment, a Si 3 N 4 film layer 18 is used to form the fin structure type capacitor (6) above the transfer gate transistor (4). Additionally, these merits are also provided in the DRAM device as shown in Fig. 3H. Figure 6 is a circuit diagram indicating a typical memory cell of the DRAM applying the present invention. In the above descriptions, a memory cell portion 2 comprises a plurality of bit lines 5, word lines 10, and memory cells MC provided at the cross-connection portions between each of the bit lines 5 and the word lines 10. The memory cell MC is constituted by a transfer gate transistor 4 and a capacitor 6. A drain (source) of the transistor 4 is connected to a bit line 5, a gate of the transistor 4 is connected to a word line 10, and a source (drain) of the transistor 4 is connected to one end of the capacitor 6. The other end of the capacitor 6 is constituted by a cell plate 13 applied a cell plate bias voltage. Note, the capacitor 6 is constituted as a fin structure type capacitor formed above the transfer gate transistor 4, as shown in Figs. 3H and 5A. Figure 7 is a block diagram indicating a typical DRAM chip applying the present invention. As shown in Fig. 7, in a DRAM chip 71, a memory cell portion 2 is constituted by a plurality of bit lines 5, word lines 10, and memory cells MC, and a peripheral circuit is constituted by a row decoder 72, a sense amplifier 73, a column decoder 74, and a logic circuit 75. Note, the peripheral circuits of the row decoder 72 and the like is constructed by a plurality of transistors 22 in the peripheral circuit 3, as shown in Fig. 3H. As described above, in the present invention, a polycrystal silicon layer is used to a cell plate of a capacitor in a memory cell portion, and a Si 3 N 4 film layer is used to form the capacitor above a transfer gate transistor in a memory cell. Both a polycrystal silicon layer and Si 3 N 4 film layer formed above a transistor of a peripheral circuit are removed simultaneously by an etching method. Therefore, an aspect ratio and a shape of a contact hole in the peripheral circuit are improved, and thus the step coverage of the wiring in the peripheral circuit can be improved. Namely, a coverage of the aluminium wiring layer improves, and the aluminium wiring layer is not snapped.

Claims: A method of producing a semiconductor memory device wherein the method comprises the steps of: forming a first transistor (4) and a second transistor (22) on the same semiconductor substrate (1), the first transistor (4) constituting a memory cell (MC), and the second transistor (22) constituting a peripheral circuit (3) other than the memory cell (MC); forming a first insulation layer (16) onto the first transistor (4) and the second transistor (22); forming an intermediate conductive layer (5) over the substrate (1), the intermediate conductive layer (5) being patterned in the shape of a bit line and electrically connected to the first transistor (4); forming a second insulation layer (18, 18A) extending over the substrate (1); forming a conductive layer (13,13A) onto the second insulation layer (18, 18A), the conductive layer (13) constituting a cell plate electrode (13) of a memory capacitor (6); removing the conductive layer (13A) and the second insulation layer (18A) from above the second transistor (22); and, making a contact hole (31, 32) passing through the first insulation layer (16) at a location where the second insulation layer (18A) and the conductive layer (13A) have been removed, and reaching to a surface of the second transistor (22). A method according to claim 1, wherein the memory cell (MC) is constituted by the first transistor (4) and the memory capacitor (6) formed onto the second insulation layer (18) and above the first transistor (4). A method according to any of the preceding claims, wherein a storage electrode (11), a dielectric layer (12), and the cell plate electrode (13) form the memory capacitor (6) above the first semiconductor transistor (4). A method according to any of the preceding claims, wherein the conductive layer (13A) and the second insulating layer (18A) are both removed by using the same resist as a mask. A method according to any of claims 2 to 4, wherein the conductive layer (13A) and the second insulating layer (18A) are removed in a single etching step. A method according to claims 2 or 3, wherein the memory capacitor (6) is a fin structure capacitor. A method according to any of the preceding claims, wherein the conductive layer (13, 13A) is constituted by a polycrystal silicon layer, the second insulation layer (18, 18A) is constituted by a Si 3 N 4 film layer, and the first insulation layer (16) is constituted by a SiO 2 film layer. A method according to claim 7, wherein the conductive layer (13; 13A) of polycrystal silicon and the second insulation layer (18, 18A) of Si 3 N 4 formed on the second transistor (22) are removed by an etching method using a mixed gas. A method according to claim 8, wherein the mixed gas is made of sulfur hexafluoride (SF 6 ) and a freon. A method according to any of the preceding claims, wherein the method further comprises a step of forming another insulation layer (17) between the first insulation layer (16) and the second insulation layer (18). A semiconductor memory device having a memory cell portion (2) including a plurality of memory cells (MC) and a peripheral circuit (3), wherein the device comprises: a first transistor (4), formed on a semiconductor substrate (1), constituting the memory cell (MC); a second transistor (22), formed on the semiconductor substrate (1), constituting the peripheral circuit (3); a first insulation layer (16), formed onto the first transistor (4) and the second transistor (22); a bit line (5) formed on the first insulation layer (16) and electrically connected to the first transistor (4); a second insulation layer (18), formed onto the first insulation film layer (16) only in the area of the memory cell portion (2); a cell plate electrode (13) of a memory capacitor (6) formed onto the second insulation layer (18) only in the area of the memory cell portion (2), the cell plate electrode being isolated from the bit line by the second insulation layer (18); and a contact hole (31, 32), provided on the second transistor (22), for constructing a peripheral circuit wiring, the contact hole (31, 32) passing through at least the first insulation layer (16) and reaching to a surface of the second transistor (22), without passing through the second insulation layer (18). A semiconductor memory device according to claim 11, wherein the memory capacitor (6) comprises a first conductive layer (11) forming a storage electrode (11A, 11B), a capacitor insulation film (12) covering the storage electrode (11A, 11B), and a second conductive layer (13) constituting said cell plate electrode (13). A semiconductor memory device according to claim 12, wherein the first conductive layer (11) and the second conductive layer (13) are polycrystal silicon layers. A semiconductor memory device according to claim 13, wherein the memory capacitor (6) comprises a plurality of storage electrodes (11a, 11b, 11c). A semiconductor memory device according to any of claims 11 to 14, wherein the device further comprises a third insulation layer (17) between the first insulation layer (16) and the second insulation layer (18). A semiconductor memory device according to any of claims 11 to 15, wherein the first and third insulation layers (16, 17) are constituted by SiO 2 film layers, and the second insulation layer (18) is constituted by a Si 3 N 4 film layer. A semiconductor memory device according to any of claims 11 to 16, wherein the pattern of the cell plate electrode (13) is substantially identical to the pattern of the second insulation layer (18).

Inventors: IKEMASU SHINICHIROU, IKEMASU, SHINICHIROU, IKEMASU, SHINICHIROU, 203 COPO HICHIFUKUDAIICHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L27