High speed numerical processor

Abstract: Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48)(50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

Description: RELATED APPLICATIONS "FLOATING POINT/INTEGER PROCESSOR WITH DIVIDE AND SQUARE ROOT FUNCTIONS", by Henry Merrick Darley et al., filed January 29, 1988, Serial No. 150,363, Attorney's Docket No. TI-13241.(European Patent Application No.0 326 415. TECHNICAL FIELD OF THE INVENTION This invention relates in general to information handling systems, and more particularly to a processor for performing divide and square root calculations at high speeds. BACKGROUND OF THE INVENTION High speed arithmetic computation is a critical design factor in many information handling systems such as computers, signal processors and process controllers. These systems increasingly rely on large scale integrated circuits employing highly parallel designs to provide high speed calculations. While devices that perform multiplication using parallel techniques are widely available, devices for performing the division and square root functions are generally serial in nature and therefore operate at slower speeds. Calculating division and square roots, unlike addition, subtraction or multiplication, is an iterative process. An apparatus or circuit for performing the division or square root function will take a number of steps or clock cycles to arrive at a quotient or root value. The execution time and accuracy of an information handling system can be greatly affected by the technique employed for performing the division and square root functions. One known technique involves using a convergence algorithm. In division, a convergence algorithm treats the dividend and divisor as a fraction. If repeated multiplication of the divisor (i.e. the denominator of the fraction) by some function of the divisor forces the denominator to one in the limit, then repeated multiplication of the dividend by the same function will force it to the quotient in the limit. In a square root calculation, the number for which the square root is to be determined is treated as a fraction where the number is the same for the numerator and denominator. Repeated multiplication of the fraction by some function forces the denominator to one and the numerator to the square root in the limit. Division and square roots, in information handling systems, can be performed by employing high speed multipliers in conjunction with other circuitry operating in accord with a convergence algorithm. A typical convergence algorithm requires repeated multiplication steps to arrive at a result. As a consequence, prior art high speed multipliers require at least three clock cycles for each duration of the convergence algorithm. Hence, division and square root calculations require a substantial amount of time relative to other calculations. Because of the desire for even faster information handling systems, a need has arisen to provide a processor which is capable of high speed division and square root calculations. An article entitled "A suggestion for a fast multiplier" (IEEE Transactions on computers, Vol. EC-13, No.1, Feb. 1964, pgs. 14-17) discloses the use of a multiplier split into "left" and "right" parts to generate the reciprocal of an operand as a means of performing division or calculating a square root. The present invention provides an arithmetic processor for performing a plurality of arithmetic functions including a first multiplier array having first and second input ports and a second multiplier array having third and fourth input ports, wherein the arithmetic processor includes a logic circuit capable of combining the first and second multiplier arrays into a combined multiplier array, an operand routing circuit for routing operands in function of the arithmetic function executed by the arithmetic processor, said operand routing circuit having input ports for receiving input operands and output ports connected to the input ports of the first and second multiplier arrays, a seed number generator having an output port connected to a further input port of the operand routing circuit, storage means having input ports connected to an output port of the first multiplier array and to an output port that, in operation, provides the output from the arithmetic processor and having an output port connected to a first feedback input port of the operand routing circuit, generator-storage means connected to an output port of the second multiplier array and to a second feedback input port of the operand routing circuit and switching and adder circuits connected between the first and second multiplier arrays and said output port that, in operation, provides the output from the arithmetic processor, the operand routing circuit, the logic circuit, the seed number generator and the switching and adder circuits including respective control input ports for receiving specific control commands to which the operand routing circuit, in operation, responds by reading input operands from the operand input ports along with a seed number from the seed generator which, in operation, selects the seed number according to one input operand, and to which the operand routing circuit, the logic circuit and the switching and adder circuits respond by circulating the operands and the seed number through the operand routing circuit, through the first and second multiplier arrays to perform in parallel two multiplications independently of each other, through the storage means and through the generator-storage means and by repeatedly circulating further operands derived from circulating the seed number and the input operands, during which the logic circuit operates, in response to the specific control commands, to combine the first and second multiplier arrays for at least one circulation whereby division and square root operations are performed. Preferably, the operand routing circuit, in operation, responds to a first control command by (a) reading input operands from the operand input ports along with a seed number from the seed generator which operates to select the seed number according to one input operand, (b) routing a first input operand to the first input port of the first multiplier array and routing a second input operand to the third input port of the second multiplier array, (c) routing the seed number to the second and fourth input ports of the first and second multiplier arrays, (d) passing the input operands and the seed number through the first and second multiplier arrays and storing the output operands from the first and second multiplier arrays in the storage means and the generator-storage means, respectively, (e) providing first and second further input operands by routing the contents of the storage means to the first input port of the first multiplier array and the contents of the generator-storage means to the third input port of the second multiplier array, (f) generating a third further input operand from the contents of the generator-storage means and routing the third further input operand to the second and fourth input ports of the first and second multiplier arrays, (g) passing the further input operands through the first and second multiplier arrays and storing the further outputs from the first and second multiplier arrays in the storage means and the generator-storage means, respectively, (h) providing a fourth further input operand from the contents of the storage means and generating a fifth further input operand from the contents of the generator-storage means, (i) routing the fourth further input operand to the first input port of the first multiplier array and the fifth further input operand to the fourth input port of the second multiplier array and passing the fourth and fifth further input operands through the first and second multiplier arrays, the logic circuit responding to the first control command by combining the first and second multiplier arrays into the combined multiplier array during the passage of the fourth and fifth input operands. Preferably, the generator-storage means includes a first register which, in operation, stores a current output operand, a second register which, in operation, stores a previous output operand and a generator which, in operation, generates further input operands from the contents of the first register. Preferably, the switching and adder circuits include a switching circuit and an adder circuit, a first input port of the switching circuit being connected to an output port of the first multiplier array and to a first input port of the storage means while a second input port of the switching circuit is connected to an output port of the second multiplier array and to an input port of the generator-storage means, first and second output ports of the switching circuit being connected to respective first and second input ports of the adder circuit, the adder circuit having an output port that is connected to a second input port of the storage means and provides the output from the arithmetic processor. Preferably, the arithmetic processor includes a decoder having an input port providing an input port to the arithmetic processor and an output port connected to the control input ports of the operand routing circuit, the logic circuit and the switching an adder circuits, the decoder, in operation, translating input commands to the arithmetic processor into internal commands that result in the arithmetic processor executing specific arithmetic processes. Preferably, the arithmetic processor includes a first rounding circuit connected to the output port that, in operation, provides the output from the arithmetic processor. Preferably, the arithmetic processor includes a second rounding circuit connected to the storage means for rounding the contents of the storage means. Preferably, the arithmetic processor includes a third rounding circuit connected to the generator-storage means for rounding the contents of the generator-storage means. Preferably, the seed number generator includes a look-up table having stored seed values that, in operation, are selected according to the operand applied to the second multiplier array. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with accompanying drawing, in which: FIGURE 1 illustrates the architecture of the processor of the present invention; and FIGURE 2 is a functional block diagram of multiplier circuitry for use in the present invention. DETAILED DESCRIPTION OF THE PRESENT INVENTION The processor of the present invention employs two convergence algorithms: one for performing a division calculation and another for performing square root calculations. In division, X÷Y=Q where X is the dividend, Y is the divisor and Q is the quotient. The equation can also be written in the form X/Y=Q. In the first step of the division algorithm, X and Y are both multiplied by a seed value S selected to drive Y to one. After the first step, X*S=Q and Y*S=G. The next step multiplies Q and G by a function F where F=2-G. The result of F*Q replaces the old value of Q and the result of F*G replaces the old value of G. The last step is repeated a predetermined number of times such that F*G approaches one and F*Q approaches the quotient of X/Y. In square roots, a square root R of a number A is such that R*R=A. In a convergence algorithm for calculating the root value R of a number A, an equation is written of the form A/A. In the first step of the convergence algorithm, the A in the numerator position is multiplied by a seed value S and the A in the denominator position is twice multiplied by the same seed value S such that A*S=Q and A*S*S=G. In the next step, Q is multiplied by a function F where F=(3-G)/2 and G is twice multiplied by the F function. The result F*Q replaces the old Q and the result F*F*G replaces the old G. The last step is repeated a predetermined number of times such that F*Q approaches the root value and F*F*G approaches one. Referring to FIGURE 1, decoder 12 receives commands from a logic unit (not shown) which determine the numerical calculation to be performed by the processor, such as multiplication, division or square root. In response to the commands, decoder 12 transmits a control signal CS on output 14, there being a different control signal for each of the different types of calculations to be performed. Control signal CS is transmitted to operand routing circuitry 16, logic circuitry 18, switching circuitry 20 and seed generator 28. The control signal instructs the circuitry to perform a specific calculation such as multiplication, division or a square root. The commands are typically generated by a stored program computer or other devices well known to those skilled in the art. Operand routing circuit 16 receives operands N and D on input lines 22 and 24 and receives seed value S from seed generator 28 on input line 26 and routes them to appropriate output lines connected to multiplier 38. Operand routing circuitry 16 transmits operand N and seed value S on output lines 30 and 32 and transmits operand D and seed value S on output lines 34 and 36. Operand N represents the numerator of the fraction and Operand D represents the denominator of the fraction. A number upon which a calculation is to be performed will be normalized and put into fraction notation of the form N/D as is well known to those skilled in the art. Logic circuitry 18 of multiplier 38 receives control signal CS from decoder 12 and, in the event that signal requires either a division or square root calculation, reconfigures multiplier 38 into two arrays labeled L and R. Operand routing circuitry 16 routes operand N and seed value S to the L array and routes operand D and seed value S to the R array. The output of array L is transmitted along line 40 to switching circuitry 20 and the output of stage R of multiplier 38 is transmitted along line 42 to switching circuitry 20. Switching circuitry 20 in response to control signal CS from decoder 12, directs the outputs of multiplier arrays L and R along a predetermined path in accord with the type of calculation to be performed. After making a predetermined number of passes through multiplier 38, switching circuitry 20 directs the output of arrays L and R of multiplier 38 to adder 44. The output of adder 44 is transmitted to rounder circuitry 46 which perform a rounding function as is well known to those skilled in the art. Associated with switching circuitry 20 are Q register 48 and G register 50. The Q and G registers receive intermediate results from multiplier 38 through switching circuitry 20 and feed those intermediate results back to operand routing circuitry 16. Rounding circuitry associated with each of the Q and G registers is provided increasing the precision of the results. Q rounder 52 receives the output from Q register 48, performs a rounding function and transmits the result to operand routing circuitry 16 along line 54. G round register 56 receives the output from G register 50, performs the rounding function, and transmits the output along line 58 to operand routing circuitry 16. Also associated with the G register 50 is F register 60 and F generator 62. Those registers are employed during certain steps associated with the square root function which will be more fully explained hereinafter. Referring now to FIGURE 2, the multiplier circuitry for use in the present invention will be more fully explained. Multiplication, as is well known to those skilled in the art, can be performed using an adder tree. The architecture for adder trees is well known. One such device is described in European Patent Appln.No.0 326 414 owned in common with the assignee of this application. This invention modifies the multiplier described in EP-A-0 326 414 by reconfiguring that multiplier into two separate arrays. The operand routing circuitry 100 directs operand N (now characterized as the multiplicand) to a bus 102. Operand D (now a multiplicand D) is directed to bus 104. Seed value S is directed by operand routing circuitry 100 to bus 106. Seed value S is now referred to as multiplier S. Bus 102 is connected to the full precision ports of a partial product generators 108 A-D and bus 104 is connected to the full precision ports of a second set of partial product generators 110A-D. Bus 106 is connected to the half precision ports of both sets of partial products generators 108A-D and 110A-D. Partial product generators 108A and B are connected to first level adder 112A. Partial product generators 108C and D are connected to first level adder 112D. Partial product generators 110 A and B are connected to first level adder 114A and partial product generators 110 C and D are connected to first level adder 114 B. The outputs of the first level adders are paired and connected to second level adders 116 A and B. The outputs of first level adders 112 A and B are connected to the inputs of second level adder 116 A and the outputs of first level adders 114 A and B are connected to the input of second level adder 116 B. The output of the second level adders 116 A and B are directed to the switching circuitry 118 for routing through the system and to final adder 120. The operation of an apparatus built in accord with the invention will now be described. For each operation, control signals CS, indicating the type of calculation to be performed, are generated by decoder 12. In the present embodiment, there are three control signals denoting multiply, divide and square root. In response to the received control signal, operand routing circuit 16, logic circuit 18 and switching circuit 20 determine the data path and number of iterations through multiplier 38. Multiplication Clock cycle 0: Operands N and D enter multiplier 38. Lines 30 through 36 are used by operand routing circuit 16 to transmit the multiplier operands onto the four ports on the L array and R array of multiplier 38. Operand N is routed to the full precision port of the L array of multiplier 38, and operand D is routed to the half precision port of the R array of multiplier 38. The product of N and D is passed through switching circuit 20 to the adder 44. Clock cycle 1: The number in adder 44 is passed to rounder 46 and is rounded as is well known to those skilled in the art. In this clock cycle, operand routing circuit 16 and multiplier 38 are free for another operation. Division Clock cycle 0: Operands N and D enter operand routing circuit 16 of the processor. Seed value S is retrieved from seed generator 28, which can be a lookup table, using a portion of D as the index. Control signal CS from decoder 12 instructs the operand routing circuit 16 and multiplier 38 to produce the partial products of N and S and the partial products of D and S. Multiplier 38 is reconfigured into L and R arrays. N is directed on bus 102 to the full precision ports of array L and D is directed on bus 104 to the full precision ports of array R. The S value is sent to the half precision ports of multiplier 38 on bus 106. The product of N and S is stored in Q register 48 and the product of D and S is stored in G register 50 at the end of the clock cycle. Clock cycle 1: is computed from the value stored in G register 50 at the end of clock cycle 0. Multiplier 38 remains configured in two array mode to produce the product of Q and F and the product of G and F, where in both multiplications, F is connected to the half precision ports by bus 106. The product of G and F is routed back to G register 50, and the product of Q and F is routed back to Q register 48. Clock cycle 2: F is computed from the value stored in G register 50 at the end of clock cycle 1. Multiplier 38 is reconfigured in single array mode to produce the product of Q and F. The product of F and Q is routed through switching circuit 20 to adder 44. The output of adder 44 is transmitted to rounder 46. The number stored in rounder 46 is the estimate of the quotient that will be rounded in the next clock cycle. Clock cycle 3: The number in rounder 46 is rounded as is well known to those skilled in the art. In this clock cycle, the operand routing circuit 16 and multiplier 38 are free for another operation. Square Root Clock cycle 0: Operands N and D enter operand routing circuit 16 of the processor. Seed value S is retrieved from seed generator 28, which can be a lookup table, using a portion of D, as the index. Multiplier 38 is configured into two arrays to produce the partial products of N and S and the partial products of D and S. N is directed on bus 102 to the full precision ports of array L and D is directed on bus 104 to the full precision ports of array R. The S value is sent to the half precision ports of buses 106. The results are routed through switching circuit 20 and the product of N and S is stored in Q register 48 and the product of D and S is stored in G register 50 at the end of the clock cycle. Clock cycle 1: The value in Q register 48 is not modified during this clock cycle. Multiplier 38 is reconfigured as a single array to operate on the G value from G register 50 and the seed value S. The product of the S and G is routed back to G register 50. Clock cycle 2: F is computed from the value stored in G register 50 at the end of clock cycle 1. Multiplier 38 is reconfigured as two arrays to produce the partial product of Q and F, and the partial product of G and F. The product of F and Q is routed back to G register 50. The F value computed at the beginning of clock cycle 2 is saved in F register 60. Clock cycle 3: The value in Q register 48 is not modified during this clock cycle. Multiplier 38 is reconfigured into a single array to operate on the value from G register 50 and the F value stored in F register 60. The product of F and G is routed back to G register 50. Clock cycle 4: F is computed from the value stored in G register 50 at the end of clock cycle 1. Multiplier 38 remains in single array mode to produce the product of Q and F. The product of F and Q is routed through switching circuit 20 to adder 44. The output of adder 44 is transmitted to rounder 46. Clock cycle 5: The number in rounder 46 is rounded as is well known to those skilled in the art. In this clock cycle, operand routing circuit 16 and multiplier 38 are free to begin another operation. From the foregoing description it will be seen by those having skill in the art that under the present invention a numerical processor is provided with a single multiplier that can be configured to operate in either single or double stage mode. The use of a double array multiplier results in performing division and square root calculations with a high degree of parallelism and higher speeds than has been previously possible.

Claims: An arithmetic processor for performing a plurality of arithmetic functions, including a first multiplier array (38L) having first and second input ports (30,32), a second multiplier array (38R) having third and fourth input ports (34,36), characterised in that the arithmetic processor includes a logic circuit (18) capable of combining the first and second multiplier arrays (38L,38R) into a combined multiplier array (38 , an operand routing circuit (16) for routing operands in function of the arithmetic function executed by the arithmetic processor, said operand routing circuit, having input ports for receiving input operands and output ports connected to the input ports (30,32,34,36) of the first and second multiplier arrays (38L,38R), a seed number generator (28) having an output port connected to a further input port of the operand routing circuit (16), storage means -(48) having input ports connected to an output port (40) of the first multiplier array (38L) and to an output port that, in operation, provides the output from the arithmetic processor and having an output port connected to a first feedback input port (54) of the operand routing circuit (16), generator-storage means (50,60,62) connected to an output port of the second multiplier array (38R) and to a second feedback input port of the operand routing circuit (16) and switching and adder circuits (20,44) connected between the first and second multiplier arrays (38L,38R) and said output port that, in operation, provides the output from the arithmetic processor, the operand routing circuit (16), the logic circuit (18), the seed number generator (28) and the switching and adder circuits (20,44) including respective control input ports for receiving specific control commands to which the operand routing circuit (16), in operation, responds by reading input operands from the operand input ports along with a seed number from the seed generator (28) which, in operation, selects the seed number according to one input operand, and to which the operand routing circuit (16), the logic circuit (18) and the switching and adder circuits respond by circulating the operands and the seed number through the operand routing circuit (16), through the first and second multiplier arrays (38L,38R) to perform in parallel two multiplications independently of each other, through the storage means (48) and through the generator-storage means (50,60,62) and by repeatedly circulating further operands derived from circulating the seed number and the input operands, during which the logic circuit (18) operates, in response to the specific control commands, to combine the first and second multiplier (38L,38R) arrays for at least one circulation whereby division and square root operations are performed. An arithmetic processor as claimed in claim 1, wherein the operand routing circuit (16), in operation, responds to a first control command by (a) reading input operands from the operand input ports along with a seed number from the seed generator (28) which operates to select the seed number according to one input operand, (b) routing a first input operand to the first input port (30) of the first multiplier array (38L) and routing a second input operand to the third input port (34) of the second multiplier array (38R), (c) routing the seed number to the second and fourth input ports (32,36) of the first and second multiplier arrays (38L,38R), (d) passing the input operands and the seed number through the first and second multiplier arrays (38L,38R) and storing the output operands from the first and second multiplier arrays (38L,38R) in the storage means (48) and the generator-storage means (50,60,62), respectively, (e) providing first and second further input operands by routing the contents of the storage means (48) to the first input port (30) of the first multiplier array (38L) and the contents of the generator-storage means (50,60,62) to the third input port (34) of the second multiplier array (38R), (f) generating a third further input operand from the contents of the generator-storage means (50,60,62) and routing the third further input operand to the second and fourth input ports (32,36) of the first and second multiplier arrays (38L,38R), (g) passing the further input operands through the first and second multiplier arrays (38L,38R) and storing the further outputs from the first and second multiplier arrays (38L,38R) in the storage means (48) and the generator-storage means (50,60,62), respectively, (h) providing a fourth further input operand from the contents of the storage means (48) and generating a fifth further input operand from the contents of the generator-storage means (50,60,62), (i) routing the fourth further input operand to the first input port of the first multiplier array (38L) and the fifth further input operand to the fourth input port of the second multiplier array (38R) and passing the fourth and fifth further input operands through the first and second multiplier arrays (38L,38R), the logic circuit (18) responding to the first control command by combining the first and second multiplier arrays (38L,38R) into the combined multiplier array (38) during the passage of the fourth and fifth input operands. An arithmetic processor as claimed in claim 1 or claim 2, wherein the generator-storage means (50,60,62) includes a first register (50) which, in operation, stores a current output operand, a second register (60) which, in operation, stores a previous output operand and a generator (62) which, in operation, generates further input operands from the contents of the first register (50). An arithmetic processor as claimed in any one of claims 1 to 3, wherein the switching and adder circuits (20,44) include a switching circuit (20) and an adder circuit (44), a first input port of the switching circuit (20) being connected to an output port of the first multiplier array (38L) and to a first input port of the storage means (48) while a second input port of the switching circuit (20) is connected to an output port of the second multiplier array (38R) and to an input port of the generator-storage means (50,60,62), first and second output ports of the switching circuit (20) being connected to respective first and second input ports of the adder circuit (44), the adder circuit (44) having an output port that is connected to a second input port of the storage means (48) and provides the output from the arithmetic processor. An arithmetic processor as claimed in any one of claims 1 to 4, including a decoder (12) having an input port providing an input port to the arithmetic processor and an output port connected to the control input ports of the operand routing circuit (16), the logic circuit (18) and the switching an adder circuits (20,44), the decoder, in operation, translating input commands to the arithmetic processor into internal commands that result in the arithmetic processor executing specific arithmetic processes. An arithmetic processor as claimed in any one of claims 1 to 5, including a first rounding circuit (46) connected to the output port that, in operation, provides the output from the arithmetic processor. An arithmetic processor as claimed in any one of claims 1 to 6, including a second rounding circuit (52) connected to the storage means (48) for rounding the contents of the storage means (48). An arithmetic processor as claimed in any one of claims 1 to 7, including a third rounding circuit (56) connected to the generator-storage means for rounding the contents of the generator-storage means (50,60,62). An arithmetic processor as claimed in any one of claims 1 to 8, wherein the seed number generator (28) includes a look-up table having stored seed values that, in operation, are selected according to the operand applied to the second multiplier array.

Inventors: DARLEY HENRY M, HIPONA MARIA B, STEISS DONALD E, DARLEY, HENRY M., HIPONA, MARIA B., STEISS, DONALD E.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1990
Main classification: G06F7
IPC codes: G06F7