Semiconductor integrated circuit devices

Abstract: A circuit arrangement of a semiconductor integrated circuit device includes logic cell arrays (12, 13, 62, 63) arranged into columns. Each of the logic cell arrays have a plurality of logic cells (14). Each of the logic cells have at least one monitor point (15). The circuit arrangement also includes select lines (16, 65) which carry select signals, each specifying a corresponding one of the logic cell arrays. Further, the circuit arrangement includes read lines (17, 64) carrying monitor signals showing logic states of monitor points of the logic cells, the select lines and the read lines being provided so that the total number of the select lines and read lines is less than the sum total of the number of the logic cell arrays and a maximum number of monitor points contained in one of the logic cell arrays, and switch elements (18) connecting the monitor points of the logic cells to the read lines in response to the select signals.

Description: The present invention generally relates to semiconductor integrated circuit devices, and more particularly to improvements in circuit arrangements within such devices, for example gate array devices or standard cell devices, suitable for a matrix probing test. There is known a semiconductor integrated circuit device called a logic LSI which includes a plurality of column shaped logic cell arrays, each having logic cells arranged into columns. One or more monitor points are provided in each of the logic cells. The logic cells are mutually coupled by interconnection lines to thereby provide desired logic circuits. There is also known a logic LSI having column shaped basic cell arrays, each having a plurality of basic cells. The recent advance of fabricating such logic LSIs makes it possible to provide a drastically increased number of logic cells arranged in one chip. Currently, it is possible to arrange logic LSIs having tens to hundreds of thousands of logic cells on a single chip. As an increased number of logic cells is provided, it becomes difficult to test logic LSIs. In order to test logic LSIs effectively and efficiently, there is proposed a logic LSI having a built-in test circuit. Normally, a test circuit built in a logic LSI is used for carrying out a good/fail judgment of internal circuits, debugging of logic design and analysis of faults. The above-mentioned situations hold true for logic LSIs having column shaped basic cell arrays. Japanese Laid-Open Patent Application No. 61-42934 (corresponding to EP-A-0 174 236) discloses a semiconductor integrated circuit device, having a built-in test circuit, which may be considered to include a plurality of cells, which are either all logic cells or all identically-patterned basic cells, arranged in linear arrays, each array having a plurality of the cells and each cell having at least one monitor point; select lines corresponding respectively to the arrays, each for delivering to its corresponding array a select signal used to select cells of that array; read lines for carrying monitor signals representative of logic states at the monitor points of the cells when the device is in use; and switch elements, each connected between one of the monitor points and one of the read lines and also connected to one of the select lines, such that when activated in response to receipt of such a select signal delivered by that select line, such a monitor signal, representative of the logic state at the monitor point concerned, is applied to the read line concerned. Referring to Fig. 1, there is illustrated the outline of this device. A plurality of logic cells 2 are formed on a semiconductor chip 1. A built-in test circuit is composed of row select lines 3, column read lines 4, switch elements 5, a row select ring counter 6, a column selector ring counter 7, a data selector 8, a row selector clock input terminal 9, a column select clock input terminal 10 and a monitor output terminal 11. The logic cells 2 are interconnected on the basis of a user's design or specification in order to provide desired logic circuits. For the sake of simplicity, such interconnections are not illustrated in Fig. 1. Output terminals of the logic cells 2 are connected to the column read lines 4 via the switch elements 5. The row select ring counter 6 selects one of the row select lines 3, and the column select ring counter 7 selects one of the column select lines 3, so that the logic cells 2 are selected one by one. The logic state of the output terminal of a selected logic cell 2 is output to the monitor output terminal 11 via the data selector 8. In this way, information about the states of the output terminals of the logic cells 2 is obtained at the monitor output terminal 11 and used for determining whether or not desired logic circuits operate correctly. The above-mentioned test method is called a matrix proving method or simply an MP method. According to the matrix probing method, it is possible to read out the logic state of each logic cell 2. Thus, it is possible to design logic circuits easily, as compared with a conventional scan path method which uses flip-flops. In addition, the reliability of the matrix probing method is high. In conventional logic LSIs as described above, the row select lines 3 are provided for the respective rows, and the column read lines 4 are provided for the respective columns. This causes a problem in that the wiring lines are not arranged efficiently and sometimes prevents the formation of the interconnection lines. Another problem arises from the fact that each of the rows has the same number of logic cells, each having one monitor point. Thus, the arrangement shown in Fig. 1 is not applied directly to a standard cell array device having various column shaped logic cell arrays in which one or more different types of logic cells having different areas are arranged and one or more monitor points are provided in the respective logic cell arrays. In order to fabricate such a standard cell array device on the basis of the concept of the arrangement shown in Fig. 1, it is necessary to provide a number of column read lines equal to a number of monitor points contained in one of the logic cell arrays having a maximum number of monitor points. This needs a large number of column read lines and makes it difficult to design the layout of interconnection lines for coupling the logic cells. A similar semiconductor integrated circuit device having a test circuit is disclosed in EP-A-0223714. In this device there are row and column select lines and the monitor points of cells belonging to the same row-direction array are connected by diodes to a common read line for the array concerned. It is desirable to improve the circuit arrangement in such semiconductor integrated circuit devices so that the aforementioned disadvantages can be eliminated. According to a first aspect of the present invention there is provided a semiconductor integrated circuit device including: a plurality of cells, which are either all logic cells or all identically-patterned basic cells, arranged in linear arrays, each array having a plurality of the cells and each cell having at least one monitor point; select lines corresponding respectively to the arrays, each for delivering to its corresponding array a select signal used to select cells of that array; read lines for carrying monitor signals representative of logic states at the monitor points of the cells when the device is in use; and switch elements, each connected between one of the monitor points and one of the read lines and also connected to one of the select lines, such that when activated in response to receipt of such a select signal delivered by that select line, such a monitor signal, representative of the logic state at the monitor point concerned, is applied to the read line concerned; characterised in that at least one of the said arrays has first and second select lines corresponding thereto, the first select line serving to deliver a first select signal to a first switch element connecting a first monitor point of the array to one of the read lines, and the second select line serving to deliver a second select signal to a second switch element connecting a second monitor point of the array to the same read line; the total number of the said select lines and the said read lines being less than the sum of the number of the said arrays and the number of monitor points in the array having the most monitor points. According to a second aspect of the present invention there is provided a semiconductor integrated circuit device including: a plurality of cells, which are either all logic cells or all identically-patterned basic cells, arranged in linear arrays, each array having a plurality of the cells and each cell having at least one monitor point; select lines for delivering to the cells of the arrays select signals used to select those cells; read lines corresponding respectively to the arrays, each for carrying a monitor signal representative of the logic state at one of the monitor points of its corresponding array when the device is in use; and switch elements, each connected between one of the monitor points and one of the read lines and also connected to one of the select lines, such that when activated in response to receipt of such a select signal delivered by that select line, such a monitor signal, representative of the logic state at the monitor point concerned, is produced on the read line concerned; characterised in that at least one of the said arrays has first and second read lines corresponding thereto; a first switch element connects a first monitor point of that array to the said first read line, and a second switch element connects a second monitor point of that array to the said second read line; and both the said first and second switch elements are connected to the same select line; the total number of the said select lines and the said read lines being less than the sum of the number of the said arrays and the number of monitor points in the array having the most monitor points. According to a third aspect of the present invention there is provided a semiconductor integrated circuit device including a first device portion, being a semiconductor integrated circuit device embodying the aforesaid first aspect of the invention in which the said arrays extend in a first direction; and a second device portion, being a semiconductor integrated circuit device embodying the aforesaid second aspect of the invention in which the said arrays extend in a second direction perpendicular to the said first direction, the said first and second device portions being positioned side-by-side in the said first direction; the select lines of the first device portion being coupled respectively to the select lines of the second device portion. According to a fourth aspect of the present invention there is provided a semiconductor integrated circuit device including a first device portion, being a semiconductor integrated circuit device embodying the aforesaid first aspect of the invention in which the said arrays extend in a first direction; and a second device portion, being a semiconductor integrated circuit device embodying the aforesaid second aspect of the invention in which the said arrays extend in a second direction perpendicular to the said first direction, the said first and second device portions being positioned side-by-side in the said second direction; the read lines of the second device portion being coupled respectively to the read lines of the first device portion. In such semiconductor integrated circuit devices embodying the invention the total number of select lines and read lines is reduced, and thus interconnection lines can be routed efficiently without being affected by the existence of lines provided for executing a matrix probing test. Reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a block diagram illustrating a conventional semiconductor integrated circuit device having a test circuit; FIGS.2A, 2B and 2C are diagrams illustrating a conventional arrangement and an improved arrangement according to a first preferred embodiment of the present invention; FIGS.3A, 3B and 3C are diagrams illustrating a conventional arrangement and an improved arrangement according to a second preferred embodiment of the present invention; FIGS.4A, 4B and 4C are diagrams illustrating a conceivable arrangement and an improved arrangement according to a third preferred embodiment of the present invention; FIGS.5A, 5B and 5C are diagrams illustrating a conceivable arrangement and a variation of the arrangement shown in FIGS.4C; FIGS.6A, 6B and 6C are diagrams illustrating a conceivable arrangement and an improved arrangement according to a fourth preferred embodiment of the present invention; FIGS.7A, 7B and 7C are diagrams illustrating a conceivable arrangement and an improved arrangement according to a fifth preferred embodiment of the present invention; FIG.8 is a block diagram illustrating the entire structure of the first preferred embodiment of the present invention; FIGS.9A and 9B are diagrams illustrating the relationship between a special symbol used in FIG.8 and a corresponding circuit configuration; FIG.10 is a circuit diagram of a column select circuit shown in FIG.8; FIG.11 is a circuit diagram illustrating another configuration of the column select circuit shown in FIG.8; FIG.12 is a circuit diagram illustrating yet another configuration of the column select circuit shown in FIG.8; FIG.13 is a circuit diagram illustrating a sense circuit shown in FIG.8; FIG.14 is a circuit diagram illustrating another configuration of the sense circuit shown in FIG.8; FIGS.15A and 15B are diagrams illustrating an example of a logic cell used in the embodiments of the present invention; FIG.16A and 16B are diagrams illustrating another example of the logic cell used in the embodiments of the present invention; FIGS.17A and 17B are diagrams illustrating a MOS transistor serving as an switch element; FIG.18 is a block diagram illustrating a sixth embodiment of the present invention; and FIG.19 is a flowchart of a procedure for obtaining an optimum number of read lines and an optimum number of select lines. A description will now be given of a first preferred embodiment of the present invention with reference to FIGS.2A, 2B and 2C. Referring to FIG.2A, two column shaped logic cell arrays 12 and 13 are arranged in columns. Each of the logic cell arrays 12 and 13 is composed of a plurality of logic cells 14. A logic cell is defined as a unit circuit which provides a logic function by itself and which is used for forming a logic circuit. Examples of the logic cell are a NOT circuit, AND circuit, OR circuit, composite gate circuit, adder circuit, decode circuit, latch circuit, flip-flop, shift register and counter. The logic cell array 12 has two logic cells 14, and the logic cell array 13 has four logic cells 14. The logic cell array 12 has two monitor points 15, and the logic cell array 13 has four monitor points 15. Select lines run in parallel with the logic cell arrays 12 and 13, and read lines run in the direction perpendicular to the direction in which the logic cell arrays 12 and 13 run. Referring to in FIG.2B, there is illustrated a conventional structure which realizes the arrangement shown in FIG.2A. In FIG.2B, two select lines 16 and four read lines 17 are provided with respect to the logic cell arrays 12 and 13 which are adjacent to each other. More specifically, the two select lines 16 are provided for the respective logic cell arrays 12 and 13. There is provided the same number of read lines 17 as that of the monitor points 15 of the logic cell array 13 which is larger than that of the logic cell array 12. Switch elements 18 formed of n-channel field effect transistors are respectively provided between the respective monitor points 15 and the corresponding read lines 17. That is, two switch elements 18 are provided for the logic cell array 12, and four switch elements 18 are provided for the logic cell array 13. It is possible to use p-channel field effect transistors or bipolar transistors in place of the n-channel field effect transistors. Hereinafter, field effect transistors are simply referred to as MOS transistors. Referring to FIG.2C, there is illustrated a corresponding arrangement according to the first preferred embodiment of the present invention. According to the first preferred embodiment of the present invention, a number of select lines 16 larger than than that of logic cell arrays 12 and 13 is provided. In FIG.2C, three select lines 16 are provided for the two logic cell arrays 12 and 13. More specifically, one select line 16 is provided for the logic cell array 12, and two select lines 16 are provided for the logic cell array 13. In general, the number of select lines 16 for each of the logic cell arrays is half the number of monitor points 15 of a corresponding one of the logic cell arrays or its nearest whole number, and the total number of read lines 17 is half the maximum number of monitor points or its nearest whole number. As a result, it is sufficient to provide two read lines 17. The sum total of the number of select lines 16 and the number of read lines 17 is one less than that for the conventional arrangement shown in FIG.2B. Two MOS transistors 18 located on the left side of the logic cell array 13 have drains connected to the respective monitor points 15, sources connected to the corresponding read line 17, and gates connected to the respective select lines 16. As described above, according to the first preferred embodiment of the present invention, it becomes possible for the sum total of the number of select lines 16 and the number of read lines 17 to be less than the sum total of the number of select lines 16 (equal to the number of logic cell arrays) and the number of monitor points in the logic cell array which has the most monitor points. A description will now be given of a second preferred embodiment of the present invention with reference to FIGS.3A, 3B and 3C. In these figures, those parts which are the same as those shown in FIGS.2A, 2B and 2C are given the same reference numerals. As shown in FIG.3A, the second embodiment of the present invention has an arrangement in which read lines run in parallel with the logic cell arrays 12 and 13 and select lines run in the direction perpendicular to the direction in which the logic cell arrays run. Referring to FIG.3B, there is illustrated a conventional structure which realizes the arrangement shown in FIG.3A. Two read lines 17 are provided for the respective column cell arrays 12 and 13, and four select lines 16 corresponding to the four monitor points of the logic cell array 13 are provided. The conventional arrangement needs a number of select lines 16 equal to a maximum number of monitor points contained in one of the logic cell arrays, and a number of read lines 17 equal to the total number of the logic cell arrays 12 and 13. Referring to FIG.3C, there is illustrated a corresponding arrangement according to the second preferred embodiment of the present invention. According to the second preferred embodiment, a number of read lines larger than that of logic cell arrays is provided. As shown in FIG.3C, three read lines 17 are provided for the two logic cell arrays 12 and 13. More specifically, one read line 17 is provided for the logic cell array 12, and two read lines 17 are provided for the logic cell array 13. Two select lines 16 are provided for the logic cell arrays 12 and 13. The total number of read lines 17 and select lines 16 shown in FIG.3C is equal to 5, and is one less than that of read lines 17 and select lines 16 shown in FIG.3B. In general, the number of read lines 17 for each of the logic cell arrays is half the number of monitor points 15 of a corresponding one of the logic cell arrays or its nearest whole number, and the total number of select lines 16 is half the maximum number of monitor points 15 or its nearest whole number. In this manner, according to the second preferred embodiment of the present invention, it becomes possible for the total number of select lines 16 and read lines 17 to be less than the sum total of the number of select lines 16 (equal to the number of logic cell arrays) and the number of monitor points of the logic cell array which has the most monitor points. Two MOS transistors located on the left side of the logic cell array 13 have drains connected to the respective monitor points 15, sources connected to the respective read lines 17, and gates connected to the corresponding select line 16. A description will now be given of a third preferred embodiment of the present invention with reference to FIGS.4A, 4B and 4C. In these figures, those parts which are the same as those shown in the preceding figures are given the same reference numerals. An arrangement shown in Fig. 4A has a first logic cell array group (first device portion) 21 composed of two logic cell arrays 19 and 20, and a second logic cell array group (second device portion) 24 composed of two logic cell arrays 22 and 23. The logic cell arrays 19 and 20 of the first group 21 run in the direction perpendicular to the direction in which the logic cell arrays 22 and 23 of the second group 24 run. Select lines run in parallel with the logic cell arrays 19 and 20, and read lines run in parallel with the logic cell arrays 22 and 23. The first and second groups 21 and 24 are located side by side in the direction in which the select lines run. Referring to FIG.4B, there is illustrated a conceivable structure which realizes the arrangement shown in FIG.4A. The structure shown in FIG.4B needs a number of select lines equal to a larger number out of the number of logic cell arrays of the first group 21 and the number of monitor points of that one of the logic cell arrays of the second group 24 that has the most monitor points. In the arrangement shown in FIG.4A, the first group 21 has two logic cells 19 and 20, and the maximum number of monitor points related to the second group 24 is equal to 4. Thus, as shown in FIG.4B, four select lines 16 are provided for the first and second groups 21 and 24. Further, the structure shown in FIG.4B needs a number of read lines equal to the sum total of the number of monitor points of that one of the logic cell arrays of the first group 21 that has the most logic cells and the number of logic cell arrays of the second group 24. In the structure shown in FIG.4A, the maximum number of monitor points related to the first group 21 is equal to 4, and the second group 24 has two logic cell arrays 22 and 23. Thus, as shown in FIG.4B, six read lines 17 are provided. Referring to FIG.4C, there is illustrated a corresponding structure which realizes the arrangement shown in FIG.4A according to the third preferred embodiment of the present invention. According to the third embodiment, select lines greater in number than the logic cell arrays of the first group 21 are provided, and read lines greater in number than the logic cell arrays of the second group 24 are provided. Two select lines 16 are provided for the logic cell array 20, and two read lines 17 are provided for the logic cell array 23. The arrangement shown in FIG.4C has three select lines 16 and five read lines 17. That is, the total number of select lines 16 and read lines 17 shown in FIG.4C is two less than the total number of select lines 16 and read lines 17 shown in Fig. 4B. Two MOS transistors 18 located on the left side of the logic cell array 20 have drains connected to the respective monitor points 15, sources connected to the corresponding read line 17, and gates connected to the respective select lines 16. Two MOS transistors 18 located on the upper side of the logic cell array 23 have drains connected to the respective monitor points 15, sources connected to the respective read lines 17, and gates connected to the corresponding select line 16. According to the third preferred embodiment, it becomes possible for the total number of select lines 16 and read lines 17 to be two less than the total number of these lines shown in FIG.4B. A description will now be given of a variation of the third preferred embodiment of the present invention with reference to FIGS.5A, 5B and 5C. As shown in FIG.5A, the first and second groups 21 and 24 are located side by side in the direction in which the read lines 17 run. Referring to FIG.5B, there is illustrated a conceivable structure which realizes the arrangement shown in FIG.5A. The arrangement shown in FIG.5B has select lines 16 equal in number to the logic cell arrays 19 and 20 of the first group 21, and a number of select lines equal to the number of monitor points 15 of that one of the logic cell arrays of the second group 24 that has the most monitor points. In the arrangement shown in FIG.5, the logic cell array 23 has the highest number of monitor points 15. Thus, the total number of read lines 17 is equal to 6. Further, the arrangement shown in FIG.5B has four read lines 17 equal in number to the monitor points 15 of the second-group logic cell array 23 which has the highest number of monitor points. It will be noted that the total number of select lines 16 and read lines 17 shown in FIG.5B is equal to 10. Referring to FIG.5C, there is illustrated a corresponding structure according to the variation of the third preferred embodiment of the present invention. The structure shown in FIG.5C needs only five select lines 16 and three read lines 17. The total of select lines 16 and read lines 17 used in the structure shown in FIG.5C is equal to 8, which is two less than that for the arrangement shown in FIG.5B. More specifically, the first group 21 has (three) select lines 16 greater in number than the (two) logic cell arrays 19 and 20, and the second group 24 has (three) read lines 17 greater in number than the (two) logic cell arrays 22 and 23. Two MOS transistors 18 located on the left side of the logic cell array 20 have drains connected to the respective monitor points 15, sources connected to the corresponding read line 17, and gates connected to the respective select lines 16. Two MOS transistors 18 on the upper side of the logic cell array 23 have drains connected to the respective monitor points 15, sources connected to the respective read lines 17, and gates connected to the corresponding select line 16. A description will now be given of a fourth preferred embodiment of the present invention with reference to FIGS.6A, 6B and 6C. Referring to FIG.6, there are illustrated two basic cell arrays 26, each having a plurality of basic cells 25. Each of the basic cells 25 has one monitor point 15. Select lines run in the direction in which the basic cell arrays 26 run, and read lines run in the direction-perpendicular to the basic cell arrays 26. A basic cell is a unit composed of grouped transistors having an identical pattern. Referring to FIG.6B, there is illustrated a conceivable structure which realizes the arrangement shown in FIG.6A. Two select lines 16 are provided for the respective basic cell arrays 26, and read lines 17 are provided for the respective basic cells 25 of the basic cell arrays 26. Switch elements 18 formed of n-channel type MOS transistors are respectively provided between the monitor points 15 of the basic cells 25 and the read lines 17. The gates of the MOS transistors 18 are connected to the corresponding select lines 16. It will be noted that one select line 16 is provided for one basic cell array 26, and one read line 17 is provided for one basic cell 25. Thus, it is necessary to provide a wiring area 61 between the adjacent basic cells 25. Referring to FIG.6C, there is illustrated a corresponding structure according to the fourth preferred embodiment of the present invention. According to the fourth preferred embodiment of the present invention, a plurality of select lines are respectively provided for each of the basic cell arrays 26. In the arrangement shown in FIG.6, two select lines 16 are provided for the respective basic cell arrays 26. On the other hand, one read line 17 is arranged for every group 60 (gate circuit) consisting of two adjacent basic cells 25. The two adjacent basic cells 25 are close to each other without having any wiring area, and the wiring area 61 is provided between the adjacent groups. Thus, although the number of read lines 17 is half the number of read lines 17 shown in FIG. 6B, this number is sufficient to configure the arrangement shown in FIG.6A. With the above-mentioned arrangement, it becomes possible to provide a reduced number of wiring areas 61. The MOS transistor 18 provided for one of the two basic cells 25 of each group 60 has a drain connected to the corresponding monitor point 15, a source connected to a corresponding one of the two read lines 17 related to the group being considered, and a gate connected to one of the corresponding select lines 16. Further, the MOS transistor 18 provided for the other basic cell 25 of the same group 60 has a drain connected to the corresponding monitor point 15, a source connected to the other read line 17, and a gate connected to the other select line 16. It should be noted that the wiring area 61 shown in FIG.6C has a length less than the sum total of the lengths of two of the wiring areas 61 shown in FIG.6B. It is also possible to provide the read lines 17 over thebasic cells 25. A description will now be given of a fifth preferred embodiment of the present invention with reference to FIGS.7A, 7B and 7C. In these figures, those parts which are the same as those shown in the previous figures are given the same reference numerals. An arrangement shown in FIG.7A has read lines which run in the direction in which the basic cell arrays 26 run, and select lines in the direction in which the basic cell arrays 26 are spaced apart from each other. Referring to FIG.7B, there is illustrated a conceivable structure which configures the arrangement shown in FIG.7A. The two read lines 17 are respectively provided for each of the two basic cell arrays 26, and the select lines 16 are provided for the respective basic cells 25 of the basic cell arrays 26. The MOS transistors 18 are respectively provided between the read lines 17 and the basic cells 25. The gates of the MOS transistors 18 are connected to the corresponding select lines 16. The wiring areas 61 are respectively provided between adjacent basic cells 25. Referring to FIG.7C, there is illustrated a corresponding structure which realizes the arrangement shown in FIG.7A according to the fifth preferred embodiment of the present invention. Two adjacent basic cells 25 are grouped to form the gate circuit 60, and one select line is arranged for every group. Two read lines 17 are provided for each basic cell array 26. According to the fifth preferred embodiment, it is possible to use a number of select that is half the number of select lines 16 shown in FIG.7B and use a reduced number of wiring areas 61. The MOS transistor 18 related to one of the two basic cells 25 of each group has a drain connected to the corresponding monitor point 15, a source connected to one of the two read lines 17, and a gate connected to one of the two select lines 16 related to the group being considered. Similarly, the MOS transistor 18 related to the other basic cell 25 has a drain connected to the corresponding monitor point 15, a source connected to the other read line 17, and a gate connected to the other select line 16. Alternatively, it is also possible to form the gate circuits 60 without forming the select lines 16 and the read lines 17, arrange one or more monitor points 15 for each gate circuit 60 and provide the read lines 17 above the basic cells 25. Referring to FIG.8, there is illustrated the entire structure of a semiconductor integrated circuit device according to the aforementioned first preferred embodiment of the present invention. The device shown in FIG.8 has a semiconductor integrated circuit chip 27, logic cells 28, column shaped logic cell arrays 29 and monitor points 30. A test circuit is composed of a timing control circuit 31, a logic cell array selecting circuit 32, array select lines 33, n-channel MOS transistors 34, read lines 35, a sense circuit 36 and a monitor output terminal 37. In FIG.8, the MOS transistors 34 are illustrated by special symbols for the sake of simplicity. The relationship between the special symbol and a corresponding circuit is illustrated in FIGS.9A and 9B. The timing control circuit 31 controls the operation timings of the array select circuit 32 and the sense circuit 36. For this purpose, the timing control circuit 31 generates a clear signal CLR, a clock signal CK, a load signal LD and a load data composed of data D0, D1, D2, ..., as shown in FIG.10. FIG.10 is a circuit diagram of the array select circuit 32. As shown, the array select circuit 32 is composed of an address counter 38 and an address decoder 39. The address decoder 39 is composed of a group 40 of NAND circuits and a group 41 of inverters. The address counter 38 is cleared by the clear signal CLR, and then starts to count the clock signal CK. Each time the address counter 38 counts the clock signal CK, it outputs an address composed of address bits A0, A1, A2, ..., as shown in FIG.10. It is also possible to input the load signal LD to the address counter 38 and load the load data D0, D1, D2, ... therein. Thereby, the address counter 38 outputs a special address. The address thus generated is supplied to the group 40 of NAND circuits. Alternatively, it is also possible to configure the array select circuit 32 shown in FIG.8 by using a ring counter 42 shown in FIG.11. The ring counter 42 is composed of cascaded D-type flip-flops 44 through 47, an OR circuit 48 and an AND circuit 49. Output terminals Q of the flip-flops 44 through 47 are connected to input terminals of the AND circuit 49. An output terminal of the AND circuit 49 is connected to an input terminal of the OR circuit 48, which has an another input terminal connected to the output terminal Q of the flip-flop 47 of the final stage. The output signal generated by the OR circuit 48 is fed back to the flip-flop 44 of the fist stage. The output signals of the flip-flops 44 through 47 are supplied to the array select lines 33. FIG.12 illustrates another ring counter 43. In FIG.12, those parts which are the same as those shown in FIG.11 are given the same reference numerals. A D-type flip-flop 50 is substituted for the AND circuit 49 shown in FIG.11. FIG.13 is a circuit diagram of the sense circuit 36 shown in FIG.8. The sense circuit 36 in FIG.8 is composed of a group 51 of sense amplifiers 53 connected to the read lines 35, and a shift register 52. The shift register 52 has a parallel-to-serial conversion function, and has input terminals equal in number to the sense amplifiers 53. The monitor output terminal 37 is connected to an output terminal of the shift register 52. The shift register 52 operates in synchronism with a clock signal and a shift/latch select signal, both of which signals are generated by the timing control circuit 31 shown in FIG.8. The sense circuit 36 is also configured, as shown in FIG.14. The sense circuit 36 shown in FIG.14 is composed of sense amplifiers 53, a data compression adder 54 and shift register 52. The data compression circuit 54 is interposed between the sense amplifiers 53 and the shift register 52, and processes the sensed signals from the sense amplifiers 53 in accordance with a data compressed addition procedure. FIG.15A is a circuit diagram of a two-input NAND circuit which is an example of the logic cells 28, and FIG.15B is a plan view illustrating a pattern of the circuit shown in FIG.15A. The NAND circuit shown in FIG.15A is composed of two p-channel MOS transistors 55 and 56, and two n-channel MOS transistors 57 and 58. An output signal X is obtained by carrying out a NAND operation between two input signals "a" and "b". A monitor output signal is output to the monitor output terminal 37 via a MOS transistor 34. The NAND circuit shown in FIG.15A is connected between a positive power supply line V DD and a negative power supply line V SS . FIG.16A is a circuit diagram of a D-type flip-flop which is an example of the logic cells 28. Two monitor points 30 are provided in the flip-flop shown in FIG.16A. Two monitor output signals are respectively obtained from the monitor points 30 via two n-channel MOS transistors 34. The monitor points 30 are located, as shown in FIG.16B. FIG.17A illustrates an n-channel MOS transistor 34 functioning as the aforementioned switch element 18. In FIG.17A, those parts which are the same as those shown in the previous figures are given the same reference numerals. It can be seen from FIG.17A that the MOS transistor 34 is fabricated as a part of the logic cell 28. FIG.17B illustrates an arrangement in which the MOS transistor 34 is fabricated separately from the logic cell 28. The monitor point 30 of the logic cell 28 is connected to the MOS transistor 34 via a metaliic lower layer 59 used for mutually connecting logic cells. This arrangement realizes the wiring efficiently and provides a large degree of freedom to route interconnection lines provided for mutually connecting the logic cells 28. For example, it is possible to position the MOS transistor at an optimum point so that the read line 35 runs straight without being bent. This increases the degree of freedom to route the interconnection lines. A description will be given of a sixth preferred embodiment of the present invention with reference to FIG.18. A semiconductor integrated circuit device shown in FIG.18 is composed of column shaped logic cell arrays 62 and 63, read lines 64, select lines 65, a megacell 66, a select circuit 67, a sense circuit 68 and a control circuit 69. The logic cell arrays 62 run in the transversal direction, and the logic cell arrays 63 run in the direction perpendicular to the transversal direction. The read lines 64 and the select lines 65 run along the logic cell arrays 62 and 63. This arrangement is different from the aforementioned embodiments of the present invention. The read lines 64 are connected to the sense circuit 68, and the select lines 65 are connected to the select circuit 67. Although switch elements, such as the MOS transistors 18, are connected between the read lines 64 and the monitor points 15, these switch elements are not shown for the sake of simplicity. The read lines 64 and the select lines 65 change direction at ends of the logic cell arrays 62 and 63 so that these lines run around the megacell 66. The read lines 64 have first portions related to the logic cell arrays 62 on the left side of the drawing and second portions related to the logic cell arrays 63, the first and second portions of each read line 64 being connected together. The megacell 66 is a block shaped circuit including a memory and an analog circuit such as a multiplier. The megacell 66 has at least one monitor point 15, which is connected to the sense circuit 68 via the read line 64. The megacell 66 is also connected to the select circuit 67 via the select line 65. The control circuit 69 inputs monitor control signals from an external circuit, and controls the select circuit 67 and the sense circuit 68. A monitor output signal is output from the sense circuit 68. FIG.19 illustrates a computer-implemented procedure showing how to obtain an optimum number of read lines and an optimum number of select lines, for example, in the arrangement shown in FIG.2A. At step 101, the number of read lines, Ns, and the number of select lines, Np, obtained by the aforementioned prior art as shown in FIG.2B are calculated. At step 102, Ns x Np is calculated. Step 103 investigates the distribution of monitor points where the monitoring is required for each column shaped logic cell array, and obtains the maximum number of monitor points, maxN, and the minimum number of monitor points, minN. At step 104, weighting functions, Er and Es, showing that the routing of read and select lines affects the layout area on the chip. At step 105, the optimum number of read lines and the optimum number of select lines are calculated by using the results obtained at steps 101, 102, 103 and 104. The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention as defined by the appended claims.

Claims: A semiconductor integrated circuit device including: a plurality of cells (14; 25), which are either all logic cells (14) or all identically-patterned basic cells (25), arranged in linear arrays (12, 13; 62, 63; 26), each array having a plurality of the cells and each cell having at least one monitor point (15); select lines (16; 65) corresponding respectively to the arrays, each for delivering to its corresponding array a select signal used to select cells of that array; read lines (17; 64) for carrying monitor signals representative of logic states at the monitor points of the cells when the device is in use; and switch elements (18), each connected between one of the monitor points (15) and one of the read lines (17; 64) and also connected to one of the select lines (16; 65), such that when activated in response to receipt of such a select signal delivered by that select line, such a monitor signal, representative of the logic state at the monitor point concerned, is applied to the read line concerned; characterised in that at least one of the said arrays (13; 62, 63; 26) has first and second select lines (16; 65) corresponding thereto, the first select line serving to deliver a first select signal to a first switch element (18) connecting a first monitor point (15) of the array to one of the read lines (17; 64), and the second select line serving to deliver a second select signal to a second switch element connecting a second monitor point of the array to the same read line; the total number of the said select lines (16) and the said read lines (17) being less than the sum of the number of the said arrays (12, 13; 62, 63; 26) and the number of monitor points in the array having the most monitor points. A device as claimed in claim 1, wherein: each of the said arrays (12, 13; 19, 20; 26) extends in a first direction; the said select lines (16) extend in the said first direction; and the said read lines (17; 61) extend in a second direction perpendicular to the said first direction. A device as claimed in claim 2, wherein: the number of select lines (16) provided for each array is half the total number of monitor points of the cells of the array concerned or the whole number nearest to half that total number of monitor points; and the total number of read lines (16; 61) is half the number of monitor points in the array having the most monitor points or the whole number nearest to half that number of monitor points. A semiconductor integrated circuit device including: a plurality of cells (14; 25), which are either all logic cells (14) or all identically-patterned basic cells (25), arranged in linear arrays (12, 13; 62, 63; 26), each array having a plurality of the cells and each cell having at least one monitor point (15); select lines (16; 65) for delivering to the cells of the arrays select signals used to select those cells; read lines (17; 64) corresponding respectively to the arrays, each for carrying a monitor signal representative of the logic state at one of the monitor points of its corresponding array when the device is in use; and switch elements (18), each connected between one of the monitor points (15) and one of the read lines (17; 64) and also connected to one of the select lines (16; 65), such that when activated in response to receipt of such a select signal delivered by that select line, such a monitor signal, representative of the logic state at the monitor point concerned, is produced on the read line concerned; characterised in that: at least one of the said arrays (13; 62, 63; 26) has first and second read lines corresponding thereto; a first switch element connects a first monitor point of that array to the said first read line, and a second switch element connects a second monitor point of that array to the said second read line; and both the said first and second switch elements are connected to the same select line; the total number of the said select lines (16; 65) and the said read lines (17; 64) being less than the sum of the number of the said arrays (12, 13; 62, 63; 26) and the number of monitor points in the array having the most monitor points. A device as claimed in claim 4, wherein: each of the said arrays (12, 13; 22, 23; 26) extends in a first direction; the said read lines (17) extend in the said first direction; and the said select lines (16; 61) extend in a second direction perpendicular to the said first direction. A device as claimed in claim 5, wherein: the number of read lines (17) provided for each array is half the total number of monitor points of the cells of the array concerned or the whole number nearest to half that total number of monitor points; and the total number of select lines (16; 61) is half the number of monitor points in the array having the most monitor points or the whole number nearest to half that total number of monitor points. A device as claimed in any preceding claim, wherein each of the said switch elements (18) includes a transistor. A device as claimed in claim 1 or 4, wherein: the said arrays (62, 63) include respective first and second arrays (62) which are positioned side-by-side in a first direction; the read lines (64) provided for carrying monitor signals from the first and second arrays (62) have respective first portions that extend in the said first direction; and the said first and second arrays (62) share the same select lines (65), which lines also run in the said first direction. A device as claimed in claim 8, wherein: the said arrays (62, 63) further include a third array (63) which runs in a second direction perpendicular to the said first direction; and the said read lines (64) provided for carrying monitor signals from the said first and second arrays (62) are also employed to carry monitor signals from the third array (63) and have respective second portions that extend in the said second direction. A device as claimed in claim 8 or 9, further including a megacell (66), the said select lines (65) and the said read lines (64) being routed so as to extend around the said megacell. A semiconductor integrated circuit device including: a first device portion (21), being a semiconductor integrated circuit device as claimed in claim 1 in which the said arrays (19, 20) extend in a first direction; and a second device portion (24), being a semiconductor integrated circuit device as claimed in claim 4 in which the said arrays (22, 23) extend in a second direction perpendicular to the said first direction, the said first and second device portions (21, 24) being positioned side-by-side in the said first direction; the select lines (16) of the first device portion (21) being coupled respectively to the select lines of the second device portion (24). A semiconductor integrated circuit device including: a first device portion (21), being a semiconductor integrated circuit device as claimed in claim 1 in which the said arrays (19, 20) extend in a first direction; and a second device portion (24), being a semiconductor integrated circuit device as claimed in claim 4 in which the said arrays (22, 23) extend in a second direction perpendicular to the said first direction, the said first and second device portions (21, 24) being positioned side-by-side in the said second direction; the read lines (17) of the second device portion (24) being coupled respectively to the read lines of the first device portion (21). A device as claimed in claim 11 or 12, wherein the number of select lines (16) provided for each array in the said first device portion (21) is half the total number of monitor points (15) of the cells of the array (19, 20) concerned or the whole number nearest to half that total number of monitor points; and the total number of read lines (17) in the said first device portion (21) is half the number of monitor points in the array (19, 20) of the first device portion having the most monitor points or the whole number nearest to half that number of monitor points. A device as claimed in claim 11, 12 or 13, wherein the number of read lines (17) provided for each array (22, 23) in the said second device portion (24) is half the total number of monitor points (15) of the cells of the array concerned or the whole number nearest to half that total number of monitor points. A device as claimed in claim 2 or 5, wherein the said cells are basic cells (25) and the said first and second monitor points (15) belong respectively to two adjacent basic cells (25) of the same array (26), which two adjacent cells constitute a basic cell group (60).

Inventors: KIKUCHI HIDEO, TANIZAWA TETSU, KIKUCHI, HIDEO, TANIZAWA, TETSU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G06F11
IPC codes: H01L21, G01R31, G11C17, G06F11, H01L23