Variable length code demodulating apparatus and address control method thereof

Abstract: In a variable length code demodulating apparatus, a bit length of the variable length code is examined to determine if it is longer than a specified bit length. The most significant bits equal in number to the specified bit length is selected from variable length codes which have a bit length exceeding the specified bit length. The most significant bits of the variable length code are converted to a conversion code which replaces the most significant lists. The conversion code has a bit length less than the specified bit length. An addressing to a conversion table in which each fixed length code is stored corresponding to each variable length code is performed on the basis of the least significant lists and the conversion code substituting for the most significant lists.

Description: The present invention relates, in general, to a variable length code demodulating apparatus. In particular it relates to a variable length code demodulating apparatus suited for image data compression. Recently, some remarkable progress has been made in image data compression techniques. In such image data compression techniques, in order to raise the efficiency of digital transmission and recording etc., the image data is encoded with a smaller bit rate. Examples of this technique are the predictive coding technique and transform coding technique, etc. These techniques are described in detail in "Multidimensional Processing of TV Pictures", by T. Fukinuki, published by Nikkan Kogyo Shinbunsha, June 25, 1984. In addition, a further image data compression can be achieved by performing variable length encoding on the code compressed by such encoding processes. The variable length encoding consists in varying the encoded bit width in accordance with the frequency of occurrence of the code. By this means, a smaller bit rate can be obtained than with fixed length coding. Next, as an example of variable length coding, a description will be given with reference to Figs. 3a and 3b of a method of generating Huffman codes. Let us know assume that t fixed length codes S₁, S₁, ... S t are converted into Huffman codes. Figs. 3a and 3b show an example for the case where t=6. First of all, these codes S₁ to S₆ are arranged in order of the magnitude of the frequency of their occurrence (the probability of occurrence). The probabilities of occurrence of codes S₁ to S₆ are respectively 0.35, 0.20, 0.15, 0.15, 0.10 and 0.05 as shown in Fig. 3a. They are therefore arranged in the order of codes S₁ to S₆. Next, taking the two codes whose probability of occurrence is smallest as one group, their composite probability (the sum of the two probabilities of occurrence) is found. In Fig. 3a, codes S₆ and S₅ have the smallest probability of occurrence, and their composite probability is 0.15. Next, this group and the other codes are arranged in order of magnitude of their probabilities of occurrence (or composite probability). The two codes (or groups) whose probability of occurrence (or composite probability) is smallest are taken as a new group, and the composite probability of this group is found. Subsequently, this process is repeated until a relisting with the composite probability of 1 has been effected as shown in Fig. 3a. Next, using Fig. 3a, a code tree as shown in Fig. 3b is compiled. "0" and "1" are then allocated in accordance with the branching of this code tree. In Fig. 3b, the upper branches are allocated "0", while the lower branches are allocated "1". The Huffman codes are obtained by following this branching. For example, as shown by the thick line in Fig. 3b, the fixed length code S₄ passes along a branch "0", along a branch "1", and finally along a branch "0", so it is converted to the Huffman code "010". The Huffman codes of the codes S₁ to S₆ found in this way are shown in Table 1 below. Code Huffman code Code Huffman Code S₁ 00 S₄ 010 S₂ 10 S₅ 0110 S₃ 11 S₆ 0111 As shown in Table 1, codes whose probability of occurrence is high are converted into Huffman codes of short bit length, while codes whose probability of occurrence is low are converted into Huffman codes of longer bit length. In this way, the overall bit rate can be reduced. In general, to demodulate such variable length code into fixed length code, a conversion table embedded in a solid state memory such as a ROM is used. In Fig. 3a, for convenience in explanation, the maximum bit number of the variable length code (Huffman code) was taken as being 4 bits, but, in an actual image data signal, the maximum bit number is very large, for example, 15 bits. Accordingly, some proposals have been made to reduce the capacity of the conversion table. As an example, this type of variable length code demodulating apparatus is described in Japanese Patent Disclosure (Kokai) No. 63-52578. This technique discloses that the bit length of coded data which is input is set as one n-th of the maximum bit length of coded data, and the conversion table is read out n times. Thus, the capacity of the conversion table can be reduced. In the variable length code demodulating apparatus described above, however, a Run-Length code is used in which two values are employed consisting of white and black. Such a technique requires a long transaction time for conversion due to numerous read outs of the conversion table. US-A-3,883,847 discloses an apparatus for decoding Huffman codes, comprising: a first conversion table for converting the most significant bits having a selected bit length of said variable length code either into a secondary table identification code or into a first fixed length code; a plurality of secondary tables selectable on the basis of the secondary table identification code, the least significant bit or bits of the variable length code being supplied as an address to the selected secondary table, and the selected secondary table supplying a second fixed length code as an output; and selector means for selecting either said first or second fixed length code as an output of said apparatus, depending on the length of said variable length code. According to a first aspect of the present invention, there is provided a variable length code demodulating apparatus for converting an input variable length code to a fixed length output code, the apparatus comprising: a first conversion table (22); a second conversion table (23); and means for supplying the most significant bits of the input code as an address to the first conversion table, and for supplying the remaining least significant bits of the input code as a partial address to the second conversion table, the most significant bits having a fixed bit length equal to a selected bit length smaller than a maximum number of bits in said variable length code, said first conversion table generating, in response to the most significant bits of each variable length code, a first fixed length code, and a conversion code having a bit length smaller than said selected bit length, the conversion code being supplied to the second conversion table as a partial address thereto, and said second conversion table generating, in response to the conversion code and the least significant bits of the input code, a second fixed length code, and the apparatus further comprising selector means (24) connected to receive said first and second fixed length codes and operable to select, as said fixed length output code, said first fixed length code if the bit length of said variable length code does not exceed said selected bit length, and to select said second fixed length code if the bit length of said variable length code exceeds said selected bit length. According to a second aspect of the present invention, there is provided a variable length code demodulating apparatus for converting an input variable length code to a fixed length output code, the apparatus comprising: a first conversion table (T1) ; second to (m-1)th conversion tables (T2 - Tm-1), m being greater than 2 ; an m-th conversion table (Tm) ; means for supplying a first group of most significant bits of the input code as an address to the first conversion table; means for supplying second to (m-1)th groups of most significant bits of the input code as respective partial addresses to the second to (m-1)th conversion tables; and means for supplying the remaining least significant bits of the input code as a partial address to the m-th conversion table, the first to (m-1)th groups of most significant bits each having a bit length equal to a respective selected bit length smaller than a maximum number of bits in said variable length code, said first conversion table generating, in response to the first group of most significant bits of each variable length code, a first fixed length code, and a first conversion code having a bit length smaller than said respective selected bit length, the conversion code being supplied to the second conversion table as a partial address thereto, said second to (m-1)th conversion tables each generating, in response to the respective group of most significant bits of each variable length code and the respective conversion code supplied thereto, a respective second to (m-l)th fixed length code, and a respective second to (m-1)th conversion code having a bit length smaller than said respective selected bit length, each of the second to (m-1)th conversion codes being supplied to a respective one of the third to m-th conversion tables as a partial address thereto, and said m-th conversion table generating, in response to the least significant bits of the input code and the conversion code supplied thereto, an m-th fixed length code, and the apparatus further comprising first to (m-1)th selector means (SE1 - SEm-1), the (m-1)th selector means being connected to receive said (m-l)th and m-th fixed length codes and operable to select, as an intermediate fixed length output code, said (m-1)th fixed length code if the bit length of said variable length code does not exceed a total of the first to (m-l)th selected bit lengths, and to select said m-th fixed length code if the bit length of said variable length code exceeds said total of the first to (m-1)th selected bit lengths, each k-th of the second to (m-2)th selector means being connected to receive said k-th fixed length code and the intermediate fixed length output code from the (k+1)th selector means and operable to select, as its intermediate fixed length output code, said k-th fixed length code if the bit length of said variable length code does not exceed a total of the first to k-th selected bit lengths, and to select said intermediate fixed length output code from the (k+1)th selector means if the bit length of said variable length code exceeds said total of the first to k-th selected bit lengths, the first selector means being connected to receive said first fixed length code and the intermediate fixed length output code from the second selector means and operable to select, as the fixed length output code of the apparatus, said first fixed length code if the bit length of said variable length code does not exceed the first selected bit length, and to select said intermediate fixed length output code from the second selector means if the bit length of said variable length code exceeds the first selected bit length. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a basic block diagram of the variable length code demodulating apparatus according to the present invention; Fig. 2 is a basic block diagram of the variable length code demodulating apparatus of other embodiment of the present invention; and Fig. 3 is a diagram given in explanation of the Huffman codes wherein Fig. 3a shows the process of generating Huffman code, and Fig. 3b shows a Huffman code tree. The preferred embodiment of the present invention will now be described in more detail with reference to the accompanying drawings. In Fig. 1, at an input terminal 21, there is input a variable length code of, for example, a maximum bit number of 15 bits. The most significant 8 bits of this variable length code are supplied to an address input terminal of a conversion table 22, while the least significant 7 bits are supplied to an address input terminal of a conversion table 23. The addresses in the conversion tables 22 or 23 are specified by the data that is input at the address input terminal, and the data stored at the designated address is output. The conversion table 22 has addresses corresponding to all'variable length codes of 8 bits or less. At each of these addresses, there is respectively stored a fixed length 9-bit code corresponding to each of these variable length codes of 8 bits or less. The conversion table 22 also has addresses corresponding to the most significant 8 bits of variable length codes of 9 bits or more. At these addresses, there are stored 5 bit conversion codes respectively corresponding to these variable length codes. In addition, the conversion table 22 has a region that stores a 1-bit length code. If this length code is "1", this indicates that the variable length code is 8 bits or less. If it is "0", this indicates that the variable length code is longer than 8 bits. Thus, the conversion table 22 is constituted by 2⁸x (9+5+1) bits. As will be clear from the above example of Huffman coding, the most significant n bits of a variable length code of bit length longer than n bits (where n is a natural number) are necessarily different from the patterns of variable length codes of n bits or less. For example, in the Huffman codes of Table 1 above, the patterns "00", "10" of the Huffman codes of S₁ and S₂ are not present in the most significant 2 bits of the Huffman codes of S₃, S₄, S₅ and S₆. Consequently, by using variable length codes of 8 bits or less or the most significant 8 bits of a variable length code of 9 bits or more to designate different addresses, a length code can be obtained whereby it is possible to determine, from its address, whether or not the variable length code is 8 bits or less. In fact, the number of patterns of the most significant 8 bits of variable length codes of 9 bits or more is comparatively small. Although there are some differences depending on the system, these patterns can be adequately distinguished by 5 bits (32 types). For this reason, in this embodiment, the bit number of the conversion code is set at 5 bits. Thus, the conversion table 22 outputs the length code (1-bit) to a control input terminal 26 of a selector 24. The conversion table 22 also outputs the fixed length code to the other input terminal of the selector 24. The conversion table 22 outputs the 5-bit conversion code as the most significant bits of the address of a conversion table 23. Thus, the conversion table 22 supplies the 5-bit code to the address input terminal of the conversion table 23, together with the least significant 7 bits from the input terminal 21. On the other hand, the conversion table 23 has addresses corresponding to these 12 bit codes. At each address, there is stored a fixed length 9-bit data code corresponding to the variable length input code of 9 bits or more. Thus, the conversion table 23 is constituted of 2¹² x 9 bits. The conversion table 23 outputs the fixed length code stored at the designated address to a second input terminal 30 of the selector 24. The selector 24 is arranged such that, when a length code "1" is input, it outputs the fixed length code that was input at the first input terminal 28 (coming from conversion table 22), while, when a length code "0" is input, it outputs the fixed length code that was input at the second input terminal 30 (coming from conversion table 23). Next, the operation of the variable length code demodulating apparatus constructed as above will be described. A variable length code of 15 bits is input through the input terminal 21. The most significant 8 bits of the variable length code are supplied to the conversion table 22. The least significant 7 bits are input at the address input terminal of the conversion table 23 as the least significant bits of the 5-bit conversion code from the conversion table 22. Now assume that the variable length code is constituted by 8 bits or less. In this case, a length code "1" is output by the conversion table 22 to the control input terminal 26 of the selector 24. Furthermore, the 9-bit fixed length code stored at the address indicated by this variable length code is output by the conversion table 22 to the first input terminal 28 of the selector 24. Since the selector 24 inputs "1" at its control input terminal 26, it outputs the fixed length code at the first input terminal 28. In contrast, if the variable length code is constituted by 9 bits or more, a length code "0" is output by the conversion table 22. The conversion table 22 outputs the 5-bit conversion code stored at the address corresponding to the most significant 8 bits. Thus, a 12-bit code is supplied to the address input terminal of the conversion table 23. The address of the conversion table 23 is thereby designated, and the 9-bit fixed length code corresponding to the variable length code of 9 bits or more is output to the second input terminal 30 of the selector 24. Since the selector 24 inputs "0" at its control input terminal 26, it outputs the fixed length code from the second input terminal 30. The total bit number of the conversion tables is 2⁸ x 15 + 2¹² x 9 = 40 (k bits), which is reduced to less than 1/7 of that used conventionally. Thus, the circuit size can be greatly reduced. In this embodiment, the patterns of the most significant 8 bits of variable length codes of 9 bits or more are necessarily different from the patterns of variable length codes of 8 bits or less. Furthermore, the number of these patterns is extremely small. Therefore, the most significant 8 bits of variable length codes of 9 bits or more are converted to a 5-bit conversion code, which is used as the most significant bits. As a result, the total number of bits of the conversion tables 22 and 23 can be greatly reduced due to the fact that the demodulation of variable length codes of 9 bits or more is performed by designating the address of the conversion table 23 by a 12-bit code. Obviously, the maximum bit length of the variable length code is not restricted to being 15 bits. Also, instead of supplying respectively the most significant 8 bits and least significant 7 bits to the two conversion tables, it is possible to split the variable length code at a suitably chosen bit number such as to obtain an optimum efficiency of reduction of the number of bits. Fig. 2 shows a second embodiment of this invention. In the second embodiment, the same numerals are applied to similar elements in the first embodiment, and therefore the detailed description thereof are not repeated. The second embodiment is an example where m conversion tables are employed. The variable length code from the input terminal 21 is divided into first to (m-1)-th (where m is a natural number) most significant bits and least significant bits, which are supplied to respective conversion tables T₁ to T m . From the conversion tables T₁ to T m-1 , first to (m-1)-th length codes and fixed length codes are respectively supplied to selectors SE₁ to SE m-1 . Furthermore, from the conversion tables T₁ to T m-1 , first to (m-1)-th conversion codes are respectively supplied to the conversion tables T₂ to T m of the next stage. The fixed length code from the conversion table T m is output to selector SE m-1 . The fixed length codes which are output from the selectors SE₂ to SE m-1 are respectively input to the selectors SE₁ to SE m-2 of the front stage. Thus, from the output terminal of the selector SE₁, a demodulated fixed length code is output corresponding to the variable length code. As described above, with this invention, the total bit length of the conversion tables can be greatly reduced. Numerous other modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the present invention can be practiced in a manner other than as specifically described herein.

Claims: A variable length code demodulating apparatus for converting an input variable length code to a fixed length output code, the apparatus comprising: a first conversion table (22); a second conversion table (23); and means for supplying the most significant bits of the input code as an address to the first conversion table, and for supplying the remaining least significant bits of the input code as a partial address to the second conversion table, the most significant bits having a fixed bit length equal to a selected bit length smaller than a maximum number of bits in said variable length code, said first conversion table generating, in response to the most significant bits of each variable length code, a first fixed length code, and a conversion code having a bit length smaller than said selected bit length, the conversion code being supplied to the second conversion table as a partial address thereto, and said second conversion table generating, in response to the conversion code and the least significant bits of the input code, a second fixed length code, and the apparatus further comprising selector means (24) connected to receive said first and second fixed length codes and operable to select, as said fixed length output code, said first fixed length code if the bit length of said variable length code does not exceed said selected bit length, and to select said second fixed length code if the bit length of said variable length code exceeds said selected bit length. A variable length code demodulating apparatus for converting an input variable length code to a fixed length output code, the apparatus comprising: a first conversion table (T1); second to (m-1)th conversion tables (T2 - Tm-1), m being greater than 2 ; an m-th conversion table (Tm) ; means for supplying a first group of most significant bits of the input code as an address to the first conversion table; means for supplying second to (m-1)th groups of most significant bits of the input code as respective partial addresses to the second to (m-1)th conversion tables; and means for supplying the remaining least significant bits of the input code as a partial address to the m-th conversion table, the first to (m-1)th groups of most significant bits each having a bit length equal to a respective selected bit length smaller than a maximum number of bits in said variable length code, said first conversion table generating, in response to the first group of most significant bits of each variable length code, a first fixed length code, and a first conversion code having a bit length smaller than said respective selected bit length, the conversion code being supplied to the second conversion table as a partial address thereto, said second to (m-1)th conversion tables each generating, in response to the respective group of most significant bits of each variable length code and the respective conversion code supplied thereto, a respective second to (m-1)th fixed length code, and a respective second to (m-1)th conversion code having a bit length smaller than said respective selected bit length, each of the second to (m-1)th conversion codes being supplied to a respective one of the third to m-th conversion tables as a partial address thereto, and said m-th conversion table generating, in response to the least significant bits of the input code and the conversion code supplied thereto, an m-th fixed length code, and the apparatus further comprising first to (m-1)th selector means (SE1 - SEm-1), the (m-1)th selector means being connected to receive said (m-1)th and m-th fixed length codes and operable to select, as an intermediate fixed length output code, said (m-1)th fixed length code if the bit length of said variable length code does not exceed a total of the first to (m-1)th selected bit lengths, and to select said m-th fixed length code if the bit length of said variable length code exceeds said total of the first to (m-1)th selected bit lengths, each k-th of the second to (m-2)th selector means being connected to receive said k-th fixed length code and the intermediate fixed length output code from the (k+1)th selector means and operable to select, as its intermediate fixed length output code, said k-th fixed length code if the bit length of said variable length code does not exceed a total of the first to k-th selected bit lengths, and to select said intermediate fixed length output code from the (k+1)th selector means if the bit length of said variable length code exceeds said total of the first to k-th selected bit lengths, the first selector means being connected to receive said first fixed length code and the intermediate fixed length output code from the second selector means and operable to select, as the fixed length output code of the apparatus, said first fixed length code if the bit length of said variable length code does not exceed the first selected bit length, and to select said intermediate fixed length output code from the second selector means if the bit length of said variable length code exceeds the first selected bit length. Variable length code demodulating apparatus as claimed in claim 1 or 2, wherein said first conversion table comprises a read only memory. Variable length code demodulating apparatus as claimed in claim 1, wherein the second conversion table comprises a read only memory. Variable length code demodulating apparatus as claimed in claim 2, wherein the second to m-th conversion tables comprise read only memories. Variable length code demodulating apparatus as claimed in any preceding claim, wherein said variable length code comprises a Huffman code.

Inventors: KONISHI KAZUO C O INTELL PROPE, KONISHI, KAZUO, C/O INTELL. PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H03M7
IPC codes: H03M7