Semiconductor device having E2PROM and EPROM in one chip

Abstract: An E²PROM and an EPROM are formed on the same substrate. An E²PROM memory cell has a floating gate (6) and a control gate (10). A tunnel insulating film (5′) is formed between the floating gate (6) and source/drain regions (3′, 4), thereby constituting a memory cell of an "FLOTOX" type. An EPROM memory cell has a floating gate (16) and a control gate (18), thus constituting a memory cell of an "SAMOS" type.

Description: The present invention relates to a semiconductor and, more particularly, to a semiconductor device having an E 2 PROM and an EPROM in one chip. Reference is made to Patent Abstracts of Japan, vol. 8, no. 1, (P-246)[1438] 6.1.84; & JP-A-58 166 596, which discloses an E 2 PROM cell and an EPROM cell integrated on the same P-type substrate, the two memory cells sharing a common n-type source and a common control gate. In US-A-4 393 474, individual DRAM and EPROM memories are integrated on a common semiconductor substrate. US-A-4 833 096 discloses techniques for simultaneously growing gate oxide films on the first layer of the layers comprising an E 2 PROM memory cell (i.e., on a floating gate formed of polysilicon) and on a substrate formed of silicon respectively, for employing a second polysilicon layer as a gate of a MOSFET in a peripheral circuit of the E 2 PROM memory cell, and for arranging a select gate in the E 2 PROM memory cell. In a known conventional one-chip microcomputer, a RAM and a ROM are formed on one chip. In such a one-chip microcomputer having both RAM and ROM mounted on one chip, the RAM is constituted by an SRAM, and the ROM is constituted by an EPROM or the like. An area per SRAM memory cell, however, is very large. For this reason, if the RAM is constituted by an SRAM, the area occupied by the RAM in one chip is increased, or the storage capacity of the RAM is undesirably decreased. It is an object of the present invention to decrease the area occupied by a RAM in one chip and to increase the storage capacity of the RAM. In order to achieve the above object, according to the present invention, there is provided a semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface, first, second, third and fourth semiconductor regions of a second conductivity type which are separately provided in a major surface region of said substrate, first carrier storage means provided above said substrate between said first and second semiconductor regions, for storing carriers, said first carrier storage means comprising a first conductor having a sheet resistance ρ s2, first insulating means provided between said first carrier storage means and said substrate, for electrically insulating said first carrier storage means from said substrate, a first control gate layer provided above said first carrier storage means, said first control gate layer comprising a second conductor having a sheet resistance ρ s6, second insulating means provided between said first control gate layer and said first carrier storage means and insulating said first control gate layer from said first carrier storage means, second carrier storage means provided above said substrate between said third and fourth semiconductor regions and provided above said fourth semiconductor region so as to partly overlap said fourth semiconductor region, for storing carriers, said second carrier storage means comprising a third conductor having a sheet resistance ρ s1, third insulating means provided between said second carrier storage means and said substrate and electrically insulating said second carrier storage means from said substrate and said fourth semiconductor region, a second control gate layer provided above said second carrier storage means, said second control gate layer comprising a fourth conductor having a sheet resistance ρ s5, fourth insulating means provided between said second gate layer and said second carrier storage means and insulating said second control gate layer from said second carrier storage means, and tunnelling means provided in said third insulating means between said fourth semiconductor region and said second carrier storage means, for allowing carriers to tunnel between said second carrier storage means and said fourth semiconductor region, an impurity concentration of said third conductor of said second carrier storage means being lower than that of said first conductor of said first carrier storage means. According to the semiconductor device having the above-described arrangement, first and second carrier storage layers are arranged. A tunnel insulating film is formed on a third insulating layer between the second carrier storage layer and a fourth semiconductor region serving as a source/drain region. With this arrangement, carriers can be electrically injected and extracted in and from the second carrier storage layer. That is, the second carrier storage layer serves as a floating gate of an E 2 PROM memory cell. The E 2 PROM capable of electrically writing and erasing data is used as a RAM. The area of one E 2 PROM memory cell is smaller than that of one SRAM memory cell. Therefore, if the RAM is constituted by E 2 PROM memory cells, the area occupied by the RAM in one chip can be decreased, and the storage capacity of the RAM can be increased. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a sectional view showing a first semiconductor device not forming an embodiment of the present invention; Figs. 2A to 2H are sectional views showing the steps in manufacturing the semiconductor device of Fig. 1; Fig. 3 is a plan view showing the device in the step in Fig. 2F; Fig. 4 is a sectional view showing a second semiconductor device not forming an embodiment of the present invention; Figs. 5A to 5D are sectional views showina the steps in manufacturing the second semiconductor device; Fig. 6 is a plan view showing the device in the step shown in Fig. 5B; Fig. 7 is a sectional view showing a third semiconductor device not forming an embodiment of the present invention; Figs. 8A to 8F are sectional views showing the steps in manufacturing the third semiconductor device; Fig. 9 is a sectional view showing a semiconductor device according to the first embodiment of the present invention; Figs. 10A to 10C are sectional views showing the steps in manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. 11 is a plan view showing the device in the step shown in Fig. 10C; Fig. 12 is a sectional view showing a semiconductor device according to the second embodiment of the present invention; Figs. 13A to 13C are sectional views showing the steps in manufacturing the semiconductor device according to the second embodiment of the present invention; Fig. 14 is a plan view showing the device in the step shown in Fig. 13C; Fig. 15 is a sectional view showing a semiconductor device according to the third embodiment of the present invention; Figs. 16A to 16D are sectional views showing the steps in manufacturing the semiconductor device according to the third embodiment of the present invention; Fig. 17 is a sectional view showing a fourth semiconductor device not forming an embodiment of the present invention; Figs. 18A to 18E are sectional views showing the steps in manufacturing this fourth semiconductor device; Fig. 19 is a plan view showing the device in the step shown in Fig. 18B; Fig. 20 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention; Figs. 21A to 21D are sectional views showing the steps in manufacturing the semiconductor device according to the fourth embodiment of the present invention; Fig. 22 is a plan view showing the device in the step shown in Fig. 21C; Fig. 23 is a sectional view showing a fifth semiconductor device not forming an embodiment of the present invention; Figs. 24A to 24E are sectional views showing the steps in manufacturing the fifth semiconductor device; Fig. 25 is a plan view showing the device in the step shown in Fig. 24B; Fig. 26 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention; Figs. 27A to 27D are sectional views showing the steps in manufacturing the semiconductor device according to the fifth embodiment of the present invention; Fig. 28 is a plan view showing the device in the step shown in Fig. 27C; Fig. 29 is a sectional view showing a sixth semiconductor device not forming an embodiment of the present invention; Figs. 30A to 30F are sectional views showing the steps in manufacturing the sixth semiconductor device; Fig. 31 is a sectional view showing a semiconductor device according to the sixth embodiment of the present invention; and Fig. 32A to 32D are sectional views showing the steps in manufacturing the semiconductor device according to the sixth embodiment of the present invention. Semiconductor devices each having an E 2 PROM and an EPROM in one chip, some not forming embodiments of the invention and others according to embodiments of the present invention, will be described below with reference to the accompanying drawings. Fig. 1 is a sectional view showing a semiconductor device not forming an embodiment of the present invention. As shown in Fig. 1, field oxide films 2 are formed on a semiconductor substrate, e.g., a silicon substrate 1. With this arrangement, element isolation is performed. An element structure in an E 2 PROM memory cell region will be described first. In the upper surface region of the substrate 1, source/drain regions 3 and 3' each having a conductivity type opposite to that of the substrate 1, and an impurity layer 4 are formed. The impurity layer 4 is in contact with the source/drain region 3'. The impurity layer 4 and the source/drain region 3' constitute an integral diffusion region. A first gate insulating film 5 is formed on the substrate 1 between one of the source/drain regions 3 and the source/drain region 3'. The first gate insulating film 5 consists of, e.g., a silicon oxide film, and has a thickness of, e.g., about 430 Å (1Å = 0.1 nm). A tunnel insulating film 5' is formed on the impurity layer 4. The tunnel insulating film 5' consists of, e.g., a silicon oxide film having a thickness of about 100 Å. A floating gate 6 consisting of a first polysilicon layer is formed on the first gate insulating film 5 and the tunnel insulating film 5'. A gate insulating film 7 is formed on the substrate 1 between the other source/drain region 3 and the source/drain region 3'. The gate insulating film 7 consists of, e.g., a silicon oxide film and has a thickness of, e.g., about 430 Å. The thickness of the film 7 is almost the same as that of the first gate insulating film 5. A gate 8 consisting of the first polysilicon layer is formed on the gate insulating film 7. A transistor which has this gate 8 is a select transistor for selecting an E 2 PROM memory cell. In this specification, a transistor having the gate 8 and the gate 8 will be respectively referred to as a "select transistor" and a "select gate" hereinafter. In addition, a transistor which has the floating gate 6 and a control gate 10 will be referred to as a "memory cell transistor" hereinafter. A second gate insulating film 9 consisting of, e.g., a silicon oxide film is formed on the floating gate 6. The control gate 10 consisting of a second polysilicon layer is formed on the second gate insulating film 9. An insulating interlayer 11 is formed on the entire upper surface of the device. Contact holes 12 are formed in the insulating interlayer 11 so as to communicate with the source/drain regions 3. Wires 12′ consisting of, e.g., aluminum are respectively formed in the contact holes 12. A surface protective film 13 is formed on the insulating interlayer 11. An element structure in an EPROM memory cell region will be described below. In the upper surface of the substrate 1, source/drain regions 14 each having a conductivity type opposite to that of the substrate 1 are formed. A first gate insulating film 15 is formed on the substrate 1 between the source/drain regions 14. A first gate insulating film 15 consists of, e.g., a silicon oxide film and has a thickness of about 250 Å. A floating gate 16 consisting of a first polysilicon layer is formed on the first gate insulating film 15. A second gate insulating film 17 consisting of, e.g., a silicon oxide film is formed on the floating gate 16. A control gate 18 consisting of a second polysilicon layer is formed on the second gate insulting film 17. The insulating interlayer 11 is formed on the upper entire surface of the device. Contact holes 19 are formed in the insulating interlayer 11 so as to communicate with the source/drain regions 14. Wires 19′ consisting of, e.g., aluminum are respectively formed in the contact holes 19. The surface protective film 13 is formed on the insulating interlayer 11. Note that each of the E 2 PROM and the EPROM shown in Fig. 1 is of a so-called "two-bus scheme" in which the wires are respectively connected to the source and drain. An element structure in a MOSFET region will be described below. In the upper surface of the substrate 1, source/drain regions 20 each having a conductivity type opposite to that of the substrate 1 are formed. A gate insulating film 21 is formed on the substrate 1 between the source/drain regions 20. This gate insulating film 21 consists of, e.g., a silicon oxide film and has a thickness of, e.g., about 250 Å. A gate 22 of a MOSFET constituting a peripheral circuit (e.g., various types of decoders), a logic circuit, or the like is formed on the gate insulating film 21. The gate 22 consists of a first polysilicon layer. An insulating interlayer 11 is formed on the entire upper surface of the device. Contact holes 23 consisting of, e.g., aluminum are in the insulating interlayer 11 so as to communicate with the source/drain regions 20. Wires 23′ consisting of, e.g., aluminum are respectively formed in the contact holes 23. The surface protective film 13 is formed on the insulating interlayer 11. In the semiconductor device having the above-described arrangement, a memory cell having the floating gate 6, which is formed above the impurity layer 4 such that they partly overlap each other, is formed. The tunnel insulating film 5′ having a thickness of about 100 Å is formed between the floating gate 6 and the impurity layer 4 so as to constitute a nonvolatile memory cell called a "FLOTOX (floating-gate tunnel oxide)". Data is stored depending on whether the memory cell transistor is turned on in accordance with the charge state of the floating gate 6. Carriers (electrons) are injected into the floating gate 6 by, e.g., applying a positive potential to the control gate 10 and grounding the source/drain region 3′. With this operation, the electrons from the source/drain region 3′ tunnel through the tunnel insulating film 5′ and are injected into the floating gate 6. Carriers (electrons) are extracted from the floating gate 6 by, e.g., applying a positive potential to the source/drain region 3′ and grounding the control gate 10. With this operation, the electrons tunnel through the tunnel insulating film 5′ and are injected into the source/drain region 3′. The memory cell having the floating gate 6, therefore, can electrically write and erase data. In addition, the semiconductor device having the above-described arrangement includes a memory cell having the floating gate 16 formed between the control gate 18 and the substrate 1 and having no tunnel insulating film. A memory cell of this type is a nonvolatile memory cell called an "SAMOS (Stacked-gate Avalanche-injection MOS)". The memory cell has no tunnel insulating film. For this reason, injection of carriers (electrons) into the floating gate 16 is performed by, e.g., generating hot electrons in the substrate 1 (channel) between the source and the drain, applying a positive potential to the control gate 18, and injecting the hot electrons into the floating gate 16. Extraction of carriers (electrons) from the floating gate 16 is performed by, e.g., exciting electrons in the floating gate 16 upon radiation of ultraviolet rays, and causing the electrons to escape to the source/drain regions 14 and the like over the barrier of the gate insulating film 15. The memory cell having the floating gate 16, therefore, can electrically write data and can erase data by an erase method other than an electrical method, e.g., a method using ultraviolet rays or the like. According to such a semiconductor device, an E 2 PROM capable of electrically erasing data and an EPROM capable of erasing data by an erase method other than an electrical method are formed on the same substrate 1. That is, a semiconductor device having an E 2 PROM and an EPROM in one chip can be obtained. The above-described semiconductor device can be applied to, e.g., a one-chip microcomputer in which a RAM and a ROM are mounted together. Since an E 2 PROM is capable of electrically erasing data, it is used as a RAM, and an EPROM is used as a ROM. If a SRAM is constituted by E 2 PROM memory cells each having the above-described arrangement, the area occupied by the SRAM in one chip is decreased, and the packing density of the SRAM, i.e., the storage capacity, can be increased. This is because the area of one E 2 PROM memory cell is about 1/5 that of, e.g, one SRAM memory cell. In addition, a CPU or the like for accessing the ROM and the SRAM is constituted by a MOSFET. Furthermore, an E 2 PROM has the characteristics of both RAM and ROM. Therefore, even if the power source for the chip is turned off, data can be held. An SRAM cannot perform such a data holding operation after the power source is turned off. Moreover, since an E 2 PROM and an EPROM are formed on one chip, if a system or the like constituted by an E 2 PROM and an EPROM of different chips is constituted by the semiconductor device according to the present invention, these elements can be integrated into one chip. Therefore, a simple, high-performance system can be realized. A method of manufacturing the first semiconductor device will be described below with reference to Figs. 2A to 2H. Figs. 2A to 2H are sectional views showing the steps in manufacturing the first semiconductor device. The same reference numerals in Figs. 2A to 2H denote the same parts as in Fig. 1. As shown in Fig. 2A, field oxide films 2 are selectively formed on the upper surface of a silicon substrate 1 of, e.g., a p type by using, e.g., a LOCOS method, thus performing element isolation. First thermal oxide films 24 are formed on the exposed surface portions of the substrate.1 by, e.g., thermal oxidation. An n-type impurity layer 4 is formed at a predetermined position of the substrate 1 in an E 2 PROM memory cell region 100 by, e.g., photoetching and selective ion implantation of As. Note that reference numerals 102 and 104 respectively denote an EPROM memory cell and a MOSFET. As shown in Fig. 2B, the first thermal oxide films 24 formed in the regions 102 and 104 on the upper surface of the substrate 1 are removed to expose the upper surface of the substrate 1. As shown in Fig. 2C, second thermal oxide films 25 are formed on surface portions of the substrate 1 corresponding to the regions 102 and 104 by, e.g., thermal oxidation. At this time, the first thermal oxide film 24 is also grown to slightly increase its due to the heat generated during this thermal oxidation. As shown in Fig. 2D, a portion of the first thermal oxide film 24 on the impurity layer 4 is selectively removed by, e.g., photoetching. The portion from which the film 24 is removed is denoted by reference numeral 26. A third thermal oxide film 27 is then formed on a surface portion of the substrate 1 corresponding to the portion 26 by, e.g., thermal oxidation. Owing to the heat during the thermal oxidation, the first- and second thermal oxide films 24 and 25 are also grown, and their thicknesses are slightly increased. As shown in Fig. 2E, a first polysilicon layer 28 is formed on the entire upper surface of the device by, e.g., CVD. When the first polysilicon layer 28 is formed, the growth of the first to third thermal oxide films 24, 25, and 27 is stopped. At this time, the first, second, and third thermal oxide films 24, 25, and 27 respectively have thicknesses of, e.g., about 430 Å, 250 Å, and 100 Å. These thicknesses are not limited to the above values but may be set to be optimal values, respectively. Subsequently, phosphorus is diffused in the first polysilicon layer 28 by, e.g., POCℓ 3 to render it conductive so as to have a desired sheet resistance ρs. Instead of using the above-mentioned method, ion implantation of an impurity or doping of an impurity into the first polysilicon layer 28 may be performed in advance. As shown in Fig. 2F, the first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, a select gate pattern 28' and a gate pattern 28' of the MOSFET are formed. Fig. 3 is a plan view showing the device in this step. Fig. 2F is a sectional view taken along a line 2F - 2F in Fig. 3. As shown in Fig. 3, the first polysilicon layer 28 is patterned into the respective gate patterns 28'. With the above-mentioned etching, cell slits 29 for isolating the floating gate in units of memory cells are simultaneously formed. These cell slits are formed in the field oxide films 2. As shown in Fig. 2G, a fourth thermal oxide film 30 is formed on the upper surfaces of the first polysilicon layers 28 and the respective gate patterns 28' by, e.g., thermal oxidation. The fourth thermal oxide film 30 serves as second gate insulating films of the E 2 PROM memory cell and the EPROM memory cell. For this purpose, the thickness of the fourth thermal oxide film 30 is optimally set in accordance with the characteristics of the E 2 PROM memory cell and of the EPROM memory cell. A second polysilicon layer 31 is then formed on the entire upper surface of the device by, e.g., CVD. Phosphorus is diffused in the second polysilicon layer 31 to render it conductive so as to have a desired sheet resistance ρs. Instead of using the above-mentioned method, ion implantation of an impurity or doping of an impurity into the second polysilicon layer 31 may be performed in advance. As shown in Fig. 2H, a photoresist (not shown) is coated on the entire upper surface of the device. Portions of the photoresist (not shown) located on the region 104 and near the select transistor in the region 100 are selectively removed by photoetching. Subsequently, the second polysilicon layer 31 is selectively removed by using the photoresist (not shown) as a mask. The photoresist (not shown) is then peeled off. Another photoresist (not shown) is coated on the entire upper surface of the device. The control gate patterns of the E 2 PROM and EPROM memory cells are formed by photoetching using the photoresist (not shown). At this time, the upper surfaces of the region 104 and the select transistor are covered with the photoresist. Thereafter, the second polysilicon layer 31, the fourth thermal oxide film 30, and the first polysilicon layer 28 are sequentially etched. With this process, the following gates and films are formed in the region 100: the first gate insulating film 5 consisting of the first thermal oxide film 24; the tunnel insulating film 5' consisting of the third thermal oxide film 27; the floating gate 6 consisting of the first polysilicon layer 28; the second gate insulating film 9 consisting of the fourth thermal oxide film 30; and the control gate 10 consisting of the second polysilicon layer 31. In addition, the gate insulating film 7 consisting of the fourth thermal oxide film 30, and the select gate 8 consisting of the first polysilicon layer 28 are formed. The following gates and films are formed in the region 102: the gate insulating film 15 consisting of the second thermal oxide film; the floating gate 16 of the memory cell, which consists of the first polysilicon layer 28; the second gate insulating film 17 consisting of the fourth thermal oxide film; and the control gate 18 consisting of the second polysilicon layer 31. In the region 104, the gate insulating film 21 consisting of the second thermal oxide film 25, and the gate 22 consisting of the first polysilicon layer 28 are formed. Subsequently, for example, As ions 32 are implanted into the substrate 1 by using the gates 8, 10, 18, and 22 as masks. As shown in Fig. 1, the insulating interlayer 11 is then formed on the entire upper surface of the device by, e.g., CVD. The insulating interlayer 11 is selectively etched to form the contact holes 12, 19, and 23 communicating with predetermined portions of the device by, e.g., photoethcing. An aluminum film is formed on the entire upper surface of the resultant structure by, e.g., sputtering. The aluminum film is selectively etched by, e.g., photoetching to form the metal wires 12', 19', and 23'. Thereafter, the surface protective film 13 is formed on the entire upper surface of the device by, e.g., CVD. With the above-described steps, the first semiconductor device is manufactured. According to the manufacturing method described above, an E 2 PROM and an EPROM can be formed on the same substrate together. If the sheet resistances of the first and second polysilicon layers in the first embodiment are respectively represented by ρsA and ρsB, the sheet resistances of the respective conductive members are given as follows: floating gate 6: ρsA control gate 10: ρsB select gate 8: ρsA floating gate 16: ρsA control gate 18: ρsB gate 22: ρsA Fig. 4 is a sectional view showing a second semiconductor device not forming an embodiment of the present invention. The same reference numerals in Fig. 4 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 4, in the second semiconductor device, if the sheet resistances of the respective conductive members are given as follows: floating gate 6: ρs1 floating gate 16: ρs2 select gate 34: ρs3 gate 36: ρs4 control gate 10: ρs5 control gate 18: ρs6 then, the respective sheet resistances have the following relationships: ρs1 = ρs2 ρs3 = ρs4 = ρs5 = ρs6 ρs1 ≠ ρs3 According to the semiconductor device having the above-described arrangement, for example, the sheet resistances of the control gate 10, the select gate 34, and the control gates 6 and 18 can be set to be smaller than those of the floating gates 6 and 16. That is, if the resistances of the select gate 34, the gate 36, and the control gates 10 and 18 can be set to be smaller than those of the floating gates 6 and 16, the resistance of each gate wire can be reduced. A method of manufacturing the second semiconductor device will be described with reference to Figs. 5A to 5D. Figs. 5A to 5D are sectional views showing the steps in manufacturing the second semiconductor device. The same reference numerals in Figs. 5A to 5D denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 5A is obtained through the above-described steps shown in Figs. 2A to 2E. The structure shown in Fig. 5A is identical to that shown in Fig. 2E. Subsequently, as shown in Fig. 5B, a first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, portions of the first polysilicon layer 28 which are located near the select transistor of the E 2 PROM and on a region 104 are removed. Fig. 6 is a plan view showing the structure at this time. Fig. 5B is a sectional view taken along a line 5B - 5B in Fig. 6. As shown in Fig. 6, when the first polysilicon layer 28 is selectively etched, cell slits 29 are simultaneously formed. As shown in Fig. 5C, a fourth thermal oxide film 30 is formed on the upper surface of the first polysilicon layer 28 and an exposed surface portion of a first substrate 1. The fourth thermal oxide film 30 serves as the second gate insulating films of the E 2 PROM and EPROM memory cells and as the gate insulating films of a select transistor and a MOSFET. A second polysilicon layer 31 is formed on the entire upper surface of the device by, e.g., CVD. Phosphorus is then diffused in the second polysilicon layer 31 by, e.g., POCℓ 3 to render it conductive so as to have a desired sheet resistance ρs. As shown in Fig. 5D, a photoresist (not shown) is coated on the entire upper surface of the device. A select gate pattern and a gate pattern of the MOSFET are formed by photoetching using the photoresist (not shown). At this time, the upper surfaces of a region 102 and the E 2 PROM memory transistor are covered with this photoresist. The second polysilicon layer 31 is etched by using the photoresist (not shown) as a mask. The photoresist is thenpeeled off. A photoresist (not shown) is coated on the entire upper surface of the device again. Control gate patterns of the E 2 PROM and EPROM memory cells are formed by photoetching using the photoresist (not shown). At this time, the upper surfaces of a region 104 and the select transistor are covered with the photoresist. The second polysilicon layer 31, the fourth thermal oxide 30, and the first polysilicon layer 28 are sequentially etched by using the photoresist (not shown). With this process, the following films and gates are formed in a region 100: a first gate insulating film 5 consisting of a first thermal oxide film 24; a tunnel insulating film 5' consisting of a second thermal oxide film 27; the floating gate 6 consisting of the first polysilicon layer 28; a second gate insulating film 9 consisting of the fourth thermal oxide film 30; and the control gate 10 consisting of the second polysilicon layer 31. In addition, a gate insulating film 33 consisting of the fourth oxide film 30, and the select gate 34 consisting of the second polysilicon layer 31 are formed. The following films and gates are formed in the region 102: a gate insulating film 15 consisting of the second thermal oxide film 30; the floating gate 16 consisting of the first polysilicon layer 28; a second gate insulating film 17 consisting of the fourth thermal oxide film; and the control gate 18 consisting of the second polysilicon layer 31. A gate insulating film 35 consisting of the fourth thermal oxide film 30, and the gate 36 consisting of the second polysilicon layer 28 are formed in the region 104. The subsequent steps are the same as those described in the first semiconductor device and hence a description thereof will be omitted. with the above-described steps, the second semiconductor device is manufactured. According to such a manufacturing method, the control gates 10 and 18, the select gate 34, and the gate 36 are set to have sheet resistances different from those of the floating gates 6 and 16, and hence the E 2 PROM and the EPROM can be formed on the same substrate. In the second semiconductor device, if the sheet resistances of the first and second polysilicon layers are respectively represented by ρsA and ρsB, the sheet resistances of the respective conductive members are given as follows: floating gate 6: ρsA control gate 10: ρsB select gate 8: ρsB floating gate 16: ρsA control gate 18: ρsB gate 22: ρsB Fig. 7 is a sectional view showing a third semiconductor device not forming an embodiment of the present invention. The same reference numerals in Fig. 7 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 7, in the second semiconductor device, the second gate insulating film of an E 2 PROM is constituted by a four-layered film consisting of an oxide film 38, a nitride film 39, an oxide film 40, and a nitride film 41, and the second gate insulating film of an EPROM is constituted by a four-layered film consisting of an oxide film 42, a nitride film 43, an oxide film 44, and a nitride film 45. The relationship between the sheet resistances of the respective conductive layers in the third semiconductor device is the same as that in the second semiconductor device. According to the semiconductor device having the above-described arrangement, the capacitance between a control gate and a floating gate can be increased. A method of manufacturing the third semiconductor device will be described below with reference to Fig. 8A to 8F. Figs. 8A to 8 are sectional views showing the steps in manufacturing the third semiconductor device. The same reference numerals in Figs. 8A to 8F denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 8A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 8A is identical to that shown in Fig. 2E. Subsequently, as shown in Fig. 8B, a first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, portions of the first polysilicon layer 28 which are located near the select transistor of an E 2 PROM and on a region 104 are removed. The surface obtained at this time is identical to, e.g., the surface shown in Fig. 6. As shown in Fig. 8C, a fifth thermal oxide film 47 is formed on the upper surface of the first polysilicon layer 28 and exposed surface portions of the substrate 1. For example, conditions for thermal oxidation are set such that a thermal oxide film having a thickness of about 350 Å is formed the upper surface of the first polysilicon layer 28 in an atmosphere of N 2 with a dilution ratio of 20% at a temperature 1,000°C. Subsequently, a first nitride film 48 is formed on the entire upper surface of the device to have a thickness of about 300 Å by, e.g., CVD. A sixth thermal oxide film 49 is formed on the upper surface of the first nitride film 48 by, e.g., thermal oxidation. At this time, conditions for the thermal oxidation are set such that a thermal oxide film having a thickness of about 60 Å is formed on the upper surface of the first nitride film 48 in an atmosphere of BOx (boron oxide) at a temperature of 950°C for 80 minutes. A second nitride film 50 is then formed on the entire upper surface of the device to have a thickness of about 300 Å by, e.g., CVD. As shown in Fig. 8D, the fifth thermal oxide film 47, the first nitride film 48, the sixth thermal oxide film 49, and the second nitride film 50 are selectively and sequentially etched by, e.g., photoetching. As a result, portions of the fifth thermal oxide film 47, of the first nitride film 48, of the sixth thermal oxide film 49, and of the second nitride film 50 which are located near the select transistor of the E 2 PROM and on a region 104 are removed. A seventh thermal oxide film 51 is then formed on exposed surface portions of the substrate 1. The seventh thermal oxide film 51 serves as the gate insulating films of the select transistor and a MOSFET. As shown in Fig. 8E, a second polysilicon layer 31 is formed on the entire upper surface of the device by, e.g., CVD. Phosphorus is then diffused in the second polysilicon layer 31 by, e.g., POCℓ 3 to render it conductive so as to have a desired sheet resistance ρs. As shown in Fig. 8F, the following gates and the like are formed in the respective regions through the same step as that shown in Fig. 5D: a floating gate 6, a control gate 10, a select gate 34, and the like in a region 100; a floating gate 16, a control gate 18, and the like in a region 102; and a gate 36 in the region 104. At this time, the following films and gates are formed in the region 100: a first gate insulating film 5 consisting of a first thermal oxide film 24; a tunnel insulating film 5' consisting of a third thermal oxide film 27; the floating gate 6 consisting of the first polysilicon layer 28; the second gate insulating film consisting of the four-layered film; and the control gate 10 consisting of the second polysilicon layer 31. In addition, a gate insulating film 33 consisting of a seventh thermal oxide film 51, and the select gate 34 consisting of the second polysilicon layer 31 are formed. The following films and gates are formed in the region 102: a gate insulating film 15 consisting of a second thermal oxide film 30; the floating gate 16 consisting of the first polysilicon layer 28; the second gate insulating film consisting of the four-layered film, and a control gate 18 consisting of the second polysilicon layer 31. A gate insulating film 46 consisting of the seventh thermal oxide film 51, and a gate 36 of the MOSFET which consists of the second polysilicon layer 28 are formed in the region 104. The subsequent steps are the same as those in the manufacturing method described in the first semiconductor and hence a description thereof will be omitted. The third semiconductor device is manufactured in the above-described steps. According to such a manufacturing method, the second insulating film formed between the control gate and the floating gate is constituted by, e.g., a four-layered film consisting of oxide and nitride films, thereby allowing an E 2 PROM and an EPROM to be formed on the same substrate In the third semiconductor device, if the sheet resistances of the first and second polysilicon layers are respectively represented by ρsA and ρsB, the sheet resistances of the respective conductive members are given as follows: floating gate 6: ρsA control gate 10: ρsB select gate 8: ρsB floating gate 16: ρsA control gate 18: ρsB gate 22: ρsB Fig. 9 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. The same reference numerals in Fig. 9 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 9, in the semiconductor device according to the first embodiment, if the sheet resistances of the following gates are: floating gate 6: ρs1 floating gate 53: ρs2 select gate 52: ρs3 gate 54: ρs4 control gate 10: ρs5 control gate 18: ρs6 then, the respective sheet resistances have the following relationships: ρs1 ≠ ρs2 ρs2 = ρs3 = ρs4 ρs5 = ρs6 Furthermore, if the relationship of inequality (4) is defined by ρs1 > ρs2 especially the reliability of the E 2 PROM memory cell can be improved. The inequality (7) is established when the impurity concentration of the floating gate 6 of the E 2 PROM memory cell is lower than that of the floating gate 53 of the EPROM memory cell. If the impurity concentration of the floating gate 6 is set to be low, leakage of carriers (electrons) from the floating gate 6 into an impurity layer 4 through a tunnel insulating film 5' can be prevented. In addition, leakage of an impurity from the floating gate 6 into the impurity layer 4 through the tunnel insulating film 5' can be prevented. Therefore, when the EPROM memory cell and the E 2 PROM memory cell are formed on the same substrate together, especially the reliability of the E 2 PROM memory cell can be improved. A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to Figs. 10A to 10C. Figs. 10A to 10C are sectional views showing the steps in manufacturing the semiconductor device according to the first embodiment of the present invention. The same reference numerals in Figs. 10A to 10C denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 10A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 10A is identical to that shown in Fig. 2E. Subsequently, as shown in Fig. 10B, a thermal oxide film 55 is formed on the upper surface of a first polysilicon layer 28 by, e.g., thermal oxidation. The thermal oxide film has a thickness of, e.g., about 400 Å. Subsequently, the thermal oxide film 55 is selectively removed by, e.g., photoetching. As a result, a portion of the thermal oxide film 55 is left on a surface portion of the polysilicon layer 28 serving as a floating gate in a region 100. Phosphorus is diffused in the first polysilicon layer 28 by, e.g., POCℓ 3 to render it conductive. At this time, almost no phosphorus is diffused in a portion of the polysilicon layer 28 under the thermal oxide film 55 because the thermal oxide film 55 serves a mask for impurity diffusion. with this process, a portion 28-2 having a high impurity concentration and a portion 28 having a low impurity concentration are formed in the first polysilicon layer 28. For example, the portion 28 having the low impurity concentration has an impurity concentration of about 1 to 3 × 10 20 cm -3 , and the portion 28-2 having the high impurity concentration has an impurity concentration of about 4 to 6 × 10 20 cm -3 . Note that a method of rendering the polysilicon layer 28 conductive is not limited to the above. For example, ion implantation may be employed. A mask for preventing impurity diffusion may be constituted not only by a thermal oxide film 55 but also by a CVD oxide film or a photoresist having an impurity blocking effect. As shown in Fig. 10C, the first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, a select gate pattern and a gate pattern 28-2' are formed. Fig. 11 is a plan view of the resultant structure. Fig. 10C is a sectional view taken along a line 10C - 10C in Fig. 11. As shown in Fig. 11, when the first polysilicon layer 28 is selectively etched, cell slits 29 are simultaneously formed. The subsequent steps are the same as the steps after the step shown in Fig. 2G. With the above-described steps, the semiconductor device according to the first embodiment is manufactured. According to such a manufacturing method, the sheet resistances ρs1 and ρs2 of the floating gates 6 and 53 of the E 2 PROM and EPROM memory cells are set to be different from each other, thereby allowing the E 2 PROM and the EPROM to be formed on the same substrate. In the first embodiment, if the sheet resistance of the first polysilicon layer is ρsA; the sheet resistance of the first silicon layer in which an impurity is doped, ρsA; and the sheet resistance of the second polysilicon layer, ρsB, the sheet resistances of the respective conductive members are given as follows: floating gate 6: ρsA control gate 10: ρsB select gate 52: ρsA' floating gate 53: ρsA' control gate 18: ρsB gate 54: ρsA' Fig. 12 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. The same reference numerals in Fig. 12 denote the same parts as in Fig. 1, and only different portions will be described below. In the semiconductor device according to the second embodiment, if the sheet resistances of the respective gates are: floating gate 6: ρs1 floating gate 53: ρs2 select gate 34: ρs3 gate 36: ρs4 control gate 10: ρs5 control gate 18: ρs6 the respective sheet resistances have the following relationships: ρs1 ≠ ρs2 ρs3 = ρs4 = ρs5 = ρs6 ρs1 ≠ ρs3 Furthermore, if the relationship of inequality (8) is defined by: ρs1 > ρs2 then, similar to the first embodiment, the reliability of the E 2 PROM memory cell can be improved. According to the semiconductor device having the above-described arrangement, since each of the select gate 34, the gate 36, and the control gates 10 and 18 has a sheet resistance different from that of the floating gate 6, the resistance of each gate wire can be reduced as described with reference to, e.g., the second semiconductor device. A method of manufacturing the semiconductor device according to the second embodiment of the present invention will be described with reference to Figs. 13A to 13C. Figs. 13A to 13C are sectional views showing the steps in manufacturing the semiconductor device according to the second embodiment of the present invention. The same reference numerals in Figs. 13A to 13C denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 13A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 13A is identical to that shown in Fig. 2E. Subsequently, as shown in Fig. 13B, a thermal oxide film 55 is formed on the upper surface of a first polysilicon layer 28 in the same step as, e.g., that shown in Fig. 10B. The thermal oxide film 55 is selectively removed by, e.g., photoethcing to leave a portion of the thermal oxide film 55 on a surface portion of the first polysilicon layer 28 serving as a floating gate in a region 100. Phosphorus is then diffused in the first polysilicon layer 28 by, e.g., POCℓ 3 to render it conductive. A portion 28-2 having a high impurity concentration and a portion 28 having a low impurity concentration are formed in the first polysilicon layer 28 by using the thermal oxide film 55 as a mask for controlling impurity diffusion. For example, the impurity concentration of the portion 28 having the high impurity concentration is set to be about 1 to 3 × 10 20 cm -3 , and the impurity concentration of the portion 28 having the low impurity concentration is set to be about 4 to 6 × 10 20 cm -3 . As shown in Fig. 13C, similar to the above-described step in Fig. 5B, the first polysilicon layer 28 is selectively etched by, e.g., photoetching to remove portions of the first polysilicon layer 28 which are located near the select transistor of the E 2 PROM and on a region 104. Fig. 14 is a plan view showing the resultant structure. Fig. 13C is a sectional view taken along a line 13C - 13C in Fig. 14. As shown in Fig. 13, when the first polysilicon layer 28 is selectively etched, cell slits 29 are simultaneously formed. The subsequent steps are the same as those after the above-described step in Fig. 5C and a description thereof will be omitted. With the above-described steps, the semiconductor device according to thesecond embodiment is manufactured. According to such a manufacturing method, the sheet resistance of the floating gate 6 of the E 2 PROM memory cell is set to be different from that of the floating gate 53 of the EPROM memory cell so that the E 2 PROM and the EPROM can be formed on the same substrate. In addition, since the select gate 34 and the gate 36 are constituted by a second polysilicon layer, the sheet resistance of each of the select gate 34 and the gate 36 can be set to be different from that of the floating gate 6 or the floating gate 53. In the second embodiment, if the sheet resistance of the first polysilicon layer is represented by ρsA; the sheet resistance of the first polysilicon layer in which an impurity is doped, by ρsA'; and the sheet resistance of the second polysilicon layer, by ρsB, the sheet resistances of the respective conductive members are: floating gate 6: ρsA control gate 10: ρsB select gate 34: ρsB floating gate 53: ρsA' control gate 18: ρsB gate 36: ρsB Fig. 15 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. The same reference numerals in Fig. 15 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 15, in the semiconductor device according to the third embodiment, the second gate insulating film of the E 2 PROM memory cell is constituted by a four-layered film consisting of an oxide film 38, a nitride film 39, an oxide film 40, and a nitride film 41, and the second gate insulating film of the EPROM memory cell is also constituted by a four-layered film consisting of an oxide film 42, a nitride film 43, an oxide film 44, and a nitride film 45. In addition, the sheet resistances of the respective conductive layers have the same relationships as those of the sheet resistances in the second embodiment. According to the semiconductor device having the above-described arrangement, as described with reference to the third semiconductor device, the capacitances between a control gate 10 and a floating gate 6 and between a control gate 18 and a floating gate 53 can be increased. As described with reference to the second embodiment, the reliability of the E 2 PROM memory cell can be improved, and the resistance of each gate wire can be further reduced. A method of manufacturing the semiconductor device according to the third embodiment will be described below with reference to Figs. 16A to 16D. Figs. 16A to 16D are sectional views showing the steps in manufacturing the semiconductor device according to the third embodiment of the present invention. The same reference numerals in Figs. 16A to 16D denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 16A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 16A is identical to that shown in Fig. 2E. A structure shown in Fig. 16B is obtained in the step shown in Fig. 13B. A structure shown in Fig. 16C is obtained in the step shown in Fig. 13C. A structure shown in Fig. 16D is obtained in the step shown in Fig. 8C. The subsequent steps are the same as those after the step in Fig. 8D, and hence a description thereof will be omitted. With the above-described steps, the semiconductor device according to the third embodiment is manufactured. According to such a manufacturing method, similar to the manufacturing method described with reference to the second embodiment, since the sheet resistance of the floating gate 6 of the E 2 PROM memory cell is set to be different from that of the floating gate 53 of the EPROM memory cell, the E 2 PROM and the EPROM can be formed on the same substrate. Since a select gate 34 and a gate 36 are composed of a second polysilicon layer, the sheet resistances of the select gate 34 and the gate 36 can be set to be different from those of the floating gates 6 and 53. In addition to these advantages, a second gate insulating film between a control gate and a floating gate can be composed of a stacked layer consisting of an oxide film and a nitride film. In the third embodiment, if the sheet resistance of the first polysilicon layer is represented by ρsA; the sheet resistance of the first polysilicon layer in which an impurity is doped, by ρsA'; and the sheet resistance of the second polysilicon layer, by ρsB, the sheet resistances of the respective conductive members are: floating gate 6: ρsA control gate 10: ρsB select gate 34: ρsB floating gate 53: ρsA' control gate 18: ρsB gate 36: ρsB Fig. 17 is a sectional view showing a fourth semiconductor device not forming an embodiment of the present invention. The same reference numerals in Fig. 17 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 17, a second polysilicon layer 8' is left above a select gate 8. A select gate of this type is generally called a "stacked select gate". According to the semiconductor device having the "stacked select gate" having the above-mentioned arrangement, a memory cell transistor is constituted by two layers of a floating gate 6 and a control gate 10. Similarly, a select transistor is constituted by two layers of the select gate 8 and the second polysilicon layer 8'. With this structure, the gate portions of the select and memory cell transistors can be patterned in the same step. Therefore, since the distances from the select gate 8 to the floating gate 6 and to the control gate can be reduced, this device is suitable for micropatterning of a memory cell. Note that when the "stacked select gate" is used, it is only required that a current be supplied to only the select gate 8 consisting of at least a first polysilicon layer. A method of manufacturing the semiconductor device will be described below with reference to Figs. 18A to 18E. Figs. 18A to 18E are sectional views showing the steps in manufacturing the semiconductor device. The same reference numerals in Figs. 18A to 18E denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 18A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 18A is identical to that shown in Fig. 2E. As shown in Fig. 18B, a first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, a gate pattern 28' of the MOSFET constituting a peripheral circuit is formed in a region 104. Fig. 19 is a plan view showing the resultant structure. Fig. 18B is a sectional view taken along a line 18B - 18B in Fig. 19. As shown in Fig. 19, in this etching step, cell slits 29 are simultaneously formed. As shown in Fig. 18C, a fourth thermal oxide film 30 is formed on the upper surfaces of the first polysilicon layer 28 and the gate pattern 28' by, e.g., thermal oxidation. A second polysilicon layer 31 is then formed on the entire surface of the device by, e.g., CVD. Phosphorus is diffused in the second polysilicon layer 31 by, e.g., POCℓ 3 to render it conductive. As shown in Fig. 18D, the second polysilicon layer 31 is selectively etched by, e.g., photoetching With this process, a portion of the second polysilicon layer 31 on the region 104 is removed. At the same time, the second polysilicon layer 31 at an end portion of a select gate (not shown) is selectively removed to form an exposed portion of a first polysilicon layer 28. The portion serves as a region in which a wire is to contact with the gate 8. Subsequently, as shown in Fig. 18E, the second polysilicon layer 31, a fourth thermal oxide film 30, and the first polysilicon layer 28 are selectively etched by, e.g., photoetching. As a result, the following films and gates are formed in a region 100: a first insulating film 5 consisting of a first thermal oxide film 24; a tunnel insulating film 5' consisting of a third thermal oxide film 27; the floating gate 6 consisting of the first polysilicon layer 28; a second gate insulating film 9 consisting of the fourth thermal oxide film 30; a control gate 10 consisting of the second polysilicon layer 31; a gate insulating film 7 consisting of a first thermal oxide film 24; and the select gate 8 consisting of the first polysilicon layer 28. In addition, the second polysilicon layer 8' is formed above the select gate 8. The following films and gates are formed in a region 102: a first gate insulating film 15 consisting of a second thermal oxide film 25; a floating gate 16 consisting of the first polysilicon layer 28; a second gate insulating film 17 consisting of the fourth thermal oxide film 30; and a control gate 18 consisting of the second polysilicon layer 31. A gate insulating film 21 consisting of the second thermal oxide film 25 and a gate 22 consisting of the first polysilicon layer 28 are formed in the region 104. Since the subsequent steps are the same as those in the manufacturing method described with reference to the first semiconductor device, a description thereof will be omitted. With the above-described steps, the semiconductor device according to the fourth embodiment is manufactured. According to such a manufacturing method, the gate patterns of the select and memory cell transistors can be patterns in the same step. Fig. 20 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. The same reference numerals in Fig. 20 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 20, in the semiconductor device according to the fourth embodiment, similar to the fourth semiconductor device, a second polysilicon layer 52' is left above a select gate 52 to form a stacked select gate. In addition, if the sheet resistances of the respective gates are: floating gate 6: ρs1 floating gate 53: ρs2 select gate 52: ρs3 gate 54: ρs4 control gate 10: ρs5 control gate 18: ρs6 the respective sheet resistances have the following relationships: ρs1 ≠ ρs2 ρs2 = ρs3 = ρs4 ρs5 = ρs6 Furthermore, if the relationship of inequality (11) is defined by ρs1 > ρs2 the reliability of the E 2 PROM memory cell can be improved as in the first embodiment. A method of manufacturing the semiconductor device according to the fourth embodiment will be described below with reference to Figs. 21A to 21D. Figs. 21A to 21D are sectional views showing the steps in manufacturing the semiconductor device according to the fourth embodiment of the present invention. The same reference numerals in Fig. 21A to 21D denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 21A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 2A is identical to that shown in Fig. 2E. As shown in Fig. 21B, a thermal oxide film 55 is formed on the upper surface of a first polysilicon layer 28 by, e.g., thermal oxidation. The thermal oxide film 55 is then selectively removed by, e.g., photoetching. As a result, a portion of the thermal oxide film 55 is left on a surface portion of the first polysilicon layer 28 which serves as a floating gate. Phosphorus is diffused in the first polysilicon layer 28 by, e.g., POCℓ 3 to render it conductive. At this time, almost no phosphorus is diffused in a portion of the first polysilicon layer 28 under the thermal oxide film 55 because the film 55 serves as a mask for controlling impurity diffusion. With this process, a portion 28-2 having a high impurity concentration and a portion 28 having a low impurity concentration are formed in the first polysilicon layer 28. As shown in Fig. 21C, the first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, a gate pattern 28-2' of the MOSFET is formed. Fig. 22 shows the resultant structure. Fig. 21C is a sectional view taken along a line 21C - 21C in Fig. 22. When the first polysilicon layer is etched, cell slits 29 are simultaneously formed. As shown in Fig. 21D, a thermal oxide film 30 is formed on the upper surfaces of the first polysilicon layers 28 and 28-2' by, e.g., thermal oxidation. A second polysilicon layer 31 is then formed on the entire upper surface of the device by, e.g., CVD. Since the subsequent steps are the same as those after the step shown in Fig. 18D, a description thereof will be omitted. With the above-described steps, the semiconductor device according to the fourth embodiment is manufactured. According to such a manufacturing method, the gate portions of the select and memory cell transistors can be patterned in the same step. In addition, the sheet resistances of the floating gates 6 and 53 can be set to be different from each other. In the fourth embodiment, if the sheet resistance of the first polysilicon layer is represented by ρsA; the sheet resistance of the first polysilicon layer in which an impurity is doped, by ρsA'; and the sheet resistance of the second polysilicon layer, by ρsB, the sheet resistances of the respective conductive members are: floating gate 6: ρsA control gate 10: ρsB select gate 52: ρsA' floating gate 53: ρsA' control gate 18: ρsB gate 54: ρsA' Fig. 23 is a sectional view showing a fifth semiconductor device not forming an embodiment of the present invention. The same reference numerals in Fig. 23 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 23, in the fifth semiconductor device, similar to the fourth semiconductor device, a second polysilicon layer 8' is left above a select gate 8 to form a stacked select gate. In addition, if the sheet resistances of the respective gates are: floating gate 6: ρs1 floating gate 16: ρs2 select gate 8: ρs3 gate 36: ρs4 control gate 10: ρs5 control gate 18: ρs6 then, the respective sheet resistances have the following relationships: ρs1 = ρs2 = ρs3 ρs4 = ρs5 = ρs6 ρs4 ≠ ρs1 According to the semiconductor device having the above-described arrangement, since a stacked select gate is used, micropatterning of the E 2 PROM memory cell is facilitated, and the sheet resistance of, e.g., each of the floating gates 6 and 16 can be set to be smaller than that of the gate 36. A method of manufacturing the fifth semiconductor device will be described below with reference to Figs. 24A to 24E. Figs. 24A to 24E are sectional views showing the steps in manufacturing the fifth semiconductor device. The same reference numerals in Figs. 24A to 24E denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 24A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 24A is identical to that shown in Fig. 2E. As shown in Fig. 24B, a first polysilicon layer 28 is selectively etched by, e.g., photoetching. As a result, a portion of the first polysilicon layer 28 on a region 104 is removed. Fig. 25 shows the resultant structure. Fig. 24B is a sectional view taken along a line 24B - 24B in Fig. 25. As shown in Fig. 25, when the first polysilicon layer 28 is selectively etched, cell slits 28 are simultaneously formed. As shown in Fig. 24C, a fourth thermal oxide film 30 is formed on the upper surface of the first polysilicon layer 28 and an exposed surface portion of the substrate 1. The fourth thermal oxide film 30 serves as the second gate insulating films of the E 2 PROM and EPROM memory cells and the gate insulating film of the MOSFET. A second polysilicon layer 31 is then formed on the entire upper surface of the device by, e.g., CVD. Phosphorus is diffused in the polysilicon layer 31 by, e.g., POCℓ 3 to render it conductive so as to have a desired sheet resistance ρs. As shown in Fig. 24D, the second polysilicon layer 31 is selectively etched by, e.g., photoetching. with this process, a gate pattern 31 of the MOSFET is formed in the region 104. As shown in Fig. 24E, the second polysilicon layer 31, the fourth thermal oxide film 30, and the first polysilicon layer 28 are selectively etched. As a result, the following films and gates are formed in a region 100: a first gate insulating film 5 consisting of a first thermal oxide film 24; a tunnel insulating film 5' consisting of a third thermal oxide film 27; a floating gate 6 consisting of the first polysilicon layer 28; a second gate insulating film 9 consisting of the fourth thermal oxide film 30; the control gate 10 consisting of the second polysilicon layer 31; a gate insulating film 7 consisting of the first thermal oxide film 24; and the select gate 8 consisting of the first polysilicon layer 28. In addition, the second polysilicon layer 8' is formed above the select gate 8. The following films and gates are formed in a region 102: a first gate insulating film 15 consisting of a second thermal oxide film 25; the floating gate 16 consisting of the first polysilicon layer 28; a second gate insulating film 17 consisting of the fourth thermal oxide film 30; and the control gate 18 consisting of the second polysilicon layer 31. A gate insulating film 35 consisting of the fourth thermal oxide film 30, and the gate 36 consisting of the second polysilicon layer 31 are formed in the region 104. Since the subsequent steps are the same as those of the manufacturing method described with reference to the first semiconductor device, a description thereof will be omitted. With the above-described steps, the fifth semiconductor device is manufactured. According to such a manufacturing method, the gate portions of the select and memory cell transistors can be patterned in the same steps, and the sheet resistance of, e.g., each of the floating gates 6 and 16 can be set to be different from that of the gate 36. In the fifth semiconductor device, the sheet resistances of the first and second polysilicon layers are respectively represented by ρsA and ρsB, the sheet resistances of the respective conductive layers are: floating gate 6: ρsA control gate 10: ρsB select gate 8: ρsA floating gate 16: ρsA control gate 18: ρsB gate 36: ρsB Fig. 26 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. The same rererence numerals in Fig. 26 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 26, in the semiconductor device according to the fifth embodiment, similar to the fourth semiconductor device, a second polysilicon layer 52' is left above a select gate 52 to form a stacked select gate. In addition, if the sheet resistances of the respective gates are represented as follows: floating gate 6: ρs1 floating gate 53: ρs2 select gate 52: ρs3 gate 36: ρs4 control gate 10: ρs5 control gate 18: ρs6 then, the respective sheet resistances have the following relationships: ρs1 ≠ ρs2 ρs2 = ρs3 ρs4 = ρs5 = ρs6 Furthermore, if the relationship of inequality (17) is defined by: ρs1 > ρs2 then, the reliability of the E 2 PROM memory cell can be improved as in the fourth semiconductor device. A method of manufacturing the semiconductor device according to the fifth embodiment will be described below with reference to Figs. 27A to 27D. Figs. 27A to 27D are sectional views showing the steps in manufacturina the semiconductor device according to thefifth embodiment of the present invention. The same reference numerals in Figs. 27A to 27D denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 27A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 27A is identical to that shown in Fig. 2E. A structure shown in Fig. 27B is obtained through the step in Fig. 21B. A structure shown in Fig. 27C is obtained through the step in Fig. 24B. Fig. 28 is a plan view showing the resultant structure. Fig. 27C is a sectional view taken along a line 27C - 27C in Fig. 28. A structure shown in Fig. 27D is obtained through the step in Fig. 24C. Since the subsequent steps are the same as those after the step shown in Fig. 21D, a description thereof will be omitted. With the above-described steps, the semiconductor device according to the fifth embodiment is manufactured. According to such a manufacturing method, the gate portions of the select and memory cell transistors can be patterned in the same step, and the sheet resistances of the floating gates 6 and 53 can be set to be different from each other. In addition, for example, the sheet resistances of the floating gate 6 and the gate 36 can be set to be different from each other. In the fifth embodiment, if the sheet resistance of the first polysilicon layer is represented by ρsA; the sheet resistance of the first polysilicon layer in which an impurity is doped, by ρsA'; and the sheet resistance of the second polysilicon layer, by ρsB, the sheet resistances of the respective conductive members are: floating gate 6: ρsA control gate 10: ρsB select gate 52: ρsA' floating gate 53: ρsA' control gate 18: ρsB gate 36: ρsB Fig. 29 is a sectional view showing a sixth semiconductor device not forming an embodiment of the present invention. The reference numerals in Fig. 29 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 29, in the sixth semiconductor device, similar to the fourth semiconductor device, a second polysilicon layer 8' is left above a select gate 8 to form a stacked select gate. In addition, the second gate insulating film of the E 2 PROM memory cell is constituted by a three-layered film consisting of an oxide film 38, a nitride film 39, and an oxide film 40, and the second gate insulating film of the EPROM memory cell is constituted by a three-layered film consisting of an oxide film 42, a nitride film 43, and an oxide film 44. Furthermore, in the semiconductor device according to the sixth semiconductor device, the sheet resistances of the respective conductive layers have the same relationships as those in the fifth semiconductor device. According to the semiconductor device having the above-described arrangement, since the select gate is constituted by the stacked select gate, micropatterning of the E 2 PROM memory cell is facilitated, and the capacitance between a control gate and a floating gate can be increased. A method of manufacturing the sixth semiconductor device will be described below with reference to Figs. 30A to 30F. Figs. 30A to 30F are sectional views showing the steps in manufacturing the sixth semiconductor device. The same reference numerals in Figs. 30A to 30F denote the same parts as in Fig. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 30A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 30A is identical to that shown in Fig. 2E. A structure shown in Fig. 30B is obtained through the step in Fig. 24B. As shown in Fig. 30C, a fifth thermal oxide film 47 is formed on the upper surface of a first polysilicon layer 28 and an exposed surface portion of the substrate 1 by, e.g., thermal oxidation. A first nitride film 48 is formed on the entire upper surface of the device. A sixth thermal oxide film 49 is formed on the upper surface of the first nitride film 48 by, e.g., thermal oxidation. As shown in Fig. 30D, the fifth thermal oxide film 47, the first nitride film 48, and the sixth thermal oxide film 49 are selectively and sequentially etched by, e.g., photoetching. As a result, portions of the fifth thermal oxide film 47, of the first nitride film 48, and of the sixth thermal oxide film 49 located in a region 104 are removed. Thereafter, a seventh thermal oxide film 51 is formed on the exposed surface portion of the substrate 1 by, e.g., thermal oxidation. The seventh thermal oxide film 51 serves as the gate insulating film of the MOSFET. As shown in Fig. 30E, a second polysilicon layer 31 is formed on the entire upper surface of the device by, e.g., CVD. A structure shown in Fig. 30F is obtained through the above-described steps in Figs. 24D to 24E. As a result, the following films and gates are formed in a region 100: a first gate insulating film 5 consisting of a first thermal oxide film 24; a tunnel insulating film 5' consisting of a third thermal oxide film 27; a floating gate 6 consisting of a first polysilicon layer 28; the second gate insulating film consisting of the three-layered film; a control gate 10 consisting of a second polysilicon layer 31; a gate insulating film 7 consisting of the first thermal oxide film 24; and the select gate 8 consisting of the first polysilicon layer 28. In addition, the second polysilicon layer 8' is formed above the select gate 8. The following films and gates are formed in a region 102: a first gate insulating film 15 consisting of a second thermal oxide film 25; a floating gate 16 consisting of the first polysilicon layer 28; the second gate insulating film consisting of the three-layered film; and a control gate 18 consisting of the second polysilicon layer 31. A gate insulating film 46 consisting of the seventh thermal oxide film 51, and a gate 36 consisting of the second polysilicon layer 31 are formed in the region 104. Since the subsequent steps are the same as those of the manufacturing method described with reference to the first semiconductor device, a description thereof will be omitted. With the above-described steps, the semiconductor device according to the sixth semiconductor device is manufactured. According to such a manufacturing method, the gate portions of the select and memory cell transistors can be patterned in the same step. In addition, the E 2 PROM and the EPROM can be formed on the same substrate by using, e.g., a three-layered film consisting of oxide and nitride films as a second insulating film between a control gate and a floating gate. In the sixth semiconductor device, if the sheet resistances of the first and second polysilicon layers are respectively represented by ρsA and ρsB, the sheet resistances of the respective conductive layers are: floating gate 6: ρsA control gate 10: ρsB select gate 8: ρsA floating gate 16: ρsA control gate 18: ρsB gate 36: ρsB Fig. 31 is a sectional view showing a semiconductor device according to the sixth embodiment of the present invention. The same reference numerals in Fig. 31 denote the same parts as in Fig. 1, and only different portions will be described below. As shown in Fig. 31, similar to the fourth semiconductor device, in the semiconductor device according to the sixth embodiment, a second polysilicon layer 52' is left above a select gate 52 to form a stacked select gate. In addition, the second gate insulating film of the E 2 PROM memory cell is constituted by a three-layered film consisting of an oxide film 38, a nitride film 39, and an oxide film 40, and the second gate insulating film of the EPROM memory cell is constituted by a three-layered film consisting of an oxide film 42, a nitride film 43, and an oxide film 44. In the semiconductor device according to the sixth embodiment, the sheet resistances of the respective conductive layers have the same relationships as those in the fifth embodiment. According to the semiconductor device having the above-described arrangement, in addition to the advantage that micropatterning of the E 2 PROM memory cell is facilitated, the capacitance between a control gate and a floating gate can be increased. By setting the sheet resistance of a floating gate 53 to be larger than that of a floating gate 6, the reliability of the E 2 PROM memory cell can be improved as in the first embodiment. A method of manufacturing the semiconductor device according to the sixth embodiment will be described below with reference to Figs. 32A to 32D. Figs. 32A to 32D are sectional views showing the steps in manufacturing the semiconductor device according to the sixth embodiment of the present invention. The same reference numerals in Figs. 32A to 32D denote the same parts as in Figs. 2A to 2H, and only different portions will be described below. A structure shown in Fig. 32A is obtained through the above-described steps in Figs. 2A to 2E. The structure shown in Fig. 32A is identical to that shown in Fig. 2E. A structure shown in Fig. 32B is obtained through the step in Fig. 27B. A structure shown in Fig. 32C is obtained through the step in Fig. 30B. A structure shown in Fig. 32D is obtained through the step in Fig. 30C. Since the subsequent steps are the same as those after the step in Fig. 30D, a description thereof will be omitted. With the above-described steps, the semiconductor device according to the sixth embodiment is manufactured. According to such a manufacturing method, the gate portions of the select and memory cell transistors can be patterned in the same step. In addition, the E 2 PROM and EPROM can be formed on the same substrate by using, e.g., a three-layered film consisting of oxide and nitride films as a second gate insulating film between a control gate and a floating gate. Moreover, the sheet resistances of a floating gate 6 and of a gate 36 can be set to be different from each other. In the sixth embodiment, if the sheet resistance of the first polysilicon layer is represented by ρsA; the sheet resistance of the first polysilicon layer in which an impurity is doped, by ρsA'; and the sheet resistance of the second polysilicon layer, by ρsB, the sheet resistances of the respective conductive members are: floating gate 6: ρsA control gate 10: ρsB select gate 52: ρsA floating gate 53: ρsA control gate 18: ρsB gate 36: ρsB Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type having a major surface; first, second, third and fourth semiconductor regions (3, 3`, 14) of a second conductivity type which are separately provided in a major surface region of said substrate (1); first carrier storage means (53) provided above said substrate (1) between said first and second semiconductor regions (14), for storing carriers, said first carrier storage means comprising a first conductor having a sheet resistance ρ s2; first insulating means (15) provided between said first carrier storage means (53) and said substrate (1) and electrically insulating said first carrier storage means (53) from said substrate (1); a first control gate layer (18) provided above said first carrier storage means (53), said first control gate layer comprising a second conductor having a sheet resistance ρ s6; second insulating means (17) provided between said first control gate layer (18) and said first carrier storage means (53) and insulating said first control gate layer (18) from said first carrier storage means (53); second carrier storage means (6) provided above said substrate (1) between said third and fourth semiconductor regions (3, 3`) and provided above said fourth semiconductor region (3`) so as to partly overlap said fourth semiconductor region (3`), for storing carriers, said second carrier storage means (6) comprising a third conductor having a sheet resistance ρ s1; third insulating means (5) provided between said second carrier storage means (6) and said substrate (1) and electrically insulating said second carrier storage means (6) from said substrate (1) and said fourth semiconductor region (3`); a second control gate layer (10) provided above said second carrier storage means (6), said second control gate layer comprising a fourth conductor having a sheet resistance ρ s5; fourth insulating means (9) provided between said second gate layer (10) and said second carrier storage means (6) and insulating said second control gate layer (10) from said second carrier storage means (6); and tunnelling means (5`) provided in said third insulating means (5) between said fourth semiconductor region (3`) and said second carrier storage means (6), allowing carriers to tunnel between said second carrier storage means (6) and said fourth semiconductor region (3`), an impurity concentration of said third conductor of said second carrier storage means (6) being lower than that of said first conductor of said first carrier storage means (53). A device according to claim 1, characterised in that a relationship between the sheet resistance ρs1 and the sheet resistance ρ s2 is represented by ρ s1>ρ s2. A device according to claim 1, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1> ρ s2 ρ s5 = ρ s6. A device according to any one of claims 1 to 3, characterised in that each of said first, second, third and fourth insulating means (15, 17, 5, 9) comprises an insulating film, and said tunnelling means (5`) comprises an insulating film having a thickness smaller than that of the insulating film of said third insulating means (5). A device according to claim 4, characterised in that each insulating film of said second and fourth insulating means (17,9) is obtained by stacking an oxide film and a nitride film. A device according to claim 1, characterised by further comprising: a fifth semiconductor region (3) of the second conductivity type arranged near said fourth semiconductor region (3') and provided in the major surface of said substrate (1) so as to be separated from said fourth semiconductor region (3`); a select gate layer (52:34) provided above said substrate (1) between said fourth and fifth semiconductor regions (3,3`), said select gate layer (52:34) comprising a fifth conductor having a sheet resistance of ρ s3; and fifth insulating means (7) provided between said select gate layer (52:34) and said substrate (1) and insulating said select gate layer (52:34) from said substrate (1). A device according to claim 6, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s3, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1> ρ s2 ρ s5 = ρ s6 ρ s2 = ρ s3. A device according to claim 6, characterised in that a relationship between the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s3, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1>ρ s2 ρ s3 = ρ s5 = ρ s6. A device according to any one of claims 6 to 8, characterised in that said fifth insulating means (7) comprises an insulating film. A device according to claim 6, characterised by further comprising: sixth and seventh semiconductor regions (20) of the second conductivity type provided in the major surface of said substrate (1) so as to be separated from each other; a gate layer (54:36) provided above said substrate (1) between said sixth and seventh semiconductor regions (20), said gate layer (54:36) comprising a sixth conductor having a sheet resistance of ρ s4; and sixth insulating means (21) provided between said gate layer (54:36) and said substrate (1) and insulating said gate layer (54:36) from said substrate (1). A device according to claim 10, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s3, the sheet resistance ρ s4, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented ρ s1>ρ s2 ρ s2 = ρ s3 = ρ s4 ρ s5 = ρ s6. A device according to claim 10, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s3, the sheet resistance ρ s4, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1 > ρ s2 ρ s3 = ρ s4 = ρ s5 = ρ s6. A device according to claim 10, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s3, the sheet resistance ρ s4, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1 > ρ s2 ρ s2 = ρ s3 ρ s4 = ρ s5 = ρ s6. A device according to any one of claims 10 to 13, characterised in that said sixth insulating means (21) comprises an insulating film. A device according to claim 1, characterised by further comprising: sixth and seventh semiconductor regions (20) of the second conductivity type provided in the major surface of said substrate (1) so as to be separated from each other; a gate layer (54:36) provided above said substrate (1) between said sixth and seventh semiconductor regions (20), said gate layer (54:36) comprising a sixth conductor having a sheet resistance of ρ s4; and sixth insulating means (21) provided between said gate layer (54:36) and said substrate (1) and insulating said gate layer (54:36) from said substrate (1). A device according to claim 15, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s4, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1 > ρ s2 ρ s2 = ρ s4 ρ s5 = ρ s6. A device according to claim 15, characterised in that relationships among the sheet resistance ρ s1, the sheet resistance ρ s2, the sheet resistance ρ s4, the sheet resistance ρ s5 and the sheet resistance ρ s6 are represented by ρ s1 >ρ s2 ρ s4= ρ s5= ρ s6 A device according to any one of claims 15 to 17, characterised in that said sixth insulating means (21) comprises an insulating film.

Inventors: HANADA NAOKI, MIZUTANI TAKAHIDE, MORI TATSUO, UEMURA TERUO, HANADA, NAOKI, MIZUTANI, TAKAHIDE, MORI, TATSUO, SHINADA, KAZUYOSHI, UEMURA, TERUO, HANADA, NAOKI, INTELLECTUAL, MIZUTANI, TAKAHIDE, INTELLECTUAL, MORI, TATSUO, INTELLECTUAL, UEMURA, TERUO, INTELLECTUAL
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L29