Gate array semiconductor integrated circuit

Abstract: A gate array semiconductor integrated circuit includes a plurality of input/output cells (12), an input/output circuit (13, 14), and a bias circuit (15). The plurality of input/output cells (12) are arranged around an internal logic gate (11). The input/output circuit (13, 14) is formed by an aluminum master slice of the input/output cells (12) and performs an input/output operation for the internal logic gate (11). The bias circuit (15) is formed by the aluminum master slice of the input/output cells (12) to supply a prede­ termined bias voltage to the input/output circuit (13, 14).

Description: The present invention relates to a semiconductor integrated circuit and, more particularly, to a gate array semiconductor integrated circuit such as a gate array LSI. In a conventional gate array LSI, such as that described in IEEE J. Solid-State Circuits, vol. 14 no.5 October 1979 pages 829-832, a plurality of bias circuits and a plurality of input/output cells, a predetermined number of input/output circuits of which are formed by an aluminum master slice, are arranged around an internal CMOS logic gate. The input/output circuits include a predetermined number of ECL input and ECL output circuits. Each bias circuit is arranged beforehand at a predetermined position on a chip to generate a bias voltage for obtaining a constant current and a bias voltage to be compared with an input signal and to supply these bias voltages to the input circuit and the output circuit respectively. An input/output cell portion excluding the bias circuits, therefore, can be used as the input or output circuits. A predetermined number of conventional bias circuits are arranged beforehand regardless of the number of the input/output circuits before the input/output circuits are arranged, because large current drive ability is required. However, some bias circuits are often not used depending on the layout of the input/output circuits, and therefor redundancy in circuit design cannot be inevitably avoided in conventional circuits. The bias circuits are arranged at fixed positions and cannot perform input/output operations of other signals, resulting in inconvenience. In Patent Abstracts of Japan, vol. 11, No.17, 17.1.87 and JP-A- 61 188 960 a masterslice IC is described wherein a cell for obtaining an ECL internal gate is fabricated as a bias circuit element by means of the aluminium masterslice wiring. It is, therefore, an object of the present invention to provide a gate array semiconductor integrated circuit apparatus capable of arranging only necessary bias circuits by arranging the bias circuits for input/output circuits by an aluminum master slice of input/output cells. It is another object of the present invention to provide a gate array semiconductor integrated circuit apparatus capable of performing input/output operations of other signals by variably changing positions of the bias circuits. In order to achieve the above objects, a gate array semiconductor integrated circuit comprises: a plurality of input/output cells arranged around an internal logic gate; an input/output circuit, formed by an aluminum master slice wiring of the input/output cells, performing an input/output operation on a signal for the internal logic gate; and a bias circuit formed by the same aluminum master slice wiring of the plurality of input/output cells to supply a predetermined bias voltage to the input/output circuit. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: The above aspects and features of the present invention will be described in detail with reference to accompanying drawings, in which: Fig. 1 is a schematic view showing an embodiment of the present invention; and Fig. 2 is a circuit diagram showing a detailed arrangement of the present invention. An embodiment of the present invention will be described in detail with reference to the accompanying drawings. Fig. 1 shows an embodiment of the present invention. In a gate array LSI, a plurality of input/output cells 12, a predetermined input/output or bias circuits and the like of which are formed by an aluminum master slice, are arranged around an internal CMOS logic gate 11. Predetermined numbers of ECL input circuits 13, ECL output circuits 14, and bias circuits 15 are formed by the aluminum master slice of the input/output cells 12. That is, in the gate array LSI, the bias circuits 15 formed by the aluminum master slice of the input/output cells 12 generate bias voltages necessary for the input and output circuits 13 and 14 also formed by the aluminum master slice of the input/output circuits 12. Fig. 2 shows a detailed arrangement of the present invention. An input circuit 16 and an output circuit 17 of a pseudo-ECL level formed by the aluminum master slice of the input/output cells 12 require a bias voltage for obtaining a constant current and a bias voltage to be compared with an input signal, respectively. A bias circuit 18 formed by the aluminum master slice of the input/output cells 12 generates these bias voltages. In Fig. 2, reference numeral 19 denotes a terminal for supplying the signals to the internal logic gate; 20, a terminal for receiving the signals from the internal logic gate; 21, a power source; and 22, ground. As described above, since the bias circuits are arranged as needed, wasteful input/output cells need not be used, and the bias circuits can be arranged at any positions. The circuit shown in Fig. 2 can be combined with a gate array LSI, an internal logic gate of which is operated at a CMOS level, to arrange different bias circuits on one chip. Note that, as an application of the present invention, a third voltage can be generated from a power source or ground voltage and can be used as a power source for the input/output circuits. As described above, according to the present invention, a non-used bias circuit need not be arranged by supplying the bias voltages to the input/output circuit from the bias circuit formed by the aluminum master slice of the input/output cells, and a gate array semiconductor integrated circuit apparatus capable of performing input/output operations of other signals can be provided by changing an arrangement of the bias circuit. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A gate array semiconductor integrated circuit comprising: a plurality of input/output cells (12) arranged around an internal logic gate (11); an input/output circuit (13, 14), formed by an aluminum master slice wiring of said input/output cells (12) performing an input/output operation on a signal from said internal logic gate (11); and a bias circuit (15) formed by the same aluminum master slice wiring of said input/output cells (12) to supply a predetermined bias voltage to said input/output circuit (13, 14). A circuit according to claim 1, characterized in that said input/output circuit (13, 14) includes an ECL input/output circuit (16, 17). A circuit according to claim 2, characterized in that said ECL input/output circuit (16, 17) includes an ECL input/output circuit performing an input/output operation on a signal of a pseudo-ECL level. A circuit according to claim 1, characterized in that said bias circuit (15) comprises means for generating a bias voltage for obtaining a constant current and a bias voltage to be compared with an input signal.

Inventors: HARA HIROYUKI C O INTELLECTUAL, HARA, HIROYUKI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L27