Source-coupled FET-logic-typ logic circuit

Abstract: A source-coupled FET-logic-type logic circuit having level shift elements (LS1, LS2) connected to a high-potential power supply (V DD ), field-effect tran­ sistors (Q1 - Q4, Q9 - Q12), load elements (LD1 - LD4) connecting the sources of the field-effect transistors (Q1 - Q4, Q9 - Q12), field-effect transistors (Q7, Q8, Q15, Q16) coupled between the high-potential power supply (V DD ) and a low-potential power supply (V SS ), constant current sources (CC2, CC3, CC5, CC6), and complementary output terminals (Q, Q ). The circuit further has a field-effect transistors (Q5, Q6, Q13, Q14) controlled by complementary signals input to two input terminals (IN, IN ). The circuit, which is a T flip-flop, further comprises a frequency switching circuit composed of field-effect transistors (Q17 - Q20) which are controlled by the signals supplied to two switching terminals (SW, SW ). When the first switching terminal (SW) is at a high level, the output terminals (Q, Q ) outputs a signal having the same frequency as the input signal. When the first switching terminal (SW) is at a low level, the output terminals (Q, Q ) outputs a signal having half the frequency of the input signal.

Description: The present invention relates to a logic circuit usable in variable frequency dividers, as disclosed in WO 86/03078. The known logic circuit includes a driver, a latch and an enabling switch each comprising a pair of emitter coupled transistors. The driver is coupled to the latch, and the emitters of the transistors of the enabling switch are coupled to a current source. A collector of each of the transistors of the enabling switch is coupled to a respective pair of emitters of the latch or the driver. The collector of one of the transistors of the enabling switch is coupled to the emitters of either the driver or the latch via a control switch, or the control switch is coupled between the driver and the current source. The control switch enables the elimination of external gating arrangements in variable frequency dividers. A variable frequency divider may be constructed from one or more of the logic circuits in combination with one or more flip-flops. The division ratio of the variable frequency divider can be varied in dependence upon a signal applied to the control switch. A prescribed signal (e.g. signal with 1/2 the frequency of a clock signal) has been obtained so far by inputting the reference signal to a T-flip-flop circuit and fetching the output signal of the T-flip-flop circuit. For mobile radio equipment for communication, however, it may be necessary to separately fetch a signal with the same frequency as the reference signal, and to fetch another signal with 1/2 the frequency of the reference signal according to necessity. Therefore, to configure the equipment with a source-coupled FET-logic (hereafter called SCFL)-type logic circuit, for example, the following logic circuit has been used. That is, as is shown in Fig. 8, the reference signal input from the input terminal IN is input to a selection circuit directly or through the T-flip-flop circuit and the reference signal is output to the output terminal of the selection circuit. By switching the level of the switching terminal, either the signal with the same frequency as the reference signal or that with 1/2 the frequency of its output. Fig. 1 shows the configuration of the T-flip-flop circuit and Fig. 2 the block diagram of the selection circuit. As is illustrated in Fig. 1, one of the electrodes of level shift element LS1 is connected to a high-potential power supply V DD , while the other end is connected to one end of load elements LD1 and LD2. Load elements LD1 and LD2 are connected, at the other end, to the drain electrodes of field effect transistors (FET) Q1 and Q2, respectively. The drain electrodes of FETs Q1 and Q2 connect with the drain electrodes of FETs Q3 and Q4, respectively. The source electrodes of the FETs Q1 and Q2 are connected to each other, and are connected to the drain of FET Q5 whose gate electrode connects with the input terminal IN . Similarly, the source electrodes of the FETs Q3 and Q4 are connected to each other, and the gate electrodes thereof are connected to the drain electrode of FET Q6 whose gate electrode is connected to the input terminal IN. In addition, the source electrodes of FETs Q5 and Q6 are connected to each other, and also to a low-potential power supply V SS by constant current source CC1. The drain electrodes of the FETs Q1 and Q2 are connected to the gate electrodes of FETs Q7 and Q8 whose drain electrodes are connected to the high-voltage power source, and whose source electrodes are connected to one end of level shift elements LS2 and LS3, respectively. The other ends of level shift elements LS2 and LS3 are connect to the low-voltage power supply V SS by constant current source CC2 and CC3. One of the electrodes of level shift element LS4 is connected to the high-potential power supply V DD , and the other end thereof is connected to one end of load elements LD3 and LD4. The other ends of load elements LD3 and LD4 are connected to the drain electrodes of FETs Q9 and Q10. The drain electrodes of FETs Q9 and Q10 connect with the drain electrodes of FETs Q11 and Q12. The source electrodes of the FETs Q9 and Q10 are connected to each other, and are connected to FET Q13 whose gate electrode connects with the input terminal IN. Similarly, the source electrodes of the FETs Q11 and Q12 are connected to each other, and are connected to FET Q14 whose gate electrode connects with the input terminal IN . In addition, the source electrodes of FETs Q13 and Q14 are connected to each other, and also to the low-voltage power supply V SS by constant current source CC4. The gate electrodes of FETs Q9, Q10, Q11, and Q12 connect with the gate electrodes of FETs Q4, Q3, Q1, and Q2, respectively. The drain electrodes of the FETs Q9 and Q10 connect with the gate electrodes of FETs Q15 and Q16 whose drains are grounded and whose source electrodes connect with level shift elements LS5 and LS6, respectively. Level shift elements LS5 and LS6 connect with the negative-voltage power supply V SS through level shift element LS7 and constant current source CC5, and through level shift element LS8 and constant current source CC6, respectively. In addition, the junction between level shift elements LS6 and LS8 connects with the gate electrodes of FETs Q1 and Q11. Similarly, the junction between level shift elements LS5 and LS7 connects with the gate electrodes of FETs Q2 and Q12. The output terminal Q connects with the junction between level shift element LS7 and constant current source CC5, and output terminal Q connects with level shift element LS8 and constant current source CC6 respectively. The following describes the configuration of the selection circuit in Fig. 2. This selection circuit comprises level shift elements LS1 through LS3, load elements LD1 and LD2, FETs Q1 through Q8, and constant current sources CC1 through CC3, which has the same configuration as the portion shown by the reference numeral 10 of the T-flip-flop circuit in Fig. 1. Therefore, only the portion different from the circuit in Fig. 1 is described below. In Fig. 2, input terminals A, A , B and B are connected to the gate electrodes of FETs Q1 through Q4, respectively. The gate electrodes of FETs Q5 and Q6 connect with switching terminals SW and SW , respectively. Output terminals Q and Q are connected to the junction between level shift element LS3 and constant current source CC3 and that between level shift element LS2 and constant current source CC3, respectively. In the SCFL-type logic circuit thus configured, if switching terminal SW is brought under high level, the signal with the same frequency as the input signal is output. Meanwhile, if switching terminal SW is brought under low level, the signal with 1/2 frequency of the input signal is output. However, the SCFL-type logic circuit having this configuration has the following problem. That is, because the circuit requires a selection circuit in addition to a T-flip-flop circuit, the number of elements increases. Therefore, a large area is necessary, resulting in decrease of integration. In view of the input terminal side, because the fan-in count equals 2, the current driving capacity at the first stage of this circuit must be increased. Therefore, it is necessary to increase the current to be supplied to the first-stage circuit. This prevents the power consumption from decreasing. On the contrary, unless the current to be supplied to the first stage is increased, a high speed circuit operation cannot be obtained. Accordingly, the purpose of this invention is to provide a source-coupled FET-logic-type logic circuit capable of accelerating the circuit operation without decreasing the integration due to an increase of the number of elements and without increasing the current to be supplied to the circuit. According to the present invention, there is provided a logic circuit according to claim 1. Preferred embodiments of the invention are indicated in the dependent claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit block diagram showing the T-flip-flop circuit of the SCFL-type logic circuit in the prior art; Fig. 2 is a circuit block diagram showing the selection circuit in Fig. 8. Fig. 3 is a circuit block diagram showing source-coupled FET-logic-type logic circuit related to the first embodiment of this invention; Figs. 4, 5A, and 5B are timing charts of the circuit in Fig. 3, which show the input signal, the output signal when switching terminal SW is low, and the output signal when the switching terminal is high, in this order; Fig. 6 is a circuit block diagram showing the SCFL-type logic circuit in the second embodiment of this invention; Fig. 7 is a circuit block diagram showing the ECL (emitter coupled logic)-type logic circuit in the third embodiment of this invention; and Fig. 8 is a block diagram showing a conventional T-flip-flop circuit. The following is the description of the embodiments of this invention using the drawings. In the embodiments, the same portions as in the prior art previously mentioned are designated by the same reference numbers and a description thereof is omitted. Fig. 3 shows the circuit block diagram of the SCFL-type logic circuit related to the first embodiment according to this invention. In Fig. 3, one of the ends of level shift element LS1 is connected a high-potential power supply V DD , and the other end thereof is connected to one end of load element LD1 and LD2. The other ends of load elements LD1 and LD2 are connected to the drain electrodes (first electrodes) of field effect transistors (FET) Q1 and Q2, respectively. The drain electrodes of FETs Q1 and Q2 are connected to those of FETs Q3 and Q4, respectively. The source electrodes (second electrodes) of the FETs Q1 and Q2 are connected to each other, and are connected to the drain electrode of FET Q5 whose gate electrode (control electrode) is coupled to input terminal IN . The drain electrode of FET Q1 is connected to the drain electrode of FET Q17 whose gate electrode is coupled to switching terminal SW. The source electrodes of the FETs Q3 and Q4 are connected to each other, and also to the drain electrode of FET Q18 whose gate electrode is connected to switching terminal SW . The source electrodes of FETs Q17 and Q18 are connected to each other, and also to the drain electrode of FET Q6 whose gate electrode is connected to an input terminal IN. The source electrodes of FETs Q5 and Q6 are connected to each other, and also to a low-potential power supply V SS by a constant current source CC1. The drain electrodes of the FETs Q1 and Q2 are connected to the gate electrodes of FETs Q7 and Q8 whose drain electrodes are grounded and whose source electrodes are connected to level shift elements LS2 and LS3, respectively. The level shift elements LS2 and LS3 are connected to the low-potential power supply V SS by constant current sources CC2 and CC3. Meanwhile, one of the ends of level shift element LS4 is connected to the high-potential power supply V DD , and the other end thereof is connected to one end of load elements LD3 and LD4. The other ends of load elements LD3 and LD4 are connected to the drain electrodes of FETs Q9 and Q10, respectively. The drain electrodes of FETs Q9 and Q10 are connected to those of FETs Q11 and Q12, respectively. The source electrodes of the FETs Q9 and Q10 are connected to each other, and also to the drain electrode of FET Q13 whose gate electrode is coupled to input terminal IN . The drain electrode of FET Q9 is connected to that of FET Q19 whose gate electrode is connected to switching terminal SW. The source electrodes of the FETs Q11 and Q12 are connected to each other, and also to the drain electrode of FET Q20 whose gate electrode connects with switching terminal SW . The source electrodes of FETs Q19 and Q20 are connected to each other, and also to the drain of FET Q14 whose gate electrode is connected to input terminal IN. The source electrodes of FETs Q13 and Q14 are connected to each other, and also to the low-potential power supply V SS by constant current source CC4. The gate electrodes of the FETs Q9 to Q12 are connected to those of FETs Q4, Q3, Q1, and Q2, respectively. The drain electrodes of FETs Q9 and Q10 are connected to the gate electrodes of FETs Q15 and Q16 whose drain electrodes are coupled to the high-potential power supply V DD , respectively, and whose source electrodes are connected to one end of level shift elements LS5 and LS6, respectively. The other ends of level shift elements LS5 and LS6 are connected to the low-potential power supply V SS by level shift element LS7 and constant current source CC5, by level shift element LS8, and constant current source CC6, respectively. In addition, the junction between level shift elements LS6 and LS8 connects with the gate electrodes of FETs Q1 and Q11. Similarly, the junction between level shift elements LS5 and LS7 connects with the gate electrodes of FETs Q2 and Q12. The output terminal Q is connected to the junction between level shift element LS7 and constant current source CC5 and the output terminal Q to the junction between level shift element LS8 and constant current source CC6. The operation of the logic circuit described above will now be explained, with reference to Fig. 3. First it will be explained how the logic circuit operates when the switching terminals SW and SW are set at a low level and a high level. When two complementary signals, which are at the low level and the high level, respectively, are input to the input terminals IN and IN , FETs Q5 and Q14 are turned on, whereas FETs Q6 and Q13 are turned off. As a result, FETs Q18 and Q20 are on, and FETs Q17 and Q19 are off. Assuming that the output terminals Q and Q are at the low level and the high level, respectively, then FET Q11 is turned off, and FET Q12 is turned on. Thus, an electric current flows through the path of: V DD → LS4 → LD4 → Q12 → Q20 → Q14 → CC4 → V SS . Hence, the output terminals Q and Q remain at the high level and the low level, respectively. Thus, as long as the input the output signal of the logic circuit remains at the same level as before. When the output terminal Q and Q are at the high level and the low level, respectively, FET Q1 is off, and FET Q2 is on. Hence, an electric current flows through the path of: V DD → LS1 → LD2 → Q2 → Q5 → CC1 → V SS . Thus, the gates of FETs Q4 and Q9 are at the high level, whereas the gates of FETs Q3 and Q10 are at the low level. When two complementary signals, which are at the high level and the low level, are input to the input terminals IN and IN , FETs Q6 and Q13 are turned on, whereas FETs Q5 and Q14 are turned off. Also, FETs Q9 and Q10 are turned on and off, respectively. As a result, an electric current flows through the path of: V DD → LS4 → LD3 → Q9 → Q13 → CC4 → V SS . Hence, the drain current of FET Q9 is at the low level whereas that of FET Q10 is at the high level. Therefore, the output terminals Q and Q are at the low level and the high level, respectively. As may be understood from the explanations above, when the potential of the input terminal rises from the low level to the high level, the output level of the logic circuit is inverted. As a result of this, the logic circuit outputs signals at half the frequency of the input signal, as is illustrated in Fig. 4 which represents the waveform of the input signal, and in Fig. 5A showing the waveform of the signal output from the output terminal Q. Now, it will be explained how the logic circuit operates when the switching terminals SW and SW are set at the high level and the low level. In this case, when two complementary signals, which are at the low level and the high level, respectively, are input to the input terminals IN and IN , FETs Q5 and Q14 are turned on, whereas FETs Q6 and Q13 are turned off. As a result, FETs Q18 and Q20 are on, and FETs Q17 and Q19 are off. Assuming that the output terminals Q and Q are at the low level and the high level, respectively, then FET Q11 is turned off, and FET Q12 is turned on. Thus, an electric current flows through the path of: V DD → LS4 → LD4 → Q12 → Q20 → Q14 → CC4 → V SS . Hence, the output terminals Q and Q remain at the high level and the low level, respectively. Thus, as long as the the input terminal IN is at the low level, the output signal of the logic circuit remains at the same level as before. When the output terminals Q and Q are at the high level and the low level, respectively, FET Q1 is off, and FET Q2 is on. Hence, an electric current flows through the path of: V DD → LS1 → LD2 → Q2 → Q5 → CC1 → V SS . Thus, the gates of FETs Q4 and Q9 are at the high level, whereas the gates of FETs Q3 and Q10 are at the low level. When two complementary signals, which are at the high level and the low level, are input to the input terminals IN and IN , FETs Q6 and Q13 are turned on, whereas FETs Q5 and Q14 are turned off. Also, FETs Q9 and Q10 are turned on and off, respectively. As a result, an electric current flows through the path of: V DD → LS4 → LD3 → Q9 → Q13 → CC4 → V SS . Hence, the drain current of FET Q19 is at the low level, whereas that of FET Q10 is at the high level. Therefore, the output terminals Q and Q are at the low level and the high level, respectively. As may be understood, when the potential of the input terminal IN rises from the low level to the high level, the output level of the logic circuit is inverted. As a result of this, the logic circuit outputs signals at half the frequency of the input signal, as is illustrated in Fig. 4 which represents the waveform of the input signal, and in Fig. 5A which shows the waveform of the signal output from the output terminal Q. It will now be explained how the logic circuit operates when the switching terminals SW and SW are set at the high level and the low level. When FETs Q6 and Q13 are on, and FETs Q5 and Q14 are off, none of FETs Q17, Q18, Q19 and Q20 can form a current path. Hence, the input terminals SW and SW remain at the high level and the low level, respectively. Hence, the input terminals IN and IN also remain at the high level and the low level, respectively. When the potential of the input terminal IN increases to the high level, the level of the output signal of the logic circuit is inverted. When two complementary signals, which are at the low level and the high level, are input to the input terminals IN and IN , FETs Q5 and Q14 are turned on, whereas FETs Q6 and Q13 are turned off. Also, FETs Q17 and Q19 are turned on, whereas FETs Q18 and Q20 are turned off. As a result, an electric current flows through the path of: V DD → LS1 → LD1 → Q17 → Q16 → CC1 → V SS . It also flows through the path of: V DD → LS4 → LD3 → Q19 → Q14 → CC4 → V SS . Therefore, the output terminals Q and Q are set at the low level and the high level, respectively. When the potential of the input terminal IN falls from the high level to the low level, the signal output from the output terminal Q has the waveform shown in Fig. 5B. As is evident from Fig. 5B, the logic circuit outputs signals at the same frequency as that of the input signal. Thus, the logic circuit having the configuration previously mentioned makes it possible to separately fetch the signal with the same frequency as the reference signal to be input and that with 1/2 frequency of the reference signal without installing a selection circuit. Therefore, it is possible to decrease the circuit area, improve the integration, and decrease the power consumption. In addition, because the fan-in count viewed from the input terminal side is "1", it is also possible to decrease the driving capacity at the first stage, compared with the existing SCFL-type logic circuit. Therefore, this also makes it possible to decrease the power consumption. It is also possible to make level shift elements LS1 through LS6 unnecessary depending on selection of FET threshold voltage. Moreover, level shift elements LS7 and LS8 should be set according to the input level of the logic circuit to the next stage. Fig. 6 is the circuit block diagram showing the second embodiment of this invention. In this embodiment, the circuit is configured by concreting the circuit elements configured as shown in Fig. 3 as follows. The description of configuration and overall operation of the elements other than those described here is omitted because it is the same as the configuration in the first embodiment. That is, resistors R1 through R6 are connected instead of level shift elements LS1 and LS4 and load elements LD1 through LD4 in the first embodiment. Diodes D1 through D6 are connected instead of level shift elements LS2, LS3, and LS5 through LS8. Constant current sources CC1 through CC6 comprise circuits consisting of FET Q21 and resistor R7, FET Q22 and resistor R8, FET Q23 and resistor R9, FET Q24 and resistor R10, FET Q25 and resitor R11, and FET Q26 and resistor R12, respectively. In Fig. 6, "V b " represents the prescribed external bias power supply. This makes it possible to separately fetch the signal with the same frequency as the reference signal to be input and that with 1/2 frequency of the said reference signal. Fig. 7 is the circuit block diagram showing the third embodiment of this invention. This embodiment shows an example when bipolar transistors are connected in the circuit in Fig. 3 instead of field effect transistors. Therefore, only the configuration is described below but the description of overall operation is omitted because it is the same as that of the first embodiment. In Fig. 7, collector electrodes (first electrodes) of bipolar transistors Q27 and Q28 are connected to high-potential power supply V CC through load elements LD1 and LD2 respectively, which connect with the collector electrodes of bipolar transistors Q30 and Q31, respectively. The emitter electrodes (second electrodes) of the transistors Q27 and Q28 are connected to each other, and are connected to the collector electrode of bipolar transistor Q31 whose base electrode (control electrode) connects with input terminal IN. The collector electrode of transistor Q27 connects with the collector electrode of bipolar transistor Q33 whose base electrode is connected to switching terminal SW. The emitter electrodes of the transistors Q29 and Q30 are connected to each other, and connect with the collector electrode of bipolar transistor Q34 whose base electrode is connected to switching terminal SW . The emitter electrodes of transistors Q33 and Q34 are connected to each other, and are connected to the collector electrode of bipolar transistor Q32 whose base electrode is connected to input terminal IN . The emitter electrodes of transistors Q31 and Q32 are connected to each other, and are connected to low-potential power supply VEE through constant current source CC7. The collector electrodes of bipolar transistors Q35 and Q36 are connected to the high-potential power supply V CC through load elements LD3 and LD4 respectively. The collector electrodes of transistors Q35 and Q36 connect with the collector electrodes of bipolar transistors Q37 and Q38, respectively. The emitter electrodes of the transistors Q35 and Q36 are connected to each other, and are connected to bipolar transistor Q39 whose base electrode is connected to input terminal IN. The collector electrode of transistor Q35 connects with the collector electrode of bipolar transistor Q41 whose base electrode is connected to switching terminal SW. The emitter electrodes of the transistors Q37 and Q38 are connected to each other, and connect with the collector electrode of bipolar transistor Q42 whose base electrode is connected to switching terminal SW similarly to transistor Q41. The emitter electrodes of transistors Q41 and Q42 are connected to each other, and are connected to the collector electrode of bipolar transistor Q40 whose base electrode is connected to input terminal IN . The emitter electrodes of transistors Q39 and Q40 are connected to each other, and are connected to low-potential power supply V EE through constant current source CC8. The base electrodes of the transistors Q35 through Q38 are connected to those of transistors Q30, Q29, Q27, and Q28, respectively. Output terminal Q is connected to the junction between the collector electrode of the transistor Q37 and the base electrode of transistor Q38, and output terminal Q to the junction between the collector electrode of transistor Q38 and the base electrode of transistor Q37. As mentioned, this invention makes it possible to provide a source-coupled FET-logic-type logic circuit capable of increasing the circuit operation speed without decreasing the integration due to an increase of the number of elements and increasing the current to be supplied to the circuit at the first stage. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A logic circuit comprising a plurality of switching means (Q27-Q42;Q1-Q6,Q9-Q14,Q17-Q20) each having a control electrode and a current path having a first electrode and a second electrode, further comprising: a first load element (LD1) connected at one end to a high potential power supply (V CC ;V DD ); a second load element (LD2) connected at one end to the high potential power supply (V CC ;V DD ); first switching means (Q27;Q1) having its first electrode (collector; drain) connected to the other end of the first load element (LD1); a second switching means (Q28;Q2) having its first electrode connected to the other end of the second load element (LD2) and having its second electrode (emitter;source) connected to the second electrode of the first switching means (Q27;Q1); a third switching means (Q29;Q3) having its first electrode connected to the first electrode of the first switching means (Q27;Q1); a fourth switching means (Q30;Q4) having its control electrode connected to the first electrode of the third switching means (Q29;Q3), its first electrode connected to the first electrode of the second switching means (Q28;Q2) and also to the control electrode of the third switching means (Q29;Q3), and its second electrode connected to the second electrode of the third switching means (Q29;Q3); a fifth switching means (Q31;Q5) having its first electrode connected to the second electrodes of the first and second switching means (Q27;Q1/Q28;Q2)and its control electrode connected to a first input terminal (IN) supplying a complementary signal; a sixth switching means (Q32;Q6) having its first electrode coupled to the second electrodes of the third and fourth switching means (Q29;Q3/Q30;Q4), its second electrode connected to the second electrode of the fifth switching means (Q31;Q5), and its control electrode connected to a second input terminal ( IN ) supplying a complementary signal; a first constant current source (CC7;CC1) connected between the second electrodes of the fifth and sixth switching means (Q31;Q5/Q32;Q6), on the one hand, and a low potential power supply (V EE ;V SS ), on the other hand; a third load element (LD3) connected at one end to the high potential power supply (V CC ;V DD ); a fourth load element (LD4) connected at one end to the high potential power supply (V CC ;V DD ); a seventh switching means (Q35;Q9) having its first electrode connected to the third load element (LD3) and its control electrode connected to the control electrode of the fourth switching means (Q30;Q4); an eighth switching means (Q36;Q10) having its first electrode connected to the fourth load element (LD4), its second electrode connected to the second electrode of the seventh switching means (Q35;Q9), and its control electrode connected to the control electrode of the third switching means (Q29;Q3) and also to the first electrode of the second switching means (Q28;Q2); a ninth switching means (Q37;Q11) having its first electrode connected to the first electrode of the seventh switching means (Q35;Q9), and its control electrode connected to the control electrode of the first switching means (Q27;Q1) and also to a first output terminal ( Q ) for supplying a complementary signal thereto; a tenth switching means (Q38;Q12) having its first electrode connected to the first electrode of the eighth switching means (Q36;Q10) and also to the control electrode of the ninth switching means (Q37;Q11), having its second electrode connected to the second electrode of the ninth switching means (Q37;Q11), and having its control electrode connected to the control electrode of the second switching means (Q28;Q2), to the first electrode of the ninth switching means (Q37;Q11), and to a second output terminal (Q) for supplying a complementary signal thereto; an eleventh switching means (Q39;Q13) having its first electrode connected to the second electrodes of the seventh and eight switching means (Q35;Q9/Q36;Q10), and its control electrode connected to the first input terminal (IN); a twelfth switching means (Q40;Q14) having its first electrode coupled to the second electrodes of the ninth and tenth switching means (Q37;Q11/Q38;Q12), its second electrode connected to the second electrode of the eleventh switching means (Q39;Q13), and its control electrode connected to the second input terminal ( IN ); a second constant current source (CC8;CC4) connected between the second electrodes of the eleventh and twelfth switching means (Q39;Q13/Q40;Q14), on the one hand, and the low potential power supply (V EE ,V DD ), on the other hand; a thirteenth switching means (Q33;Q17) having its first electrode connected to the first electrode of the first switching means (Q27;Q1), and its control electrode connected to a first switching terminal (SW) supplying a complementary signal; a fourteenth switching means (Q34;Q18) having its first electrode connected to the second electrodes of the third and fourth switching elements (Q29;Q3/Q30;Q4), its second electrode connected to the second electrode of the thirteenth switching means (Q33;Q17) and also to the first electrode of the sixth switching means (Q32;Q6), and its control electrode connected to a second switching terminal ( SW ); a fifteenth switching means (Q41;Q19) having its first electrode connected to the first electrode of the seventh switching means (Q35;Q9), and its control electrode connected to the first switching terminal (SW); and a sixteenth switching means (Q42;Q20) having its first electrode connected to the second electrodes of the ninth and tenth switching means (Q37;Q11/Q38;Q12), its second electrode connected to the second electrode of the fifteenth switching means (Q41;Q19) and also to the first electrode of the twelfth switching means (Q40;Q14), and its control electrode connected to the second switching terminal ( SW ). A logic circuit according to claim 1, characterized in that the switching means (Q27-Q42) are bipolar transistors. A logic circuit according to claim 1, characterized in that the switching means (Q1-Q6,Q9-Q14,Q17-Q20) are field effect transistors. A logic circuit according to claim 3, characterized by further comprising a first level shift element (LS1) connected between said high-potential power supply (V DD ) and the one end of the first and second load elements (LD1,LD2), and a second level shift element (LS4) connected between the high-potential power supply and the one end of the third and fourth load elements (LD3,LD4). A logic circuit according to claim 3 or 4, characterized by further comprising a seventeenth switching means (Q7) having its control electrode connected to the first electrode of the first switching means (Q1), its first electrode connected to the high potential power supply (V DD ), and its second electrode connected to the control electrode of the fourth switching means (Q4); an eighteenth switching means (Q8) having its control electrode connected to the first electrode of the second switching means (Q2), its first electrode connected to the high potential power supply (V DD ), and its second electrode connected to the control electrode of the third switching means (Q3); a third constant current source (CC2) connected between the second electrode of the seventeenth switching means (Q7) and the low potential power supply (V SS ); a fourth constant current source (CC3) connected between the second electrode of the eighteenth switching means (Q8) and the low potential power supply (V SS ); a nineteenth switching means (Q15) having its control electrode connected to the first electrode of the seventh switching means (Q9), its first electrode connected to the high potential power supply (V DD ), and its second electrode connected to the control electrode of the tenth switching means (Q12); a twentieth switching means (Q16) having its control electrode connected to the first electrode of the eighth switching means (Q10), its control electrode connected to the high potential power supply (V DD ), and its second electrode connected to the control electrode of the ninth switching means (Q11); a fifth constant current source (CC5) connected between the second electrode of the nineteenth switching means (Q15) and the low potential power supply (V SS ); and a sixth constant current source (CC6) connected between the second electrode of the twentieth switching means (Q16) and the low potential power supply (V SS ). A logic circuit according to claim 5, characterized by further comprising a third level shift element (LS2) connected between the second electrode of the seventeenth switching means (Q7) and the control electrode of the fourth switching means (Q4), a fourth level shift element (LS3) connected between the second electrode of the eighteenth switching means (Q8) and the control electrode of the third switching means (Q3), a fifth level shift element (LS5) connected between the second electrode of the nineteenth switching means (Q15) and the control electrode of said tenth switching means (Q12), and a sixth level shift element (LS6) connected between the second electrode of the twentieth switching means (Q16) and the control electrode of the ninth switching means (Q11). A logic circuit according to claim 6, characterized by further comprising a seventh level shift element (LS7) connected between the control electrode of the tenth switching means (Q12) and the first output terminal (Q), and an eighth level shift element (LS8) connected between the control electrode of the ninth switching means (Q11) and the second output terminal ( Q ). A logic circuit according to any one of claims 4 to 7, characterized in that the first and second level shift elements (LS1,LS4) comprises resistors (R1,R2). A logic circuit according to any one of claims 6 to 8, characterized in that the third to sixth level shift elements (LS2,LS3,LS5,LS6) comprise diodes (D1, D2, D3, D4). A logic circuit according to any one of claims 7 to 9 characterized in that the seventh and eighth level shift elements (LS7,LS8) comprise diodes (D5, D6). A logic circuit according to any one of claims 1 to 10, characterized in that the first to fourth load elements (LD1,LD2,LD3,LD4) comprise resistors (R3,R4,R5,R6). A logic circuit according to any one of claims 1 to 3, characterized in that the first and second constant current sources (CC1,CC4) each comprise a resistor (R7,R10). A logic circuit according to any one of claims 5 to 12, characterized in that the third to sixth constant current sources (CC2,CC3,CC5,CC6) each comprise a resistor (R8,R9,R11,R12). A logic circuit according to claim 13, characterized in that each of said first to sixth constant current sources (CC1 - CC6) comprises a series circuit having a resistor (R7 - R12) and a field-effect transistor (Q21 - Q26).

Inventors: NAGASAWA HIRONORI C O INTELLEC, NAGASAWA, HIRONORI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: H03K19
IPC codes: H03K3, H03K19