SEMICONDUCTOR CAVITY DEVICE WITH ELECTRIC LEAD

Abstract: The invention provides a method of making a semiconductor cavity device provided with an electrode within its cavity and an electric lead into the cavity and electrically continuous with the electrode therewithin, comprising depositing metal, in the shape of the lead and the electrode, on a non-conductive substrate, then providing an annular insulating layer in the shape of the boundary of the cavity on the substrate including where necessary on the metal of the lead, but not of the electrode, then (preferably in vacuo) placing on the insulating layer a semiconductor formed to define the remainder of the cavity, and applying a voltage between the substrate and the semiconductor whereby to promote electrostatic bonding between the insulating layer and the semiconductor.

Description: SEMICONDUCTOR CAVITY DEVICE WITH ELECTRIC LEAD This invention relates to a semiconductor cavity device provided with an electrode within its cavity and an electric lead into the cavity, and in particular to a method of making such a semiconductor cavity device. The background to the invention, and the invention itself, will be explained with reference to the accompanying drawings, 1n which:- Figure 1 1s a cross-section of a semiconductor cavity device of the kind to which the invention relates, and Figure 2 is a plan of the device of Figure 1, with the top layer removed for cl rity. The illustrated device may be made by known methods or by. the improved method according to the invention as described below. Such devices are well known to have wide applicability as pressure sensors and accelero eters, as will be described. The semiconductor cavity device of Figures 1 and 2 comprises a diaphragm of semiconductive material 1 (typically silicon ) bonded to a non-conductive substrate 3 (typically glass) through an annular insulating layer 4. The substrate 3 carries a metallic electrode 5a which is disposed between the semiconductive material 1 and the substrate 3 but which is electrically continuous with an electrical feedthrougb or lead 5b extending therefrom and terminating at a point beyond an edge of the semiconductive material 1 for connection to external circuitry. Such an arrangement, with the electrode 5a disposed within an evacuated hermetically sealed num ular cavity 7 between the substrate 3 and the silicon 1, is common in capacitatlve pressure sensors, accelerometers, etc. The pressure or acceleration force, as the case may be, depresses the diaphragm of silicon 1, changing the capacitance of the cavity (the glass 3 being relatively rigid). To measure this capacitance, the metallic electrode 5a must be provided on the glass with the lead 5b to external measuring circuitry. Many attempts have been made to seal electrical feedthroughs 1n semiconductor devices, such as diffused feedthroughs, providing etched tunnels for the feedthroughs, which tunnels are subsequently filled with metal, and providing conductive glass channels. Problems commonly encountered with these approaches are high series resistance, poor electrical isolation, gas leakage paths and complicated, and hence expensive, process steps, themselves being so uncertain as to lead to high reject rate in production, this further serving to increase the cost per usable unit. It has been proposed in UK Patent Application GB 2208754A to provide a method of hermetically sealing an electrical feedthrough for such a semiconductor cavity device which overcomes those problems by producing an electrically insulating layer (e.g. silicon nitride) on a first surface of a semi-conductive material (e.g. silicon), producing one o more electrodes on a non- conductive substrate (e.g. glass) of area greater than the first surface, with each electrode having an electrical feedthrough associated therewith, placing the silicon nitride layer in contact with the glass such that each electrical feedthrough extends beyond the first surface, and bonding the semiconductive layer to the substrate to provide an hermetic seal around the feedthrough and thus protect the integrity of the electrode associated therewith and disposed between the semiconductive layer and the substrate. The bonding step is preferably accomplished using the field- assisted bonding process which is sometimes referred to as anodic bonding, Mallory bonding or electrostatic bonding. With this process, the semiconductive sheet and the substrate are electrostatically pulled together at a suitably elevated temperature and it has been postulated that both the substrate and insulating layer soften and thus flow or deform around the feedthroughs to effect a bond " between the insulating layer and the substrate. The "bond" between the feedthrough and the Insulating layer is believed to be purely physical but nevertheless such that an hermetic seal 1s provided to the cavity. The force of the electrostatic bonding, although advantageous for ensuring the integrity of the cavity, introduces a new problem. The force is sometimes sufficient to break the feedthrough at its point of emergence from the insulating layer 4 and break its electrical continuity. This is a further cause of rejects, and it will readily be seen that the later the stage of manufacture, the more value has been added to the components, and hence the more costly any reject. Thus, while reducing reject rates at any stage in manufacture is useful, it would be particularly desirable to reduce the reject rate at this bonding stage, representing as it does the final assembly of the semiconductor device (pressure sensor, accelero eter, etc). The present Invention provides, therefore, a novel and improved method of making a semiconductor cavity device provided with an electrode within its cavity and an electric lead into the cavity and electrically continuous with . the electrode therewithin, comprising depositing metal, in the shape of the lead and the electrode, on a non-conductive substrate, then providing an annular Insulating layer in the shape of the boundary of the cavity on the substrate including where necessary on the metal of the lead, but not of the electrode, then (preferably in vacuo) placing on the insulating layer a semiconductor formed to define the remainder of the cavity, and applying a voltage between the substrate and the semiconductor whereby to promote electrostatic bonding between the insulating layer and the semiconductor. The invention also provides a semiconductor cavity device provided with an electrode within its cavity and an electric lead into its cavity and electrically continuous with the electrode therewithin, when made by the aforesaid method. The substrate is conveniently glass (such as a borosilicate glass), preferably with a thermal expansion coefficient matched to that of the semiconductor, which would usually be single- crystal silicon, no other material being as cheap, consistent and well-characterised. Suitable proprietary glasses include Corning 7070, Schott 8248 and Corning 1729, which also have a suitably high volume resistivity for the electrostatic bonding. The last of these three glasses, though more expensive, can (and must) be bonded at higher temperatures (e.g. 600°C), having a coefficient of thermal expansion compatible with silicon up to this temperature (the other glasses diverging above 400°C). The metal deposition is normally performed imagewise by techniques well established in the microelectronics industry, such as sputtering or evaporation in conjunction with photolithography, to a thickness of a fraction of a micron, such as 0.05μm. Each electrode and lead may be of a two-layer construction, for example a layer of nickel chromium (N1Cr) covered by one of gold (Au), although other metal combinations and alloys may be employed, especially chromium or molybdenum in place of NiCr. The NiCr or chromium provides a very good adhesion to a glass substrate and gold provides a low resistivity electrical path. If desired, NiCr, Cr, Al , Mo, Ti or other suitable metal can be deposited (e.g. sputtered or evaporated) on the underside of the glass too, to improve field uniformity during the electrostatic bonding. The insulating layer can conveniently be silicon dioxide Si0 2 or silicon nitride S1 3 N 4 , applied typically to a depth of lμm. Both these materials deposit equally successfully over metal (i.e. the electrode lead) as over glass. Si 3 N 4 has a much more glass-compatible coefficient of expansion than has S10 2 , and 1f chosen, Mo will be preferred to NiCr in the preceding paragraph. The insulating layer should not be too thick for successful electrostatic bonding. Otherwise, the thicker the insulating layer, the better the electrical isolation of the electrode and lead, and the lower the parasitic capacitance. Moreover, a thicker insulating layer gives a stronger mechanical protection to the lead during the electrostatic bonding. This protection reduces the rate of rejects attributable to lead breakage. The electrostatic bonding with the substrate (e.g. glass) as the negative electrode is strong enough to seal the cavity hermetically. It tends to withdraw cations from the bonding surface of the glass yielding an imrnobile S10 2 skeleton. Thus the cation concentration profile 1s characteristic of the invention, as are the relative strengths of the 1-4 and 4-3 bonds. The other component participating in the electrostatic bonding is the semiconductor 1, typically silicon. As already mentioned, it constitutes a diaphragm (typically 400 μm thick) forming one face of the nummular cavity 7, which is 2%mm in diameter and lμm deep. The better to define the diaphragm, an optional annular boundary trench 25μm deep and 250μm (%mm) across is etched into the silicon. The trench if present affords a more uniform diaphragm movement and reduced bending and reduces stray capacitance. The invention will now be described by way of example. SILICON PROCESSING Boron-doped (O.OlΩcm) three-inch diameter (1ID-orientation silicon wafers are used, each of which is to make 250 devices each being 4mm square. The high conductivity helps minimise the eventual device electrical dissipation and the (111) orientation is chosen due to its low temperature coefficient of the elastic modulus. The silicon wafers are first coated overall with a 0.5μm thick layer of silicon dioxide using plasma-enhanced chemical vapour deposition. This oxide layer is then patternwise protected with positive photoresist leaving (optionally) exposed circles (to become the trenches 8) and an exposed grid to assist later separation of the devices and to leave open the leads 5b. The exposed oxide is then removed using 7:1 buffered hydrofluoric acid (BHF) to reveal the underlying silicon. This silicon is then anisotropically etched in a plasma etch system to produce the trenches 25μm deep with near-vertical side walls and the grid. A gas mixture of SiCl 4 and Cl 2 is used to obtain the desired profile, under the following conditions: Substrate Temperature 20°C R.F. Power 40 Watts (13.56 MHz) SiCl 4. flow rate 28 seem (28 seem = the mass per minute which would be yielded by a flow rate of 28 ml/minute at S.T.P.) Cl 2 flow rate 12 seem Pressure 40 milliTorr These conditions give a 10:1 etch selectivity of the silicon with respect to the S10 2 mask, i.e. the silicon etch rate is 106.7nm min -1 compared with 10.7nm min -1 for the Si0 2 . After completing the trench etching, the remaining S10 2 masking layer is removed in 7:1 BHF (which does not attack silicon) and the wafer cleaned ready for bonding. GLASS PROCESSING Corning glass type 7070 is used in three inch diameter disc form. The surfaces are polished to a specular finish (surface roughness <25 nm r.m.s.) with the faces parallel to within ± lμ and the thickness controlled to 3mm ± Iμm. The glass 3 is cleaned with ultrasonic agitation using detergent, deionised water and absolute alcohol in succession. This is followed by imagewise positive photolithography so as to cover the glass except for the 250 areas 5a-5b with photoresist. The glass discs are then two-stage overall batch coated using D.C. magnetron sputtering, the first layer consisting of lOnm of nichrome which serves as a keying layer for the subsequent 30nm of gold. Lift-off processing of the underlying photoresist using acetone and ultrasonic vibration results in the desired glass metallisation pattern 5a/5b. The glass is then recleaned and overall coated, using plasma-enhanced chemical vapour deposition, with Iμm of silicon nitride: Substrate Temperature 300°C Pressure 650mTorr 2% SiH 4 /98%N 2 Flow Rate 2000 seem NH 3 Flow Rate 14 seem R.F. Power - High Frequency 20 (13.56 MHz for 7 seconds followed by 187.5 kHz for 1% seconds, repeated until the desired thickness is attained) This switching technique produces an optimised low tensile stress of 9.378 x 10 7 Nm~ z . Upon completion of the Iμm thick silicon nitride layer, the appropriate pattern of photoresist is applied to it and etched using 7:1 BHF. This does not affect the underlying metallisation, but leaves the silicon nitride coating 4 defining the cavities 7. An optional step at this juncture Is to apply further metallisation (not shown) to the upper (free) surface of the Insulating coating 4, circumferentially displaced from the thin 5a-5b connection, and extending to form a contact pad on the platform (described later) spaced from 5b. The last processing step on the glass is to coat the backside overall by DC magnetron sputtering with a lOnm (transparent) nichrome layer to ensure uniform electrostatic bonding. The glass is now ready for bonding. SILICON/GLASS BONDING In the case of making a pressure sensor, the silicon 1 and glass 3 need to be bonded in vacuum to ensure a 'zero-pressure' reference cavity. A turbomolecular pumped chamber is therefore used for bonding at a pressure of <10 ~s mbar. The silicon 1 to be bonded is placed on a platen mounted on a XYZΘ Z (all axes movable, and rotatable about axis z) micromanipulator stage. The glass 3 is mounted on a platen fixed above the manipulator stage such that the patterned face (i.e. that carrying metal 5 and nitride 4) faces downwards, towards the silicon wafer (i.e. all upside down compared with Figure 1). The glass can be viewed through a viewpoint via a hole in the centre of the platen. A stereo microscope is positioned above this viewpoint. After pumpdown, both platens are heated until the silicon 1 and glass 3 are both at a temperature of 400°C. The silicon wafer is then aligned with the glass using the XY and θ z manipulators so that the two patterns coincide when viewed through the stereo microscope. The two components are then brought together using the Z control. A voltage of 4kV is then applied across the two platens such that the silicon is positive. This Initiates the bonding process which takes 15 minutes to complete. The bonded assemblies are then removed from the bonding rig. (At this juncture, if required, the silicon 1 is lapped or ground to that thickness which will produce a full scale deflection of the diaphragm at a desired applied pressure.) Then, the bonded assemblies are again mounted in the DC magnetron sputtering system and the silicon backsides are coated with lμm of aluminium which 1s then further treated in dry nitrogen at 450°C for 15 minutes to provide an ohmic contact for subsequent lead attachment, but this aluminium coating step can be omitted if, as described above, metallisation of the free surface of the layer 4 has been performed before application to it of the wafer 1. The bonded assemblies are now ready for dicing Into individual pressure sensors. However before dicing into the 4mm pills a depth-controlled saw cut is made from the silicon side, using a 0.125mm diamond saw, and stopping within 15μm of the nitride fayer 4. The cut is made (0.5mm wide) towards the platform 3/5b to ensure that when the individual pressure sensors are separated by cutting along the 0.125mm wide grid lines the bonding pads 5b on the glass surface become exposed for attachment to external circuitry. The semiconductor cavity device of Figures 1 and 2 may be modified. In the modification, the glass substrate is widened so that the platform 3/5a projecting along one side of the silicon 1 is 5mm rather than y.mm wide. This extra surface allows the metallisation at 5b to be made more sophisticated, in particular it may form part of a thin film hybrid circuit with discrete components and integrated circuit chips added later in die form, with external leads being bonded to suitable pads on the glass platform. The silicon 1 is also modified. On the cavity-facing surface of the diaphragm, an optional metallisation is deposited, and the trench 8 is omitted. That metallisation makes ohmic contact (or, if omitted, the silicon 1 makes ohmic contact) with the metallisation 9, which emerges towards the platform via a route between the silicon 1 and the insulator 4. To avoid spurious capacitance effects, this route was as described well spaced from the route 5a-5b, the length of the platform making this possible. Since the front-end circuitry is thus now integrated into the pressure sensor, no separate hybrid circuit will be needed for electrically interfacing with the sensor. This reduces subsequent packaging costs. In addition, the silicon back surface is now free from any bond wires; this also produces packaging benefits. For instance, in wafer form, one can bond a second glass disc, suitably preprocessed with an array of holes matching the circular cavities in the silicon, to the top (as drawn in Figure 1) of the silicon. This glass can then (after dicing) act as the bonding surface to hold the assembly where it can measure a pressure. This not only isolates the silicon from packaging stresses but also Isolates the associated circuitry from the pressure medium. Under extreme high pressure, the glass 3 beneath the annular insulator 4 tends to become more compressed than that beneath the cavity 7. This produces an additional capacitance change which is non-elastic and therefore undesirable. For such applications, the glass 3 may be thinned from underneath after all the above steps, thus minimising this non-elastic effect, and then bonding the glass to a silicon support wafer (not shown), which compresses elastically.

Claims: CLAIMS 1. A method of making a semiconductor cavity device provided with an electrode within its cavity and an electric lead into the cavity and electrically continuous with the electrode therewithin, comprising depositing metal, in the shape of the lead and the electrode, on a non-conductive substrate, then providing an annular insulating layer in the shape of the boundary of the cavity on the substrate including where necessary on the metal of the lead, but not of the electrode, then (preferably in vacuo) placing on the insulating layer a semiconductor formed to define the remainder of the cavity, and applying a voltage between the substrate and the semiconductor whereby to promote electrostatic bonding between the insulating layer and the semiconductor. 2. A method according to Claim 1, wherein the substrate is glass. 3. A method according to Claim 2, wherein the glass and the semiconductor are selected with matching thermal expansion coefficients. 4. A method according to any preceding claim, wherein the semi-conductor is single-crystal silicon. 5. A method according to any preceding claim, wherein the insulating layer is Si0 2 or silicon nitride SI34. 6. A semiconductor cavity device having an electrode within its cavity and an electric lead into the cavity and electrically continuous with the electrode therewithin, when made by the method of any of Claims 1 to 5.

Inventors: ROGERS TONY WILLIAM JAMES, ROGERS, TONY, WILLIAM, JAMES
Applicants: NAT RES DEV, NATIONAL RESEARCH DEVELOPMENT CORPORATION
Application year: 1990
Main classification: G01L9
IPC codes: G01L9