Delay circuit

Abstract: A delay circuit includes a memory (4) addresses of which is designated by a counter (6) incremented in response to each clock signal from an initial value set by an initial value setting circuit (7) to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier (13). A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter to the initial value is generated by a first signal generating circuit (9) when the end value is reached and a setting completion signal is generated by a second signal generating circuit (11) when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a delay circuit. More specifically, the present invention relates to a delay circuit utilizing a memory and capable of varying a delayed time. A delay circuit according to the pre-characterizing portion of claim 1 is disclosed for example in US-A-4 731 835. Description of the Prior Art US-A-4 731 835 discloses a delay circuit for an analog signal comprising: an A/D converting circuit for A/D converting an input signal; a memory for storing a digital signal outputted from said A/D converting circuit; a D/A converting circuit for D/A converting a digital signal outputted from said memory; and a counter for designating addresses to be used of said memory. By A/D converting an input analog signal to be written in a memory and by reading the signal being stored in the memory to be D/A converted, it is possible to obtain a delay circuit having a delay time from the writing timing to the reading timing. For example, with respect to addresses of the memory from A l address to A N address, if the writing of the signal as A/D converted and reading the same are repeated, it is possible to obtain a delay time equal to clock signals of N, and if the number of addresses being used is changed, it is possible to vary the delay time correspondingly thereto. In such a delay circuit, if the number of addresses to be used of the memory is changed to vary the delay time in the course of the operation thereof, addresses that have not used until this time become to be newly used. In such a case, since random data are stored in the addresses which become to be newly used, there was a problem that a noise is generated on the output if the random data are read and used as they are. SUMMARY OF THE INVENTION Therefore, a principal object of the present invention is to provide a novel delay circuit. Another object of the invention is to provide a delay circuit using a memory, in which no noise is generated on an output even-if addresses of the memory become to be newly used to vary a delay time in the course of an operation thereof. These objects are achied by a delay circuit as disclosed in claim 1. Since the input signal is A/D converted and temporarily stored in the memory and the signal read from the memory is D/A converted to obtain an output, it is possible to constitute a delay circuit in which a time period during when the signal is stored in the memory becomes a delay time. In such a case, since the addresses of the memory are designated by the counter, it is possible to vary a delay amount by controlling a counted value of the counter. An initial value is set in the counter by the initial value setting circuit. When the setting of the initial value is completed, the setting completion signal is generated and, when the end value is reached by the counted value of the counter, the control signal is generated. The muting signal generating circuit generates the muting signal in response to the setting completion signal and the control signal. Therefore, by utilizing the muting signal, it is possible to prevent a noise from being generated at a timing when the initial value is changed to vary the delay time in the course of an operation thereof. In accordance with the present invention, it is possible to obtain a delay circuit in which a delay time can be arbitrary varied. Furthermore, in such a delay circuit, it is possible to prevent a noise from being generated at an output even when the delay time is varied. The objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the present invention when taken in conjunction with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an embodiment in accordance with the present invention. Fig. 2 is a timing chart showing an operation of Fig. 1 embodiment. DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 is a block diagram showing an embodiment in accordance with the present invention. An analog input signal is applied to an input terminal 1, and the analog input signal is converted into a digital signal by an A/D converting circuit 2. A clock signal, writing signal, reading signal and etc. to be applied to respective portions of this embodiment are generated by an oscillator 3. The reference numeral 4 denotes a memory to which an output signal of the A/D converting circuit 2 is stored in response to the writing signal. A digital signal read from the memory in response to the reading signal is converted into an analog signal by a D/A converting circuit 5. The reference numeral 6 denotes a counter for designating addresses to be used in the memory 3. To the counter 6, an initial value is set by an initial value setting circuit 7. More specifically, an output of the initial value setting circuit 7 is latched by a latch circuit 8 to be applied to the counter 6. A first signal generating circuit 9 detects that an end value is reached by the counter 6 and outputs an output signal in response to such a detection. The output signal of the first signal generating circuit 9 and a clock signal obtained from the oscillator 3 are applied to an AND gate 10 which generates a control signal for controlling the latch circuit 8. A second signal generating circuit 11 generates a setting completion signal when an initial value setting operation by the initial value setting circuit 7 is completed. The control signal generated by the AND gate 10 and the setting completion signal generated by the second signal generating circuit 11 are applied to a muting signal generating circuit 12 which generates a muting signal in response thereto. In addition, a buffer amplifier 13 is connected between an output of the D/A converting circuit 5 and an output terminal 17. As shown in Fig. 1, the muting signal generating circuit 12 includes a first D-FF (D-type Flip-Flop) 14, a second D-FF 15 and a NAND gate 16. A data terminal D and a clock terminal CL of the first D-FF 14 are connected to a power source (not shown) and an output terminal of the second signal generating circuit 11, respectively. A data terminal D and a clock terminal CL of the second D-FF 15 are connected to an output Q of the first D-FF 14 and an output of the AND gate 10, respectively. The NAND gate 16 has a first input connected to the output of the AND gate 10, a second input connected to an output Q of the second D-FF 15, and an output connected to a reset R input of the first D-FF 14. Now, a description will be made on a generic operation of Fig. 1 embodiment. A delay time for the input signal is defined by the number of addresses being used of the memory 4. If the memory 4 has addresses of X and an initial address of addresses to be used is A N , the addresses of X - N are used for delaying the signal and, it is possible to obtain a delay time that is X - N times an interval of address designating clocks. When the initial value setting circuit 7 is operated to set an initial value of the counter 6, data of the initial value setting circuit 7 is latched by the latch circuit 8, and the initial value is set into the counter 6 by the data outputted from the latch circuit 8. The counter 6 designates the address of the memory 4 in response to the initial value as set. Therefore, the address (A N , for example) being designated of the memory 4 is brought in a writable or readable state. In such a state, when the reading signal is applied to the memory 4 from the oscillator 3, the data stored in the address A N is read to a terminal Q of the memory 4, and the data is converted into an analog signal by the D/A converting circuit 5 to be outputted to the output terminal 17 through the buffer amplifier 13. Thereafter, when the writing signal is applied to the memory 4 from the oscillator 3, the digital signal which was applied to the input terminal 1 and A/D converted by the A/D converting circuit 2 is written in the memory 4. Then, when the counter 6 is incremented in response to the clock signal from the oscillator 3, the next address A N + 1 of the memory 4 is designated so that the data is read and written to or from the address A N + 1. Since the counter 6 is sequentially incremented in response to the clock signal from the oscillator 3, the reding and writing operations with respect to all the addresses from A N to A X are sequentially performed. If the end value is reached by the counted value of the counter 6, a signal indicative of that the end value is reached is generated from the first signal generating circuit 9. The signal is passed through the AND gate 10 in response to the clock signal from the oscillator 3 to be applied to the latch circuit 8 as a control signal. Therefore, the output signal of the latch circuit 8 is applied to the counter 6 so that the counted value of the counter 6 is returned to the initial value. Thereafter, the same or similar operations are repeated. Therefore, a signal written into an arbitrary address of the memory 4 is read from the memory after a lapse of a time determined by the intervals of the clock signal and the number of addresses being used of the memory 4, thereby to delay the signal by that time. Meanwhile, as seen from the above description, in one cyclic period after that the value of the counter 6 is set as the initial value, the random data that is stored in advance in the address being used of the memory 4 is read and outputted through the D/A conversion by the D/A converting circuit 5. An output corresponding to the random data has nothing to do with the input signal, and therefore, the output signal due to the random data becomes a noise with respect to the input signal and to be generated at the output terminal 17. In the embodiment shown in Fig. 1, such a noise due to the random data can be prevented from being generated, and such a preventing operation will be described with reference to Fig. 2. At every timing when the end value is reached by the counted value of the counter 6, the control signals C1, C2 and C3 as shown in Fig. 2 (A) are generated. If the initial value setting circuit 7 is operated at a time t0 in the course of the delaying operation so as to set a further initial value, the output signal between the control signals C2 and C3 is generated based upon the random data, and therefore, a noise occurs. However, as shown in Fig. 2 (B), the setting completion signal is generated from the second signal generating circuit 11 at a time t1 when the setting of the further initial value is completed, to be applied to the first D-FF 14. Therefore, as shown in Fig. 2 (C), the output Q of the first D-FF 14 becomes "H" in response to the rising edge of the setting completion signal. In such a state, when the control signal C2 is generated from the AND gate 10, which is applied to the clock terminal CL of the second D-FF 15 so that the output Q of "H" of the first D-FF 14 is fetched by the second D-FF 15. Therefore, as shown in Fig. 2 (D), the output Q of the second D-FF 15 becomes "H". The Q output of "H" is applied to the buffer amplifier 13 as the muting signal, and therefore, the output signal from the D/A converting circuit 5 is muted by the buffer amplifier 13. The output Q of the second D-FF 15 is also applied to the NAND gate 16. Then, when the control signal C2 is generated at the output terminal of the AND gate 10, the output of the NAND gate 16 becomes "L". Therefore, the first D-FF 14 is reset, and as shown in Fig. 2 (C), the output Q of the first D-FF 14 becomes "L". When the control signal C3 is generated from the AND gate 10 at a time t3, the Q output of "L" from the first D-FF 14 is fetched by the second D-FF 15. Therefore, as shown in Fig. 2 (D), the output Q of the second D-FF 15 also becomes "L". Such a series of operation is performed at every timing when the initial value setting circuit 7 is operated. As understood through comparison of Fig. 2 (A) and Fig. 2 (C), a time period during when the noise due to the random data is generated and a time period during when the muting signal obtained at the output Q of the second D-FF 15 is generated are exactly coincident with each other. Therefore, it is possible to surely prevent a delayed signal including a noise from being generated at the output terminal 17. In addition, in the embodiment described above, in order to prevent a noise due to random data read from the memory 4 when the initial value is changed from being outputted, the buffer amplifier 13 mutes the output of the D/A converting circuit 5. However, it is easy for those skilled in the art to modify such a circuit configuration. For example, the output from the memory 4 itself may be disabled by a gate circuit when the random data is read from the memory 4, or the output from the D/A converting circuit 5 may be disabled. Therefore, it is to be understood that a specific configuration of a means for preventing a noise due to the random data is not so important for the invention. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A delay circuit, comprising: A/D converting means (2) for A/D converting an input signal; memory means (4) for storing a digital signal outputted from said A/D converting means (2); D/A converting means (5) for D/A converting a digital signal outputted from said memory means (4); counter means (6) for designating addresses to be used of said memory means (4); outputting means (13, 17) for outputting an output of said D/A converting means (5) as a delay signal characterized in that said delay circuit further comprises: initial value setting means (7, 8) for initially setting an initial value of said counter means (6); first signal generating means (9, 10) for detecting that an end of value of said counter means (6) is reached and for generating a control signal; second signal generating means (12) for generating a setting completion signal when an initial value setting operation by said initial setting means (7, 8) is completed; disabling signal generating means (12, 14, 15, 16) for generating a disabling signal in response to said setting signal and said control signal; and disabling means (13) for substantially disabling the output of said memory means (4) to prevent a noise due to random data from said memory means (4) from being outputted through said outputting means (13,17). A delay circuit in accordance with claim 1, wherein said memory means (4) is constructed such that a plurality of addresses are sequentially designated in response to each address designating signal obtained from said counter means (6), and the delay time is defined by the number of the addresses as designated. A delay circuit in accordance with claim 1 or 2, wherein said disabling signal generating means (12) includes a first D-Flip Flop (14) having a clock input (CL) to which said setting completion signal is applied, a second D-Flip Flop (15) having a data-input (D) to which an output signal of said first D-Flip Flop (14) is applied, a clock input (CL) to which said control signal is applied and a gating means (16) which generates a reset signal for said first D-Flip Flop (14) in response to said control signal and an output of said second D-Flip Flop (15), whereby said disabling signal is generated at the output of said second D-Flip Flop (15).

Inventors: ONAYA MASATO, TANNO MASAYA, ONAYA, MASATO, TANNO, MASAYA
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1990
Main classification: H03K5
IPC codes: H03H17, H03K5