Drive circuit for an IGBT device

Abstract: A MOS transistor (Q M ) detects an increase of the collector current (I C ) of an IGBT device (Q₀). When an excess current flows, the transistor (Q M ) turns on, which restricts the gate voltage (V G ) of the IGBT device (Q₀) to decrease the collector current (I C ). This protects the IGBT device (Q₀) from the ex­ cess current. A Zener diode (D Z ) placed in a path which is for detecting the excess current of the IGBT device (Q₀) restricts the current passing through the path. This decreases a reac­ tive power which is consumed in protecting the device (Q₀) from the excess current while protecting a drive circuit from an erroneous operation.

Description: The present invention relates to a drive circuit for driving an IGBT (Insulated Gate Bipolar Transistor) device which is a semiconductor switching device and, more particularly, to the protection of an IGBT from an excess current. An IGBT device is characterized by a high breakdown voltage and a large current capacity similar to a bipolar transistor. Further, similar to a power MOSFET, the IGBT device has a high input impedance due to its insulation gate structure, so that it is also characterized by easiness in driving and rapid switching capability. Hence, the IGBT device has recently attracted attention as a new device having such characteristics. Devices named IGT, COMFET, GEMFET, MBT or BiFET are commercially available. Fig. 1A is a diagram showing a symbol of an IGBT device, including a gate G, a collector C and an emitter E. Fig. 1B is a circuit diagram showing an equivalent circuit of the IGBT device. Referring to Fig. 1B, the IGBT device has its gate G connected to a gate of a MOS transistor Q MOS and its emitter E connected to a source of the MOS transistor Q MOS . A pnp transistor Q 1 and an npn transistor Q 2 which make up a thyristor are inserted between the collector C and the emitter E. The transistor Q 1 has its emitter connected to the collector C of the IGBT device and its base connected to a collector of the transistor Q 2 and its collector connected to a base of the transistor Q 2 . The transistor Q 2 has its collector connected to a drain of the MOS transistor Q MOS through a modulation resistor R M and its emitter connected to the emitter E of the IGBT device. A resistor R BE is connected between the base and emitter of the transistor Q 2 . A collector current I C is shown in Figs. 1A and 1B. Now, protecting the IGBT device from an excess current will be described. When the collector current I C rises to be above a predetermined value, a parasitic thyristor composed of the transistors Q 1 , Q 2 turns on. Once current begins to flow in response to this turn on, this current can not be broken and generates heat which destructs the IGBT device. This phenomenon is called latch-up, and the current value is referred to as a latch-up current. So, sufficient care must be taken in using the IGBT device with regard to the above problems. For protecting the IGBT device from an excess current, it is important to restrain an excess current below the latch-up current in the IGBT device. The collector current I C of the IGBT device depends upon a gate voltage. If the gate voltage is above a predetermined value, the collector current would rise above the latch-up current to cause the latch-up. Fig. 2 is a circuit diagram showing a conventional drive circuit for the IGBT device. A switching unit SU is provided with voltage sources V GE1 and V GE2 . A negative potential terminal of the voltage source V GE1 and a positive potential terminal of the voltage source V GE2 are grounded. The positive potential terminal of the voltage source V GE1 is connected to an output point OUT via an output resistor R O and a switching element S1. The negative potential terminal of the voltage source V GE2 is connected to the output point OUT via a switching element S2. The output point OUT is connected to a gate of an IGBT device Q O via a gate resistor R G . The IGBT device Q O has its emitter grounded and its collector connected to a positive potential terminal of a voltage source V CC via a load LD and a current sensor CS. A negative potential terminal of the voltage source V CC is grounded. Capacities C GC and C GE exist between the gate and collector and between the gate and emitter as a parasitic capacity, respectively. An output of the current sensor CS is applied to control system. When the current sensor CS senses an excess current, the control system SY performs its protecting operation to turn off the switching element S1 and to turn on the switching element S2, whereby the IGBT device Q O is forced into the OFF condition. Now, an operation of the above prior art will be described. A control signal from the control system SY decides the ON /OFF condition of the switching elements S1, S2. When the switching element S1 is in the ON condition, and the switching element S2 is in the OFF condition, the IGBT device Q O turns on to supply current to the load LD. When the switching element S1 is in the OFF condition, and the switching element S2 is in the ON condition, the IGBT device Q O turns off not to supply current to the load LD. Thus, the current supplied to the load LD is controlled by controlling the ON/OFF condition of the switching elements S1, S2. An abnormal operation with regard to the prior art will be described. When a motor, for example, is employed as the load LD, the supply voltage V CC could be directly applied to the collector of the IGBT device Q O due to an abnormal operation of the motor, as shown by a dotted line in Fig. 2. Since a voltage of several hundreds volt is used as the supply voltage V CC , the collector current I C is so rapidly increased as to cause the IGBT device Q O to generate heat. The collector current I C is further increased as the temperature of the IGBT device Q O goes up, so that the parasitic thyristor composed of the transistors Q 1 , Q 2 shown in Fig. 1B can easily turn on. As a result, when the load LD becomes short circuited, latching-up due to a heat generation is liable to occur before the above-mentioned protection operation is executed by the control system SY. Further, when the load LD is short-circuited, a high voltage from the supply voltage V CC is instantaneously applied across the collector and emitter. At this time, the gate voltage is instantaneously increased because the parasitic capacities C GC , C GE exist. The increased voltage Δ V GE is given by the following equation with an increased voltage Δ V CE applied across the collector and emitter in step manner: Δ V GE = Δ V CE X C GC /C GE The increased voltage Δ V CE is ranged approximately from tens of volts to hundreds of volts, and the capacity ratio C GC /C GE is approximately 0,01 - 0,05. For example, providing Δ V CE = 100V and C GC /C GE 0,05, Δ V GE = 5V in accordance with the equation (1). In this case, the gate voltage is increased by 5V compared with the gate voltage at the normal operation, so that the collector current I C increases and latching-up may instantaneously occur. Reducing a value cf the gate resistor R G relieves the latch-up due to the voltage increase of the capacitive components to some extent. However, when the resistance of the gate resistor R G is reduced too much, a variation dV/dt becomes large on switching to the voltage source V GE2 , so that the IGBT device Q O is liable to be latched up. Accordingly, tens of ohms to hundreds of ohms of resistance is required for the gate resistor R G . It is generally known that when the resistance is increased too much, a switching time becomes long and power loss at the time of switching is increased, so that switching in a high frequency becomes difficult. In the conventional drive circuit, in order to avoid a latch-up as described above, the gate voltage in the normal operation is reduced by using a low voltage of the voltage source V GE1 . In this way, the amount of a normal collector current I C is kept small in the IGBT device Q O , and therefore latch-up does not occur even if the collector current I C is increased by the short-circuited load LD. However, an increase of the ON state resistance of the IGBT device Q O aggravates power losses in circuit elements other than the load LD. A drive circuit for a conventional IGBT device structured as has been described drives the IGBT device Q O with the relatively low gate voltage not to latch-up the IGRT device Q O . Therefore, such a drive circuit has the disadvantages that the ON state resistance of the IGBT devices Q O is high, and that significant power loss is caused in the IGBT device Q O . Specific components which may be known as such in MOSFETs are disclosed in e.g. German Patent Application DE-A 38 21 065. Patent Abstracts of Japan, Vol. 11, No. 113 (E-497)(2560) April 9, 1987 & JP-A 61 261 919 describe a drive circuit for a conductive modulation driving type MOSFET (BiFET), connected to a load to supply a current to the load, comprising: a forward gate bias power source for applying a forward gate bias voltage to the gate of the BIFET to drive the BIFET; a voltage divider connected between the the drain of the BIFET and the source of the BIFET, which has an intermediate point for providing a divided voltage; a current path disposed between the gate of the BIFET and a terminal having a predetermined voltage; a MOS transistor having a gate connected with the intermediate point of the voltage divider and a source and drain serially disposed in the said current path; an output resistor connected between the gate of the BIFET and the forward gate bias power source; and a switching element which is connected between the forward gate bias power source and the gate of the BIFET and switched on and off so as to switch the BIFET. It is the object of the present invention to provide a drive circuit for an IGBT device which inhibits a latch-up of the IGBT device and is capable of reducing undesired power losses. This object is solved in an advantageous manner by the features of claim 1. The present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: Fig. 1A is a diagram showing a symbol of an IGBT device; Fig. 1B is a diagram showing an equivalent circuit of the IGBT device; Fig. 2 is a circuit diagram of a conventional drive circuit of an IGBT device; Fig. 3 is a circuit diagram of a drive circuit of the IGBT device of an embodiment according to the present invention; Fig. 4 is a timing chart illustrating a waveform of the gate voltage at the normal operation of the circuit shown in Fig. 3; Fig. 5 is a timing chart illustrating waveforms of a collector-emitter voltage and a collector current at the normal operation of the circuit shown in Fig. 3; Fig. 6 is a timing chart illustrating a waveform of a gate voltage of the circuit shown in Fig. 3 in the case of a short-circuit of a load; Fig. 7 is a timing chart illustrating waveforms of a collector-emitter voltage and a collector current of the circuit shown in Fig. 3 in the case of the short-circuit of a load; Fig. 8 is a graph illustrating a relationship between the collector-emitter voltage and a current I R ; Fig. 9A is a sectional view of a VDMOS transistor. Fig. 9B is a plan view of the VDMOS transistor shown in Fig. 9A. An embodiment according to the present invention will be described in conjunction with the accompanying drawings. Fig. 3 is a circuit diagram of a drive circuit of an IGBT device according to an embodiment of the present invention. A switching unit SU is provided with voltage sources V GE1 , V GE2 . A negative potential terminal of the voltage source V GE1 and a positive potential terminal of the voltage source V GE2 are grounded. The positive potential terminal of the voltage source V GE1 is connected to an output point OUT via a output resistor R O and a switching element S1, and the negative potential terminal of the voltage source V GE2 is connected to the output point OUT via a switching element S2. In response to a control signal from the control system SY, the ON/OFF condition of the switching elements S1, S2 is designated. The output point OUT is connected to a gate of an IGBT device Q O via a gate resistor R G . The IGBT device Q O has its emitter grounded and its collector connected to a positive potential terminal of a voltage source V CC via a load LD and a current sensor CS. A negative potential terminal of the voltage source V CC is grounded. Further, capacities C GC and C GE exist between the gate and collector and between the gate and emitter as a parasitic capacity, respectively. An output of the current sensor CS is applied to a control system SY. When the current sensor CS senses an excess current, the control system SY executes its protecting operation causing the switching element S1 to be in the OFF condition and the switching element S2 to be in the ON condition so as to force the IGBT device Q O to be in the OFF condition. A junction of the output resistor R O and the switching element S1 is connected to a drain of a MOS transistor Q M via a resistor R L . The source of the MOS transistor Q M is connected to the anode of diode D 1 , and the cathode of the diode D 1 is connected to the ground potential. A current I L flows along the path in a direction shown in the Fig. 3. The diode D 1 serves to prevent the current I L from flowing reversely. The resistor R L serves to limit the value of the current I L . The collector of the IGBT device Q O is connected to the anode of a diode D 2 , and the cathode of the diode D 2 is connected to the cathode of a Zener diode D Z . The anode of the Zener diode D Z is grounded via resistors R 1 and R 2 serving as a potential dividers. A current I R flows along the path in a direction shown in the Fig. 3. The diode D 2 serves to prevent the current I R from flowing reversely and is not essential. A junction of the resistor R 1 and the resistor R 2 is connected to the gate of the MOS transistor Q M . A flywheel diode D W is incorporated between the collector and the emitter of the IGBT device Q O usually in anti-parallel connection thereto. The flywheel diode D W has its anode connected to the emitter of the IGBT device Q O and its cathode connected to the collector. As can be seen, a collector current I C flows from the collector to the emitter in the IGBT device Q O . Usually, the whole drive circuit is structured as a bridge circuit consisting of a plurality of arms. The drive circuit shown in Fig. 3 corresponds to one of those arms, and other arms have similar construction. Wiring between the arms is so provided that a flywheel diode D X in another arm AR is connected to the opposite ends of the load LD in anti-parallel connection thereto. An operation of the drive circuit will be described. Figs. 4 and 5 are timing charts illustrating waveforms of each element of the drive circuit shown in Fig. 3 in its normal operation. At at time t < t 1 , the switching element S1 of Fig. 3 is in the OFF condition and the switching element S2 is in the ON condition. In the normal operation, the switching elements S1 and S2 are alternately switched ON/OFF and, in response to this, the IGBT device Q O is switched at a predetermined frequency. The negative potential terminal of the voltage source V GE2 is connected to the gate of the IGBT device Q O via the switching element S2 and the gate resistor R G . Referring to Fig. 4, during this period, a negative voltage (-V GE2 ) is applied to cause the IGBT device Q O to turn off. Referring to Fig. 5, no collector current I C flows, and supply voltage V CC is applied as a collector-emitter voltage V CE . Further, since a very large supply voltage V CC is applied to a path composed of the diodes D 2 and D Z and the resistors R 1 and R 2 a current with a constant value I R flows. The currenL I R is involved in the protection operation described later but not involved in the normal drive operation. Therefore, the current I R is a reactive current for a period when the IGBT device Q O is in the OFF condition. Setting of a constant of each element for reducing the reactive current will be explained later. At a time t 1 , the switching element S1 is in the ON condition and the switching element S2 is in the OFF condition. The positive potential terminal of the voltage source V GE1 is conneted to the gate of the IGBT device Q O via the resistor R O , the switching element S1 and the gate resistor R G . As shown in Fig. 4, the gate voltage V G goes up and reaches OV at a time t 2 . Further, the gate voltage V G reaches a potential at which the IGBT device Q O becomes active, before time t 3 . In accordance with the rise of the gate voltage V G , the collector current I C begins to flow before a time t 3 . On the other hand, voltage V CE begins to go down since the IGBT device Q O turns from the OFF condition to the ON condition. In general, a phenomenon that the gate voltage is kept at a constant level appears in the initial stage of the ON condition in accordance with a known characteristic of the IGBT device. Thus, after the IGBT device Q 0 has turned on, the gate voltage V G is kept at a certain voltage until time t 4 , and thereafter it further goes up. At a time t 5 , the gate voltage V G reaches the voltage completely equal to that of the positive potential terminal of the voltage source V GE1 . The collector current I C is temporarily increased from the time t 3 to the time t 4 because of a reverse recovery current of the flywheel diode D X in the arm AR to reach a normal peak current I CPN . After that, it comes into a stationary state to reach a normal current value I CN determined depending upon the voltage of the voltage source V GE1 . In accordance with the ON transition of the IGBT device Q O , the voltage V CE goes down from the time t 3 to the time t 4 . After the time t 4 , it reaches a saturation voltage V CES since the IGBT device Q O reaches the complete ON condition. Figs. 6 and 7 are timing charts illustrating waveforms of each part of the drive circuit in the case of the short-circuit of the load. In contrast to the protection operation explained later, the-operation of the conventional drive circuit shown in Fig. 2 in the case of the short-circuit of the load will be described. This conventional drive circuit is equivalent to a circuit in which a protection circuit consisting of the diodes D 1 , D 2 and D Z , the resistors R 1 , R 2 and R L and the MOS transistor Q M is eliminated unlike the circuit of Fig. 3 and, therefore, has no protection function. Assume that the load LD is short-circuited before the time t 3 . Referring to Fig. 6, a waveform of the gate voltage V G in the case of the short-circuit of the load LD is identical with that of the gate voltage V G in the normal operation explained hereinbefore with reference to Fig. 4, in accordance with the ON/OFF condition of the switching elements S1 and S2 before the time t 5 . After the time t 5 , since the supply voltage V CC is directly applied to the collector because of the short-circuited load LD, the gate voltage V G transiently goes up by a voltage increase Δ V GE in proportion to the capacity ratio C GC /C GE until the time t 6 . After that, the gate voltage V G goes down to the voltage of the positive potential terminal of the voltage source V GE1 to be in a stationary state. Referring to Fig. 7, the collector current I C begins to flow before the time t 3 in accordance with the rise of the gate voltage V G , and thereafter it is increased. It is temporarily increased in accordance with the increased amount of the voltage Δ V GE and reaches the peak current I CPS in the case of the short-circuit of the load LD at the time t 6 . It comes to a stationary state thereafter to reach a constant current value I CS in the case of the short-circuit of the load LD. For a period from the time t 3 to the time t 4 where the IGBT device Q O is transferred to the complete ON condition, the collector-emitter voltage V CE temporarily goes down from the supply voltage V CC because a small collector current I C flows and the collector-emitter resistance of the IGBT device Q O is also small. After that, as the collector current I C is increased, the collector-emitter resistance of the IGBT device Q O becomes large. Further, because the load LD is short-circuited, the collector-emitter voltage V CE goes up to the supply voltage V CC and almost reaches the supply voltage V CC in the stationary state after the time t 6 . In the stationary state after the time t 6 , the collector-emitter voltage V CE is maintained almost at the supply voltage V CC , and hence the current value I CS in the case of the short-circuit of the load LD is much larger than the normal current value I CN mentioned above with reference to Fig. 5, approximately 6 to 7 times, for example, as large as the rated current flowing in the normal operation. In the above stated drive circuit without protection function, latch-up may be instantaneously caused in the IGBT device Q O because of a temporarily increased peak current I CPS in the case of the short-circuit of the load. Additionally, even if latch-up is not caused in the IGBT device Q O due to the peak current I CPS in the case of the short-circuit of the load LD, latch-up may be caused by a current increase due to a heat generation as explained below. As has been described, such a drive circuit is usually protected by the control system SY for controlling the switching elements S1, S2. Usually, however, it takes approximately 30 µsec for the current sensor CS to sense an excess current caused by an abnormal operation such as short-circuiting of the load LD and for the control system SY to cause the switching element S1 to take the OFF condition and the switching element S2 to take the ON condition so as to force the IGBT device Q O to turn off. When the load LD is short-circuited, the collector current I C having a current value I CS which is 6 to 7 times as large as the rated current flows even in the stationary state after the time t 6 , and therefore latch-up is caused by a heat generation in approximately 5 - 30 µsec. Consequently, the protection operation by the control system SY becomes insufficient. Now, the operation of the drive circuit shown in Fig. 3 having an effective protection function will be described. The operation before the time t 4 is the same as that of the above-mentioned circuit without protection function. After the time t 4 , the collector-emitter voltage V CE of the IGBT device Q O is increased. When the collector-emitter voltage V CE is larger than the sum of the Zener voltage V Z of the Zener diode D Z and a forward voltage V F of the diode D 2 , the current I R flows in accordance with a characteristic shown in Fig. 8. The V - I characteristic assumes a monotonic increase although it depends upon the characteristics of the diodes D 2 and D Z , and the current I R is increased in accordance with an increase in the voltage V CE . The gate voltage of the MOS transistor Q M is given by I R x R 2 . The collector-emitter voltage V CE when the gate voltage I R x R 2 is above the sum of a predetermined threshold voltage V TH with which the MOS transistor Q M turns on and the forward voltage V F of the diode D 1 is herein defined as a threshold voltage V CET . When the collector-emitter voltage V CE rises above the threshold voltage V CET , the MOS transistor Q M turns on causing the current I L to flow. As a result, the voltage at the output point OUT in the switching unit SU, that is, the gate voltage V G of the IGBT device Q O has the same value as that of a restricted gate voltage V GL given in accordance with the following equation (2): V GL = I L x (R L x r DS ) + V F where r DS is a drain-source resistance in the ON condition of the MOS transistor Q M . The peak current value of the collector current I C which flows when the collector-emitter voltage V CE reaches the threshold voltage V CET to start a restriction operation must be so small that latch-up may not be instantaneously caused in the IGBT device Q O . Specifically, a constant of each element must be set so that the collector-emitter voltage V CE reaches a threshold voltage V CET and the MOS transistor Q M turns on before the time t 6 when the peak current I CPS in the case of the short-circuit of the load flows and as early as possible after time t 4 . With such a setting, it is possible to prevent latch-up in the IGBT device Q O due to the peak current I CPS in the case of the short-circuit of the load LD. However, when the threshold voltage V CET is set excessively low so as to put forward the timing of starting the protection operation, the timing of starting the normal drive operation may be delayed or the protection operation mad be erroneously started due to noise or the like. Accordingly, the threshold voltage V CET must be set at a level where both the normal and protection operations can be smoothly performed. Setting of the timing of turning the MOS transistor Q M to the ON condition will be further explained later. Referring to Fig. 6, since the constant of each element of the equation (2) is so set that the restricted gate voltage V GL has a value sufficiently low, the collector current I C at the protection operation is restricted to a sufficiently small current value I CL even if a significantly large supply voltage V CC is applied as a collector-emitter voltage V CE in the stationary state after the time t 6 . A period from the beginning of flow of an excess current to an occurence of latch-up due to a generated heat can be extended to be approximately 50 µsec by making the current value I CL approximately twice as large as the rated current flowing in the normal operation. In this way, the control system SY performs the above-mentioned protection operation effectively, and latch-up due to any generated heat can be prevented. Now, setting of a constant of each element of the diodes D 2 and D Z and the resistors R 1 and R 2 for reducing a reactive current will be described. The Zener diode D Z is provided as means for dropping voltage. With the Zener diode D Z , voltage across the resistors R 1 and R 2 is sufficiently smaller than the collector-emitter voltage V CE and, therefore, the current I R is also sufficiently small even if the supply voltage V CC is applied as the collector-emitter voltage V CE of the IGBT device Q O in the case of short-circuiting of the load LD or at the time of the OFF condition of the IGBT device Q O . Further, while the load LD is not short-circuited and the IGBT device Q O is in the normal ON condition, the current I R is blocked by the Zener diode D Z and hence does not flow in the resistors R 1 and R 2 because the collector-emitter voltage V CE becomes a very small saturation voltage V CES as shown in Fig. 5. As has been described, a reactive current in the resistors R 1 and R 2 can be decreased and a power consumption can also be reduced by providing the Zener diode D Z as voltage dropping means. Without the Zener diode D Z , a sufficiently large resistance value of the resistors R 1 and R 2 can make a power consumption in these resistors small. However, in the integration of the drive circuit shown in Fig. 3, it is difficult to form a high resistance on a semiconductor substrate with high accuracy, and also a comparatively large packaging area is required. As previously mentioned, the gate voltage of the MOS transistor Q M depends upon a resistance value of the resistors R 1 and R 2 . When the resistance value of the resistors R 1 and R 2 varies widely, the timing where the gate voltage V G reaches a threshold voltage V TH , that is, the timing of starting the protection operation also varies widely. As a result, a drive circuit which does not start an expected protection operation may be manufactured as a finished product. Considering the situation described above, it is preferable to use the resistors R 1 and R 2 of relatively small resistance value which have a small packaging area and can be formed with high accuracy, by employing the Zener diode D Z having a Zener voltage V Z according to the value of the supply voltage V CC or connecting a plurality of Zener diodes in series so as to make the voltage drop in this part of the circuit sufficiently large. Now, setting of the timing of turning the MOS transistor Q M to the ON condition will be described. The threshold voltage V TH of the MOS transistor Q M can be arbitrarily set by controlling the concentration of impurity ions injected into a channel region in manufacturing processes, for example. Thus, the threshold voltage V CET with which the protection function becomes available can be set more freely. It is desirable that a transient period necessary for turning the MOS transistor Q M from its OFF condition to the ON condition, that is, a period from the application of the threshold voltage V TH to the gate of the MOS transistor Q M to the completion of turning on of the MOS transistor Q M is short so as to prevent latch-up due to the peak current I CFS in the case of the short-circuit of the load LD. However, when the transient time is too short, the MOS transistor Q M may erroneously turn on in response to the normal peak current I CPN as explained below. That is, as shown in Fig. 5, during the period from the time to to the time t 4 when the normal peak current I CPN flows, the collector-emitter voltage V CE has not yet sufficiently gone down and hence there is a high possibility that the diode D 2 and the Zener diode D Z are in the ON condition. Hence, there is also a possibility that a part of the reverse recovery current flows as a part of the current I R and the gate voltage of the MOS transistor Q M temporarily goes up, so that the MOS transistor Q M might erroneously turn on. The threshold voltage V TH is set at such level that such an erroneous operation can not be caused. Meanwhile, such erroneous operation can be avoided assuredly by selecting the construction of the MOS transistor Q M as described below. Fig. 9A is a sectional view showing an example of a construction of a MOS transistor. A MOS transistor which has a vertical double diffused structure (VDMOS) shown in Fig. 9A is applied as the MOS transistor Q M . A VDMOS transistor has the characteristics of a high voltage proof and a large current capacity. Further it has a structure which has a larger capacity of a gate electrode than the other structures have as described below. In Fig. 9A an n - type diffused region 2 which is connected to a drain electrode D is formed on an n + type diffused region 1. The regions 1, 2 function as a drain. A p type diffused region 3 is formed in the n - type diffused region 2 and an n + type diffused region 4 which functions as a source and is connected to a source electrode S is formed in the p type diffused region 3. In the surface of the p type diffused region 3 between the n + type diffused region and the n - type diffused region 2 a channel region 5 is formed. Above the channel region 5 and the n - type diffused region between a channel region 5 and another one a gate electrode 7 is formed on a gate oxide film 6. Fig. 9B is a diagram showing a plan view of a unit cell of the VDMOS transistor shown in Fig. 9A. As shown in Fig. 9B the channel region 5 has a plane structure of a rectange each side of which is L in length and the size of the gate electrode 7 is decided in accordance with the length L. Preferably, a MOS transistor having a large length L at the side of channel region 5 and a small resistance r DS between drain and source in its conductive state, that is, having a large current capacity and a gate electrode whose capacity is large is selected as the MOS transistor Q M . With such a MOS transistor Q M , a drive circuit can be obtained in which needless protection operation can be avoided because the gate voltage does not remarkably go up with regard to the instantaneous peak current I CPN and the gate voltage sufficiently goes up with regard to the peak current I CPS in the case of the short-circuit of the load LD where an excess current continues to flow for more than a certain time so that necessary protection operation can be started. The capacity of the gate electrode 7 can be increased by forming many unit cells shown in Fig. 9B and connecting them in a parallel manner. Further, it can be increased by decreasing the thickness of the gate oxide film 6. or adjusting thickness of the oxide film on the gate electrode 7 or the junction capacity of the pn junction. The gate capacity can be controlled in a similar manner with respect to other structures, i.e., a comb type or hexagon type VDMOS transistor. For example, a required period of time from the time t 1 shown in Fig. 7 to the time t 6 when the peak current I CPS flows is approximately 2 - 3 µsec. Further, a required period of time from the time t 1 shown in Fig. 5 to the time when the normal peak current I CPN flows is approximately 0,1 µsec in an IGBT device for a high frequency and approximatly 0,8 - 1,0 µsec in an IGBT device for a low frequency. Under the condition of such numerical values, the MOS transistor Q M can be turned on quite well without erroneous operation after the time when the normal peak current I CPN flows and until the time when the peak current I CPS in the case of the short-circuit of the load LD flows to prevent latch-up due to the peak current I CPS , by selecting the construction of the MOS transistor Q M , mainly controlling the gate capacity although the selection depends on whether the switching unit SU and load LD is for a high frequency or for a low frequency. That is, the MOS transistor having a small gate capacity is used when the IGBT device is for a high frequency and the MOS transistor having a large gate capacity is used when the IGBT device is for a low frequency. Thus, by inhibiting an excess collector current I C flowing in the IGBT device Q O in the case of the short-circuit of the load LD, the latch-up due to instantaneous voltage rise and generated heat can be prevented, while avoiding erroneous operation, whereby the IGBT device Q O can be protected from an excess current.

Claims: A drive circuit for driving an insulated gate bipolar transistor (QO) connected to a load (LD) to supply a current to the load (LD), comprising: a forward gate bias power source (VGE1) for applying a forward gate bias voltage to the gate of the insulated gate bipolar transistor (QO) to drive the insulated gate bipolar transistor (QO); voltage lowering means (D2, DZ) connected to the collector of the insulated gate bipolar transistor (QO) for lowering the voltage of the collector by a predetermined potential; a voltage divider (R1, R2) connected between the voltage lowering means (D2, DZ) and the emitter of the insulated gate bipolar transistor (QO), which has an intermediate point for providing a divided voltage; a current path disposed between the gate of the insulated gate bipolar transistor (QO) and a terminal having a predetermined voltage; a MOS transistor (QM) having a gate directly connected with the intermediate point of the voltage divider (R1, R2) and a source and drain serially disposed in the current path; an output resistor (RG) connected between the gate of the insulated gate bipolar transistor (QO) and the forward gate bias power source (VGE1); a switching element (S1) which is connected between the forward gate bias power source (VGE1) and the gate of the insulated gate bipolar transistor (QO) and switched on and off so as to switch the insulated gate bipolar transistor (QO) at a predetermined frequency; and a control system (SY) for detecting a load current flowing in the load (LD) to activate a reverse gate bias power source (VGE2) to apply a reverse gate bias voltage to the gate of the insulated gate bipolar transistor (Q0) with a delay time when the load current exceeds a predetermined level, wherein the MOS transistor (QM) has a relatively small gate capacity when the predetermined frequency is relatively large, and has a relatively large gate capacity when the predetermined frequency is relatively small.

Inventors: MAJUMDAR GOURAB C O MITSUBISHI, YOSHIDA SHIGEKAZU C O MITSUBIS, MAJUMDAR, GOURAB, C/O MITSUBISHI DENKI K.K., YOSHIDA, SHIGEKAZU, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H03K17
IPC codes: H03K17