Multiprocessor system with global data replication and two levels of address translation units

Abstract: In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses in addresses conventionally defined as real, the translation being performed by a first translation unit associated to and managed bythe processor which generates the global data, the first translation being followed by the translation of the real address in a physical address generally differing for each local memory and performed by a plurality of translation unis, each associated with a one of the local memories and managed by the processor associated with that local memory.

Description: The present invention relates to a multiprocessor system with global data replication and two levels of address translation units. Multiprocessor data processing systems are known where a plurality of processors, interconnected and communicating each to the other through a communication bus, operate in semi-independent or independent manner for concurrently executing a plurality of processes. Multiprocessors are used to obtain high performances. Multiprocessor systems may take several architectural forms which span from architectures defined in the literature as "tightly coupled" to the "loosely coupled" ones. Both architectures offer advantages and drawbacks. To overcome such drawbacks "tightly coupled" architectures have been proposed where certain resources, such as memory, are distributed among processors, but shared by the processors. A further improvement is achieved with the architecture described in the EP-A-88118058.2. where the concept of global data replication is introduced. In this architecture, having shared local resources, shared local memories in particular, each local memory contain a copy of the data which are used by more processors. These data are defined as global. Each processor may have access to the global data for reading them, without need of access to the system bus. In this kind of architecture the problem arises of assuring the consistency or identity of the global data in each of the local memories. Every time a global data is generated or modified in a local memory, it has to be replicated or modified in all other local memories with procedures and apparatuses of multiple or global writing which constitute a feature described in the already mentioned european patent application, as well as of italian patent application N. 22652A/88 filed Nov. 11 1988. The present invention has for its object the resolution of another problem which occurs with the replication of global data in each of the local memories of a multiprocessor system having shared local resources. The problem consists in the allocation of the global data in the physical space of each one of the local memories and it occurs by reason of the use, in the modern data processing systems, of the virtual memory concept. At program level, the instruction sequences and the set of information to be used are identified by logical addresses, which are completely independent of the memory capacity and the effective physical allocation in the memory of the several information items. Process execution by the several processing units is generally, if not always, performed by using logical addresses as references. A memory management unit, commonly identified as MMU or ATB (Address Translation Buffer) converts the logical addresses in physical addresses. In case the MMU can also signal the missing of the requested information from the memory or its invalid status. A component of the operating system or supervisor program, named MMM (Memory Management Module), manages, according to the needs, the MMU status and establishes the relation between logical addresses and physical addresses. The unit of memory location handled in this way is usually a page of four kilobytes. In other words the address conversion is performed on a portion of the address. The least significant portion of an address, which is named "offset" coincides in both the physical and logical addresses. In multiprocessor systems having local memories, each processor has its own MMU and manages its own local memory in an autonomous way. Depending on the processes/programs to be executed, it decides which information has to be located in its own local memory and at which physical locations. This autonomy is essential for an efficient use of the memory resources but, in the case the local resources are shared and the global data are replicated in each one of the local memories, it causes some problem in the allocation of the global data. Each processor which generates a set of global data in its own local memory and allocates them in a physical space of local memory, according to its own requirement, must find available a corresponding physical space in the local memory of the other processors. The physical space of the other memory must be defined by the same physical addresses where the replica of the generated global data may stored. The problem could be solved by the previous reservation in each of the local memories, of a predetermined physical space, having the same addresses in each of the memories, for the allocation of global data. However this approach is rigid and results in memory wasting. It requires the reservation to global data of a memory space sufficing for allocating the maximum predictable volume of global data, even if the effective need, depending on circumstances, is lesser. This problem is overcome by the european patent application EP-A-0092895 which describes a data processing network where global data are replicated in the local memory of each processor connected to the network, but the updating operations of global data are performed with the use of virtual addresses instead of physical addresses. In other words, a processor which intends to update a global data, references the same data, on an processors intercommunication channel, with a virtual address, rather than a physical address. The Memory Management Unit of each processor provides to convert, in independent way, the logical address in physical address, so that each processor can freely allocate the same global data at differing physical addresses. This solution involves a serious drawback: the several processors must reference the same global data with the same virtual address. In addition, the address translation unit MMU must be accessible both from the related processor and from the intercommunication channel, with obvious access conflicts which precludes the MMU from being used from within the processor, by way of example for access to a cache, when the same is used by the intercommunication channel. Further, in the frequent case of MMU integrate in a single chip with a microprocessor, the access to the MMU from outside the chip is not feasible. Other problems, such as discrimination at level of intercommunication channel among physical addresses and virtual addresses are not considered. The cited EP-A-0092895 mentions the possibility of removing the first of the above limitations by a two level address translation unit, so as to convert a global data virtual address, specific to each processor, in a virtual address common to all processors, without providing explanations on how this concept must or may be implemented. According to the invention the problem of the free allocation of global data, without introducing limitations and conflicts of any kind in use and arrangement of the MMU within the processor architecture, which MMU remains for exclusive use by the owning processor, is overcome by providing a multiprocessor system with two levels of address translation units and with a translation criterion which, in case of global data and only for global data includes two translation levels: a logical or virtual address is translated, with a first translation operation, in an address which is defined as "real" (only for the purpose of distinguishing it from a physical address). Thereafter the real address is converted in a physical address by a second translation operation. In case of local data the virtual address is directly converted in a physical address. The real and physical addresses have a format such that a portion of the address (one or more bits) enables to detect if an address is a real one or a pysical one and in the first instance causes the execution of the second operation (conversion from real to physical). These operation are performed by two pluralities of distinct MMUs as claimed in claim 1. A first plurality of MMUs, each one related to one processor of the system and exclusively addressed by the related processor is used to convert a logical address in a physical address or, in case of global data, in a real address. A second plurality of translation units, each one related to one of the local memories of the system and addressed by a real address generated by any one of the MMUs in the first plurality (hence by the related processor or by any other processor, through the system bus), is used to convert the real address in physical addresses each specific to the related local memory. In this way each global data is characterized by a logical address (which may be be different for each processor) to which a single real address is related and a plurality of physical addresses, generally differing from one another, each one for each of the system local memories. In this way each copy of the same global data may be physically allocated at physical addresses which differ in each local memory and the allocation may be performed in autonomous way by each of the system processors, as a function of the occupation status of its own local memory. Additionally, since the real address is a conventional information, differently from the logical addresses, which comprise a bit number sufficing to identify one information in a logical/virtual space much greater than the available physical memory space, the real address may comprise a bit number related to the effective size or capacity of the local memories, hence a smaller bit number. The second level address translation units may therefore be implemented with static random access (RAM) memories having a small capacity and full coverage of real addresses. In such memories a local memory physical address is stored and read out, which is related to each one of any possible real address, which is used as address for the static translation memory. The second level address translation unit is therefore and performs like a simple translation table. It does not require the constructive and management complications of the MMUs of conventional type. According to a further aspect of the invention the translation units which convert a real address in a physical address additionally operate as memory module selection units, the selection being predetermined as a function of the relation between physical address and real address. In other words, it is not required that a physical address be available to establish which of the memory modules must be selected and the selection may be performed with the knowledge of the real address. In this way the time required for translation from real to physical address, that is the read time of the second level address translation unit overlaps to the address decoding time for the selection of the module. It does not add further delay in the reading process and from a timing standpoint is completely "transparent". These and other features, and the advantages of the invention will appear more clearly from the following description of a preferred form of embodiment and from the enclosed drawings where: Figure 1 is a block diagram of a multiprocessor system having global data replication and two levels of address translation units. Figure 2 shows the format of the physical and real addresses used in the system of fig. 1. Figure 3 shows a preferred embodiment of local memory and related translation unit for converting real addresses to physical addresses in the system of Fig. 1. Figure 4 shows an alternative embodiment of address translation unit for the system of Fig. 1. Considering Fig. 1 the system comprises four central processing units (CPU0,CPU1,CPU2,CPU3) 1,2,3,4 connected each to the other through a system bus 5. The several CPU are timed by a timing unit 6. CPU0 comprises a microprocessor 7(MPU0), a memory address management unit 9 (MMU0), a local memory 8 (LM0), a local bus arbitrator 13 and an interface and arbitration unit 10. Microprocessor 7 communicates with local memory 8 and with the interface unit 10 by means of a local bus 11, arbitrated by arbitration unit 13. Microprocessor 7 may have access to the system bus, through interface unit 10, for receiving and sending information to/from the other CPUs, as well as for having access to the local memories of the other CPUs, or to peripheral control units, connected to the system bus, such as a controller 20 of disk units 21, a controller 22 of a display 23 with keyboard 24, a line controller 25, a controller 26 for a printer 27. The interface unit 10, together with corresponding units of the other CPUs, arbitrates access to the system bus by the several CPUs and manages the communication protocol on the system bus. Through interface unit 10, the CPUs other than CPU0 may have access to the local bus 11 of CPU0 and from there to the local memory 8. The address management unit 9, which in fig. 1 is shown as a unit distinct from processor 7, may be integral to processor 7. For instance this occurs if processor 7 consists in the integrated circuit microprocessor, marketed by the US firm Motorola with the code MC68030. In addition to the address management unit 9 (MMU0), the CPU0 comprises, as a part of the local memory 8, a second address translation unit or translation table 8A, for converting real addresses of global data to physical addresses. The other CPUs of the system have an architecture identical to the one of CPU0. Thus, for instance CPU3 comprises a local memory 14 (LM3), a processor 16 (MPU3), an address management unit 17 (MMU3), an interface unit 29, an arbitrator 15 for controlling access to a local bus 28 and a second translation unit 14B for converting real addresses to physical addresses. Figure 2 shows the format of the physical and real addresses used in the system of fig. 1 and generated by the address management units such as 9 and 17. A physical or real address comprises 32 bits (bits 0-31). The most significant bits, from 31 to 28, respectively designated as I (for Internal space, bit 31), PN (for Processor Number, bits 29,30) and G (for Global, bit 28) define the nature of the space addressed by bits 0-27. The following table summarizes, among the several possible configuration of addresses, those which are of interest for understanding the invention. In the table, the symbols 1 and 0 correspond to the logical level true, false and X expresses a condition of indifference. In other words the most significant bits of the address identify a physical resource of the system (CPU local memory, registers, I/O peripheral units,) and in case the local memory is selected they indicate (bit 28) if the address is related to a local data or a global data and therefore if the bits from 0 to 27 are to be considered a physical address or a real address. In case internal registers are selected, the least significant bits from 0 to 27 or a portion thereof, constitute a code for selection of one of a plurality of registers where information has to be read out or written. A typical example of internal register addressing occurs in the addressing of the memory management units 9,17 for loading them with information required to convert addresses from logical/virtual ones to physical ones. Likewise, in case of I/O peripheral units selection, the bits from 0 to 27 or a portion thereof, form a code for selection of one among a plurality of units. In case the internal or another local memory is selected, the bits from 0 to 27 enable to address up to 256 Mbytes of information, at byte level. The addressable memory space is conceptually composed of a plurality of pages, each page comprising 4K bytes, so that the bit field from 0 to 11 constitute an "offset", that is a byte address within a page, and the bit field from 12 to 27 constitute a page address. In the conversion of logical addresses to physical addresses, the criterion is usually followed by allocating information in the memory by pages. A logical page address is related to a physical page address and the "offset" is equal for both the physical and the logical addresses. The same criterion may be followed in the allocation of global data, so that a real address may be considered as comprising an "offset" which does not change in the address conversion, and a real page address, which requires conversion in a physical page address. By this assumption an address translation unit 8B of figure 1, for conversion of real addresses to physical addresses, and providing a full coverage of all possible physical addresses, may consist in a translation memory having a capacity of 64K entries (addressable locations). The capacity may be lesser if one of the following restrictions is imposed: A) Even if the addressable memory space of each local memory has a size of 256 Mbytes, the maximum effective capacity of the local memories is lesser and for instance 64 Mbytes. In this case the bits 26,27 of the physical or real page address are superfluous. B) Even if the effective memory capacity of each local memory is 256 Mbytes, the global data are assumed to require a maximum of 64 Mbytes corresponding to 16K pages, for their allocation. This number of real pages may be identified with a real page address of 14 bits only. In this case, at the extent real addresses are concerned, the bits 26,27 are superfluous. In both cases the conversion of a real page address to a physical page address may be performed by a memory having a capacity of 16 K entries. The second restriction is assumed as acceptable and true in the following description. Figure 3 shows a preferred embodiment of local memory 8 and address translation unit 8B for the system of the invention. The local memory 8, preferably arranged with a parallelism of 4 bytes, comprises a read only memory or ROM 30 having small capacity, for instance 4 Kbytes, for system initialization, and a plurality of read/write memory modules 31,32,33 up to a maximum of 8. In fig. 3 the modules are referenced as MOD1, MOD2, MOD8. Each module has preferably a capacity of 32 Mbytes, obtained with two banks of integrated circuits, each bank being formed by 32 (plus integrated circuits for parity bits or error detection/correction codes) integrated circuit components, each having a capacity of 4 Mbit. The local memory 8 further comprises interface registers for latching commands (register 34) addresses (register 35) data in input to memory (register 36) and data in output from memory (register 37). A module and bank selection logic, essentially consisting in a static memory 38 and a decoder 39 is further included in the local memory. A memory and timing logic 40 receives as inputs the commands (read/write) latched in register 34, the most significant address bits, latched in register 35, and provides to generate control and selection signals S1,S2,....SN, with the due timing and as a function of the input information. The address translation unit 8B consists in a bank of 5 integrated circuits SRAM, each having a capacity of 16Kx4bit (for instance of the type marketed by the Japanese firm HITACHI with the code HM6788H) so as to obtain a parallelism of 20 bits. The "offset" bits AD 2-11, latched in register 35 are sent, through a lead set 41, to ROM40 and to the several modules 31,32,33. The page address bits AD12-23 are distributed, through a lead set 42 and through a set 43 of tristate gates, to ROM 30 and to the several modules 31,32,33. The bits AD12-25 are further input to the address inputs of SRAM memory 8B. For each addressed entry, memory 8B outputs a 12 bit code which constitutes a least significant portion of a physical page address corresponding to the real address expressed by the input address. This code is broadcast to the several modules 31,32,33 through a set of tristate gates 44. In addition to such code, for each addressed entry, the translation memory 8B outputs a 4 bit selection code, which is sent, through leads 45, to decoder 39. The four most significant bits AD24-27 of page address, in output from register 35, are used as address for memory 38, which outputs a selection code as input to decoder 39. The control logic 40, depending on the logical level of bits 28-31 and other address bits, as well as on the contents of register 34, generates timed signals for memory activation and control signals S0....SN. For instance a signal S0, mutually exclusive with the signals for bank and module selection SEL1...SEL8, selects ROM 30. If the bits 31-28 have the configuration 1000, the address latched in register 35 is a physical address: therefore a signal S2 is generated which enables gates 43 and memory 38 respectively to the transfer of the physical page address and the module selection code. If the bits 31-28 have the configuration 1001, the address latched in register 35 is a real address of a global data: therefore a signal S1 is generated, which enables memory 8B to output a physical address corresponding to the real one as well as a corresponding module selection code. The data to be written in the memory and latched in register 36, are distributed, through channel 46 to all the modules and are written in the selected one. Channel 46 forms a collector for receiving from a selected module, the data read out from memory, which are loaded in register 37. Figure 3 does not show, for simplification purpose, memory write circuits for the memories 8B and 38 which are basically known. For example US Patent 4,592,011 describes the writing circuits for a memory such as 38 and a related memory mapping procedure, used at system initialization. The process for generation of real, physical addresses and the loading of translation SRAM 8B may be summarized as follows. At system initialization each CPU, such as CPU0, activates a procedure for "bootstrapping" the operating system, in a well known manner. Processor 7 controls a read operation at a fixed address of a register space, which identifies ROM 30 as destination and by subsequent incrementation of an internal register (instruction counter) it fetches and executes a sequence of instructions. These instructions provide for the detection of the local memory capacity, the loading of the module selection logic, the activation of a peripheral unit controller (for instance the disk unit controller 20 of fig. 1) and the reading from the disk unit and the storing in local memory, at predetermined physical addresses of a portion of the operating system, or supervisor, or kernel, according to the several current expressions. During this process the status of MMU9 and translation table 8B is irrelevant, because they are not used. The same procedure is also followed by the other CPUs of the system, in autonomous way. At this point processor 7 has in its own local memory and as a kernel portion, a memory managemenet module or allocator. This program identifies some predetermined and unmodifiable memory spaces, defined by physical addresses, where to allocate tables which describe the status of the local memory. At this point the supervisor identifies the status of the system and the presence of processes or user programs waiting for execution. The information related to the system status is information used by all the CPUs and may be changed in the time, particularly due to the supervisor program or in the course of user processes execution. This information is threfore a set of global data. The allocator provides for identifying a free space in the local memory 8 where to load such data, and establishes a correspondence between physical addresses of such space, real addresses which it decides to assign to such data and logical addresses of the same. The correspondence among addresses is loaded in tables which describe the local memory status, together with additional information, such as protection bit, valid/invalid table bits and so on. Then it proceeds to load the translation memory 8B with the physical addresses corresponding to real addresses, by addressing memory 8B with real addresses and writing therein the physical addresses, which are forwarded as data. More precisely, in the case, as the one shown in Fig. 3 that the translation memory performs the additional function of module and bank selection, the most significant bits of the physical address are substituted with a module/bank selection code, determined as a function of the local memory configuration. It must be noted that so far, the global data have not yet been stored in the local memory, even if it has been planned where to allocate them. At this point, processor 7, which for instance is the first to decide global data allocation in local memory, under supervisor control, notifies to the other CPUs of the system, the need to reserve a certain memory space for allocation of global data, identified by predetermined real addresses and related logical addresses. This notification process may be performed with direct interprocessor communication or with indirect communication through "mailbox", depending on the system features. Once this notification has been received, each CPU reserves, under control of its own allocator, the physical local memory space where to load the global data and defines its own correlation table between real addresses and physical addresses. It provides further to load the translation memory of its own local memory with the physical addresses so assigned (and related selection codes). Once this operation has been performed it notifies to the requesting CPU, in this case CPU0, that the memory space has been reserved and that the loading operation may be performed. CPU0, once received confirmation by all other CPUs that the memory space has been reserved, (note: each CPU completely ignores which are the physical addresses of the memory space, used by other processors), may then start the processes which generate global data and write such global data in its own local memory and at the same time in the local memory of the other processors, with write commands which are defined as global write, broadcast to the other system processor through the system bus, as described in the already mentioned patent applications. These global write commands, use the real address rather than the physical address, as addressing information. Therefore it may be said that the processor which generates the global write command, uses its own MMU as a first level translation unit for generating real addresses, and then uses each one of the translation memories, each related to one of the several local memories and preset by the several processors as a second level translation unit for locally converting the same real address in a plurality of physical addresses. It is clear that this operation of memory space allocation to global data may be performed and repeated at any time of the system operation, not only at initialization. It is performed every time it is required to allocate new memory space to new global data for use by the supervisor or global data needed by user programs, which for a greater efficiency are concurrently executed by more processors. It is clear that Fig. 3 shows a preferred form of embodiment for a local memory having a second level of address translation unit, additional to the first level translation unit coupled to each processor. Several changes can be made to this embodiment. For instance tristate gates 43 and 44 of figure 3 may be substituted with a multiplexer. In addition the direct coupling 45 between output of memory 8B and output of memory 38 implies that such memories have a tristate output enabled only if such memories are selected for operation. If this is not the case, a multiplexer has to be provided, in order to input to decoder 39 either the signals present on leads 45 or output from memory 38, in a mutually exclusive way. As an alternative, the multiplexing function may be performed by decoder 39 which may receive the two sets of signals plus a control signal from unit 40 at different inputs. It is further clear that, even if providing advantages in terms of operative speed, it is not required that the translation memory 8B performs the function of selection code generation. Figure 4 shows an interconnection of translation memory 8B with a memory module selection unit where the module selection function is always and exclusively performed by the selection unit. In figure 4, unit 88 receives the real address bits AD12-24 and outputs the corresponding physical address bits PAD12-27. Bits PAD12-23 are input to a multiplexer 47 which receives address bits AD12-23 (in output from register 35) at a second input set. Multiplexer 47 is controlled by a signal S4 to enable the transfer of the one or the other input information depending on whether the address stored in register 35 is a real or physical address. The bits PAD24-27 in output from memory 8B are input to a mutliplexer 48 which receives bits AD24-27 (in output from register 35) at a second set of inputs. Multiplexer 48 too is controlled by signal S4. The outputs of mutliplexer 48 are connected to the input of static RAM 38. It is clear that in this case the conversion of real addresses in physical addresses (memory 8B) and the generation of a module selection code, based on a physical address, are performed in time sequence or in cascade. If no time constraints preclude such arrangement it could result advantageous because it simplifies the generation process of the physical addresses to be loaded in memory 8B and renders it independent of the local memory configuration and of the module selection process.

Claims: Multiprocessor system with global data replication and two levels of address translation wherein each of a plurality of processing units (1,2,3,4) has a processor (7,16) a local memory (8,14) an interface unit (10,29) and a local bus (11,28) associated therewith, each processor (7,16) has access to the local memory (8,14) associated therewith through its associated local bus (11,28) and each processor (7,16) has access to the local memory (8,14) of another processing unit (1,2,3,4) through its associated local bus (11,28) its associated interface unit (10,29) a system bus (5), the interface unit (10,29) and the local bus (11,28) of said another processing unit (1,2,3,4), where further global data used by more than one processor (7,16) are replicated and stored in a plurality of said local memories (8,14) characterised by that said system comprises: a first address translation unit (9,17) in each one of said processing units (1,2,3,4) coupled to the processor (7,16) and to the local bus (11,28) associated therewith, for receiving from said associated processor a logical address generated therein and for converting said logical address either into a real address related to global data, or into a physical address related to data which is not global, said real address containing a bit code which identifies it as real, said real or physical address being output on said associated local bus (11,28), a second address translation unit (8B,14B) in each one of said processing units (1,2,3,4) coupled to the local memory (8,16) and to the local bus (11,28) associated therewith for converting a real address received either from the associated first translation unit (9,17) through said associated local bus (11,28) or from any other first translation unit (9,17) through said associated local bus, said system bus (5) and the local bus (11,28) associated to said other translation unit, into a physical address input as address to said local memory coupled thereto, and logical means in each said address translation unit (40) for detecting said bit code in said real address and for activating said second translation unit only upon detection of said real address. System as in claim 1, comprising means (5,10,29) for transferring a real address generated by any one of said first translation units (9,17), in case of a write operation, to all said second translation units (8B,14B9), whereby said real address generated by the first translation unit associated to one processing unit (1,2,3,4) is sent through said system bus (5) to each one of the other processing units (1,2,3,4) and converted by said second translation units each associated to one of said processing units, into a plurality of physical addresses, each one for addressing one of said local memories. System as in claim 1 where said second translation units (8B,14B) are static random access memories. System as in claim 3 where at least one of said local memories (8,14) comprises a plurality of modules (31,32,33) individually selectable for a read/write operation by a selection code obtained from a field of a physical address and at least the second translation unit (8B,14B) associated to said one local memory translates said received real address into a physical address and at the same time generates a module selection code.

Inventors: CASAMATTA ANGELO, MANTELLINA CALOGERO, ZANZOTTERA DANIELE, CASAMATTA, ANGELO, MANTELLINA, CALOGERO, ZANZOTTERA, DANIELE
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS ITALIA S.P.A.
Application year: 1990
Main classification: G06F12
IPC codes: G06F15, G06F12