Semidonductor device and method of manufacturing the same

Abstract: At least part of a low impurity concentration col­ lector region (4, 6) which lies between the emitter (30) and collector regions (4, 6) of a bipolar transistor in a Bi-CMOS device is formed to have a low impurity concentration. Therefore, a high emitter-collector withstanding voltage can be obtained. Further, at least part of the low impurity concentration collector region (4, 6) which lies between the base region (24) and an opposite conductivity type region (5) is formed to have a high impurity concentration. Therefore, the punch-­ through withstanding voltage of a parasitic transistor formed of the base (24), collector (6) and, opposite conductivity type region (5) can be enhanced, and, at the same time, the collector resistance can be reduced.

Description: This invention relates to a semiconductor device having a bipolar transistor and a method for manufacturing the same, and more particularly to a Bi-CMOS device and a method of manufacturing the same. Fig. 1 is a cross sectional view showing the construction of a Bi-CMOS device having a bipolar transistor and CMOS transistors disposed therein disclosed in Japanese Patent Application No. 63-170683 filed by the Applicant of this invention. In Fig. 1, reference numeral 1 denotes a P-type substrate, 2 an N + -buried layer, 3 a P + -buried layer, 4 an N-type epitaxial layer, 5 a P-well region, 6 an N-well region, 7 a field oxide film, 9 an N + -diffused layer, 13 a polysilicon layer, 14 a gate oxide film, 15 an nMOS source region having a low impurity concentration, 16 an nMOS drain region having a low impurity concentration, 17 a pMOS source region, 18 a pMOS drain region, 19 an external base region, 20 a CVD-SiO 2 film, 21 an nMOS source region having a high impurity concentration, 22 an nMOS drain region having a high impurity concentration, 24 a base region, 28 a polysilicon layer serving as an emitter electrode, 30 an emitter region, 32 an interlayer film, and 36, 37 and 38 aluminum wirings. The pMOS transistor, nMOS transistor and bipolar transistor are formed on the same P-type substrate 1. In the Bi-CMOS with the above construction, a drawback that the withstanding voltage between the emitter 30 and the collector 4 may be lowered occurs when the impurity concentration of the N-type epitaxial layer 4 acting as a collector of the bipolar transistor is high. In order to solve this drawback, it is considered to set the impurity concentration of the N-type epitaxial layer 4 lower than a predetermined impurity concentration. Fig. 2 shows the relation between the impurity concentration of the collector and the collector-emitter withstanding voltage (open base). As shown in Fig. 2, as the impurity concentration Nc of the collector becomes lower, the collector-emitter voltage BV CEO becomes higher. However, when the impurity concentration of the N-type epitaxial layer 4 of the bipolar transistor is lowered, current flows via a PNP parasitic transistor formed of the P-well region 5, N-type epitaxial layer 4 and base regions 24 and 19, causing a punch-through phenomenon. When the impurity concentration of the N-type epitaxial layer 4 is lowered, the resistance of the N-type epitaxial layer 4 becomes larger, making the collector resistance larger. GB-A-1 280 022 shows the features of the preamble of claim 1. EP-A-0 219 641 shows a MOSFET and a bipolar transistor on the same substrate. A buried N well (14) formed over the buried collector area (3) has a uniform impurity concentration. JP-A-63 240 058 shows implanting boron ions, and lowering the impurity concentration in an N-well used for forming a bipolar transistor. US-A-4 267 557 shows a protective diode with a uniform impurity concentration collector region under the base region. An object of this invention is to provide a semiconductor device in which the withstanding voltage preventing the punch-through phenomenon in a parasitic transistor can be set high and the collector resistance thereof can be set low while the emitter-collector withstanding voltage can be held at a desired value, and a method for manufacturing the same. According to the invention, there is provided a semiconductor device as set out in claim 1. A method of manufacturing a semiconductor device according to claim 1 is defined in claim 4. In this invention, the impurity concentration of at least part of the low impurity concentration collector region which lies between the emitter region and the collector region is set low so that a high emitter-collector withstanding voltage can be obtained. Further, the impurity concentration of at least part of the low impurity concentration collector region which lies between the base region and the opposite conductivity type region is set high so that a withstanding voltage preventing the punch-through phenomenon in the parasitic transistor formed of the base region, collector region and opposite conductivity type region can be enhanced and the collector resistance can be lowered. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross sectional view showing the construction of the conventional Bi-CMOS device; Fig. 2 shows the relation between the impurity concentration of the collector and the collector-emitter withstanding voltage in a bipolar transistor of Fig. 1; Figs. 3A to 3G are cross sectional views for illustrating the process of manufacturing a first embodiment of a semiconductor device of this invention; Fig. 4 is a cross sectional view showing the construction of an embodiment not covered by the invention; and Fig. 5 is a cross sectional view, showing the construction of an embodiment not covered by the invention. There will now be described embodiments of the present invention with reference to the accompanying drawings. Figs. 3A to 3G are cross sectional views for illustrating the steps of manufacturing a first embodiment of a semiconductor device of this invention. As shown in Fig. 3A, N + -buried layers 2 are selectively formed in those portions of the surface area of a P-type semiconductor substrate 1 of monocrystalline silicon on which a bipolar transistor and a pMOS transistor are formed by using the lithographic method and ion-implantation technique. For example, arsenic (As) or antimony (Sb) is used in the ion-implantation process. The N + -buried layer 2 is used as a high impurity concentration collector region of the bipolar transistor. Then, boron (B) is ion-implanted into those portions of the surface area of the substrate 1 on which nMOS transistors are formed by using the lithographic method and ion-implantation technique to form P + -buried layers 3. The ion-implantation condition for boron (B) is that the acceleration energy is 100 KeV and the dose amount is 1.5 × 10 13 cm -2 , for example. After this, as shown in Fig. 3B, an N-type epitaxial layer 4 containing phosphorus (P) of approx. 1 × 10 16 cm -3 , for example, is formed on the semiconductor substrate 1 by using the epitaxial growth method. At this time, the growth temperature is set at 1130°C and the thickness of the epitaxial layer is approx. 1.2 µm. Next, as shown in Fig. 3C, a mask (not shown) is formed by using the lithographic method and then boron (B) is ion-implanted into the nMOS forming area of the N-type epitaxial layer 4 with the acceleration energy of 100 KeV and the dose amount of 6 × 10 12 cm -2 , for example, so as to selectively form P-well regions 5. After this, the mask is removed. Then, an ion-implantation mask (not shown) is formed on an area other than the pMOS forming area and emitter forming area by the lithographic method, and phosphorus (P) is then ion-implanted into the N-type epitaxial layer 4 with the acceleration energy of 160 KeV and the dose amount of 5 × 10 12 cm -2 , for example, so as to selectively form N-well regions 6 in the bipolar transistor forming areas. Next, as shown in Fig. 3D, an SiN film (not shown) is formed and a preset ion-implantation mask (not shown) is formed on the SiN film as the preparation process for forming field oxide films 7. In order to form field lu inversion preventing ion-implanted regions 8 in the formation areas of the field oxide films 7 of the MOS transistors, arsenic (As) or antimony (Sb) is ion-implanted into the p-channel MOS transistor area, for example, and boron (B) is ion-implanted into the n-channel MOS transistor area, for example. Next, the field oxide films 7 for isolating the MOS transistors from each other and from the bipolar transistor are formed by the selective oxidation method. After this, a mask is formed on an area other than the formation area of an N + -type diffused region 9 in the N-well region 6 and the N + -type diffused region 9 is formed in connection with the N + -buried layer 2 by using the ion-implantation technique. Arsenic (As) or antimony (Sb) is used in the ion-implantation process, for example. Next, a dummy gate oxide film 10 is formed to a thickness of approx. 15nm (150 Å) on the entire surface of the resultant structure by a thermal oxidation method. Then, channel ion-implantation regions 11 and 12 are formed in the P-well region 5 and N-well region 6, respectively. The channel ion-implantation regions 11 and 12 are formed to properly match the threshold voltages of the N-channel MOS transistor and P-channel MOS transistor and prevent occurrence of the punch-through phenomenon. The channel ion-implantation region 11 of the N-channel MOS transistor is formed by ion-implanting boron (B) ions with the acceleration energy of 20 KeV and the dose amount of 4 × 10 12 cm -2 , for example. The channel ion-implantation region 12 of the P-channel MOS transistor is formed by effecting two ion-implantation processes including the process of ion-implanting boron (B) ions with the acceleration energy of 20 KeV and the dose amount of 3 × 10 12 cm -2 and the process of ion-implanting phosphorus (P) ions with the acceleration energy of 240 KeV and the dose amount of 2 × 10 12 cm -2 . Next, as shown in Fig. 3E, the dummy gate oxide film 10 is completely removed from the entire surface and then a gate oxide film is formed to a thickness of approx. 15nm (150 Å) on the entire surface by using the thermal oxidation method. In order to form gate electrodes 14, a polysilicon layer is deposited to a predetermined thickness on the gate oxide film by the chemical vapor deposition (CVD) method. Then, impurity is doped into the polysilicon layer by a phosphorus (P) diffusing method to lower the resistance of the polysilicon layer. The gate oxide film and the polysilicon layer are patterned by using the lithographic process so as to form gate insulation films 13 and the gate electrodes 14 of the MOS transistors on the P-well region 5 and N-well region 6. After a mask is formed on an area other than the P-well region 5, and then phosphorus (P) ions are ion-implanted into the P-well region 5 to form an N - -type source region 15 and drain region 16. At this time, the field oxide film 7 and gate electrodes 14 are served as masks. The ion-implantation process is effected with the acceleration energy of, for example, 60 KeV and the dose amount of 4 × 10 13 cm -2 , for example. Likewise, a mask is formed on an area other than the N-well region 6 and then BF 2 ions are ion-implanted into the N-well region 6 to form a P + -type source region 17 and drain region 18. The ion-implantation process is effected with the acceleration energy of, for example, 50 KeV and the dose amount of 5 × 10 15 cm -2 , for example. By the ion-implantation of BF 2 ions, an external base region 19 in the formation area of the bipolar transistor is also formed. Next, as shown in Fig. 3F, a CVD-SiO 2 film (not shown) is deposited to a thickness of 200 nm (2000 Å) on the entire surface by the CVD method and then the CVD-SiO 2 film is etched by an anisotropic etching method such as a reactive ion etching (RIE) method to leave SiO 2 films 20 only on the side portions of the gate electrodes 14. After this, a mask is formed on an area other than the P-well region 5 and then As ions are ion-implanted into the surface area with the acceleration energy of 50 KeV and the dose amount of 5 × 10 15 cm -2 so as to form an N + -type source region 21 and N + -type drain region 22 in the P well region 5. As a result, an N-channel MOS transistor of so-called lightly doped drain (LDD) structure is formed. Then, an oxidation process is effected at a temperature of 900°C in an O 2 atmosphere for 30 minutes to form an oxide film 23 on the entire surface. A mask is formed by the lithographic method and then a P-type base region 24 of the bipolar transistor is formed. The base region 24 is formed by ion-implanting BF 2 ions with the acceleration energy of, for example, 30 KeV and the dose amount of 5 × 10 13 cm -2 , for example. After this, the mask is removed. Next, as shown in Fig. 3G, a CVD-SiO 2 film 25 is deposited to a thickness of 200 nm (2000 Å) on the entire surface by the CVD method. Then, a contact hole 26 which reaches the surface of the base region 24 is formed in the CVD-SiO 2 film 25 by the RIE method, and a contact hole 27 which reaches the surface of the N + -type drain region 22 of the N-channel MOS transistor is also formed in the CVD-SiO 2 film 25. After this, a polysilicon layer is deposited to a thickness of 200 nm (2000 Å) on the entire surface. Then, it is patterned by using the lithographic method and RIE method so as to leave polysilicon layers 28, 29 and 31. Next, a mask (not shown) such as a photoresist is formed to cover part of the polysilicon layer 29, and As ions are ion-implanted into the polysilicon layers 28 and 29 with the acceleration energy of 50 KeV and the dose amount of 5 × 10 15 cm -2 . Then, the mask is removed. By the ion-implantation process, an N-type emitter region 30 is formed in part of the base region 24, and at the same time, the electrical resistance of the polysilicon layer 28 is lowered to form the emitter electrode of the bipolar transistor. Further, the resistance of a portion of the polysilicon layer 29 other than a polysilicon layer 29a is lowered by the above ion-implantation process to form a drain wiring of the N-channel MOS transistor. That portion of the polysilicon layer whose resistance is not lowered is used as the high-resistance element 29a. The two N-well regions 6 formed in contact with the P-type base region 24 and the N-type epitaxial layer 4 constitute a low impurity concentration collector region. Next, an interlayer film 32 formed of a CVD-SiO 2 film and a BPSG (silicon glass containing B and P) film which is an insulation film is deposited on the entire surface to make the surface flat. A contact hole 33 which reaches the polysilicon layer 28 serving as the emitter electrode and a contact hole 34 which reaches the polysilicon layer 29 serving as the drain wiring is formed in the interlayer film 32 by using the RIE method. Further, a contact hole 35 which reaches the source region 17 of the P-channel MOS transistor is formed in the interlayer film 32 and CVD-SiO 2 film 25. Then, aluminum for wirings is deposited on the entire surface by a vapor deposition method or the like and it is patterned by the photolithographic method and RIE method to form aluminum wirings 36, 37 and 38. In this way, the semiconductor device of the first embodiment of this invention is completed. According to the first embodiment, since the N-well region 6 having a relatively high impurity concentration is formed in the low impurity concentration collector region between the base region 24 and the P-well region 5, occurrence of the punch-through phenomenon in the bipolar transistor formed of the base region 24, N-well region 6 serving as the relatively high impurity concentration collector region and the P-well region 5 can be prevented. Further, since the impurity concentration of the N-type epitaxial layer (collector region) 4 formed below the emitter region 30 is lower than that of the N-well region 6, the emitter-collector withstanding voltage can be kept at a proper value. In addition, since the N-well region 6 having an impurity concentration higher than that of the N-type epitaxial layer 4 is formed between the base region 24 and the N + -type diffused layer 9, the collector resistance can be reduced. Further, in the above method of manufacturing the semiconductor device, the step of forming the N-well region 6 of the pMOS transistor and the step of forming the N-well region 6 in the N-type epitaxial layer 4 of the bipolar transistor can be effected at the same time. Therefore, the number of steps is not increased in comparison with the conventional manufacturing method. Further, in the first embodiment, the P-type base region 24 is formed in contact with the collector of the npn junction transistor, but the same effect can be attained in a case where an N-type base region is formed in contact with the collector of a pnp junction transistor. Fig. 4 is a cross sectional view showing an embodiment not covered by the invention. In Fig. 4, portions which are the same as those in the first embodiment are denoted by the same reference numerals and the explanation thereof is omitted. As shown in Fig. 4, in the embodiment, an N-well region 106 of high impurity concentration which is a collector of the bipolar transistor is formed so as not to be in contact with a base region 24. That is, all the portion lying under the P-type base region 24 of the bipolar transistor is formed of an N-type epitaxial layer 4 of low impurity concentration, and the N-well region is formed separately from the base region 24. With this embodiment, the junction capacitance of the N-type epitaxial layer 4 serving as the collector can be reduced in comparison with the case of the first embodiment, and, at the same time, occurrence of the punch-through phenomenon of a parasitic transistor can be prevented and the collector resistance can be reduced as in the first embodiment. Fig. 5 is a cross sectional view showing the construction of an embodiment not covered by the invention. In this embodiment, a field N - -region 40 is formed in the surface area of an N-type epitaxial layer 4 of the bipolar transistor. The method of forming the semiconductor device of this embodiment is explained with reference to Figs. 3 and 5. In this embodiment, after the steps of Figs. 3A and 3B are effected, a step of Fig. 3C in which an N-well region 6 is formed in a bipolar transistor forming area is not effected. When a step of Fig. 3D in which a field inversion preventing ion-implanted region 8 is formed in a P-channel MOS transistor area by the ion-implantation technique is effected, ions are simultaneously implanted in those portions of the N-type epitaxial layer 4 other than the base forming area 24 of the bipolar transistor forming area, N + -diffused layer 9 and P-well region 5, thus forming the field N - -region 40. After this, the mask is removed and then the same steps as those of the first embodiment are effected. With this embodiment, the junction capacitance of the collector can also be reduced. Further, the withstanding voltage against the punch-through of the parasitic transistor can be raised and the collector resistance can be reduced. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device comprising: a semiconductor substrate (1); an emitter region (30) of a first conductivity type formed on said semiconductor substrate (1); a base region (24) of a second conductivity type formed to surround said emitter region (30); a low impurity concentration collector region (4, 6) of the first conductivity type formed to surround said base region (24); a high impurity concentration collector region (2) of the first conductivity type formed under said low impurity concentration collector region (4, 6); and a well region (5) of the second conductivity type formed in contact with and being laterally adjacent to said low impurity concentration collector region (4, 6); wherein a first part (4) of said low impurity concentration collector region (4, 6) which lies between said base region (24) and said high impurity concentration collector region (2) and directly below said emitter region (30) is formed to have an impurity concentration lower than that of a second part (6) of said low impurity concentration collector region (4, 6) which lies between said base region (24) and said high impurity concentration collector region (2) and between said base region (24) and said well region (5) of the second conductivity type, characterized in that the second part extends beneath and is in contact with the bottom of the base region (24) and extends from the first part to the well region (5). A semiconductor device according to claim 1, characterized by further comprising a first conductivity type region (6) formed on said semiconductor substrate (1); source (17) and drain (18) regions of the second conductivity type separately formed on said first conductivity type region; and an electrode (13) formed on said first conductivity type region (6) which lies between said source (17) and drain (18) regions. A semiconductor device according to claim 1, characterized in that the impurity concentration of said first part (4) of said low impurity concentration collector region (4, 6) which lies directly below said emitter region (30) is lower than that of a portion (6) of said low impurity concentration collector region (4, 6) which does not lie directly below said emitter region (30). A Method of manufacturing a semiconductor device according to claim 1, comprising the steps of: forming at least two first buried layers (2) having a high impurity concentration on selected surfaces in a second MOS transistor-forming region and a bipolar transistor-forming region of a semiconductor substrate (1), respectively, and forming a second buried layer (3) having a high impurity concentration in a first MOS transistor-forming region of said semiconductor substrate (1); forming an epitaxial layer (4) of a first conductivity type on the entire surfaces of said semiconductor substrate (1); forming a well region (5) of a second conductivity type in said first MOS transistor-forming region, said well region (5) having an impurity concentration higher than that of said epitaxial layer (4); forming at least two ion-injected regions (8, 8) of said first conductivity type in a first portion of said epitaxial layer (4) which is located above said second MOS transistor-forming region and a second portion of said epitaxial layer (4) which is located above said bipolar transistor-forming region and excluding a portion located below a base-forming portion, respectively, said ion-injected regions preventing a field region from being inverted; forming device-isolation insulating film (7) on selected surfaces of the resultant structure; forming a first MOS transistor in said well region (5) of the second conductivity type formed in said first MOS transistor-forming region, and a second MOS transistor in a well region (6) of the first conductivity type formed in said second MOS transistor-forming region; and forming a bipolar transistor in said epitaxial layer (4) and a well region (6) of the first conductivity type formed in said bipolar transistor-forming region. A method according to claim 4, characterized in that said step of forming the well region (6) of the first conductivity type in that portion of said epitaxial layer (4) which is located above said bipolar transistor-forming region and other than that portion located below an emitter-forming portion is to form the well region (6) of the first conductivity type, in contact with a base region (24) of the bipolar transistor-forming region. A method according to claim 4, characterized by further comprising the step of forming ion-injected regions (8) for preventing field inversion, in those portions of said first and second MOS transistor-forming regions in which said device-isolation insulating films (7) is to be formed.

Inventors: MOMOSE HIROSHI, UNNO YUKARI, MOMOSE, HIROSHI, UNNO, YUKARI, MOMOSE, HIROSHI, C/O INTELLECTUAL PROPERTY DIV., UNNO, YUKARI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: H01L27
IPC codes: H01L29, H01L21, H01L27