Pipeline processor and pipeline processing method for microprocessor

Abstract: A pipeline processor adopted for a microprocessor executes pipeline processes. The pipeline processes comprise the steps of reading a machine language instruction; decoding the read instruction; generating an address according to the decoded instruction; reading operand data from a cache memory (27) according to the generated address; executing the instruction; and writing data into the cache memory (27). When the machine language instruction is a write instruction, the operand data reading step involves a process of searching the cache memory (27) for the address where data is to be written. A result of the search is held in flag memories. Thereafter, the data writing step involves a process of referring to the flag memories, and is completed in one machine cycle.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a cache memory, and particularly to a pipeline processor and pipeline processing method for the microprocessor. 2. Description of the Prior Art Figure 1 is a block diagram showing a conventional pipeline processor. An instruction reading part 1 reads a machine language instruction. A decoding part decodes the instruction. An address generating part 5 provides an operand address. Based on the operand data, an executing part 9 executes the instruction. A writing part 11 writes a result of the execution. The data reading and writing processes mentioned above are carried out with respect to a cache memory 13. When data is read out of the cache memory 13, an address tag area of the cache memory 13 is simultaneously searched for an address tag of the read data to judge the validity of the read data. This reading operation needs, therefore, only one machine cycle. When data is written into the cache memory 13, there is a risk of writing the data into an incorrect location of the cache memory 13 if the data writing operation and address tag searching operation are simultaneously carried out and if a cache miss is judged by the address tag searching operation. To avoid the risk, the address tag searching operation must be done first, and then the data writing operation. The data writing process requires, therefore,two machine cycles. Figure 2 shows a flow of pipeline processes carried out in the conventional pipeline processor of Fig. 1. Respective processing stages are vertically arranged in Fig. 2 with the same reference marks seen in Fig. 1. In Fig. 2, time elapses from the left to the right, and an interval between adjacent dotted lines corresponds to one machine cycle. In Fig. 2, a read instruction A, write instructions B and C, and a read instruction D are pipeline-processed in parallel. The fifth and sixth machine cycles of an operand reading stage OF carried out in the operand reading part 7 are blank, because the write instructions B and C do not involve an operand reading operation. Each of the write instructions B and C requires, however, two machine cycles in a writing stage OS carried out in the writing part 11. The first one of the two machine cycles is used to search the cache memory 13 for an address tag of data to be written, and the second one is used to write the data into the cache memory 13. In this way, the conventional pipeline processor involves a processing stage where blanks occur and a processing stage where two machine cycles are consumed. These are disadvantageous in achieving an effective parallel processing. GB-A-2 200 483 relates to a microprocessor including a 4-stage instruction pipeline (Figure 8) for processing instruction execution and a cache memory. While an execution unit is calculating the results for one instruction, an address unit is calculating the effective addresses and reading source operands for the following instruction, and a loader is decoding a third instruction and prefetching a fourth instruction. A method is disclosed for completing instructions without waiting for writes to memory, whereby a precheck for the write permission is done simultaneously with the previous instruction execution before writing to an internal buffer. When a write access is requested, the address unit issues a probe request to the MMU and saves the virtual write address. once the MMU has acknowledged the request, the write address is provided to MMU, which translates the virtual address, and protection violations on each reference are checked, and possibly the use of the on-chip caches for the reference are inhibit For the access of the data cache 16 the following steps are performed: MMU 18 translates the virtual address and the physical address is transferred to the data cache 16 and to the BIU 20; the data cache 16 compares the tags with the physical address while BIU 20 initiates a bus cycle to read data from external memory; if there is a hit, the selected data is transferred to the execution unit 32 and BIU 20 cancels the bus cycle; if there is a miss, BIU 20 completes the external bus cycle; for memory write references, since the data cache is a write-through cache, if there is a hit, the contents of the cache are updated; the CPU 10 implements a method for completing instructions without waiting for writes to memory, in that when a write access is requested, the address unit 30 issues a probe request to the MMU 18 and saves the virtual write address, MMU translates the virtual address to determine whether the referenced page is in physical memory and if a write permission to that page. If a write permission exists a valid signal is asserted. If not a stop signal is asserted. When the instruction is executed, these signals are examined. If "stop", the execution unit suspends execution of the instruction and processes an abort trap. If "valid" the execution unit writes to its internal write buffer. A write request is then issued by the execution unit to the MMU for the data held in the write buffer. There is no suggestion of how to reduce the time required to write to the cache memory. SUMMARY OF THE INVENTION An object of the present invention is to provide a pipeline processor and a pipeline processing method for a microprocessor, which enable a writing process of a write instruction to be completed in one machine cycle. According to the present invention, there is provided a pipeline processor as set out in claim 1. Another aspect of the invention is set out in claim 2. This arrangement can reduce the number of machine cycles of the writing stage from two to one. The and other objects, features and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a conventional pipeline processor; Fig. 2 is an explanatory view showing a flow of pipeline processes carried out in the pipeline processor of Fig. 1; Fig. 3 is a block diagram showing a pipeline processor according to the present invention; Fig. 4 is a block diagram showing a cache memory and a flow of a cache memory search signal, according to the present invention; and Figs. 5 and 6 are explanatory views showing a flow of pipeline processes carried out in the pipeline processor of Fig. 3. DETAILED DESCRIPTION OF THE EMBODIMENTS Figure 3 is a block diagram showing a pipeline processor according to an embodiment of the present invention. The pipeline processor comprises an instruction reading part 15, an instruction decoding part 17, an address generating part 19, an operand reading part 21, an instruction executing part 23, and a writing part 25. The operand reading part 21 and writing part 25 are connected to a cache memory 27. Figure 4 shows the details of the cache memory 27. The cache memory comprises a data memory 27-1 and a tag memory 27-2 for storing address tags that indicate addresses of data blocks stored in the data memory 27-1. According to the present invention, the operand reading part 21 is particularly important. If an instruction to be processed is a read instruction, operand data of the instruction is read out of the cache memory 27, and at the same time, an address tag of the operand data is searched in the cache memory 27, similar to the conventional pipeline processes. If no cache miss is detected, i.e., if the address tag of the operand data is found in the tag memory 27-2 of the cache memory 27, the read operand data is transferred to the executing part 23 as shown in Fig. 5A. If the instruction to be processed is a write instruction, operand data is not needed for executing the instruction. In this case, unlike the conventional pipeline processor whose operand reading part 7 carries out no operation for the write instruction and provides a blank machine cycle, the operand reading part 21 of the present invention utilizes the machine cycle to see whether or not an address where data is to be written exists in the cache memory 27, as shown in Fig. 5B. Namely, the operand reading part 21 compares the address where data is to be written with the address tags stored in the tag memory 27-2 of the cache memory 27, and provides a signal indicating a result of the comparison, i.e., a cache hit signal or a cache miss signal. The signal is stored in a flip-flop 29. In the next machine cycle, the instruction is executed in the executing part 23, and the contents of the flip-flop 29 are transferred to a flip-flop 31 as shown in Figs. 3 and 4. The writing part 25 refers to the comparison result held in the flip-flop 31, and immediately writes the data into the cache memory 27 if a cache hit is confirmed. Effects of the present invention will be explained with reference to Fig. 6 which corresponds to Fig. 2. Unlike the conventional pipeline processor which carries out no process for a write instruction in the operand reading part 7, the operand reading part 21 of the present invention handles the write instruction such as the instructions B and C. Namely, the operand reading part 21 searches the tag memory 27-2 of the cache memory 27 for an address where data is to be written. This brings effects that the operand writing part 25 requires only one machine cycle for writing the data into the cache memory 27, that each of the pipeline stages is completed in one machine cycle, and that respective instructions are effectively aligned linearly as shown in Fig. 6. According to the conventional pipeline processes of Fig. 2, execution of the instruction C is completed in the tenth cycle. According to the present invention, the same is completed in the eighth cycle as shown in Fig. 6. In connection with an instruction E involving reading and writing processes, two instruction, i.e., a read instruction El and a write instruction E2 are processed similar to the instructions A and B after the addresses thereof are calculated. For the write instruction E2, an address tag of the address is searched in the tag memory 27-2 of the cache memory 27 in the operand reading stage OF.

Claims: A pipeline processor comprising: an instruction reading part (15) for reading a machine language instruction; a decoding part (17) for decoding the reading instruction; an address generating part (19) for generating an address according to the decoded instruction; an operand reading part (21) for reading operand data from a cache memory (27) according to the address generated by said address generating part, said operand reading part searching a tag storing area (27-2) of the cache memory for the generated address where data is to be read, when the machine language instruction is a read instruction; an executing part (23) for executing the instruction; a writing part (25) for writing data into the cache memory; characterized in that said operand reading part (21) also searches said tag storing area (27-2) for the generated address where data is to be written, when the machine language instruction is a write instruction; and further characterized by a first flag memory (29) for holding a result of the search; and by a second flag memory (31) for holding the contents of said first flag memory; and further characterized in that said writing part (25) writen data into the cache memory after referring to the contents of said record flag memory. A pipeline processing method comprising the steps of: reading a machine language instruction; decoding the read instruction; generating an address according to the decoded instruction; reading operand data from a cache memory according to the address generated in said address generating step; executing the instruction; and writing data into the cache memory, said operand data reading step involving, when the machine language instruction is a write instruction, a process of searching the cache memory for the address where data is to be written, a result of the search being held in a first flag memory that is prepared for some of said steps to be carried out after said operand data reading step, and thereafter copying the contents of the first flag memory to a second flag memory said data writing step involving a process of referring to the second flag memory, and being completed in one machine cycle.

Inventors: SASAI KIYOTAKA, SASAI, KIYOTAKA
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F12
IPC codes: G06F9, G06F12, G11C8