Image reduction/enlargement technique

Abstract: A method of reducing an M X N input binary image (M rows of N pixels each) by a factor of m vertically and n horizontally includes the steps of performing at least one logical operation between bits in consecutive groups of m adjacent rows to provide a resultant single row for each group of m rows, and performing at least adjacent columns to provide a resultant single column for each groups of n columns. For certain types of reductions the resulting reduced image will be the desired output image, while for other types, the resultant image will be one of a required plurality of intermediate images, which are then combined to provide the desired output image.

Description: The present invention relates generally to image processing and is concerned, more specifically, with reducing or enlarging image bit maps. At the resolutions used by modern electronic printers and scanners, the number of pixels in an image can be quite large. At 600 dots per inch, a single 8.5 inch by 11 inch image contains 33,000,000 pixels. Processing such large amounts of data is expensive and time consuming. Fortunately, many image interpretation operations need not be done at full resolution, but may be done on images that have been uniformly reduced in size. Operations on reduced images can provide significant performance improvements. In general, it is not necessary to reduce images by arbitrary factors. Rather, reductions by simple powers of 2 will generally suffice. US-A- 4,742,553 discloses the possible use of thresholded reductions in the context of accomplishing resolution conversion. The example given is a 2x2 reduction wherein each tile of 4 input pixels is mapped onto a single output pixel. The particular example had the output pixel value being OFF for 0-2 input pixels ON and the output pixel being ON for 3-4 input pixels being ON. It is noted that the technique inevitably results in the loss of gray scale information. There are, however, applications where the loss of gray scale information is not significant. GB-A-2 160 057 discloses image reproduction in which a pixel matrix is divided into groups which are mapped to groups of larger pixels in the reproduction. Within each original array, subarrays thereof are mapped to respective pixels in the reproduction, by a logic sum function of the original pixel binary values. Circuitry disclosed for carrying out image reproduction includes AND gates and OR gates that operate on binary pixel values. The present invention is concerned with the provision of techniques for efficiently reducing or enlarging image bitmaps. In one aspect of the invention, there is provided a method for reducing an image composed of pixelwords by operating on consecutive groups of m vertically adjacent pixelwords, each consecutive group of m vertically adjacent pixelwords including subregions, each subregion having m pixels down and n pixels across, each subregion to be mapped to a single pixel in the reduced image. comprising: performing logical operations to combine a consecutive group of m vertically adjacent pixelwords into a resultant pixelword with valid bits, each valid bit indicating whether the number of ON pixels in one of the subregions is greater than or equal to a threshold level; the logical operations including: at least one logical operation that combines bits in a consecutive group of vertically adjacent pixelwords; and at least one operation that combines a consecutive group of horizontally adjacent bits within a pixelword; the operation including shifting the pixelword to obtain a shifted version and performing a logical operation on the pixelword and the shifted version to combine horizontally adjacent bits; and extracting the valid bits from the resultant pixelword. Consider the examples of a 2x2 reduction wherein each 2x2 tile of input pixels is mapped onto a single pixel in the output image, with the value of the pixel in the output image being determined by whether the number of ON pixels in the tile in the input image is greater than or equal to a threshold level. A reduction with LEVEL=1 (1 or more pixels ON) is produced by ORing pairs of adjacent rows to provide a reduced number of rows and then ORing pairs of adjacent columns to provide the desired reduced image. Similarly, a reduction with LEVEL=4 is produced by ANDing pairs of adjacent rows and then ANDing pairs of adjacent columns to provide the desired reduced image. However, a reduction with LEVEL=2 or LEVEL=3 requires producing a pair of intermediate images which are then combined. One intermediate image is produced by ORing pairs of adjacent rows and then ANDing pairs of adjacent columns; the other intermediate image is produced by ANDing pairs of adjacent rows and ORing pairs of adjacent columns. The reduced image with LEVEL=2 is produced by ORing the intermediate images; the reduced image with LEVEL=3 is produced by ANDing the intermediate images. Word parallelism in the computer makes logical operations between rows computationally efficient. A row of pixels is represented by a number of adjacent words in memory, and therefore logically combining a pair of rows, bit by bit, may be accomplished by combining the words that make up one row with the words that make up the other row. This is computationally efficient since a single operation that combines two words logically combines many pairs of bits at a time. By way of contrast, a column of pixels is represented by one bit from each of many words in memory. Therefore, logically combining two columns requires combining pairs of bits in each word, one pair at a time, without the benefit of word parallelism. Therefore, the column operations are much less efficient computationally since the corresponding bits in the two columns must be found, two bits at a time, before the logical operations can be done. Column operations can be speeded up by use of lookup tables. If each row is considered a logically contiguous pixelword, a reduction by a factor n requires a lookup table for each logical operation. The pixelword is broken up into segments n*k pixels wide. The table contains 2 n*k entries, addressable by an (n*k)-bit address. The entry for that address is k bits wide, with each bit being equal to the result of performing the desired logical operation on n-bit groups of the (n*k)-bit address. Performing row and column operations in a general purpose computer, even with lookup tables for column operations, is limited by the width of the computer word. The invention overcomes this limitation by providing techniques and specialized hardware for performing column operations on very wide pixelwords. Assume a wide pixelword has 2Q bits, with bits being numbered 0 to (2Q-1). In another aspect of the invention, there is provided a method for reducing an image composed of 2Q-bit pixelwords by performing a logical operation between vertically adjacent pixelwords to obtain and then pairwise bit reduce a resultant pixelword, comprising the steps of: (a) reading a pair of vertically adjacent pixelwords from a first memory in which the image is stored onto a data bus and into a first register and a second register; (b) ANDing the first and second registers and storing the results in a third register and a fourth register; (c) shifting the content of the fourth register one bit to the right; (d) ORing the third and fourth registers and storing the results in the fourth register, so that the fourth register contains the results of ANDing the pixelwords and ORing pairs of adjacent bits with the valid bits in the odd bit position; (e) ORing the first and second registers and storing the results in the second and third registers; (f) shifting the content of the third register one bit to the right; (g) ANDing the second and third registers and storing the result in the third register, so that the third register contains the result of ORing the two pixelwords and the ANDing pairs of adjacent bits with the valid bits in the odd bit position; (h) effecting the reduction by ORing the third and fourth registers and providing the result to a data port which is coupled to the data bus for access thereto; and (i) extracting the valid bits from the result. Similarly, specialized hardware can reduce a pixelword in two stages. To perform a first stage, apparatus provides the facility to combine the wide pixelword with a shifted version of itself. To this end, the pixelword is read into a pair of registers, shifted one position (say to the right) in one register, and the contents of the two registers are logically combined. The result is a pixelword having the desired pairwise combinations in every other bit position, which in the case of a right shift are the odd bit positions 1, 3, ... (2Q-1). The even bit positions contain invalid data. The result transferred to a processor data port and made available on a data bus. To perform a second stage, apparatus provides the facility for compressing the separated bits. It includes first and second latched transceivers, each having two ports. The lines from each of the first ports are connected to the odd data bus lines. The lines of the second port of the first transceiver are connected to adjacent lines on one half of the data bus while the lines from the second port of the second transceiver are coupled to adjacent lines on the other half of the data bus. Thus, pixelwords are compressed as follows. A first input pixelword is processed at the first stage so that the bits of interest (valid bits) occupy the odd bit positions, and the result is put on the data bus. The odd bits of the bus are latched into the first transceiver via its first port. A second input pixelword is similarly processed and the odd bits are latched into the second transceiver via its first port. The contents of the two transceivers are read out through their second ports onto respective halves of the data bus and are communicated to the processor data port. This represents a new pixelword that is the column reduced version of the two input pixelwords. It is written back into memory in a location set aside for the reduced image. In yet another aspect of the invention, there is provided apparatus for reducing an image composed of 2Q-bit pixelwords by performing a logical operation between vertically adjacent pixelwords to obtain and then pairwise bit reduce a resultant pixelword, characterized by: a data bus with bits 0 through (Q-1) and bits Q through (2Q-1); a first memory and a second memory, each connected to the data bus; a processor including a plurality of registers and having a 2Q-bit data port coupled to the data bus; first and second Q-bit latched transceivers, each with first and second ports, the first ports of both latched transceivers being coupled to the same set of alternating bit positions of the data bus, the second port of the first latched transceiver being coupled to bits 0 through (Q-1) of the data bus, the second port of the second latched transceiver being coupled to bits Q through (2Q-1) of the data bus; and a control unit for controlling the first and second memories and the processor; the control unit controlling the first and second memories and the processor: to read pairs of vertically adjacent pixelwords from the first memory into two of the registers; to perform logical operations to combine each pair of vertically adjacent pixelwords into a resultant pixelword with valid bits in every other bit position, each valid bit indicating whether a 2 × 2 array of pixels is greater than or equal to a threshold level; the logical operations including: at least one logical operation that combines bits in the pair of vertically adjacent pixelwords; and at least one operation that combines horizontally adjacent bits within a pixelword stored in two of the registers; the operation including shifting the pixelword in one of the registers to obtain a shifted version and performing a logical operation on the pixelword and the shifted version to combine horizontally adjacent bits; and to use the first and second latched transceivers to extract the valid bits from the resultant pixelwords obtained from two pairs of vertically adjacent pixelwords for storage in the second memory. By way of example only, embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of an image scanning and processing system; Figs. 2A and 2B are schematic views showing the reduction of an image by successive row and column operations; Fig. 2C shows flow diagrams for implementing thresholded 2x2 reductions; Fig. 3A shows 2x2 arrays that return an ON pixel when acted on by 2x2 basis operators; Fig. 3B shows the set of 2x2 arrays in canonical form; Fig 4 is a schematic view of a table lookup system for performing column operations; Figs. 5A and 5B show the set of 3x3 arrays in canonical form, with the threshold operators for a 3x3 reduction; Figs. 6A-6H show the set of 4x4 arrays in canonical form; Figs. 7 and 8 are schematic representations of 4x1 thresholding operators applied to particular column vectors; Fig. 9 is a schematic view of a table lookup system for performing expansions; Fig. 10 is a logic schematic of hardware for use in performing column operations; and Fig. 11 shows flow diagrams for morphological implementations of thresholded reductions. Definitions and Terminology The present discussion deals with binary images. In this context, the term "image" refers to a representation of a two-dimensional data structure composed of pixels. A binary image is an image where a given pixel is either "ON" or "OFF." Binary images are manipulated according to a number of operations wherein one or more source images are mapped onto a destination image. The results of such operations are generally referred to as images. The image that is the starting point for processing will sometimes be referred to as the original image. Pixels are defined to be ON if they are black and OFF if they are white. It should be noted that the designation of black as ON and white as OFF reflects the fact that most documents of interest have a black foreground and a white background. While the techniques to be described could be applied to negative images as well, the discussion will be in terms of black on white. A "solid region" of an image refers to a region extending many pixels in both dimensions within which substantially all the pixels are ON. A "textured region" of an image refers to a region that contains a relatively fine-grained pattern. Examples of textured regions are halftoned or stippled regions. "Text" refers to portions of a document or image containing letters, numbers, or other symbols including non-alphabetic linguistic characters. "Line graphics" refers to portions of a document or image composed of graphs, figures, or drawings other than text, generally composed of horizontal, vertical, and skewed lines having substantial run length as compared to text. Graphics could range from horizontal and vertical lines in an organization chart to more complicated horizontal, vertical, and skewed lines in engineering drawings. A "mask" refers to an image, normally derived from an original image, that contains substantially solid regions of ON pixels corresponding to regions of interest in the original image. The mask may also contain regions of ON pixels that don't correspond to regions of interest. AND, OR, and XOR are logical operations carried out between two images on a pixel-by-pixel basis. NOT is a logical operation carried out on a single image on a pixel-by-pixel basis. "Expansion" is a scale operation characterized by a SCALE factor N, wherein each pixel in a source image becomes an NxN square of pixels, all having the same value as the original pixel. "Reduction" is a scale operation characterized by a SCALE factor N and a threshold LEVEL M. Reduction with SCALE = N entails dividing the source image into NxN squares of pixels, mapping each such square in the source image to a single pixel on the destination image. The value for the pixel in the destination image is determined by the threshold LEVEL M, which is a number between 1 and N 2 . If the number of ON pixels in the pixel square is greater or equal to M, the destination pixel is ON, otherwise it is OFF. "Subsampling" is an operation wherein the source image is subdivided into smaller (typically square) elements, and each element in the source image is mapped to a smaller element in the destination image. The pixel values for each destination image element are defined by a selected subset of the pixels in the source image element. Typically, subsampling entails mapping to single pixels, with the destination pixel value being the same as a selected pixel from the source image element. The selection may be predetermined (e.g. upper left pixel) or random. A "4-connected region" is a set of ON pixels wherein each pixel in the set is laterally or vertically adjacent to at least one other pixel in the set. An "8-connected region" is a set of ON pixels wherein each pixel in the set is laterally, vertically, or diagonally adjacent to at least one other pixel in the set. A number of morphological operations map a source image onto an equally sized destination image according to a rule defined by a pixel pattern called a structuring element (SE). The SE is defined by a center location and a number of pixel locations, each having a defined value (ON or OFF). Other pixel positions, referred to as "don't care", are ignored. The pixels defining the SE do not have to be adjacent each other. The center location need not be at the geometrical center of the pattern; indeed it need not even be inside the pattern. A "solid" SE refers to an SE having a periphery within which all pixels are ON. For example, a solid 2x2 SE is a 2x2 square of ON pixels. A solid SE need not be rectangular. A " hit-miss" SE refers to an SE that specifies at least one ON pixel and at least one OFF pixel. " Erosion" is a morphological operation wherein a given pixel in the destination image is turned ON if and only if the result of superimposing the SE center on the corresponding pixel location in the source image results in a match between all ON and OFF pixels in the SE and the underlying pixels in the source image. "Dilation" is a morphological operation wherein a given pixel in the source image being ON causes the SE to be written into the destination image with the SE center at the corresponding location in the destination image. The SE's used for dilation typically have no OFF pixels. "Opening" is a morphological operation that consists of an erosion followed by a dilation. The result is to replicate the SE in the destination image for each match in the source image. "Closing" is a morphological operation consisting of a dilation followed by an erosion. The various operations defined above are sometimes referred to in noun, adjective, and verb forms. For example, references to dilation (noun form) may be in terms of dilating the image or the image being dilated (verb forms) or the image being subjected to a dilation operation (adjective form). No difference in meaning is intended. System Overview Fig. 1 is a block diagram of an image analysis system 1. The basic operation of system 1 is to extract or eliminate certain characteristic portions of a document 2. To this end, the system includes a scanner 3 which digitizes the document on a pixel basis, and provides a resultant data structure, typically referred to as an image. Depending on the application, the scanner may provide a binary image (a single bit per pixel) or a gray scale image (a plurality of bits per pixel). The image contains the raw content of the document, to the precision of the resolution of the scanner. The image may be sent to a memory 4 or stored as a file in a file storage unit 5, which may be a disk or other mass storage device. A processor 6 controls the data flow and performs the image processing. Processor 6 may be a general purpose computer, a special purpose computer optimized for image processing operations, or a combination of a general purpose computer and auxiliary special purpose hardware. If a file storage unit is used, the image is transferred to memory 4 prior to processing. Memory 4 may also be used to store intermediate data structures and possibly a final processed data structure. The result of the image processing, of which the present invention forms a part, can be a derived image, numerical data (such as coordinates of salient features of the image) or a combination. This information may be communicated to application specific hardware 8, which may be a printer or display, or may be written back to file storage unit 5. Basic Procedure Consider an mxn reduction (reduction by a factor of m vertically and n horizontally) of an MxN original image (M rows, N columns). Since most of the following discussion deals with binary images (one bit per pixel), pixels will often be referred to as bits. The reduction occurs in a sequence of two steps. In the first step, raster operations (either AND or OR) are performed on each set of m rows, with the result going into a single row in a temporary array. This is illustrated in Fig. 2A for m = 2. In this way, the number of rows is reduced by a factor of m. If M/m is not an integer, the excess (= M mod m) rows will be ignored. In the second step, raster operations map each set of n columns in the temporary array into a single column in the reduced array, as illustrated in Fig. 2B for n = 2. In this reduction, any excess (= N mod n) columns will be ignored. This procedure reduces the problem from a transformation on the full image to the logical problem of reducing an mxn rectangular array of bits (called a tile) to one bit. We wish to find a sequence of AND and OR operations between the rows and columns that will result in a thresholding operation on each mxn tile in the original. For the purpose of illustration consider equal reduction factors in both dimensions, i.e., m = n. Specifically, we want a set of n 2 boolean operators, implementable by row and column raster operations, that map an nxn bitmap to a single bit, such that for i = 1, 2, ..., n 2 there exists an operator with the following property: for all nxn bit arrays with fewer than i ON bits, the result is a single OFF bit, and for all arrays with i or more ON bits, the result is a single ON bit. There is in general no unique solution to this problem, but we will develop results subject to the constraints that: (1) we first do row operations and then column operations; and (2) the operations between rows and columns are either AND or OR. The first constraint is in a sense arbitrary, but it allows for a more concrete description. Depending on the particular implementation, however, it may be faster if the row operations are carried out first. For a 2x2 reduction, there are only 2 4 = 16 configurations, and the minimum mapping operators are easily found by considering these 16 cases. However, the number of configurations grows exponentially with the power n 2 : for n = 3 there are 2 9 = 512 configurations; for n = 4 there are 2 16 = 65,536; etc. The way to find operators that work over such large sets is to decompose them into products of particular row and column operators that will exploit symmetries among the configurations. We will choose to use row and column operators that themselves are thresholding operators for 1xn and nx1 arrays. The product of these row and column operators can then be used to form a basis set for the nxn operators, from which we select appropriate boolean combinations for thresholding. To put the analytic discussion below in context, it is helpful to consider a brief outline of the row and column operations for performing 2x2 thresholded reductions. Fig. 2C shows flow diagrams for these operations. A reduction with LEVEL = 1 (1 or more pixels ON) is produced by ORing pairs of adjacent rows to provide a reduced number of rows and then ORing pairs of adjacent columns to provide the desired reduced image. Similarly, a reduction with LEVEL = 4 is produced by ANDing pairs of adjacent rows and then ANDing pairs of adjacent columns to provide the desired reduced image. However, a reduction with LEVEL = 2 or LEVEL = 3 requires producing a pair of intermediate images which are then combined. One intermediate image is produced by ORing pairs of adjacent rows and then ANDing pairs of adjacent columns; the other intermediate image is produced by ANDing pairs of adjacent rows and ORing pairs of adjacent columns. The reduced image with LEVEL = 2 is produced by ORing the intermediate images; the reduced image with LEVEL = 3 is produced by ANDing the intermediate images. One significant attribute of performing reductions in this way is that it is not necessary to have the entire original image or the entire intermediate images (if required) in memory. Rather, only m rows are needed. The rows, or segments thereof, are logically combined to form a single row, groups of n bits in this row are combined, and the result is stored, either permanently as a portion of the desired reduced image, or temporarily as a portion of an intermediate image. In the latter case, portions of other necessary intermediate images will be similarly generated and temporarily stored, and the portions of the intermediate images will be combined and stored as a portion of the desired reduced image. Threshold Operators for n = 2 Reduction : 2x2 → 1x1 As mentioned above, we choose row (and column) operators that threshold the 1x2 (and 2x1) bitmaps. Clearly, the requisite thresholding operators on either rows or columns are: a OR 1 or more ON bits b: AND 2 ON bits The four products of these operators form a basis set of operators on 2x2 bit arrays: aa OR/OR all with 1 or more ON bits ab OR/AND some with 2 or more ON bits ba AND/OR some with 2 or more ON bits bb AND/AND all 4 ON bits The comment on the right describes those 2x2 arrays for which the operator returns an ON bit. The operators aa and bb are in fact the required ones for thresholding at 1 and 4 ON bits, respectively. To find thresholding operators for 2 and 3 ON bits, we must form boolean combinations of the basis operators. It is useful to recast the above descriptions of the array types for which the basis operators return an ON bit. Because the one-dimensional (row and column) operators are chosen to be threshold operators, these four 2x2 basis operators return an ON bit when they act on the stated subset of 2x2 arrays: aa 1 or more ON bits ab at least 1 ON bit in each column ba at least one column with 2 ON bits bb all 4 ON bits Now consider the 16 possible 2x2 bit arrays. Choose a subset of these arrays by applying the following two rules of reduction, which follow directly from the use of one-dimensional threshold operators: (1) The position of ON bits within a column does not matter. Thus, put the ON bits in each column in the top rows. (2) The columns can be permuted. Thus, arrange the columns to have number of ON bits in each column decreasing to the right. These reduction rules generate the canonical form of an array. Fig. 3A shows the minimum arrays (in canonical form) that will return an ON bit when operated on by the stated operator. For example, any array with one ON bit will return an ON bit when its rows are ORed and then its columns are ORed. However, the array with the single ON bit in the upper left corner is the canonical form according to the two rules above. Fig. 3B shows the set of all distinct canonical 2x2 bit arrays. (Not shown is the array of all OFF pixels). The general procedure then is to represent the set of distinct arrays in this canonical form. The operator that projects any one of these distinct arrays is in general an intersection of basis operators, which are figuratively represented in Fig. 2. Group these canonical arrays into sets that have exactly one, two, three,... ON bits. The thresholding operators are then the union of operators specific to each array. For use in later sections, we adopt the following notation for both the canonical arrays and, by implication, the operators that project them. An nxn canonical array with e(j) entries in the j th column is denoted n(e(1),...,e(n)) Thus, the canonical arrays depicted in Fig. 3 are 2(1,0) (one ON bit) 2(1,1) and 2(2,0) (two ON bits) 2(2,1) (three ON bits) 2(2,2) (four ON bits) Reference to Fig. 2 for the representation of the two-dimensional basis operators makes it possible to write the 2x2 threshold operators II 1 , II 2 , II 3 , and II 4 by inspection: II 1 aa all with 1 or more ON bits II 2 ab ∪ ba all with 2 or more ON bits II 3 ab ∩ ba all with 3 or more ON bits II 4 bb all 4 ON bits There are two canonical arrays for 2 ON bits, given in Fig. 3, and the union of basis operators ab and ba clearly projects all such arrays. Hence, operator II 2 is the union of these two basis operators. There is only one canonical array for 3 ON bits, and the thresholding operator II 3 corresponding to this array requires the intersection of the basis operators ab and ba. (This appears graphically as the union of the array representations for ab and ba given in Fig. 2.) The threshold operators display a simple symmetry when expressed in terms of these basis operators. They could have been written down by inspection after trying a few examples, but the formal approach given above will be useful for thresholded reductions with n > 2. Implementation of 2x2 → 1x1 reduction The 2x2 operators II 1 -II 4 have been implemented in C, using the Sun rasterops functions on memory pixrects. The Sun raster operations are themselves written in C, and the column raster operations (Fig. 2B) are, in particular, very slow. Using a Sun 3/260, a 1000x1000 pixel binary image can be reduced by II 1 and II 4 in 2.5 seconds, and by II 2 and II 3 in 5 seconds. However, over 90% of this CPU time is used by the relatively small column raster operations. A table lookup scheme can speed up column reduction operations by a factor of 25. Fig. 4 is a schematic view of a table lookup for computing pairwise bit combinations (OR and AND) for 8-bit segments of a row of pixels. This entails constructing two 2 8 -entry tables, one for OR and one for AND, that are indexed by eight bits in the intermediate image (generated by raster operations on the rows), and contain four bits of the reduced image that correspond to the pair-wise ORing or ANDing of the index bits, respectively. The figure shows some representative pixel segments and the table entries that they point to. As noted above, Fig. 4 shows an 8-bit index into 2 8 -entry tables of 4-bit entries. This is for simplicity; the actual embodiment uses a 16-bit index into tables containing 2 16 8-bit entries. The OR and AND lookup tables can be generated from an iterative algorithm that does not require bit masking. For the OR table with a 16-bit index i, the 8-bit table values t(i) are generated by t(0) = 0, i = 1; for (d = 0 ... 7) i 0 = 2 2d ; /* start value of i */ t 0 = 2 d ; /* increment value of t*/ for(r = 1... 3) for k = 0 ... (i 0 - 1) t(i) = t(k) + t 0 ; i = i + 1; Similarly, a 16-bit index AND table is generated by t(0) = 0,i = 1; for (d = 0 ... 7) i 0 = 2 2d ; /* start value of i */ t 0 = 2 d ; /* increment value of t*/ for(r = 1...3) if (r < 3) tlnc = 0; else tlnc = t 0 ; for k = 0... (i 0 - 1) t(i) = t(k) + tlnc; i = i + 1; With this hybrid (rasterop/lookup) implementation, the column logical operations are as fast, on a per-word basis, as the Sun rasterop row operations. Thus, the column operations take one-half the time of the row operations. The total time is reduced by a factor of ten when compared to an implementation that uses only raster operations. With the hybrid implementation, the reduction operations II 1 and II 4 take 0.25 seconds, and II 2 and II 3 take 0.5 seconds on a 1000 x 1000 pixel binary image. Optimizing the row operations and the table lookup for columns brings these times down to 0.1 seconds and 0.2 seconds. The processing speed on a Sun 3/260 is thus 10x10 6 pixels/second and 5x10 6 pixels/second, for the fast and slow reductions, respectively. Threshold Operators for n = 3 Reduction: 3x3 → 1x1 The methods used for 2x2 reductions can be extended to an analogous 3x3 reduction. Figs. 5A and 5B show the canonical 3x3 arrays and threshold operators, developed as described below. To find the threshold operators for the 2 9 3x3 bit arrays, we again start with threshold operators between either rows or columns. These operators are now composed of more than one successive operation. Denote an operator OR i,j (or AND i,j ) to mean the OR (or AND) of i and j, where i and j are unequal elements of the set (1,2,3). Then the three threshold projection operators for rows or columns are easily seen to be a OR 2,1 ∪ OR 3,1 (1 or more ON bits) b AND 2,1 ∪ AND 3,1 ∪ AND 3,2 (2 or more ON bits) c AND 2,1 ∩ AND 3,1 (all 3 ON bits) Note that the a and c operators can be reduced to two operations (from three) by sequentially operating as follows: a OR 2,1 OR 3,1 c AND 2,1 AND 3,1 where here the result of OR i,j or AND i,j is put in j, and the operators are evaluated from left to right. As before, form a basis set of nine operators on the 3x3 bit arrays from products of these row and column operators. When these operators act on the 3x3 bit arrays, they give an ON bit for the stated subset of arrays: aa 1 or more ON bits ab at least 1 ON bit in 2 columns ac at least 1 ON bit in 3 columns ba at least 2 On bits in 1 column bb at least 2 On bits in 2 columns bc at least 2 ON bits in 3 columns ca at least 3 ON bits in 1 column cb at least 3 ON bits in 2 columns cc all 9 bits ON To form the threshold operators as boolean combinations of these basis operators, we form all canonical 3x3 bit arrays that are distinct in the sense of the rules discussed above. These canonical arrays are 3(1,0,0) (one ON bit) 3(1,1,0), 3(2,0,0) (two ON bits) 3(1,1,1), 3(2,1,0), 3(3,0,0) (three ON bits) 3(2,1,1), 3(2,2,0), 3(3,1,0) (four ON bits) 3(2,2,1), 3(3,1,1), 3(3,2,0) (five ON bits) 3(2,2,2), 3(3,2,1), 3(3,3,0) (six ON bits) 3(3,2,2), 3(3,3,1), 3(3,3,0) (seven ON bits) 3(3,3,2) (eight ON bits) 3(3,3,3) (nine ON bits) The action of the nine basis operators given above leads to the identification associated with each canonical array, expressed in general as an intersection of basis operators. The threshold operators III 1 -III 9 are then found as the union of these generally composite operators corresponding to the canonical arrays. The thresholding operators display a high degree of symmetry. They can be reduced to some extent by combining terms, and some of the terms can be expressed by the 2x2 operators. For example, III 3 = ac ∪ II 3 ∪ ca Note, however, that in this expression, the a and b operators in II 3 are the threshold operators for a 3x1 (or 1x3) bit array, not those for a 2x1 array. Threshold Operators for n = 4 Reduction: 4x4 → 1x1 The extension to 4x4 reduction is straightforward. Figs. 6A-6H show the canonical 4x4 arrays and threshold operators, developed as described below. The threshold operators that work on the 2 16 4x4 arrays are derived from products of one-dimensional 4x1 (and 1x4) threshold operators. These can be written down directly, by extension of the 3x1 operators given above. However, they are most efficiently represented by the following set of sequential operations: a OR 2,1 OR 4,3 OR 3,1 (1 or more ON bits) b (OR 2,1 OR 4,3 AND 3,1 ) ∪ (OR 4,1 OR 3,2 AND 2,1 ) (2 or more ON bits) c (AND 2,1 OR 4,3 AND 3,1 ) ∪ (OR 2,1 AND 4,3 AND 3,1 ) (3 or more ON bits) d AND 2,1 AND 4,3 AND 3,1 (all 4 ON bits) As in the case of operators a and c for the 3x3 reductions, these operations are carried out from left to right, with the result of each part being placed in the row or column given by the second subscript. These operators perform the same thresholding function on a 4x1 bit array as the operators II 1 -II 4 perform on a 2x2 bit array. However, the representation for the former is considerably more complicated because of the one one-dimensional nature of the array. Figs. 7 and 8 show the actions of operators b and c, respectively, on a particular bit in four adjacent rows. In Fig. 7, the operator b acts on the four bits 1100. The left side gives a 0, but the right side evaluates to 1, and because the result is an OR of these two parts, the operator b returns a 1 for this bit. In Fig. 8, the operator c acts on the four bits 1101. In this case the left side evaluates to 1 and the right side to 0, and the operator c returns a 1, the OR of the two parts. With the row and column thresholding operators defined above, we can take products of these operators to form a basis set of 16 operators which, when applied to the set of 4x4 bit arrays, result in an ON bit for the stated subset: aa 1 or more ON bit ab at least 1 ON bit in 2 columns ac at least 1 ON bit in 3 columns ad at least 1 ON bit in 4 columns ba at least 2 ON bits in 1 column bb at least 2 ON bits in 2 columns bc at least 2 ON bits in 3 columns bd at least 2 ON bits in 4 columns ca at least 3 ON bits in 1 column cb at least 3 ON bits in 2 columns cc at least 3 ON bits in 3 columns cd at least 3 ON bits in 4 columns da at least 4 ON bits in 1 column db at least 4 ON bits in 2 columns dc at least 4 ON bits in 4 columns dd all 16 bits ON The distinct canonical 4x4 bit arrays are denoted as follows: 4(1,0,0,0) (one ON bit) 4(1,1,0,0), 4(2,0,0,0) (two ON bits) 4(1,1,1,0), 4(2,1,0,0), 4(3,0,0,0) (three ON bits) 4(1,1,1,1), 4(2,1,1,0), 4(2,2,0,0), 4(3,1,0,0), 4(1,0,0,0) (four ON bits) 4(2,1,1,1), 4(2,2,1,0), 4(3,1,1,0) 4(3,2,0,0), 4(4,1,0,0) (five ON bits) 4(2,2,1,1), 4(2,2,2,0), 4(3,2,1,0) 4(3,3,0,0), 4(4,1,1,0), 4(4,2,0,0) (seven ON bits) 4(2,2,2,2), 4(3,2,2,1), 4(3,3,1,1), 4(3,3,2,0), 4(4,2,1,1), 4,(4,2,2,0), 4(4,3,1,0) 4(4,4,0,0) (eight ON bits) 4(3,2,2,2), 4(3,3,2,1), 4(3,3,3,0), 4(4,2,2,1), 4(4,3,1,1), 4(4,3,2,0), 4(4,4,1,0) (nine ON bits) 4(3,3,2,2), 4(3,3,3,1), 4(4,2,2,2), 4(4,3,2,1), 4(4,3,3,0) 4(4,4,1,1), 4(4,4,2,0) (ten ON bits) 4(3,3,3,2), 4(4,3,2,2), 4(4,3,3,1) 4(4,4,2,1), 4(4,4,3,0) (eleven ON bits) 4(3,3,3,3), 4(4,3,3,2), 4(4,4,2,2) 4(4,4,3,1), 4(4,4,4,0) (twelve ON bits) 4(4,3,3,3), 4(4,4,3,2), 4(4,4,4,1) (thirteen ON bits) 4(4,4,3,3), 4(4,4,4,2) (fourteen ON bits) 4(4,4,4,3) (fifteen ON bits) 4(4,4,4,4) (all sixteen ON bits) As before, each of these canonical arrays has an associated operator that is an intersection of the two-dimensional basis operators. The sixteen threshold operators on 4x4 arrays are then found as unions of these operators that represent the canonical arrays. The expressions can be simplified somewhat by noticing that sets of canonical arrays for lower order reducing operators are invariably contained within higher order operators. For example, that the forms if IV 1 , IV 2 , and IV 3 , in terms of the basis operators a, b, and c, are identical to those III 1 , III 2 , and III 3 , respectively, except that the meanings of the one-dimensional thresholding operators a, b, and c are different in the two cases. Image Expansion Operators Operators that expand a binary image in each direction by an integral factor can be simply constructed by a variant of the approach given above. Suppose it is desired to magnify an image by factors c and r in the horizontal and vertical directions, respectively. As before, the process requires two steps: replication of each row r times, with insertion into the expanded image, followed by similar expansion of the columns by a factor c. Because of the inefficiency of column raster operations, fast implementations require table lookup for column expansion. Fig. 9 is a schematic view of a table lookup for expanding a row of an image to twice its length. The illustration is in terms of expanding 4-bit segments to 8 bits. More generally, if the number of columns is to be expanded by a factor of c, for example, a lookup table with 2 8 entries of c bytes each will suffice to convert 1 byte (8 bits) of the original image into c bytes of expanded image. The following algorithm generates a table of 2 8 16-bit entries t(i), that map 8 bits of the original image into 16 bits, thereby doubling the width: t(0) = 0,i = 1; for (d = 0...7) i 0 = 2 d ; /* start value of i */ t 0 = 3(i 0 ) 2 ; /* increment of value of t */ for (k = 0... i 0 - 1) t(i) = t(k) + t 0 ; i = i + 1; As before, performance of this algorithm is comparable to row raster operations, on a per-word basis. Extension to Grayscale images These methods lead to a simple approach to reduction of grayscale images. Consider a simple example of a 2x2 reduction of a 4-bit or 8-bit grayscale image, that yields a reduced grayscale image with the same number of bits/pixel. Suppose it is desired to replace the four pixel values in each 2x2 square by a single pixel with the average value, and pixel values are 8 bits. Thus, an efficient method is needed for summing the four 8-bit numbers in each 2x2 square, and dividing the result by 4. The first step is to sum corresponding (same column) pixels in even and odd numbered rows, in analogy with the row rasterops for binary images. To avoid overflow, first right-shift all pixel values: each byte in the image is right-shifted by two bits. Thus, division by 4 is done before summation. Then the pixel data in each set of even and odd rows is added. For efficiency, this can be done a word at a time, treating each set of four consecutive pixels as a 32-bit integer. (Note that each line of pixel data must be padded to word boundaries). The column sums can be carried out either directly or via table lookup. In the direct method, the even and odd adjacent bytes in a row are simply added. A somewhat more efficient implementation uses table lookup. As in the binary case, each successive 16-bits represent a pair of pixel values, and the 8-bit content of the array is the integer sum of the two bytes. The result of these row and "column" operations is a grayscale image, reduced in size by a factor of 2 in each dimension, where the value of each pixel in the reduced image is the approximate average of the four corresponding pixels in the original. These reductions are easily cascaded, giving a series of grayscale images with size reductions by powers of two. For a 4-bit/pixel image, only the first step, the division of each pixel value by 4, need be altered. Special purpose hardware can shift each nibble within a byte, but an efficient implementation on a general purpose machine requires a table lookup, Again, one can use 16 consecutive bits (4 pixels in this case) as an index into a table. The contents of the table entry are 16 bits that represent each of the four pixel values right-shifted by two bits. Special Hardware Configuration As discussed above, 2x2 reductions require a first logical operation between rows followed by a second, possibly different, logical operation between columns. Moreover, some threshold levels require two intermediate reduced images which are then combined. The table lookup technique for column operations can become cumbersome if it is desired to have a very wide pixelword. Either the table becomes enormous or one needs special techniques of looking up parts of the wide pixelword in multiple parallel tables. The latter, while clearly superior, does require some way to use portions of the data word as memory addresses, which may not otherwise be necessary. Fig. 10 is a logic schematic of specialized hardware for performing a logical operation between vertically adjacent 2Q-bit pixelwords and a pairwise bit reduction of the resulting 2Q-bit pixelword (bits 0 through 2Q-1). Although the drawing shows a 16-pixel word, the benefits of this hardware would become manifest for much longer pixelwords where the lookup table technique has become cumbersome. A 512-bit pixelword is contemplated, since a line of image would represent only a few pixelwords. The reduction of the two pixelwords occurs in two stages, designated 200 and 202. In the first stage, a vertically adjacent pair of pixelwords is read from a first memory 203, and the desired first logical operation is carried out between them. The desired second logical operation is then carried out between the resulting pixelword and a version of the pixelword that is shifted by one bit. This provides a processed pixelword having the bits of interest (valid bits) in every other bit position. In the second stage, the valid bits in the processed pixelword are extracted and compressed, and the result stored in a second memory 204. Memory 203 is preferably organized with a word size corresponding to the pixelword size. Memory 204 may be organized the same way, and may be part of the same physical device. The preferred implementation for stage 200 is an array of bit-slice processors 210, such as the IDT 49C402 processor, available from Integrated Device Technology. This specific processor 210 is a 16-bit wide device, each containing 64 shiftable registers. Thirty-two such devices would be suitable for a 512-bit pixelword. For simplification, a 16-bit system with four registers 205, 206, 207, and 208 is shown. Among the processor's operations are those that logically combine the contents of first and second registers, and store the result in the first. The apparatus has control and logical unit 212 and a data port 215, which is coupled to a data bus 217. Control unit 212 is coupled to a program memory 218, which may be separate from memories 203 and 204, or may be part of them. Second stage 202 includes first and second latched transceivers 220 and 222, each half as wide as the pixelword. Each transceiver has two ports, designated 220a and 220b for transceiver 220 and 222a and 222b for transceiver 222. Each transceiver is half as wide as the pixelword. Ports 220a and 222a are each coupled to the odd bits of data bus 217, which correspond to the bits of interest. Port 220b is coupled to bits 0 through (Q-1) of the data bus, while port 222b is coupled to bits Q through (2Q-1). The bus lines are pulled up by resistors 225 so that undriven lines are pulled high. Consider the case of a 2x2 reduction with LEVEL = 2. The sequence of operations requires that (a) a vertically adjacent pair of pixelwords be ANDed to form a single 2Q-bit pixelword, adjacent pairs of bits be ORed to form a Q-bit pixelword, and the result be stored; (b) the vertically adjacent pair of pixelwords be ORed, adjacent bits of the resultant 2Q-bit pixelword be ANDed, and the resultant Q-bit pixelword be stored; and (c) the two Q-bit pixelwords be ORed. To effect this, a pair of vertically adjacent pixelwords are read from first memory 203 onto data bus 217 and into registers 205 and 206. Registers 205 and 206 are ANDed and the result stored in registers 207 and 208. The content of register 208 is shifted one bit to the right, registers 207 and 208 are ORed, and the result is stored in register 208. Registers 205 and 206 are ORed, and the result stored in registers 206 and 207. The content of register 207 is right shifted by one bit, registers 206 and 207 are ANDed, and the result stored in register 207. At this point, register 207 contains the result of ORing the two pixelwords and ANDing pairs of adjacent bits, while register 208 contains the result of ANDing the pixelwords and ORing pairs of adjacent bits. However, registers 207 and 208 contain the valid bits in the odd bit positions 1, 3,... (2Q - 1). For a reduction with LEVEL = 2, registers 207 and 208 are ORed and the result is made available at processor data port 215 which is coupled to data bus 217. The odd bits of the data bus are latched into transceiver 220 through port 220a, resulting in a Q-bit pixelword with the valid bits in adjacent positions. Although this Q-bit entity could be read back onto the bus and transferred to memory 204, it is preferable to use both latches. Thus, two new pixelwords (horizontally adjacent to the first two) are processed at stage 200 as described above, the result is made available at processor data port 215, and is latched into transceiver 222 through port 222a. The contents of the two transceivers are then read out through ports 220b and 222b onto data bus 217 in order to provide a 2Q-bit pixelword that represents the reduction of four 2Q-bit pixelwords. The result is transferred to second memory 204. This overall sequence continues until all the pixelwords in the pair of rows has been processed. Once the pair of rows has been processed, subsequent pairs are similarly processed. As mentioned above each bit-slice processor has 64 registers. Accordingly, since memory accesses are more efficient in a block mode, faster operation is likely to result if 8 pairs of pixelwords are read from memory 203 in a block, processed as discussed above, stored in the processor's registers, and written to memory 204 in a block. Image enlargement is similar, but the steps are executed in the reverse order. First, the processor reads a pixelword and sends the left half through port 220b of transceiver 220. This is read onto the bus through port 220a. Only every other pixel in the resulting word on the bus will initially be valid, so the processor will need to validate all the pixels using a sequence of shifts and logic operations. Since resistors 225 pull up all the bus lines that are not driven, each undriven line, all the even bits in this case, will be 1's. This expanded pixelword, which alternates 1's with valid data, is read into two registers, the content of one register is shifted one place, and the registers are logically ANDed. Everywhere there was a 0 in an odd bit, there will be 00 in an even/odd pair. None of the other bits will be affected. This pixelword is then written to two vertically adjacent words in the expanded image. This process is repeated for the right half of the pixelword using the transceiver 222. The processor expands the entire row one pixelword at a time and the entire image one row at a time. Architectural Considerations The following is a brief discussion of some architectural issues, such as parallelism, pipelining, and stream processing, from the perspective of both speed and resource requirements for practical implementations. First, it should be evident that the algorithms given above lend themselves to parallelism, whereby many processors can independently perform thresholded reduction on parts of the image, such as bands of a given number of scanlines. If I/O bandwidth is not a limiting factor, then processing time scales inversely with the number of processors involved. Second, it should be noted that for nxn thresholded reduction, it is only necessary to process n lines at a time, and for expansion, only one line need be stored in a buffer. For reduction, the intermediate image (full width, 1/n times the original number of lines) need not be generated, because each line of the intermediate image is immediately converted to a reduced width line of the reduced image. Using special purpose hardware, the row and "column" operations can be pipelined: while the column operations proceed on a line, the operation on the next set of rows can execute in parallel. Many of the thresholded reductions require generation of multiple reduced images. For example, for 2x2 reduction with either LEVEL = 2 or LEVEL = 3, two reduced images must be produced, and the thresholded image is derived from an AND or an OR of these two images. Again, such reduced images need not be stored. It is only necessary to produce one line of each reduced image, and then apply the appropriate logical operation to those two lines. From the preceding observations, it follows that the image can be reduced, for whatever threshold is desired, by a streaming process that requires little intermediate storage. Sets of two or more lines of the original image are input, and single lines of the reduced image are produced. This process can be cascaded. For example, using n stages of a 2x2 reduction, after 2 n lines of the original image have been processed by the first stage, a single line of the 2 n -fold reduced image is output from the n th stage. Because of the independence of the stages in the cascade, a different threshold could be chosen for each stage. Fig. 11 shows flowcharts illustrating an alternative way of implementing thresholded reductions. A 2x2 → 1 thresholded reduction with LEVEL = 1 may be implemented by dilating (step 300) with a 2x2 SE 302, followed by subsampling (step 305), taking only the upper left pixel in each 2x2 tile of the resulting image. Likewise, the 2x2 → 1 thresholded reduction with LEVEL = 4 can be implemented by eroding (step 310) with a 2x2 SE 312, followed by subsampling (step 315), taking only the upper left pixel in each 2x2 tile of the image. SE 302 is a 2x2 solid SE having its center position in the lower right corner; SE 312 is a 2x2 solid SE having its center position in the upper left corner. Another way to perform the LEVEL = 1 reduction is by dilating (step 320) with a 1x2 horizontal SE 322, dilating (step 325) with a 2x1 vertical SE 327, and then subsampling (step 328), taking only the upper left pixel in each 2x2 tile of the image. Likewise, a LEVEL = 4 reduction can be performed by eroding (step 330) with a 1x2 horizontal SE 332, eroding with a 2x1 vertical SE 337, and then subsampling (step 338), taking only the upper left pixel in each 2x2 tile. The horizontal and vertical SE's for the LEVEL = 1 reduction have their center positions in the right and bottom positions while those for the LEVEL =4 reduction have their center positions in the left and upper pixel locations. These distinctions are only necessary because of the specific definitions of dilation and erosion, which are taken from R.M. Haralick, S.R. Sternberg, and X. Zhuang "Image Analysis Using Mathematical Morphology", IEEE Transactions on Pattern Analysis and Machine Intelligence, Volume PAMI-9, pages 532-550, July, 1987. The 2x2 → 1 reduction with threshold LEVEL = 2 is a bit more complicated because it requires both dilations (OR's) and erosions (AND's). It is performed by making a first intermediate image by dilating with SE 322 and eroding with SE 337; making a second intermediate image by eroding with SE 332 and then dilating with SE 327; making a third intermediate image by ORing the first and second intermediate images; and subsampling the third intermediate image taking only the upper left pixel in each 2x2 tiling of the image. Similarly, the 2x2 reduction with threshold LEVEL=3 is obtained in the same manners for LEVEL = 2 except that in the third step, the first and second intermediate images are ANDed. Implementation on a general purpose computer is efficient, because it involves only a sequence of full image logical raster operations, followed by a single subsampling operation. The full image raster operations are efficiently implemented in hardware or software, and the subsampling operation can be performed by a fast table lookup on, for example, 16 image bits at a time. For the subsampling step for 2x2 = > 1 reduction, only every other row needs to be subsampled (i.e., row(0), row(2), etc.). The bits in each sampled row can be taken, for example, 16 at a time, and each such 16 bit word can be used as an index into a 2 16- entry table, whose contents are the 8 bits consisting bits 0, 2,... 14 the 16-bit word. For the subsampling table for 2x2 = > 1 reduction with a 16-bit index, the 8-bit table values t(i) are generated by: t(0) = 0; i = 1; for (d = 0, ...,7) i0 = 2**2d; /* start value of i */ t0 = 2**d; /* increment value of t */ for (r = 1,..., 3) if (r < 2) tlnc = 0; else tlnc = t0; for(k = 0,...,i0 - 1) t(i) = t(k) + tlnc; i = i + 1; In a similar manner, the general thresholded reductions (m x n) can be constructed by the following sequence: (1) morphological operations on the original image, producing a set of intermediate images, (2) logical operations carried out on the intermediate images, producing a final full-size image, and (3) an m x n subsampling of the final full- sized image to produce the reduced image. For the general case, the SE's used in the morphological operations are of dimension (m x 1) and (1 x n). The (m x n) subsampling is performed by taking every n-th bit (bit(0), bit(n, ..) on every m-th row (rows 0, m, 2m, ...). The most efficient implementation in software is by table lookup. The embodiments of the present invention described above provide efficient techniques for performing thresholded reductions.

Claims: A method for reducing an image composed of pixelwords by operating on consecutive groups of m vertically adjacent pixelwords, each consecutive group of m vertically adjacent pixelwords including subregions, each subregion having m pixels down and n pixels across, each subregion to be mapped to a single pixel in the reduced image, comprising : performing logical operations to combine a consecutive group of m vertically adjacent pixelwords into a resultant pixelword with valid bits, each valid bit indicating whether the number of ON pixels in one of the subregions is greater than or equal to a threshold level, the logical operations including: at least one logical operation that combines bits in a consecutive group of vertically adjacent pixelwords; and at least one operation that combines a consecutive group of horizontally adjacent bits within a pixelword; the operation including shifting the pixelword to obtain a shifted version and performing a logical operation on the pixelword and the shifted version to combine horizontally adjacent bits; and extracting the valid bits from the resultant pixelword. A method as in claim 1 in which m=n=2. A method as in claim 2 in which the threshold level is 2. A method as in claim 3 in which performing logical operations includes: ANDing two vertically adjacent pixelwords to form a resulting pixelword; ORing the two vertically adjacent pixelwords to form a resulting pixelword; shifting each resulting pixelword to obtain a shifted version; ORing each of the resulting pixelwords and its shifted version to obtain a processed pixelword, each of the processed pixelwords including valid bits in every other bit position; and ORing the processed pixelwords. A method for reducing an image composed of 2Q-bit pixelwords by performing a logical operation between vertically adjacent pixelwords to obtain and then pairwise bit reduce a resultant pixelword, comprising the steps of: (a) reading a pair of vertically adjacent pixelwords from a first memory (203) in which the image is stored onto a data bus (217) and into a first register (205) and a second register (206); (b) ANDing the first and second registers and storing the results in a third register (207) and a fourth register (208); (c) shifting the content of the fourth register one bit to the right; (d) ORing the third and fourth registers and storing the results in the fourth register, so that the fourth register contains the results of ANDing the pixelwords and ORing pairs of adjacent bits with the valid bits in the odd bit position; (e) ORing the first and second registers and storing the results in the second and third registers; (f) shifting the content of the third register one bit to the right; (g) ANDing the second and third registers and storing the result in the third register, so that the third register contains the result of ORing the two pixelwords and the ANDing pairs of adjacent bits with the valid bits in the odd bit position; (h) effecting the reduction by ORing the third and fourth registers and providing the result to a data port (215) which is coupled to the data bus (217) for access thereto; and (i) extracting the valid bits from the result. The method as claimed in claim 5, wherein the odd bits of the data bus are latched into a first transceiver (220) through a first port (220a) thereof, so that a Q-bit pixelword is formed with the valid bits in adjacent positions; and reading the Q-bit pixelword back onto the data bus and transferring the Q-bit pixelword into a second memory (204). The method as claimed in claim 5, wherein the odd bits of the data bus are latched into a first transceiver (220) through a first port (220a) thereof, so that a Q-bit pixelword is formed with the valid bits in adjacent positions; reading a pair of horizontally adjacent pixelwords from the first memory onto the data bus and into the first register and the second register; repeating steps (b) through (h) for the horizontally adjacent pixelwords; latching the result of step (h) for the horizontally adjacent pixelwords into a second transceiver (222) through a first port (222a) thereof; reading out the contents of the first and second transceivers through respective second ports (220b, 222b) onto the data bus (217) thereby providing a 2Q-bit pixelword that represents the reduction of four 2Q-bit pixelwords; transferring the reduced four 2Q-bit pixelwords to a second memory (204); and repeating the above steps for subsequent pairs of pixelwords until all of the image has been reduced. Apparatus for reducing an image composed of 2Q-bit pixelwords by performing a logical operation between vertically adjacent pixelwords to obtain and then pairwise bit reduce a resultant pixelword, characterized by: a data bus (217) with bits 0 through (Q-1) and bits Q through (2Q-1); a first memory (203) and a second memory (204), each connected to the data bus; a processor (210) including a plurality of registers (205-208) and having a 2Q-bit data port (215) coupled to the data bus; first and second Q-bit latched transceivers (220, 222), each with first and second ports (220a, 220b, 222a, 222b), the first ports (220a, 222a) of both latched transceivers being coupled to the same set of alternating bit positions of the data bus, the second port (220b) of the first latched transceiver being coupled to bits 0 through (Q-1) of the data bus, the second port (222b) of the second latched transceiver being coupled to bits Q through (2Q-1) of the data bus; and a control unit (212) for controlling the first and second memories and the processor, the control unit controlling the first and second memories and the processor; to read pairs of vertically adjacent pixelwords from the first memory into two of the registers (205, 206); to perform logical operations to combine each pair of vertically adjacent pixelwords into a resultant pixelword with valid bits in every other bit position, each valid bit indicating whether a 2 × 2 array of pixels is greater than or equal to a threshold level; the logical operations including: at least one logical operation that combines bits in the pair of vertically adjacent pixelwords; and at least one operation that combines horizontally adjacent bits within a pixelword stored in two of the registers (207, 208; 206, 207); the operation including shifting the pixelword in one of the registers (208; 207) to obtain a shifted version and performing a logical operation on the pixelword and the shifted version to combine horizontally adjacent bits; and to use the first and second latched transceivers to extract the valid bits from the resultant pixelwords obtained from two pairs of vertically adjacent pixelwords for storage in the second memory.

Inventors: BLOOMBERG DAN S, DAVIES DANIEL, BLOOMBERG, DAN S., DAVIES, DANIEL
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1990
Main classification: G06T3
IPC codes: G06T3