ELECTRONIC SYSTEMS DISPOSED IN A HIGH FORCE ENVIRONMENT

Abstract: A high acceleration object includes an electronic system which is operable at accelerations in excess of 20,000g. Connections between integrated circuit chips (130) and other portions of the electronic system are provided by metallization patterns (168) disposed on polymer dielectric layers (164) which are self-supporting across gaps (143) between components. A high density interconnect structure is disposed within the cavity of a hermetically sealed package (140).

Description: ELECTRONIC SYSTEMS DISPOSED IN A HIGH FORCE ENVIRONMENT Background of the Invention Field of the Invention The present invention relates to the field of electronic systems, and more particularly, to high acceleration objects containing electronic systems. Background, iπfoππatigπ Modern electronic systems normally include integrated circuits. Integrated circuits themselves are substantially unaffected by high accelerations such as 20,000g to 100,000g or higher, where "g" is the force of gravity, since they are monolithic, relatively small, low mass structures. Consequently, such integrated circuits themselves are suitable for use in h_.gh acceleration objec such as rockets, systems which are launched as projectiles and so forth. Integrated circuits are normally connected into a larger electronic system by packaging them in packa which help to protect the integrated circuit and facilitat connecting them into the larger electronic system. Normal the integrated circuit is connected to package conductors wire bonds and after mounting of the integrated circuit, t package is hermetically sealed by a metallic lid which spa the cavity in which the integrated circuit and its wire bo are disposed. Unfortunately, when such packages are exposed t accelerations on the order of 20,000g or more, the wire b collapse against the integrated circuit and the package ( lid is also deformed inward into contact with the wire bo and/or contact pads) creating sh-r-t circuits and breaking some of the wires. Both of these effects disable the integrated circuit and the electronic system in which it connected. Consequently, for use in high acceleration environments, an electronic system must be free of wire bo which can be damaged by that high acceleration. There is a need in high acceleration objects for 5 electronic systems which can withstand high accelerations, both while they are not in operation and while they are in active operation. Objects of the Invention Accordingly, a primary object of the present 10 invention is to provide a high acceleration object with an electronic system which can survive the high accelerations the object is intended to undergo. Another object is to provide .an electronic syste which is fabricated at all levels in a manner to withstand 15 high accelerations. Still another object of the invention is to prov a high acceleration object with an electronic system which free of wire bonds. Summary of the Invention 20 The above and other objects which will become apparent from the specification as a whole, including the drawings, are accomplished in accordance with one embodime of the present invention by interconnecting integrated circuits in a high acceleration object with a high density 25 interconnect system in which a dielectric layer is dispose over the integrated circuits and any gaps between them and supports conductors which interconnect the integrated circuits of the system in a manner which is immune to acceleration induced damage for accelerations in the range 30 from 20,000g to 100,000g and higher. Brief Description of the Drawings The subject matter which is regarded as the invention is particularly pointed out and distinctly claime in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the followi description taken in connection with the accompanying drawings in which: Figure 1 is a perspective cross-section view of portion of a prior art electronic system disposed in a mobi object; Figure 2 illustrates the prior art system of Fig 1 after exposure to high acceleration or shock in the upwar direction; Figure 3 is a perspective, cross-section partial cut away view of a high acceleration object including an electronic system in accordance with the present invention; Figure 4 is a cross-section view of the Figure 3 structure during high acceleration; Figures 5-7 illustrate steps in the process of fabricating the structure of Figure 4; and Figure 8 is a plan view of a modified embodiment the Figure 4 structure. Detailed Description In Figure 1, an object 8, including an electroni system 10, comprises a structural portion 20 of the object an integrated circuit 30 and a package 40 in which the integrated circuit is packaged. The integrated circuit 30 has a plurality of contact pads 32 disposed on an upper surface thereof and a back metallization 34 disposed on a back or lower surface thereof. This integrated circuit is mounted in a package 40 by a solder or adhesive layer 38. The package 40 includes a shoulder or plateau 42 on which ar disposed conductive runs or lands 44 to which the contact pads 32 of the integrated circuit are connected by wire bond 50. The package 40 is a typical prior art package designed 5 for use with wire bonds to connect the integrated circuit to the package conductors. Typically, the recess 45 in which the chip 30 is disposed is 400 mils (10.2 mm) square and the chip is 350 x 370 mils (8.9 x 9.4 mm). Thus, where the chip 30 is centered in the recess 45, a gap of between 15 and 25 10 mils (0.38-0.63 mm) exists between the edge of the chip 30 .and the shoulder 42 of the package. This gap is easily bridged by the wire bonds 50. It will be understood that the manner in which th package contact lands 44 extend to the outside of the packag 15 and the type of lead provided on the outside of the package varies in accordance with the type of package. As is well known in the integrated circuit art, the term "wire bonds" i a term of art referring to fine wires which have one end solderless bonded to a contact pad of one portion of an 20 electronic structure and the other end solderless bonded to contact pad of another portion of the structure. "Wire bonds" are sometime referred to as "nail head bonds" because of an enlargement of the wire at the end thereof at which th first bond of a wire bond is formed or wedge bonds in which 25 the wire is crushed in spots to form the solderless bond. "Solderless bonded" means without solder and usually involv thermocompression bonding or ultrasonic bonding. The wire bond wires 50 for low power integrated circuits are typical 1 mil (25 microns) in diameter and 0.3-0.4 inch (0.76-1.27 30 cm) long. These are delicate wires which are adequate for use in normal fixed or low acceleration objects. However, when subjected to shock or high accelerations, the wire bon wires 50 are easily bent or deflected. Object 8 is illustrated in Figure 2 following exposure to a high acceleration (greater than about 30,000 in the positive Z-direction in Figure 2. As can be seen, of the wire bond wires 50 within the package 40 have been bent down in the negative Z-direction in a manner which creates short circuits and breaks some of the wires 50 as 54 where they extend across the gap 43 between the integra circuit 30 and the package shoulder 42. Even in an absenc of the gap 43, short circuits would result from the collap of the wire bond wires. Further, the package lid 49 has b stretched and deformed downward in the figure in a manner which it contacts and shorts contact pads 32 of the integrated circuit and the bond wires 50. These broken wi and short circuits disable the electronic system 10 or par of it. A high acceleration in the XY plane bends the bo wires substantially into the XY plane and causes failures to bond wire breakage, bond wires contacting contact pads from which they should be isolated, and so forth. Similar a high acceleration in the negative Z direction stretches bond wires upward breaking or dislodging some of them. Th lid also bows outward. Thus, failure modes are present in wire bond systems in response to high acceleration in any direction, although the acceleration at which failures fir occur may vary with the orientation of the package relati to the direction of acceleration. For these reasons, wire bonding is not an acceptable connection technique for electronic systems for use in high acceleration environme In Figure 3, a high acceleration object in accordance with the present invention including electroni circuitry 110 therein is shown generally at 108. In Figu 3, reference numerals in the one hundreds are utilized. Those reference numerals ending in the same two digits as reference numerals in Figures 1 and 2 identify correspond structures and may not be discussed at this point. For th function or purpose of those structures not discussed at t point, the reader is referred to the earlier discussion of the similar structures in Figures 1 and 2. The package 14 is like the package 40, however, the method and structure which is used to connect the integrated circuit contact pa 132 to the package contact lands 144 is vastly different. high density interconnect system such as that disclosed in U.S. Patent 4,783,695, entitled "Multichip Integrated Circ Packaging Configuration and Method" issued in the name of C.W. Eichelberger et al. is used to connect the chip conta pads 132 to the package lands 144. A method of forming th structure is disclosed in copending application Serial No. 240,367, filed August 30, 1988, as a continuation of application Serial No. 912,458 filed September 26, 1986, a entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer". Bo of these documents are incorporated herein by reference. In Figure 3, a polymer dielectric layer 164 is disposed over the integrated circuit chip 130 and over the shoulder 142 of the package 140. This dielectric layer bridges or spans the gap 143 between the integrated circui and the shoulder 142 of the package. The dielectric layer covers the contact pads 132 on the integrated circuit and least the portion of the contact lands 144 nearest the integrated circuit. A via hole 166 is provided in the dielectric layer 164 at each location where it is desired have one of the conductors 168 which are disposed on the upper surface of the dielectric layer 164 make electrical contact to an underlying chip contact pad 132 or package contact land 144. In Figure 3, only a single dielectric layer 164 and a single layer of conductors 168 is illustr for clarity in the drawing. Where necessary, or desirabl additional dielectric layers may be disposed over the lay 164 and additional conductor layers may be disposed over those dielectric layers. Connections are made between subsequent conductor layers and the layer 168 through via holes in the overlying dielectric layer. A block 170 of solid dielectric material is disposed between the lid 149 a the high density interconnect system disposed on integrated circuit 130. The dielectric layer 164 bridges the gap 143 , between the edge of the semiconductor chip 130 and the package shoulder 142 and supports the conductor 168 over th gap. Typically, the dielectric layer 164 is a KAPTC2.® polyimide film which is available from DuPont de Nemours Company and is preferably 1-2 mils (25-50 microns) thick. The conductors 168 are preferably copper films 0.1-0.5 mils (2-10 microns), thick (ideally about 5 microns thick) with a adhesion promotion layer such as titanium or tungsten adjacent the dielectric film 164. Such a conductor 1 mil ( microns) wide and and 25 mils (635 microns) long has a mass of only about 0.73 x 10~ 6 grams. As such, the force on suc conductor undergoing 100,000g acceleration is only about 6. pounds per square inch (psi) . That force is sufficient to deflect the dielectric film 164 and conductor 168 in the general manner illustrated in Figure 4 in the vicinity of t gap 143. This deflection is within the elastic tolerance o both the dielectric film 164 and the ductile copper conduct 168 (of about 30%) . Consequently, the integrated circuit 1 and its connection to the package contact lands 14.4 are not adversely affected by 100,000g accelerations. Unfortunate the same cannot be said .for the package lid 149, which in prior art, typically has an unsupported span of 1 to 2 inc (25-50 mm) , which for a steel package lid 10-20 mils thick results in a force in excess of 640 psi on the center of t lid at 100,000g acceleration. Consequently, in the absenc of dielectric block 170, the lid would deform in the same manner as illustrated in Figure 2. That deformation of the lid could result in short circuits between the lid and the conductors within the package in the absence of the dielectric block 170. To prevent this adverse effect, the solid dielectric block, layer or pad 170 disposed within the package between the chip and the lid should have sufficient strength to support (at least partially) the lid under high acceleration and to thereby ensure that even in the deformed state of the lid, the integrated circuit and the conductors thereon are electrically insulated from the lid. The dielectric block 170 should have a sufficient stiffness (durometer reading) to survive the acceleration and continue to hold the lid out of contact with the chip 130 and the wiring thereover. Since the connection structure is itself crush resistant, this ensures survival and continued operation of the electronic system 110 of which the integrated circuit 130 forms a part. A silicone rubber pad may be used as the solid dielectric buffer between the integrated circuit chip and the inside of the package lid provided a buffer polyimide layer is disposed between that silicone rubber pad and any exposed polyimide films of the packaging structure in order to isolate the package polyimide films from the silicone rubber pad. The silicone rubber pad helps to support the package lid 149 and ensures that even if the lid is severely deforme by acceleration, that lid does not come into contact with the conductors of the high density interconnect structure. This ensures, that even in a deformed state, the lid will not render the electronic system inoperative. The accelerations which the resulting object and its electronics can withstand can be maximized by tailoring the recess 145 to match the actual chip size, thereby minimizing the gap between the chip and the package shoulder or by filling the gap 145 with a dielectric material such as the ULTEM polyetherimide material discussed hereinafter as a adhesive for the KAPTON polyimide film. Either of these techniques reduces both the unsupported span across which th dielectric layer 164 extends and the mass of the dielectric layer and the conductors extending across this gap. It will be noted that in the Figure 3 and 4 structure, the dielectric layer 164 is recessed within the package below the sealing ring 148 of the package. The height of the sidewall portion 146 of the package in prior art packages, is typically 50-80 mils (1.25-2 mm) and is determined by the expected height to which the wire bond wires 50 of Figure 1 extend .above the shoulder 42 of that prior art package. This height or depth is substantially larger than is required with the high density interconnect system since the high density interconnect system provides a substantially planar connection structure. The method of fabricating the interconnect structure in the package 140 will now be discussed in connection with Figures 5-7. As illustrated and described in U.S. Patents 4,783,695 and patent application Serial No. 240,367, referre to above, a high density interconnect structure is preferabl formed on a flat substrate containing recesses for the integrated circuit chips whose depth is selected to dispose the upper surface of the integrated circuits in substantiall the same plane as the upper surface of the substrate on whi conductors are disposed. This facilitates the lamination o the first dielectric layer across the integrated circuit chips and the substrate. The substrate is preferably a ceramic such as alumina (AI2O3) . The polyimide film 164 cannot be a * , lied in the small cavity of this package using the specific techniques illustrated and described ir. he application Serial No. 240,367 referred to above. _.nis is because of the relative small surface area of the cavity and the relatively large height of the sidewall portion 146 of the package around th cavity. Attempts to apply the film 164 as part of a larger film result in tearing or separation of the polyimide film a result of exceeding its elastic limit or a failure of that film to come into proper contact with the chip 130. - In accordance with the present invention, this problem is overcome by cutting an individual piece of the polyimide film to fit within the cavity and applying the bonding pressure thereto via a high temperature elastic pressure block 167 (Figure 6) which may preferably be made o high temperature silicone rubber. In Figure 5, the chip 130 has been bonded to the bottom of the recess 145 in the package by use of an adhesi or solder 138, depending on the preferred bonding technique for the package in question. A glue layer 162A has been deposited on the upper surface of the chip 130, including i contact pads 132, and on the shoulder 142 and the contact lands 144 of the package 140 and at the bottom of the reces 145 between the chip and the package shoulder. This adhesi is preferably a polyetherimide available from General Electric Company under the trade name ULTEM 1000® and is deposited by spraying a solvent solution as taught in U.S. Patent 4,783,695 entitled, "Multichip Integrated Circuit Packaging Configuration and Method" and U.S. patent application Serial No. 312,536 filed February 17, 1989, as continuation-in-part of application Serial No. 156,318, fil February 16, 1988, and entitled, "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondab Laminate". The spray solution preferably comprises 10% by weight ULTEM 1000®, 50% by weight acetophenone and 40% by weight ethylene chloride. This solution is sprayed onto t integrated circuit and the package shoulder while masking t sealing ring portion 148 of the package. Consequently, the glue layer 162A is typically also disposed at the bottom of the recess 145 between the chip 130 and the shoulder 142 of the package and may also be disposed on the sidewalls of th cavity 145 and the chip 130. The glue in the bottom of thi recess does not present any problems, but also is not involved in the bonding of the dielectric layer 164. A pie of a polyimide film 164 which may preferably be KAPTON® is cut to fit within the sealing ring 148 and to cover substantially all of the shoulder 142 of the package. A layer 162B of the same glue is applied to what will be the lower side of this polyimide film 164 and dried. In both cases, the drying may preferably be done at a temperature o 160"C for a period of approximately 5 minutes and then at temperature of 290 * C for approximately 5 minutes. This drying is to remove the acetophenone and methylene chlorid solvent in which the desired ULTEM 1000® is dissolved for spray application. After both glue layers are dried, the polyimide layer is inserted in the cavity of the package i preparation for bonding this polyimide film to the integra circuit chip 130 and the shoulder portion 142 of the packa In order to bond the film 164 in place, a high temperature silicone rubber pressure pad 167 which has bee cut to fit the cavity of the package is placed over the fi 164 and a buffer polyimide film 165 (Figure 6) . The buffe layer 165 of polyimide film is included between the polyim film layer 164 and the silicone rubber pressure pad 167 because silicone rubber is known to poison polyimide films high temperatures (above about 200 * C) . This poisoning is believed to be due to a reaction between the polyimide fil and the silicone rubber. The buffer polyimide film layer protects the package polyimide film 164 from contact with silicone rubber .and thereby prevents deterioration of the package polyimide film 164. The structure is placed in a bonding furnace whi is evacuated to eliminate air from within the gap between integrated circuit and the package shoulder. The film 164 i bonded to the device and package by slowly heating the structure to the vicinity of 250 * C and by applying a pressur of 30 psi to the upper surface of the silicone rubber pad 16 by use of bladder membrane 172. The heating is stopped whil the pressure is maintained until the structure—eeols to the vicinity of 100"C. Under these conditions, the adhesive layers 162A and 162B merge to form a single adhesive layer where they are disposed in contact with each other and they permanently bond the polyimide layer 164 to the chip 130 and package 140. If it is desired to remove that polyimide film 164 at a later time, it may be removed by heating the structure to the vicinity of 250 * C and lifting the polyimide film off the chip and package. A residue of the ULTEM® polyetherimide layer is left on the chip and package after such removal, but may be removed by appropriate solvents suc as a mixture of acetophenone and methylene chloride. Once the package, chip and dielectric layer 164 have cooled, the silicone rubber pressure pad 167 and the buffer polyimide film 165 are removed from the package. Interconnections between the chip pads and the package contact lands are then formed in the standard method for the high density interconnect system as disclosed in U.S. Patent 4,783,695 referred to above. In Figure 7, the chip and package are illustrated after bonding of the polymer film to the chip and package an removal of the silicon rubber pad 167 and the buffer polyimide layer 165. The two adhesive layers 162A and 162B have merged into a single layer 162. To complete the package, conductors 168 are forme on the dielectric layer, the insulating pad 170 is disposed in the package cavity on top of the high density interconne structure and the package is sealed by lid 149 (Figure 3) . The completed package 140 and the remainder of the electron system 110 are then mounted in the object 108 on structural member 120. Thus far, the discussion of this structure has be in terms of a single integrated circuit disposed in a packa and Figures 1-7 each illustrate only a single integrated circuit for clarity, This technique and structure is equal applicable to multiple integrated circuits 230 packaged in single package 240 as shown in Figure 8 in plan view with t cover removed. The integrated circuits 230 may preferably placed as close together as possible, essentially edge-to- edge. This provides several advantages. First, the connections between chips are kept as short as possible. Second, the gap which must be spanned by the dielectric lay 264 (not shown) is minimized, thereby maximizing the acceleration forces which the dielectric layer 264 and the conductors 268 thereon can survive. The dielectric layer 2 is preferably applied in the same manner as discussed above and the interconnection metallization is formed in the standard way. As can be seen, the integrated circuits 230 are connected to contact lands 244 of package 240 and to ea other by conductors 268 disposed on the dielectric layer 26 (not shown) . The conductors 268 make contact with the underlying conductors through via holes in the dielectric layer. Additional dielectric and metallization layers may applied if needed because of the complexity of the interconnections among the integrated circuit and the pack contact lands. As can be seen, the high acceleration object 110 free of wire bonds. As a result, the electronic system ca operate continuously from a period where the object 110 is rest, through a high acceleration of up to 100,000g or mor through a period of constant velocity operation, through a period of deceleration and into a second period of at rest operation. It is preferred to mount the electronic system so that its greatest acceleration is in the upward (positive Z- direction) in the figures. The high density interconnect system of connections is substantially insensitive to the direction of acceleration. However, the bond holding the chip to the package and the semiconductor chip itself may be fractured by excessive accelerations in the XY plane or in the negative Z-direction. Further, the package itself may come loose from its mountings under such accelerations. The glue 162A at the bottom of the gap 143 can aid in retaining the chip in place. Filling the gaps with glue further secures the chips. Thus, the overall structure of the object itself and the orientation and mounting of the electronic system as a whole and its individual components themselves must be carefully designed to withstand the expected magnitude and direction(s) of accelerations which the electronic system must survive. With an electronic system in accordance with these teachings, that design becomes possible whereas with the wire bond connected integrated circuits of the prior art, that design is not possible. The package and sidewall 146 and the lid 149 may be omitted if a hermetic seal is not required. In that case, the circuit is packaged essentially in the manner taught in U.S. Patent 4,783,695. The overall electronic system includes appropriate voltage sources such as solar cells, batteries, fuel cells or capacitors which store or provide sufficient charge to operate the. electronic system during acceleration and subsequent thereto. For some systems, the desired period of operation is short enough that a battery or other power supply may be used as a source of pre-acceleration power and ceramic or other acceleration-surviving capacitors may be used to provide the power to continue system operation during and after acceleration where the battery or initial primary power source fails during acceleration. While the invention has been described in detail herein in accord with certain preferred embodiments thereof, many modifications and chr-.ges therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims: WHAT IS CLAIMED IS: 1. An electronic system disposed in an environment where it is expected to experience unbalanced forces in excess of 20,000g, said electronic system comprising: a substrate; an integrated circuit bonded to said substrate and including a first conductor disposed on a first surface thereof; a second conductor laterally spaced from said integrated circuit; a polymer dielectric layer disposed over said firs and second conductors, said dielectric layer having first an second via holes therein, said first via hole being disposed in alignment with said first conductor and said second via hole being disposed in alignment with said second conductor; a third conductor disposed on said dielectric laye and in electrical contact with said first conductor in said first via hole and in electrical contact with said second conductor in said second via hole. 2. The system recited in claim 1 wherein: said second conductor comprises a package pin. 3. The system recited in claim 1 wherein said second conductor is disposed on said substrate. 4. The system recited in claim 1 wherein: said substrate is mounted with said first surface of said integrated circuit oriented substantially perpendicular to the expected direction of maximum force on said electronic system. 5. The system recited in claim 4 wherein: said substrate is mounted with said first surface facing in the direction of acceleration whereby, during said acceleration, the acceleration force will push said dielectric layer against said integrated circuit. 6. The syster recited in claim 1 wherein: sa.. first and -cond conductors are disposed in substantially a common plane. 7. The system recited in claim 1 wherein: there is a gap between said first surface of said i ntegrated circuit and said second conductor; and said dielectric layer and said third conductor sp 8- The system recited in claim 7 wherein: said dielectric layer is unsupported where it spa said gap, 9. The system recited in claim 8 wherein: said dielectric layer comprises a polyimide. 10. The system recited in claim 9 wherein: portion of said dielectric layer is disposed ov sa i d i ntegrated circuit and comprises a polyetherimide. 11. The system recited in claim 8 wherein said conductor comprises copper. 12. The system recited in claim 1 further comprising: a hermetic enclosure enclosing said integrated c i rcuit and said substrate, said enclosure including a wall spanning said integrated circuit ; and a solid dielectric disposed within said enclosure between said dielectric layer and the spanning wall of said enclosure. 13. The system recited in claim 12 wherein: said spanning wall of said enclosure comprises a metallic lid. 14. The system recited in claim 1 further comprising: a fourth con d uctor disposed on said fi rst surface of said integrated circuit; a second integrated circuit bonded to said substrate and including a fifth conductor disposed on a firs surface thereof, said polymer dielectric layer also being disposed over said fourth and fifth conductors, and having third and fourth via holes therein, respectively, disposed i alignment with said fifth and fourth conductors; a sixth conductor disposed on said dielectric laye and in electrical contact with said fourth conductor in said fourth via hole and in electrical contact with said fifth conductor in said third via hole. 15. The system recited in claim 1 wherein: said system is expected to experience forces in excess of 50,000g. 16. The system recited in claim 1 wherein: said system is expected to experience forces in excess of 100,000g. 17. A high acceleration object intended for use accelerations in excess of 20,000g including electronic circuitry, said electronic circuitry comprising: a substrate; an integrated circuit bonded to said substrate an including a first conductor disposed on a first surface thereof; a second conductor laterally spaced from said integrated circuit; a polymer dielectric layer disposed over said fir surface of said integrated circuit and said second conductor, said dielectric layer having first and second via holes therein, said first via hole being disposed in alignment with said first conductor and said second via hol being disposed in alignment with said second conductor; a third conductor disposed on said dielectric lay and in electrical contact with said first and second conductors. 18. An electronic system intended for use at accelerations in excess of 20,000g comprising: a substantially rigid surface supporting conductiv runs, said surface having a gap therein; a polymer dielectric layer spanning said gap; a conductor which spans said gap and is disposed o said dielectric layer where it spans said gap; said dielectric layer and said conductor being sufficiently flexible to bend in response to accelerations in excess of 20,000g without breaking. 19. The system recited in claim 18 comprising an integrated circuit and additional circuitry; said ' conductor connecting between said integrated circuit and said additional circuitry. 20. An electronic system designed to withstand an remain operational in the presence of shocks in excess of 20,000g comprising: a substrate; an integrated circuit bonded to said substrate and including a first conductor disposed on a first surface thereof; said system including a second conductor which is laterally spaced from said integrated circuit; a polymer dielectric layer disposed over said firs surface of said integrated circuit and a portion of said second conductor, said dielectric layer having first and second via holes therein, said first via hole being disposed in alignment with said first conductor and said secc.d via hole being disposed in alignment with said second conductor; a third conductor disposed on said dielectric laye and in electrical contact with said first and second conductors. 21. The electronic system recited in claim 20: having power applied thereto; having signals applied thereto or emanating therefrom; and undergoing an acceleration in excess of 30,000g while continuing to operate. 22. The electronic system recited in claim 20 wherein: said system is designed to withstand shocks in excess of 100,000g. 23. A high density interconnect structure comprising: a package having a cavity therein including a recess in the bottom of the cavity in which a semiconductor chip in which a semiconductor chip is disposed, said package including contact lands disposed in said cavity adjacent said recess; a polymer dielectric layer disposed on the exposed major surface of said semiconductor chip, extending across any gap between said chip and said contact lands and being disposed on said contact lands; a plurality of via holes in said dielectric layer disposed in alignment with selected ones of said contact pads of said semiconductor chip and said contact lands of said package; a plurality of conductor interconnecting selected ones of said chip contact pads and said package contact lands and extending into appropriate ones of said via holes to provide those connections; said polymer dielectric film and said interconnecting conductor pattern being recessed within the cavity of said package. 24. The structure recited in claim 23 further comprising a package lid bonded to said package base to hermetically enclose said semiconductor chip, said dielectri layer and said interconnecting metallization within said package . 25. in a packaged integrated circuit of the type in which the integrated circuit is sealed in a cavity by a metallic lid which spans that cavity, the improvement comprising: a solid dielectric block disposed within said cavity between said lid and said integrated circuit.

Inventors: EICHELBERGER CHARLES WILLIAM, WOJNAROWSKI ROBERT JOHN, EICHELBERGER, CHARLES, WILLIAM, WOJNAROWSKI, ROBERT, JOHN
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1990
Main classification: H01L23
IPC codes: H01L21, H01L23