A digital modulating circuit

Abstract: This invention relates to a digital modulating method used for recording PCM audio signal, computer data, and etc. on a recording medium such as optical disc. The digital modulating method is constructed so that the minimum length between transition could be the maximum in encoding M bits into N bits (M < N), and can generate clocks with simple circuit arrangement by satisfying the relationship N = α M, where α is an integer equal to or larger than 2. Further, by converting a predetermined unit of input data into a first code signal according to substantially the same conversion rule and selectively adding coupling bits of different bit number to each junction between a first code signal and an adjacent such signal, the digital modulating method is adaptable for various transmission systems with a simple arrangement.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a digital modulating method used for recording a PCM audio signal, digital data used in a computer, etc. on an optical disc or other recording medium. Description of the Prior Art In recording digital data on a magnetic tape, optical disc or other recording medium, the digital data to be recorded is modulated. This modulation is called a digital modulation or a channel coding. There have been proposed various methods of digital modulation. Parameters for evaluation of digital modulating methods are their window margin Tw, minimum length between transition Tmin, maximum length between transition Tmax, recording density DR (density ratio), and so on. Digital modulating methods having been proposed heretofore are directed to removal of a DC component in a frequency spectrum of a modulated signal (so-called DC free) and an increase of the minimum length between transition Tmin or an increase of the window margin Tw. For example, EFM (eight to fourteen modulation) employed in a CD (compact disc) converts 8 bits as data bits into 14 bits as channel bits, as described in Japanese Patent Laid Open Publication No. Sho 57-48848 and in corresponding GB-A-2 083 222 and FR-A-2 486 740. Selected are bit patterns of 14 bits which include two or more "0"s (logic 0) sandwiched between "1" (logic 1) and "1". Bit patterns which satisfy this condition are 277 pieces among (2¹⁴ = 16,384) pieces, and these 277 pieces include 267 pieces whose Tmax's do not exceed a predetermined value. 256 picese among these 267 patterns are associated with 256 pieces of 8-bit data bits by one to one. When indicating the data bit interval by Tb, the above-mentioned EFM has the parameters indicated below: Tw = (8/17)Tb Tmin = 3Tw = (24/17)Tb Tmax = 11Tw = (88/17)Tb DR = (24/17) Respective symbols of 14 bits satisfy the condition that two or more "0"s are placed between "1" and "1". In order to satisfy this condition also between symbols, 3-bit coupling bits are used. Prepared are four such coupling bits (000), (100), (010) and (001). One of four coupling bits is determined so as to satisfy the parameters Tmin, Tmax, etc. and to minimize DSV (digital sum value; where the summation is done regarding high levels as +1 and low levels as -1) of data after modulation. By deciding the coupling bit according to this rule, low frequency components of the modulated data can be reduced. Therefore, data bits in the form of 8 bits are finally converted into channel bits in the form of 17 bits. PHILIPS TECHNICAL REVIEW, vol.40, no.6, 1982, Eindhoven, NL, pages 157-165, J.P.J. Heemskerk et al 'Compact Disc: system aspects and modulation' a CD-ROM system is disclosed. A EFM modulation system is discussed, which helps to produce the desired high information density on the disc. In EFM,the 8 data bit are converted into 14 channel bits with a minimum run length of 3 and a maximum run length of 11 channel bits. This means at least 2 and at the most 10 successive "0"s are in the channel bits. 3 merging bits are coupled to the channel bits to ensure that the run-length conditions continue to be satisfied to give sufficient freedom for effective suppression of the low-frequency content. IEEE SPECTRUM, vol.23, no.4, April 1986, New York, US, pages 44-49, P.PIN-SHAN CHEN 'The compact disk ROM: how it works' discloses an 8-to-14-bit modulation (EFM) used in CD-ROM systems. A modulation schemes makes sure that logical "0"s are added where necessary between logical "1"s. Such a modulation scheme must have a minimum run length of 3 channel bits and a maximum run length of 11. For avoiding run lengths of fewer than 3 bits, a group of 3 "merging" or coupling bits are inserted between sequences of 14 channel bits. The EFM, for example, which is one of conventional digital modulating methods, provides easy extraction of clocks from modulated data and, for reducing low frequency components of demodulated data, the EFM minimizes the maximum length between transition Tmax. However, in case of recording and reproduction not requiring removal of DC components or in case of no need for clock extraction from modulated data, restriction on Tmax may be alleviated. Examples of such cases having no or less need for removal of DC components are a case not passing through a transformer or other element incapable of DC transmission, and a case using an NRZI or other recording and reproducing method in which edges invertible from "0" to "1" or vice versa have information. On the other hand, there is proposed a method for forming clock pits and tracking servo pits in preformat areas provided for respective segments in one track of a rewritable optical disc such as magnetooptical disc. Since this method supplies a reproduced output of a clock pit to a PLL and extracts a bit clock, the clock extraction is not affected even if the Tmax of data to be recorded in the data area is long. Further, a tracking servo is done stably even in the case having DC components as there are servo pits for tracking. Additionally, the EFM, which converts 8 bits into 17 bits, involves a problem that the generation of modulation clocks is difficult. More specifically, a frequency of a clock regarding data bits and a frequency of a clock regarding channel bits are not held in an integer ratio relationship: therefore, the scale of hardware for producing both clocks is large. OBJECTS AND SUMMARY OF THE INVENTION It is, therefore, an object of the invention to provide a digital modulating circuit capable of alleviating restriction on maximum length between transition Tmax and improving other parameters. A further object of the invention is to provide a digital modulating circuit facilitating generation of a clock for data bits and a clock for channel bits. According to an aspect of the invention, there is provided a digital modulating circuit according to Claim 1, in which a parallel converter codes M data bits into N channel bits (M < N), being configured to maximize the minimum value of the number of successive "0"s sandwiched between "1" and "1" in a row of coded bits. According to another aspect of the invention, there is provided a digital modulating circuit for coding M data bits into N channel bits (M < N), being conligured to satisfy the relationship (N = α M) (where α is a positive integer equal to or larger than 2). Therefore, since the inventive circuit is configured to maximize the number of successive "0"s sandwiched between "1" and "1", Tmin can be elongated. Further, removal of restriction on the maximum length between transition Tmax can decrease N as compared to other modulating methods in which the number of successive "0"s is identical. The above, and other, objects, features and advantages of the present invention will become readily apparent from the following detailed description thereof which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of an embodiment of the invention; Figs. 2A to 2H are schematic views showing conversion tables for a code converter; Fig. 3 is a block diagram of a modulator in another embodiment of the invention; Figs. 4A to 4H are schematic views showing conversion tables for a code converter; Fig. 5 is a schematic view for use in explanation of modulated data; and Fig. 6 is a block diagram of a demodulator. [Embodiment] An embodiment of the invention is described below referring to the drawings. In Figs 1, reference numeral 1 denotes an input terminal which is supplied with digital data to be recorded on a recording medium such as magneto-optical disc, numeral 2 refers to a serial-parallel converter for converting input data into data of 8 parallel bits, and numeral 3 denotes a data converter. The data converter 3, which is made of ROM, PLA and so on, is fed with data bits d1, d2, ..., d8 in the form of 8 bits and outputs channel bits c1, c2, ..., c16 in the form of 16 bits. Tables for converting 8 bits into 16 bits are, for example, as shown in Figs. 2A to 2H. The data of 16 parallel bits c1, c2, ..., c16 from the data converter 3 is applied to a parallel-serial converter 4, and recording data of serial bits is obtained at an output terminal 5. The recording data is fed to an optical pickup not shown and recorded on a magneto-optical disc. The magneto-optical disc is provided with concentrical or vortex tracks. Each track is divided into a predetermined number of sectors and each sector is subdivided into segments. Servo areas are prerecorded on respective segments in an embossing process. Formed in the servo area are an access code coinciding with a lower significant bit of a track address, a clock pit for clock extraction and a wobbling pit for detection of a tracking error. The recording data is recorded in a data area subsequent to the servo area. The access code is used in seeking operation for seeking a target track. When the data is reproduced from the disc, a playback clock synchronizing with a reproduced output of the clock pit in the servo area is formed by the PLL, and the tracking servo is activated by the reproduced output of the wobbling pit. In order to generate a clock for modulation, a clock generator shown at 6 is provided, and an output signal of the clock generator 6 is supplied to the parallel-serial converter 4. The output signal of the clock generator 6 is fed to a 1/2 frequency divider 7, and a clock whose frequency is divided into 1/2 by the 1/2 frequency divider 7 is fed to the serial-parallel converter 2. This embodiment is a digital modulation for converting M data bits into N channel bits, where M = 8 and N = 16. Therefore, frequencies of clocks required for data bit processings and channel bit processings are held in an integer ratio relationship, and a simple circuit arrangement using the 1/2 frequency divider 7 can generate required clocks. The code conversion tables shown in Figs. 2A to 2H comply with the rule that the data (c1 to c16) obtained by such modulatior never fails to place 2 or more "0"s between "1" and "1", and the rule is complied with also when symbols of 16 bits are coupled. In order to satisfy the foregoing rule by converting data of 8 bits, at least 14 bits are necessary as they are in case of EFM. More specifically, excluding the pattern whose 16 bits are all "0", there are 276 patterns which satisfy the foregoing rule, and (2⁸ = 256) pieces of data are associated by one to one with 256 pieces among 276 patterns. Figures 2A to 2H show that last 2 bits c15 and c16 of the channel bits are both "0", and they never fail to comply with the rule that two or more "0"s are present between "1" and "1" even when symbols of 16 bits are coupled. Parameters of the digital modulation according to this embodiment are shown below. Tb indicates intervals of data bits. Tw = (1/2) Tb Tmin = 3Tw = (3/2) Tb Tmax = 19Tw = (19/2) Tb DR = 3/2 In the code conversion tables shown in Figs. 2A to 2H "0"s added to the EFM conversion tables as two channel bits c15 and c16. In this case, 2-bit "0"s may be added to the head of 14 bits obtained by the EFM conversion tables or, 1-bit "0" may be added to the head and tail, respectively. Apparently, code conversion tables different from the EFM conversion tables can be used. Any other integer ratio in lieu of 2 as the relationship between M and N is also acceptable to facilitate clock generation. As mentioned above, this invention does not necessarily require removal of DC components, and can remove restriction on the maximum length between transition Tmax in a recording/reproducing mode which can form clocks synchronizing with reproduced data, by other means of recorded data. Therefore, the minimum length between transition Tmin and the recording density DR which are parameters other than the maximum length between transition Tmax can be improved. On the other hand, required degrees of reducing low frequency components or Tmax usually vary depending on characteristics of transmission paths, contents of transmitted data, and so on. A transmission path may have a very bad transmission characteristic as for low frequency components and may require more suppression of low frequency components than that of the EFM. Another transmission path may not necessarily require removal of low frequency components or extraction of clocks from modulated data. Preparation of different digital modulator, considering such variant characteristics of transmission paths and contents of transmitted data, needs developments and designes of conversion rules, modulator, demodulator and so on, separately. On the other hand, this invention can provide a digital modulator and an associated demodulator circuit having a simple circuit arrangement and readily adaptive to variant characteristics of transmission paths. Another embodiment of the invention will now be described referring to the drawings. In Fig. 3, reference numeral 21 refers to an input terminal supplied with digital data to be recorded on a recording medium such as magneto-optical magnetic disc, numeral 22 refers to a serial-parallel converter for converting input data into data of 8 parallel bits, and numeral 23 denotes a data converter. The data converter 23, which consists of ROM, PLA and others, is supplied with data bits d1, d2, ... and d8 in the form of 8 bits, and supplies channel bits c1, c2, ... and c14 in the form of 14 bits. Tables for converting 8 bits into 14 bits are, for example, as shown in Figs. 4A to 4H which are the same conversion tables as the formerly proposed EFM modulations. More specifically, the code conversion tables shown in Figs. 4A to 4H comply with the rule that two or more "0"s are inserted between "1" and "1", and limit such "0"s between "1" and "1" within 10 pieces in order to shorten Tmax. In order to convert data of 8 bits and satisfy the foregoing rule, at least 14 bits are required. That is, there are 267 patterns in which 14 bits satisfy the above rule, and (2⁸ = 256) pieces of data are associated by one to one with 256 pieces among 267 patterns. The data of 14 parallel bits c1, c2, ... and c14 from the data converter 23 are fed to the parallel-serial converter 24, from which is obtained a first code signal in the form of serial bits. The first code signal is fed to the selector 25. The selector 25 has three output terminals which are connected to coupling bit adders 26A, 26B and 26C. As shown in Fig. 5, the coupling bit adders 26A, 26B and 26C are circuits which add coupling bits of p bits as a second code signal to each junction between a 14-bit code signal c1 to c14 and an adjacent such signal formed by the data converter 23. The coupling bit adder 26A adds coupling bits of (p = 2) bits, the coupling bit adder 26B adds coupling bits of (p = 3) bits, and the coupling bit adder 26C adds coupling bits of (p = 4) bits. These coupling bit adders 26A, 26B and 26C each add coupling bits so as to satisfy the requirement regarding the Tmin in the data converter 23, i.e., the condition that two or more successive "0"s are present between "1" and "1". The same type of coupling bit adder as used in conventional EFM modulation is employed as the coupling bit adder 26B of (p = 3). More specifically, prepared are 3-bit patterns (000), (100), (010) and (001) having two or more successive "0"s between "1" and "1". A 3-bit pattern is determined by satisfying the condition of Tmax (ten or less "0"s between "1" and "1") and by considering which coupling bits should be inserted into two successive 14-bit patterns to minimize DSV. Therefore, an output signal of the coupling bit adder 26B is made of a symbol of 17 bits corresponding to 8-bit data. The output signal of the coupling bit adder 26B is fed to a selector 27. Parameters of modulated data obtained from the coupling bit adder 26B are shown below, where Tb indicates data bit intervals. Tw = (8/17) Tb Tmin = 3Tw = (24/17) Tb Tmax = 11Tw = (88/17) Tb DR = (24/17) The coupling bit adder 26A adds 2-bit coupling bits at 14 bits intervals. Therefore, an output signal of the coupling bit adder 26A is made of a 16-bit symbol corresponding to 8-bit data. The output signal of the coupling bit adder 26A is fed to the selector 27. The coupling bit adder 26A adds coupling bits (00) to the end of each 14-bit symbol of the EFM conversion tables shown in Figs. 4A to 4H. In this case, 2-bit "0"s may be added to the head of each set of 14 bits obtained from the EFM conversion tables, or 1-bit, "0" may be added to the head and tail, respectively. Further, 2-bit patterns of (10) and (01) may be prepared in addition to (00) to determine coupling bits so as to minimize DSV in the same manner as the coupling bit adder 26B. Parameters of modulated data obtained from the coupling bit adder 26A are shown below. Tw = (8/16)Tb = (1/2)Tb Tmin = 3Tw = (3/2) Tb Tmax = 19Tw = (19/2) Tb ... coupling bit (0, 0) only Tmax = 11Tw = (11/2) Tb ... coupling bits (0, 0), (1, 0), (0, 1) DR = 3/2 The coupling bit adder 26C is used in case of (p = 4). In the same manner as the coupling bit adder 26B, bit patterns (0000), (0001), (0010), (0100), (1000) and (1001) are prepared in the coupling bit adder 26C, and one of the coupling bits is determined, considering which one of the coupling bits should be inserted between successive two 14-bit patterns to minimize DSV. Since more patterns of coupling bits are prepared than those prepared in the coupling bit adder 26B; better suppression of low frequency components can be provided. Parameters of modulated data obtained from the coupling bit adder 26C are shown below. Tw = (8/18) Tb = (4/9)Tb Tmin = 3Tw = (4/3) Tb Tmax = 11Tw - (44/9)Tb DR = 4/3 An output signal of the coupling bit adder 26C is fed to the selector 27. It is evident by comparison among the foregoing parameters that the output signal of the coupling bit adder 26B or 26C is suitable for a system to extract clocks from modulated data itself. In contrast, the output signal of the coupling bit adder 26A in the case where a fixed data (00) is suitable for a system having other clock extracting means such as clock bits of a magneto-optical disc. Recording density can be increased most by a system using the coupling bit adder 26A, and it is decreased least by a system using the coupling bit adder 26C. Low frequency components, however, can be reduced most by the system using the coupling bit adder 26C. Any one output signal of the coupling bit adders 26A, 26B and 26C selected by the selector 27 is extracted at an output terminal 28. A select signal from a select signal generator 29 is supplied to the selectors 25 and 27, and one of output signals of the coupling bit adders 26A, 26B and 26C is selected in response to the select signal. The select signal generator 29 generates the select signal in response to a key signal, instructions from a control circuit and so on. The modulated data and the select signal taken out at the output terminals 28 and 30, respectively, are converted into recording data by a formating circuit not shown. The recording data is fed to an optical pickup or other recording means via a recording amplifier and recorded on a magneto-optical disc or other recording medium. Fig. 6 shows an arrangement of digital demodulator associated with the foregoing digital modulator. In Fig. 6, an input terminal shown at 11 is supplied with reproduced data, and an input terminal shown at 12 is supplied with a select signal which is reproduced together with reproduced data. The reproduced data is fed to a data detector 13 and its waveform shaping is done. An output signal of the data detector 13 is supplied to a separator 14. The separator 14 excludes the coupling bits and extracts the first code signal alone. The bit number p of the coupling bits is 2 bits, 3 bits or 4 bits as indicated above. The select signal indicates the bit number of the coupling bits. Therefore, it is fed to the separator 14. The separator 14 separates the first code signal alone in which 14 bits form a symbol. An output signal of the separator 14 is supplied to a serial-parallel converter 15 and converted into parallel data of 14 bits. The 14-bit data is fed to a data converter 16, which converts the 14-bit data into 8-bit data, in contrast to the modulation process, according to the conversion tables shown in Figs. 4A to 4H. The data converter 16 is made of ROM, PLA and so on. The 8-bit parallel data from the data converter 16 is fed to a parallel-serial converter 17, and serial output data is obtained at an output terminal 18. The data conversion tables are completely identical in three different modulating methods in the foregoing embodiment. However, the invention can be also applied to the case where the conversion rule is identical in most part and different in minor part. Kinds of different modulating methods are not limited to three. As mentioned above, this invention uses a common circuit for converting data excluding coupling bits for different modulating method. Therefore, the circuit having a simple construction, is adaptive to any characteristics of transmission paths, contents of data to be transmitted, and so on.

Claims: A digital modulating circuit comprising: an input terminal (1), which is supplied with digital data to be recorded on a recording medium, a serial-parallel converter (2) for converting the serial input data into data of M parallel bits, a data converter (3) for coding M data bits into N channel bits, where M < N, being configured to maximize the minimum value of the number of successive "0"s sandwiched between "1" and "1" in a row of coded bits, a parallel-serial converter (4) for converting the data of N channel bit into recording data of serial bits, an output terminal (5) for receiving the data of serial bits, and a clock generator (6) for generating a clock signal for modulating, whereby the clock signal is supplied to said parallel-serial converter (4) and a frequency divided clock signal (7) is supplied to said serial-parallel converter (2) to hold the frequencies of the clock signals required for data bit processings and channel bit processings in an integer ratio relationship. A digital modulating circuit according to claim 1, wherein said M data bits are eight bits. A digital modulating circuit according to claim 2, wherein said minimum value of the number of successive "0"s is two. A digital modulating circuit according to claim 2, wherein said N channel bits are sixteen channel bits. A digital modulating circuit according to claim 1, wherein said N channel bits satisfies N = αM, where α is an integer equal to or larger than 2. A digital modulating circuit according to claim 5, wherein said M data bits are eight bits. A digital modulating circuit according to claim 6, wherein said minimum value cf the number of successive "0"s is two. A digital modulating circuit according to claim 6, wherein said α is 2. A digital modulating circuit according to claim 8, wherein the pattern of successive fourteen channel bits in said N channel bits and the pattern of eight to fourteen modulation are identical. A digital modulating circuit according to claim 9, wherein two channel bits exclusive of said fourteen channel bits are "0".

Inventors: SAKO YOICHIRO, YAMAGAMI TAMOTSU, SAKO, YOICHIRO, YAMAGAMI, TAMOTSU
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H03M5
IPC codes: H03M5, G11B20