CIRCUITS WITH SWITCHING PROTECTION AND PARTS THEREFOR

Abstract: A controllable circuit (10) having protection against damaging switching conditions for its component transistors (12) is described. The circuit (10) is a full-wave inverter bridge being controlled by a pulse width modulation technique, to which is connected an inductive load (50) and a resonant circuit (30). The circuit (10) also comprises snubber circuit (18) and free-wheeling diodes (14) associated with each transistor (12). The transistors (12) are switched between on-states and off-states to synthesize a pulse width modulation waveform from input supplies Vs<+> and Vs<-> at the output terminals VA and VB. The elements of the resonant circuit (30) provide for placing the transistors (12) in an advantageous condition for switching between states, such that they do not experience undue damage or stresses. The method of operation includes switching-on one of the controllable transistors (22) to provide an alternative path for the load current, IL, thereby forming a resonant circuit by two capacitors (20), the inductor LC and the load. In this way, there is control over the rate of rise of the off-state voltage, dv/dt, and the rate of rise of on-state current, di/dt, and minimization of the static off-state voltage all with respect to the transistors (12). The diodes (24) provide blocking in respective opposite half cycles.

Description: CIRCUITS WITH SWITCHING PROTECTION AND PARTS THEREFOR FIELD OF THE INVENTION This invention relates to circuits with switching protection and parts therefor, and relates particularly but not exclusively to arrangements for the protection of such circuits having switching devices which are switched under load conditions. DESCRIPTION OF THE PRIOR ART Semiconductor devices used in power circuits can be considered as forming two specific groups. The first group comprises devices such as SCR's or Triacs which can be switched into an on-state via a control electrode, but can not be switched into an off, or blocking state through the same electrode, rather, require natural or forced commutation. The second group comprises devices such as GTO's, Power Transistors and IGFET's which can be switched into both the on-state and the off-state via a control electrode. This discussion will focus on circuits containing semiconductor power devices of this second group. Such semiconductor power devices find greatest usage in rectifier, chopper and inverter circuits, where their switching capabilities are used to synthesize waveforms supplying electrical loads. In designing these types of circuits * , there are a number of design performance criteria which must be considered. In the off-state, the device will have some finite principal voltage withstand characteristic, above which avalanche breakdown will occur. Avalanche breakdown occurs when minority carriers dislodge further minority carriers thereby transforming the device into the on-state. In addition to an off-state voltage withstand rating, the time rate of change of voltage rating, dv/dt, is also important. If the off-state voltage increases too rapidly with time, there may be a spontaneous change to the on-state. A further consideration is the critical rate of rise of on-state current, di/dt. If the rate of change of current is too high there will be a deleterious effect to the semiconductor power device due to junction heating or direct avalanche breakdown. This problem has, in part, been alleviated by the use of series inductors. Known pulse width modulation (PWM) systems are designed to synthesize an output waveform of one or more phases having a frequency differing from that of the input. Improvements in semiconductor power devices in terms of current rating and dv/dt limits have allowed PWM switching frequencies to increase. Nevertheless, with higher switching frequencies has come the problem of greater Radio Frequency Interference (RFI). There are also problems associated with the frequency of switching between the on-state and off-state for such devices due to limitations placed by minority carrier recombination times, which manifests itself in finite switch-off times and the need to absorb an amount of energy in snubber circuitry. Where the load being supplied is inductive, the current flowing will be lagging the supply voltage, and despite techniques such as the provision of free-wheeling diodes, there will nevertheless be an amount of energy which must be dissipated by the semiconductor power device. This energy is in the form of heat, which must be considered in the circuit design in terms of cooling requirements. If there is insufficient protection of the semiconductor power device, adverse junction heating can occur which could lead to its ultimate destruction. One approach to alleviate these problems is the use of a high frequency resonant source (viz., at the input) to assist in the switching of semiconductor power devices and introduce controlled dv/dt and di/dt. The use of a constant natural frequency to commutate the switching devices has the drawback that switching between states can only take place at points of natural commutation, which is not particularly useful for PWM circuits in which it is desirable to switch any device at any time, especially if a variable frequency output is to be synthesized. As a result there will be poor switching resolution which reduces the advantages of high natural frequency and can also lead to unwanted modulation noise. OBJECT USD STATEMENT OF THE INVENTION It is an object of the invention to provide for the change of state for switching devices at any desired time, even in the presence of inductive load currents, in a manner such that undue stresses, which would otherwise lead to failure, are not placed on the devices. According to one aspect of the invention, there is provided an electrical circuit with switching protection comprising: a controlled circuit having an input of fixed frequency and including switching devices, the controlled circuit being adapted to produce one or more outputs of a frequency different to the input by the switching devices; an electrical load connected to the one or each outputs &£ the controlled circuit; and a resonant circuit connected to the one or each outputs of the controlled circuit, wherein, the resonant circuit is operable to cooperate with the load to provide the controlled circuit in an advantageous condition for activation of the switching devices at a change of state. Most preferably, the controlled circuit is operable using a pulse width modulation technique. According to yet a further aspect of the invention, there is provided a resonant circuit for use with a controlled circuit having a load connected to one or more outputs thereof, the resonant circuit being adapted for connection to the one or each outputs and comprising: anti-parallel connected controllable semiconductor devices in combination connected in series with at least one inductive element; and capafcitive elements connected between an output and a reference voltage; the resonant series circuit being formed by at least one of the capacitive elements, at least one of the inductive elements and the load, whereby the controlled circuit can be placed in an advantageous condition for switching between states. According to yet a further aspect of the invention, there is provided a method for protecting a controlled circuit having an input of fixed frequency and including switching devices, the controlled circuit supplying a load and being adapted to produce one or more outputs of a frequency different to the input of the switching devices, the method comprising the steps of: providing a resonant circuit connected to the one or each outputs; and operating the resonant circuit in cooperation with the load to provide the controlled circuit in an advantageous condition for activation of the switching devices at a change of state. BRIEF DESCRIPTION OF THE DRAWINGS in order that the invention may be more clearly understood, examples of preferred embodiments will now be described with reference to the accompanying drawings wherein: Figure 1 shows one form of an idealised pulse width modulation generated waveform in accordance with the prior art; Figure 2 shows a single phase inverter disposed in one particular state and constructed in accordance with the invention; Figure 3 shows the single phase inverter of Figure 2 in another state; Figure 4 shows details of current and voltage waveforms during turn-on of one limb of the bridge as shown in Figure 2; and Figure 5 shows a further embodiment of a three phase application for the invention. Detailed Description of Preferred Embodiments The description of preferred embodiments will be made with reference to pulse width modulation (PWM) controlled inverters supplying inductive loads, however it is to be understood that the invention need not be limited to such an application, and is equally applicable in circuits for rectifiers, choppers, cyclo-convertors, switched mode power supplies and other similar uses. Figure 1 shows a simple illustration of one form of a pulse width modulation technique. The output waveform V 0 is synthesized in the two half-cycles by a number of voltage pulses V having magnitude V in the positive half cycle, and the magnitude V in the negative half cycle. That is, the resultant of the pulses approximates the sinusoidal representation of the output waveform V Q . The number and width of the various pulses V will be changed in accordance with the desired frequency of the output waveform V Q . A limitation on the maximum achievable output frequency will depend on how quickly the switching devices which are synthesizing the waveform can be switched on or off. The technique of pulse width modulation is well known. Referring now to Figure 2, there is shown a single phase full-wave PWM controlled inverter bridge circuit 10 connected to an inductive load 50. A resonant circuit 30 is connected across the output of the bridge circuit 10, with the output being identified as terminals V- and V R . This configuration allows switching to the on-state or to the off-state from the opposite state at any point on the output voltage waveform. The sources for the bridge circuit 10 are the two DC supply voltages V + and V —. It is equally possible to provide for the supply voltage to be of a frequency other than DC, such as would be the case for a cyclo-convertor. The bridge circuit 10 is formed by two limbs, each of which comprises a pair of switching devices in the form of bipolar junction transistors 12. The first limb is The bridge circuit 10 is formed by two limbs, each of which comprises a pair of switching devices in the form of bipolar junction transistors 12. The first limb is constituted by transistors Q1A and Q2A and the second limb by transistors QlB and Q2B. Each of the transistors 12 is provided with a free wheeling diode 14, being variously D1A, D2A, DIB and D2B. Although transistors have been shown in the limbs of the bridge, it would be equally applicable to substitute other semiconductor devices which can be switched-off via a control electrode, such as GTO's or IGFET's. The centrepoint 16 of each limb is connected to a respective snubber circuit 18 comprising a parallel resistor and inductor combination RSA and LSA, RSB and LSB, after which is formed the respective output terminals V, and V,-,. At the output terminals, there are also connected capacitors 20 (CS1 - CS4) which are components of the resonant circuit 30, and which also connect to either of the supply voltages V or The inductive load 50 is shown connected between the output terminals V. and V β . Also connected between the output terminals is part of the resonant circuit 30, which is symmetric and comprises two anti-parallel connected series transistor/diode configurations, in combination being in series with inductor LC. The transistors 22 are designated QC1, QC2 respectively, and the diodes 24 are designated DCl, DC2. For the purpose of this discussion, the snubber circuits 18 will be temporarily ignored, as they are of small value and do not significantly affect operation of the bridge circuit 10. The example of Figure 2 shows the condition of transistors Q1A and Q2B conducting. This corresponds to any particular one of the pulses V in the positive half-cycle of the output voltage waveform V Q as shown in Figure 1. In this state, load current I τ flows from the supply V through the inductive load 50 returning to the input supply V as shown. The voltage appearing between the output terminals V, and V β would be close to 2*V , allowing for collector-emitter voltage drops in transistors QLA and Q2B, as well as the voltage drop across resistors RSA and RSB. Although the controlling electronics for the base terminals of the various transistors 12,22 are not shown, in use, they can all be driven by appropriate circuitry which would be under the control of digital processing apparatus. The negative half cycle of waveform V shown in Figure 1, would be achieved by the appropriate switching of transistors Q2A and QlB such that the polarity of the voltage appearing between the output terminals V. and V β would be reversed. In the examples shown, transistors Q1A and Q2B are conducting, and capacitors CS2 and CS3 will become charged with approximately voltage of 2*V £_ . Considering firstly the instance of switching-off transistors Q1A and Q2B for the purpose of generating an off-state within the PWM generated waveform. This is achieved by gating these transistors via their base terminals such that they become blocking. Since the load 50 is inductive, the current I I τ through the transistors will be lagging and must find a path through forward biased diodes D1A and D2B. The voltage at the output terminals V and V β will slew with a controlled rate of I-/(2*CS) until such time as diodes DIB and D2A conduct. The voltage between the output terminals V. and V β will then .be at its zero reference value, and the load current I will continue to flow for a finite time until the stored energy of capacitors CS2 and CS3 is dissipated. It is usual to institute a further on-state well before the load current I L has decreased substantially. That is, it is preferable to maintain the load current L as being continuous. The switching between on-states and off-states is clearly shown in Figure 1. Considering now the switch-on procedure, which again will conveniently be a consideration of transistors Q1A and Q2B. Since the charge stored in capacitors CS2 and CS3 will not have totally dissipated following an off-state, if the resonant circuit 30 was not provided there would be a large in-rush current experienced by the transistors upon switch-on due to this stored charge, which can cause substantial damage to the transistors. In describing the switch-on procedure in more detail, reference will be made to Figures 3 and 4. Before transistors QlA and Q2B are switched-on, transistor QC2 is activated, thereby including inductance LC in parallel arrangement with the load 50. Diode DC2 will be forward biased, and therefore, stored energy in capacitors CS2 and CS3 now has a second path other than through load 50. Following switch-on of transistor QC2, the current through LC will increase linearly at a rate of (V + + V —)/LS until it is equal to the load current I L . Figure 4 shows the near continuous load current I_ together with current through inductor LC and the load voltage between output terminals V, and V β . The section A-B in Figure 4 represents the increase of current through inductor LC up to a point where it is equal to the load current I τ . After this point, the current through inductor LC continues to increase following a resonant trajectory B-C for a period of l/(4*7f*,/(LC*CS) ) due to the resonant circuit formed between inductor LC and capacitors CS2 and CS3. The voltage across respective capacitors CS2 and CS3 has now decreased as the load voltage increases following a half sine wave in section B-C until the voltage between the output terminals V- and V β has changed sign. At point C, transistors Q1A and Q2B are switched-on, in which instance there will be virtually no voltage difference between V », and V5 , and V_ n D and VS respectively, and hence transistors Q1A and Q2B are not inordinately stressed. The current through inductor LC will then decay linearly at the rate of (V __> - V•__>~)/LC along section C-D until it reaches zero. At the zero point, the transistor QC2 can be turned off. The maximum current flowing through inductor LC will be (V + - V ~>V(CS/LC) . The diodes DCl and DC2 provide reverse blocking for their respective transistors QCl, QC2. In the example given, transistor QC2 is utilised in switching-on transistors QlA and Q2B; conversely transistor QCl would be used in the switch-on procedure for transistors Q2A and QlB. Transistors QCl and QC2 are shown as bipolar junction transistors, but could easily be other types of semiconductor devices, such as GTO's, IGFET's, or indeed, SCR's, since there is no particular need for turn-off by a control electrode. A single Triac could replace both transistors QCl and QC2. It is necessary for the transistors 22 and diodes 24 in the resonant circuit 30 to be rated with the equivalent forward current rating of the load, however the advantages of low stress switching and the elimination of commutation clamp rails are sufficient to justify the extra cost when operating at high switching frequency associated with PWM techniques. Returning to the components of the snubber circuit 18, RSA/LSA and RSB/LSB. These components have been included to allow for losses in the resonant circuit 30, and to prevent _. momentary excessive current at switch-on of the bridge transistors 12. That is, there will always be a small remnant voltage across the complimentary capacitor in each limb (for example QlA and CS2) which could cause in-rush current upon change of state of a transistor 12. This in-rush current must be controlled and dissipated by the combination of the parallel resistance and inductance of the snubber circuit 18. Although not shown, it is most preferable to include an interlock in the circuit 10 to ensure that the bridge transistors Q1A/Q2B and Q2A/Q1B do not switch-on unless their forward voltage is below the maximum safe level determined by the snubber circuit 18. In the example described above, the switching of transistors QlA, Q2B and QC2 corresponds to the positive half cycle of the synthesized output waveform V„. For the negative half cycle, operation of the complementary components would take place. The bridge circuit 10 shown is not self starting, rather an initiating circuit must be included to charge the capacitors CS1-4, which could be achieved by a pair of relatively low current FET's or BJT's with series resistors. As noted, the transistors 22 and diodes 24 in the resonant circuit 30 must be rated for full load current, but it is also possible to duplicate the transistor 22, diode 24 and inductor LC structure shown and provide an interconnecting centrepoint between the duplicated sections which is at a zero voltage reference level, whereby the voltage ratings of the transistors could be halved. If the inverter bridge circuit 10 were only a half wave bridge, the limbs containing transistors QlB and Q2B would not be required and therefore, the output terminal V β would simply be connected to a zero voltage reference level. A further embodiment is the extension to a three phase application as shown in Figure 5. The three phase inverter 60 is shown in block diagram form, as is the inductive load 55. The resonant circuit 30 of the previous embodiment is provided in three equivalent circuits 70, each of which is connected to the output phases ψ-. ~ r _ ' Tne transistors QC5-10 are in a symmetric arrangement and are shown connected by a pair of diodes 72 between the respective phase outputs, each pair having a common connection to a neutral point, N. The neutral point, N is also connected to the respective third output phase via inductors LC1-3. The function of capacitors CS1-CS4 as discussed in the single-phase embodiment is achieved by six inter-phase capacitors provided within the inverter 60. This example allows one simultaneous state change from a present state to the diagonally opposite state. All other state combination must be as a result of switch-off of the bridge transistors in the three phase inverter 60 from the opposite state. Modification may be made to the examples referred to above as would be apparent to persons skilled in the electronics arts. These and other modifications may be made without departing from the ambit of the invention, the nature of which is to be determined from the foregoing description.

Claims: CLAIMS : 1. An electrical circuit with switching protection comprising: a controlled circuit having an input of fixed frequency and including switching devices, the controlled circuit being adapted to produce one or more outputs of a frequency different to the input by the switching devices; an electrical load connected to the one or each outputs of the controlled circuit; and a resonant circuit connected to the one or each outputs of the controlled circuit, wherein, the resonant circuit is operable to cooperate with the load to provide the controlled circuit in an advantageous condition for activation of the switching devices at a change of state. 2. A circuit as claimed in claim 1, wherein the controlled circuit is operable by a pulse width modulation (PWM) technique. 3. A switching circuit as claimed in claim 1, wherein the advantageous condition comprises controlling the rate of rise of off-state voltage, controlling the rate of rise of on-state current, and minimizing the static off-state voltage for the switching devices. 4. A circuit as claimed in claim 1, wherein the resonant circuit is symmetrical and separately controllable with respect to positive and negative half-cycle waveforms forming the one or each output. 5. A circuit as claimed in claim 4, wherein the resonant circuit comprises anti-parallel connected semiconductor devices in combination connected in series with inductive and capacitive elements. 6. A circuit as claimed in claim 5, wherein the resonant circuit includes a blocking diode in series connection with each of the semiconductor devices. 7. A circuit as claimed in claim 2, wherein the PWM controlled circuit is a full-wave inverter. 8. A resonant circuit for use with a controlled circuit having a load connected to one or more outputs thereof, the . resonant circuit being adapted for connection to the one or each output and comprising: anti-parallel connected controllable semiconductor devices in combination connected in series with at least one inductive element; and - capacitive elements connected between an output and a reference voltage; the resonant series circuit being formed by at least one of the capacitive elements, at least one of the inductive elements and the load, whereby the controlled circuit can be placed in an advantageous condition for switching between states. 9. A resonant circuit as claimed in claim 8 for use with a controlled circuit which is operable using a pulse width m<S £ _ulation (PWM) technique. 10. A resonant circuit as claimed in claim 9, wherein the advantageous condition comprises controlling the rate of * , rise of off-state voltage across any one of a plurality of semiconductor switching devices in the PWM controlled circuit, controlling the rate of rise of on-state current and minimizing the static off-state voltage difference across any one of the semiconductor switching devices. 11. A method for protecting a controlled circuit having an input of fixed frequency and including switching devices, the controlled circuit supplying a load and being adapted to produce one or more outputs of a frequency different to the input of the switching devices, the method comprising the steps of: providing a resonant circuit connected to tne one or each outputs; and operating the resonant circuit in cooperation with the load to provide the controlled circuit in an advantageous condition for activation of the switching devices at a change of state. 12. A method as claimed in claim 11, wherein the controlled circuit is operable by a pulse width modulation (PWM) technique. 13. A method as claimed in claim 12, wherein the step of operating comprises actuating a semiconductor device to form a series resonant circuit formed by at least one capacitive element, at least one inductive element and the load, such that for switching devices in the PWM controlled circuit the rate of rise of off-state voltage and the rate of rise of on-state current is controlled, and the static off-state voltage is minimized.

Inventors: ECKERSLEY GREGORY P, ECKERSLEY, GREGORY, P.
Applicants: BORAL JOHNS PERRY IND PTY LTD, BORAL JOHNS PERRY INDUSTRIES PTY LTD.
Application year: 1990
Main classification: H03K17
IPC codes: H02J1, H02M7, H03K17