Structure of solid-state image sensing devices

Abstract: A structure of a solid-state image sensing device applicable to an HDVS is disclosed in which at least one of both trans­ mission paths for drive pulses used for driving vertical registers and horizontal registers incorporated in the solid-state image sensing device can achieve reduced propa­ gation delays and signal distortions of the drive pulses. In the first preferred embodiment, a control gate (3) for controlling the transfer of signal charges between the horizontal registers is constituted by a first polycrystalline silicon layer, a metal wiring layer (10) is formed which is connected to the first polycrystalline silicon layer via contact regions (9), and transfer electrodes (5) provided for driving the horizontal registers are constituted by second and third semiconductor layers placed between the first polycrystalline silicon layer and metal wiring layer and formed so as to avoid contact against the contact regions (9). In the second preferred embodiment, the control gate is formed of a wiring layer placed at an layer upper than the semiconductor layers constituting the transfer electrodes of the horizontal registers. In the third preferred embodiment, shunt wiring films (12) are formed independently on the transfer electrodes for the vertical registers of an image portion and on those of a storage portion.

Description: The present invention relates to a structure of a solid-state frame interline type (FIT) imager or image sensing device in which signal charges generated by a plurality of photo receiving elements arranged in a matrix form are transferred in a vertical direction by means of a plurality of vertical registers and the signal charges transferred by means of the plurality of vertical registers are partially transferred by means of a plurality of horizontal registers. It becomes necessary to provide a high resolution for solid-state image sensing devices commonly used as photographing means in video cameras in order to meeet requirements for highly resolved video cameras. Specifically, the number of pixels (constituted by the photo receiving elements) arranged in a matrix form must be increased. Although the number of pixels in the solid-state image sensing device of a commercially available video camera are about 300 thousands through 400 thousands, about 2,000 thousands of pixels are required since the resolution is five times higher than that in the comercially available video camera in the case of the video camera applicable to an HDTV (High Definition Television). In addition, since an increase in size of a chip in proportional to the increase in the number of pixels is not allowed, the number of pixels must remarkably be increased with no increase in the chip size. Since a limit of the number of pixels aligned in a horizontal direction is generally determined acording to a unit length of one bit of a horizontal register with the chip size of the solid-state image sensing device constant, this horizontal register provides a factor for restricting the high resolution of the image sensing device. A Japanese Patent Application Second Publication (Examined) No. Heisei 1- 13676 published on March 7, 1989 exemplifies the structure of the solid-state image sensing device in which a plurality of horizontal registers are arranged in parallel to one another and signals charges generated by means of the photo receiving elements and transferred in the vertical direction by means of the vertical registers are shared and distributed into a plurality of horizontal registers so that an improvement in integrations of the pixels in the horizontal direction can be achieved. A result of study on the solid-state image sensing devices in which the horizontal registers are installed is published in a paper of Television Society Vol. 41, No. 11 (published in 1987) titled " Super High Resolution CCD Image Sensor " on pages 74 to 80. One previously proposed solid-state image sensing device includes: a photo receiving portion in which photo receiving elements are arranged in the matrix form; a storage portion located below the photo receiving portion; a gate region located at a side of storage portion opposite to the photo receiving portion, the gate region transferring signal charges to a first horizontal register at the same time when receiving a gate voltage. The first horizontal register is arranged at a side of the gate region opposite to the storage portion. A control gate is arranged at a side of the first horizontal register opposite to the control gate. A second horizontal register is arranged at.a side of the control gate opposite to the first horizontal register. A multiplexor is provided for multiplexing the signal charges derived from the first and second horizontal registers. The control gate transfers signal charges transferred from any other vertical registers which does not correspond to respective channel stoppers provided at every other interval along the control gate to the second horizontal register. In addition, the control gate is formed by a first layer of a polycrystalline silicon layer. The polycrystalline silicon layer is located above an insulating film formed on a main surface of a semiconductor substrate. It is noted that an interlayer insulating film encloses the control gate and transfer electrodes are formed so as to intersect the control gate via the interlayer insulating film. The transfer electrodes serve to drive the horizontal registers. The transfer electrodes for the horizontal registers are arranged so that second and third layers of polycrystalline silicon layers are alternatingly arranged in the horizontal direction. One of the transfer electrodes constituted by one of the polycrystalline silicon layers receives a pulse Ø 1 and the other transfer electrode constituted by the other polycrystalline silicon layer receives a pulse Ø 2 . Since the previously proposed solid-state image sensing device applicable to an HDVS is provided with the control gate having a relatively long length of, e.g., about 15 mm, an application of a gate voltage Ø HP to the control gate is carried out from both ends of the control gate in order to reduce a time of propagation delay of the control signal transmitted thereto as short as possible. However, since a specific resistance (resistivity) of the polycrystalline silicon layer is never low and therefore an equivalent circuit of a transmission path of the gate voltage is constituted by a plurality of R-C circuits, a waveform of the gate voltage Ø HP is distorted at the control gate and/or its amplitude becomes reduced. In this way, when a time constant of the transmission path becomes large, the propagation delay occurs and gives an ill effect on operating characteristics of the control gate. Especially, since the transfer of the signal charges toward the horizontal registers by means of the control gate must be carried out within a very short horizontal blanking interval in a television system of HDVS (High Definition Video System), such a propagation delay as described above cannot be neglected any more. From JP-A-63 120 463 is known a solid-state FIT imager having multi-layer electrodes formed of laminated poly-Si and silicide to reduce a sheet resistance of a vertical transfer electrode. SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure of a solid-state image sensing device in which at least one of drive pulse transmission paths of a control gate for controlling transfer of signal charges transferred from vertical registers toward horizontal registers in synchronization with first drive pulses and of transfer electrodes provided for driving vertical registers to transfer signal charges generated in a plurality of photo receiving elements can achieve reduced drive pulse signal propagation delays and reduced signal distortions. This object is achieved by a solid-state frame interline type (FIT) imager according to the enclosed independent claim 1. Advantageous features of the present invention are defined in the corresponding subclaims. BRIEF DESCRIPTION OF THE DRAWINGS: Fig. 1 is a schematic elevational view of an internal structure of an image sensing device in a first additional development of a device according to the present invention. Fig. 2 is a cross sectional view cut away along the line of II - II of Fig. 1. Fig. 3 (A) is a circuit wiring diagram of a control gate in the first additional development shown in Figs. 1 and 2. Fig. 3 (B) is an equivalent circuit diagram of Fig. 3 (A). Fig. 4 is a schematic elevational view of an internal circuit of the structure of the image sensing device in a second additional development of a device according to the present invention. Fig. 5 is a cross sectional view cut away along the line of V - V of Fig. 4. Fig. 6 is a chematic elevational view of the structure of the image sensing device in a preferred embodiment according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT : Reference will hereinafter be made to the drawings in order to facilitate a better understanding of the present invention. Figs. 1 through 3(B) show a first preferred additional development to be used with a solid-state frame interline type imager according to the present invention which will be described below. In the drawings of Figs. 1 and 2, a semiconductor substrate 1 is located below an insulating film constituted by SiO 2 (silicon dioxide). A first polycrystalline silicon layer 3 is formed on the surface of the SiO 2 insulating layer. A plurality of interlayer insulating layers 4 are formed on the control gate 3. A plurality of transfer electrodes 5 for driving horizontal registers constituted by second polycrystalline silicon layers are formed on the respective interlayer insulating layers 4. A plurality of interlayer insulating layers 6 are formed so as to enclose the respective transfer electrodes 5. A plurality of other transfer electrodes 7 for driving the horizontal registers are formed on the interlayer insulating layers 6. In addition, as shown in Fig. 2, numeral 8 denotes a plurality of interlayer insulating layers, numerals 9, 9, -- denotes contact regions through which the control gate 3 is partially exposed, numeral 10 denotes a metal wiring layer, constituted by, e.g., aluminium, connecting the control gate 3 to the contact regions 9, 9. In the first preferred additional development, the control gate 3 for controlling signal charge transfer between two horizontal registers is constituted by the first polycrystalline silicon layer. The transfer electrodes 5, 7, 5, 7, -- controlling the two horizontal registers are formed by the second and third polycrystalline silicon layers. Then, the metal wiring layer 10 which serves as a shunt wire to intend a lower specific resistance for the control gate 3 is placed on an upper layer than the third polycrystalline silicon layers 7, 7, 7, ---. The contact regions 9, 9, --- serve to contact between the metal wiring layer 10 and control gate 3. The second and third multicrystalline silicon layers 5, 5, 7, 7, --- constituted by the horizontal register driving transfer electrodes are formed so as to avoid contacts against the contact regions 9, 9, --- in order to avoid occurrence of short-circuiting. Figs. 3 (A) and 3 (B) show a circuit wiring diagram of the control gate 3 and its equivalent circuit. Since the metal wiring layer 10, e.g., constituted by aluminium having a sheet resistance extremely lower than the control gate 3 ( one-thousandth or lower) is connected in parallel to one another as a shunt wiring form, a time constant of a transmission path of a gate voltage Ø HP is extremely small. Hence, since the propagation delay can remarkably be reduced, it is possible for the image sensing device to be applied to an HDVS (High Definition Video System). Figs. 4 and 5 show a second preferred additional development to be used with a solid-state frame interline type imager according to the present invention which willl be described below. In Figs. 4 and 5, numerals 11, 11, 11, --- denote transfer electrodes for driving storage portions of the horizontal registers and constituted by the first polycrystalline silicon layer. Numeral 12 denotes the interlayer insulating film. Numerals 13, 13, --- denote transfer electrodes for driving the transfer portion of the horizontal registers and constituted by the second polycrystalline silicon layer. Numeral 14 denotes the control gate for controlling the signal charge transfer between the horizontal registers, the control gate 14 being placed on an upper portion of the first and second layers of the polycrystalline silicon layers and constituted by polyside. The control gate 14 is opposed to the semiconductor substrate 1 via the insulating layer via regions 15, 15, --- cut out partially along the polycrystalline silicon layers 11, 13, 11, 13. The control gate 14 controls the transfers of signal charges between the two horizontal registers. Channel stops (denoted by oblique lines) 16, 16, 16, --- are arranged between the respective regions 15, 15 controlling the surface of the semiconductor substrate 1. In the second preferred additional development, since the control gate 14 is constituted by the polyside, the specific resistance along the control gate 14 can be reduced as compared with the conventional one which is merely constituted by the polycrystalline silicon. Hence, the time constant of the signal transmission path through which the gate voltage Ø HP is applied can become small. It is noted that since the control gate 14 is placed at an upper layer of the transfer electrodes 11, 13 for driving the horizontal registers, the control gate 14 may be formed with the third polycrystalline silicon layer and the metal wiring layer constituted by, e.g., aluminium and which provides a shunt wiring for the upper layer of the control gate 14 may be formed so that the contact regions serve to connect between the metal wiring layer and control gate 14 in order to reduce the specific resistance of the control gate. Fig. 6 shows a preferred embodiment of the structure of a solid-state frame interline type (FIT) imager according to the present invention. In the preferred embodiment, a solid-state frame interline type (FIT) image sensing device includes: an image portion having a multinumber of photo receiving elements arranged in the matrix form and a plurality of vertical registers, installed so as to correspond to respective vertical rows of the photo receiving elements, for transferring signal charges stored in the photo receiving elements in the vertical direction; and a storage portion, placed at the vertical transferred portion of the image portion, having a plurality of vertical registers temporarily storing the signal charges generated at the image portion. Shunt wiring films are formed independently on the transfer electrodes of the vertical registers of the image portion and on the transfer electrodes of the vertical registers of the vertical registers of the storage portion, respectively. The drive pulses are applied to the transfer electrodes corresponding to the shunt wiring films. The transfer electrodes are controlled by means of a quadruple drive pulse and are constituted by IM1, IM2, IM3, IM4, IM1, IM2, IM3, IM4, ---. In Fig. 6, numeral 29 1 through 29 4 denote shunt wiring films for the transfer electrodes IM1 through IM4 of the respective vertical registers of the image portion 21 and does not extend toward the storage portion 22. An origin of the shunt wiring films 29 1 through 29 4 is placed on the upper side of the image portion 21. The drive pulses IV1 through IV4 are applied to the respective transfer electrodes IM1 through IM4 of the image portion 21 via the image bus lines sequentially in orders from upper side. Numerals 30 1 through 30 4 denote shunt wiring films for the respective transfer electrodes ST1 through ST4 of the storage portion 22. The shunt wiring films receive drive pulses SV1 through SV4 for the vertical registers within the storage portion 22 via the bus line from the lower side and transferring the drive pulses via the transfer electrodes ST1 through ST4. Since, in the preferred embodiment, the shunt wiring films 29 1 through 29 4 of the image portion 1 and those 30 1 through 30 4 are mutually separated so as to operate independently of each other, a coupling capacitance across both image portion 21 and storage portion 22 is substantially reduced by half. Hence, a burden imposed on a clock generator which generates the drive pulses can be reduced, distortions in the drive pulses can be reduced and deteriorations in the operating characteristics in the image sensing device can be prevented. Although the drive pulses are transmitted to upper portions of the shunt wiring films 29 1 through 29 4 of the image portion 21 and to the lower portions of the shunt wiring films 30 1 through 30 4 of the storage portion 22, the drive pulses may be transmitted to upper and lower end portions of both shunt wiring films 29 1 through 29 4 and shunt wiring films 30 1 through 30 4 . It is noted that a combination of the first or second additional development with the preferred embodiment can be applied to the solid-state image sensing device according to the present invention. As described above, since in the solid-state image sensing device according to the present invention, the specific resistance of the signal transmission path of the drive pulses can be reduced, the drive pulse signal propagation delays in the solid-state image sensing device can remarkably be reduced and operating characteristics thereof can be improved. Thus, the solid-state image sensing device according to the present invention can be applied to HDVS. It will fully appreciated by those skilled in the art that the foregoing description has been made in terms of the preferred embodiment and various changes and modifications may be made without departing from the scope of the present invention which is to be defined by the appended claims.

Claims: A solid-state frame interline type (FIT) imager comprising: (a) an image portion (21) comprising a plurality of photo receiving elements arranged in a matrix form and a plurality of first vertical registers having first transfer electrodes (IM) for transferring in the vertical direction signal charges read out from the plurality of photo receiving elements; (b) a storage portion (22) comprising a plurality of second vertical registers having second transfer electrodes (ST) for temporarily storing the signal charges transferred from the image portion (21); (c) a plurality of horizontal registers, each having third transfer electrodes for transferring the signal charges from said storage portion (22) in the horizontal direction sharing the signal charges with respective ones thereof; (d) first shunt wirings (29) provided over the first transfer electrodes (IM) and connected at selected locations to said first transfer electrodes (IM) said first shunt wirings (29) being used for applying first drive pulses (IV) from a first bus line to the first transfer electrodes (IM); and (e) second shunt wirings (30) provided separately from said first shunt wirings (29) and provided over the second transfer electrodes (ST) and connected to said second transfer electrodes (ST) at selected locations, said second shunt wirings (30) being used for applying second drive pulses (SV) from a second bus line independent from the first bus line to the second transfer electrodes (ST), said imager further comprising: a control gate (3, 14) for controlling the transfer of signal charges between said horizontal registers in synchronization with said second drive pulses (SV). An imager as set forth in claim 1, wherein at least one of said shunt wirings comprises a wiring layer (10) connected in parallel to a respective drive pulse transmission path (3) for reducing the specific resistance along said transmission path (3). An imager as set forth in claim 2, wherein the specific resistance reducing means (9, 10) comprises the control gate (3, 14) formed by a first semiconductor layer located on a semiconductor substrate (1) surface at a first layer portion; a metal wiring layer (10) connected to the first semiconductor layer via contact regions (9); and the third transfer electrodes (5, 7) comprised of second and third semiconductor layers located between said metal wiring layer (10) and said first semiconductor layer without contacting said contact regions (9). An imager as set forth in claim 2, wherein the specific resistance reducing means (9, 10) comprises said third transfer electrodes (5, 7) comprised of semiconductor layers having different layers and said control gate (3, 14) formed with the wiring layer (10) placed above said semiconductor layers of said third transfer electrodes (5, 7). An imager as set forth in claim 4, wherein said semiconductor layers of said third transfer electrodes (5, 7) are comprised of first and second layers placed on an upper surface of a semiconductor substrate (1). An imager as set forth in claim 3, wherein said first semiconductor layer is formed of a polycrystalline silicon layer, said first transfer electrodes (5, 7) are formed of polycrystalline silicon layers sandwiched with an interlayer insulating layer (4, 6), and the metal wiring layer (10) is formed of a metal having a sheet resistance much lower than that for the control gate (3, 14). An imager as set forth in claim 6, wherein said metal wiring layer (10) is formed of aluminium. An imager as set forth in claim 4, wherein said third transfer electrodes (5, 7) are formed of a first layer of polycrystalline silicon (11) and of a second layer of polycrystalline silicon (13), the control gate (3, 14) is formed of a polyside (14) placed above said first and second layers of polycrystalline silicon (11, 13) and the control gate (3, 14) opposes a semiconductor substrate (1) at regions where the polycrystalline silicon layers (11, 13) are partially cut out. An imager as set forth in claim 8, wherein a metal wiring layer (10) is formed on a portion above said control gate (3, 14) and contact regions (9) are placed between the metal wiring layer (10) and control gate (3, 14) so as to form a connection therebetween. An imager as set forth in claim 4, wherein said first and second shunt wirings (29; 30) are first and second shunt wiring films (29), respectively.

Inventors: HARADA KOICHI, IIZUKA TETSUYA, WADA KAZUSHI, YAMAMURA MICHIO, YONEMOTO KAZUYA, HARADA, KOICHI, IIZUKA, TETSUYA, WADA, KAZUSHI, YAMAMURA, MICHIO, YONEMOTO, KAZUYA, HARADA, KOICHI, C/O SONY CORPORATION, IIZUKA, TETSUYA, C/O SONY CORPORATION, WADA, KAZUSHI, C/O SONY CORPORATION, YAMAMURA, MICHIO, C/O SONY CORPORATION, YONEMOTO, KAZUYA, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H01L27
IPC codes: H01L27