Pulse delay circuit having two comparators

Abstract: A pulse signal delay circuit comprises an input node (IN) for receiving a first pulse signal (P1), an output node (OUT) for outputting a second pulse signal (P3), a delay circuit (2) for delaying the first pulse signal (P1) to provide a delayed signal, a first com­ parator (5) for comparing the first pulse signal (P1) with the second pulse signal (P3) to output a first comparison result, and a second comparator (3) for comparing the first comparison result with the delayed signal to output a second comparison result.

Description: This invention relates to a pulse generation circuit used in an electronic circuit of a communication device such as a television receiver. Fig. 3 is a block diagram showing a pulse delay circuit. In operation, a pulse P1 input to an input terminal IN is supplied to a time constant circuit formed of a resistor R₁ and a capacitor C₁, via a buffer amplifier, so that a wave P2 which is delayed by time t₁ with respect to the pulse P1 can be derived from a point a . The wave P2 is input to the next stage comparator (COMP) 23, sliced at a voltage level V th , and output as an output wave P3 from an output terminal OUT. The waveforms P1 - P3 thus obtained are shown in Fig. 4. In the above described case, in order to generate the pulse P3 which is delayed by the time t₁ with respect to the pulse P1, it is only necessary to determine the delay time t₁ by the resistor R₁ and the capacitor C₁. However, in order to determine the pulse width of the pulse P3, it has been necessary to change the reference voltage V th to adjust the slice level of the wave P2 at the point a . The adjustment of the reference voltage V th must be effected each time the pulse delay time t₁ is changed, thus causing a troublesome problem. An object of this invention is to provide a pulse circuit capable of automatically adjusting the pulse widths of input and output signals to have a fixed relation therebetween. According to the present invention, there is provided pulse delay circuit comprising: an input node for receiving a first pulse signal; an output node for outputting a second pulse signal; delay means for delaying the first pulse signal from said first output node to provide a delayed signal; first comparator means for comparing a first signal proportional to the pulse width of the first pulse signal from said input node with a second signal proportional to the actual pulse width of the second pulse signal from said output node to output a first comparison result; and second comparator means for comparing the first comparison result from said first comparator with the delayed signal from said delay means to output the second pulse signal. With the above construction, a voltage (or current) which is proportional to the pulse width of the input pulse signal is compared with a voltage (or current) which is proportional to the pulse width of the output signal output from the circuit by means of the first comparator so as to generate a difference therebetween. When a voltage (or current) corresponding to the generated difference and a pulse delayed by the delay circuit are input to the second comparator, the pulse width of a pulse signal which has been delayed by the delay circuit is set to be equal to the pulse width of the input pulse signal and then the pulse is derived from the output terminal OUT. As a result, the pulse widths of the input and output pulse signals are automatically set equal to each other irrespective of the delay time set. Therefore, it becomes unnecessary to set the circuit parameters again. Further, it is also possible to set the ratio of the input pulse width to the output pulse width to a constant value, for example, 1:2 or 1:10, by changing and adjusting the circuit parameters. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a pulse circuit showing an embodiment of this invention; Fig. 2 is a circuit diagram of a pulse circuit showing an embodiment of this invention; Fig. 3 is a circuit diagram showing a pulse circuit to which this invention is not applied; and Fig. 4 is a timing chart for illustrating the operation of a pulse delay circuit as shown in Fig 3. Fig. 2 is a circuit diagram showing one embodiment of this invention. The construction shown in Fig. 2 is the same as that shown in the block diagram shown in Fig. 1. In Fig. 2, 1 denotes an example of a buffer amplifier. The buffer amplifier is constituted by a first transistor QP1 which is of PNP type, an NPN transistor QN1, and resistors R2 and R3 and is used to effect the impedance conversion with respect to an input pulse signal. 2 denotes an example of a delay circuit which is constituted by a resistor R1 and a capacitor C1 and functions to determine the delay time based on the time constant of the resistor and capacitor. Further, 3 denotes an example of a second comparator constituted by NPN transistors QN8 and QN9, PNP transistors QP8 and QP9, resistors R8, R9 and R10, and a fourth current source I₄. A difference current generated in the first comparator 5 is input to b and a wave of a delayed pulse signal is input to "a". The delayed pulse signal is sliced by a voltage at b. As a result, the pulse widths of the input pulse signal and output pulse signal are set equal to each other and the pulse signal is output from the output terminal OUT. 4 denotes an example of a first amplifier. This circuit is constituted by NPN transistors QN2 and QN3, PNP transistors QP2 and QP3, a first current source I₁, resistors R4 and R5, and a capacitor C₂. In this circuit, a current which is proportional to the pulse width of an input pulse signal is charged by means of QP3 into C2 and is output as a voltage from "d". Further, 5 denotes an example of the first comparator. The circuit is constituted by NPN transistors QN4 and QN5, PNP transistors QP4 and QP5, and a second current source I₂. The first comparator 5 compares voltages output from the first and second amplifiers with each other and converts a voltage difference into a current which is output as voltage from the point "b". The first comparator compares the pulse width of an input pulse signal and the pulse width of an output pulse signal with each other and generates a difference represented in terms of voltage. 6 denotes an example of the second amplifier. The circuit is constituted by PNP transistors QP6 and QP7, NPN transistors QN6 and QN7, resistors R6 and R7, a capacitor C3, and a third current source I₃. The second amplifier causes a current which is proportional to the pulse width of an output pulse to be charged into the capacitor C3 via the PNP transistor QP6 and output as a voltage from "e". This invention is not limited to the above embodiment and various modifications can be made. For example, the pulse widths of input and output pulse signals set in the circuit of this invention can be selectively set to be equal to each other or set in the ratio of an integral number if necessary. A concrete method of changing the relation between the input and output may be realized by changing the amplification factors of the comparators COMP-1 and -2, the gains of the AMP-1 and -2 or the like. More specifically, in the case of the COMP-1, the ratio of the areas of the transistors QN4, QN5, QP4 and QP5 in the block 5 is changed. That is, the amplification factor of the comparator COMP-1 can be changed by changing the ratio of the area of the transistors QN4 and QP4 to the area of the transistors QN5 and QP5 which is set to 1:x (at this time, the ratio of the area of the transistor QN4 to that of the transistor QP4 and the ratio of the area of the transistor QN5 to that of the transistor QP5 are kept unchanged). As a result, the slice level is changed and the pulse width of P3 can be changed. Further, in the case of the comparator COPM-2, the resistances of R8 and R9 in the block 5 in the embodiment of Fig. 2 are set to proper values without changing the ratio thereof. In the case of the gain of the AMP-1, the ratio of the areas of the transistors QP2 and QP3 in the block 4 is changed, and in the case of the gain of the AMP-2, the ratio of the areas of the transistors QP6 and QP7 in the block 4 is changed. In the conventional pulse delay circuit, the pulse width of the delayed pulse signal is set each time delay time is selectively set, but the proportional relation between the pulse widths of the input and output pulse signals can be automatically obtained with respect to a selectively set delay time or a given input signal if the circuit parameters are initially set by using the circuit construction of this invention. In this way, the operation of adjusting the pulse width of a pulse signal or an external device for effecting the operation can be alleviated or omitted. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A pulse delay circuit comprising: an input node (IN) for receiving a first pulse signal (P1); an output node (OUT) for outputting a second pulse signal (P3); delay means (2) for delaying the first pulse signal (P1) from said first input node (IN) to provide a delayed signal; first comparator means (5) for comparing a first signal (d) proportional to the pulse width of the first pulse signal (P1) from said input node (IN) with a second signal (e) proportional to the actual pulse width of the second pulse signal (P3) from said output node (OUT) to output a first comparison result; and second comparator means (3) for comparing the first comparison result from said first comparator (5) with the delayed signal from said delay means (2) to output the second pulse signal. A pulse delay circuit according to claim 1, characterized in that pulse widths of said first pulse signal (P1) and said second pulse signal (P3) are substantially equal to each other. A pulse delay circuit according to claim 1, characterized in that a ratio of a pulse width of said first pulse signal (P1) to that of said second pulse signal (P3) is set substantially to 1:2. A pulse delay circuit according to claim 1, characterized in that a ratio of a pulse width of said first pulse signal (P1) to that of said second pulse signal (P3) is set to an integral number. A pulse delay circuit according to any one of claims 1 to 4, characterized by further comprising first amplifier means (4), connected to said input node (IN), for amplifying said first pulse signal (P1) to provide an amplified signal to said first comparator (5). A pulse delay circuit according to claim 5, characterized by further comprising second amplifier means (6), connected to said output node (OUT), for amplifying said second pulse signal (P3) to provide another amplified signal to said first comparator (5). A pulse delay circuit according to any one of claims 1 to 6, characterized by further comprising a buffer circuit (1), connected between said input node (IN), for feeding said first pulse signal (P1) to said delay means (2). A pulse delay circuit according to any one of claims 1 to 7, characterized in that each of said first and second comparator means (3, 5) compares voltages of signals supplied thereto. A pulse delay circuit according to any one of claims 1 to 7, characterized in that each of said first and second comparators (3, 5) compares currents of signals supplied thereto. A pulse delay circuit according to any one of claims 1 to 9, characterized in that said delay means (2) includes a combination of a capacitor and a resistor.

Inventors: GOTO KUNIAKI, GOTO, KUNIAKI, GOTO, KUNIAKI, C/O INTELLECTUAL
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H03K5
IPC codes: H03K5