Process for making a multilevel interconnection structure

Abstract: A process for forming a connection between two layers of a multilayer interconnection in a semiconductor device comprises the steps of: forming a first conductive layer 3; forming on the first conductive layer a layer 4 for preventing stress- and/or electro-migration of the conductive layer; forming an opening 8 through the entire thickness of the migration-preventing layer 4, the opening having a diameter less than the width of the conductive layer, to expose the surface of the conductive layer; forming an interlayer insulating layer 9,11 on the migration-­ preventing layer 4 and the exposed surface of the conductive layer 3 to cover the layers and to fill the opening 8; forming a through-hole 6 having a diameter less than that of the opening in the insulating layer 9,11 to the surface of the conductive layer, the through-hole 6 lying entirely within the region of the filled opening so that the surface of the conductive layer is exposed but the periphery of the opening 8, i.e. the remaining part 41,42 of the migration-­ preventing layer 4, is not exposed; and forming a second conductive layer 15 on the interlayer insulating layer so that, during the formation of the second conductive layer, the through-hole 6 is filled with the conductive substance of said conductive layer 15 thereby electrically to connect the first and the second conductive layers. Since the periphery of the opening 8 is not exposed, an undercut of the subsequently formed through-hole 6 due to faster etching of the layer 4 is avoided, reducing the danger of contamination of the conductive connection.

Description: The present invention relates to a process for producing a semiconductor device having a multilayer interconnection composed of a plurality of conductive layers electrically separated from each other in an area other than the sites at which conductive layers are electrically interconnected via a through hole. Most semiconductor devices have a layer such as a TiN (titanium nitride) film formed on a conductive layer, such as an Al(aluminum)-interconnection, to prevent stress- and/or electro-migration of the conductive layer. In a semiconductor device having a multilayer interconnection composed of a plurality of conductive layers electrically separated from each other, the necessary interconnections between these cnoductive layers are effected through a through-hole formed in an interlayer insulating layer inserted between and electrically separating the conductive layers. Referring to Fig. 1, in a process for producing a semiconductor device on a semiconductor substrate 201 having an insulation substrate 202 formed thereon, a through hole is conventionally formed in the following manner: an Al conductive layer 20 and an overlying TiN layer 21 are uniformly covered with a SiO₂ (silicon oxide) hillock-preventing insulating layer 22; a flattening insulating layer 23 and a PSG (phosphosilicate glass) layer 24 are then formed, in that order (Fig. 1 (a)); and the SiO₂ and the PSG layers 22, 24 are patterned by a photoetching method using a photoresist 25, to open a through-hole 26 (Fig. 1 (b)). A fluorine-based gas is usually used as an etchant to form the through-hole 26 and, during the etching, the TiN layer 21 is also etched and the through-hole 26 also extends through the TiN layer 21. TiN is etched by the fluorine-based gas at a higher rate than the SiO₂ or PSG of the layers 22 or 24, and thus the sideways etching of the TiN layer 21 is excessive, with the result that the SiO₂ and the PSG layers 22, 24 overhang the TiN layer 21, i.e. a side groove 27 is formed between the TiN layer 21 and the SiO₂ layer 22, or the through hole 26 has a broadened bottom. In a subsequent process step, when a conductive substance 28 is deposited in the through hole 26 and a heat treatment is carried out, any residue present within the side groove 27 is evaporated and diffuses to the interface between the Aℓ conductive layer 20 and the deposited conductor 28. This causes a problem in that the contact resistance between these two conductors 20 and 28, and in turn the two conductive layers, is undesirably increased. For more background on the formation of contacts between layers of metallization reference may be made to US 4507852 (assignee Rockwell), which uses an intermediate silicide layer to overcome the problem of oxide formation on aluminium, and EP-A1-0287096 (Toshiba), in which shaped via holes are formed using multiple etching steps. It is desirable to provide a process for producing a semiconductor device in which an interconnection between the conductive layers of a multilayer interconnection is ensured without an increase of the contact resistance. According to the claim 1 of the present invention, there is provided a process for producing a semiconductor device having a multilayer interconnection composed of a plurality of conductive layers electrically interconnected via a through hole and electrically separated from each other by interposed insulating layers in other areas, in which at least one of the conductive layers has a layer formed thereon for preventing stress- and/or electro-migration, comprising the steps of: forming a first conductive layer; forming on the first conductive layer a layer for preventing stress- and/or electro-migration in the conductive layer; forming an opening through the entire thickness of the migration-preventing layer, the opening having a diameter less than the width of the conductive layer so as to expose a surface of the conductive layer within the region surrounded by the periphery of the opening; forming an interlayer insulating layer on the migration-preventing layer and the exposed surface of the conductive layer to cover these layers and to fill the opening; forming a through-hole having a diameter less than that of the opening and extending through the entire thickness of the interlayer insulating layer to the surface of the conductive layer within the region of the filled opening so that the surface of the conductive layer is exposed but the periphery of the opening is not exposed; and forming a second conductive layer on the interlayer insulating layer so that, during the formation of the second conductive layer, the through-hole is filled within the conductive substance of the second conductive layer, thereby electrically connecting the first and second conductive layers. In this way, since the through-hole has a diameter less than that of the opening previously formed in the migration-preventing layer, which can be a TiN film such as 21, and is formed through the opening after the opening is filled with the interlayer insulating substance without exposing the periphery of the opening, the migration-preventing layer is protected against the etching step used to form the through-hole, e.g. using a fluorine-based gas. This protection eliminates the excessive sideways etching of the migration-preventing layer, i.e. the overhang of the SiO₂ and PSG insulation layers 22, 24 or the formation of a side groove 27. The present invention thus prevents accumulation of a residue which would otherwise remain in the base of the through-hole, and eliminates any undesirable increase of the contact resistance, thereby ensuring a good interconnection between the conductive layers. An example of the invention will now be described with reference to the drawings, in which: Figures 1(a) and (b) are sectional views showing a proposed process sequence; and Figures 2(a) to 2(i) are sectional views showing a process sequence embodying the present invention. In Fig. 2(a), an interconnection-patterned layer 1 has a predetermined pattern of a conductive interconnection of a semiconductor device and is composed of a 0.5 µm (1 µm = 1 micrometer = 10³ nm) thick Aℓ conductive layer 3 formed on a PSG (phosphosilicate glass) insulating substrate 2 on a semiconductor substrate or wafer 101 and a 500 Å (10 Å = 1 nm) thick TiN migration-preventing layer 4 formed by sputtering on the Aℓ conductive layer 3. The migration-preventing layers usually used are layers of silicides of refractory metals such as MoSi x (molybdenum silicide) and TaSi x (tantalum silicide) and nitrides of refractory metals such as TiN. Other silicide such as WSi x (wolfram (tungsten) silicide) and TiSi x (titanium silicide) can be used. Intermetallic compounds of refractory metals such as TiW also may be used, although particular care must be taken to prevent a reaction between the TiW and Aℓ of the conductive layers. The interconnection between the A1 conductive layer 3 and another not-shown conductive layer to be formed above the A1 conductive layer 3 is realized in the following sequence. A 1.5 µm thick photoresist layer 5 is applied on the insulating substrate 2 and the patterned layer 1 and subjected to exposure and development treatments to form a window 7 in the photoresist layer 5 and on the TiN migration-preventing layer 4. The window 7 has a diameter of 2.1 µm, which is smaller than the width 2.9 µm of the layer 1 or the layers 3 and 4 and greater than the diameter 1.3 µm of a through hole to be later formed (Fig. 2 (b)). Then, using the photoresist layer 5 as a mask, the TiN migration-preventing layer 4 of the patterned layer 1 is subjected to an etching treatment using a gaseous mixture of CHF₃ and CF₄ as an etchant to form an opening 8 in the TiN migration-preventing layer 4, the opening 8 having substantially the same diameter (2.1 µm) as that of the window 7, i.e., a diameter smaller than the width of the patterned layer 1 or the layers 3 and 4 and greater than the diameter of a through hole to be later formed, and after the etching the photoresist layer 5 is removed (Fig. 2 (c)). The non-etched, retained parts 41 and 42 of the TiN layer 4 have a width of 0.4 µm. A preferred etching condition is, for example, an etchant gas composition of 100 sccm CHF₃ and 100 sccm CF₄ in terms of gas flow rate, a plasma power of 700 W, and a background pressure 0.3 Torr. AnSF₆ gas also may be used as an etchant gas under a preferred etching condition of, for example, a flow rate of 200 sccm, a plasma power of 300 W, and a background pressure of 0.2 Torr. The latter SF₆ etching provides a faster etching rate than the former mixed gas etching. A 3000Å thick SiO₂ hillock-preventing insulating layer 9 is then formed on the substrate 2 and the layer 1 or the layers 3 and 4 by sputtering, or chemical vapor deposition with or without plasma, etc. (Fig. 2 (d)). Sputtering is preferred as a harder SiO₂ layer 9 is obtained thereby, and a harder layer 9 more effectively prevents the formation of hillocks in the conductive layer 3. During the formation of the SiO₂ layer 9, the opening 8 is filled with the insulating substance of this layer 9. A 4000 Å thick SOG (spin-on-glass) layer 10 is formed on the SiO₂ layer 9 by spin-coating and heating for setting-up as shown by a double-dotted line in Fig. 2 (e), and is then etched back by a thickness of 2400 Å to flatten the vicinity of the interconnection-patterned layer 1 and improve the step-coverage (shown by a solid line in Fig. 2 (e)). An insulating layer 11 such as PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) is then formed by chemical vapor deposition and a photoresist layer 12 is applied. The photoresist layer 12 is subjected to exposure and development treatments to form a window 13 having a diameter necessary for forming a through hole to be later formed (which diameter is smaller than that of the opening 8) above and within the region of the opening 8 (Fig. 2 (f)). Then, using the photoresist layer 12 as a mask, the upper portion of the PSG layer 11 is isotropically etched by a plasma etching method using a gaseous mixture of CF₄ and O₂ as an etchant. This isotropic etching gives a funnel-shape etched portion (or the top portion of a through hole) as shown in Fig. 2 (g), which ensures an improved step-coverage during the forming of another conductive layer to be formed later on the PSG insulating layer 11 (to be later described with reference to Fig. 2 (i)). A preferred condition for the isotropic etching is, for example, a gas flow rate of 800 sccm CF₄ and 130 sccm O₂, and a plasma power of 1.0 kW, and a background pressure of 1.0 Torr. Wet etching using an HF solution containing ammonium fluoride or a buffered HF solution also may be used for the isotropic etching when a relatively rough distribution of the etching rate is acceptable. After the isotropic etching, using the photoresist layer 12 again as a mask, the remaining PSG layer 11 and SiO₂ layer 9 are anisotropically etched by a reactive ion etching method using a gaseous mixture of CHF₃ and CF₄ as an etchant, to complete a through hole 6 extending through the entire thickness of the interlayer insulating layers 9 and 11 to the surface of the A1 conductive layer 3 within the region of the filled opening 8, so that the surface of the A1 conductive layer within the region of the opening 8 is exposed but the periphery of the opening 8 is not exposed (Fig. 2 (h)). The non-etched, retained parts 91 and 92 of the SiO₂ insulating layer 9 inside the periphery of the opening 8 have a wall thickness of 0.4 µm. A preferred condition for the anisotropic etching is, for example, a gas flow rate of 100 sccm CF₄ and 100 sccm CHF₃, a plasma power of 700 W, and a background pressure of 0.3 Torr. The through hole 6 having a diameter 1.3 µm, which is less than that of the opening 8 (2.1 µm) previously formed in the TiN migration-preventing layer 4, is formed through the opening 8 after the opening is filled with insulating substances PSG and SiO₂ of interlayer insulation layers 9 and 11 in a manner such that the periphery of the opening 8 is not exposed but covered by a 0.4 µm thick non-etched, retained wall of SiO₂ insulating layer 9, and therefore, the TiN migration-preventing layer 4 is protected against etching (reactive ion etching) using the fluorine-based gas (a gaseous mixture of CHF₃ and CF₄) during the forming of the through hole 6. This protection eliminates the excessive sideways etch of the TiN migration-preventing layer 4, i.e., the overhang of the SiO₂ and the PSG interlayer insulating layers 9 and 11 or the formation of a side groove 27, which was conventionally unavoidable as shown in Fig. 1 (b). A preferred ratio of the isotropic/anisotropic etching depths is about 6:4. Another conductive layer 15 having a thickness of 1.0 µm is then formed on the interlayer insulating layer 11 so that, during the forming of this layer 15, the through hole 6 is filled with the conductive substance 14 of the conductive layer 15 to electrically connect two conductive layers 3 and 15 (Fig. 2 (i)). A good interconnection between the conductive layers 3 and 15 is ensured, since sites of a possible residue such as the conventional side groove 27 are eliminated and any residue present in the bottom of the through hole can be easily removed. Experiments showed that, in the through holes formed in the above-mentioned process according to the present invention, the occurrence of voids due to such side grooves was decreased to less than one third of that occurring during the conventional through holes forming process. Note, although a process for producing a semiconductor device having an A1 conductive layer is described, the present inventive process also may be applied to semiconductor devices having conductive layers of other alloys such as A1-1%Si-0.1%Cu alloy, A1-0.5%Ti-0.1%Cu alloy, etc. having a higher mechanical strength than unalloyed or pure A1 metal.

Claims: A process of producing a semiconductor device having a multilayer interconnection composed of a plurality of conductive layers (3, 15) electrically interconnected via a through-hole and electrically separated from each other by interposed insulating layers (9-11) in other areas, in which at least one of the conductive layers has a layer formed thereon for preventing stress- and/or electro-migration, comprising the steps of: forming a first conductive layer (3); forming on the first conductive layer (3) a layer (4) for preventing stress- and/or electro-migration in the conductive layer; patterning the first conductive layer (3) and the migration-preventing layer (4) to form an interconnection-patterned layer (1); forming an opening (8) through the entire thickness of the migration-preventing layer (4), the opening (8) having a diameter less than the width of the interconnection-patterned layer (1), so as to expose a surface of the conductive layer (3) within the region surrounded by the periphery of the opening; forming an interlayer insulating layer (9, 11) on the migration-preventing layer (4) and the exposed surface of the conductive layer (3) to cover these layers and to fill the opening (8); forming a through-hole (6) having a diameter less than that of the opening (8) and extending through the entire thickness of the interlayer insulating layer to the surface of the conductive layer (3) within the region of the filled opening so that the surface of the conductive layer is exposed but the periphery of the opening (8) is not exposed; and forming a second conductive layer (15) on the interlayer insulating layer so that, during the formation of the second conductive layer, the through-hole (6) is filled within the conductive substance of the second conductive layer (15), thereby electrically connecting the first and second conductive layers. A process according to claim 1, wherein the formation of the through-hole (6) is carried out by an etching comprising the following two steps: isotropically etching the upper portion of the interlayer insulating layer (11) proceeding from its free surface; and anisotropically etching the remainder of the thickness until the through-hole is completed, exposing the surface of the first conductive layer (3). A process according to claim 2, wherein the isotropic etching is carried out by a dry etching. A process according to any one of claims 1 to 3, wherein the migration-preventing layer (4) comprises a layer substantially composed of TiN. A process according to claim 4, wherein the TiN migration-preventing layer is subjected to an etching treatment using a gaseous mixture of CHF₃ and CF₄ as an etchant in forming the opening (8). A process according to any of claims 1 to 5, wherein the interlayer insulating layer is composed of a hillock-preventing layer (9) and a PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) layer (11). A process according to claim 6, wherein the hillock-preventing layer (9) consists of SiO₂. A process according to claim 2 and claim 6 or 7, wherein the isotropic etching of the upper portion of the interlayer insulating layer (11) is carried out by a plasma etching method using a first gaseous mixture comprising fluoromethane and/or fluoroethane as an etchant and the anisotropic etching of the remainder of the thickness of the interlayer insulation layer is carried out by a reactive ion etching method using a second gaseous mixture comprising fluoromethane and/or fluoroethane as an etchant. A process according to claim 8, wherein the first gaseous mixture further comprises oxygen. A process according to any preceding claim, wherein the first and/or second conductive layers (3, 14) are composed of Aℓ, or an aluminium-based alloy containing at least one of silicon, copper, titanium and tungsten as an alloying element.

Inventors: NAGATA SHUNICHI, NAGATA, SHUNICHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H01L21
IPC codes: H01L23, H01L21