Semiconductor device

Abstract: The invention concerns a semiconductor device comprising a semiconductor chip (15) having a reception circuit for removing a direct-current component of a reception signal by the utilization of a capacitor and a metal film formed on the back side thereof; a first conductive pattern (12) formed on an electrically insulating substrate (11) and set at a common reference voltage for device; and a second conductive pattern (13) formed on said substrate (11) to be electrically insulated from said first conductive pattern (12), fixed to said metal film, and electrically connected to said capacitor. This arrangement results in a high receiving sensitivity and a wide receiving band of the reception circuit, because there is almost no floating capacitance present in the capacitor.

Description: Background of the Invention The present invention relates to a semiconductor device used in a light reception circuit section or the like in an optical data link or an optical CATV system. A conventional light reception circuit of this type is shown in Fig. 1, cf. "Semiconductor Devices for Optical Communication " edited by H. Kressel, 1980, pages 89 to 94, for example. A light signal is received by a light-receiving element 1 and converted into a voltage signal by a resistor R L . A direct-current component is removed by a capacitor C c from the reception signal which is converted into the voltage signal, and the reception signal is amplified and demodulated by an amplifier 2. The resistor R L , the capacitor C C , and the amplifier 2 are formed on the same integrated circuit (IC) chip 3. Generally, the resistor R L has a resistance of several hundreds ohms to 10 kΩ, and the direct-current component cutoff capacitor C C has a capacitance of several pico-farad to several hundreds pico-farad. A junction capacitance C PD of about 0.5 pF is present in a p-n junction of the light-receiving element I, a floating capacitance C CG (to ground) is present in the capacitor C C , and an input capacitance C IN is present in an input section of the amplifier 2. When an input resistance of the amplifier 2 is given by R IN , a high-pass cutoff frequency F H and a low-pass cutoff frequency F L of the reception signal are expressed by the following equations, respectively. F H = 1/[2π (R L //R IN ) · (C PD + C IN + C CG )] F L = 1/[2π (R L //R IN ) · C C ] Figs. 2(A) and 2(B) show the inside of a package when the IC chip is packaged. Fig. 2(A) is a plan view of the IC chip, and the Fig. 2(B) is a side view of the IC chip. A common ground pattern 5 which is set at a common reference voltage for the circuit is formed on a ceramic substrate 4, and IC chip 3 is die-bonded on the ground pattern 5 through a back metal formed on the back of the IC chip 3. A reference potential of an inner circuit of the IC chip 3 is set to be equal to a potential of the ground pattern 5 by means of a bonding wire. A signal terminal pattern 6 electrically isolated from the common ground pattern 5 is wire-bonded with external terminals of the IC chip 3 and electrically connected to frame lead pins. In the above conventional device arrangement, when the resistance of the resistor R L is increased to improve receiving sensitivity of the circuit, an S/N ratio showing a signal-to-noise ratio is increased, thereby improving the receiving sensitivity. However, as understood from equation (1), the high-pass cutoff frequency F H is decreased. When the resistance of the resistor R L is constant, the high-pass cutoff frequency F H is increased proportional to a decrease in capacitance of (C PD + C IN + C CG ). In order to decrease the low-pass cutoff frequency F L , as understood from equation (2), when the resistance of the resistor R L is constant, the capacitance of the direct-current component cutoff capacitor C C must be large. For this reason,an electrode pattern 7 for the capacitor C C occupies a large area in the IC chip 3 as shown in Fig. 3. Therefore, the floating capacitance C CG present between the electrode pattern 7 and the ground pattern 5 is increased, thereby decreasing the high-pass cutoff frequency F H . In addition, when the capacitance of the capacitor C C is decreased to decrease the floating capacitance C CG , the low-pass cutoff frequency F L is increased, thereby increasing jitter. Patent Abstracts of Japan, Vol. 12, No. 30 (E-578) [2877]; & JP-A-62 186 552 disclose a package for a high-frequency semiconductor element. The package comprises a ceramic substrate on which a ground potential conductor layer is provided other than in the vicinities of the input signal lines and output signal lines of the semiconductor element. A power-supply conductor pattern is formed on the ground potential layer through a dielectric layer. The semiconductor element is electrically connected to the signal lines and the power-supply conductor pattern by bonding wires. Summary of the Invention It is an object of the present invention to provide a semiconductor device having a high receiving sensitivity and a wide receiving band. The invention is defined in claim 1. Particular embodiments of the invention are set out in the dependent claims 2 and 3. Thus, a variation in voltage of the capacitor formed within the semiconductor chip is substantially equal to a variation in voltage of the second conductive pattern underlying the capacitor. As a result, there is almost no floating capacitance in the capacitor for removing a direct-current component of the reception signal. For this reason, a semiconductor device having a high receiving sensitivity and a wide receiving band can be provided. The device according to the present invention is effectively employed in a high-speed and wide-band communication system. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. Brief Description of the Drawings Fig. 1 is a circuit diagram showing a light reception circuit on a conventional IC chip mounted on a semiconductor device; Fig. 2A is a plan view showing the inside of the semiconductor device on which the conventional IC chip shown in Fig. 1 is mounted; Fig. 2B is a side view showing the inside of the conventional semiconductor; Fig. 3 is a view showing a electrode pattern of the conventional IC chip shown in Fig. 1; Fig. 4A is a plan view showing the inside of a semiconductor device according to an embodiment of the present invention; Fig. 4B is a side view showing the inside of the semiconductor device shown in Fig. 4A; and Fig. 5 is a circuit diagram showing a light reception circuit on an IC chip mounted on the semiconductor device shown in Figs. 4A and 4B. Detailed Description of the Preferred Embodiment Figs. 4A and 4B show an embodiment of the present invention, in which Fig. 4A is a plan view and Fig. 4B is a side view. A ceramic substrate 11 is made of an electrically insulating material such as alumina (Al₂O₃). The substrate 11 is metallized by gold-palladium or silver-palladium to form a ground pattern 12 in a wide area. The ground pattern 12 is set at a common reference voltage of each semiconductor circuit chip mounted on the substrate 11. The metal used in metallization is patterned by etching techniques to form an island-like die area pattern 13 electrically isolated from the ground pattern 12. By patterning, a signal terminal pattern 14 having an elongated shape is formed to be electrically isolated from the ground pattern 12. An IC chip 15 which incorporates a light reception circuit is die-bonded on the die area pattern 13, and a metal film formed on the back side surface of the IC chip is electrically connected and fixed to the die area pattern 13. The external terminals of the IC chip 15 are wire-bonded on the signal terminal pattern 14, thereby transferring a signal from the circuit to a frame lead pin (not shown) connected to the signal terminal pattern 14. One of the external terminals is wire-bonded on the die area pattern 13. Fig. 5 shows a circuit incorporated in the IC chip 15. An external terminal 16 of the IC chip 15 is connected to a light-receiving element 17 such as a photodiode outside the chip and connected to a resistor R L inside the chip. That is, the light-receiving element 17 and the resistor R L are connected in series with each other and the resistor R L is electrically connected to the ground pattern 12. The external terminal 16 is connected to one terminal of a capacitor C C inside the chip, and the other terminal of the capacitor C C is connected to the input terminal of a buffer amplifier 18 which is a non-inverting amplifier having a amplification factor of 1. The buffer amplifier 18 is constituted by a source follower circuit and the like, and an output from the amplifier 18 is sent to an amplifier 19. The output terminal of the amplifier 19 is connected to an external terminal 20, and the external terminal 20 is connected to a receiver (not shown). The output terminal of the buffer amplifier 18 is connected to an external terminal 21, and the external terminal 21 is wire-bonded on the above die area pattern 13 to be electrically connected with the above die area pattern. In the above arrangement, when a light signal is received by the light-receiving element 17, the light signal is converted into an optical output current. The optical output current is converted into a voltage signal by the resistor R L , and then a direct-current component of the voltage signal is removed by the capacitor C C . The reception signal from which the direct-current component is removed is amplified and demodulated by the amplifier 19 through the buffer amplifier 18. The demodulated signal is sent to the receiver through the external terminal 20. The reception signal output from the buffer amplifier 18 is sent to the die area pattern 13 through the external terminal 21. For this reason, the voltage of the capacitor C C is applied to the die area pattern 13. Therefore, a variation in voltage of the capacitor C C is substantially equal to a variation in voltage of the die area pattern 13 underlying the IC chip 15. That is, the amplitudes of the voltages at the capacitor C C and the metal film formed on the back side of the IC chip 15 are equal to each other, and the phases of their voltages are equal to each other. In this case, a floating capacitance C CG to ground (die area pattern 13) of the capacitor C C is parasitically formed between the electrode of the capacitor C C and the metal film (die area pattern 13). That is, since the floating capacitance C CG defines a rate of ,variation in charge accumulated between both the electrodes to a variation in voltage applied between both the electrodes, the floating capacitor C CG is almost not present. For this reason, the high-pass cutoff frequency F H of the reception signal expressed in equation (1) can be increased because the floating capacitance C CG can be neglected. The capacitance of the direct-current component cutoff capacitor C C can be increased regardless of the floating capacitor C CG , and the low-pass cutoff frequency F L expressed in equation (2) can be decreased. Therefore, the width of a receiving band of the circuit is increased. In addition, since the capacitance C CG is decreased in equation (1) and the capacitance C C is increased in equation (2), the resistance of the resistor R L can be increased, thereby improving the receiving sensitivity of the circuit. In the light reception circuit of this type, the low-pass cutoff frequency F L is generally set to be less than 1/100 to 1/1,000 of the high-pass cutoff frequency F H . Therefore, in order to form a light reception circuit having, e.g., a bandwidth of 500 MH z , the low-pass cutoff frequency F L must be set to be less than 5 MH z . When a minimum receiving sensitivity is set at -30 dBm, the resistor R L connected to the light-receiving element 17 in series must have a resistance of 1 kΩ at least. In this case, the capacitance of the direct-current component cutoff capacitor C C can be calculated by substituting each constant in equation (2) expressing the low-pass cutoff frequency F L as follows. In this case, since the resistance of the resistor R L is sufficiently larger than that of the input resistor R IN of the amplifier 19, the resistance of the parallel combination resistor R L //R IN of the resistor R L and the resistor R IN is substantially equal to that of the resistor R L . 5 × 10 6 s -1 = 1/(2π · 1 × 10 3 .Ω.C C ) ∴ C C = 31.8 pF A capacitance per unit area of a capacitor which can be monolithically formed on the IC chip falls within the range of about 0.05 to 0.1 fF/(µm)². In this case, even if a capacitor having a capacitance per unit area of 0.1 fF/(µm)² can be formed, the area of the capacitor C C is 318,000 (µm)². In the conventional arrangement shown in Figs. 1 and 2, when the capacitor C C having this area is formed, a floating capacitance C CG (to ground) of the capacitor C C is as follows. In this case, assume that the IC is made of gallium arsenide (GaAs), that the thickness of a GaAs substrate is normally set to be 400 µm, and that its specific dielectric constant ε is set to be 13. C CG = ε o · ε · (318,000 / 400) = 92 fF The sum (C PD + C IN ) of the junction capacitance C PD of the light-receiving element 1 and the input capacitance C IN of the amplifier 2 falls within the range of 0.4 to 0.6 pF. For this reason, in a conventional device arrangement, the ratio of the floating capacitance C CG to the sum of the capacitances is about 20%, and the floating capacitance cannot be neglected. Therefore, the denominator of equation (1) is increased, and the high-pass cutoff frequency F H is decreased due to the influence of the floating capacitance C CG . As a result, the bandwidth of the signal received by the circuit is narrowed. However, according to the present invention, the variation in voltage of the capacitor C C is substantially equal to the variation in the die area pattern 13 as described above. Therefore, even when the capacitor C C has the large area of 318,000 (µm)², the floating capacitance C CG is not almost present in the die area pattern 13. For this reason, the bandwidth of the signal received by the reception circuit is large, and the receiving sensitivity of the circuit is improved.

Claims: A semiconductor device comprising a reception circuit having a capacitor (C C ) for removing a direct-current component of a reception signal, a semiconductor chip (15) mounted on an electrically insulating substrate (11), said chip (15) having a metal film formed on the back side thereof and the reception circuit incorporated therein, a first conductive pattern (12) formed on said substrate (11); and a second conductive pattern (13) formed on said substrate (11) to be electrically insulated from said first conductive pattern (12) and electrically connected to said capacitor (C C ) ; wherein said semiconductor chip (15) is die-bonded on said second conductive pattern (13) and said metal film formed on the back side of the semiconductor chip (15) is fixed and electrically connected to said second conductive pattern (13). A device according to claim 1, wherein said reception circuit incorporated in said semiconductor chip (15) comprises: a resistor (R L ) connected in series with a light-receiving element (17) arranged outside said circuit, said capacitor (C C ) a terminal of which is connected to a connection point between said light receiving element (17) and said resistor (R L ) for removing a direct-current component of a reception signal, a non-inverting amplifier (18) having an input terminal which is connected to the other terminal of said capacitor (C C ), said non-inverting amplifier (18) having an amplification factor of 1, and an amplifier (19) having an input terminal which is connected to an output terminal of said non-inverting amplifier (18), said output terminal of said non-inverting amplifier (18) being electrically connected to said second conductive pattern (13). A device according to claim 2, wherein said output terminal of said non-inverting amplifier (18) is wire-bonded on said second conductive pattern (13).

Inventors: SHIGA NOBUO, SHIGA, NOBUO, SHIGA, NOBUO, C/O YOKOHAMA WORKS
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES, LTD.
Application year: 1990
Main classification: H01L23
IPC codes: H01L21, H01L31, H01L23, H01L27