Bi-CMOS circuit

Abstract: The Bi-CMOS circuit comprises a first transistor (Mn1) comprising an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal (V IN ) and that supplies a first current (I B″ ) to the base of an output transistor (Q₃) when the first transistor is turned on. An active pull-down current supplying circuit (2) is connected to the gate electrode of the first transistor and for supplying a second current (I B′ ), which is an active pull-down current, to the base of the output transistor so that the first and second currents can be supplied to the base of ths output transistor.

Description: The present invention relates to a logic circuit, and more particularly to a logic circuit of Bi-CMOS construction used for driving capacitive load. DESCRIPTION OF THE PRIOR ART In the Bi-CMOS process that adds a part of a MOS process to a normal bipolar process and that forms bipolar elements and MOS elements at the same time, a logic circuit of high performance can be made by building a bipolar circuit having advantages of high accuracy analog processing and large power drive and a CMOS circuit having advantages of high integration and low power consumption, together on the same IC chip. FIG. 7 schematically shows a conventional logic circuit which forms an inverter with the Bi-CMOS process. In the figure, M n1 is an input transistor made from an N-channel MOS transistor, Q 1 and Q 2 are off-buffer transistors made from bipolar transistors, and Q 3 is an output transistor made from a bipolar transistor. R 1 through R 4 are resistors, and D 1 , D 2 schottky barrier diodes.C is a capacitive load, V IN an input signal, and V OUT an output signal. In a construction such as this, in order to obtain a high drive capability, Q 1 and Q 3 normally comprise transistors with schottky barriers, and alternatively, the areas of Q 2 and Q 3 are increased. In the conventional logic circuit described above, and in particular when the area of the transistor Q 3 is increased to obtain a high drive capability, it is necessary to increase current that is supplied to the base of the output transistor Q 3 . However, since the MOS transistor (M n1 ) is used as a source of the base current, a sufficient amount of the base current cannot be supplied to the output transistor Q 3 . Consequently, there is the drawback that the output transistor Q 3 is turned on very slowly, that is, the propagation delay time t PHL of the output signal V OUT increases. Accordingly, it is an object of the present invention to make the turn-on speed of the output transistor Q 3 faster and shorten the propagation delay time t PHL of the output signal V OUT . US 4 845 386 discloses an output buffer circuit in which the signal propagation time is reduced by supplying an output bipolar transistor base from a Darlington pair. EP 0 209 805 discloses a Bi-CMOS circuit comprising: a gate circuit having an input and an output and comprising a first, N-channel MOS transistor which is turned on and off in response to the logic state of the input signal and which supplies a first current to the base of an output transistor when the first transistor is turned on. According to the invention, the circuit further comprises an active pull-down current supplying circuit, thc input of which is connected to the gate electrode of said first transistor, for supplying an active pull-down current to the base of said output transistor so that said first current and the active pull-down current can be supplied to the base of said output transistor, the current supplying circuit having a supply transistor which feeds the active pull-down current to the base of the output transistor when the input signal makes a transition from a low state to a high state or from a high state to a low state, the supply transistor being driven by a supply voltage of the current supplying circuit. The active pull-down current supplying means may comprise a second transistor made from a P-channel MOS transistor and having its gate electrode connected to the gate electrode of the first transistor, a third transistor made from an N-channel MOS transistor and having its gate electrode connected to the gate electrode of the second transistor, the third transistor being connected in series with the second transistor, and a fourth transistor comprising a bipolar transistor and having its base connected to the third transistor and its emitter connected to the base of the output transistor. The second transistor may be substantially identical in area to the third transistor. The second transistor may also be greater in area than the third transistor. The active pull-down current supplying means may also comprise a second transistor made from a P-channel MOS transistor and having its gate electrode connected to the gate electrode of the first transistor, a third transistor made from an N-channel MOS transistor and having its gate electrode connected to the gate electrode of the second transistor, the third transistor being connected in series with the second transistor, a fourth transistor made from a P-channel MOS transistor, a fifth transistor made from an N-channel MOS transistor and having its gate electrode connected to the gate electrode of the fourth transistor, the fifth transistor being connected in series with the fourth transistor, a line between the second and third transistors being connected to a line between the fourth and fifth transistors, and a sixth transistor made from a bipolar transistor and having its base connected to the fifth transistor and its emitter connected to the base of the output transistor. In the present invention, during the turn-on transition period of the first transistor (corresponding to the conventional input transistor M n1 ), the second and third transistors are turned on, and the fourth transistor comprising a bipolar transistor is turned on by the current that flows through the second and third transistors. Consequently, the current that flows through both first transistor and the fourth transistor is supplied to the base of the output transistor (corresponding to the transistor Q 3 ), and the turn-on speed of the output transistor is thus made greater. Preferably, the gate circuit further comprises a second, P-channel MOS transistor, also turned on and off in response to the logic state of the input signal, the gate circuit supplying a first current to the base of the output transistor when the first and second transistors are turned on; and in which the active pull-down current supplying circuit is connected to the gate electrodes of said first and second transistors. Alternatively, the gate circuit may further comprise second and third transistors respectively comprising a P-channel MOS transistor and an N-channel MOS transistor that are turned on and off in response to the logic state of the input signal and which supply a second current to the base of a second output transistor when the second and third transistors are turned on, in which the active pull-down current supplying circuit supplies the active pull-down current to the base of said output transistor so that said first current and the active pull-down current can be supplied to the base of said output transistor, and in which there is further provided : a second active pull-down current supplying circuit, the input of which is connected to the gate electrodes of said second and third transistors, for supplying a second active pull-down current to the base of said second output transistor so that said second current and said second active pull-down current can be supplied to the base of said second output transistor, the second current supplying circuit having a second supply transistor which feeds the second active pull-down current to the base of the second output transistor, the second supply transistor being driven by a supply voltage of the second current supplying circuit, said active pull-down current supplied through said active pull-down current supplying circuit being supplied to the base of said output transistor when said input signal makes a transition from a low to a high, and said second active pull-down current supplied through said second active pull-down current supplying circuit being supplied to the base of said second output transistor when said input signal makes a transition from a high to a low. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and advantages will become apparent from the following detailed description when read in conjunction with the accompanying drawings wherein : FIG. 1 is a schematic view illustrating an embodiment of a Bi-CMOS circuit in accordance with the present invention; FIG. 2 is a timing diagram of the FIG. 1 embodiment; FIG. 3 is a schematic view illustrating part of a Bi-CMOS circuit in accordance with the present invention; FIG. 4 is a waveform diagram of the output signals from the FIG. 1 embodiment; FIG. 5 is a schematic view illustrating a second embodiment of the Bi-CMOS circuit in accordance with the present invention; FIG. 6 is a schematic view illustrating a third embodiment of the Bi-CMOS circuit in accordance with the present invention; and FIG. 7 is a schematic diagram of a conventional logic circuit. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now in greater detail to the drawings and initially to FIGS. 1 through 4, there is shown a preferred embodiment of a Bi-CMOS circuit constructed in accordance with the present invention. The same reference characters and numbers will be applied to the corresponding parts as FIG. 5. Reference numeral 1 denotes a gate part that functions as an inverter. The gate part 1 comprises off-buffer transistors Q 1 and Q 2 each made from a bipolar transistor, an output transistor Q 3 made from a bipolar transistor, and an input transistor (first transistor) M n1 made from an N-channel MOS transistor. The logic state of an output signal V OUT of the inverter is determined by turning on either the off-buffer transistors Q 1 and Q 2 of high level side or the output transistor Q 3 of low level side with an ON/OFF operation of the input transistor M n1 . That is, if the input signal V IN is in a logic low state, the input transistor M n1 is turned off and the off-buffer transistors Q 1 and Q 2 are turned on. Consequently, the output signal V OUT goes to a logic high state. If, on the other hand, the input signal V IN is in a logic high state, then the input transistor M n1 is turned on, a base current I B is supplied to the output transistor Q 3 , and therefore the output transistor Q 3 is turned on. Consequently, the output signal V OUT goes to a logic low state. Reference numeral 2 is an auxiliary drive circuit in accordance with the present invention. Between a high level power supply V cc and a low level ground V ss , the auxiliary drive circuit 2 comprises a P-channel MOS transistor (second transistors M p1 , an N-channel MOS transistor (third transistor) M n2 , and a resistor R 5 which are connected in series. The auxiliary drive circuit 2 further comprises a bipolar transistor Q 4 (fourth transistor) having its base connected to the line between M n2 and R 5 and its emitter connected to the base of the output transistor Q 3 . Assume now that the area of M p1 is substantially the same as that of M n2 . This makes the turn-on speed of M n2 faster than that of M p1 by the difference of carrier mobility (the mobility of electrons µn is about two or three times greater than the mobility of holes µp) between the two transistors (P-channel and N-channel MOS transistors). Consequently, when the input signal V IN makes a transition from a low state to a high state, the transistors M p1 and M n2 can be both turned on instantaneously. When this occurs, current I D flows through the transistors M p1 and M n2 , and causes voltage V 1 to generate across the resistor R 5 . If V 1 is greater than the total value of the base-emitter voltage V BE4 of Q 4 and the base-emitter voltage V BE3 of Q 3 (2 V BE = V BE3 + V BE4 ), then Q 4 is turned on by V 1 and the emitter current I B′ can be added to the base current I B of Q 3 . That is, the total current of the current I B″ supplied through M n1 and the current I B′ supplied through Q 4 can be employed as the base current I B (I B = I B′ + I B″ ) of Q 3 , so the base current I B of Q 3 can be increased instantaneously during the low-to-high transition period of V IN . Consequently, the turn-on speed of Q 3 can be made faster, and the high-to-low transition speed of the output signal V OUT is made faster and the propagation delay time t PHL of the output signal V OUT is thus shortened. The current I B ′ functions as active pull-down current, makes the turn-on of Q 3 deep, and can rapidly pull out a wiring load capacity connected to V OUT . As a result, high-speed operation can be obtained. The shortening of t PHL will hereinafter be described in accordance with the timing diagram of FIG. 2. If both M p1 and M n2 are concurrently turned on as the input signal V IN makes a low-to-high transition, then the current I D flows through the transistors M p1 and M n2 . The current I D causes the base voltage V 1 of Q 4 to increase. If the voltage V 1 exceeds 2V BE , Q 4 is turned on and I B′ flows. The current I B′ is added to the current I B″ that flows through M n1 As a result, since the base current I B of Q 3 is increased by the amount of I B′ , the turn-on speed of Q 3 can be made faster. As described above, in the embodiment of the present invention, when the input signal V IN makes a transition from a low to a high, the base current of the output transistor Q 3 is increased by supplying the current from Q 4 of the auxiliary drive circuit 2. Consequently, the turn-on speed of Q 3 can be made faster and therefore t PHL can be shortened. Although the above described embodiment is applied to an inverter, it is noted that it may also be applied to a logic circuit in which input and output signals V IN and V OUT change in the same logic state. In that case, the area of M n2 is made smaller than that of M p1 so that the turn-on speed of M n2 can be made slower when V IN makes a transition from a high to a low. Consequently, the base current of Q 3 can be increased in the same way. FIG. 3 schematically shows another embodiment of the auxiliary drive circuit 2 of FIG. 1. In this embodiment, an auxiliary drive circuit 2′ is provided at its input side with an inverter stage 3 comprising a P-channel MOS transistor M p2 and an N-channel MOS transistor M n3 . When the input signal V IN makes a transition from a high to a low, the turn-on speed of M n2 can be made slower. In the same way, the base current of Q 3 can be increased. FIG. 4 illustrates the waveform of the output signal V OUT . V cc was set to 5.5V, 5.0V and 4.5V, and each t PHL according to the present invention was compared with that of the conventional logic circuit. It will be understood from FIG. 4 that, with the rapid turn-on speed of Q 3 , the high-to-low transition according to the present invention is faster than that of the conventional logic circuit. While the present invention has been applied in order to improve t PHL , it is noted that it is also applicable to improve t PLH . FIG. 5 schematically illustrates a Bi-CMOS circuit to which the present invention is applied to improve t PLH . The same reference characters will be applied to the same parts as FIG. 1 and therefore a detailed description will not be given. In the embodiment of FIG. 5, the base current I B′ of Q 4 is added to the base current I B″ of Q 1 , so that the turn-on speed of Q 2 is made faster and the propagation delay time t PLH of the output signal V OUT is shortened. In addition, the present invention is applicable to improve both t PHL and t PLH . FIG. 6 schematically illustrates a Bi-CMOS circuit in which both t PHL and t PLH are shortened in accordance with the present invention. As shown in FIG. 6, the base currents of Q 2 and Q 3 are increased in the same manner as those of the embodiments of FIGS. 1 and 5, so both t PHL and t PLH can be shortened.

Claims: A Bi-CMOS circuit comprising : a gate circuit (1) operative from a high and low supply voltage (respectively V cc , V ss ) and having an input (V in ) and an output (V out ) and comprising a first, N-channel MOS transistor (M n1 ) which is turned on and off in response to the logic state of the input signal (V in ) and which supplies a first current (I B" ) to the base of an output transistor (Q 3 ; Q 1 ) when the first transistor (M n1 ) is turned on; an active pull-down current supplying circuit (2), the input of which is connected to the gate electrode of said first transistor (M n1 ), for supplying an active pull-down current (I B' ) to the base of said output transistor (Q 3 ; Q 1 ) so that said first current (I B" ) and the active pull-down current (I B' ) can be supplied to the base of said output transistor (Q 3 ; Q 1 ), the current supplying circuit (2) having a supply transistor (Q 4 ; Q 4' ) which feeds the active pull-down current (I B' ) to the base of the output transistor (Q 3 ; Q 1 ) when the input signal makes a transition from a low state to a high state or from a high state to a low state; characterized in that said supply transistor (Q 4 ; Q' 4 ) is supplied directly by said high supply voltage (V cc ) and is biased by a voltage drop stage (M p1 , M n2 ) that is controlled directly by said input signal (V in ). A Bi-CMOS circuit as set forth in claim 1, wherein said voltage drop stage comprises : a second, P-channel MOS transistor (M p1 ) having its gate electrode connected to the gate electrode of said first transistor (M n1 ), a third, N-channel MOS transistor (M n2 ) having its gate electrode connected to the gate electrode of said second transistor (M p1 ), the third transistor (M n2 ) being connected in series with said second transistor (M p1 ), and wherein a fourth transistor (Q 4 ), being the supply transistor, comprises a bipolar transistor having its base connected to said third transistor (M n2 ) and its emitter connected to the base of said output transistor (Q 3 ). A Bi-CMOS circuit as set forth in claim 2, wherein said second transistor (M p1 ) is substantially identical in area to said third transistor (M n2 ). A Bi-CMOS circuit as set fourth in claim 2, wherein said second transistor (M p1 ) is greater in area than said third transistor (M n2 ). A Bi-CMOS circuit as set fourth in claim 1, wherein said active pull-down current supplying means comprises : a second, P-channel MOS transistor (M p2 ) having its gate electrode connected to the gate electrode of said first transistor (M n1 ), a third, N-channel MOS transistor (M n3 ) having its gate electrode connected to the gate electrode of said second transistor (M p2 ), the third transistor (M n3 ) being connected in series with said second transistor (M p2 ), and wherein said voltage drop circuit comprises a fourth, P-channel MOS transistor (M p1 ), a fifth, N-channel MOS transistor (M n2 ) having its gate electrode connected to the gate electrode of said fourth transistor (M p1 ), the fifth transistor (M p2 ) being connected in series with said fourth transistor (M p1 ), the common output of said second and third transistors being connected to the gate electrodes of said fourth and fifth transistors, and a sixth transistor (Q 4 ), being the supply transistor, comprising a bipolar transistor and having its base connected to said fifth transistor (M n2 ) and its emitter connected to the base of said output transistor (Q 3 ). A Bi-CMOS circuit as claimed in claim 1, in which the gate circuit further comprises a second, P-channel MOS transistor (M p1' ), turned on and off in response to the logic state of the input signal (V in ), the gate circuit supplying a first current (I B" ) to the base of the output transistor (Q 1 ) when the first (M n1' ) and second (M p1' ) transistors are turned on; and in which the active pull-down current supplying circuit is connected to the gate electrodes of said first and second transistors (M n1' , M p1' ). A Bi-CMOS circuit as set fourth in claim 6, wherein said active pull-down current supplying circuit comprises a third, P-channel MOS transistor (M p2 ) having its gate electrode connected to the gate electrodes of said first and second transistors (M n1' , M p1' ), a fourth, N-channel MOS transistor (M n3 ) having its gate electrode connected to the gate electrode of said third transistor (M p2 ), the fourth transistor (M n3 ) being connected in series with said third transistor (M p2 ), and wherein said voltage drop circuit comprises a fifth, P-channel MOS transistor (M p1 ), a sixth, N-channel MOS transistor (M n2 ) having its gate electrode connected to the gate electrode of said fifth transistor (M p1 ), the sixth transistor being connected in series with said fifth transistor (M p1 ), the common output of said third and fourth transistors (M p2 , M n3 ) being connected to the gate electrodes of said fifth and sixth transistors (M p1 , M n2 ), and wherein a seventh transistor (Q 4 ), being the supply transistor, comprises a bipolar transistor and having its base connected to said sixth transistor (M n2 ) and its emitter connected to the base of said output transistor (Q 1 ). A Bi-CMOS circuit as claimed in claim 1, in which the gate circuit further comprises : second and third transistors (M p1' , M n1' ) respectively comprising a P-channel MOS transistor and an N-channel MOS transistor that are turned on and off in response to the logic state of the input signal (V in ) and which supply a second current (I B" ) to the base of a second output transistor (Q 1 ) when the second and third transistors are turned on, in which the active pull-down current supplying circuit supplies the active pull-down current (I B' ) to the base of said output transistor (Q 3 ) so that said first current (I B" ) and the active pull-down current (I B' ) can be supplied to the base of said output transistor (Q 3 ), and in which there is further provided : a second active pull-down current supplying circuit, the input of which is connected to the gate electrodes of said second and third transistors (M p1' , M n1' ), for supplying a second active pull-down current (I B' ) to the base of said second output transistor (Q 1 ) so that said second current (I B" ) and said second active pull-down current (I B' ) can be supplied to the base of said second output transistor (Q 1 ), the second current supplying circuit having a second supply transistor (Q 4 ) which feeds the second active pull-down current (I B' ) to the base of the second output transistor (Q 1 ), the second supply transistor (Q 4 ) being driven by a supply voltage (V cc ) of the second current supplying circuit, said active pull-down current supplied through said active pull-down current supplying circuit being supplied to the base of said output transistor (Q 3 ) when said input signal (V in ) makes a transition from a low to a high, and said second active pull-down current supplied through said second active pull-down current supplying circuit being supplied to the base of said second output transistor (Q 1 ) when said input signal (V in ) makes a transition from a high to a low. A Bi-CMOS circuit as set fourth in claim 8, wherein said voltage drop stage comprises : a fourth, P-channel MOS transistor (M p1 ) having its gate electrode connected to the gate electrode of said first transistor (M n1 ), a fifth, N-channel MOS transistor (M n2 ) having its gate electrode connected to the gate electrode of said fourth transistor (M p1 ), the fifth transistor being connected in series with said fourth transistor, and a sixth transistor (Q 4' ), being the supply transistor, wherein comprises a bipolar transistor and having its base connected to said fifth transistor (M n2 ) and its emitter connected to the base of the output transistor (Q 3 ). A Bi-CMOS circuit as set fourth in claim 8, wherein said second active pull-down current supplying means comprises : a fourth, P-channel MOS transistor (M p2 ) having its gate electrode connected to the gate electrodes of said second and third transistors (M p1' , M n1' ), a fifth, N-channel MOS transistor (M n3 ) having its gate electrode connected to the gate electrode of said fourth transistor, the fifth transistor being connected in series with said fourth transistor, and wherein said voltage drop circuit comprises a sixth, P-channel MOS transistor (M p1 ), a seventh, N-channel MOS transistor (M n2 ) having its gate electrode connected to the gate electrode of said sixth transistor (M p1 ), the seventh transistor being connected in series with said sixth transistor, the common output of said fourth and fifth transistors (M p2 , M n3 ) being connected to the gate electrodes of said sixth and seventh transistors (M p1 , M n2 ), and wherein an eighth transistor (Q 4 ), being the second supply transistor, comprises a bipolar transistor and having its base connected to said seventh transistor (M n2 ) and its emitter connected to the base of said second output transistor (Q 1 ).

Inventors: KOREEDA TOSHIYUKI, NAKAMURA TORU, KOREEDA, TOSHIYUKI, NAKAMURA, TORU
Applicants: FUJITSU LTD, KYUSHU FUJITSU ELECTRONIC, FUJITSU LIMITED, KYUSHU FUJITSU ELECTRONICS LIMITED
Application year: 1990
Main classification: H03K19
IPC codes: H03K19