Logic circuit

Abstract: A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected in cascade, wherein plural groups of input transistors are provided (106-108,109-111) with a load (104) between the voltage source (101) and one of the groups, field effect transistor (103) between the voltage source and the other group, so that its gate is connected to the node (116) between the load (104) and first group and its source is connected to the output terminal (105), with the improvement being in finding a leakage load for the field effect transistor through the voltage source, providing a clamping circuit for the gate of the transistor. The clamping circuit can include a transistor (1191) having its gate connected to the output (1121) with a delay (12201 Fig 33) so that it will not come on until after a substantial portion of the rise time of the output has expired. An additional logic output may be taken from the gate of this transistor, preferably through a transistor (1103, Fig. 25) to match the outputs, so that the logic circuit is provided with two independent outputs (11104,11105) useful for providing adjacent logic or digital circuits with a conveniently close terminal for input, and further to take advantage of the isolation of the outputs by providing other directions for both outputs for circuit elements that must remain isolated, for example in cross coupling two logic circuits (11215,11216, Fig 24) as a flipflop. One or more of the may be a field effect transistor, particularly provided with boot strapping. For otherwise identical logic circuits as a part of an overall integrated logic circuit, the clamping circuits may differ only with respect to matching respective output voltages or respective output currents with respective fan outs or other characteristics of load circuits to be driven by the outputs. Preferably, all of the elements are constructed of field effect transistors.

Description: BACKGROUND OF THE INVENTION The present invention relates to logic circuits, and more particularly to a GaAs single chip integrated logic circuit of ultrahigh speed and low power consumption. A priort art high speed circuit discussed in IEEE Transactions on Electron Devices, ED-25, No. 6 (1978), pp. 628-639 is shown in Fig. 18. It has plus side voltage sources (of, for example, O V), 1151, 1152, and a minus side voltage source (of, for example, -2V) 153, and it is constructed of field-effect transistors "FETs", 1101, 1102, 1104, 1105, and 1106, and a load element 1103 formed of a FET or the like. An input terminal 1155 is connected to the gate electrodes of the FETs 1101 and 1104. Another input terminal 1156 is similarly connected to the FETs 1102 and 1105. An output terminal 1157 is led out of the node between the source of the FET 1106 and the common drain electrodes of the FETs 1104, 1105. The operation of this Fig. 18 circuit is in accordance with NOR logic that, when a logically high level (for example, -1.4V) is applied to either the input terminal 1155 or 1156, a logically low level (for example, -2.0 V) appears at the output terminal 1157. The logical operation is chiefly determined by the FETs 1101, 1102 and the load element 1103. By way of example, when the input terminal 1155 is at the high level, current flows through the FET 1101 and the load element 1103, so that the potential of a lead 1120 lowers to approach the voltage of the minus side voltage source 1153. Accordingly, the logically low level (nearly equal to the voltage of the minus side voltage source) appears at the source of the FET 1106, namely, the output terminal 1157. In contrast, when the logically low level is applied to both the input terminals, no current flows through the load element 1103, so that the potential of the lead 1120 becomes nearly equal to the voltage of the plus side voltage source 1151 to turn on FET 1106, and the logically high level appears at the output terminal 1157, because FET's 1104 and 1105 are off. The output voltage value of the logically high level at the output terminal 1157 depends upon the form of a gate circuit at the succeeding stage. When quite the same circuit as in Fig. 18 is connected in cascade, the logically high level at the output terminal 1157 of an initial stage becomes the input of the next stage at a level which is V f higher than the voltage of the minus side voltage source of the next stage. Here, V f denotes the forward bias of a Schottky junction which is formed between the gates and sources of the FETs 1101 and 1104 of the next stage when the input terminal 1155 of the next stage is assumed to be at the high level by way of example. Assuming that the forward bias V f is about 0.6 V, the high level becomes about -1.4 V when the voltage of the minus side voltage source is -2 V. The FETs 1104 and 1105 serve to shorten a delay time. Especially when the input signals rise, FETs 1104 and 1105 discharge a load capacitance at high speed, thereby to quicken the fall of the output signal at output terminal 1157. On the other. hand, when the inputs lower, the FET 1106 charges the load capacitance at high speed, thereby to quicken the rise of the output signal at output terminal 1157. A problem in the prior-art technique shown in Fig. 18 is that variation in a circuit current is large. It is assumed that plural circuits as shown in Fig. 18 are connected in cascade. the circuit at any desired stage and the circuit at a stage succeeding it shall be respectively called the "initial stage" and the "next stage". Consider a case where the FETs 1102 and 1105 do not exist. The output terminal 1157 of the initial stage is assumed to be connected to the input terminal 1155 of the next stage. When the point of the connection between stages is at the logically low level, current flows from the FET 1106 of the initial stage through the FET 1104 of the initial stage. The value of this current is determined by the difference between the potential of the lead 1120 and that of the output terminal 1157. Current does not flow to the next stage from the connection between stages. In contrast, when the point of the connection is at the logically high level, the FET 1104 of the initial stage is cut off and causes no current to flow, and a current path extends from the FET 1106 of the initial stage to a Schottky diode which is formed between the gates and sources of the FETs 1101 and 1104 of the next stage. The potential of the output terminal 1157 is determined so as to equalize currents which flow through the Schottky diode and the FET 1106, whereby the current value is determined. However, the Schottky diode and the FET have the current voltage characteristics of an exponential function and a square function, respectively, and they respond to voltages very sensitively, hereby to determine the current. Accordingly, when the potential difference between the lead 1120 and the minus side voltage source 1153 changes even slightly, the current changes greatly. Since, in the case of a high at the point of connection, the lead 1120 is nearly equal in potential to the plus side voltage source, the current of this circuit changes greatly, depending upon the supply voltage. Moreover, even when the supply voltage does not change, the current to flow to the next stage changes greatly, depending upon the threshold voltage V th of the FET 1106. That is, the prior-art technique has the problem that, since the circuit current depends greatly upon the supply voltage and the voltage V th of the FET 1106, variations in characteristics, especially the delay time etc., becomes very large. A further logic circuit with field effect transistors is disclosed in EP-A-0 296 508. This logic circuit includes the features of the precharacterising part of claim 1. SUMMARY The object of the present invention is to provide a logic circuit with a stabilised current by eliminating or at least reducing the dependency upon the supply and threshold voltages of the FETs. This object is met by a logic circuit according to claim 1. Preferred embodiments are disclosed in the subclaims. The logic circuit of the present invention has a clamping circuit for clamping the potential of the output node of a logic portion connected in parallel with an FET and other elements which determine current through the output node, and the potential difference between the output node of the logic portion and a voltage source is held constant against the change of the voltage of the voltage source by the clamping circuit. In addition, elements similar to the FET and other elements which determine the current at the output node are employed for the clamping circuit, whereby very stable characteristics are achieved even against variation in the threshold voltage V th of the FET. Since the clamping circuit is disposed in parallel between the gate electrode of the FET of an initial stage and the N-electrode of a Schottky diode of the next stage, namely, the minus side voltage source, it functions to hold the potential difference between the electrodes of the Schottky diode constant even against the fluctuation of the voltage of the voltage source. Accordingly, the variation of the current to flow to the next stage can be made very small. In addition, the clamp circuit is constructed of a FET and a Schottky diode that have characteristics matching the initial stage FET and next stage Schottky diode, respectively whereby the current to flow to the next stage does not change due to the V th variation of the FET. BRIEF DESCRIPTION OF THE DRAWINGS Further objects, features and advantages of the present invention will become more clear from the following detailed description of a preferred embodiment, shown in the drawing, wherein: Fig. 1 is a diagram showing a fundamental construction of the present invention. Figs. 2 thru 17 are diagrams each showing an embodiment of the construction of Fig. 1 of the present invention. Fig. 18 is a diagram showing a prior-art example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Now, embodiments of the present invention will be described with reference to the drawings. Fig. 1 shows one embodiment of the present invention. This circuit operates under plus side voltage sources 1151, 1152 and minus side voltage sources 1153, 1154 in such a manner that an output signal is produced at an output terminal 1157 in response to input signals which are applied to input terminals 1155, 1156. The logic function is the NOR logic similarly to that of the prior-art example in Fig. 29. Numerals 1101, 1102, 1104 and 1105 designate FETs to which the input signals are applied, and numeral 1106 designates a driving FET for pull-up which serves to heighten a driving capability for a load capacitance parasitic to the output terminal 1157. A load element 1103 provides a voltage drop across it in response to the input signals applied to the input terminals 1155 and 1156. As a result, the output signal of logically high or low level appears at the node or lead 1120 and at the output terminal 1157. A clamp device 1107 plays the central role of this embodiment. In order to describe this embodiment in detail, reference will be had to Fig. 2. Here, for the sake of brevity, the plus side voltage sources 1151 and 1152 and the minus side voltage sources 1153 and 1154 are respectively made common, and only one input terminal is provided. Besides. the figure illustrates one circuit at any desired stage "initial stage" and only part of a similar "next stage" circuit connected to the output terminal of the initial stage, for plural cascaded circuits. That is, FETs 1201, 1204 within the circuit 1200 of the next stage correspond to FETs 1101, 1104 of the circuit 1100 of the initial stage. When the input signal at the high level is applied to the input terminal 1155 of the circuit 1100, the FETs 1101 and 1104 fall into conductive states, and current flows from the load element 1103 through the FET 1101. As a result, the lead 1120 obtains a potential near the voltage of the minus side voltage source 1153. In accordance with the potential at lead 1120, a comparatively small current flows from the FET 1106 to the FET 1104. No current flows to the circuit 1200 of the next stage. On the other hand, when the input signal of the circuit 1100 is at the low level, the FETs 1101 and 1104 fall into nonconductive states, so that the current from the load element 1103 flows to the clamp device 1107 without flowing through the FET 1101. As a result, owing to a voltage drop across the clamp device, the lead 1120 has a potential higher than the voltage of the minus side voltage source by the voltage drop across the clamp device 1107. Besides, the source-gate voltage of the FET 1106 enlarges, so that a comparatively great current is about to flow through the FET 1106. Since, however, the FET 1104 is in the nonconductive state similarly to the FET 1101, the current from the FET 1106 flows to a Schottky diode which is formed between the gate electrodes and source electrodes of the FETs 1201 and 1204 of the next-stage circuit 1200. The present invention stabilizes this current I out . In this state, the following relational formula holds: v(1120) = V gs (FET 1106) + V f (FETs 1201, 1204) = V f (device 1107) Here, V (1120) denotes the potential difference between the lead 1120 and the voltage of the minus side voltage source, V gs (FET 1106) the gate-source voltage of the FET 1106, V f (FETs 1201, 1204) the forward voltage drop of the Schottky diode of the parallel FETs 1201 and 1204, and V f (device 1107) the forward voltage drop of the device 1107. The current I out is determined by the square function characteristic of V gs (FET 1106) and the exponential function characteristic of V f (FETs 1201, 1204). Accordingly, although the current I out can greatly change even in case of a slight change in V (1120), this voltage V (1120) is determined by the voltage V f (device 1107) in the present invention. Therefore, if the current to flow through the device 1107 does not depend considerably upon the supply voltages etc., the changes of the voltages V f (device 1107) and V (1120) and further changes of the current I out can be made very small. The influences of the fluctuations in the threshold voltages V th of the FETs can be made very little when elements identical in kinds to the FET 1106 and the Schottky diode of the FETs 1201, 1204 are used for the device 1107. By way of example, when the voltage V th of the FET 1106 has lowered, the current I out fluctuates greatly and enlarges for the same value of the voltage V (1120). However, when the current of the device 1107 is also subjected to the same fluctuation of the voltage V th , the voltage drop thereof decreases for a certain current value, and the voltage V (1120) lowers and operates so as to reduce the current I out to the original value thereof. Reference will be had to Figs. 3(a) - (d) in order to describe the above operation in more detail. Figs. 3(a) - (d) show several examples of the practicable arrangement of the clamp circuit 1107 in Figs. 1 and 2. In Fig. 3(a) the clamp circuit is constructed of a series connection consisting of a FET 1301 and a Schottky diode 1302. The FET 1301 is designed to have the same threshold voltage V th as that of the FET 1106. The Schottky diode 1302 is designed to have the same forward voltage V f as the Schottky diode that receives the output of the initial stage and is formed between the gates and sources of the FETs 1201 and 1204 in the circuit 1200 of the next stage. In practical use, it is considered that elements which are formed in a simultaneously identical semiconductor substrate by implanting an impurity in equal doses at the same energy will have almost equal values of the voltage V th or V f . For the sake of brevity, it is assumed that, also in size, the FET 1301 is equal to the FET 1106, while the Schottky diode 1302 is equal to the Schottky diode formed between the gates and sources of the FETs 1201, 1204. On this occasion, current I c to flow through the clamp circuit 1107 and the current I out become almost equal. The reason therefor is that the voltage which is applied across the clamp circuit 1107 and the voltage which is applied across the series circuit consisting of the FET 1106 and the Schottky diode between the gates and sources of the FETs 1201, 1204 are the same. Meanwhile, the current value is determined by only the current of the load element 1103 because all the current of the clamp circuit 1107 is supplied from the load element 1103. By setting the characteristics of the load element as desired, accordingly, a desired stable current is attained as the current I out . When the sizes of the elements of the clamp circuit are made n times as large as those of the FET 1106 and the Schottky diode between the gates and sources of the FETs 1201, 1204, the current I c of the clamp circuit is n times as much as the current I out . Fig. 3(b) shows another example of the clamp circuit 1107. Here, the Schottky diode 1302 in Fig. 3(a) is replaced with a FET 1303. The gate electrode of the FET 1303 is connected to the source electrode of the FET 1301, and Schottky diodes between the gate electrode of the FET 1303 and the source and drain electrodes thereof are utilized. As shown in Fig. 3(c), it is also possible to use only a Schottky diode between the gate electrode and the source or drain electrode of a FET 1304. Fig. 3(d) shows still another example of the clamp circuit 1107. Here, the FET 1303 in Fig. 3(b) is replaced with two FETs 1305 and 1306. In this way the voltage drop V f of the clamp circuit 1107 at a certain value of the current I c can be readily changed according to the number of the FETs 1305 and 1306. The same effect can be expected by similarly connecting FETs of the same sort in parallel with the FET 1301 or by enlarging the gate width of the FET 1301. Accordingly, the output current I out can be changed. This method is effective when the number of circuits to be connected to the output terminal of one circuit, that is, the fan-out has increased. An example in which the fan-out is two, is shown in Fig. 4. In the figure, four circuits 1400 - 1403 are interconnected, and the circuit 1400 has a fan-out of one, while the circuit 1401 has the fan-out of two. When the number of fan-out increases in this manner, the current of the Schottky diode enlarges for the same value of the voltage V f (FETs 1201, 1204) in Eq. (1), and hence the current I out increases. On such an occasion, the number of the FETs 1305, 1306 etc. is increased owing to the structure in Fig. 3(d), whereby the voltage V f of the clamp circuit 1107 can be lowered to reduce the current I out . In a case where the length of interconnection wiring is great and correspondingly the load capacitance is great, it is sometimes required that the resulting large delay time for overcoming this capacitance is shortened by increasing the current I out . On this occasion, the number of FETs 1305, 1306 etc. is reduced, whereby conversely to the above, the voltage V f of the clamp circuit 1107 can be enlarged to increase the current I out . Of course, the requirement can also be met by changing the gate widths of the FETs 1305 and 1306. Except in the special case when the gate width of the FET 1301 is set to be n times that of the FET 1106, the total of the gate widths of the FETs 1305 and 1306 should preferably be made n times the total of the gate widths of the FETs 1201 and 1204 when the fan-out is large, for the purpose of diminishing the temperature characteristics of the FETs and the variations of devices to the utmost. The sequence of connection of the FET 1301 and the Schottky diode 1302 may be reversed in Fig. 3(a). That is, it is also allowed that the anode of the diode 1302 is connected to the lead 1120, that the drain-gate path of the FET 1301 is connected to the cathode of the diode 1301, and that the source of the FET 1301 is connected to the minus side voltage source 1153. This holds true also for Figs. 3(b) - (d). Fig. 5 shows the load element 1103 in Fig. 1. A FET 1503 is a normally-on FET, the gate and source electrodes of which are connected to each other. As a result, when the potential difference between the lead 1120 and the plus side voltage source 1151 is sufficiently great, the current that flows through the FET 1503 becomes substantially constant. Fig. 6 shows the load element 1103 in Fig. 1 constructed of a normally-on type FET 1603, and a certain fixed potential V g is the gate bias of the FET 1603. Fig. 7 shows an example of a circuit for generating the potential V g . Here, FETs 1703, 1712 and 1101 are of the normally-off type, and FETs 1709, 1711, 1713, 1714 and 1603 are of the normally-on type. In addition, numerals 1702 and 1705 indicate diodes. This circuit uses the same circuit as in Fig. 6 as a circuit 1600, and it is so constructed that the potential V g is connected to the gate of the FET 1603 in the circuit 1600 by a lead 1753, while at the same time, the source potential of the FET 1603 is fed back by a lead 1752. The potential of the lead 1752 is automatically adjusted so as to approach the potential of a lead 1750. The operation of the circuit will be described. The gate electrode of the FET 1709 is supplied with a bias by the lead 1750. The bias is generated by a circuit configured of resistors 1704, 1706, 1707 and the diode 1705. More specifically, a voltage, for example, 0.5 V appears across the diode 1705, and this value hardly changes in spite of some change in the supply voltage if a potential difference across the resistor 1704 is sufficiently great. Therefore, when the divider resistors 1706 and 1707 are connected in parallel with the diode 1705, the divided value of the voltage of the diode 1705 arises at the node 1750 between the resistors 1706 and 1707, and it is hardly affected by the change of the supply voltage. Moreover, since an FET is not used, the divided voltage value is not affected by the threshold voltage V th of the FET. Thus, when the resistance ratio of the resistors 1706 and 1707 is set at 2:3 by way of example, the potential difference between the lead 1750 and the minus side voltage source 1153 becomes 0.3 V. This potential of the lead 1750 and the potential of the lead 1752 fed back from the circuit 1600 are compared by a differential transistor circuit. Assuming now that the threshold voltage V th of the FET 1603 has become lower than its design value, thereby to increase the current, the source potential of the FET 1603 rises on this occasion. Consequently, the potential of the lead 1752 becomes higher than that of the lead 1750. Then, current flows through the FET 1711 more than through the FET 1709, and the potential of a lead 1754 lowers. Accordingly, the potential V g of the lead 1753 is responsively lowered, and the potential of the lead 1752 is automatically adjusted so as to approach that of the lead 1750. That is, the potential V g lowers, thereby functioning to restore the current to the expected design value. A current configured of a resistor 1701, the diode 1702 and the FET 1703 serve to supply the bias potential of the gate of the FET 1712 through a lead 1751. When a potential difference applied across the resistor 1701 is sufficiently great, the potential difference between the lead 1751 and the minus side voltage source 1153 is not influenced by the supply voltage. Accordingly, the current of the FET 1712 is stabilized, and a potential difference across a resistor 1710 and the potential of the lead 1754 become less susceptible to the influence of the supply voltage. A source follower configured of the FETs 1713 and 1714 plays the role of a buffer for connecting the lead 1753 to many circuits 1600. When the gate widths of the FETs 1713 and 1714 are equal, the potentials of the leads 1754 and 1753 become nearly equal because the gate and source electrodes of the FET 1714 are shorted. According to the circuit of this example, the V th dependency of the current to flow through the FET 1603 can be rendered very little. It is accordingly possible to stabilize the characteristics of the circuit, such as the delay time. Fig. 8 shows another embodiment of the present invention. This embodiment corresponds to a case where the present invention is applied to a logic circuit proposed in Japanese Patent Application No. 13903/1989. When compared with the embodiment of Fig. 6, the embodiment of Fig. 8 is additionally provided with a FET 1801. Like the FET 1106, FET 1801 functions to quicken the rise of the output signal. Fig. 9 shows another embodiment of the present invention. In this embodiment, the arrangement of the clamp circuit 1107 is altered relative to the embodiment of Fig. 6. The load element 1603 may well be the FET 1503 as shown in Fig. 5. This embodiment is effective when a higher operating speed is attained in such a way that the amplitude of the signal at the output terminal 1157 is rendered smaller than the Vf (forward voltage drop) of a Schottky diode formed between the gates and sources of the FETs of the next-stage circuit receiving this signal (corresponding to the FETs 1101, 1104 or 1102, 1105 when the next-stage circuit has the same circuit arrangement as that of the initial-stage circuit). For this purpose, a FET 1902 is interposed between the output terminal 1157 and the minus side voltage source 1153. Thus, when the output terminal 1157 is at the logically high level, most of the current does not flow from the FET 1106 to the Schottky diode of the next-stage circuit, but it flows from the FET 1106 to the FET 1902. As a result, in correspondence with Eq. (1), the potential difference V (1120) between the lead 1120 and the minus side voltage source becomes: V(1120) = V gs (FET 1106)+ V gs (FET 1902) = V gs (FET 1301) + V gs (FET 1901) Here, V gs (FET xxx) denotes the gate-source voltage V gs of the FET xxx. In order to hold Eq. (2), the clamp circuit 1107 is configured of the FET 1301 and a FET 1901, the gate electrode is connected to the output terminal 1157 similarly to that of the FET 1902. In this way, as in the description up to Fig. 8, all the current to flow through the clamp circuit is supplied from the load element 1603, so that a desired stable current is attained as the output current I out in conformity with the relationship of Eq. (2). Fig. 10 shows a modification to the embodiment in Fig. 9, and the FETs 1901 and 1902 in Fig. 9 are respectively replaced with resistors 11001 and 11002. Fig. 11 shows another embodiment of the present invention. Here, a circuit 11100 drives circuits 11101 and 11102. However, the input of the circuit 11101 is connected to the output terminal 11104 of the circuit 11100, and the input of the circuit 11102 is connected to the source electrode of a FET 11103. This construction is effective on such an occasion that the circuit 11102 lies at a position very close to the circuit 11100, whereas the circuit 11101 lies at a position comparatively remote therefrom. Besides, it is very effective in a case where the propagation of a signal to the circuit 11102 is to be prevented from depending upon the magnitude of the load of the output terminal 11104, in this example, the length of wiring to the circuit 11101. In this embodiment, the clamp device in the circuit 11100 is constructed of a series circuit which consists of the FET 11103 and a Schottky diode formed between the gates and sources of FETs 11111 and 11114 in the circuit 11102. that is, the input FETs of the next-stage circuit are used instead of the FET 1303 in Fig. 6. Even when the load of the output terminal 11104 has become heavy, it exerts almost no influence on the response of the lead 1120, and hence, the signal can be sent to the circuit 11102 with a fixed delay time. The application of this embodiment will be somewhat detailed. Figs. 12(a) and (b) show arrangements of "RS flip-flops". In Fig. 12(a), NOR gates 11205 and 11206 constitute an information holding portion. NOR gates 11207 and 11208 serve as buffers for driving a load. Also, they function to prevent the speeds of the feedback operations of the NORs 11205 and 11206 from depending upon the load of the flipflop. This arrangement, however, has, not only the disadvantage that the number of the NOR gates is large, but also the disadvantage that delay times involved from input terminals 11201 and 11202 to output terminals 11203 and 11204 become long. When the circuit of Fig. 11 is therefore applied, the arrangement of Fig. 12(b) is realized. Here each of NOR gates 11215 and 11216 has the arrangement of the circuit 11100 in Fig. 11. By way of example, the output terminals 11204 and 11211 of the NOR 11215 correspond respectively to the output terminal 11104 and the source electrode of the FET 11103 in Fig. 22. In more detail, accordingly, Fig. 12(b) is expressed as shown in Fig. 13. Fig. 14 shows a further embodiment. Here, in order to realize the same function as in the embodiment of Fig. 11, a normally-on type FET 11401 is interposed between the source electrode of the FET 11103 and the minus side voltage source 1153. Since the FET 11401 has its gate electrode and source electrode shorted, it exhibits a constant-current characteristic. In case of setting the current value of the FET 11401 at a comparatively small value, most of the current from the FET 1603 flows from the FET 11103 to the FETs 11111 and 11114 when the input is at the logically low level. That is, the clamp operation for the lead 1120 is determined by a circuit configured of the FET 11103 and the FETs 11111 and 11114, and hence, it is substantially the same as in the foregoing. On the other hand, when the input signal rises, the potential of a lead 11105 is discharged by the FET 11401 so as to rapidly fall. The FET 11401 may well be replaced with a resistor of comparatively high resistance. Fig. 15 shows a modification to the embodiment in Fig. 14. In this embodiment, the FET 11401 in Fig. 14 is substituted by FETs 11501 and 11502. The gate electrodes of the FETs 11501 and 11502 are respectively connected to input terminals In10 and In11. This serves to quicken the fall of the second output terminal 11105, and the output terminal 11105 is rapidly lowered when the input terminal In10 or In11 rises. Fig. 16 shows a further embodiment. In this example, the source electrodes of the respective FETs 1301 and 1106 are connected to each other. In this circuit, as in the embodiments of Fig. 22 et. seq., the clamp circuit is configured of the FET 1301 and the FETs 1101 - 1105 of the next-stage circuit. With such a configuration, in comparison with the embodiment of Fig. 15, the number of output terminals decreases to one, but as to the pulling-down FETs 11501, 11502, 1104 and 1105, only 1104 and 1105 can be shared. Moreover, the current to flow through the clamp circuit can be effectively utilized also for charging and discharging the output terminal 1157. Fig. 17 shows a still further embodiment. This embodiment is such that the concept of the embodiment in Fig. 14 is applied to the embodiment in Fig. 6. Instead of the pulling-down FETs 1104 and 1105 in Fig. 6, a normally-on type FET 11701 is interposed between the source electrode of the FET 1106 and the minus side voltage source 1154. Owing to this arrangement, the number of FETs can be decreased. The output fall at the output terminal 1157 is quickened by a discharge operation based on the FET 11701. In Fig. 3, the FET 1301 whose gate and drain are shorted is used as part of the clamp circuit, and this is intended to hold Eqs. (1) and (2) in correspondence with the FET 1106 for pulling up the output. Besides, although the FET 1603 is employed as the load element 1103 in Fig. 9, it is obvious from the above description that the FET 1503 as shown in Fig. 5 or a mere resistor may well be employed. As described above, according to the present invention, a circuit of ultrahigh speed which is very stable against fluctuations in the voltages of voltage sources and the threshold voltages V th of devices can be realized.

Claims: A logic circuit (1100) comprising: at least one first junction field effect transistor (1101; 1102) receiving an input signal at its gate; load means (1103; 1503; 1603) including a load capacitance and being connected at a node (1120) to said first junction field effect transistor (1101; 1102) for providing a load, wherein said load means and said first junction field effect transistor are series connected between first and second supply voltages (1151; 1153); pull down means (1104; 1105) connected to an output (1157) of said logic circuit for discharging the load capacitance in response to the input signal, wherein said output is to be connected to a junction field effect transistor (1201, 1204) included in another logic circuit (1200); pull up junction field effect transistor (1106) connected to said output (1157) for charging the load capacitance in response to a voltage of said node (1120); and clamping means (1107) connected to said node (1120) and said second supply voltage (1153) in parallel to said first junction field effect transistor (1101; 1102) for clamping the node voltage at a value substantially independent of the first supply voltage, wherein said clamping means includes a second junction field effect transistor (1301); characterised in that said clamping means (1107) further includes a Schottky diode (1302) series connected to said second junction field effect transistor (1301); and the gate of said second junction field effect transistor (1301) is connected to its drain. The logic circuit according to claim 1, characterised in that the threshold voltage of said second junction field effect transistor (1301) is the same as that of said pull up junction field effect transistor (1106). The logic circuit according to claim 1 or 2, characterised in that said Schottky diode (1302) is formed between the gate and the source of a third junction field effect transistor (1303; 1304). The logic circuit according to any of claims 1 to 3, characterised in that said clamping means (1107) includes a plurality of Schottky diodes (1305, 1306) connected in parallel to each other, wherein each Schottky diode corresponds to one of a plurality of junction field effect transistors to be connected to said output (1157) and is substantially equivalent to the Schottky diode formed between the gate and the source of the corresponding junction field effect transistors. The logic circuit according to any of claims 1 to 4, characterised in that said load means (1503) includes a normally-on type junction field effect transistor. The logic circuit according to any of claims 1 to 5, characterised in that a plurality of logic circuits (1400-1403) are connected to each other, wherein the fan outs of said logic circuits are different from each other, and the gate width of the junction field effect transistor (1301) included in the clamping means (1107) of each logic circuit is dependent upon the fan out of the said logic circuit. The logic circuit according to any of claims 1 to 5, characterised in that a plurality of logic circuits (1400-1403) are connected to each other, wherein the load capacitances at the outputs of said logic circuits are different from each other; and the gate width of the junction field effect transistor (1301) included in the clamping means (1107) of each logic circuit is dependent upon the load capacitance at the output of said logic circuit. The logic circuit according to any of claims 1 to 7, characterised in that said load means (1603) comprises a normally-on type transistor; and a voltage supply circuit (1701 - 1716, 1750 - 1754) provides the gate of the normally-on type transistor (1603) with a voltage which decreases depending upon an increase of the absolute value of the threshold voltage of said normally-on type transistor.

Inventors: ITOH HIROYUKI, KAWATA ATSUMI, TANAKA HIROTOSHI, YAMASHITA HIROKI, YOSHIHARA KAZUHIRO, ITOH, HIROYUKI, KAWATA, ATSUMI, TANAKA, HIROTOSHI, YAMASHITA, HIROKI, YOSHIHARA, KAZUHIRO
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1990
Main classification: H03K19
IPC codes: H03K19