Semiconductor device and method of testing the same

Abstract: According to this invention, a testing apparatus including a semiconductor chip having data lines (L₁ to L₈) and output terminals (O₁ to O₈) respectively connected to the data lines and a connecting means (202) for commonly connecting an arbitrary number of ones of the output terminals includes a control means for enabling one of the plurality of data lines connected to each other by the connecting means and disabling remaining data lines and a measuring means (203) for measuring data output from the enabled data line.

Description: The present invention relates to a semiconductor device comprising a semiconductor chip having multiple output terminals, and to a method for testing the chip. A method and apparatus of this type are disclosed in PATENT ABSTRACTS OF JAPAN, vol. 9, no. 165 (E-327) (1888), 10 July 1985 & JP-A-60 412 37. An LSI tester is generally used for a test such as a selection of LSIs. In conventional techniques, in order to test an LSI, the tester must have terminals corresponding to the number of terminals of an LSI. When the number of terminals of the tester is less than that of the LSI, the LSI can be tested by banding terminals to be tested (terminals of an LSI) and using a relay or the like. Fig. 1 shows, as a conventional method for testing, a basic structure for testing an LSI by banding the terminals to be tested using a relay. In Fig. 1, reference numeral 101 denotes an LSI; and 102, a tester. Reference symbols I n (n = 1, 2,...) denote inverted signals of data output to output terminals; SW n (n = 1, 2,...), relays inserted between the LSI and the tester; O n (n = 1, 2,...), output terminals of the LSI; and E n (n = 1, 2,...), signals supplied to the tester. Each pair of outputs O n of the LSI 101 are commonly connected through a corresponding one of the relays SW n , and each common connecting point is connected to a corresponding one of the measuring terminals of the tester 102. For this reason, the LSI 101 having output terminals, the number of which is larger than the number of measuring terminals of the tester 102, can be tested. All the output terminals O n can be tested by switching the relays. At this time, the signal E m (m = 1, 2,...) supplied to the tester 102 corresponds to I (2m-1) when the relay SW (2m-1) is set in an ON state and the relay SW 2m is set in an OFF state. When the relay SW (2m-1) is set in an OFF state and the relay SW 2m is set in an ON state, the signal Em corresponds to I 2m . However, along with the advance of semiconductor techniques, an LSI is highly integrated, and an increase in number of terminals of the LSI is conspicuous. On the other hand, the development of a tester for testing the above LSI cannot cope with an increase in number of terminals of the LSI, and a large-sized device is required. For this reason, a production cost is increased. As described above, when a test is performed by using a relay or the like and banding the terminals to be measured, depending on an increase in terminals of the LSI, the number of measuring terminals of the tester is increased, the capacity of a relay and the characteristics and reliability of the test are degraded, and wirings are complicated. An object of the invention is to provide a semiconductor device for testing an LSI having a large number of output terminals even in a tester having a small number of measuring terminals, and a method and apparatus for testing the same. According to one aspect of the invention, there is provided a semiconductor device comprising: a semiconductor chip having a plurality of data lines and a plurality of output terminals respectively connected to said data lines, said semiconductor chip comprising selecting means, operable to select only one data line among said data lines in response to a plurality of control signals and to supply data on the selected data line to one of the output terminals; a connecting means for connecting said output terminals to each other, said connecting means comprising an insulating tape and a plurality of leads to be formed on said insulating tape, said insulating tape including a hole for disposing said semiconductor chip in the center, one end of each lead being connected to one of the output terminals, the other ends of respective leads being connected together to constitute a test electrode to be connected to an input of said testing means. According to another aspect of the invention, there is provided a method for testing a semiconductor chip having a plurality of output terminals, comprising the steps terminals of: disposing said semiconductor chip in the center of a hole in an insulating tape; internally arranging the output terminals of said semiconductor chip into at least one group of output terminals and electrically connecting the output terminals of said at least one group to each other via respective leads formed on said insulating tape and being connected together to constitute a test electrode for testing; selecting and enabling only one output terminal for testing among the output terminals of said at least one group; outputting data from the semiconductor chip through the selected output terminal; measuring the data output through the selected output terminal; repeating said selecting, outputting and measuring steps for each output terminal in said at least one group; and electrically disconnecting the output terminals of said at least one group from each other. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a basic structure for performing a conventional method of testing a semiconductor device; Fig. 2 is a circuit diagram showing a basic structure for performing a method of testing a semiconductor device according to the present invention; Figs. 3 to 5 are circuit diagrams respectively showing arrangements for supplying control signals, respectively; Fig. 6 is a timing chart showing signals according to a semiconductor testing method of the present invention; Fig. 7 is a view showing a basic arrangement which embodies a method of testing a semiconductor device according to the second embodiment of the present invention; Fig. 8 is a view showing a basic arrangement which embodies a method of testing a semiconductor device according to the third embodiment of the present invention; Fig. 9 is a plan view showing a structure of a connecting means; and Fig. 10 is a view showing the connecting means in Fig. 9 in detail. The first embodiment of the present invention will be described below with respect to the accompanying drawings. The same reference numerals throughout the drawings denote the same parts, and a detailed description thereof will be omitted. Fig. 2 shows a basic arrangement which embodies a method of testing a semiconductor device according to the first embodiment of the present invention. In Fig. 2, reference numeral 201 denotes an LSI; 202, a connecting means; 203, a tester (a measuring means); and 204, a clocked inverter. Reference symbols I n (n = 1, 2,...) denote data output to output terminals; L n (n = 1, 2,...), data output lines; T₁ to T₄, control signals; O n (n = 1, 2,...), output terminals of an LSI; and E n (n = 1, 2,...), signals supplied to the tester, respectively. The output terminals O₁ to O₄ are commonly connected by the connecting means 202 outside the LSI 201, thereby constituting a first block B₁. The common connecting point is connected to a predetermined measuring terminal of the tester 203. The control signals T₁ to T₄ are supplied from, e.g., the control means (not shown) of the tester 203 to the clocked inverter 204. In response to the control signals T₁ to T₄, one of the data output lines L₁ to L₄ is enabled, and other output lines are disabled by the clocked inverter 204. The output terminals O₅ to O₈ are commonly connected by the connecting means 202 outside the LSI 201, thereby constituting a second block B₂. The connecting point is connected to a predetermined measuring terminal of the tester 203. The control signals T₁ to T₄ supplied from, e.g., the tester 203 are input to the clocked inverter 204. In response to the control signals T₁ to T₄, one of the data output lines L₅ to L₈ is enabled and other data output lines are disabled by the clocked inverter 204. In the third and subsequent blocks (not shown), four output terminals are commonly connected by the corresponding connecting means, thereby constituting a block. The common connecting point is connected to a predetermined measuring terminal of the tester 203. In a single block, two or more data output lines are not simultaneously enabled in response to the control signals T₁ to T₄. The control signals T₁ to T₄ may be supplied from the outside of the LSI, or may be generated in the LSI. The control signals T₁ to T₄ can be supplied from the outside of the LSI by, e.g., an arrangement shown in Fig. 3. In Fig. 3, reference numeral 205 denotes a control means, and it is provided in the tester 203. Reference symbols O x denote input terminals. Note that, in use of an LSI, all control signals TST₁ to TST₄ are set at "L (Low)" level. In addition, the control signals T₁ to T₄ can be supplied by an arrangement shown in Fig. 4. In Fig. 4, reference numeral 206 denotes a line decoder. According to the above arrangement, the control signals T₁ to T₄ can be supplied by an operation shown in the following truth table. That is, during testing, an enable signal ENABLE is kept at "L" level. The control signals T₁ to T₄ can be obtained by inputting two control signals TST₁ and TST₂ from the control means 205 to the line decoder 206. Note that, in use of an LSI, the enable signal ENABLE is set at "H (High)" level. According to the above arrangement, since the number of input terminals for control signals can be decreased as compared with the arrangement in Fig. 3, the arrangement in Fig. 4 is further effective. In order to produce the control signals T₁ to T₄ in the LSI, an arrangement shown in Fig. 5 can be employed. A clock signal CLOCK is output from the control means 205, and the clock signal CLOCK is input to a binary counter 207. Two control signals TST₁ and TST₂ are output from the binary counter 207, and the control signals TST₁ and TST₂ are input to the line decoder 206. Thus, the control signals T₁ to T₄ are obtained from the line decoder 206. As described above, according to this embodiment, the four output terminals are commonly connected to the connecting means 202, thereby constituting one block. In response to the control signals T₁ to T₄, one of the data output lines connected to the four output terminals is enabled, and other data output lines are disabled. That is, data output lines to be enabled are sequentially changed, and all the output terminals can be tested. For this reason, an LSI having a large number of output terminals can be tested by a tester having a small number of measuring terminals. Fig. 6 is a timing chart showing signals according to a method of testing a semiconductor device of the present invention. A method of testing a semiconductor device according to the present invention will be described with reference to Figs. 2 and 6 below. The control signal T₁ is set at "H" level to enable the data output line L₁. The control signals T₂ to T₄ are set at "L" level to disable the data output lines L₂ to L₄. At this time, data I₁ is applied from a first block B₁ to the tester 203 to test functional and electric characteristics of the output terminal O₁. Note that a path from the output terminals O₂ to O₄ to the inside of the LSI 201 is set in a high impedance state. Input data I₅ is applied from the second block B₂ to the tester 203 to test functional and electric characteristics of the output terminal O₅. Note that a path from the output terminals O₆ to O₈ to the inside of the LSI 201 is set in a high impedance state. In addition, from the third block, any one of output terminals selected in the blocks by the control signal T₁ is tested. The control signal T₂ is set at "H" level to enable the data output line L₂, and the control signals T₁, T₃, and T₄ are set at "L" level to disable the data output lines L₁, L₃, and L₄. At this time, data I₂ is applied from the first block B₁ to the tester 203, thereby testing functional and electric characteristics of the output terminal O₂. Note that a path from the output terminals O₁, O₃, and O₄ to the inside of the LSI 201 is set in a high impedance state. Input data I₆ is applied from the second block B₂ to the tester 203, thereby testing functional and electric characteristics of the output terminal O₆. Note that a path from the output terminals O₅, O₇, and O₈ to the inside of the LSI 201 is set in a high impedance state. In addition, from the third block, any one of output terminals selected in the blocks by the control signal T₂ is tested. Like the above signals, the control signals T₃ and T₄ are set at "H" level to test any one of output terminals selected in the block by the control signal T₃ or T₄. As described above, according to this embodiment, four output terminals respectively controlled by the control signals T₁ to T₄ constitute one block. Among output terminals in one block, a data output line connected to a terminal to be measured is enabled, and data output lines connected to other terminals in this block are disabled. In this state, testing is performed. For this reason, the number of measuring terminals of the tester 203 is about 1/4 the number of output terminals of an LSI to be tested. In this embodiment, four output terminals respectively controlled by the control signals T₁ to T₄ constitute one block. However, the present invention is not limited to this embodiment, and the number of terminals of one block can be set in accordance with the number of measuring terminals of a tester. For example, five output terminals may constitute one block using five control signals T₁ to T₅, and five or more output terminals may constitute one block. However, a control signal does not simultaneously enable two or more data output terminals in one block. Fig. 7 shows a basic arrangement which embodies a method of testing a semiconductor device according to the second embodiment of the present invention. In this embodiment, in place of the clocked inverter 204 used in the embodiment shown in Fig. 2, a transmission gate 208 is used. Fig. 8 shows a basic arrangement which embodies a method of testing a semiconductor device according to the third embodiment of the present invention. In this embodiment, in place of the clocked inverter used in the embodiment shown in Fig. 2, a tri-state logic circuit 209 is used. In any case using the transmission gate 208 or the tri-state logic circuit 209, testing is performed by enabling/disabling the data lines L₁ to L₄ as in the first embodiment. The connecting means 202 for commonly connecting a plurality of output terminals O n to form one block can be obtained by directly connecting the plurality of output terminals O n to the measuring terminals of the tester or by using a structure shown in Fig. 9. More particularly, as shown in Fig. 9, in a semiconductor device in which an LSI chip (semiconductor chip) 602 is arranged on a film carrier tape 601, a plurality of lead terminals 603 wired on the film carrier tape 601 are connected with each other, thereby providing one test electrode 604. Thus, one block is constituted by the plurality of lead terminals 603 which are connected to each other. When an LSI which is tested is used in a practical operation, no problem is posed, if connections of output terminals of each block are cut along a line I - I′, and if the control signals T₁ to T₄ are set at "H" level, as shown in Fig. 10.

Claims: A semiconductor device comprising: a semiconductor chip (201, 602) having a plurality of data lines (L1 to L4) and a plurality of output terminals (01 to 04) respectively connected to said data lines, said semiconductor chip comprising selecting means (204, 208, 209), operable to select only one data line among said data lines in response to a plurality of control signals (T1 to T4) and to supply data on the selected data line to one of the output terminals; a connecting means (202) for connecting said output terminals to each other, said connecting means comprising an insulating tape (601) and a plurality of leads (603) to be formed on said insulating tape, said insulating tape including a hole for disposing said semiconductor chip in the center, one end of each lead being connected to one of the output terminals, the other ends of respective leads being connected together to constitute a test electrode (604) to be connected to an input of said testing means. A semiconductor device according to claim 1, wherein said selecting means selects only one data line among at least three data lines in response to the control signals, and supplies data on the selected data line to one of the output terminals; and said connecting means connects at least three output terminals to each other. A semiconductor device according to claim 1, wherein said selecting means is a clocked inverter to be connected between said data lines and said output terminals. A semiconductor device according to claim 1, wherein said selecting means is a transmission gate to be connected between said data lines and said output terminals. A semiconductor device according to claim 1, wherein said selecting means is a tri-state logic circuit to be connected between said data lines and said output terminals. A semiconductor device according to claim 1, wherein said semiconductor chip further comprises a plurality of output terminals (Ox) for inputting said control signals. A semiconductor device according to claim 1, wherein said semiconductor chip further comprises a line decoder (206) for outputting said control signals, and a plurality of output terminals (Ox) for inputting control signals which control said line decoder. A semiconductor device according to claim 1, wherein said semiconductor chip further comprises a line decoder (206) for outputting said control signals, a binary counter (207) for outputting control signals which control said line decoder, and a plurality of output terminals (Ox) for inputting control signals which control said binary counter. A method of testing a semiconductor chip (201, 602) in the semiconductor device of Claim 1 having a plurality of output terminals (01 to 04), comprising the steps of: disposing said semiconductor chip in the center of a hole in an insulating tape (601); internally arranging the output terminals of said semiconductor chip into at least one group of output terminals and electrically connecting the output terminals of said at least one group to each other via respective leads (603) formed on said insulating tape and being connected together to constitute a test electrode for testing; selecting and enabling only one output terminal for testing among the output terminals of said at least one group; outputting data from the semiconductor chip through the selected output terminal; measuring the data output through the selected output terminal; repeating said selecting, outputting and measuring steps for each output terminal in said at least one group; and electrically disconnecting the output terminals of said at least one group from each other. A method for testing a semiconductor chip according to claim 9, wherein said step of electrically disconnecting the output terminals from each other includes severing the output terminals of said at least one group from said respective leads.

Inventors: MASUKO AKIRA INTELLECTUAL PROP, SAKUMOTO AIICHIRO INTELLECTUAL, YAMAMOTO KEN INTELLECTUAL PROP, MASUKO, AKIRA, INTELLECTUAL PROPERTY DIV., SAKUMOTO, AIICHIRO, INTELLECTUAL PROPERTY DIV., YAMAMOTO, KEN, INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F11
IPC codes: G06F11