FREQUENCY MODULATOR

Abstract: A frequency-modulated signal is digitally integrated through an integration circuit (20) and is phase modulated through a phase-modulating circuit (30). The modulated signal that is integrated is converted through the phase-modulating circuit (30) into first and second digital modulated signals whose phases are orthogonal to each other. Further, a carrier signal from a carrier signal generating circuit (40) is converted into first and second carrier signals whose phases are also orthogonal to each other. The first digital modulated signal is multiplied by the first carrier signal through D/A converter (35); the second digital modulated signal is multiplied by the second carrier signal through a D/A converter (36). The two resultant signals are outputted as analog signals, and are added to each other through an adder (37), thereby to output a frequency-modulated signal. Because of the digital processing, the frequency modulator can have exellent linear characteristics, little harmonic distortion, and high reliability.

Description: The present invention relates generally to FM modulators for use in recording video signals and for radio communication, and particularly, to FM modulators for FM-modulating integrated modulation signals by phase-modulating the same. Video signals are ordinarily recorded on optical discs and magnetic tapes after being once FM modulated. Such a multivibrator system modulator as shown in Fig. 1 and a frequency converting system modulator as shown in Fig. 2 are well known as FM modulators for use in such a case as described above. The FM modulator shown in Fig. 1 has a pair of transistors 1 and 2. A video signal as a modulation signal is supplied in common to a base terminal 3 of transistors 1 and 2. Then, an FM modulated output is obtained from an output terminal 4. The FM modulator shown in Fig. 2 includes an FM modulator 6 having a center frequency of f1 and an FM modulator 7 having a center frequency of f2. The frequencies of the FM modulated outputs of FM modulators 6 and 7 are mixed by a frequency converter 8. Extracted by a low pass filter 9 is only a frequency of the difference (f1-f2) of the FM modulated outputs after the frequency mixing. FM modulators 6 and 7 are structured to have frequency deviation directions opposite to each other. That is, FM modulators 6 and 7 are structured such that when one FM modulation frequency is increased with respect to the positive input, the other FM modulation frequency is decreased. Consequently, the frequency of the difference (f1-f2) which the ultimate FM modulated output has become in practice a frequency of the sum of the center frequencies f1 and f2. Such FM modulators as shown in Figs. 1 and 2 are structured to process modulation signals in a purely analogue manner, thereby causing the following problems (1) - (4). (1) A frequency relation between an input voltage and an output voltage is non-linear. (2) An FM modulation output signal includes a higher distortion (especially secondary distortion). (3) An oscillating frequency is not stabilized, particularly due to a temperature characteristic. (4) A modulated signal is leaked to an output side. Various adjustments and compensations are required to improve the above-described problems, even by which it is difficult to obtain sufficient precision. Digital FM modulators are known from JP-A-63-279604 and JP-A-62-62603. The object of the present invention is to provide a highly reliable FM modulator of high precision causing none of such problems as described above. In accordance with a first aspect of the invention, there is provided an FM modulator comprising: integration means for converting an analogue input signal to a digital signal and integrating said digital signal to produce an integrated digital output signal, carrier signal generating means for generating a carrier signal, and phase-modulating means for phase-modulating said carrier signal in dependence upon said digital output signal, said phase-modulating means including: digital modulating signal generating means for generating, from said digital output signal, first and second digital modulating signals having mutually orthogonal phases, carrier signal converting means for converting said carrier signal to first and second carrier signals having mutually orthogonal phases, first converting means for generating, from said first digital signal modulating signal and said first carrier signal, an analogue output signal corresponding to the multiplication result of the first digital modulating signal and the first carrier signal, second converting means for generating, from said second digital modulating signal and said second carrier signal, an analogue output signal corresponding to the multiplication result of the second digital modulating signal and the second carrier signal, and arithmetic means for adding or subtracting the outputs of said first and second converting means to produce an FM-modulated analogue output signal, characterised in that: each of said first and second digital modulating signals comprises an m-bit signal (where m is a positive integer not less than 2), said m-bit signal being divided into a first component comprising a group of bits from the most significant bit to bit k (m < k) and a second component comprising a group of bits from bit (k + 1) to the least significant bit, said phase modulating means includes: first attenuating means for attenuating said first carrier signal by a predetermined amount, second attenuating means for attenuating said second carrier signal by a predetermined amount, said first converting means includes: first D/A converting means for higher digits with multiplication function for outputting an analogue signal corresponding to the multiplication result of said first component of the first digital modulating signal and said first carrier signal, and first D/A converting means for lower digits with multiplication function for outputting an analogue signal corresponding to the multiplication result of said second component of the first digital modulating signal and said first carrier signal attenuated by said first attenuating means, said second converting means includes: second D/A converting means for higher digits with multiplication function for outputting an analogue signal corresponding to the multiplication result of said first component of the second digital modulating signal and said second carrier signal, and second D/A converting means for lower digits with multiplication function for outputting an analogue signal corresponding to the multiplication results of said second component of the second digital modulating signal and said second carrier signal attenuated by said second attenuating means. In accordance with a second aspect of the invention, there is provided an FM modulator comprising: an integration means for converting an analogue input signal to a digital signal and integrating said digital signal to produce an integrated digital output signal, digital carrier signal group generating means for generating a digital carrier signal group including four digital carrier signals having phases mutually staggered by π/2, and phase-modulating means for phase-modulating said digital carrier signal group in dependence upon said digital output signal, said phase-modulating means including: digital modulating signal generating means for generating, from said digital output signal, first and second digital modulating signals having mutually orthogonal phases, digital carrier signal group converting means for converting said digital carrier signal group to first and second digital carrier signal groups having mutually orthogonal phases, first multiplication means for multiplying said first digital modulating signal by said first digital carrier signal group, second multiplication means for multiplying said second digital modulating signal by said second digital carrier signal group, and arithmetic means for adding or subtracting the outputs of said first and second multiplication means to produce an FM-modulated digital output signal. In the FM modulators according to the first and second aspects of the present invention, an analogue modulation signal is digitally processed to be FM-modulated. Therefore, a linear characteristic thereof is excellent, no higher distortion is included and furthermore, a temperature characteristic is improved. In addition, in the FM modulator according to the second aspect of the present invention, the arrangement of the multiplication means is simplified by using the carrier signal group including four digital carrier signals having phases mutually staggered by π/2. Fig. 1 is a circuit diagram showing an arrangement of a conventional multivibrator system FM modulator. Fig. 2 is a schematic block diagram showing an arrangement of a conventional frequency converting system FM modulator. Fig. 3 is a block diagram showing an arrangement of a digital FM modulator. Fig. 4 is a graph showing a relation between the input and the output of the waveform converting ROM shown in Fig. 3. Fig. 5 is a block diagram showing an arrangement of a first embodiment of the present invention. Fig. 6 is a block diagram showing an arrangement of a second embodiment of the present invention. Fig. 7 is a timing chart showing a carrier signal for use in the embodiment shown in Fig. 6. Fig. 8 is a logic gate diagram showing the arrangement of the digital multiplier for use in the embodiment of Fig. 6. Figs. 9A and 9B are diagrams showing a logic relation between the input and the output of the digital multiplier for use in the embodiment shown in Fig. 6. Fig. 10 is a graph showing a band characteristic of a band pass filter for use in the embodiment shown in Fig. 6. Fig. 11 is a diagram showing a phase characteristic of the band bass filter for use in the embodiment shown in Fig. 6. For a more detailed disclosure, the present invention will be described with reference to the attached drawings. Fig. 3 is the block diagram showing the arrangement of the FM modulator according to the first embodiment of the present invention. In Fig. 3, an FM modulator 11 comprises an integration circuit 20, a phase modulating circuit 30 and a carrier signal generating circuit 40. Integration circuit 20 integrates the analogue modulation signal supplied to an input terminal 21. For example, a video signal can be used as an analogue modulation signal. Phase modulating circuit 30 phase-modulates the integration output of integration circuit 20 in response to the carrier signal applied from carrier signal generating circuit 40. The FM modulator 11 of Fig. 3 is structured to digitally process the analogue modulation signal supplied to input terminal 21. Thus, integration circuit 20 has an A/D converter 22 which converts the analogue modulation signal (a video signal of a still picture in the present embodiment) supplied to input terminal 21 to a digital signal having a predetermined number of bits (8 bits in the present embodiment). The digitized video signal is added in an adder 24 to a video signal one clock before outputted from a register 23. Adder 24 comprises 2n (n is a positive integer) bits. It is assumed that n = 5. Therefore, the less significant 8 bits of adder 24 receive the 8-bit video signal as input to and the remaining 2 bits receive no input. Then, the output (comprising 10 bits) of adder 24 is again supplied to register 23. As the foregoing, by sequential adding video signal one block before, an integrated digital video signal is obtained from register 23. As the clock signal CK for use in A/D converter 22 and register 23, employed is an output from a reference oscillator 41 included in carrier signal generating circuit 40. Reference oscillator 41 comprises a crystal oscillator or the like. In the present embodiment, a still picture video signal having a time base extended by a factor of 15 is FM-modulated, 2.5MHz is used as a clock frequency fc of reference oscillator 41. The clock signal CK is supplied from an input terminal 25. A clear signal is supplied to an input terminal 26 provided for register 23. The clear signal initializes the contents of register 23. This takes into consideration also that a video signal having no direct component is supplied to input terminal 21. That is, even if the supplied video signal includes no direct current component, an initial value of register 23 is fixed by resetting the contents of register 23 for each horizontal cycle at a tip portion of a horizontal synchronizing signal. Therefore, an integration value at a level of the tip of the synchronizing signal can be fixed. The video signal digitally integrated in integration circuit 20 is supplied to phase modulating circuit 30. Phase modulating circuit 30 is provided with first and second waveform converting ROMs 32 and 33. The first and the second waveform converting ROMs 32 and 33 convert the input digital video signals (integration output) to two digital video signals having phases orthogonal to each other. That is, first and second waveform converting ROMs 32 and 33 store an amplitude value (digital signal) corresponding to a cosine wave and an amplitude value (digital signal) corresponding to a sine wave as shown in Fig. 4, respectively. In first and second waveform converting ROMs 32 and 33, amplitude values corresponding to the level of the input digital video signal are simultaneously referred to output two digital video signals having phases orthogonal to each other, that is, a cosine digital video signal cos(c) and a sine digital video signal sin(c). Herein, the above-described phase c corresponds to the level of the input digital video signal (the level of the integration output). The cosine digital video signal cos(c) and the sine digital video signal sin(c) are used as modulation signals as will be described later. The cosine digital video signal cos(c) is supplied to a first D/A converter 35 comprising 2n bits. The sine digital video signal sin(c) is supplied to a second D/A converter 36 comprising 2n bits. First and second D/A converters 35 and 36 receive the supply of analogue carrier signals from carrier signal generating circuit 40 in addition to the digital video signals. In carrier signal generating circuit 40, the reference clock signal CK from reference oscillator 41 is once supplied to a band pass filter 42 wherein the signal is converted to a sine wave signal sin(2πfct) having the same frequency as that of the reference clock signal CK. Herein, π is a ratio of the circumference of a circle to its diameter and t is a time (the same hereinafter). The sine wave signal sin(2πfct) is supplied to a 1/4 cycle delayer 31 wherein the signal is delayed by 1/4 cycle. As a result, the sine wave signal sin(2πfct) is converted to a cosine wave signal cos(2πfct). By using such a 1/4 cycle delayer 31, the sine wave signal sin(2πfct) can be converted to first and second carrier signals having phases orthogonal to each other. Herein, the first carrier signal is a sine carrier signal sin(2πfct) and the second carrier signal is a cosine carrier signal cos(2πfct). The sine carrier signal sin(2πfct) and the cosine digital video signal cos(c) are supplied to first D/A converter 35. The cosine carrier signal cos(2πfct) and the sine digital video signal sin(c) are supplied to second D/A converter 36. First and second D/A converters 35 and 36 are D/A converters having four quadrant multiplication function. In other words, first and second D/A converters 35 and 36 are structured to have output amplitudes controlled by an input carrier signal when an input digital video signal is converted to an analogue signal. For example, DAC-7533, the product of DATEL Corporation is used as such D/A converters 35 and 36. Therefore, first D/A converter 35 outputs such an analogue signal as expressed by the following equation (1). sin(2πfct) · cos(c) Second D/A converter 36 outputs such an analogue signal as expressed by the following equation (2). cos(2πfct) · sin(c) The output of first D/A converter 35 and the output of second D/A converter 36 are applied to an analogue adder 37 wherein they are added. The output of analogue adder 37 will be expressed by the following equation (3). As the foregoing, analogue adder 37 outputs a sine carrier signal sin(2πfct+c) with a phase lead of c over the sine carrier signal sin(2πfct). The sine carrier signal sin(2πfct+c) is band-limited by a band pass filter 38 and then output from an output terminal 39. The sine carrier signal sin(2πfct+c) thus obtained at output terminal 39 is a signal of which phase changes at a high speed (1/fc = 400 nsec) for every cycle of a carrier signal in response to an amplitude of an input video signal for the carrier signal. This means that FM modulation is carried out consequently. Phase resolutions of the above-described sine carrier signal sin(2πfct) and cosine carrier signal cos(2πfct) input to first and second D/A converters 35 and 36 depend on the bit arrangements of first and second D/A converters 35 and 36. For example, assuming that first and second D/A converters 35 and 36 each comprise 10 bits, the phase resolution is 0.35° (= 360° ÷ 1023). The relation between a minimum phase change dc and a frequency change df per unit time will be expressed by the following equation (4). df = (1/2π) (dc/dt) The relation between a minimum phase change dc and a maximum frequency deviation Δf will be accordingly expressed by the following equation (5). Δf = df (2⁸-1) Thus, when dc = 6.14 x 10⁻³ rad dt = 400nsec (= 1/fc = 2.5MHz) it can be shown as follows: Δf = 0.623MHz df = 2443Hz wherein a completely linear relation is established between the input voltage and the output frequency. That is, a linear characteristic is obtained. In the arrangement shown in Fig. 3, it is assumed that the carrier frequency fc is set to 2.5MHz which is set to a level of a tip of a synchronization signal of a video signal. In addition, the maximum frequency deviation ΔF is set to 0.623MHz and a frequency is modulated to become higher. As described above, in the arrangement of Fig. 3, FM modulation is carried out through a digital processing of operating a carrier signal for every cycle. As a result, it is possible to achieve an FM modulator having a more excellent linear characteristic and temperature characteristic than those of a conventional analogue system FM modulator and having no higher distortion. Fig. 5 is the block diagram showing the arrangement of the first embodiment of the present invention. A FM modulator 12 shown in Fig. 5 has the same arrangement as that of the FM modulator 11 shown in Fig. 3 except for the following points. The same reference numerals are allotted to the corresponding parts, and therefore no description of which will be made here. FM modulator 12 shown in Fig. 5 is provided with a phase modulating circuit 50 having a different arrangement from that of phase modulating circuit 30 in FM modulator 11 of Fig. 3. Phase modulating circuit 50 comprises four D/A converters 35a, 35b, 36a and 36b. Each of D/A converters 35a, 35b, 36a and 36b comprises 5 bits and has a four quadrant multiplication function. The more significant 5 bits out of 10 bits of the cosine digital video signal cos(c) are supplied to D/A converter 35a and the less significant 5 bits are supplied to D/A converter 35b. The more significant 5 bits out of 10 bits of the sine digital video signal sin(c) are supplied to D/A converter 36a and the less significant 5 bits are supplied to D/A converter 36b. The sine carrier signal sin(2πfct) is supplied to D/A converter 35a and the cosine carrier signal cos(2πfct) is supplied to D/A converter 36a. The sine carrier signal sin(2πfct) having the level attenuated to 1/(2 n -1) by an attenuator 51, is supplied to D/A converter 35b. The cosine carrier signal cos(2πfct) having the level attenuated to 1/(2 n -1) by an attenuator 52, is supplied to D/A converter 36b. Each output of D/A converters 35a, 35b, 36a and 36b is supplied to an analogue adder 37 wherein an addition of the same is carried out. The arrangements of other parts in phase modulating circuit 50 are the same as those of phase modulating circuit 30 in Fig. 3. When a maximum amplitude of a carrier signal is resolved by n bit, that is, by 5 bits, a minimum resolution width corresponds to 1/(2⁵-1) of the maximum amplitude of the carrier signal. Thus, it results in that the minimum resolution width of D/A converter 35a is further resolved by 5 bits by means of attenuator 51 and D/A converter 35b. As a result, the pair of D/A converters 35a and 35b and attenuator 51 as a whole function as a D/A converter of 2n bits. Similarly, the pair of D/A converters 36a and 36b and attenuator 52 as a whole function as a D/A converter of 2n bits. As the foregoing, the embodiment shown in Fig. 5 employing the D/A converters comprising 5 bits can be manufactured at an extremely reduced cost as compared with the embodiment shown in Fig. 3 employing the D/A converter comprising 10 bits. The present invention is not limited to the above- described embodiment shown in Fig. 5. For example, a sine wave signal and a cosine wave signal are exchangeable in the above-described embodiment of Fig. 5 to have completely the same effect because the sine wave signal and the cosine wave signal are completely the same signals except that they are out of phase by 1/4 cycle. Multiplication can be performed between sine waves or cosine waves in D/A converters 35a, 35b, 36a and 36b. Furthermore analogue adder 37 can perform a subtraction in place of an addition. Since D/A converter 35a, 35b, 36a and 36b in the embodiment of Fig. 5 require a processing of digital video signals based on analogue carrier signals of a sine wave or a cosine wave, they cannot be composed of only simple logic circuits for logic operations of digital signals, which the makes the circuit arrangement complicated. A second embodiment of the present invention will be described in the following with reference to Fig. 6, in which embodiment such problems as described above are improved. Fig. 6 is the block diagram showing the arrangement of the second embodiment of the present invention. An FM modulator 13 of Fig. 6 comprises an integration circuit 20, a phase modulating circuit 60 and a carrier signal generating circuit 70. The arrangement of integration circuit 20 is the same as that of integration circuit 20 in the arrangements of Figs. 3 and 5. A video signal digitally integrated in integration circuit 20 is supplied to phase modulating circuit 60. Phase modulating circuit 60 is provided with first and second waveform converting ROMs 32 and 33 having the same arrangements as those shown in Figs. 3 and 5. First waveform converting ROM 32 converts the output of integration circuit 20 to a cosine digital video signal cos(c) and second waveform converting ROM 33 converts the output of integration circuit 20 to a sine digital video signal sin(c). The phase (c) corresponds to the level of the input digital video signal (the output of integration circuit 20). The above-described cosine digital video signal cos(c) and the sine digital video signal sin(c) are supplied to first and second digital multipliers 61 and 62 each comprising 2n bits. First and second digital multipliers 61 and 62 receive a supply of a digital carrier signal group CK (CK0-CK3) from carrier signal generating circuit 70 in addition to digital video signals. Carrier signal generating circuit 70 includes a reference oscillator 71 and a multistage frequency divider 72. Reference oscillator 71 comprises a crystal oscillator, for example, and an oscillating frequency thereof is selected to have a frequency four times those of reference oscillators 41 in the embodiments of Figs. 3 and 5, that is, set to 2.5 x 4 = 10.0MHz. Multistage frequency divider 72 converts the reference clock signal 4CK from reference oscillator 71 (see Fig. 7(a)) to four digital carrier signals CK0-CK3 (see Figs. 7(b)-(e)) each out of phase by π/2 one another. Each of the digital carrier signals CK0-CK3 has one-fourth the frequency of the reference clock signal 4CK. Multistage frequency divider 72 comprises four frequency dividers each for 1/4 frequency-dividing the reference clock signal 4CK. Assuming now that the digital carrier signal CK0 has a reference phase, the digital carrier signals CK1, CK2 and CK3 are out of phase by π/2, 2π/2 and 3π/2 from the digital carrier signal CK0, respectively. Assuming that the digital carrier signal CK0 at a H (logical high) level is defined as the state 1, the digital carrier signal CK1 at a H level is defined as the state 0, the digital carrier signal CK2 at a H level is defined as the state -1 and the digital carrier signal CK3 at a H level is defined as the state 0, the analogue signal having an amplitude repeatedly changing in the order of state 0→state 1→state 0→state →1 can be expressed by these digital carrier signals CK0-CK3. The analogue signal is a carrier signal obtained by analogizing a digital carrier signal. That is, the above-described respective states correspond to the amplitude values of the sine wave signal sin(2πfct) having the same frequency as that of the carrier signal CK0 at phases 0, π/2, 2π/2 and 3π/2, respectively. One sine wave signal sin(2πfct) can be therefore expressed by the four digital carrier signals CK0-CK3. In the following description, the four digital carrier signals CK0-CK3 are referred to as sine digital carrier signals sin(2πfct). The digital carrier signal CK0 having a reference phase is used as a clock signal for use in an A/D converter 22, a register 23 and first and second waveform converting ROMs 32 and 33. The digital carrier signal CK0 is supplied through an input terminal 25. The four digital carrier signals CK0-CK3 forming the sine digital carrier signal sin(2πfct) are supplied to a one-clock delayer 63 comprising a register, for example. In one-clock delayer 63, each of the four digital carrier signals CK0-CK3 is delayed by one clock (1/4 cycle). The delay amount corresponds to π/2 in phase, so that one-clock delayer 63 outputs a cosine digital carrier signal CKc {= cos(2πfct)}. That is, with one-clock delayer 63 provided, the digital carrier signal group CK is converted to a first digital carrier signal group (sine digital carrier signal sin(2πfct)} and a second digital carrier signal group (cosine digital carrier signal cos(2πfct)} the phases of which are orthogonal to one another. The sine digital carrier signal sin(2πfct) and the cosine digital video signal cos(c) are supplied to first digital multiplier 61 and the cosine digital carrier signal cos(2πfct) and the sine digital video signal sin(c) are supplied to second digital multiplier 62. A multiplication of first digital multiplier 61 will be described. For a multiplication of four quadrant by using the four digital carrier signals CK0-CK3 as sine digital carrier signals, the following logic operation is carried out by using the most significant bit signal D9 of the cosine digital video signal cos(c) as a sign bit signal. Such a multiplication can be performed by a simple logic circuit. Fig. 8 is the logic circuit diagram showing one example of the arrangement of first digital multiplier 61 shown in Fig. 6. It is pointed out that second digital multiplier 62 has the same arrangement as that of Fig. 8. In Fig. 8, first digital multiplier 61 comprising 10 bits includes ten NAND gates 100-109 and ten exclusive OR gates 110-119. Bit signals D0-D9 forming the multiplication digital video signal cos(c) having 10 bits are applied to the corresponding NAND gates 100-109, respectively. The digital carrier signals CK0 and CK2 are applied in common to NAND gates 100-109. The outputs of NAND gates 100-109 are applied to the corresponding exclusive OR gates 110-119, respectively. The digital carrier signal CK3 is applied in common to the exclusive OR gates 110-118 except the exclusive OR gate 119 corresponding to the most significant bit signal. The most significant bit signal D9 is a sign bit signal and the corresponding exclusive OR gate 119 receives an inversion signal of the digital carrier signal CK1. Figs. 9A and 9B show a logic relation between the input and the output of such first digital multiplier 61 as shown in Fig. 8. Fig. 9A shows a logic relation between the input bit signals D0-D8 and the output bit signals D0'-D8'. The upper columns of Fig. 9A show the logic of the output bit signal Di' when the input bit signal Di (i = 0 - 8) is at a low level (this level is assumed to be a logic 0). The lower columns of Fig. 9A show the logic of the output bit signal Di' when the input bit signal Di is at a H level (this level is assumed to be a logic 1). As indicated in Fig. 9A, the output bit signal Di' attains a L level in the state 0 irrespective of the logic of the input bit signal Di. In the state 1, the input is output without conversion. In the state -1, the input is inverted to be output. Fig. 9B shows the logic relation between the input bit signal D9 and the output bit signal D9'. In Fig. 9B, it is assumed that "L" denotes (-) and "H" denotes (+). Now it is assumed that a zero point of an analogue carrier signal (sine wave signal) is denoted as "0 (= 1000000000)", a minimum value thereof is denoted as "-512 (= 0000000000)" and a maximum value is "+511 (= 1111111111)". In this case, the multiplication output at the state 0 is zero, so that not (0000000000) but (1000000000) should be output. That is, the output bit signal D9' should attain a H level. First digital multiplier 61 has a logic allowing the above. As is clear from Fig. 9B, in the state 1, the input bit signal D9 is output without conversion and in the state -1, the input bit signal D9 is inverted to be output. As described previously, second digital multiplier 65 also has the same arrangement as that of first digital multiplier 61 and therefore no description will be made thereof. As described in the foregoing, first and second digital multipliers 61 and 62 can be constituted by simple logic circuits only. First and second digital multipliers 61 and 62 attain digital multiplication outputs of a sine signal and a cosine signal, respectively. First digital multiplier 61 therefore outputs the digital signal expressed by the following equation (11). sin(2πfct) · cos(c) Second digital multiplier 62 outputs the digital signal expressed by the following equation (12). cos(2πfct) · sin(c) The outputs of first and second digital multipliers 61 and 62 are applied to a digital adder 66 through buffer registers 64 and 65, respectively. Digital adder 66 outputs the digital signal expressed by the following equation (13) by adding the output of first digital multiplier 61 and the output of second digital multiplier 62. As described above, digital adder 66 outputs a sine digital carrier signal sin(2πfct+c) with a phase lag of c with respect to the sine digital carrier signal sin(2πfct). The sine digital carrier signal sin(2πfct+c) is converted to an analogue signal by a D/A converter 67. The output of D/A converter 67 is band-limited by a band pass filter 68, which is output through an output terminal 69. The sine carrier signal sin(2πfct+c) thus obtained at output terminal 69 is the same signal as the FM modulation output obtained at output terminal 39 in Figs. 3 and 5. Consequently, it results in that the video signal input to an input terminal 21 is FM modulated. Fig. 10 shows a band characteristic of band pass filter 68. As shown in Fig. 10, the band characteristic of band pass filter 41 is preferably selected such that the attenuation amount is 1/(2 n -1) or more at a frequency ±4fo, centered at the carrier frequency fo and the frequency in the range ±(1/2)fo is allowed to pass satisfactorily. In addition, a phase characteristic of a band pass filter 68 is preferably selected such that a phase lag characteristic maintains a linear characteristic as shown in Fig. 11 in the frequency range of ±(1/2)fo, centered at the carrier frequency fo. The above-described phase resolutions of the sine digital carrier signal sin(2πfct) and the cosine digital carrier signal cos(2πfct) input to first and second digital multipliers 61 and 62 depend on the bit arrangements of first and second digital multipliers 61 and 62, respectively. Assuming that each of first and second digital multipliers 61 and 62 comprises 10 bits, for example, the phase resolution is 0.35° (= 360° ÷ 1023). In the embodiment of Fig. 6, the relation between a minimum phase change dc and a frequency change df per unit time will be expressed by the following equation (14). df = (1/2π) (dc/dt) The relation between a minimum phase change dc and a maximum frequency deviation Δf per unit time will be therefore expressed by the following equation (15). Δf = df (2⁸-1) Thus, when, dc = 6.14 x 10⁻³ rad dt = 400nsec (= 1/fc = 2.5MHz) it can be shown as follows, Δf = 0.623MHz df = 2443Hz so that a completely linear relation is established between the input voltage and the output frequency. That is, it has a linear characteristic. The embodiment of Fig. 6 shows a case where the carrier frequency fc is set to 2.5MHz which corresponds to a synchronization signal tip level of a video signal and the maximum frequency deviation Δf is set to 0.623MHz so that a frequency is modulated to become higher. Since a sine wave signal and a cosine wave signal are completely the same signals except that they are out of phase by 1/4 cycle, completely the same effect can be obtained even exchanging a sine wave signal and a cosine wave signal in the embodiment shown in Fig. 6. Digital multipliers 61 and 62, in the embodiment shown in Fig. 6 can be structured to multiply sine waves by each other or cosine waves by each other. Furthermore, digital adder 66 can perform a subtraction in place of an addition. While in the embodiments shown in Figs. 5 and 6, first waveform converting ROM 32 generates a cosine digital video signal cos(c) and second waveform converting ROM 33 generates a sine digital video signal sin(c), it is possible to generate sine and cosine digital video signals by using either first or second waveform converting ROM 32 or 33 because the sine digital video signal sin(c) and the cosine digital video signal cos(c) have phases orthogonal to one another. The FM modulator according to the present invention is suitable for FM modulating an analogue signal such as a video signal.

Claims: An FM modulator comprising: integration means (20) for converting an analogue input signal to a digital signal and integrating said digital signal to produce an integrated digital output signal, carrier signal generating means (40) for generating a carrier signal, and phase-modulating means (30) for phase-modulating said carrier signal in dependence upon said digital output signal, said phase-modulating means including: digital modulating signal generating means (32, 33) for generating, from said digital output signal, first and second digital modulating signals having mutually orthogonal phases, carrier signal converting means (31) for converting said carrier signal to first and second carrier signals having mutually orthogonal phases, first converting means (35) for generating, from said first digital signal modulating signal and said first carrier signal, an analogue output signal corresponding to the multiplication result of the first digital modulating signal and the first carrier signal, second converting means (36) for generating, from said second digital modulating signal and said second carrier signal, an analogue output signal corresponding to the multiplication result of the second digital modulating signal and the second carrier signal, and arithmetic means (37) for adding or subtracting the outputs of said first and second converting means to produce an FM-modulated analogue output signal, characterised in that: each of said first and second digital modulating signals comprises an m-bit signal (where m is a positive integer not less than 2), said m-bit signal being divided into a first component comprising a group of bits from the most significant bit to bit k (m < k) and a second component comprising a group of bits from bit (k + 1) to the least significant bit, said phase modulating means includes: first attenuating means (51) for attenuating said first carrier signal by a predetermined amount, second attenuating means (52) for attenuating said second carrier signal by a predetermined amount, said first converting means includes: first D/A converting means for higher digits with multiplication function (35a) for outputting an analogue signal corresponding to the multiplication result of said first component of the first digital modulating signal and said first carrier signal, and first D/A converting means for lower digits with multiplication function (35b) for outputting an analogue signal corresponding to the multiplication result of said second component of the first digital modulating signal and said first carrier signal attenuated by said first attenuating means (51), said second converting means includes: second D/A converting means for higher digits with multiplication function (36a) for outputting an analogue signal corresponding to the multiplication result of said first component of the second digital modulating signal and said second carrier signal, and second D/A converting means for lower digits with multiplication function (36b) for outputting an analogue signal corresponding to the multiplication results of said second component of the second digital modulating signal and said second carrier signal attenuated by said second attenuating means (52). An FM modulator according to claim 1, wherein said digital modulating signal generating means includes: first digital modulating signal outputting means (32) for outputting as said first digital modulating signal a cosine function of said digital output signal, second digital modulating signal outputting means (33) for outputting as said second digital modulating signal a sine function of said digital output signal. An FM modulator according to claim 2, wherein: said first digital modulating signal outputting means (32) includes first storage means having a conversion table for converting an input signal to a cosine function, said second digital modulating signal outputting means (33) includes second storage means having a conversion table for converting an input signal to a sine function. An FM modulator according to any one of claims 1 to 3, wherein: said carrier signal is a sine wave analogue signal having a fixed frequency, said carrier signal converting means includes delay means (31) for converting said sine wave analogue signal to a cosine wave analogue signal by delaying the sine wave analogue signal by 1/4 cycle, said sine wave analogue signal is used as said first carrier signal and said cosine wave analogue signal is used as said second carrier signal. An FM modulator comprising: an integration means (20) for converting an analogue input signal to a digital signal and integrating said digital signal to produce an integrated digital output signal, digital carrier signal group generating means (70) for generating a digital carrier signal group including four digital carrier signals (CK₀-CK₃) having phases mutually staggered by π/2, and phase-modulating means (60) for phase-modulating said digital carrier signal group in dependence upon said digital output signal, said phase-modulating means including: digital modulating signal generating means (32, 33) for generating, from said digital output signal, first and second digital modulating signals having mutually orthogonal phases, digital carrier signal group converting means (63) for converting said digital carrier signal group to first and second digital carrier signal groups having mutually orthogonal phases, first multiplication means (61) for multiplying said first digital modulating signal by said first digital carrier signal group, second multiplication means (62) for multiplying said second digital modulating signal by said second digital carrier signal group, and arithmetic means (66) for adding or subtracting the outputs of said first and second multiplication means to produce an FM-modulated digital output signal. An FM modulator according to claim 5, wherein said digital modulating signal generating means includes: first digital modulating signal outputting means (32) for outputting as said first digital modulating signal a cosine function of said digital output signal, and second digital modulating signal outputting means (33) for outputting as said second digital modulating signal a sine function of said digital output signal. An FM modulator according to claim 6, wherein: said first digital modulating signal outputting means (32) includes first storage means having a conversion table for converting an input signal to a cosine function, and said second digital modulating signal outputting means (33) includes second storage means having a conversion table for converting an input signal to a sine function. An FM modulator according to any one of claims 5 to 7, wherein: said digital carrier signal converting means includes delay means (63) for delaying said carrier signal group by 1/4 cycle, said digital carrier signals (CK₀-CK₃) before being delayed by said delay means are used as said first digital carrier signal group and said digital carrier signals delayed by said delay means are used as said second digital carrier signal group.

Inventors: HIRAMATSU YONEJIROU, SATOU SHUN-ICHI, HIRAMATSU, YONEJIROU, SATOU, SHUN-ICHI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1990
Main classification: H03C3
IPC codes: H03C3, G11B20