Integrated memory comprising a sense amplifier

Abstract: An integrated memory comprising a sense amplifier which includes a parallel connection of a first and a second current branch, each current branch including channels of a control transistor and a load transistor which are coupled via a relevant junction point, the relevant junction points on the one side and gates of the load transistors on the other side being cross-wise coupled, said junction points constituting outputs of the sense amplifier, said transistors being of the same conductivity type, each load transistor being connected in a source-follower configuration with the relevant control transistor. As a result, the control transistors will be operative in the saturation region at all times and can be driven to full output, so that an integrated memory in accordance with the invention is faster.

Description: The invention relates to an integrated field-effect transistor memory comprising a sense amplifier which includes a parallel connection of a first and a second current branch, each current branch comprising a channel of a control transistor and a channel of a load transistor, which channels are coupled via a relevant junction point, the junction point in each current branch being coupled to the gate of the load transistor in the other current branch, at least one of said junction points constituting an output of said sense amplifier, said transistors being of the same conductivity type, the control transistors being connected in a source follower configuration, the relevant load transistor being connected to the source of the relevant control transistor. Such an integrated field transistor memory is known from US 4,069,475 and also from US 4,123,799. When the sense amplifier according to these publications is turned on it develops a voltage at the output in response to an input signal presented at the gates of the control transistors. The sense amplifier latches the voltage at the output into a stable state, in which the voltage at the output is kept at an extreme corresponding to one of the supply voltages. US 4,479,202 describes a memory circuit in which, in a sense amplifier of a different latching type, the load transistors are shared among a number of sense amplifiers. In this case, each sense amplifier contains additional transistors to connect only one active sense amplifier to the load transistors. When a new input signal must be sensed, the prior art amplifier must be restored. For this purpose its junction points are connected via the channel of a restore transistor. In order to restore the sense amplifier a restore signal is applied to the gate of the restore transistor, to make its channel conductive. The need to restore the sense amplifier is disadvantageous because it requires a restore transistor, and carefully timed signals for selecting the sense amplifier. From JP Kokai 61-96587 an integrated field effect transistor memory is known in which the control transistor are of N-type and the load transistors are of P-type. The bit line voltages in integrated memory circuits usually approximate the positive supply voltage. Consequently, sense amplifiers of this kind have the drawback that the voltages on the drains of the transistors Q1 and Q2 may decrease only from 1 to 2 V below the positive supply voltage in order to ensure that the control transistors Q1 and Q2 are operative exclusively in the saturation zone as to achieve an as fast as possible sense amplifier. In the event of disturbances (VDD bumps) in the positive supply voltage in the negative direction in the known sense amplifiers, however, the setting of at least one of the transistors Q1 and Q2 will still leave the saturation zone, so that such sense amplifiers become slower. It is an object of the invention to provide for an integrated memory circuit which does not require signals for restoring it. It is a further object of the invention to provide for an integrated memory circuit, which is fast and whose speed is relatively unaffected by negative bumps on the positive supply voltage. To achieve this, an integrated memory circuit according to the invention is characterized, in that the transistors are dimensioned such that a width length ratio (W/L) of the load transistor in each current branch is no more than twice the width length ratio (W/L) of the control transistor in the relevant current branch, whereby in operation the output of the sense amplifier is not latched to a supply voltage, the voltage on the output following the input signal on a gate of the control transistors when a new input signal is presented. Thus, the sense amplifier in accordance with the invention is of the self restoring type, i.e. the voltage on the output of the sense amplifier automatically follows the voltage on its input when a new input signal is presented. Another embodiment of an integrated memory in accordance with the invention is characterized in that said width/length ratios (W/L) are substantially equal. As a result, the same dimensions can be chosen for the load transistors and the control transistors, so that the chip lay-out of such a sense amplifier is very simple. Another embodiment of an integrated memory, comprising several sense amplifiers which are connected to a same bus at the output side, and also comprising a selection circuit for selecting a single sense amplifier in accordance with the invention, is characterized in that the selection circuit comprises a first and a second selection transistor in each sense amplifier, a channel of said selection transistors being included in the first and the second current branch, respectively, between a supply terminal on the one side and a drain of the respective control transistor on the other side, the coupled gates of said selection transistors receiving a selection signal for the selective activation of a single sense amplifier. When a desired sense amplifier is selected, the relevant selection transistors are driven to full output so that the drains of the control transistors receive the entire or substantially the entire supply voltage. As a result, these transistors continue to operate in the saturation region. The invention will be described in detail hereinafter with reference to the embodiments shown in the drawing; therein: Fig. 1 shows an embodiment of a sense amplifier in accordance with the invention, and Fig. 2 shows an embodiment of an integrated memory comprising several sense amplifiers in accordance with the invention. Fig. 1 shows an embodiment of a sense amplifier in accordance with the invention. The sense amplifier comprises 4 NMOS-transistors T1, T2, T3 and T4 and 2 PMOS-transistors T5 and T6. The sources of selection transistors T5 and T6 are connected to a supply terminal VDD, the drains of these transistors being connected to the drains of respective control transistors T1 and T2. The sources of the control transistors T1 and T2 are connected to respective junction points A and B and the drains of respective load transistors T3 and T4. The sources of the load transistors T3 and T4 are connected to a supply terminal VSS. The gates of the selection transistors T5 and T6 receive a selection signal YSEL, the gates of the load transistors T3 and T4 being connected to respective junction points B and A. The gates of the control transistors T1 and T2 are coupled to bit lines BL and BLN. The bit lines BL and BLN themselves are connected to memory cells in a memory column which are not shown in the Figure. The selection transistors T5 and T6, however, may also be N-type transistors if their gates receive a sufficiently high selection voltage upon selection of the sense amplifier. The operation of the circuit shown in Fig. 1 is as follows: when the selection signal YSEL for selecting the sense amplifier shown is logic low, the selection transistors T5 and T6 are turned on. The drains of the control transistors T1 and T2 thus receive the entire or substantially the entire supply voltage VDD. The transistors T1 and T2 are connected as source-followers. The input signals on the bit lines BL and BLN are amplified by means of the transistors T1, T2 and T3, T4 and are available on the junction points A and B. Being source-followers, the transistors T1 and T2 have a gain of approximately 1, but the cross-wise coupled transistors T3 and T4 transfer the signals on the bit lines BL and BLN to the junction points A and B in amplified form still. If the width/length ratio (W/L) of the transistors T3 and T4 are no more than twice as large as the W/L ratios of the transistors T1 and T2, the sense amplifier will amplify the signals on the bit lines BL and BIN so that on the output (the junction points A and B) of the sense amplifier the voltages will not be latched to the supply voltage VDD and VSS, or VSS and VDD, respectively. This offers the advantage that such a sense amplifier is a self-restoring type. This means that the voltage on the output of the sense amplifier automatically follows the voltage on its input when a new input signal is presented. Consequently, a sense amplifier in accordance with the invention is faster, because the switching-on and off of the sense amplifier by means of a control signal, as in the sense amplifier described in the cited Japanese reference, can be dispensed with. Fig. 2 shows an embodiment of an integrated memory comprising several sense amplifiers 40, 41 etc. in accordance with the invention. Elements in Fig. 2 which correspond to elements of Fig. 1 are denoted by corresponding references. The outputs of the sense amplifiers 40, 41 etc. are connected to the common data lines DL and DIN. The sense amplifiers 41, etc. are constructed in the same way as the sense amplifier 40. The cross-wise coupled transistors T13 and T14, analogous to T3 and T4 shown in Fig. 1, are provided only once in this circuit and are coupled to the data lines DL and DIN. Furthermore, a further amplifier stage 20 is connected to the data lines DL and DLN. A buffer circuit 30 which produces an output signal on output Y is connected to output X of the amplifier stage 20. The operation of the circuit shown in Fig. 2 is as follows: after the selection of a single, desired sense amplifier by means of a selection signal YSEL, the bit line signals of the relevant memory column are applied to the transistors T13 and T14 via the data lines DL and DLN. The signals on these data lines are amplified by the transistors T13 and T14 and applied to the further amplifier stage 20. In this amplifier stage the signals are further amplified and applied to a buffer circuit 30 via the output X. The output Y of the buffer circuit 30 supplies an output signal having CMOS output levels. Because the transistors T13 and T14 are provided only once for several sense amplifiers connected to the data lines DL and DLN, these sense amplifiers comprise only a small number of components so that they require only a small chip surface area and readily fit in the "pitch" of a memory column.

Claims: An integrated field-effect transistor memory comprising a sense amplifier which includes a parallel connection of a first and a second current branch, each current branch comprising a channel of a control transistor (T1, T2) and a channel of a load transistor (T3, T4), which channels are coupled via a relevant junction point (A, B), the junction point (A,B) in each current branch being coupled to the gate of the load transistor (T3, T4) in the other current branch, at least one of said junction points (A, B) constituting an output (DL, DLN) of said sense amplifier, said transistors (T1, T2, T3, T4) being of the same conductivity type, the control transistors (T1, T2) being connected in a source follower configuration, the relevant load transistor (T3, T4) being connected to the source of the relevant control transistor (T1, T2), characterized, in that the transistors (T1, T2, T3, T4) are dimensioned such that a width length ratio (W/L) of the load transistor (T3, T4) in each current branch is no more than twice the width length ratio (W/L) of the control transistor in the relevant current branch, whereby in operation the output (DL, DLN) of the sense amplifier is not latched to a supply voltage (Vss, Vdd), the voltage on the output (DL, DLN) following the input signal on a gate of the control transistors (BL, BLN) when a new input signal is presented. An integrated field-effect transistor memory circuit as claimed in Claim 1, characterized in that said width/length ratios (W/L) are substantially equal. An integrated field-effect transistor memory circuit as claimed in Claim 1 or 2, comprising several sense amplifiers (40, 41) which are connected to the same bus (DL, DLN) at the output side, and also comprising a selection circuit (T5, T6) for selecting a single sense amplifier (40, 41), further characterized in that the selection circuit comprises a first and a second transistor (T5, T6) in each sense amplifier (40, 41), a channel of said first and second transistors (T5, T6) being included in the first and the second current branch, respectively, between a supply terminal (Vdd) on the side and a drain of the respective control transistor (T1, T2) on the other side, the coupled gates of said first and second transistors (T5, T6) receiving a selection signal (Ysel) for the selective activation of a single sense amplifier (40, 41). An integrated field-effect transistor memory circuit as claimed in Claim 1, 2 or 3, characterized in that the memory circuit comprises several sense amplifiers (40, 41) which together comprise one common pair of load transistors (T3, T4), the load transistors being coupled between the bus (DL, DLN) and a first supply terminal (Vss), there being provided a selection circuit (T5, T6) for the selective activation of a single sense amplifier (40, 41). An integrated field-effect transistor memory circuit as claimed in Claim 4, in which the selection circuit comprises selection transistors (T5, T6), characterized in that channels of the relevant selection transistors (T5, T6) are connected between a drain of the relevant control transistor (T1, T2) and a second supply terminal (Vdd).

Inventors: SEEVINCK EVERT, SEEVINCK, EVERT
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: G11C7
IPC codes: G11C11, G11C7