Optical semiconductor device

Abstract: Disclosed herein is a semiconductor device comprising a region in which carriers are transferred in the lamination direction of a multiple quantum well, such as a multiple quantum well multiplication layer of a superlattice APD, wherein a superlattice structure with a varying well width is introduced to a hetero-interface present in the transfer region, thereby preventing pile-up of the carriers.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, more particularly to a semiconductor device which is especially preferable when applied to a semiconductor device having a hetero-interface therein, such as light receiving elements, e.g., avalanche photodiode (APD) or PIN photodiode, and optical modulators. 2. Description of the Related Art The APDs, which per se have a multiplication function, are widely used in the field of optical communication because of their wide bandwidth and high gain. In consideration of application of the APDs to high-speed optical communication systems with modulation speeds on the order of 10 Gb/s, however, there is a technical problem to be solved. That is, it is required to overcome the so-called pile-up phenomenon in which the transfer of photo-carriers is impeded at a hetero-interface in a high field application region. As countermeasures against the pile-up, there have been proposed: (1) a method in which a material having a band-discontinuity value between those of two materials constituting the hetero-interface is introduced to the hetero-interface (J. C. Cambell et. al. 'InP/InGaAsP/InGaAs avalanche photo diodes with 70 GHz gain band product' Appl. Phys. Lett. 51, 1454 (1987)); (2) a method in which a graded gap superlattice is introduced to the hetero-interface (JP-A-61-224 468 or F. Capasso et. al. 'Pseudo-quaternary GaInAsP semiconductors: A new GaInAs/InP graded gap superlattice and its applications to avalanche photo diodes' Appl.Phys. Lett. 45(11) p.1193-1195 (1984)); and (3) a method in which a semiconductor laminate transition region having an extra thin film barrier layer is provided (Japanese Patent Application Laid-Open (KOKAI) No. 61-224468 (1986)). The above-mentioned techniques are intended to cope with the pile-up at the hetero-interface in APD or PIN photodiodes, represented by light receiving elements. However, the pile-up phenomenon is considered to cause hindrance of high-speed operations, also in many other semiconductor devices such as optical modulators. None of the three techniques according to the prior art can prevent the pile-up satisfactorily. For instance, it is difficult to achieve high-speed operations on the order of 10 GHz, even with these techniques. This is because these techniques employ a structure in which an absorption layer and a multiplication layer are separate from each other, with a bulk semiconductor being used for the multiplication layer. Especially in the method of (1) above, the problem of band-discontinuity at the hetero-interface is left essentially unsolved. In the method of (2) on the other hand, it is necessary to use a barrier layer with a large film thickness at part of the structure, leading to an increase in the time required for the carriers to pass through the superlattice. With the superlattice APD, it is yet impossible on a practical basis to accomplish a high-speed operation on the order of 10 GHz or above. This is probably because the hetero-interface present in a superlattice multiplication layer causes pile-up. Therefore, it is required to introduce a novel structure for suppressing the pile-up phenomenon, even in the multiplication region of the so-called superlattice APD. SUMMARY OF THE INVENTION It is an object of the present invention % provide a semiconductor device of high speed which is less affected by carrier pile-up of an interface between different layers. This object is solved by the device set forth in claim 1. Particular embodiments of the invention are specified in the dependent claims. An advantage of this invention resides in that the pile-up phenomenon at the hetero-interface in a semiconductor device, e.g. superlattice APD, as mentioned above can be prevented substantially perfectly and, therefore, a semiconductor device capable of extremely high response can be realized. Especially when the invention is applied to the APD, a high-speed performance of 10 GHz or more is obtainable. Another advantage of the invention lies in that it is possible to increase the ionization rate (ratio), thereby realizing a semiconductor device with a further enhanced high-speed performance and a reduced noise. A still further advantage of the invention resides in that it is possible to produce a semiconductor device while fulfilling easily the lattice match conditions during the crystal growth process in the production, and therefore to maintain satisfactorily the intrinsic feature of the element, such as enhanced yield (in the case of light receiving elements, particularly a reduced dark current). Still further advantages of the present invention will apparent to those of ordinary skill in the art upon reading and understanding the following detailed description of the preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS The invention may take form in various parts and arrangements of parts. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Figure 1 is a band diagram of a miniband in a conventional superlattice; Figure 2 is a band diagram of a miniband in a superlattice employed in this invention; Figures 3 and 6 are each a sectional view of an APD according to one embodiment of this invention; Figure 4 is a band diagram of a superlattice multiplication layer in an APD according to one embodiment of this invention; Figure 5 is a diagram illustrating an optical transmission system; and Figure 7 is a sectional view of an optical modulator according to one embodiment of this invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The miniband transfer according to this invention will now be explained in detail, taking as an example an application of the miniband transfer to a superlattice APD. A detailed explanation of an application of the miniband to other semiconductor elements would be similar to the following. A band diagram of a miniband formation is shown in Figure 1, in which Ec and Ev represent a conduction band and a valence band, respectively. The miniband, corresponding to the hatched region in the figure, is the band-like region of allowed states extending throughout a superlattice comprising a periodic structure of less than about 100 Å (10Å= 1nm) thick well layers and barrier layers, caused by interactions between the electrons located in different wells. It is known that the transfer time of carriers in the miniband is shortened sharply when the film thickness of the barrier layers is reduced to about 30 Å. According to the invention, a superlattice structure is introduced to a hetero-interface at which pile-up would otherwise occur, in order to prevent the pile-up by use of carrier transfer in the miniband. As has been mentioned above, in an ordinary miniband the well layers and the barrier layers in the periodic structure have substantially equal respective thicknesses. Since an APD is used in a high electric field with an operation voltage of several tens of volts, however, no miniband is formed by the above-mentioned superlattice under the operation voltage of the APD. The present invention uses a superlattice structure as shown in Figure 2 at each well-barrier heretojunction of a superlattice structure. In the figure, Ec and Ev represent a conduction band and a valence band, respectively, and the hatched area represents a miniband formed upon application of a voltage. The superlattice structure 22 is disposed at the hetero-interface of a narrow bandgap material 21 and a wide bandgap material 23. This invention has the typical characteristics as follows: (1) The film thickness of the barrier layers is desirably not more than 4 nm from the viewpoint of miniband formation, and is desirably not more than 3 nm in order to shorten the carrier transfer time in the miniband. (2) The film thickness of the well layers decreases monotonously, from the narrow bandgap material side toward the wide bandgap material side. (3) The number of the barrier layers is desirably large, from the viewpoint of miniband formation, but, for better high-speed performance, the number is desirably small. Taking both points into account, the number of the barrier layers should be in the range from one to ten. It is more desirable that the film thickness of the barrier layers is not more than 2 nm, and that the number of the barrier layers is one to five. Also, it is desirable that the superlattice pile-up prevention layer 22 comprise a combination of the materials 21 and 23 which constitute the hetero-interface. With such a combination it is possible to fulfill easily the lattice match conditions in the production of the intended element, and to form the miniband easily. The introduction of the superlattice structure having the characteristics mentioned above ensures that the quantum levels of the wells in the superlattice conform to each other in the vicinity of the miniband when the operation voltage of the APD is applied, resulting in the formation of the miniband as denoted by 24 in Figure 2. Consequently, the carriers which would be accumulated at the hetero-interface between the materials 21 and 23 in the absence of the superlattice structure (the carriers in this case are atoms in the conduction band) are now transferred into the material 23 through the miniband in a short time. Thus, the pile-up is prevented. This invention will now be described more in detail below with reference to some specific embodiments. Example 1 One embodiment of this invention will be explained with reference to Figures 3 and 4. Figure 3 shows a structural view of a superlattice APD according to the invention. Denoted by numerals 32 to 36 are a p-InAlAs buffer layer (p = 2 x 10 18 cm -3 , film thickness d = 1.0 µm), a p-InGaAs absorption layer (p = 5 x 10 15 cm -3 , d = 1.2 µm), a p-InAlAs field adjusting layer (p = 5 x 10 16 cm -3 , d = 0.2 µm), an undoped superlattice multiplication layer ( d = 0.5 µm, n < 1 x 10 15 cm -3 ), and an n-InAlAs buffer layer (d = 1.0 µm, n = 2 x 10 18 cm -3 ), respectively. The junction diameter and the light reception diameter are 40 µm and 20 µm, respectively. The superlattice structure for miniband transfer according to this invention is disposed inside the superlattice multiplication layer 35, at the 33-34 interface and at the 34-35 interface. The details of the superlattice multiplication layer 35 are shown in Figure 4. The superlattice multiplication layer has a periodic structure of ten combinations of an InGaAs well layer 41 (d = 20 nm) an InAlAs barrier layer 43 (d = 10 nm), and a superlattice structure 42 of the invention (d = 20 nm). The superlattice structure 42 comprises four combinations of InAlAs barrier layer 45 (d = 1 nm) and InGaAs well layer 46, the well layers differing in film thickness. The film thickness values of the InGaAs well layers 46 are 5.5, 4.5, 3.5 and 2.5 nm, in this order from the side of the well layer 41. This geometry has been designed so that a miniband 44 is formed when an electric field of about 300 kV/cm is applied to the superlattice multiplication layer 35. The above element is fabricated by the process as follows. Crystal growth was carried out by an MBE method using a solid source. A growth temperature of 500°C and an arsenic pressure of 1.3 mPa are used. A substrate of n-InP 37 (n = 2 x 10 18 cm -3 , d = 400 µm) is used, and the InGaAs and InAlAs grown are set in lattice match to the substrate with accuracy within 0.02%. Mesa-etching is carried out by wet etching based on a dichromic acid or dichromate system. For a p-electrode 31, Ti/Au formed by evaporation using an electron beam is used, whereas AuGeNi/Au formed by evaporation based on a resistance heating system is used for an n-electrode 38. Now, the characteristics of the element will be shown. The breakdown voltage is 33 V, and the dark current is 40 nA at a multiplication factor of 1, and is 1 µA under an applied voltage (30 V) equal to 0.9 times the breakdown voltage. The quantum efficiency for an incident light wavelength of 1.55 µm is 60%. The ionization rate ratio determined by noise measurement is about 5 at a multiplication factor of 10. Analysis of high-frequency characteristics by a network analyzer gives a cut off frequency of 11 GHz, for 3 dB down at a multiplication factor of 10. The high-speed performance and high gain arise from the effect of the pile-up prevention layer (42 in Figure 4) formed by use of the superlattice according to the invention. To confirm this effect, an element devoid of the pile-up prevention layer 42 in Figure 4 was prepared, and the high-frequency characteristics thereof were compared with those of the above element according to the invention. The comparative element gives a maximum cut off frequency of only up to 1.5 GHz, with the multiplication factor at that point being 4. These results show that the introduction of the superlattice structure of this invention is extremely effective for enhancing the high-speed performance of APD. Also, with the element according to this invention, a simple transmission experiment is carried out using a transmission system as shown in Figure 5. A random signal with a bandwidth of 10 Gb/s generated by a signal generator is used to drive a DFB-LD through a driver. An optical signal thus generated is transmitted through a 100 km long optical fiber, to be received by the APD according to the invention. An electrical signal obtained through conversion by the APD is amplified by an amplifier, and minimum receiver-sensitivity at various error rates is determined by use of an error detector. In the 10 Gb/s transmission experiment carried out using the DFB laser with an oscillation wavelength of 1.55 µm, a minimum receiver-sensitivity of -30 dBm is obtained at a bit error rate of 10 -9 . Example 2 Another embodiment of an InGaAs/InAlAs superlattice APD will be explained with reference to Figure 6. Figure 6 shows a sectional view of the element according to this embodiment. The element is a back-illumination type element mounted facedown. Denoted by numerals 51 to 55 are a p-InAlAs buffer layer, a p-InGaAs absorption layer, a p-InAlAs field adjusting layer, an undoped superlattice multiplication layer, and an n-InAlAs buffer layer, respectively, which correspond respectively to the layers 32 to 36 in Example 1. The values of film thickness and carrier concentration of the layers 51 to 55 are the same as those of the layers 32 to 36. The structure of the superlattice multiplication layer is also the same as in Example 1 shown in Figure 4, and comprises a pile-up prevention layer 42 using the superlattice according to the invention. In Figure 6, numeral 57 denotes a p-InP (p = 5 x 10 18 cm -3 , d = 400 µm), 56 and 58 denote an n-electrode and a p-electrode, respectively, and 59 denotes a light incidence portion formed by boring a 350-µm deep hole in a substrate. The junction diameter of the element is 20 µm. The fabrication process of this element is fundamentally the same as in Example 1. The main characteristics of the element are: a breakdown voltage of 35 V, a dark current of 80 nA at a multiplication factor of 1, a quantum efficiency of 55% (λ = 1.55 µm). The 3-dB cut off frequency is 12 GHz (multiplication factor 10). Although the invention has been described above with reference to its application to an InGaAs/InAlAs superlattice APD, the invention is applicable to InP/InGaAs APDs and GaSb/GaAlSb APDs, also. Example 3 Figure 7 shows an embodiment of an optical modulator using the miniband transfer of the invention. This modulator is an absorption type optical modulator employing the quantum-confinement Stark effect produced when a reverse bias is applied to a multiple quantum well layer 74. An n-InAlAs clad layer 75, an undoped multiple quantum well optical waveguide layer 74 and a p-InAlAs clad layer 73 are provided on n + -InP 76, and an n-electrode 77 and a p-electrode 71 are provided at lower and upper portions. Denoted by 72 is an SiN film serving as an insulating film for the p-electrode and serving also for passivation of side surface portions of a ridge portion. The width of the waveguide in the ridge portion is 5 µm, and the element length is 200 µm. The optical waveguide 74 comprises a miniband structure of the invention therein, with the fundamental construction being the same as in Figure 4, except that the well width was adjusted to 5 nm. in accordance with an operation wavelength of 1.5 µm. The fabrication process of this element is substantially the same as in Example 1. This modulator shows an extinction ratio of 20 dB and a bandwidth of 10 GHz. The above examples have been described with principal reference to the elements in which the film thickness of the barrier layer for forming the miniband is I nm. As has also been described above, however, the invention is not limited to this thickness value. Although the invention has been mainly described with reference to photodiodes, it is to be appreciated that other optical devices are applicable, including optical modulators, imaging devices, and the like.

Claims: A semiconductor device including a first semiconductor layer (36, 55, 75), a second semiconductor layer (35, 54, 74) disposed over said first semiconductor layer and comprising a first superlattice structure (41, 43) having first well regions (41) and first barrier regions (43) alternately disposed, and a third semiconductor layer (32, 33, 34; 51, 52, 53; 73) disposed over said second semiconductor layer, wherein said second semiconductor layer (35, 54, 74) further comprises second superlattice structures (42) each disposed between a respective first well region (41) and a respective first barrier region (43) and having second well regions (46) and second barrier regions (45) alternately disposed, wherein the thicknesses of the second well regions (46) increase with increasing distance from the respective first barrier region (43); so that a miniband (44) is formed in each of said second superlattice structures whereby pile-up of carriers at the interfaces between the first well regions and the first barrier regions is reduced. A device according to claim 1, wherein the second barrier regions (45) include the same material as the first barrier regions (43) and the second well regions (46) include the same material as the first well regions (41). A device according to any of claims 1 to 2, wherein each of the first and second well regions (41, 46) comprises a layer of InGaAs and each of the first and second barrier regions (43, 45) comprises a layer of InAlAs. A device according to any of claims 1 to 3, wherein the first semiconductor layer (36, 55, 75) comprises a layer of InAlAs and the third semiconductor layer (32,34;51,53;73) comprises a layer of InAlAs. A device according to any of claims 1 to 4, said device being a photodiode, wherein said first semiconductor layer is a buffer layer (36, 55) of said photodiode, said second semiconductor layer is a superlattice multiplication layer (35, 54) of said photodiode, and said third semiconductor layer is an absorption layer (33, 52) of said photodiode. A device according to claim 5, wherein the photodiode further includes a field adjusting layer (34, 53) disposed between the superlattice multiplication layer (35, 54) and the absorption layer (33, 52). A device according to claims 5 or 6, wherein the absorption layer (33, 52) comprises a layer of InGaAs. A device according to any of claims 1 to 4, said device being an optical modulator, wherein said first semiconductor layer is a first clad layer (75), said second semiconductor layer is a multiple quantum well optical waveguide layer (74) of said optical modulator, which multiple quantum well optical waveguide layer is disposed on said first clad layer, and said third semiconductor layer is a second clad layer (73) disposed on said multiple quantum well optical waveguide layer.

Inventors: HANATANI SHOICHI, ISHIDA KOJI, NAKAMURA HITOSHI, NOTSU CHIAKI, OHTOSHI TSUKURU, HANATANI, SHOICHI, ISHIDA, KOJI, NAKAMURA, HITOSHI, NOTSU, CHIAKI, OHTOSHI, TSUKURU
Applicants: HITACHI DEVICE ENG, HITACHI LTD, HITACHI DEVICE ENGINEERING CO., LTD., HITACHI, LTD.
Application year: 1990
Main classification: H01L31
IPC codes: H01L31