Loaded line phase shifter

Abstract: Disclosed is a loaded line phase shifter using strip lines formed on a semiconductor substrate (1), which includes a main line (3) constituted by a strip line having an electrical length of a half-wavelength, loaded lines (4) each constituted by strip lines connected to both ends of the main line (3), a field effect transistor (8) having its source electrode (7) and its drain electrode (5) connected to positions spaced apart from nodes of the loaded lines (4) and the main line (3), a bias circuit (12) constituted by a strip line (9,10,11) connected to a gate electrode (6) of the field effect transistor (8) for controlling a bias voltage applied to the gate electrode (6), and a resonant line (17) constituted by a strip line connected between the source electrode (7) and the drain electrode (5).

Description: FIELD OF THE INVENTION The present invention relates to loaded line phase shifters for controlling a phase shift amount by inserting susceptance loads into a main line in parallel to change the electrical length of the main line. BACKGROUND OF THE INVENTION Figure 7 is a diagram showing an example of a conventional loaded line phase shifter formed on a semiconductor substrate, and Figure 8 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in Figure 7. In Figure 7, reference numeral 1 denotes a semiconductor substrate formed of silicon, GaAs or the like, and 2 denotes a grounding conductor formed on the bottom surface of the semiconductor substrate 1 by metallizing a conductor such as gold. Reference numeral 3 denotes a main line of the loaded line phase shifter, and reference numerals 18 denote loaded lines loaded to the main line 3 with spacing of approximately one quarter-wavelength. Reference numerals 5a and 5b denote drain electrodes of field effect transistors (referred to as FETs hereinafter), 6a and 6b denote gate electrodes of the FETs, and reference numeral 19 denotes a common source electrode of the two FETs. The drain electrode 5a, the gate electrode 6a and the source electrode 19 constitute an FET 8a, and the drain electrode 5b, the gate electrode 6b and the source electrode 19 constitute an FET 8b. Reference numerals 9a and 9b denote high impedance lines approximately one quarter-wavelength long, 10a and 10b denotes low impedance lines approximately one quarter-wavelength long, and 11a and 11b denote bias pads for receiving a driving bias voltage from the exterior. The high impedance line 9a, the low impedance line 10a and the bias pad 11a constitute a distributed constant bias circuit 12a, and the high impedance line 9b, the low impedance line 10b and the bias pad 11b constitute a distributed constant bias circuit 12b. Reference numeral 13 denotes a high impedance line approximately one quarter-wavelength long, 14 denotes a low impedance line approximately one quarter-wavelength long, and 15 denotes a grounding pad. The high impedance line 13, the low impedance line 14 and the grounding pad 15 constitute a grounding bias circuit 16, which is connected to the main line 3. In addition, reference numeral 20 denotes a gold wire for grounding the source electrode 19, 24 denotes an input terminal, and 25 denotes an output terminal. Description is now made of the operation of the loaded line phase shifter. In the loaded line phase shifter having the above described structure, the same driving bias voltage must be always applied to the two FETs 8a and 8b. This driving bias voltage is switched to a forward bias (zero volt) or a reverse bias (minus several volts) to change the impedances of the FETs 8a and 8b and therefore, to change susceptance values of the loaded lines 18 viewed from the main line 3. The loaded line phase shifter exercises control such that the difference in transmission phases at that time becomes a desired value. The grounding conductor 2 is grounded by soldering into a chassis or the like. The driving bias voltage is applied to the gate electrodes 6a and 6b from the distributed constant bias circuits 12a and 12b, respectively. In order to normally operate the FETs 8a and 8b as FETs at that time, the common source electrode 19 is grounded by the gold wire 20 or the like and the drain electrodes 5a and 5b are grounded by grounding the grounding pad 15 using the gold wire or the like, so that the common electrode 19 and the drain electrodes 5a and 5b are set at the same voltage level as that of the grounding conductor 2. When the driving bias voltage is the forward bias, the FETs 8a and 8b enter the on state, so that an FET portion is brought to a low resistance of several ohms, which is considered to be a short-circuited state. Accordingly, in this case, the impedance of the FET portion viewed from nodes of the main line 3 and the loading lines 18 becomes inductive. On the other hand, when the driving bias voltage is the reverse bias, the FETs 8a and 8b enter the off state, so that the FET portion enters a state where a capacitance between the source electrode and the drain electrode and a high resistance of several kilo-ohms are connected in parallel. Accordingly, in this case, the impedance of the FET portion viewed from the nodes of the main line 3 and the loading lines 18 becomes capacitive. As described in the foregoing, the bias voltage applied to the gate electrodes 6a and 6b is changed to make the FETs 8a and 8b inductive stubs or capacitive stubs, thereby to change the phase of a wave propagating along the main line 3 so that the loaded line phase shifter is operated as a phase shifter. In the conventional loaded line phase shifter formed on the semiconductor substrate, however, the susceptance values of the two loaded lines 18 are respectively changed using the different FETs 8a and 8b as described above. Accordingly, variations in characteristics between the two FETs 8a and 8b introduces the problem that phase characteristics and insertion loss characteristics or the like of the phase shifter are degraded, so that desired phase characteristics can not be obtained. Figure 9 shows an example of a loaded line phase shifter constructed so as to make variations in characteristics between the FETs as small as possible in consideration of the above described problem. More specifically, Figure 9 is a circuit diagram showing a loaded line phase shifter in another conventional example, which is disclosed in Japanese Patent Laying Open Gazette No. 51602/1984, and Figure 10 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in Figure 9. In Figs. 9 and 10, the same reference numerals as those in Figures 7 and 8 refer to the same portions. A reference numeral 21 denotes a penetrating conductor 21 for grounding a source electrode 19, 22 denotes a capacitor connected to both gate electrodes 6a and 6b, and 23 denotes a bias circuit having its end connected to the capacitor 22. This loaded line phase shifter is adapted such that the source electrode 19 is made common to two FETs 8a and 8b, connected to respective end terminals of loaded lines 18 connected to the main line 3 with spacing of one quarter-wavelength, to make the FETs 8a and 8b as close to each other as possible and the common source electrode 19 is connected to a grounding conductor 2 by the penetrating conductor 21 so as to decrease variations in characteristics between the FETs. In addition, the capacitor 22 is connected to both the gate electrodes 6a and 6b and the bias circuit 23 is connected to one end of the capacitor 22, to apply a bias voltage to the gate electrodes 6a and 6b. In the loaded line phase shifter having this structure, the bias voltage applied to the gate electrodes 6a and 6b through the bias circuit 23 are changed to change susceptance values of the loaded lines 18 loaded to the main line 3 with spacing of one quarter-wavelength, thereby to change the phase of a wave propagating along the main line 3, as in the above described loaded line phase shifter in the first conventional example. In the above described structure, the FETs 8a and 8b are provided in close proximity to each other at the end terminals of the loading lines 18. Accordingly, the loaded line phase shifter has the advantage that variations in characteristics between the FETs 8a and 8b can be prevented, as compared with the above described loaded line phase shifter in the first conventional example shown in Figure 6. In addition, a single bias circuit is used for determining the bias voltage applied to the gate electrodes 6a and 6b. Accordingly, the loaded line phase shifter has the advantage that the bias circuit can be simplified. In the structure of the loaded line phase shifter in the above described second conventional example, variations in characteristics between the FETs 8a and 8b can be decreased but can not be completely eliminated. Furthermore, in the above described both first and second conventional examples, the source electrode 19 must be grounded. Consequently, various problems arise. More specifically, in the first conventional example, the source electrode 19 is grounded by the gold wire 20. Accordingly, variations in the effect of an inductance component of the gold wire 20 on the entire phase shifter is caused due to the effect of non-uniformity of the length of the gold wire 20, so that phase characteristics of the phase shifter is changed, thereby introducing the problem of degrading insertion loss characteristics and the voltage standing wave ratio (referred to as VSWR hereinafter) of the phase shifter. In addition, the source electrode 19 must be formed in a chip end in order to reduce such degradation of the performance of the phase shifter due to the inductance component of the gold wire 20 to the upmost, whereby there are limitations in pattern design. Furthermore, in the second conventional example, the source electrode 19 is grounded using the penetrating conductor 21. Also in this case, an inductance component of the penetrating conductor 21 can not be ignored, thereby presenting the same problem as that in the first conventional example. In addition, although the degree of freedom in pattern design is increased, there is a problem that complicated manufacturing processes are required to form the penetrating conductor 21. SUMMARY OF THE INVENTION An object of the present invention is to provide a loaded line phase shifter capable of solving degradation of the performance of the phase shifter due to the effects such as non uniformity of characteristics between FETs and a gold wire as well as removing the restrictions in pattern design due to a source electrode. Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter. The present invention is directed to a loaded line phase shifter having a main line and loaded lines each comprising a stripe line formed on a semiconductor substrate and an FET formed on the semiconductor substrate, the loaded line phase shifter being adapted such that the electrical length of the main line is set to a half-wavelength, the loaded lines are connected to both ends of the main line, a source electrode and a drain electrode of the FET are respectively connected to positions spaced apart from nodes of the main line and the loaded lines by the same electrical length, a bias circuit comprising a strip line for controlling a bias voltage is further connected to a gate electrode of the FET, and a resonant line comprising a strip line is connected between the source electrode and the drain electrode. The loaded line phase shifter according to the present invention is operated by setting spacing between the loaded lines connected to the main line to a half-wavelength, connecting end terminals of the two loaded lines to the source electrode and the drain electrode of the FET, and controlling the gate voltage of the FET. Accordingly, susceptance values of the two loaded lines can be controlled by a single FET and the source electrode need not be grounded. consequently, degradation of the performance of the phase shifter due to the effects such as non-uniformity of characteristics between the FETs connected to the loaded lines and grounding of the source electrode by the gold wire in the conventional examples can be prevented. In addition, the degree of freedom in patter design can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view showing a structure of a loaded line phase shifter according to an embodiment of the present invention; Figure 2 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in Figure 1; Figure 3 is a diagram showing an equivalent circuit of a loaded line phase shifter according to an embodiment of the present invention at the time when an FET for controlling susceptance values of loaded lines is brought to the on state; Figure 4 is a diagram showing an equivalent circuit of the loaded line phase shifter according to an embodiment of the present invention at the time when an FET for controlling susceptance values of the loaded lines is brought to the off state; Figure 5 is a diagram showing an example of the results of simulation of the loaded line phase shifter according to an embodiment of the present invention; Figure 6 is a diagram showing a case in which a multiple-bit loaded line phase shifter is constructed as a loaded line phase shifter according to another embodiment; Figure 7 is a perspective view showing an example of a conventional loaded line phase shifter; Figure 8 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in Figure 7; Figure 9 is a diagram showing a loaded line phase shifter in another conventional example; and Figure 10 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in Figure 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings. Figure 1 is a perspective view showing a loaded line phase shifter according to an embodiment of the present invention. In Figure 1, the same reference numerals as those in the above described conventional loaded line phase shifter refer to the same portions. Loaded lines 4 are connected to a main line 3 with spacing of an electrical length of a half-wavelength. A reference numeral 17 denotes a resonant line comprising a strip line. Figure 1 illustrates only a substrate portion of the loaded line phase shifter. When the loaded line phase shifter is actually used as a phase shifter, a grounding conductor 2 is grounded by soldering the semiconductor substrate 1 into a chassis or the like and a grounding pad 15 is grounded by a gold wire or the like. The loaded line phase shifter according to the present invention is adapted such that the two loaded lines 4 whose lengths are set depending on a desired phase shift amount are loaded to the main line 3 with spacing of a half-wavelength, and end terminals of the two loaded lines 4 are respectively connected to a source electrode 7 and a drain electrode 5 of an FET 8. A strip line 17 for resonance is connected between the source electrode 7 and the drain electrode 5 of the FET 8, and a distributed constant bias circuit 12 comprising a high impedance line 13, a low impedance line 10 and a bias pad 11 is connected to a gate electrode 6 of the FET 8, thereby to control a driving bias voltage applied to the gate electrode 6. In addition, a grounding bias pad 16 comprising a high impedance line 13, a low impedance line 14 and a grounding pad 15 is connected to the main line 3. Furthermore, Figure 2 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in Figure 1. In Figure 2, a reference numeral 24 denotes an input terminal, and a reference numeral 25 denotes an output terminal. The driving bias voltage applied to the gate electrode 6 of the FET 8 is changed to a forward bias (zero volt) or a reverse bias (minus several volts) by the distributed constant bias circuit 12 to change the impedance of the FET 8 and therefore, to change susceptance values of the loaded lines 4 viewed from the main line 3. The loaded line phase shifter exercises control such that the difference in transmission phases at that time becomes a desired value, thereby to change the phase of a wave propagating along the main line 3 so that the loaded line phase shifter is operated as a phase shifter. First, description is now made of a case in which the gate driving bias voltage is the forward bias. At the time of the forward bias, the FET 8 enters the on state, so that an FET 8 portion can be considered to be a low resistance. Furthermore, on this occasion, the electrical length of the main line 3 is a half-wavelength. Accordingly, it follows that the phases of high frequencies inputted to the FET 8 from the two loaded lines 4 are reversed by 180°. Consequently, high frequency components of both the loaded lines 4 cancel each other in the FET portion 8, so that the loaded lines 4 can be considered to be grounded. Accordingly, grounding of the loaded lines 4 to a grounding conductor is not required. In this case, the impedances viewed from nodes of the loaded lines 4 and the main line 3 toward and end of the FET 8 becomes inductive. Consequently, the equivalent circuit enters a state in which both the loaded lines 4 are grounded as shown in Figure 3. Description is now made of a case in which the gate driving bias voltage is the reverse bias. At the time of the reverse bias, the FET 8 enters the off state. In the FET portion 8, a capacitance between the source electrode 7 and the drain electrode 5 and the resonant line 17 constitute a resonant circuit, so that the impedance of the resonant circuit at a frequency to be used is increased to infinity. Accordingly, the impedances viewed from the nodes of the loading lines 4 and the main line 3 toward the end of the FET 8 becomes capacitive, so that the end terminals of the loaded lines 4 can be considered to be opened. Consequently, the equivalent circuit becomes as illustrated in Figure 4. An example of circuit constants of the main line 3, the resonant line 17 and the loading line 4 in a case where the loaded line phase shifter according to the present embodiment constitutes a 45° bit phase shifter, a 22.5° bit phase shifter and a 11.25° bit phase shifter will be described in Table 1. where Z: characteristic impedance E: electrical length An example of the results of simulation in a case where the loaded line phase shifter has the lines having such circuit constants and uses an FET 8 having a source-drain resistance of 3.5Ω at the on time and having a capacitance value of 2.6 p F and a source-drain resistance of 3 kΩ at the off time will be shown in Table 2. The range of a frequency to be used is 11.7 GHz to 12.3 GHz. Additionally, Figure 5 graphically shows a phase shift amount in the above described frequency range in each of the phase shifters. As can be seen from the above described results, the present embodiment is particularly effective in a case where the loaded line phase shifter constitutes a phase shifter having a small phase shift amount. In this case, a decrease in VSWR and insertion loss can be achieved. As described in the foregoing, the loaded line phase shifter according to the present embodiment is adapted such that a single FET is used for controlling susceptance values of the loaded lines 4 and grounding of the FET by a gold wire or the like is not required. Accordingly, the degradation of phase characteristics due to the effects such as non-uniformity of characteristics between the FETs for controlling the susceptance values of the loaded lines and the gold wire used for grounding the FETs in the conventional examples can be prevented. Consequently, a high-precision phase shifter having desired phase characteristics can be obtained with high reproducibility. In addition, the FET need not be grounded, so that the degree of freedom in pattern design and manufacturing processes can be simplified. Additionally, Figure 6 shows an example in which several FETs are added to intermediate points of loaded lines in the loaded line phase shifter having the structure according to the above described embodiment, to construct a multiple-bit loaded line phase shifter, as another embodiment of the present invention. In Figure 6, reference numerals 4a to 4c denote loaded lines, 8a to 8c denote FETs respectively connected to ends of the loaded lines 4a, 4b, and 4c, 17a to 17c denote resonant lines respectively connected between source electrodes and drain electrodes of the FETs 8a to 8c, 12a to 12c denote distributed constant bias circuits for respectively controlling bias voltages applied to gate electrodes of the FETs 8a to 8c. In the loaded line phase shifter having such a structure, only the loaded lines 4a can be used when only the FET 8a is brought to the on state, the loaded lines 4a and 4b can be used when the FETs 8a and 8b are brought to the on state and the FET 8c is brought to the off state, and all the loaded lines 4a and 4c can be used when all the FETs 8a to 8c are brought to the on state. Accordingly, the length of the loaded line is made variable by bringing each of the FETs 8a to 8c to the on state or the off state. The present embodiment has the advantage that many kinds of phase shift amounts can be obtained using a single loaded line phase shifter, in addition to the effect of the above described embodiment. As described in the foregoing, according to the present invention. the loaded line phase shifter is adapted such that the electrical length of a main line is set to a half-wavelength, loaded lines are connected to both ends of the main line, a source electrode and a drain electrode of an FET are respectively connected to positions spaced apart from nodes of the loaded lines and the main line by the same electrical length, a bias circuit comprising a strip line for controlling a bias voltage applied to a gate electrode of the FET is connected to the gate electrode thereof, and a resonant line comprising a strip line is connected between the above described source electrode and drain electrode. Accordingly a single FET can be used for controlling grounding of the source electrode by a gold wire or the like can be required, so that the present invention has the effect of being able to achieve a high-precision loaded line phase shifter unaffected by non uniformity of characteristics between FETs, the gold wire, or the like. In addition, no grounding of the FET is required, so that the present invention has the effect of being able to simplify the degree of freedom in pattern design and manufacturing processes.

Claims: A loaded line phase shifter using strip lines formed on a semiconductor substrate (1), said loaded line phase shifter comprising: a main line (3) comprising a strip line having an electrical length of a half-wavelength; loaded lines (4) each comprising a strip line connected to both ends of said main line (3); a field effect transistor (8) having its source electrode (7) and its drain electrode (5) respectively connected to positions spaced apart from nodes of said loaded lines (4) and said main line (3) by the same electrical length; a bias circuit (12) comprising a strip line connected to a gate electrode (6) of said field effect transistor (8) for controlling a bias voltage applied to said gate electrode (6); and a resonant line (17) comprising a strip line connected between said source electrode (7) and said drain electrode (5). The loaded line phase shifter as defined in claim 1, wherein respective field effect transistors (8) are provided at a plurality of positions spaced apart from respective nodes of said loaded lines (4) and said main line (3) by the same electrical length, respectively. A loaded line phase shifter comprising: a main strip line; first and second load strip lines connected to respective points of said main strip line; and a field effect transistor, the source and the drain of which are connected to said first and second load strip lines, respectively, for controlling susceptance values of the same. A multiple-bit loaded line phase shifter comprising: a main strip line; first and second load strip lines connected to respective points of said main strip line, and each having a plurality of sections; and a plurality of field effect transistors, each one thereof being associated with a respective section of each first and second load strip line and having source and drain connected respectively thereto, for controlling susceptance values of the same.

Inventors: NAKAHARA KAZUHIKO C O MITSUBIS, NAKAHARA, KAZUHIKO, C/O MITSUBISHI DENKI
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H01P1
IPC codes: H01P1