Semiconductor memory device

Abstract: There is disclosed a semiconductor memory device comprising an internal circuit (B) including a plurality of memory cells which can store data thereinto, respectively, to output, as a first output signal, data in a memory cell (MC) selected by an address signal, and an output circuit (C) adapted to receive the first outpt signal to output a second output signal corresponding thereto to the external. A power from the same external power supply (V cc , V ss is delivered to the internal circuit (B) and the output circuit (C) through power supply terminals (5 to 8), and power supply wirings (1 to 4). The power is delivered to the internal circuit (B) through a resistor (R x ) formed in the middle of the power wirings.

Description: FIELD OF THE INVENTION This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device adapted to output signals from an internal circuit, e.g., a memory cell, etc. to the external through an output circuit. BACKGROUND OF THE INVENTION To meet demands for markets using a great quantity of semiconductor integrated circuits, these circuits are being incessantly improved to have high performance. By taking an example of a semiconductor memory, explanation will now be given. As systems in which a required semiconductor memory or memories are used, there are known various systems widely spread, e.g., personal computers, transmitters, TVs, or VTRs, etc. in addition to the main memory units of computers. To meet the requirements of miniaturization, lightness in weight, and low power dissipation of these systems, it is required to replace the section where four memories of 64k × 4 bits were used until now by a single memory of 64k × 16 bits. For this reason, the demand for memories of large capacity and of the multi-bit type is increasing. In such semiconductor integrated circuits, there are many instances where a current at the time of output increases in proportion to the number of output circuits (output buffers), resulting in a great change (hereinafter referred to as an output noise) in the power supply potential and the ground potential. Accordingly, in semiconductor integrated circuits where power supply wirings of the output circuit and the internal circuit are commonly used, the internal circuit would be directly affected by the output noise, so there is a significant possibility that some erroneous operation in the circuit may take place. As a typical measure to cope with this, there is proposed means to independently provide a power supply wiring for the output circuit, or the like. FIG. 1 is a block diagram of a semiconductor integrated circuit (semiconductor memory) of a background art wherein respective power supply wirings for the internal circuit and the output circuit are independently provided. This block diagram shows an equivalent circuit of a chip mounted in a package. In FIG. 1, on the semiconductor chip A, an internal circuit B including an input circuit and an output circuit C are provided. The internal circuit B includes, in addition to the input circuit, other circuits of the semiconductor memory except for the output circuit, e.g., a memory cell array including a plurality of memory cells, a sense amplifier SA, and the like. Storage data in one selected memory cell MC is outputted to the external through the output circuit C. On the chip, power supply pads (power supply terminals) 5 to 8 are provided. These pads 5 to 8 are connected to the circuits B and C by way of wirings 1 to 4, respectively. The input sides of these pads 5 to 8 are connected to external power supplies V cc and V ss through wirings 101 to 104. These wirings 101 to 104 include all the wirings from the external power supplies V cc and V ss up to the pads 5 to 8, for example, include inner leads of the package, bonding wires, and the like. At the time when this device is used, an external pass capacitor C pass is ordinarily connected between these power supplies V cc and V ss . Furthermore, a capacitor C chip of the chip body is equivalently conceivable in the internal circuit B. This capacitor C chip is a capacitor (through a substrate or the like) between power supplies V cc and V ss in the chip. In this example, elements connected on the output side of the output circuit C out are artificially indicated by an output load C out and resistors R 1 and R 2 connected in series between the power supply V cc and the ground GND. The semiconductor integrated circuit of the background art in which the power supply wiring is separated by the internal circuit and the output circuit is constructed as shown in FIG. 1. However, this circuit has the drawbacks described below. Namely, when the output circuit operates, since charges are delivered from the capacitor C chip via a path including the pad 6, the wiring 2, the wiring 1, and the pad 5, an internal current path is formed within the chip. For this reason, the influence of the output noise appears on the power supply wiring for the internal circuit, so it is exerted on the internal circuit B. This phenomenon is accelerated by multi-bit and high speed implementations. For this reason, even if the power supply wiring is simply separated as described above, it is difficult to sufficiently suppress output noise. US-A-4 727 518 shows inserting a resistor in series with memory circuits to dampen voltage fluctuations so that capacitive parts of the memory circuits do not see substantially different fluctuations to those seen by non-capacitive parts of the circuits. US-A-3 621 302 shows a resistor coupled in series with memory circuits to reduce power consumption when in a standby state. SUMMARY OF THE INVENTION With the above in view, this invention has been made, and its object is to provide a semiconductor memory device constructed so that the influence of noise on the internal circuit can be suppressed to as little as possible. This invention provides a semiconductor memory device as set out in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1 is an equivalent circuit diagram of an embodiment of the background art; FIG. 2 is an equivalent circuit diagram of an embodiment according to this invention; FIG. 3 is an equivalent circuit diagram of a different embodiment according to this invention; and FIGS. 4A and 4B are diagrams showing the experimental results carried out for confirmation of the effects and/or advantages of this invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an equivalent circuit of an embodiment of this invention. In FIG. 2, the same reference numerals as those of FIG. 1 are attached to components identical to those of FIG. 1, respectively. The embodiment shown in FIG. 2 differs from the embodiment shown in FIG. 1 in that a resistor R x is connected in series between the pad 6 and the circuit B, i.e., in a current path to the internal circuit B. Other components are substantially the same as those of the circuit of FIG. 1. The operation of the circuit of FIG. 2 will now be described. As described above, the reason why the influence of output noise is exerted on the internal circuit B is that an internal current path is formed in the chip through the capacitor C chip of the chip body. Accordingly, if a measure is taken to allow such an internal current path to be difficult to form, then it becomes difficult influence of output noise to be exerted on the internal circuit. The embodiment of this invention is constructed so that it operates just in a manner stated above. Namely, since the resistor R x is connected in series in the internal current path, the impedance of this path increases. In contrast, the impedance of an external current path including the external pass capacitor C pass is lowered relatively. For this reason, a current which passes through the external pass capacitor C pass of the charge/discharge current increases, whereas a current which passes through the capacitor C chip of the chip body decreases. Thus, the influence on the internal circuit B of output noise is relaxed. FIGS. 4A and 4B show the experimental results for confirmation of effects and/or advantages with the embodiment of this invention. FIG. 4A is a waveform diagram of currents I in and I out flowing in the internal capacitor C chip and the external capacitor C pass of the chip, respectively. FIG. 4B is a waveform diagram of voltages (power supply voltages V cc , V ss ) of pads 6 and 7. In these figures, R0 to R2 indicate waveforms in the case where the value of the resistor R x is increased from zero stepwise, i.e., in two stages. Namely, R0 shows a waveform when the resistor R x is equal to zero. This eventually represents the waveform in the conventional case of FIG. 1 where there is no resistor R x . It is readily seen from FIG. 4A that insertion of the resistor R x decreases a current I in flowing in the internal current path, and increases a current I out flowing in the external current path. It is seen from the indication of a decrease in voltage changes on V cc line and V ss line that a desired object is achieved by changing the currents I in and I out flowing in the internal and external paths so that they increase and decrease as stated above, respectively. Namely, attention is now drawn to R0 of V cc and V ss of FIG. 4B. The reference voltage of the power supply voltage V cc is assumed to be 5 volts. Both pads 6 and 7 (V cc line, V ss line) indicate large noise amplitudes of about 2 volts, respectively. In the case where the reference voltage is 5 volts, it is apparent that such a reduction in the level of 2 volts would result in an erroneous operation in the circuit. Furthermore, if attention is drawn to the V ss line 7, this line is once level-down, and is then level-up by about 1 volt. In accordance with an increase in the level, a high level input voltage is lowered on the adjacent input terminal by an increased voltage on the V ss line 7. For this reason, a margin of a high level input voltage is not ensured, leading to erroneous operation in the input circuit. In contrast, the effect resulting from the fact that the resistor R x is inserted into the internal current path can be seen from R1 and R2 of FIG. 4B. Namely, it is seen that a reduction in the level of R1 and R2 is equal to a value of less than one half of that in the conventional case of R0, and that an increase in the level of R1 and R2 is equal to a value of less than one third of that in the conventional case of R0. FIG. 3 shows another embodiment of this invention. The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 2 only in the manner of power supply wiring in the chip A. Namely, in the chip A of FIG. 3, pads 13 and 14 are connected in parallel with these V cc and V ss , respectively, and the internal circuit B and the output circuit C are connected in parallel with these pads 13 and 14 through wirings 11A, 11B, 12A and 12B. Furthermore, the pad 13 and the internal circuit B are connected through the resistor R x . In FIG. 3, reference numerals 111 and 112 represent wirings on the input side, respectively. Also with the embodiment of such a configuration, the same effects and/or advantages as those of FIG. 2 can be provided. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory device comprising: an internal circuit (B) including a plurality of memory cells (MC) which can store data thereinto, respectively, to output, as a first output signal, data in a memory cell (MC) selected by an address signal, the internal circuit (B) having a chip capacitance (C chip ) between its power supplies lines (V cc , V ss ); and an output circuit (C) adapted to receive said first output signal to output from the device a second output signal corresponding thereto; power supply terminals (5 to 8, 13 and 14), and power supply wirings (1 to 4, 11A, 11b, 12A and 12B), adapted to deliver, power from the same external power supply (V cc , V ss ) to said internal circuit (B) and said output circuit (C); a resistor (R x ) for suppressing voltage fluctuations on the internal circuit power supply, the resistor being formed in the middle of said power supply wirings for supplying power to said internal circuit (B) such that said internal circuit (B) is supplied with power exclusively via said resistor (R x ); said power supply wiring (1, 11A) being adapted to deliver power from said external power supply directly to said output circuit . A device as set forth in Claim 1, wherein said output circuit (C) is comprised of a buffer circuit. A device as set forth in Claim 1, wherein said power supply terminal includes first separate power supply terminals (5, 8) for delivering a power to said output circuit, and second separate power supply terminals (6, 7) for delivering a power to said internal circuit, said power supply wiring including first separate power supply wirings (1, 4) for connecting said first power supply terminals (5, 8) and said output circuit (C), and second separate power supply wirings (2, 3) for connecting said second power supply terminals (6, 7) and said internal circuit (B). A device as set forth in claim 1, wherein said power supply wirings include first power supply wirings (11A, 12A) for connecting said power supply terminals (13, 14) and said output circuit (C), which are branched from said power supply terminals (13, 14), respectively, and second power supply wirings (11b, 12B) for connecting said power supply terminals (13, 14) and said internal circuit (13). A device as set forth in claim 1, wherein said power supply terminals include high voltage side power supply terminals (5, 6) adapted to be connected to a high voltage side of said external power supply, and low voltage side power supply terminals (7, 8) adapted to be connected to a low voltage side of said external power supply, said power supply wirings including high voltage side power supply wirings (1, 2) for connecting said high voltage side power supply terminals (5, 6) to said output circuit (C) and said internal circuit (B), respectively, and low voltage side power supply wirings (3, 4) for connecting said low voltage side power supply terminals (7, 8) to said output circuit (C) and said internal circuit (B), respectively. A device as set forth in claim 1, wherein said power supply terminals include a high voltage side power supply terminal (13) adapted to be connected to a high voltage side of said external power supply, and a low voltage side power supply terminal (14) adapted to be connected to a low voltage side of said external power supply, said power supply wirings including high voltage side power supply wirings (11A, 11b) for connecting said high voltage side power supply terminal (13) to said output circuit (C) and said internal circuit (B), and low voltage side power supply wirings (12A, 12B) for connecting said low voltage side power supply terminal (14) to said output circuit (C) and said internal circuit (B). A device as set forth in claim 1, wherein said internal circuit (B) and said output circuit (C) are formed in the same semiconductor chip (A), each of said power supply terminals (5 to 8; 13, 14) being comprised of a conductive pad formed on said chip (A). A device as set forth in claim 3, wherein said internal circuit (B) and said output circuit (C) are formed in the same semiconductor chip (A), said first and second power supply wirings (1, 4; 2, 3) being formed on said chip (A), each of said first and second power supply terminals (5, 8; 6, 7) being comprised of a conductive pad formed on said chip (A). A device as set forth in claim 4, wherein said internal circuit (B) and said output circuit (C) are formed in the same semiconductor chip (A), said first and second power supply wirings (11A, 12A; 11b, 12B) being formed on said chip (A), each of said power supply terminals (13, 14) being comprised of a conductive pad formed on said chip (A).

Inventors: HIYOSHI TERUYUKI, KOMATSU KENJI, NAKAGAWA KAORU, YOSHIKAWA TOHRU, HIYOSHI, TERUYUKI, KOMATSU, KENJI, NAKAGAWA, KAORU, YOSHIKAWA, TOHRU
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: G11C5
IPC codes: G11C7, H01L27, G11C5, H01L21