Packaging semiconductor chips

Abstract: A semiconductor device comprising at least one semiconductor chip (4), the or each semiconductor chip having a plurality of chip bonding pads, a package (2) which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit (8) which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads (12), and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.

Description: The present invention relates to a semconductor device which includes a package enclosing at least one semiconductor chip. In particular, the present invention relates to the packaging of multi-chip RAM assemblies. US-A-3780352 discloses a semiconductor device having the features of the pre-characterising portion of claim 1. In the semiconductor industry many advances are taking place in packaging different varieties of semiconductor components. Power components and components having high pin count are being provided with new packagings and to a lesser extent packagings for random access memories (RAMs) are also being developed. As RAMs constitute a large proportion of the electronics cost of a system, advances in packaging RAMs are very desirable. Generally, it is desired to build systems that are easy to build, easy to cool and have a high performance per unit volume. The applicant has already developed a microcomputer on a single chip (known as the "Transputer" - Transputer being a Registered Trade Mark of INMOS Limited) which attacks these problems by minimising the amount of "glue" logic needed to interface the processing chips to the memory and peripheral chips. This gives a substantial benefit in terms of processing power per unit volume. An effect of the improvement of this single chip microcomputer development is that the physical size and power consumption of the microcomputer system tends to be dominated by the amount of RAM used in the system. Typically, the microcomputer and glue logic take only 15% of the printed circuit board area, the remainder being taken by the RAM required by the system. A number of known RAM packages exist. For example it is known to have dual-inline-packages (DIPs), zig-zag-packages (ZIP), surface mount packages (SOIC or SOJ) and the so-called "flip-chip" dies. Particular examples of such packages can achieve a packing density of silicon area over printed circuit board area of above 25%, the density normally achieved only with hybrid packaging techniques which mix thin or thick film and printed circuit technologies. All of these known packages except for the flip-chip package suffer from the disadvantage that a large amount of area is required by the fan-out of the leads extending from the chips. In addition, RAMS tend to be rectangular chips, with bonding pads at the two ends thereof, whilst the packages tend to have leads along their sides and therefore considerable area is taken up in turning the leads through a right angle. In the flip-chip design, the fan-out from the chip bonding pads takes place within the area of the chip but the disadvantage of this package is that it is not surface-mount and so the package cannot be assembled on both sides of a printed circuit board. Even the existing surface-mount packages are not always ideal for mounting on both sides of a board because they have substantial thickness. The thickness is necessary partly to turn the leads under the body and also partly to give enough thickness of plastics material used for the package to give the package mechanical strength. A so-called "VSOP" single RAM chip has been produced by Mitsubishi which is very small, has short leads on a fine pitch at the ends of the package and is only lmm thick. However, the VSOP package is so small that many RAM chips are too large to fit into it. Also, it has such a small surface area that heat dissipation from the package is lower than for a larger package, although a benefit from the thinness is that there is a very short thermal path between the chip and the outside surface of the package. The present invention aims at least partially to alleviate these problems of the prior art and aims to provide a package which takes less volume than the known packages and preferably can also provide improved heat dissipation when compared to the prior art. Accordingly, the present invention provides a semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect which extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the first level interconnect, which contacts overlie the at least one semiconductor chip, characterised in that the first level interconnect comprises a printed circuit which overlies the at least one semiconductor chip in the package and comprises a plurality of electroconductive tracks disposed between two layers of insulating material, the plurality of electroconductive tracks extending between opposed rows of outer leads on respective opposed ends of the printed circuit, one of said two layers of insulating material which is remote from the or each semiconductor chip either having holes therein which reveal the said contacts which comprise bonding pads of the electroconductive tracks, or having a plurality of electroconductive vias of the electroconductive tracks extending therethrough to comprise the contacts, and the means for electrically connecting respectively comprises either a plurality of bonding wires each of which connects a respective bonding pad to a respective chip bonding pad or an array of electroconductive leads each of which connects a respective via to a respective chip bonding pad. In a particularly preferred embodiment of the invention, the semiconductor device comprises a plurality of random access memory chips. However, the present invention is not limited to the packaging of memory chips. Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings, in which:- Figure 1 is a a schematic partly-exploded cross-section through a semiconductor chip package in accordance with a first embodiment of the present invention; Figure 2 is a schematic plan of part of the semiconductor chip package of Figure 1; Figure 3 schematically illustrates the electrical connections between a semiconductor chip and the printed circuit of the package of Figures 1 and 2; Figure 4 schematically illustrates in greater detail the relationship between the electrical connections, the semiconductor chip and the printed circuit shown in Figure 3; Figure 5 schematically illustrates a portion of a strip of flexible circuit which is to form the printed circuit shown in Figures 1 to 4; Figure 6 is a schematic partly-exploded cross-section through a semiconductor chip package in accordance with a second embodiment of the present invention; Figure 7 is a schematic plan of part of the semiconductor chip package of Figure 6; and Figure 8 schematically illustrates the electrical connections between a semiconductor chip and the double-sided printed circuit of the package of Figures 6 and 7. Referring to Figure 1, there is shown a semiconductor chip package 2 in accordance with a first embodiment of the present invention. The semiconductor chip package 2 comprises a row of four RAM chips 4. The underside of each chip 4 is adhered to a thermally conductive sheet 6 which constitutes the base of the package 2. Typically, the base 6 is composed of metal. A thin printed circuit 8 overlies the four RAM chips 4. In this specification, the term "printed circuit" is intended to mean a plurality of electroconductive tracks carried on an insulating material. In this embodiment the printed circuit 8 is flexible and comprises an electroconductive layer of circuitry, e.g. an array of copper tracks 20, sandwiched between two layers of insulating material, e.g. of polyimide or epoxy. At opposed ends 10 of the flexible printed circuit 8 are provided outer leads 12 for connection to a printed circuit board (not shown) on which the package is to be mounted, the outer leads 12 being formed by exposure of the electroconductive tracks 20 in the flexible printed circuit 8. A lid 14 overlies the flexible printed circuit 8 and has the same dimensions as the base 6. The base 6 and lid 14 have peripheral flanges which are provided with complementary registration pegs and holes 16, 18 which enable the base and lid 6, 14 accurately to be located in registry with each other thereby to form a sealed package 2. The base 6 and lid 14 are adhered together e.g. by a silicone adhesive along their peripheral mating surfaces so as to seal the package. The inner volume of the package 2 may include a material (not shown) which covers the electrical connections in the package and provides protection from moisture penetration of the chips. Such a material may be, for example a conventional moulding material, a "glob top" epoxy as used in known hybrid packages or a self-healing gel contained by a non-hermetic enclosure. Figures 2 to 4 illustrate how the chips 4 are electrically connected to the flexible printed circuit 8. The flexible printed circuit 8 comprises an array of electroconductive tracks 20, each of which extends transverse to one or more of the chips 4 and in a direction extending between the opposed outer leads 12. Each track 20 is connected, depending upon its function, either to a single respective outer lead 12 at a respective end of the package 2 or to a pair of opposed respective outer leads 12 at respective ends of the package 2. The tracks 20 are parallel in that portion of the flexible circuit 8 which overlies the row of chips 4 and the tracks 20 diverge at the opposed ends of the flexible circuit 8 so as to be able to connect to a respective outer lead 12. A row of sixteen outer leads 12 is provided at each end 10 of the flexible printed circuit 8. In an alternative embodiment, a row of twenty outer leads is provided at each end of the printed circuit. Each end 10 of the flexible printed circuit 8 is also provided with registration holes 22 to enable the outer leads 12 accurately to be registered onto respective contacts on a printed circuit board (not shown). The flexible circuit 8 as described above, comprises the electroconductive tracks 20 which are sandwiched between a lower insulating layer 24 which is between the tracks 20 and the chips 4 and an upper insulating layer 26 which covers the tracks 20. The upper insulating layer 26 is provided with a number of openings 28 each of which exposes a respective bonding pad 30. The ends 32, 34 of each chip 4 are each provided, in known manner, with a row of chip bonding pads 36. Each chip bonding pad 36 is connected to a respective bonding pad 30 on the flexible circuit by a wire 38 which is bonded at its opposed ends to the two bonding pads 36, 30. The bond wires 38 comprise a second level of interconnect which is located above the first level of interconnect constituted by the flexible printed circuit. It will be seen that the interconnections are such that no bond wire 38 overlies any other bond wire 38 so as to avoid any short circuit from being made. In addition, since the tracks 20 are covered by the upper insulating layer 26 of the flexible printed circuit 8, there is no possibility of any bond wire 38 short circuiting by inadvertent contact with a track 20. In the illustrated arrangement, the width of the flexible printed circuit 8 is greater than the length of each chip 4, in order to provide sufficient mechanical strength for the flexible printed circuit. Accordingly, as shown in Figure 4, three partially-overlapping rectangular holes 40, 42, 44 are cut in the insulating layers 24, 26 of the flexible circuit 8 at a location overlying each row of chip bonding pads 36. This enables the bond wires 38 to extend upwardly through the holes 40, 42, 44 from the chip bonding pads 36 thereby to extend over the upper surface of the flexible printed circuit 8 and connect with the respective bonding pads 30. In alternative arrangements, there may be provided a group of spaced holes or slots overlying the chip bonding pads. This gives a mechanically more stable flexible printed circuit. In addition, such spaced holes are required when the invention is employed to package an integrated circuit having chip bonding pads on all four of its sides. Figure 5 shows schematically the layout of a portion of an elongate strip 45 including the thin flexible printed circuit 8 prior to connection to the chips 4. For clarity of illustration, any holes which are cut in the thin printed circuit are not shown. However, the printed circuit may be provided with registration holes to allow registration of the thin printed circuit relative to the base of the package. The strip consists of a central region 46 comprising the tracks 20 and the bonding pads 30. The strip 45 also includes the outer leads 12 at opposed ends of the central region 46. Connected to the outer leads 12 at opposed ends of the portion of the strip 45 are opposed regions of test circuitry 48 which are employed, when the flexible printed circuit 8 has been connected to the chips 4 by the bond wires 38, to test the operation of the packaged semiconductor device. The central region 46 also includes opposed, longitudinally directed regions 50 of copper which act mechanically to support the central region 46. The central and test regions 46, 48 are bounded on opposed transverse sides by lateral supporting regions 54 which are provided with rows of tractor feed holes 56 which enable the flexible printed circuit 8 to be fed along a production line in a continuous manufacturing process. Typically, there is provided an elongate strip having a row of the flexible printed circuits 8 therealong. A preferred manufacturing process will be described hereinafter. After the chips 4 have been packaged and tested, the test regions 48 and the lateral supporting regions 54 of the strip are removed so that the final flexible printed circuit 8 is as shown in Figure 2. Figures 6 to 8 illustrate a semiconductor chip package in accordance with a second embodiment of the present invention. A semiconductor package 70 consists of a base 72 e.g. of metal to which is adhered a row of semiconductor chips 74. In the illustrated embodiment, there is a row of four RAM chips 74. A flexible printed circuit 76 overlies the row of chips 74. The flexible printed circuit 76 is carried by a rectangular supporting member 78 which, in the package 70, constitutes a peripheral side wall of the package 70. A lid 80 overlies the side wall 78 and the base 72. The base 72 and the lid 80 are sealingly adhered to the side wall 78 thereby to seal the chips 74 inside the package 70. A material (not shown) for protecting the chips from moisture may be incorporated in the package 70. The thin flexible printed circuit 76 extends outwardly away from opposing longitudinal ends of the package 70 and is provided at opposing ends 82 thereof with a row of upwardly directed outer leads 84. The ends 82 of flexible printed circuit 76 are also provided with registration holes 86 to enable the package 70 to be accurately mounted on a printed circuit board (not shown). In this embodiment, the flexible printed circuit 76 has a different construction from that of the first embodiment and also a different means is employed to connect electrically the chip bonding pads to the flexible printed circuit 76. As is shown in Figures 7 and 8, the flexible printed circuit 76 employs a multi-layer tape. The flexible printed circuit 76 comprises a lower insulating layer 88 which is disposed against the upper surface 90 of the chips 74. A parallel array of electroconductive tracks 92 e.g. of copper is disposed on the lower insulating layer 88. The tracks 92 are similar to the tracks 20 of the first embodiment and are connected to respective outer leads 84 at the ends 82 of the flexible printed circuit 76. An upper insulating layer 94 covers the tracks 92. At selected locations, each track 92 is provided with an upstanding via 96 which extends through the upper insulating layer 94. Each via 96 is connected to a respective chip bonding pad 98 by a tape-automated-bonding (TAB) inner lead 100 which extends from the respective via 96 over the upper insulating layer 94 and the TAB inner lead 100 is bonded to the chip bonding pad 98. It will be understood that the insulated layers 88, 94 of the flexible printed circuit 76 are provided with holes in registry with the chip bonding pads 98, the holes being similar to the holes 40, 42, 44 provided in the first embodiment. Figure 7 shows schematically the connections made between the tracks 92 and the chip bonding pads 98 although it will of course be understood that the TAB inner leads do not require the thin wire-like connectors shown schematically in Figure 7 but rather they consist of narrow strips so as to have sufficient mechanical strength at the ends thereof which are to be bonded to the chip bond pads 98. As is clear from Figure 7, the insulating material 88, 94 of the flexible printed circuit 76 extends fully across the width of the package so as to provide increased mechanical strength for the flexible printed circuit 76. For the avoidance of doubt, it should be understood that the construction of the base and lid, as exemplified in Figures 1 and 6, is not directly dependent upon the construction of the printed circuit and the electrical connections between the printed circuit and the chips, as exemplified in Figures 3 and 8. Thus, the base/lid assembly of Figure 1 could be optionally employed in the second embodiment and the base/lid assembly of Figure 6 could optionally be employed in the first embodiment. In each of the foregoing embodiments, the flexible printed circuit may be provided with additional electroconductive and insulating layers thereby to provide a plane for power and ground which extends over the row of chips. The ground plane acts both to shield the RAMs from any noise generated by the signals across the thin printed circuit and to provide a low inductance path for the logic reference and supply voltages. In Figure 5, the ground plane outline of the flexible printed circuit is indicated by reference numeral 140. If desired, in the first embodiment the bond wires may be arranged so as to allow decoupling capacitors within the package as disclosed in US Patent No. 4744008. In each of the illustrated embodiments, the underside of each of the chips is adhered to a thermally conductive sheet constituting the base of the package. The sheet spreads the heat out between the chips so that all the chips are within a few degrees of the same temperature. The sheet also provides and exceptionally short thermal path to the external surface of the package. Particular preferred materials for the thermally conductive sheet are metals which also give excellent mechanical strength, thereby providing a mechanically sound package which is thinner than would be possible using standard package plastics. Typically, the base of the package may be made of aluminium having a thickness of around 0.038 cm. The thermally conductive sheet constituting the base is actually treated as the top of the package when the package is assembled onto a printed circuit board. As has been described above, the outer leads on the flexible printed circuit are connected to a printed circuit board and this results in the base of the package, to which the chips are adhered, being located on the side of the package which is remote from the printed circuit board. This further exploits the short thermal path from the chips to the external surface of the package since that surface is directly in contact with air and is able to irradiate heat to adjacent cooler surfaces. Radiation may be assisted, as is conventional with heat sinks, by black anodizing or painting the thermally conductive sheet and by giving the sheet a larger surface area, for example by adding fins to the sheet. This orientation of the package also puts the outer leads of the thin printed circuit in the right orientation so that they can be soldered to the printed circuit board without removing the insulating laminate of the thin printed circuit. This keeps the package leads in exact register with respect to each other and overcomes the problems of the fragility of conventional package leads. Furthermore, since a number of chips are assembled in a single package, this means that the package is large enough to dissipate the heat generated by the chips. Normally, the circuitry would be arranged so that only one or two of the chips in the package is or are active at any given time, thus providing that for the one or two active chips, an effective heat sink capability of four chips is available. It is difficult to quantify the improvement in the thermal characteristics of the packages in accordance with the present invention compared to the prior art. However, it is believed that there is a substantial improvement in the temperature differential between the chips and the ambient cooling air. A possibly more significant effect comes from the heat spreading: if one of the RAMs is accessed at a 100% duty cycle, and the others are in standby, the temperature of the RAM that is being continuously accessed will be approximately the same as a singly packaged RAM would be when running at a 25% duty cycle, because the heat is spread out over the four RAM chips. A small reduction in chip temperature can make a large improvement in the reliability of the chip, since higher operating temperatures result in reduced chip lifetimes, so that the package of the present invention can provide improved reliability of the RAM. The thermal improvements can also give cost and/or performance benefits because MOS circuits become slower and have higher leakage currents at increasing temperatures. Accordingly, since the packages of the present invention can provide improved heat sink capabilities, the performance of the RAM is improved compared to the prior art. In the packages of the present invention, the chips are connected to each other and to external leads by a thin printed circuit which lies over the active circuitry on the chip. This drastically reduces the number of leads needed to connect the package to the printed circuit board when the package is assembled thereon. For example, in the prior art 96 leads would be required by an assembly of four RAMs consisting of four separate 24 lead packages whereas in the present invention a single package containing four RAMs would require only 32 leads. In addition, the reduction in the number of leads provides a gain in reliability when compared to the prior art since a reduced number of soldered joints on the board is employed using the multi-chip RAM packages of the present invention. In each of the illustrated embodiments, mechanical tooling holes are provided adjacent the package leads so that the precise registration of the leads of the package can be extended to register with the printed circuit board without the need for pattern recognition equipment, although this could be employed if appropriate. If the insulating laminate of the thin printed circuit is removed to give unsupported leads, the tooling holes can be put into copper, thereby in effect making wide leads which are particularly appropriate for power and ground terminals. Furthermore, the packages of the present invention give great advantage over the prior art constructions in reducing the package size. In the illustrated embodiments, it will be seen that the four RAMs can be closely assembled together in the package and since the flexible printed circuit overlies the RAMs, this greatly reduces the overall size of the package. In the embodiment illustrated in Figures 1 and 2 for example, the package consists of four 64K x 4 static RAMs assembled to make 256K x 4 of static RAM in a package having the dimensions 2.64 cm x 1.30 cm x 0.19 cm. The smallest standard known package for the 64K x 4 RAM is the so-called SOJ surface mount package which has the dimensions 1.54 cm x 0.86 cm x 0.33 cm, four of which would occupy a printed circuit area (allowing for minimal gaps between components) of 3.18 cm x 1.84 cm. Thus the package in accordance with the invention gives an area improvement of about 1.7 times compared to such a known package. This improvement in area is achieved in spite of using a so-called "gull wing" style of lead, (i.e. the leads extend away from the ends of the package and are bent down towards the level of the PCB and are not folded back beneath the package). The "gull wing" style of lead employed in the present invention gives a solder joint which is much more easily inspected than the SOJ package. The reduction in height achieved by the present invention is also an improvement of about 1.7 times over the prior art, thereby giving a volumetric improvement of the package of the present invention when compared to the prior art of about three times. More significant is a reduction in height to below the 0.254 cm height of conventional solder joints on the solder side of the printed circuit board, allowing the packages of the present invention to be assembled onto the solder side of almost any printed circuit board. A further benefit from the height reduction is that a memory board 0.127 cm thick, with the RAM packages of the present invention on both sides, becomes just 0.508 cm thick, which is the height of standard dual-in line packages (DIP's). The second illustrated embodiment employs flexible circuit tape such as is used for tape automated bonding (TAB). The package in accordance with the present invention can make more effective use of the area of the flexible circuit tape than in the TAB process of the prior art since the TAB tape overlies the chips. If the TAB tape is used in accordance with the present invention, the packages can be made by a continuous flow assembly, employing static burn-in and testing, with consequential benefits in reduced costs of the finished products. This is discussed further below. It should be understood that whilst the illustrated embodiments employ a plurality of semiconductor memory chips in the packages of the present invention, the packages of the present invention can be employed to package any type of integrated circuit either singly or multiply wherein a number of integrated circuits are packaged in a single package. The illustrated embodiments respectively employ bonding wires and tape-automated-bonding (TAB) tape to form a second level of interconnect which is separated from the first level of interconnect, constituted by the tracks of the printed circuit on an insulating layer, by an insulating layer. The use of conventional bonding wires reduces the cost of the semiconductor package. However, it is also possible to use a single layer circuit and a second layer can be added for power and ground without the need for plated through holes. Such plated through holes, if used to connect to tracks acting in place of the bond wires, would need to be on a pitch of about 0.02cm, which, while possible, is not inexpensive. The packages of the present invention therefore offer a number of benefits in costs, performance and reliability compared to those of the prior art, both at the level of a single RAM package and at the level of a system which is assembled from single- or multi-chip packages and other components.

Claims: A semiconductor device (2) comprising at least one semiconductor chip (4), the or each semiconductor chip (4) having a plurality of chip bonding pads (36), a package (6,14) which encloses the at least one semiconductor chip (4), a first level interconnect which extends externally of the package (6,14) to provide a plurality of outer leads (12), and a second level interconnect comprising means (38) for electrically connecting the chip bonding pads (36) to selected contacts (30) on the first level interconnect, which contacts (30) overlie the at least one semiconductor chip (4), characterised in that the second level interconnect is located above the first level interconnect, the first level interconnect comprises a printed circuit (8) which overlies the at least one semiconductor chip (4) in the package (6,14) and comprises a plurality of electroconductive tracks (20) disposed between two layers (24,26) of insulating material, the plurality of electroconductive tracks (20) extending between opposed rows of outer leads on respective opposed ends of the printed circuit (8), one of said two layers of insulating material (26) which is remote from the or each semiconductor chip (4) either having holes (28) therein which reveal the said contacts (30) which comprise bonding pads of the electroconductive tracks (20), or having a plurality of electroconductive vias (96) of the electroconductive tracks (92) extending therethrough to comprise the contacts (30), and the means for electrically connecting respectively comprises either a plurality of bonding wires (38) each of which extends over the said one layer of insulating material (26) and connects a respective bonding pad (30) to a respective chip bonding pad (36) or an array of electroconductive leads (100) each of which extends over the said one layer of insulating material (94) and connects a respective via (96) to a respective chip bonding pad (98). A semiconductor device according to claim 1 wherein the said means for electrically connecting is disposed within the area of the at least one semiconductor chip (4). A semiconductor device according to claim 1 or claim 2 comprising a plurality of random access memory chips (RAMs). A semiconductor device according to any one of claims 1 to 3 wherein the printed circuit (8) is flexible. A semiconductor device according to any foregoing claim wherein the electroconductive leads (100) are formed from a tape automated bonded (TAB) tape. A semiconductor device (2) according to any foregoing claim, wherein the printed circuit (8) includes a plurality of registration holes (22) located externally of the package (6,14) for enabling the outer leads (12) to be registered onto a printed circuit board.

Inventors: WAKEFIELD ELWYN PAUL MICHAEL, WALKER CHRISTOPHER PAUL HULME, WAKEFIELD, ELWYN PAUL MICHAEL, WALKER, CHRISTOPHER PAUL HULME
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS LIMITED
Application year: 1990
Main classification: H01L23
IPC codes: H01L27, H01L25, H01L23, H01L21