Semiconductor device manufacturing process

Abstract: A semiconductor device manufacturing process and a bias ECRCVD apparatus for carrying out the same. The semiconductor device manufac­ turing process comprises steps of forming trenches in the surface of a substrate, forming an insulating film by bias ECRCVD over the surface of the substrate, etching the insulating film by lateral leveling etching to expand the width of grooves formed in portions of the insulating film formed in regions other than those corresponding to the trenches, masking the portions of the insulating film filling up the trenches and removing the portions of the insulating film formed in the regions other than those corresponding to the trenches. An etching stop layer is formed over the surface of the substrate before forming the trenches and the insulating film, and the etching stop layer is removed by etching after removing the portions of the insulating film formed in the regions other than those corresponding to the trenches by etching with the portions of the insulating film filling up the trenches masked. The surfaces of the portions of the insulating film filling up the trenches are finished flush with the surface of the substrate. Desirably, the etching stop layer is annealed to make the grains grow making the surface of the etching stop layer smooth to enable the complete removal of the portions of the insulating film formed in the regions other than those corresponding to the trenches.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device manufacturing process. Description of the Prior Art It is a common practice to isolate the component elements of semiconductor devices, such as ICs, LSIs and VLSIs, by a selectively oxidized film (LOCOS) formed by selectively oxidizing the surface of the semiconductor substrate. However, the use of the selectively oxidized film for isolating the elements from each other entails the formation of bird's beaks increasing critical dimension loss to make forming minute elements difficult. Therefore, a trench-isolation method, which does not form any bird's beak and causes very small critical dimension loss, has been attractive. A trench-isolation method, such as disclosed in Japanese Patent Laid-open (Kokai) No. 57-176742 or 60-53045, forms trenches in the surface of a semiconductor substrate, and fills up the trenches with SiO 2 deposited by bias ECRCVD. Figs. 6A to 6E are sectional views showing steps of an other trench-isolation method, by way of example, employing bias ECRCVD. Trenches formed in the surface of a semiconductor substrate are filled up with an insulating film through the following steps of the trench-isolation method. (A) As shown in Fig. 6A, trenches 2 are formed in the surface of a semiconductor substrate 1, and then an insulating film 3, i.e., a SiO 2 film, is formed over the surface of the semiconductor substrate 1 by bias ECRCVD so that the trenches 2 are filled up with the insulating film 3. The thickness of the insulating film 3 is substantially equal to the depth of the trenches 2. Indicated at 3a are portions of the insulating film 3 formed in the active regions on the surface of the semiconductor substrate 1. (B) As shown in Fig. 68, the portions 3a of the insulating film formed by bias ECRCVD are etched laterally as indicated by arrows by lateral levelling etching so that flat portions are not etched. The width of grooves formed in trench regions corresponding to the trenches 2 in the portions 3a of the insulating film 3 is expanded by lateral leveling etching to facilitate masking the trenches 2 with a resist film. (C) As shown in Fig. 6C, the portions of the insulating film 3 formed in the trenches 2 are masked with a resist film 4 by processing a film of a resist material applied to the insulating film 3 through a photolithographic process. (D) As shown in Fig. 6D, the portions 3a of the insulating film 3 formed in the active regions are removed by anisotropic etching using the masks of the resist film 4. (E) As shown in Fig. 6E, the resist film 4 is removed. The trench-isolation method effectively utilizing the specific properties of ECRCVD that the etching rate is smaller than the deposition rate, and the etching rate with inclined surfaces inclined to the flat surface of the semiconductor substrate is larger than the deposition rate with the same is excellent to some extent in that the trench-isolation method is able to fill up comparatively narrow trenches and comparatively wide trenches with insulating films of substantially the same thickness. Since the ordinary CVD process is featured by good step coverage, the ordinary CVD process tends to form thick insulating films in narrow trenches and thin insulating films in wide trenches, whereas the bias ECRCVD process has a less tendency to form the insulating films in such a manner. Incidentally, Figs. 6A to 6E show an ideal configuration of the insulating film in the successive steps of the bias ECRCVD process. However, in a practical bias ECRCVD process, the side surfaces of the portions 3a of the insulating film formed in the active regions are slopes 5 as shown in Fig. 7 at a stage after the lateral levelling etching step (Fig. 6B), because the inclination of the slopes 5 to the surface of the substrate 1 is nearly zero, and hence the slopes 5 are etched scarcely by lateral levelling etching. Accordingly, if the portions 3a of the insulating film 3 formed in the active regions and having the slopes 5a in their side surfaces are etched by using the masks of the resist film 4, fragments of the portions 3a of the insulating film 3 will remain under the masks of the resist film 4 as shown in Fig. 8A when an anisotropic etching process is employed or portions of the insulating film 3 formed in the trenches 2 are etched to form recesses 5b as shown in Fig. 8B when an isotropic etching process is employed. Such portions of the insulating film reduces the dielectric strength of the isolation film.. When the portions 3a of the insulating film 3 are etched by anisotropic etching to secure spaces for forming the masks of the resist film 4, portions of the insulating film formed in the trenches 2 are removed as shown in Fig. 9 and hence the trenches 2 are filled with the insulating film unsatisfactorily, which reduces the dielectric strength of the isolation film. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device manufacturing process for perfectly removing portions of an insulating film formed in active regions so that the trenches are filled up satisfactorily with the insulating film even if the side surfaces of the portions of the insulating film formed in the active regions are inclined surfaces. This object is met by a semiconductor device manufacturing process as defined in claim 1. Advantageous embodiments are defined in the dependent claims. In the semiconductor device manufacturing process in accordance with the present invention, the surfaces of portions of an insulating film filling up trenches can be finished flush with the surface of the substrate by etching the portions of the insulating film filling up the trenches by a depth corresponding to the thickness of the etching stop layer, even if the portions of the insulating film filling up the trenches are removed partially during the anisotropic etching of portions of the insulating film formed in active regions after forming the trenches and the insulating film. Accordingly, the trenches are filled up properly with the insulating film, the portions of the insulating film formed in the active regions can completely be removed, and the surfaces of the portions of the insulating film filling up the trenches are finished flush with the surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following description taken in connection with the accompanying drawings, in which: Figures 1A to 1H are sectional views showing sequential steps of a semiconductor device manufacturing process in a first embodiment according to the present invention; Figure 2 is a schematic sectional view of a bias ECRCVD apparatus for carrying out the process of the present invention; Figures 3A to 3D are sectional views showing sequential steps of a semiconductor device manufacturing process in a second embodiment according to the present invention; Figures 4A to 4D are sectional views showing sequential steps of a semiconductor device manufacturing process in a third embodiment according to the present invention; Figure 5 is a sectional view of assistance in explaining a modification of the semiconductor device manufacturing process shown in Figs. 4A to 4D; Figures 6A to 6E are sectional views showing sequential steps of a conventional semiconductor device manufacturing process; and Figures 7, 8A, 8B and 9 are sectional views of assistance in explaining problems to be solved by the present invention, in which: Fig. 7 shows slopes, Figs. 8A and 8B show a stage after the removal of portions of an insulating film formed in active regions bY anisotropic etching and by isotropic etching, respectively, and Fig. 9 shows the result of anisotropic etching for securing a space to be covered with a resist film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing process in a first embodiment according to the present invention will be described hereinafter with reference to Figs. 1A to 1H. Step (A): As shown in Fig. 1A, an etching stop layer 6 of polycrystalline silicon for stopping etching action on an insulating film filling up trenches is formed over the surface of a semiconductor substrate 1. The thickness of the etching stop layer 6 is, for example, in the range of about 500 to about 2000 Å (10Å = 1 nm). Step (B): As shown in Fig. 1B, trenches 2 are formed in the semiconductor substrate 1 by anisotropic etching. Step (C): As shown in Fig. 1C, an insulating film 3 of SiO 2 is formed on the semiconductor substrate 1 by bias ECRCVD so as to fill up the trenches 2 properly. Conditions for the bias ECRCVD, for example, are: SiH 4 supply rate: 17.5 sccm, N 2 O supply rate: 35 sccm, power of the 2.45 GHz microwave: 1000 W, power of RF bias: 500 W, magnetic flux density: 875 gauss (1gauss = 10 -4 T), and pressure: 7 × 10 -4 torr (1 torr = 133Pa). Indicated at 3a are portions of the insulating film 3 formed in active regions, namely, regions other than those corresponding to the trenches 2. Step (D): As shown in Fig. 1D, the portions 3a of the insulating film 3 are subjected to bias ECRCVD for lateral levelling etching. Conditions for the bias ECRCVD are determined so that flat portions are not etched. The conditions for the bias ECRCVD for lateral levelling etching are the same as those for the bias ECRCVD for forming the insulating film 3, except that the SiH 4 supply rate is 7 sccm. The step (D) shown in Fig. 1D is executed to secure spaces necessary for forming a resist film so as to surely mask portions of the insulating film 3 filling up the trenches 2 over and around the trenches 2. As stated above, since slopes 5 are formed, the spaces necessary for forming a satisfactory resist film cannot be secured in the step (D) shown in Fig. 1D. In Fig. 1D, indicated by alternate long and two short dashes lines are the shapes of the portions 3a of the insulating film 3 before the anisotropic etching. Step (E): As shown in Fig. 1E, the portions 3a of the insulating film 3is subjected to RIE for anisotropic etching to etch the portions 3a by a depth corresponding to the thickness of the etching stop layer 6. Conditions for the anisotropic etching, for example, are: CHF 3 supply rate: 75 sccm, O 2 supply rate: 8 sccm, power of RF bias: 1350 W, pressure: 80 millitorr, and etching mode: parallel flat plate RIE. Sufficient spaces for satisfactorily masking the portions of the insulating film 3 filling up the trenches 2 can be secured in the step (E) shown in Fig. 1E. Step (F): As shown in Fig. 1F, portions of the insulating film 3 filling up the trenches 2 are masked with a resist film 4 by photolithography. Step (G): As shown in Fig. 1G, portions 3a of the insulating film 3 formed in the active regions are removed. Step (H): As shown in Fig. 1H, the resist film 4 is removed, and then the etching stop layer 6, i.e., polycrystalline silicon film, is removed by etching using KOH. Thus, the trenches 2 are filled up properly with the insulating film 3 and the portions 3a of the insulating film 3 formed in the active regions are removed completely. Thus, the semiconductor device manufacturing process comprises sequential steps of forming the etching stop layer 6 over the surface of the semiconductor substrate 1, forming the trenches 2, forming the insulating film 3, subjecting the portions 3a of the insulating film 3 formed in the active regions to lateral levelling etching, and further subjecting the portions 3a to anisotropic etching. Consequently, the slopes in the portions 3a of the insulating film 3 formed in the active regions can completely be removed, and hence sufficient spaces for masking the portions of the insulating film 3 filling up the trenches with the resist film 4 can be secured and the portions 3a of the insulating film 3 can completely be removed. Although the anisotropic etching subsequent to the lateral levelling etching etches the surfaces of the portions of the insulating film 3 filling up the trenches 2 to some extent, the surfaces of the portions of the insulating film 3 filling up the trenches 2 become flush with the surface of the semiconductor substrate 1, because the thickness of the insulating film 3 as deposited is greater than the depth of the trenches 2 by the thickness of the etching stop layer 6. Since the active regions, i.e., the regions other than the trench regions, of the semiconductor substrate 1 are covered with the etching stop layer 6 during the anisotropic etching, it is not possible that the surface of the semiconductor substrate 1 is etched by the anisotropic etching. In etching the insulating film 3 by anisotropic etching in the step (E) shown in Fig. 1E, the insulating film 3 may be etched by a depth slightly smaller than the thickness of the etching stop layer 6 so that the portions of the insulating film 3 formed in the trench regions protrude slightly from the surface of the semiconductor substrate 1 as indicated by alternate long and two short dashes lines in Fig. 1H to secure sufficient dielectric strength at the shoulders of the trenches 2, because the dielectric strength is not reduced even if the thickness of the insulating film 3 is greater than the design thickness of the same, whereas the dielectric strength is reduced when the surfaces of the portions of the insulating film 3 filling up the trenches 2 are sunk below the surface of the semiconductor substrate 1 even by a small depth. In Fig. 1H, indicated at 3b are portions of the insulating film 3 protruding from the surface of the semiconductor substrate 1. A bias ECRCVD apparatus for carrying out the semiconductor device manufacturing process described with reference to Figs. 1A to 1H will be described hereinafter with reference to Fig. 2. The steps (C) and (D) (Figs. 1C and 1D) of the semiconductor device manufacturing process require simple bias ECRCVD and hence the steps (C) and (D) can be carried out by an ordinary bias ECRCVD apparatus. Requiring anisotropic RIE, the step (E) (Fig. 1E) cannot be carried out by an ordinary bias ECRCVD apparatus. The bias ECRCVD apparatus for carrying out the process of the present invention is capable of operating for anisotropic RIE. Referring to Fig. 2, there are shown a plasma producing chamber 11, a cooling water jacket 12, a microwave transmission window 13 formed of a quartz glass plate hermetically attached to the upper wall of the plasma producing chamber 11, a waveguide 14 placed on the upper wall of the plasma producing chamber 11, a plasma injecting opening 15 formed in the bottom wall of the plasma producing chamber 11, exciting coils 16 surrounding the plasma producing chamber 11, a reaction chamber 17 disposed under the plasma producing chamber 11, a substrate support table 18 disposed within the reaction chamber 17 directly under the plasma injecting opening 15 to support a semiconductor substrate 19, a gas supply pipe 20 for supplying a plasma source gas (1), such as O 2 , into the plasma producing chamber 11, a plasma flow 21, a gas supply ring 22a for supplying a CVD source gas (2), such as SiH 4 , for CVD into the reaction chamber 17, a gas supply ring 22b for supplying an etching gas, such as CHF 3 or NF 3 , into the reaction chamber 17, and a bias RF power source 23. The bias ECRCVD apparatus supplies the plasma source gas (1) and the CVD source gas (2) respectively into the plasma producing chamber 11 and the reaction chamber 17, energizes the exciting coils 16 to create a magnetic field and sends microwaves into the plasma producing chamber 11 to produce a plasma by ionizing the plasma source gas (1). Ions of the plasma produced in the plasma producing chamber 11 are directed onto the semiconductor substrate 19 placed on the substrate support table 18 disposed within the reaction chamber 17 by the divergent magnetic field created by the exciting coils 16. Then, the surface of the semiconductor substrate 19 is etched or a film is formed over the surface of the semiconductor substrate 19 by the vapor-phase reaction of the CVD source gas (2). The RF bias power source 23 applies a bias to the substrate support table 18 to control the CVD of the insulating film. The flow rate of the CVD source gas (2) supplied through the gas supply ring 22a into the reaction chamber 17 is changed to change the operating mode from an insulating film CVD mode to a lateral levelling etching mode. Accordingly, the step (C) (Fig. 1C) for the CVD of the insulating film 3 and the step (D) (Fig. 1D) for the lateral leveling etching can be carried out successively. Subsequently, the supply of the CVD source gas (2) through the gas supply ring 22a is stopped, and then an etching gas (3) for etching the insulating film, such as CHF 3 or NF 3 , is supplied through the gas supply ring 22b for the anisotropic RIE of the insulating film 3 including the portions 3a formed in the active regions (Fig. 1E). The bias ECRCVD apparatus in this embodiment is provided with the two gas supply rings 22a and 22b to supply the CVD source gas (2) through the gas supply ring 22a and to supply the etching gas (3) through the gas supply ring 22b. The bias ECRCVD apparatus may be provided with a single gas supply ring connected to external selector means which connects the gas supply ring selectively to one of gas sources to supply a desired source gas into the reaction chamber 17. Thus, various modifications of the bias ECRCVD apparatus for carrying out the process of the present invention are possible. A semiconductor device manufacturing process in a second embodiment according to the present invention will be described hereinafter with reference to Figs. 3A to 3D. Step (A): As shown in Fig. 3A, a pad layer 7 of a thickness in the range of 50 to 100 Å of, for example, SiO 2 and an etching stop layer 6 of polycrystalline silicon are formed in that order over the surface of a semiconductor substrate 1. The etching stop layer 6 may be coated with a capping layer 8 of SiO 2 or SiN as indicated by an alternate long and two short dashes line to prevent the oxidation of the etching stop layer 6 in the next annealing process using a laser beam. Step (B): As shown in Fig. 3B, grains of polycrystalline silicon forming the etching stop layer 6 are made to grow properly by heating only the etching stop layer 6 by annealing with a laser beam emitted by an excimer laser for the following purpose. When the insulating film 3 including the portions 3a is etched by anisotropic etching as shown in Fig 1E, a small amount of SiO 2 deposited by the bias ECRCVD process remains between the grains of the etching stop layer 6, and the residual SiO 2 must be removed or it is possible that the etching stop layer 6 cannot be removed by etching using KOH. Incidentally, since the etching stop layer 6 as formed by CVD has an irregular surface and grain boundaries in the surface, the portions 3a of the insulating film of SiO 2 are formed in a complex configuration along the grain boundaries and the irregularities in the surface by the bias ECRCVD process. Such a complex insulating film 3 cannot readily be removed in a short time by etching using hydrofluoric acid (HF). If the etching for removing the portions 3a of the insulting film 3 is continued for a long time to remove the same completely, it is possible that the surfaces of the portions of the insulating film formed in the trench regions are etched. Therefore, the grains of the etching stop layer 6 formed by CVD are made to grow by annealing the etching stop player 6 with a laser beam to smooth the irregular surface of the etching stop layer 6 so that fragments of the SiO 2 film remaining in the grain boundaries can readily be removed with hydrofluoric acid. The step (B), namely, the annealing process, distinguishes the bias ECRCVD process in the second embodiment from the bias ECRCVD process illustrated in Figs. 1A to 1H. Step (C): As shown in Fig. 3C, trenches 2 are formed in the surface of the semiconductor substrate 1 by anisotropic etching. Step (D): As shown in Fig. 3D, SiO 2 films 9, i.e. passivation films, are formed over the side surfaces and bottom surfaces of the trenches 2 by thermal oxidation. After the step (D) shown in Fig. 3D, the third process (Fig. 1C) and the following steps of the bias ECRCVD process in the first embodiment are executed for trench isolation. Since the surface of the etching stop layer 6 formed by the semiconductor device manufacturing process in the second embodiment remains smooth after the same has been used, the SiO 2 film can readily be removed, and hence the etching stop layer 6 also can readily be removed. A semiconductor device manufacturing process in a third embodiment according to the present invention will be described hereinafter with reference to Figs. 4A to 4D. Step (A): As shown in Fig. 4A a pad layer 7 and an etching stop layer 6 of polycrystalline silicon are formed in that order over the surface of a semiconductor substrate 1. Naturally, the etching stop layer 6 similarly to the etching stop layer 6 formed in the second embodiment, may be annealed with a laser beam. Trenches 2 are formed in the semiconductor substrate 1, and then the trenches 2 are filled up with an insulating film 3 as shown in Fig. 4A by bias ECRCVD. Step (B): As shown in Fig. 4B, the insulating film 3 including portions 3a formed in active regions is etched by anisotropic etching by a depth substantially equal to the thickness of the etching stop layer 6. Step (C): As shown in Fig. 4C, portions of the insulating film 3 formed in the trenches 2 are masked with a resist film 4. Step (D): As shown in Fig. 4D, the portions 3a of the insulating film formed in the active regions are removed by etching using the masks of the resist film 4. Subsequently, the resist film 4 is removed, the etching stop layer 6 is removed by etching using KOH, and the pad layer 7 is removed by using hydrofluoric acid. In the third embodiment, the step of bias ECRCVD for forming the insulating film 3 is followed by the step (B) for anisotropic etching, and the step of lateral levelling etching by bias ECRCVD is omitted. Thus, spaces necessary for forming the masks of the resist film 4 for etching for removing the portions 3a of the insulating film formed in the active regions are formed only by the step (B) for anisotropic etching. Naturally, the formation of the portions 3a of the insulating film 3 by bias ECRCVD and the anisotropic etching in the step (B) can be carried out successively by the bias ECRCVD apparatus shown in Fig. 2. Fig. 5 shows a modification in the semiconductor device manufacturing process in the third embodiment described with reference to Figs. 4A to 4D. In a step of this modification corresponding to the step (B) of the semiconductor device manufacturing process in the third embodiment, the insulating film 3 including the portions 3a is etched by anisotropic etching by a depth slightly smaller than the thickness of the etching stop layer 6 in order that that the level of the surface of the insulating film 3 is higher than the surface of the semiconductor substrate 1 indicated by an alternate long and two short dashes line in Fig. 5 to prevent the deficiency in the dielectric strength of a layer insulating film to be formed in the following process in portions corresponding to the shoulders of the trenches 2 by filling up the trenches 2 surely with the insulating film 3 As is apparent form the foregoing description, according to the present invention, an etching stop layer resistant to etching actions for etching an insulating film is formed over the surface of a substrate before forming trenches in the substrate, an insulating film is formed on the substrate so as to fill up the trenches, portions of the insulating film formed in active regions are removed by etching with portions of the insulating film filling up the trenches masked, and then the etching stop layer is removed. Accordingly, only small portions of the portions of the insulating film filling up the trenches protruding from the surface of the substrate are removed when the insulating film is etched by anisotropic etching by a depth corresponding to the thickness of the etching stop layer, and hence the surfaces of the portions of the insulating film filling up the trenches are finished flush with the surface of the substrate. Furthermore, annealing the etching stop layer formed of polycrystalline silicon to make the grains of the etching stop layer grow makes the surface of the etching stop layer smooth, so that the insulating film formed over the etching stop layer can completely be removed, and hence the etching stop layer can readily be removed.

Claims: A semiconductor device manufacturing process comprising steps of: forming trenches (2) in the surface of a semiconductor substrate (1); forming an insulating film (3,3a) by bias ECRCVD over the surface of the substrate so as to fill up the trenches; etching the insulating film; masking the portions (3) of the insulating film filling up the trenches; and removing the portions (3a) of the insulating film formed in the regions other than those corresponding to the trenches; characterized in that an etching stop layer (6) resistant to etching actions for etching the insulating film is formed over the surface of the substrate before forming the trenches and the insulating film, that in the step of filling the trench the trench is filled to the upper surface of the etching stop layer, that in the step of etching the insulating film before performing the step of masking the insulating film is anisotropically etched by a thickness substantially equal to or slightly smaller than the thickness of the etching stop layer and that the etching stop layer is removed by etching after removing the portions of the insulating film formed in the regions other than those corresponding to the trenches with the portions of the insulating film filling up the trenches being masked. A semiconductor device manufacturing process according to Claim 1, wherein the etching stop layer is formed of polycrystalline silicon, and the etching stop layer is annealed to make the polycrystalline silicon grains grow. A semiconductor device manufacturing process according to claim 1 or 2, wherein prior to the step of anisotropic etching of the insulating film said insulating film is etched by lateral levelling etching using bias ECRCVD wherein the etching does not attack surfaces parallel to the substrate's surface.

Inventors: GOCHO TETSUO, MORITA YASUSHI, SATO JUNICHI, GOCHO, TETSUO, MORITA, YASUSHI, SATO, JUNICHI, GOCHO, TETSUO, C/O SONY CORPORATION, MORITA, YASUSHI, C/O SONY CORPORATION, SATO, JUNICHI, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L21