Broadband space switch using path sensitizing

Abstract: A broadband space tree-switch matrix establishes a desired switching path by sensitizing only the sequence of logic gates defined by the desired path such that only these sensitized logic gates are operable to undergo switching and thereby permit transmission of only the corresponding input signal. The tree-switch includes a plurality of cascaded stages wherein the first stage consists of dual-input NAND gates (10) each receiving a corresponding input signal (A) at one input (12) and a control signal (14) at another input (11). The remaining stages include a plurality of switching nodes (N20) each having a first NAND gate (20) cascaded to a second NAND gate (25) wherein the second NAND gate has a HIGH steady-state logic signal present at one of its inputs (24). An appropriate combination of control signals are applied to the NAND gates (10) in the first stage to effect a selected switching path. The tree-switch matrix provides low power dissipation due to the path sensitizing and exhibits minimum pulse shrinkage. A second broadband space switch matrix comprises a plurality of NAND gates arranged into a series of cascaded stages to form a tree-switch configuration. The first and second stages include equal numbers of NAND gates corresponding to the number of input signals. Furthermore, the NAND gates in only the first and second stages each have a control input for receiving control signals to establish a selected path. The tree-switch likewise operates to sensitize a particular path in response to the control signals so that only the NAND gates in the selected path are operable to undergo switching.

Description: This invention relates to broadband space switch matrices as defined in the preamble parts of patent claims 1 and 3. There are current efforts in the telecommunications industry to provide broadband video services utilizing high performance technology at low cost. CMOS technology has the potential to provide broadband switching at low cost due to its high speed, high density, and low power dissipation. The performance of broadband switches implemented in CMOS is affected by the specific configuration. In particular, a majority of conventional CMOS space switches encounter size and speed limitations due to stray capacitances in the array crosspoints. A relatively new switch architecture having a tree-switch configuration has been introduced recently that overcomes the aforecited limitations by isolating each crosspoint from the stray capacitances in the array. The configurations for implementing these tree-switches offer improvements in speed, chip area economy, and power dissipation. One such configuration is the 64 X 17 non-blocking crosspoint switch disclosed by Barber et al. in Digest of Technical Papers IEEE International Solid-State Circuits Conference, 17-19 Feb. 1988 pages 116-117. The Barber, et al. switch is constructed as a series of cascaded stages wherein the first stage consists of NAND gates each receiving an input signal and the remaining stages are comprised of switching nodes having a NAND gate cascaded to an inverter. The control is relatively simple in that only the NAND gates in the first stage receive control signals to effect a desired propagation path. Since only the gates in the sensitized path are operable to be switched due to the control signals, low power dissipation is possible. Disadvantageously, an input signal propagating through the Barber et al. switch experiences an undesirable delay due to the cascaded sequence of NAND gate and associated inverter in each stage of the switch. Furthermore, the input signal is susceptible to pulse narrowing since rising and falling inputs could be treated differently by the cascaded sequence of NAND gate and inverter. Regarding pulse-width narrowing, it is impossible in Barber, et al. for the rise and fall delay to stay exactly the same with variations in process, supply voltage, and environmental tolerances. Consequently, an unequal rise and fall delay causes the bit element pulse to shrink or expand thereby reducing operating speed. For example, if every stage produced a pulse shrinkage of 0.2 ns, then the 13 cascaded stages in a 64 X 1 input switch would cause a pulse shrinkage of 13 X 0.2 = 2.6 ns. Thus, an input pulse of 7 ns (corresponding to 150 Mb information rate) would shrink at the output to 4.4 ns. This would prevent one 64 module from driving the next without reclocking the output and expanding the 4.4 ns pulses back to 7 ns. Constant pulse width is difficult to achieve since the gates in successive stages are not identical, resulting in inexact compensation of rise and fall delay. The object underlying the present invention is to provide a switch matrix which is fast with respect to the propagation of the input signals and exact in operation. This object is solved by a switch matrix having the features of claims 1 and 3. Preferred embodiments are subject to various dependent claims. The invention will be more fully understood from the following description of the preferred embodiment with reference to the figures. In the drawings: Figure 1 is a prior art circuit diagram of an 8 X 1 tree-switch matrix; Figure 2 shows a pair of inverter circuits illustrating the effect of cascaded inversion on an input signal having both a rising and falling edge; Figure 3 shows an 8 X 1 tree-switch matrix in accordance with one embodiment of the present invention; and Figure 4 shows an 8 X 1 tree-switch matrix in accordance with a preferred embodiment of the present invention. The prior art tree-switch matrix in Figure 1 is shown as an 8 X 1 switch for exemplary purposes. The four stages comprising the matrix operate in a cascaded tree configuration to accept eight input signals through the NAND gates in stage No. 1 and provide a selected one of the signals in accordance with the control signals applied to the NAND gates in stage No. 1. The bit pattern of control signals as shown in Figure 1 enable signal A entering input 3 to propagate through the switch. Each switching node N2 in the remaining stages after stage No. 1 includes a NAND gate 20 cascaded to an inverter 21. As mentioned hereinbefore, there cannot be exact compensation of rise and fall delay in the switching node N2 due to the different switching delays of NAND gate 20 and inverter 21. When a digital signal propagates thorough a chain of identical inverting logic gates such as those shown in the circuit diagrams of Figure 2, the pulse width of the signal is unaffected even when the rise delay (DR) and the fall delay (DF) are not equal. This is due to the fact that the sums of DF's and DR's are the same for both rising inputs and for falling inputs. In contradistinction, the switching nodes in Fig. 1 cause pulse-width narrowing. In one embodiment of the present invention as shown in Figure 3, the logic circuits of Figure 2 are incorporated into a novel tree-switch configuration having improvements to the prior art switch of Figure 1. The tree-switches of Fig. 1 and Fig. 3 are similar in construction and operation except that where each switching node N2 in Figure 1 includes a cascaded sequence of NAND gate 20 and inverter 21, a representative switching node N20 in Figure 3 includes a first NAND gate 20 cascaded to an identical second NAND gate 25. The advantage of replacing the inverter with a NAND gate is that the cascaded sequence of NAND gates avoids the problem of pulse-width narrowing present in Figure 1. The array in Figure 3 has a plurality of stages configured as a tree matrix wherein stage No. 1 includes NAND gates each connected to an input port and the remaining stages consist of switching nodes which are constructed as described above. In stage No. 1, a representative NAND gate 10 has one input 12 connected to input port 3 and a second input 11 through which control signals such as signal 14 are coupled to gate 10. Each other NAND gate in stage No. 1 likewise has an input dedicated to receiving control signals. Switching node N20, being representative of the other switching nodes in the matrix, has the output of its first gate 20 connected to a first input 23 of the associated second gate 25 wherein output 26 of gate 25 drives a single input of a first NAND gate 30 in the following stage No. 3. As is the case in every switching node, a HIGH steady-state logic signal is present at a control input 24 of second gate 25 for ensuring that gate 25 is always operable to undergo switching. The tree-switch in Fig. 3 operates in response to the control signals applied to the NAND gates in stage No. 1 to establish a desired switching path between one of the input ports and the output of switching node N40 in stage No.4. The selected path is established according to the appropriate set of control signals such that only the NAND gates in the selected path are operable to undergo switching, while the other NAND gates in the matrix are forced into steady-state logic levels. The particular control signals indicated in Figure 3 enable signal A to propagate through the switch while preventing unwanted signals entering the other input ports from proceeding past stage No. 1. Although a shift register is shown in Fig. 3 to indicate how the control signals are presented to the first stage of the switch, other means for applying control signals would be obvious to those skilled in the art. A problem may exist in the tree-switch of Figure 3 when a switching node such as node N20 has its first gate 20 and the associated second gate 25 both part of the same switching node since this might result in the connection from gate 20 to gate 25 being shorter than the connection from gate 25 to gate 30 of switching node N30 in the following stage No. 3, thereby making the effective gates non-identical. This problem is avoided in the switch of Figure 3 by making the connection from gate 20 to gate 25 as long as that from gate 25 to gate 30. This requirement regarding connection lengths is likewise implemented in each other switching node of the tree-switch. Figure 4 is a preferred embodiment of the tree-switch matrix in accordance with the present invention. Even though an 8 X 1 matrix is shown for exemplary purposes, the array can be easily expanded to include any number of inputs. In order to accommodate multiple outputs, such as in an MxN switch, the desired switch array is formed by driving N Mx1 switch arrays in parallel. Further expansion is possible by driving multiple MxN arrays in parallel. The matrix operates to switch a digital signal entering of the input ports labeled 1-8 to the output port connected to the output of NAND gate 500 in stage No. 5. The tree-switch is constructed from a plurality of dual-input NAND gates wherein each NAND gate drives only a single NAND gate in a following stage. In the first two stages, each NAND gate receives external control signals at one of its inputs in order to establish a particular switching path in the matrix, whereas the NAND gates in the remaining stages have both of their inputs connected to different NAND gate outputs from a preceding stage and hence have not externally applied control signals other than the signals which are received from the prior stage. The matrix in Figure 4 establishes a desired connection by sensitizing only the selected switching path. In other words, only the NAND gates in the selected path are operable to undergo switching, thereby permitting only the input signal entering the selected path to propagate through the switch. Any path can be sensitized by forcing the outputs of stage No. 1 and stage No. 2 to the appropriate states by applying a corresponding combination of control signals to the NAND gates in stages No. 1 and No. 2. The chart below shows the control inputs necessary to achieve a particular output from stage No. 2. Input to Stage 1 Gate Control Input to Stage 1 Gate Control Input to Stage 2 Gate Output of Stage 2 Gate A HIGH HIGH A A HIGH OR LOW LOW HIGH A LOW HIGH LOW The appropriate control signals applied to stages No. 1 and No. 2 ensure that for each NAND gate in the selected path, the input line which is not carrying the selected signal is in a HIGH logic state. For example, the darkened switching path in Figure 4 corresponding to the switching path for signal A is established by maintaining a HIGH logic state level on the inputs 11, 21, 31, 41, and 51 of the gates 100, 200, 300, 400, and 500, respectively. When the switch is operating, the control signals indicated place HIGH state logic signals on select inputs 11 and 21 while forcing the outputs of each other NAND gate in the switch into a particular steady-state value such that inputs 31, 41, and 51 are placed in a HIGH state. The information provided in the chart above plus the output conditions of all stages necessary to establish any particular switching path are sufficient to determine the correspondingly appropriate combination of control signals to apply to stages No. 1 and No. 2. Although a shift register is shown in Fig. 4 to indicate how the control signals are presented to the first and second stage of the switch, other means for applying control signals would be obvious to those skilled in the art. As mentioned hereinabove, the unique feature of the tree-switch in Figure 4 is that the only gates that switch and dissipate power are the gates in the sensitized path, namely gates 100, 200, 300, 400, and 500 for the path traversed by signal A. The remaining gates are either in a HIGH or LOW state in accordance with the control signals, thereby dissipating only standby power which is in the microwatt range for NAND gates implemented with CMOS technology. In this particular 8-input case, 5 out of a total of 23 gates are switched. For an array with 64 inputs, only 8 out of 191 gates would switch. In contradistinction, thirteen gates (including inverters) would be switched for a 64-input array configured like the switch in Figure 1. Clearly, the reduction in logic gates which a signal must traverse reduces the delay and power dissipation and thereby makes higher propagation speed possible. What has been shown and described herein are two novel tree-switch matrices as shown in Figures 3 and 4 which have improvements to conventional broadband space switch matrices resembling the array of Figure 1. In one embodiment of the present invention as shown in Figure 3, each switching node N20 has a first NAND gate cascaded to a second NAND gate, whereas in the prior art switch of Figure 1 each switching node N2 has a NAND gate cascaded to an inverter. Advantageously, the cascade of NAND gates provides minimum pulse shrinkage. The preferred embodiment in Figure 4 and the prior art switch in Figure 1 both provide the following advantages: (1) low power dissipation because only the gates in the sensitized path are switched, and (2) high speed because each gate drives only one load. The Figure 4 switch, however, has the following advantages over the Figure 1 switch (1): approximately half the number of stages are in the switching path thereby providing less delay, higher throughput speed, and half the power dissipation, and (2) the total delay for positive and negative input transitions is the same even though the rise and fall delay of the NAND gates is not equal, thereby preventing pulse shrinkage and resulting in higher operational speed. Although the switch in Figure 1 has simplified control, this is not a critical performance parameter when fast control is not a requirement. Furthermore, the number of control lines is not a significant concern since the lines are only a small part of the chip real estate. The architectures according to the present invention are not limited to CMOS implementation, and hence the means for establishing a desired switching path in accordance with the requirements described hereinabove accompanying the embodiments of Figs. 3 and 4 are applicable to other switch configurations which utilize different logic gates that are appropriate for the particular technology. For example, a tree-switch that is constructed from logic gates other than NAND gates might be a more advantageous design, but this embodiment still falls within the scope of the appended claims since a switching path is established in the same manner as set forth in the appended claims and the supporting specification. Because CMOS is the preferred technology for the switch array disclosed herein, the use of NAND gates is determined by the fact that the fastest gate in CMOS is the NAND gate. The invention as defined by the claims provides a broadband space tree-switch matrix having high switching speed and very low power dissipation, and one that is immune to pulse-width narrowing.

Claims: A switch matrix for receiving input digital signals through input ports (1-8) and providing a selected one of said signals as an output signal, comprising: a first selection stage comprising a plurality of logic gates (100) each having a data input connected to a corresponding one of said input ports, a control input, and an output line; a second selection stage cascaded to said first selection stage comprising a like plurality of logic gates (200) each having a data input connected to a single logic gate output line (14) from said first selection stage, a control input, and an output line; a plurality of cascaded stages comprising logic gates (200, 300, 400) arranged into a multiplexing configuration for receiving logic signals and providing said selected signal; each logic gate (300, 400, 500) in said plurality of cascaded stages having an output line, a first input connected to one of said logic gate outputs from a preceding stage, and a second input connected to a different one of said logic gate outputs from said preceding stage; means for establishing a desired switching path in said plurality of cascaded stages by applying an appropriate combination of digital signals to the control inputs of said logic gates (100,200) in said first and second selection stage, whereby only said logic gates in said chosen path are operable to undergo switching, thereby permitting only said selected input signal to propagate through said switch. The matrix as recited in claim 1 wherein: said logic gates (100,200) in said first and second selection stages being NAND gates; and said logic gates (300, 400, 500) in said multiplexing configuration being NAND gates. A switch matrix for receiving input digital signals through input ports (1-8) and providing a selected one of said signals through an output port, comprising: a plurality of cascaded stages wherein said first stage comprises a plurality of logic gates (10) and said remaining stages comprise a plurality of switching nodes (N20,N30,N40) each having a first input connection, a second input connection, an output connection, and a control input connection wherein each output connection drives a single input connection in a following stage; each of said logic gates (10) having a data input connected to a corresponding one of said input ports (1-8), a control input, and an output line wherein each output line drives the input connection of a single switching node in a next stage; said output port being coupled to the output connection of a single switching node (N40) in said last stage; each of said switching nodes (N20,N30,N40) including a first logic gate (20, 30, 40) having a first data input connected to the first input connection of said respective switching node, a second data input connected to the second input connection of said respective switching node, and an output; each of said switching nodes further includes a second logic gate (25) cascaded to said associated first logic gate (20) and having a data input connected to the output of said associated first logic gate, a control input (24) connected to the control input connection of said respective switching node, and an output connected to the output connection of said respective switching node wherein said control input is at a steady-state logic level for permanently enabling said second logic gate; and means for establishing a desired switching path between a selected one of said input ports (1 to 8) receiving said selected input signal and said output port by applying an appropriate combination of control signals to the control input of said first stage logic gates (10); whereby only that first stage logic gate and those switching nodes in said chosen path are operable to undergo switching, thereby allowing only said selected input signal to propagate through said plurality of cascaded stages. The switch matrix as recited in claim 3 wherein: each first stage logic gate being a NAND gate; and each of said first and second logic gates being a NAND gate. The switch matrix as recited in claim 4 further including: control input signal means for providing control signals on the control inputs of said first stage logic gates (10). The switch matrix as recited in claims 3 or 4 wherein: said steady-state logic level being a HIGH state logic level. The switch matrix as recited in claim 5 wherein said control input signal means further includes: a shift register.

Inventors: COOPERMAN MICHAEL, PAIGE ARNOLD, SIEBER RICHARD W, COOPERMAN, MICHAEL, PAIGE, ARNOLD, SIEBER, RICHARD W.
Applicants: GTE LABORATORIES INC, GTE LABORATORIES INCORPORATED
Application year: 1990
Main classification: H04Q3
IPC codes: H03K17, H04Q3