Method of manufacturing a semicondcutor device

Abstract: A method of manufacturing a semiconductor device comprises the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity type on the entire surface of the semiconductor substrate (1); forming a first well (6) through a first thermal diffusion; injecting ions of a second conductivity type through the oxide film into a second well (9) region within the first well; and removing the oxide film formed on the second well region, and thereafter forming a second well having a depth smaller than that of the first well. The semiconductor device manufactured by this method has a first well of a first conductivity type formed on the entire surface of a semiconductor substrate and having higher impurity concentration than that of said semiconductor substrate and a second well of a second conductivity type opposite to said first conductivity type formed within a desired region of said first well. The depth of said first well which is suitable for forming trend capacitors is greater than that of said second well.

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having an alignment mark, and more particularly, to a method of manufacturing a complementary MOS integrated circuit with wells. As integrated circuits are miniaturized more and more, memories such as DRAM memories introduce a vertical structure more often than a conventional planar structure. Capacitors of a trench structure are therefore used in such DRAM memories. Various problems are encountered in the manufacture of memories with trench capacitors. One of the problems is that a well is made deep in order to suppress leakage between trenches of shallow wells. A conventional method of forming a twin well in a complementary CMOS integrated circuit (hereinafter simply called CMOS IC) will be described with reference to Figs. 4A to 4F. A p-type silicon substrate 1 having impurity condition of 1 × 10 15 to 5 × 10 15 cm -3 is subjected to thermal oxidation under an oxygen atmosphere to form a first oxide film 2 having a thickness of 100 nm (1000 angstroms, Fig 4A). A photoresist 3 is deposited on the first oxide film 2 is selectively patterned so as to remain on a region where an n-type well is to be formed in order to form a p-type well. By using this photoresist 3 as a mask, boron ions are injected. In this case, a first damage layer 4 is formed by inactive borons (Fig. 4B). Next, in order to form an alignment mark to be used at the succeeding photoetching process, the oxide film 2 on the p-well region is removed using ammonium fluoride liquid (NH 4 F) and using the photoresist 3 as a mask. Thereafter, the photoresist 3 is removed (Fig. 4C). In order to form the alignment mark for the photoetching process, a p-type well 6 is formed through thermal diffusion of boron ions under oxidation atmosphere. In this case, an oxide film 5 is formed at the same time on the p-type well so that a step or a level difference between oxide films is formed on the surface of the silicon substrate 1, of which the step is used as the alignment mark (Fig. 4D). Next, a photoresist 7 is selectively patterned on the p-type well region. By using the patterned photoresist 7 as a mask, phosphorus ions are injected. In this case, a second damage layer 8 is formed by inactive phosphorus ions (Fig. 4E). Next, after removing the photoresist 7, thermal diffusion is carried our for the purpose of activation of impurities and obtaining a desired diffusion depth, to thereby form an n-type well 9 and thus a twin well (Fig. 4F). Thereafter, a trench capacitor is formed on the semiconductor substrate by using suitable conventional manufacturing methods. In the above conventional technique, thermal diffusion under an oxygen atmosphere for the exposed p-type well region on the silicon substrate 1, for example, at step shown in Fig. 4C, may cause Oxidation-induced Staking Faults (OSF). OSFs occur more often in the p-type boron ion injection region than the n-type phosphorus ion injection region, and increase in proportion with the ion injection dose. In addition, in forming trench capacitors in DRAM memories as described previously, it is necessary to form a deep p-type well region in order to suppress leakage between trenches. In order to form a deep p-type well, it is necessary to increase the boron ion injection dose and form at first a p-type well, so that OSFs are likely to occur. Furthermore, a process of patterning a photoresist is required to be carried out twice in forming a twin well, thereby posing an increased number of manufacturing processes. JP-A-60 105 267 discloses the manufacture of a semiconductor device with increased latch-up withstanding voltage. First phosphorus ions are implanted into the bare surface of a semiconductor substrate and subjected to heat treatment for providing an n type well. Then boron ions are selectively implanted directly into the bare surface of the semiconductor substrate and subjected to heat treatment for providing a shallow p type well formed in the deep n type well. JP-A-60 138 955 discloses the manufacture of a semiconductor device wherein first an oxide film is formed on a semiconductor substrate. Then phosphorus ions are implanted into the semiconductor substrate and boron ions are selectively implanted without removing the oxide film. By a following thermal diffusion a shallower p type well is formed on a deeper n type well. SUMMARY OF THE INVENTION An object of the invention is to provide a method of manufacturing a semiconductor device having a twin well of novel structure and being of high reliability by suppressing occurrence of crystalline defects in the formation of the twin well and by reducing the number of manufacturing steps. Methods according to the present invention are defined in claims 1 and 2. Semiconductor devices manufactured according to the present invention can considerably reduce leakage between trenches of trench capacitors. According to the methods of manufacturing a semiconductor device of this invention crystalline defects in the formation of a twin well can be effectively suppressed. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1E are cross sections illustrating the manufacturing processes for a semiconductor device according to the present invention; Figs. 2A to 2D are cross sections illustrating the manufacturing processes according to a second embodiment of this invention; Fig. 3 shows the profile of impurities in an N-type well according to the present invention; Figs. 4A to 4F are cross sections illustrating the manufacturing processes for a conventional semiconductor device; and Fig. 5 shows the profile of impurities in a conventional N-type well. DESCRIPTION OF THE PREFERRED EMBODIMENT A semiconductor device manufactured by a method according to an embodiment of this invention is shown in Fig. 1E. On a p-type silicon substrate (1 to 5× 10 15 cm -3 impurity concentration), there are formed a first well 6 (p-type well region, 3 × 10 16 cm -3 ) and a second well 9 (n-type well region, 6 × 10 16 cm -3 ). The surface of the substrate is formed with an oxide film 5 (SiO 2 ). The depth of the first well is about 10 microns, and that of the second well is about 5 microns. The depth of the first well is two times that of the second well. A trench capacitor formed in such semiconductor device (e.g., DRAM) has a depth of 3 to 5 microns so that leakage between trenches is considerably small. The method of manufacturing such a semiconductor device of this embodiment will be described with reference to Figs. 1A to 1E. A p-type silicon substrate 1 is subjected to thermal oxidation under oxygen atmosphere to form an oxide film 2 having a thickness of 100 nm (1000 angstroms). Thereafter, boron ions are injected over the entire surface of the p-type silicon substrate 1 through the oxide film 2, under the conditions that the injection energy is 150 keV and the dose is 1.5 × 10 13 cm -2 . In this case, a damage layer 4 is formed by boron ion injection (Fig. 1A). In order to form a first well 6 (p-type well region), thermal diffusion (1190°C, 200 minutes) is carried out under oxygen atmosphere. During this thermal diffusion, the surface of the first damage layer 4 on the silicon substrate 1 is covered with the oxide film 2 so that OSFs will not occur even during the thermal oxidation under oxygen atmosphere (Fig. 1B). Next, a photoresist 3 is selectively patterned to cover the region other than the region where a well is to be formed. By using this photoresist 3 as a mask, phosphorus ions are injected, under the conditions that the injection energy is 150 keV and the injection dose is 2.5 × 10 13 cm -2 . A damage layer 8 is formed by inactive phosphorus (Fig. 1C). Next, in order to form an alignment mark to be used at the succeeding photoetching process, the oxide film 2 on the n-well region is etched using ammonium fluoride liquid (NH 4 F) and using the patterned photoresist 3 as a mask. Thereafter, the photoresist is removed (Fig. 1D). Next, thermal diffusion (1190°C, 480 minutes) is carried out for the purpose of activation of impurities and obtaining a desired diffusion depth, to thereby form a second well 9 (n-type well region) and thus a twin well. In the above manner, a twin well can be formed while suppressing occurrence of OSFs particularly in the region where p-type ions are injected. In the above embodiment of this invention, the first thermal diffusion is carried out for forming a deep p-type well in a DRAM having a trench capacitor. For a DRAM without a trench capacitor (using a stacked capacitor or a planar capacitor), the first thermal diffusion is omitted and the second thermal diffusion is used for both p-type and n-type well diffusion. Specially, after injecting boron ions (Fig 2A), phosphorus ions are selectively injected (Fig. 2B) and thermal diffusion is carried out to thereby realize the structure (Fig. 2D) same as shown in Fig. 1E. Furthermore, a although a twin well is formed in the embodiment, this invention is applicable to forming a triple threefold well by forming the third well after forming the second well 9 in the similar manner described above. By repeating the above steps, a multiple well such as quadruple-well, quintuple-well and so on, may also be formed. Although a p-type silicon substrate is used, the invention is applicable to an n-type silicon substrate. As described in detail, according to the present invention, the profile of impurities in n-type well substantially the same as conventional can be realized by properly setting the first thermal diffusion time, phosphorus ion injection conditions (acceleration energy, dose) for the formation of an n-type well region, and second thermal diffusion time. The profile of impurity concentration in an n-type well according to this invention is shown in Fig. 3, and the profile of impurity concentration in a conventional n-type well is shown in Fig. 5. As understood from Figs. 3 and 5, both the profiles are substantially the same. According to the present invention, in forming the p-type well, thermal diffusion is carried out while covering the surface of the silicon substrate 1 with the oxide film 2 so that the occurrence of OSFs can be suppressed in the order of 0.2/cm 2 and the pn-junction leakage can also be suppressed, allowing the formation of a semiconductor device of high quality and reliability. Furthermore, in forming a twin well, a conventional method requires two processed of patterning a photoresist, whereas the present invention requires one photoresist patterning process thereby reducing the number of processes. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A method of manufacturing a semiconductor device having an alignment mark, comprising: forming an oxide film (2) on the surface of a silicon substrate (1), and thereafter injecting boron ions on the entire surface of said silicon substrate; performing a first heat treatment to form a first p-type well (6) through a first thermal diffusion for activcating said boron ions; forming a mask layer (3) on the oxide film, said mask layer having an aperture corresponding to a second well region where an n-type second well (9) is to be formed within said first p-type well; injecting n-type ions through said oxide film into the second well region; etching off said oxide film formed on said second well region by using said mask layer as a mask to form an alignment mark, thereafter removing said mask layer, thereafter forming the n-type second well having a depth smaller than that of said first p-type well and simultaneously forming an oxide film (5) having the alignment mark which is a level difference of said oxide film through a second thermal diffusion. A method of manufacturing a semiconductor device having an alignment mark, comprising: forming an oxide film (2) on the surface of a silicon substrate (1), and thereafter injecting boron ions on the entire surface of said silicon substrate; forming a mask layer (3) on the oxide film, said mask layer having an aperture corresponding to a predetermined region in the substrate; selectively injecting n-type ions into said predetermined region, said injection depth of said n-type ions being shallower than that of said boron ions; etching off said oxide film formed on the surface in said predetermined region by using said mask layer as a mask and thereafter removing said mask layer; performing a thermal diffusion to form a second n-type well of said n-type ions within a first p-type well (6) of said boron ions and forming an oxide film (5) on said second n-type well which has an alignment mark which is level difference of said oxide film at the boundary between said first p-type well and said second n-type well the depth of said first p-type well being greater than that of said second n-type well.

Inventors: YOSHIDA TOHRU, YOSHIDA, TOHRU
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L27