SLIP SYNC RECORDING IN A SOLID STATE FAST FRAME RECORDER

Abstract: A fast frame recorder (10) records images of an event at a fast frame rate and plays back the images at a slower frame rate to facilitate analysis of the event. Disclosed is a solid state fast frame recorder (10) having a solid state imager (12), which is selectively operable at different frame rates and having a solid state memory (30) for storing a plurality of image frames. The recorder (10) is operable in a slip sync recording mode to capture images of a repetitive event. A trigger (40) is actuated each time the event occurs and the recorder (10) stores an image frame of the event. Both repetitive single image frames and repetitive bursts of consecutive image frames may be stored. The number of image frames in a stored burst and the frame rate of the stored burst may be selectively varied. A variable delay (46) allows storage of image frames which occur at a delayed period after trigger actuation.

Description: SLIP SYNC RECORDING IN A SOLID STATE FAST FRAME RECORDER Technical Field This invention relates in general to a solid state fast frame recorder which records an event at a fast frame rate and plays back the event at a slower frame rate so that the event may be analyzed. More particularly, this invention relates to a solid state fast frame recorder having a solid state imager and a solid state memory for recording image frames of a repetitive event. Background Art Fast frame recorders are. seful for motion analysis of an event. A fast frame recorder records a great number of images during an event at a high or fast image frame rate and reproduces the image frames more slowly at a lower frame rate. Thus, any movement occurring during the event may be analyzed in a step-by-step progression. Applications for a fast frame recorder include, malfunctions in high speed machinery, movements of an athlete, testing of safety equipment, shattering an object, etc. One type of fast frame recorder is disclosed in commonly assigned U.S. Patent 4,496,995, issued January 29, 1985. As disclosed in the latter patent, the fast frame recorder-motion analyzer includes a video camera, a variable speed magnetic tape processor and a video display monitor. The camera is read out in block format so that a plurality of lines of video information that correspond to rows of photosites in the camera solid state imager are simultaneously recorded on magnetic tape in parallel longitudinal tracks. During play back, the magnetic tape is played back at a reduced tape speed. A plurality of parallel video signals reproduced from a plurality of parallel tracks on the tape, are processed into a serial video signal which may be used with standard video monitors. Although a magnetic tape, fast frame recorder is advantageous because of its ability to record a large number of image frames and because of the non-volatility of the image storage, there are limitations to magnetic tape recording. Such a fast frame recorder tends to be costly since, in recording and reproducing a plurality of parallel video signals, separate record and reproduce signal processing circuitry must be provided for each video signal channel. Since the video signals are recorded directly on magnetic tape in an analog format, picture quality is degraded significantly due to induced flutter and other noise, due to reduced bandwidth and increased phase distortion and due to imprecisely recorded pixel signal values. In many applications where the use of a fast frame recorder is appropriate, the event to be recorded may occur at repetitive moments during an extended period of time. Due to the inherent recording length constraints of a magnetic tape fast frame recorder, its ability to capture repetitive events occurring at spaced intervals may require the recording of a large number of image frames which are unnecessary for the analysis of the event. During playback, the unwanted images must be scanned before images relating to the event can be analyzed, resulting in a waste of time, money and recording tape. Moreover, certain events may be incapable of being recorded due to the length of elapsed time between recordable events . Disclosure of Invention According to the present invention, there is provided a fast frame recorder which minimizes the limitations of magnetic tape fast frame recorders. According to an aspect of the present invention, a fast frame recorder includes solid state memory for storing a plurality of image frames produced by a solid state image sensor wherein picture degradation produced by flutter of a magnetic tape fast frame recorder is eliminated and wherein dropouts are minimized to single pixel events. According to another aspect of the present invention, video information representing image frames are recorded in digital format in the solid state memory, thus inherently eliminating media noise and electronic noise associated with tape recording. Moreover, bandwidth limitations and phase distortion produced in magnetic tape recording systems is minimized by digital storage of image frames. The solid state fast frame recorder of the present invention is substantially immune to shock and vibration and to environmental conditions such as temperature and humidity. According to a further aspect of the present invention, a solid state fast frame recorder includes a solid state imager which is selectively operable at different frame rates and includes solid state memory for recording image frames from the imager. The recorder is operable in a slip sync recording mode to capture images of a repetitive event. According to a feature of the invention a single frame or a burst of frames are recorded each time the event occurs in response to a trigger. According to another feature of the invention, a variable delay allows storage of image frames captured a preselected delay period after occurrence of the trigger. Th s, unwanted images are not recorded resulting in savings of time, money and storage space. Brief Description of Drawings In a detailed description of a preferred embodiment of the invention presented below, reference is made to the accompanying drawings in which like numerals refer to like elements. Figure 1 is a block diagram of a preferred embodiment of the solid state fast frame recorder of the present invention. Figure 2 is a functional block schematic diagram of a block readable image sensor. Figures 3A-3F are diagrammatic showings useful in describing the operation of the embodiment of Figure 1. Figure 4 is a functional block schematic diagram of the solid state memory of the embodiment of Figure 1, and Figure 5A—5D are diagrammatic showings useful in describing the operation of the embodiment of Fig. 1. Best Mode for Carrying out the Invention Referring now to Figure 1, there will be described a preferred embodiment of the solid state fast frame recorder of the present invention. As shown in Figure 1, fast frame recorder 10 includes solid state imager 12 which images an event, such as scene 14, by means of a solid state, area imager 16. Imager 12 is controlled by central controller circuit 36 which supplies suitable control signals to imager 12 as a function of operator selectable frame rate and exposure time parameters. Imager 12 may operate, for example, at frame rates of 1 to 1,000 frames per second. Image sensor 16 is preferably a block "readable" area image sensor. The basic concept of a block readout of a solid state area image sensor and the timing and control thereof is disclosed in U.S. Patent Number 4,322,752 in the name of James A. Bixby. Although the referenced patent provides detailed information, a brief description of the concept of block readout may be illustrated with respect to Figure 2. Figure 2 shows a block readable sensor 16 that includes an array of photosites (not individually shown) arranged in rows and columns. For purposes of readout, sensor 16 is schematically shown as being formatted into 12 blocks of 16 photosite rows in each block. Through appropriate control circuitry including block select circuit 18 and column select circuit 20, blocks 1 - 12 of sensor 16 are sequentially read out as parallel rows of photosites to block multiplexer circuit 22. Multiplexer 22 produces an image frame signal which includes sequential blocks of video information wherein each block of video information includes (16) parallel lines of video signals. The parallel lines of video signals from multiplexer 22 are amplified and conditioned in analog processor 24 for preparation to be digitized. These parallel analog signals from analog processor 24 are converted into digital signals in ADC 26 by an Analog to Digital converter on each parallel signal line. Each ADC will output n parallel signal lines where n is equal to it's bit conversion size. Therefore, the number of output lines of ADC 26 will be n times the number of parallel lines of video signals. For example, if the number N of parallel video signals is "16" and the bit conversation number n is "8", the number of signal lines from ADC 26 is "128". The multiplicity of signal lines from ADC 26 are converted to a more manageable number by the. serializer 25. The serializer takes the n parallel lines associated with each ADC and converts the information on them into a bit serial format on one line. Therefore in this example, after serialization, there are the same number of parallel digital signal lines as there are parallel analog signal lines. External data signals from source 42 are temporally associated with an image frame by inserting them in multiplexer 28 as a header or trailer with the image frame signals from ADC 26. These combined signals are then serialized in serializer 25 and stored in an image frame location in solid state image memory 30. Image memory 30 is made up of a number of solid state Random Access Memory devices such as DRAMs or SRAMs . Inherently, to store information in RAM, a location needs to be addressed and then the information writte to their input port. Subsequently, to retrieve the information back the location is re—addressed and then the information is read from the output port. Memory controller 44 is used to give order to the random access capability of RAM. When recording, it generates the address signals to the RAM in a known, fixed sequential format. Most importantly, this format is circular; once Image Memory 30 is full (can not store another image frame in a unique location) the RAM generator repeats the sequence of address signals thereby recording the newest image frame over the oldest. Visual analysis is accomplished when, during playback, the address signals are repeated in the same sequential format, but at a slower rate while Memory 30 is read. Memory 30 may have a storage capacity of any size but should be large enough to store a sufficient number of image frames to capture an event in totality for later analysis. As shown in Fig. 4, memory 30 includes M image frame locations numbered M, to M . As an example, if an image frame plus external data information forms a display matrix of 256 x 256 pixels and each pixel is represented by 8 bits of information, each image frame stored in memory 30 occupies approximately 65 kilobytes of memory. If 1000 image frames were to be stored, then memory 30 must have approximately 65 megabytes of solid state memory storage. Image frames stored in memory 30 are displayed on monitor 32 by converting the digital image frame signal into an analog image frame signal by means of digital to analog converter processor (DAC) 34. Processor 34 extracts external data and displays them in a border around the image frame on display monitor 32. Central controller circuit 36 controls image memory 30 and processor 34 to vary the frame rate of playback on display monitor 32. Key pad 38 has suitable switches and controls to input data into control circuit 36 to control the operation of fast frame recorder 10. Fast frame recorder 10 is operable in recording mode to continuously record (in a circular or FIFO (First In, First Out) format) image frames of an event produced by imager 12. When memory 30 is full, new image frames produced by imager 12 are recorded over the oldest image frames in memory 30. In order to stop recording, either the operator actuates a stop switch or external trigger circuit 40 produces a trigger signal in response to an external event to stop recorder 10 from storing image frames in memory 30. Trigger 40 detects physical phenomena unique to the event to be recorded. The phenomena that sets the trigger can be as simple as a flash, switch closure, sound, temperature or a voltage change. At the time fast frame recorder 10 is triggered to stop, memory 30 will hold the sequence of image frames that depict the event prior to the trigger. A variable delay is provided by delay circuit 46 to stop recording after a trigger signal is produced by external trigger 40. Thus, a variable number of image frames before and after the triggering event may be recorded in memory 30. According to the present invention fast frame recorder 10 is operable in a slip sync recording mode. This mode is used to capture images of a repetitive event. For example, it may be desirable to record images of a rotating member when it is repeatedly at the same rotational position. Trigger 40 is set to provide a trigger signal each time the member is rotated past the triggering position. Recorder 10 is programmed to store in memory 30 one image frame per trigger signal. Playback of the stored image frames, provides a sequence of images which show the dynamics of what was occurring to the rotating member at the selected position. The advantages of the slip sync recording mode over the continuous recording mode are (1) more efficient storage of the information of interest and (2) easier comparison of the sequence of events since numerous unwanted images are not recorded between images of interest. The slip sync recording mode will now be described in greater detail with reference to Figs. 1, 3A-3F, 5A-5D. As shown in Fig. 3A, a member 47 rotates about axis 48 in the direction of arrow 50. Member 46 has structure 52 (e.g., an actuating member) which rotates past trigger position "T", once during every revolution. Thus, structure 52 repetitively rotates past position "T". In the example shown, it is assumed that is is desirable to analyze the dynamics of structure 52 over a period of time as it passes position "T". For example, assume that member 47 is rotating at 480 revolutions per minute and that structure 52 passes position "T" 8 times per second. If the operation of member 47 is recorded continuously at a fast frame rate, the storage capacity of the recorder may be exhausted before completion of the event to be analyzed. Moreover, in such case, innumerable unwanted image frames will be recorded which are irrelevant to analysis of the event, thus causing a waste of time, money and storage capacity. According to the slip sync recording mode of the present invention, the disadvantages of continuous recording are minimized. In the case of Fig. 3A, trigger 40 is set to produce a trigger signal each time that structure 52 of member 47 rotates past trigger position "T". In response to the trigger signal, memory controller 44 controls memory 30 to store a single image frame captured once for every revolution of member 47. As shown in Fig. 5A, for the example given, memory 30 stores frames F, , F Q , , , etc. When the recorded image frames are played back, only those of interest are displayed, greatly facilitating analysis of the dynamics of rotating member 47 and of structure 52 as it passes trigger position "T". According to another feature of the present invention, variable delay 46 allows storage of image frames which occur at a preselected delayed period after actuation of trigger 40. This feature enables analysis of..an event at a different time without having to change the position of the trigger 40. As depicted in Figs. 3B and 5B, application of the trigger signal is delayed one frame period by delay 46, so that image frames of structure 52 are captured and stored in memory 30 at a time which is subsequent to said trigger time and which is delayed by a preselected frame period. As shown in Fig. 3B, structure 52 is rotated about 45" past position "T" and repetitive image frames F 2 , F 1Q , F lg , etc. (Fig. 5B) are stored in memory 30. Figs. 3C, 3D, 3E and 5C illustrate a further feature of the present invention wherein a different time delay is applied to successive trigger signals. As illustrated, delay 46 delays the trigger signal by different delay periods so that structure 52 is captured at different positions during successive rotations of member 47. As shown in Fig. 3C, structure 52 is captured at the trigger position and image frame F^, is stored (Fig. 5C). As shown in Fig. 3D, during the next rotation of member 47, structure 52 has rotated past the trigger position to a 45° position and the trigger signal is delayed one frame period so that image frame F, Q is stored in memory 30. As shown in Fig. 3E, during the next rotation of member 47, structure 52 has rotated past the trigger position to a 90° position and the trigger signal is delayed two frame periods so that image frame F 20 is stored in memory 30. Delay circuit 46 may thus be programmed to delay the application of a trigger signal from trigger 40 by a delay period which is unchanged over time or by a delay period which changes over time according to a preselected algorithm. Referring now to Figs. 3F and 5D, there will be described another feature of the present invention. Recorder 10 is set to record bursts of sequential image frames at repetitive intervals, when triggered. This burst mode enables the user to see a larger window of time around the trigger event. The frame rate in the burst mode can be any of the normal frame rates recorder 10 is capable of recording. Moreover, the burst mode can be combined with a trigger delay. This case is illustrated in Figs. 3F and 5D. As shown in Fig. 3F, structure 52 of member 47 is shown in solid lines at a 45° position from the trigger position "T" and in dashed lines at 90° and 135° positions from the trigger position. Fig. 5D depicts delayed frame bursts F 2 , F 3 , F 4 ; F 1Qi F n , F χ2 ; and F lg , F, Q , F 20 being stored in memory 30. The number of image frames in a frame burst to be stored may be selected by means of a suitable control on keypad 38. Although a preferred embodiment of the present invention has been described above, variations and modifications thereof will be evident to one skilled in the art. Thus, for example, fast frame recorder 10 can record at one frame rate and can play back at the same or a faster or slower frame rate. Moreover, the image frames recorded in memory 30 can be played back on display monitor 32 in the same sequence as they were recorded, or in a random sequence. Both the preselected delay time and number of image frames in a recorded burst may be different from the examples described above. Industrial Applicability This invention has applicability in industrial applications where motion analysis of an event is desired. Such applications include analysis of failure in high speed machinery, testing of safety equipment, analysis of objects shattering, aeronautical applications, etc.

Claims: Claims 1. A solid state fast frame recorder comprising: solid state imager means for capturing an image and for producing an image frame signal corresponding to said captured image, said imager means being selectively operable at different frame rates; solid state memory means for storing a plurality of said image frame signals; trigger means for producing a repetitive trigger signal in response to a repetitive event ; and control means for controlling said memory means to store image frame signals from said imager means in response to said repetitive trigger signal. 2. The recorder of claim 1 wherein said control means includes variable delay means for delaying application of said trigger signal by a preselected delay period, such that said control means controls said memory means to store an image frame signal corresponding to an image which is captured by said imager means during a frame period which is subsequent to said trigger signal by said preselected delay period. 3. The recorder of claim 2 wherein said variable delay means is programmable to effect a delay period which changes over time according to a preselected algorithm. 4. The recorder of claim 1 wherein said control means controls said memory means to store a burst of more than one image frame signal from said imager means in response to said repetitive trigger signal. 5. A solid state fast frame recorder comprising: solid state imager means for capturing an image of an event and for producing an image frame signal corresponding to said captured image, wherein said imager means has a plurality of photosites arranged in an array of rows and columns and wherein said image frame signal is produced by reading out said array of photosites in blocks of parallel rows of photosites, such that each block includes parallel lines of video signals, said imager means being selectively read out at different frame rates; solid state memory means for storing a plurality of image frame signals; trigger means for producing a repetitive trigger signal in response to a repetitive imaged event; and control means for controlling said memory means to store image frame signals from said imager means in response to said repetitive trigger signal. 6. The recorder of claim 5 wherein said control means selectively controls said memory means to store, in response to said trigger signal, one image frame signal or a burst of two or more image frame signals. 7. The recorder of claim 6 wherein said control means includes variable delay means for delaying application of said trigger signal by a preselected delay period, such that said control means controls said memory means to store one image frame signal or a burst of image frame signals which correspond to an image or images captured by said imager means during a frame period or periods which are subsequent to said trigger signal by said preselected delay period. 8. The recorder of claim 5 wherein said control means includes delay means for delaying application of said trigger signal by a preselected delay period, such that said control means controls said memory means to store an image frame signal corresponding to an image of said event which is captured by said imager means during a frame period which is subsequent to said trigger signal by said preselected delay period.

Inventors: BALCH KRIS S, BLESSINGER KURT VAN, BALCH, KRIS, S., BLESSINGER, KURT, VAN
Applicants: EASTMAN KODAK CO, EASTMAN KODAK COMPANY
Application year: 1990
Main classification: H04N5
IPC codes: H04N5