Hybrid GaAs MMIC FET-PIN diode switch

Abstract: A hybrid transfer switch (40) comprises at least a pair of GaAs MMIC FET SPDT switches (12, 14) coupled together by a pair of transmission lines (16, 18). PIN diodes (20, 42) are coupled to the transmission lines (16, 18) and to a DC bias circuitry (B+, 48, B-, 46, 44). The hybrid switch performance closely approximates that of a mechanical/electromechanical transfer switch while providing improved repeatability.

Description: Field of the Invention This invention relates generally to electronic switches. More particularly, this invention relates to a hybrid GaAs MMIC FET-PIN diode transfer switch having high "off" state isolation, low "on" state insertion loss and broad bandwidth. Background of the Invention Transfer switches are well known in the art and are commonly employed in connection with electronic test equipment, such as network analyzers, to route a signal from one path to another, e.g., from a straight through condition to a path which passes through a device under test ("the test path"). The signals that are switched are typically in the RF and microwave range, so special consideration must be given to their design. Generally, the switches must exhibit low insertion loss when on, high isolation when off, good impedance match, and high stability and repeatability (including insertion loss and isolation stability and repeatability), all over a broad bandwidth and over temperature changes. It is desirable that the frequency range over which the switch exhibits these characteristics extends, at the low end, as close to DC as possible, and well into the microwave band at the high end. Mechanical and electromechanical transfer switches have been widely used in the prior art. The model HP 8761 A/B and HP 33311 B/C coaxial switches are exemplary. Also exemplary are electromechanical transfer switches employed in the model HP 85046 A/B, HP 85047A, and HP 8753 test sets. All of the aforementioned equipment is manufactured by Hewlett-Packard Company, Palo Alto, CA (hereinafter "HP"). Mechanical and electromechanical transfer switches exhibit many of the aforementioned characteristics, but are subject to wear and failure and hence are not suitable for use in continuous switching applications. They are also bulky and expensive. Additionally, mechanical and electromechanical transfer switches do not provide repeatable return loss as the switch is cycled - a return loss stability of about 0.005, or minus 46 dB, is common. The switching speed of mechanical and electromechanical transfer switches is also limited. Solid state transfer switches are also known in the art. Generally, known solid state transfer switches fall into two categories: PIN diode switches; and, GaAs MMIC (gallium arsenide monolithic microwave integrated circuit) FET switches. Both overcome the aforementioned failings of mechanical/electromechanical transfer switches, but they suffer from other shortcomings. One example of a PIN diode switch is the model HP 333016C manufactured by HP. Examples of a GaAs MMIC FET switch are the models SW-200 and SW-210 manufactured by Adams Russell Electronics Co., Inc., of Burlington, MA. PIN diode switches are satisfactory for high frequency (e.g., microwave) applications, but they exhibit poor isolation below frequencies of about 45 MHz. Reverse biased series PIN diodes can be used to achieve greater isolation at low frequencies, but this results in another problem: the series diodes must be strongly forward biased in the switch's "on" state, resulting in increased insertion loss and insertion loss drift caused by heating effects. Moreover, series PIN diodes can cause distortion at low frequencies due to self bias in the diodes from RF energy. Additionally, PIN diode switches require large drive currents to achieve the needed isolation. Bias circuits for supplying such large drive currents are difficult to manufacture. Still further, PIN diode switches exhibit poor impedance matching in their "off", or isolation, state because they are effectively shunts in this state. Although matching resistors can improve the match, they result in greater insertion loss. GaAs MMIC FET switches, on the other hand, typically exhibit very good isolation at low frequencies, but poor isolation at high frequencies. They therefore complement the performance of PIN diode switches. Nonetheless, known GaAs MMIC FET switches do not provide the same isolation as mechanical transfer switches, which can be greater than 100 dB to 6 GHz. This is because, although GaAs MMIC FET switches generally have a series-shunt configuration, and use one or more GaAs chips, the series impedance of the shunt devices (FET's) is too high to obtain the required isolation. Also, a large number of GaAs chips is needed to obtain the required isolation, and the insertion loss increases as the number of chips increases. Furthermore, the low frequency power handling capabilities of GaAs MMIC FET switches is limited by the RF self bias of the GaAs FET's on the chips. Finally, known GaAs MMIC FET switches are unacceptably mismatched in both the "on" and "off" states. It is therefore desirable to provide a high speed, solid state transfer switch that: exhibits high "off" state isolation and low "on" state insertion loss; is well matched to the systems with which it is used; and, exhibits stability and repeatability, including insertion loss and isolation stability and repeatability, all across a wide bandwidth that extends from substantially DC to well into the microwave range, and also over temperature changes. It is also desirable that the switch be compact, reliable and inexpensive. Preferably, such a switch would exhibit pin for pin compatibility with a mechanical switch, such as the model HP 33311 B/C, which it is intended to replace. The present invention achieves these goals. Summary of the Invention The switch according to the invention is defined by the features of claim 1 An electronic switch according to one embodiment of the present invention comprises: (a) at least first and second electronic switches each having at least two RF ports, one defining an input port, the other defining an output port; (b) a first transmission line having a characteristic impedance and electrical length ℓ₁ cascaded with the output port of the first switch; (c) a second transmission line having a characteristic impedance and electrical length ℓ₂ cascaded with the input port of the second switch; and, (d) at least one shunt PIN diode cascaded with the first and second transmission lines, and coupled to bias circuitry. The characteristic impedance and electrical lengths ℓ₁, ℓ₂ of the first and second transmission lines are selected to provide input and output impedances within a predefined range of impedances. In a most preferred embodiment of the invention, there is a common port and two switched ports, and the electronic switch comprises first, second and third GaAs MMIC FET switches. Two PIN diodes, defining a first pair of PIN diodes, are connected in parallel with each other, and the anodes of the first pair of PIN diodes are connected to a first switched port of the first GaAs MMIC FET switch. Two additional PIN diodes, defining a second pair of PIN diodes, are connected in parallel with each other, and the anodes of the second pair of PIN diodes are connected to a second switched port of the first GaAs MMIC FET switch. A first switched port of the second GaAs MMIC FET switch is connected to the anodes of the first pair of PIN diodes. A second switched port of the second GaAs MMIC FET switch is grounded through a first resistive load. The anodes of the second pair of PIN diodes are connected to a first switched port of the third GaAs MMIC FET switch. A second switched port of the third GaAs MMIC FET switch is grounded through a second resistive load. Bias circuitry provides a level of DC biasing to the PIN diodes and GaAs MMIC FET switches. In the most preferred embodiment of the present invention, the switches are GaAs MMIC FET SPDT switches. Also in the most preferred embodiment, the PIN diode is biased with a V d matching circuit described more fully below. The most preferred embodiment is pin for pin compatible with the HP 33311 B/C mechanical switch. Brief Description of the Drawings Figure 1 is a schematic diagram of a two-stage hybrid GaAs MMIC FET-PIN diode transfer switch illustrating the principles of the present invention. Figure 2 is a schematic diagram of a single-stage hybrid GaAs MMIC FET-PIN diode transfer switch illustrating the principles of the present invention. Figures 3A, 3B and 3C illustrate an exemplary topology of the two-stage hybrid GaAs MMIC FET-PIN diode transfer switch of Figure 1. Figures 4A and 4B illustrate the topology of the most preferred embodiment of a hybrid, multiple port GaAs MMIC FET-PIN diode switch according to the invention. Figures 5A, 5B and 5C illustrate a preferred implementation of bias circuitry for the switch of Figure 4. Figures 6A and 6B are a schematic diagram of the switch of Figure 4. Figure 7 illustrates a preferred housing for the switch of Figure 4. Figures 8A through 8D are graphs illustrating the performance of the switch of Figure 4. Detailed Description of the Invention Referring now to the drawings wherein like numerals represent like elements, there is shown in Figure 1 a schematic diagram of a hybrid two-stage GaAs MMIC FET-PIN diode switch 10 illustrating the principles of the present invention. The exemplary switch 10 is shown and described herein for switching signals through or around a device under test 52, i.e., for switching the device 52 in and out of a circuit, but it will be appreciated that the switch 10, as well as all embodiments of the invention described herein, may be employed for routing signals from one path to another. The exemplary switch 10 comprises two GaAs MMIC single-pole-double-throw (SPDT) FET switches 12, 14 cascaded with two transmission lines 16, 18. The anode of a shunt PIN diode 20 is connected to the junction of the first and second transmission lines 16, 18, as shown. The transmission lines 16, 18 can alternately be a single line tapped in approximately the center, such that it is center tapped by the anode of PIN diode 20. The two switches 12, 14 preferably each comprise three RF ports. An example of such a switch is the model SW-200 described above. Referring to switch 12, the "RF com ", or "common", port is labeled 26 (labeled 32 for switch 14) and the two switched RF ports, RF₁ and RF₂, are labeled 22 and 24, respectively (labeled 36, 34, respectively, for switch 14). Switch 12 is controlled by applying appropriate control signals to control terminals A and B (labeled 28, 30, respectively). Similarly, switch 14 is controlled by applying appropriate control signals to control terminals A and B (labelled 38, 40, respectively). The GaAs MMIC FET switch comprises a series-shunt FET configuration, as shown in blocks 150 and 150' of Figure 6. In the isolation (high loss) state, the series FET 13 is open, providing low frequency isolation. The shunt FET 15 provides a high frequency shunt which, when rotated in phase by the quarter-wavelength line 16 (Figure 1) connected to the PIN diode 20 (diodes 82, 82' of Figures 6A and 6B), appears as a high source impedance. The diode 20 is forward biased to a low impedance. In the low loss state, forward bias of the FET 13 gate-to-source junction causes gate current to flow. The voltage on resistor 48 (resistors 128, 128' in Figures 6A and 6B) is chosen to both reverse bias the PIN diode 20, and to maintain zero volts DC on the drain line 26, thus drawing the same current that flows into the series FET 13 gate. This prevents V gs from reaching pinch off in the series FETs, even with large RF signals present. Resistors 46, 48, PIN diode 42, and capacitor 44 constitute DC bias circuitry for biasing PIN diode 20. As shown, resistor 48 is coupled to a source of DC voltage, B+, and to the anode of PIN diode 20. The cathode of PIN diode 20 is coupled to a parallel combination of capacitor 44 and matched PIN diode 42, as shown. Note that the cathodes of the two PIN diodes 20, 42 are coupled together. One side of the parallel combination of diode 42 and capacitor 44 is coupled to a source of DC voltage, B-, and the other side is coupled to ground. The operation of the exemplary switch 10 and bias circuitry 42, 44, 46, 48 is described below. When the switches 12, 14 are set to their "off" state at the A and B terminals 28, 38 and 30, 40, respectively, a signal applied at port 26 of switch 12 will be directed to port 24, through transmission lines 16 and 18, into switch 14 at port 36, and out of switch 14 at port 32. Thus, the device 52 is out of the circuit when the switches 12, 14 are in this state. PIN diode 20 is reverse biased and does not add substantially to the insertion loss through the switch. When switches 12, 14 are set to their "on" state, a signal applied at port 26 will be directed to port 22, through the device 52, then into switch 14 at port 34, and out of switch 14 at port 32. PIN diode 20 is forward biased by the DC bias circuitry so that a low impedance path to ground is provided for RF signals, i.e., through PIN diode 20 and capacitor 44. These signals are then partially reflected back to transmission lines 16, 18. The addition of the shunt PIN diode 20 greatly increases the isolation of the signal from port 26 to port 32, the only signal path being through device 52. Thus, the device 52 is in the circuit when the switches 12, 14 are in this state. The electrical length of the transmission lines 16, 18 can be about one quarter of a wavelength at 6.0 GHz, 6.0 GHz being the highest frequency in the desired operating frequency range. These lengths can be adjusted, however, when tuning the circuit to achieve a better-matched circuit in accordance with well known principles. The impedance of the transmission lines 16, 18 is preferably about 55 ohms. This can also be adjusted for improved match to 50 ohms. Many GaAs MMIC FET switches, including the aforementioned SW-200, require that the voltage on the transmission lines 16, 18 be less than approximately 0.4 volts. The PIN diode 20, when forward biased, however, has a voltage drop of approximately 0.7 volts. Use of a V d matching technique to provide DC bias avoids any need for DC blocking capacitors in the transmission lines, while maintaining the bias voltage thereon at the required level. Thus, a preferred DC biasing circuit employs such a technique. The PIN diodes 20 and 42 are matched so that diode 42 conducts the same amount of current as the PIN diode 20 and pulls the voltage at the cathode of the PIN diode 20 below ground level. This holds the voltage on the transmission lines 16, 18 to within a few tenths of a volt of ground. The capacitor 44 provides a low impedance path to ground for RF signals. However, it will be apparent to those skilled in the art that other biasing circuitry can be employed. Referring now to Figure 2, there is illustrated a single stage hybrid GaAs MMIC FET-PIN diode switch 10' illustrating the principles of the present invention. The switch 10' of Figure 2 employs a single GaAs MMIC FET switch 12' cascaded with transmission line 16'. The anode of shunt PIN diode 20' is connected to transmission lines 16' and 18'. The unused port 22' of the switch 12' is preferably terminated with a 50 ohm resistive load 50. The principles of the circuit of Figure 1 are otherwise applicable to the circuit of Figure 2. Figures 3A, 3B and 3C illustrate an exemplary topology for a switch of the type of Figure 1. Figure 3A illustrates physical connections to switch 12, Figure 3B illustrates connections to the PIN diode 20 and DC biasing circuitry, and Figure 3C illustrates connections to switch 14. Like reference numerals designate like components in Figures 1, 3A, 3B and 3C, so the circuit layout is readily apparent. The switches 12, 14 may be bonded to a substrate by conductive epoxy or other well known means, and wire bonding may be employed to make the connections shown. It has been discovered that a top cover over the circuit improves its performance. Figures 4A and 4B, 5A through 5C, and 6A and 6B illustrate the most preferred embodiment of a hybrid GaAs MMIC FET-PIN diode switch according to the invention. Figures 4A and 4B illustrate the topology of the most preferred embodiment, Figures 5A through 5C illustrate a preferred implementation for bias circuitry for the switch of Figures 4A and 4B, and Figures 6A and 6B are a schematic diagram of the switch of Figures 4A and 4B. The principles of the circuits of Figures 1 and 2 are applicable to those of Figures 4A and 4B, 5A through 5C, and 6A and 6B. The solid state switch 60 of Figures 4A and 4B is most preferably a three port device (although the principles of the invention may be employed in a switch having more or less ports), with one port being the common port 62, and the other ports being switched, and labeled 64 and 66 in Figures 4A and 4B. Switch 60 has two states. State 1 provides a low loss path from the common port 62 to port 64 with high isolation between the common port 62 and port 66, and with port 66 presenting a good match. State 2 provides a low loss path between the common port 62 and port 66, and a good match at port 64. Switch 60 is symmetrical about common port 62. Describing the operation of the switch from port 62 to port 64 in both states will completely describe the operation of the switch. In Figure 4, elements labeled with primed numerals on the side of port 66 are identical to the elements on the side of port 64 identified with unprimed numerals. Furthermore, port 64 side elements in state 1 and state 2 have the same operating conditions as port 66 side elements in state 2 and state 1, respectively. Common port 62 is connected to a first GaAs MMIC FET switch 70 through transmission line 68, which is nominally 50 ohms. Transmission line 68 is connected to switch 70 by bond wire 72. GaAs MMIC FET switch 70 is a SPDT switch, with one side connected to the port 64 side through bond wire 74, and the other side connected to the port 66 side through bond wire 74'. GaAs MMIC FET switch 70 is controlled by applying voltages through bond wires 131 and 131'. Bypass capacitors 124 and 124' maintain isolation on bias lines 131, 131'. GaAs MMIC FET switch 70 is connected to a pair of PIN diodes 82 and 84, through a matching structure consisting of transmission lines 76, 78 and 80. The length and impedance (or width) of these transmission lines are preferably optimized by well known methods to achieve the optimal return loss, or impedance match, looking into port 64. These lines compensate for the excess inductance of the bond wires, and excess capacitance of the GaAs MMIC FET switches and PIN diodes. PIN diodes 82, 84 are mounted on a 1500 pF capacitor 146, which in turn is mounted on a ground plane. The cathodes of the diodes are mounted to the capacitor, and the anodes are mounted in shunt with the transmission structures 80 and 88, and gold mesh 86. PIN diodes 82, 84 are also connected to a second GaAs MMIC FET switch 150 through transmission lines 88, 90, 92, which are optimized in the same manner as lines 76, 78, 80 to minimize the return loss at port 64. Line 92 is connected to one of the two SPDT outputs of GaAs MMIC FET switch 150 through bond wire 94. The other output is connected through bond wire 148 to gold pad 140. Gold pad 140 is connected to a 47.5 ohm resistor 142 which is connected to ground through a ribbon bond 144. The common output of GaAs MMIC FET switch 150 is connected through bond wire 98 to transmission line 100. Line 100 is connected to line 102, which is connected to line 104, ribbon 120, and bond wire 112. Bond wire 112 also connects to the anode of PIN diode 110. The cathode of PIN diode 110 connects to the cathode of zener diode 116. The anode of zener diode 116 connects to ground. Line 104 connects to line 106 and to the cathode of PIN diode 108. The anode of PIN diode 108 is connected to the anode of zener diode 118 through bond wire 114. The cathode of zener diode 118 is grounded. In the structure described in the preceding paragraph, none of the diodes (i.e., PIN diodes 108, 110 and zener diodes 116, 118) is used in the normal operation of the switch. They provide protection to the sensitive GaAs MMIC FET switch in the form of a voltage limiter, clamping the voltage to 0.7 volts more than the zener voltage in either polarity, in this case +/- 6.2 volts. Lines 102, 104, 106 and ribbon 120 are optimized for minimum return loss at port 64. Transmission line 122 is connected to the port 64 connector (not shown) to complete the circuit on the port 64 side of the switch. Bias for the GaAs MMIC FET switches 70, 150, 150' is provided on pins 136 and 136' from the bias circuitry illustrated in Figure 5B and described below. These are distributed to the correct bias points through lines 152, 154, 152' and 154'. These lines are isolated from the port 64 side to the port 66 side by the network of series resistors 126, 127, 133, 156, 127', 156', 126', 133' and bypass capacitors 123, 125, 129, 130, 123', 125', 129', 130'. Bias to the PIN diodes is provided at pins 132, 134, 132' and 134'. Pin 132 is connected to capacitor 146 through resistor 138. Pin 134 is connected to the anodes of the PIN diodes 82, 84 through the network of capacitor 158 and resistor 128. State 1 is achieved by biasing GaAs MMIC FET switch 150 so that the side connected to resistor 142 is isolated, with the opposite side being the through-path. PIN diodes 82, 84 are reverse biased to provide very low loss by positively biasing the pin 132 and negatively biasing the pin 134. On the port 66 side, GaAs MMIC FET switch 70 presents a short to line 76', and PIN diodes 82', 84' are forward biased to also provide a short by biasing pin 132' negative and pin 134' positive. GaAs MMIC FET switch 150' presents a short to wire 94', and is isolated (open) to wire 98'. This provides for very high insertion loss between port 66 and port 62 when switch 60 is in state 1. The broadest band loss is achieved when the distances between the GaAs MMIC FET switches 70, 150, 150' and PIN diodes 82, 84, 82', 84' approaches 1/4 wavelength at the highest frequency of operation. Transmission lines 76', 78', 80', 88', 90' and 92' are preferably optimized by well known means to yield maximum insertion loss with the switch in state 1. Port 66 presents a good RF match by connecting GaAs MMIC FET switch 150' through to wire 148', and to the resistor network of pad 140', thin film resistor 142' and ground 144'. Pad 140' and resistor 142' are optimized by well known means to yield minimum return loss at port 66. Finally, the gates of GaAs MMIC FET switches 70, 150, 150' are forward biased by applying voltage at pins 136, 136'. This dramatically increases the power handling capability of switch 60 by limiting RF self bias effects in the GaAs MMIC FET switches. In the internal series FETs of switches present in the low loss state, the gate current is removed though the drain by negatively biasing PIN 134 with a voltage which just draws out the gate current though resistor 128. The voltage is chosen to maintain zero volts on transmission line 88. All the DC feedthroughs are provided with integrated bypass capacitors 159, 160, 161, 159', 160' and 161' (value 10,000 pF) to provide isolation in the bias paths. In the circuit depicted in Figures 4A and 4B, the circuit components have the following values: Capacitors 129, 129', 130, 130', and 158, 158' are most preferably about 80 pF. Capacitors 146, 146' are most preferably about 1500 pF. Resistors 126, 126', 127, 127' and 133, 133' are preferably about 200 ohms; resistors 128, 128' and 156, 156' are preferably about 650 ohms; and resistors 138, 138' are preferably about 450 ohms. Capacitors 123, 123', 124, 124' and 125, 125' are preferably about 80 pF. Referring to Figures 5A through 5C, a preferred implementation of the bias circuitry earlier referenced is illustrated. Pins for effecting connection to the hybrid switch of Figures 4A and 4B are labeled 132, 134, 136, 132', 134' and 136', and these are preferably coupled to pins of like reference numerals on the circuitry of Figures 4A and 4B. As shown, the bias circuitry comprises three sections: a FET gate bias section 210; a PIN bias section 212; and, a power supply section 180. The power supply section 180 supplies the voltages E1-E4 utilized by sections 210 and 212. Section 210 provides bias to the GaAs MMIC FET switches 70, 150, 150'; section 212 provides bias to PIN diodes 82, 84, 82', 84'. The normal operational voltage and current for state 1 for each pin is labeled in Table 1 below, along with preferred values for the circuit components. Different methods can be used to obtain different voltages, but this scheme and these voltages have been employed to allow pin for pin compatibility with the HP 33311 B/C mechanical switch, which the switch of Figure 4 can replace. The compact size of the circuitry and hybrid housing (discussed below) allow this to be a drop-in replacement for the HP 33311 B/C mechanical switch. The only critical circuitry in the bias circuitry is the arrangement of capacitors C7 and C8. These capacitors are needed to provide low frequency bypass of the gate bias lines, and should be within about 1 inch of the DC feedthrough to prevent parasitic inductance from causing a parallel resonant circuit between the DC feedthrough capacitors and capacitors 161 or 161'. Those skilled in the art will appreciate that the bias circuitry of Figures 5A through 5C employ a V d matching technique as earlier described. Resistor R7 is used to prevent large current flow from the +3.7 volt supply to the -9.1 volt supply during switching transients, or if both inputs (E7 and E8) are left open. In operation, one must be ground and the other must be open. In the power supply section 180, device 182 provides regulated drive for the positive voltage requirements, device 184 provides voltage inversion for a negative supply, and device 186 regulates the negative supply. Chips 188, 190, 192, 194, 196, 198, 200 and 202 are switches which route the correct bias to the hybrid bias pins. Figures 6A and 6B illustrate a schematic diagram of the circuit of Figures 4A and 4B. Like reference numerals designate like components in Figures 4 and 6, so the circuit details are readily apparent. The value of the capacitor C in Figures 6A and 6B is 80 pF, and the value of the resistors R is 200 ohms. Referring to Figure 7, therein is depicted a preferred housing for the circuit of Figures 4A and 4B. As discussed above, this housing is designed for drop-in compatibility between the circuit shown in Figure 4 and the HP 33311 B/C mechanical switch. The ports 62, 64, 66 correspond to those of Figure 4, and the circuitry 60, including a cover 61, are shown. Figures 8A through 8D illustrate the performance of the switch of Figures 4A and 4B. Figure 8A illustrates the "on" state return loss as measured at RF port 1. Figure 8B illustrates the "off" state return loss as measured at RF port 1. Figure 8C illustrates the "off" state isolation of the switch. Figure 8D illustrates the "on" state insertion loss of the switch.

Claims: A hybrid GaAs MMIC FET-PIN diode electronic switch comprising: (a) at least one GaAs MMIC FET switch (12;12') having a first RF port (24;22'), a second RF port (22;24') and a control terminal (28 or 30;28' or 30'); (b) a first transmission line (16;16') having a first characteristic impedance and electrical length (l₁) cascaded with said first RF port (24;22') of said GaAs MMIC FET switch (12;12'); (c) a second transmission line (18;18') connected to said first transmission line (16;16'), said second transmission line (18;18') having a second characteristic impedance and electrical length (l₂); and (d) at least a first PIN diode (20;20') connected at the interconnection of said first and second transmission lines (16,18;16',18'), and also coupled to bias circuitry (42,44,46,48;42',44',46',48'); the first and second characteristic impedances and electrical lengths (l₁,l₂) of said first and second transmission lines (16,18;16',18') being selected to provide input and output impedances at said RF ports within a predefined range. The electronic switch according to claim 1, further comprising a second GaAs MMIC FET switch (14) having a third RF port (34); a fourth RF port (36) and a second control terminal (38 or 40), the fourth RF port (36) being connected to the second transmission line (18) such that the second transmission line (18) is connected between the first transmission line (16) and the second GaAs MMIC FET switch (14). The electronic switch according to claim 1 wherein the at least one GaAs MMIC FET switch (12') comprises a first FET having a drain, source, and gate, either the drain or the source of the first FET being connected to the first RF port (22'), and further comprises a second FET having a drain, source, and gate, either the drain or the source of the second FET being connected to the other of the drain and the source of the first FET at a junction, the other of the drain or the source of the second FET being connected to the second RF port (24'), and the gate of the second FET being connected to a third control terminal (28'or 30'), the junction of the first and second FETs being connected to an RF common port (26') to provide an electronic transfer switch. The electronic switch according to claim 1 wherein the at least one GaAs MMIC FET switch (12) comprises a first FET having a drain, source, and gate, either the drain or the source of the first FET being connected to the first RF port (24), and further comprises a second FET having a drain, source, and gate, either the drain or the source of the second FET being connected to the other of the drain and the source of the first FET at a first junction, the other of the drain or the source of the second FET being connected to the second RF port (22), and the gate of the second FET being connected to a fourth control terminal (28 or 30), the junction of the first and second FETs being connected to a first RF common port (26), and further comprising a second GaAs MMIC FET switch (14) which comprises a third FET having a drain, source, and gate, either the drain or the source of the third FET being connected to a third RF port (34) and the gate of the third FET being connected to a fifth control terminal (38 or 40), and further comprises a fourth FET having a drain, source, and gate, either the drain or the source of the fourth FET being connected to the other of the drain and the source of the third FET at a second junction, the other of the drain or the source of the fourth FET being connected to a fourth RF port (36), and the gate of the fourth FET being connected to a sixth control terminal (38 or 40), the second junction being connected to a second RF common port (32), the fourth RF port (36) being connected to the second transmission line (18) such that the second transmission line (18) is connected between the first transmission line (16) and the second GaAs MMIC FET switch (14) to provide an electronic transfer switch. Switch according to any of the preceding claims wherein said bias circuitry employs V d matching, there being a DC voltage level of less than about 0.4 V on said first and second transmission lines (16,18;16'). Switch according to any of the preceding claims wherein l₁ and l₂ are approximately one quarter wavelength at a highest frequency of operation. Switch according to any of the preceding claims wherein the first and second characteristic impedances are approximately 50 ohms. Switch according to any of the preceding claims wherein said bias circuitry comprises: (a) a first resistor (48;48') coupled between a first source of forward DC bias current and a first terminal of said first PIN diode (20;20'); (b) a capacitor (44;44') connected between a second terminal of said first PIN diode (20;20') and ground; (c) a second PIN diode (42;42') having a first terminal coupled to said capacitor (44;44') and to the second terminal of said first PIN diode (20;20'), and a second terminal coupled to ground; and (d) a second resistor (46;46') connected between the first terminal of said second PIN diode (42;42') and a second source of forward DC bias current. Switch according to any of the preceding claims wherein said bias circuitry prevents self bias of the GaAs MMIC FET switches (12,14;12';70,150,150') in a low loss state at high RF drive power.

Inventors: DUNSMORE JOEL P, DUNSMORE, JOEL P.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1990
Main classification: H01P1
IPC codes: H03K17, H01P1