Method for etching tapered vias

Abstract: A multi-step plasma etch method for etching a tapered via having uniform bottom diameter ("CD") and extending through the resist and into the oxide layer of a coated semiconductor substrate, and a coated semiconductor substrate whose coating has been plasma etched to define such a tapered via. The first step of the inventive method is an anisotropic oxide plasma etch operation, preferably employing a plasma consisting primarily of CF₄, which produces a non-­ tapered via having diameter substantially equal to CD and extending through the resist and into the oxide layer. A preferred embodiment of the inventive method includes a second step defining an upper sloping via portion without significantly increasing the diameter of a lower portion of the non-tapered via. This second step is a tapered resist plasma etch operation employing a mixture of oxygen (O₂) and CF₄. The slope of the upper sloping via portion may be controlled by varying the ratio of oxygen to CF₄. In an alternative embodiment, the method produces a "stepped" via having an upper non-tapered portion which extends through the resist and has an opening diameter substantially greater than CD, and a lower non-tapered portion which extends through the oxide and has diameter substantially equal to CD. This embodiment includes an isotropic resist plasma etch operation which enlarges the diameter of the upper via portion extending through the resist, but does not significantly enlarge the lower via portion extending into the oxide layer, followed by an anisotropic oxide plasma etch operation which vertically erodes the lower via portion extending into the oxide layer, and which may also increase the via depth to the desired total depth. Preferably, the plasma used in the isotropic resist plasma etch step consists primarily of O₂ and the plasma used in the subsequent anisotropic oxide plasma etch step consists primarily of CF₄.

Description: The invention is a method for etching a coated semiconductor substrate to define a tapered via, and a coated semiconductor substrate whose coating has been etched to define such a tapered via. More particularly, the invention is a method for defining a tapered via by plasma etching the coating of a coated semiconductor substrate (such as a semiconductor wafer used in an integrated electronic circuit manufacturing process), and a coated semiconductor substrate whose coating has been plasma etched to define such a tapered via. In conventional integrated circuit manufacturing processes, wafers comprising a semiconductor substrate (typically silicon) having a metal pattern deposited thereon are first coated with an oxide layer. A layer known as a "resist" is then coated on the oxide layer. In order to deposit conductive material directly onto a region of the substrate, or onto a region of the metal pattern deposited on the substrate, the oxide and resist layers above such region must be removed. The channel through the oxide and resist layers formed by such removal is known as a "via." Various conventional etching processes have been employed to produce vias. For example, a conventional anisotropic plasma etch process produces vias having sidewalls substantially perpendicular to the plane of the resist and oxide layers ("non-tapered" vias). Such non-tapered vias are produced in this process by exposing a coated wafer to an oxide etch plasma, typically consisting of CHF 3 , C 2 F 6 , or a CHF 3 /C 2 F 6 mixture. Such fluorocarbons are often used as the oxide etch substance since they are "selective" to silicon in the sense that they will not erode silicon over a characteristic time period in which they will erode the resist and oxide layers coated on a silicon substrate. However, poor metal coverage typically results when metal is deposited in the non-tapered vias produced by such conventional processes. This phenomenon can be explained by recognizing that in a typical metal deposition process, the metal coverage is limited by the amount of metal arriving to the inside of the via through the via opening and by the ability of the metal to distribute evenly on the vertical (non-tapered) via sidewalls. It has been found that when a metal film consisting of a TiW/Al/TiW sandwich is sputtered in a conventional manner inside a conventional cylindrical via having 1.0 micron depth and 1.5 micron diameter, the resulting metal coverage on the via sidewalls is often less than twenty percent. One technique that has been tried for improving metal coverage on the sidewalls is to produce a via whose sidewalls have a tapered profile. Such a tapered profile via can be produced by employing a conventional resist erosion plasma etch process. In such a resist etch process, the resist and the oxide layer are simultaneously eroded (with a fixed ratio of vertical etching rate to lateral etching rate) by exposure to a plasma consisting of a mixture of oxygen and an oxide etch substance such as CHF 3 , C 2 F 6 , or a CHF 3 /C 2 F 6 mixture. Given a selected mixture of oxide etch substance and oxygen, the slope of the via sidewalls produced in such process is fixed. Thus, variations in the resist or oxide layer thickness (or in the thickness of metal deposits or other topographic features on the semiconductor substrate) will vary the bottom diameter (also referred to as the critical dimension or "CD") of the vias produced by such process, in a manner that will be readily appreciated with reference to Figure 1. Three vias (identified by numerals 41, 42, and 43) of the type produced by a conventional resist erosion plasma etch process are shown in Figure 1. Fig. 1 is a cross-sectional view of semiconductor substrate 10, which is coated by oxide layer 20 and resist 30. Metal portion 14 is deposited on substrate 10, and metal portion 15 is deposited on topographic feature 16 on substrate 10. Since the plane of Fig. 1 is perpendicular to the planar interface between substrate 10 and oxide layer 20, the cross-section of each of vias 41, 42, and 43 is shown in Fig. 1. Vias 41, 42, and 43 may be frusto-conical or conical, or may be laterally elongated with a longitudinal axis perpendicular to the plane of Fig. 1. Vias 41, 42, and 43 have been produced by exposing layers 20 and 30 above metal portion 14, metal portion 15, and region 17 on the surface of substrate 10, respectively, to the resist etching plasma for the same time period. The critical dimension (or " CD") of via 41 extending to metal portion 14 has magnitude A, which is less than the CD (having magnitude B) of via 42 extending to metal portion 15. Due to an increased thickness of oxide 20 above region 17, via 43 above region 17 does not extend all the way to region 17, so that via 43 would need to be etched for an additional time period (i.e. would need to be "overetched") in order to reach substrate 10. However, if via 43 were overetched for a sufficient time duration so that it reached region 17, the diameter of the portion of such overetched version of via 43 farthest from substrate 10 (the diameter of the "opening" of overetched via 43) would undesirably be far greater than the opening diameter (length C) of via 41 or 42. Improved metal coverage can alternatively be achieved by using conventional wet etch processes or sequential dry and wet etch processes. Two vias of the type produced by this class of process are shown in Figure 2. The liquid chemicals (typically acids) employed in wet etching will erode unimaged portions of the resist (indicated by dashed resist portions 34 and 35) but will not react with imaged portions of the resist such as resist portions 31, 32, and 33. The wet etching process will accordingly undercut an imaged resist portion such as portion 31 if allowed to proceed for a sufficiently long time. More generally, because wet etching is an isotropic etching process (i.e., the vertical and lateral etching rates are substantially the same), wet etching is unsuitable for etching vias having high aspect ratio, where the phrase "aspect ratio" denotes the ratio of via depth (i.e., "vertical" extent in the direction perpendicular to the plane of the semiconductor substrate) to via lateral dimension. It has not been known until the present invention how to produce vias by a plasma etching process in a manner eliminating both the above-described problems of poor metal coverage and CD variation. Nor has it been known until the present invention how to eliminate both the problem of poor metal coverage and the problem of CD variation in a process for etching high aspect ratio vias. The document IBM Technical Disclosure Bulletin Vol. 20 #4 Sept. 1977 discloses a via sidewall tailoring process using two successive etch operations on a substrate having an oxide layer coated by a photoresist layer, an anisotropic oxide plasma etch and a plasma etch with the plasma comprising CF 4 . Two via profiles are disclosed: After a first step, a slightly tapered lower portion partly extending into the oxide, and a strongly tapered upper portion extending through the resist. After a second step, the via profile is tapered from top to bottom. A preferred two-step embodiment of the invention is a method for producing a via having an upper tapered portion and a lower non-tapered portion. The second step of this embodiment is a resist erosion tapered plasma etch operation which erodes both the resist and the oxide layer, but is controlled so as to produce a via having a non-tapered lower portion, and an upper portion with a sloping profile. A plasma including a mixture of oxygen (O 2 ) and CF 4 is employed during the second step to etch the resist and oxide simultaneously. The slope of the via's upper sloping portion may be controlled by varying the ratio of oxygen to CF 4 employed by the second step, and the depth to which the sloping portion extends is determined by the duration of the second step. Figure 1 is a cross-sectional view of a semiconductor wafer in which three vias have been etched using a conventional process. Figure 2 is a cross-sectional view of a semiconductor wafer in which two vias have been etched using another conventional process. Figure 3 is a cross-sectional view of a semiconductor wafer embodying the invention. The phrase "tapered via" is used throughout this disclosure (including in the claims) to denote a via whose bottom diameter (CD) is substantially less than its opening diameter. An example of a tapered via is a frusto-conical via, or a laterally elongated via having longitudinal axis parallel to the wafer surface and having the same sloping profile (i.e., projection in a plane perpendicular to the longitudinal axis) as does a frusto-conical via. Another example is a via having two or more cylindrical portions of different diameter, or an elongated via having longitudinal axis parallel to the wafer surface and having the same profile (i.e., projection in a plane perpendicular to the longitudinal axis) as does a via having two or more cylindrical portions of different diameter. The term "diameter" as used throught this specification and in the appended claims is to be understood to designate, in the case of elongated vias referred to above, the width of the via transverse to the via axis. A preferred two-step embodiment of the inventive method will be described with reference to Figure 3. Via 110 and via 111 are examples of completed vias produced by performing both steps of this preferred embodiment. The first step of this preferred embodiment is an anisotropic oxide plasma etch operation which produces a non-tapered via, such as via 112 of Fig. 3. The first step is preferably timed to have a normal duration sufficient to extend the via to a normal target depth (for example, 60% of the oxide layer thickness). Because the thickness of the resist and oxide layer above the target will typically vary across the wafer, it is desirable to monitor a characteristic of the via (such as the thickness of the material at the via's bottom) during or after performance of the first step. If the monitoring operation indicates that the first step has extended the via to the target, then the second step of this embodiment of the invention is commenced. However, if the monitoring operation indicates that the target (a deeper than normal target) has not been reached, then a control signal is generated for continuing the first step for a longer than normal duration (or a control signal is generated for repeating the first step) to reach the deeper than normal target. Preferably, the plasma employed in the first step consists primarily of CF 4 , rather than known etchants such as CHF 3 , C 2 F 6 , or a CHF 3 /C 2 F 6 mixture. Although a CHF 3 /C 2 F 6 mixture has the advantage that its chemistry is "selective" to silicon (in the sense that it will erode a silicon embodiment of substrate 10 at much less rapid rate than it will erode oxide layer 20), it has been found that use of such a CHF 3 /C 2 F 6 mixture will undesirably generate an oxide/polymer residue that will accumulate in the via during the first step of this embodiment. Such residue will mask the via sidewall during the second step of this inventive embodiment, thus inhibiting the second step. Since CF 4 is less prone to polymerizing reactions than are other etch chemicals, we prefer to employ a plasma consisting primarily of CF 4 in order to eliminate the problem of oxide/polymer residue accumulation. Where the via target is a metal portion (such as portion 101, 102, or 103) deposited on a silicon substrate, rather than the substrate itself, use of CF 4 (which is not "selective" to silicon, in the sense that CF 4 will not erode oxide at a greater rate than it will erode silicon) is not a disadvantage since CF 4 will not erode the metal portion. However, where the via is intended to terminate directly at a silicon substrate, it may be preferable to employ an etching chemical (such as CHF 3 , C 2 F 6 , or a CHF 3 /C 2 F 6 mixture) which is "selective" to silicon, rather than a non-selective chemical such as CF 4 , despite the resulting polymer residue accumulation problem. CF 4 is not only non-selective to silicon, but will in fact erode silicon at a greater rate than it will erode oxide. Thus, CF 4 will seldom be suitable as a via etching chemical where the via target is a silicon substrate. The second step of the preferred embodiment is a resist erosion tapered plasma etch operation. An example of the resist and oxide layer material eroded when such a second step performed on via 112 is the material outlined by dashed line segments 113. In the second step, both the resist and the oxide layer are eroded in a controlled manner so as to produce a via having a sloping upper portion which traverses the resist and a portion of the oxide, and a non-tapered lower portion which traverses a portion of the oxide layer. The plasma used in the second step is a mixture of O 2 and CF 4 . A mixture including CF 4 is used (rather than a mixture including some other fluorocarbon, such as C 2 F 6 ) in order to eliminate the problem of polymer residue accumulation (which residue may inhibit efficient completion of the second step, or may inhibit a subsequent metal coating operation). Preferably, the O 2 :CF 4 ratio should be equal to or greater than one, so that the resulting sloping via is free of polymer residue, regardless of the cleanliness of the etching equipment employed. In one preferred embodiment, a "50%/50%" mixture including equal parts of O 2 and CF 4 is employed. The slope of the upper sloping via portion is controllable by varying the ratio of oxygen to CF 4 employed in the second step. The depth to which the sloping portion extends is controlled by the duration of the second step. The cross-sectional profile of a via produced in this preferred embodiment results in two advantages. First, the profile permits improved metal coverage of the via since more metal particles that are sputtered will arrive at the sloping sidewalls of the upper via portion than would arrive at vertical sidewalls of a non-tapered via such as via 112. In the latter case, the top of the non-tapered via would shadow the vertical sidewalls. The second advantage is that the via's bottom diameter ("CD") will not significantly vary despite: (a) significant wafer nonuniformities as the via is etched across the wafer; and (b) substantial variations in the duration of the first and second steps as the via is etched. The duration of the first step may be varied to ensure that the non-tapered via produced during the first step will reach the desired targets. The targets typically will be metal portions such as portion 101, 102, or 103 in Figure 3, whose depths below the surface of the resist will in general differ (for example, as metal portion 101 is at a different depth than is metal portion 102). This duration variation may be accomplished by continually monitoring a characteristic of the via (for example, the electrical resistance at its bottom) during the first step, and terminating the first step when the measured characteristic attains a predetermined value. Despite variations in the first step duration, the diameter of the non-tapered vias produced in the first step (and thus the bottom diameter of such vias) will be substantially uniform. This embodiment of the invention may accordingly be employed to produce vias having a broad range of aspect ratios, yet having uniform bottom diameter. In the second step, the ratio of O 2 to CF 4 may be selected to achieve a desired "second step erosion region" slope (i.e., ratio of the depth D to the lateral (horizontal) extent H of the "second step erosion region" bounded by dashed lines 113 of Figure 3), and the second step duration may be chosen to achieve a desired sloping region depth D. The second step may thus be controlled so that the bottom diameter of the via may be left substantially unchanged during the second step, over a wide range of possible combinations of depths (D) and slopes (D/H). For example, only a very thin layer of oxide 20 within dashed line 113 of Figure 3 is removed from the vertical sidewalls of the lower portion of via 112 during the second step (so that the via's bottom diameter is not significantly changed during the second step), while a much greater volume of resist 30 is removed from the upper sidewalls of via 112 during the second step. Although via 110's target (metal portion 101) is shallower than is via 111's target (so that the first step of the etching operation producing via 110 likely had a longer duration than that producing via 111), and the depth D 1 of via 110's upper sloping portion is less than the depth D 2 of via 111's upper sloping portion, both via 110 and via 111 have substantially the same bottom diameter CD. Only the via above metal 102 exhibits the profile defined in claim 1. The preferred embodiment described above may be implemented using a conventional oxide etching device (such as a commercially available Model GCA 606 unit), or another conventional plasma etching device having two-step etch capability. Typical parameters employed when implementing this embodiment of the invention using a GCA 606 etching unit are as follows. The first step is performed using CF 4 at a gas flow rate of 100.00 Sccm, with a chamber pressure of 120 Mtorr (1Torr = 133.3Pa); the second step is performed using equal parts of O 2 and CF 4 , each at a gas flow rate of 50.00 Sccm, with a chamber pressure of 150 Mtorr. The first step is divided into a first substep (10 seconds in duration) in which the RF power for the unit is switched off, and a second substep (18 seconds in duration) in which the RF power supplied to the plasma is 430 watts. The second step is divided into a first substep (10 seconds in duration) in which the RF power for the unit is switched off, and a second substep (48 seconds in duration) in which the RF power supplied to the plasma is 360 watts.

Claims: A semiconductor substrate having a coating comDrised of an oxide layer on said substrate and a resist layer on said oxide layer, said coating having a tapered via extending through said resist layer and at least partly through said oxide layer towards a target which is an area of the substrate or a topographical feature on said substrate, said via having a lower Dortion which is non-tapered and an upper sloping profile Dortion, said upper sloping Drofile portion extending through said resist layer and the upper part of said oxide layer. The substrate of claim 1 wherein said target is a metal layer deposited directly on said substrate. A method for forming a semiconductor substrate as defined by claim 1 or claim 2, the method comprising: (a) performing an anisotropic oxide plasma etch operation on the coating to define a non-tapered via which extends through the resist and through the oxide layer, (b) performing a olasma etch oDeration on the coating, the plasma comprising CF 4 , thereby Droviding the upper profile portion, and the duration of said plasma etch being controlled to define the extension of the tapered via portion into the oxide.

Inventors: ABT NORMAN EDWIN, CHEUNG DAVID WINGTON, MCNALLY PETER A, ABT, NORMAN EDWIN, CHEUNG, DAVID WINGTON, MCNALLY, PETER A.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L21