Output amplifying stage with power saving feature

Abstract: A memory (10) uses address transition detection to reduce power consumption of the output amplification stage (14). The output amplification stage (14), which drives an output driver (26), has a series of stages which are disabled except when there is an address transition. When there is an address transition all of the stages (21,22,23,24) are quickly enabled except the last stage (25). The last stage (25) has its output clamped to an invalid state when the other stages (21-24) are first enabled and then is enabled a predetermined time after the other stages (21-24) are enabled. The output of the last stage (25) is sensed by a detector (19). After the last stage (25) has been enabled and is providing valid data, the detector (19) detects that the output of the last stage (25) is valid, and the series of stages (21-24) are all disabled. The output driver (26) latches the data and provides an output. The output stage (14) is thus disabled and thus not wasting power except during the portion of a cycle when there is actual need for amplification. The stage at which valid data is detected, which is the last stage (25), is clamped and disabled at the beginning of the cycle to ensure that the detector does not detect, as being valid, data that is invalid.

Description: This invention relates to memories, and more particularly, to the output amplifying stage of a memory. Background of the Invention One of the critical aspects of a memory is the signal path from a selected memory cell to the output. The memory cell produces a relatively small signal to indicate a particular logic state which comprises one bit of information. This small signal is amplified through a number of stages and finally output as a relatively strong output signal. The strength of the signal primarily relates to voltage level and current drive capability. The signal from the memory cell is generally weak in both voltage and current drive, and thus the need for amplification. This amplification is necessary, but the amplification path is also a critical path in determining the speed with which the memory can operate. Thus, it is desirable to perform the needed amplification as quickly as possible. European patent publication no. EP-A-0235889 discloses a data reading circuit of a static random access memory comprising at least two sense amplifiers and reset circuitry connected between the outputs of the two sense amplifiers to speed up the read out operation of the memory. A multi-stage structure providing improved performance is also disclosed. Generally, there is a speed/power tradeoff. Thus, the speed of amplification for a particular circuit type can be increased but at the cost of using more power. There are two major components of power usage, standby and active. The active power tends to increase as the frequency increases. Thus, at some maximum frequency of operation, the memory is using maximum power for a given power supply voltage. The maximum power that can be consumed is a function of how well heat can be dissipated. If the heat becomes too great, the memory can experience various problems including actually permanently damaging the particular memory device. Thus, it is desirable to save power whenever it is feasible, especially if it can be done without degrading the performance of the memory device. The amplification stage, particularly at high frequency, is a major contributor to the overall power consumed by the device. This is due to a large extent because speed of amplification is so important. There are power saving techniques available but they generally have only nominal affect at the higher frequencies of operation. One such technique is to power down the amplifier stage some predetermined time after an address transition. Another approach has been to power-up the sense amplifier stage with a transition signal initiated by an address transition, detect when the output is valid, and disable the transition signal in response to detecting that the output is valid. This is described in Two Novel Power-Down Circuits on the 1Mb CMOS SRAM," by Masataka Matsui, et al., in the 1988 Symposium On VLSI Circuits, Digest of Technical Papers, Circuits Symposium, Tokyo, IEEE Cat. No. 88 TH 0227-9, pages 55 and 56. This approach continues to offer power-savings benefits even at higher frequencies. There are, however, some problems with this approach. One problem is that the data can give a false reading of validity. The point in the amplification stage at which the validity is detected may have a voltage movement which is sufficient to cause the validity detector to falsely detect that the data is valid. This can happen due to noise in the system which is amplified or to unbalanced bit lines which begin with a differential which is opposite to that which will be eventually established for valid data. If the detector falsely detects that the data is valid, the sense amplifier will be disabled prematurely. Summary of the Invention Accordingly, it is an object of the present invention to provide an improved output amplifying stage for a memory. Another object of the invention is to provide an improved output amplifier of a memory with power saving feature. In accordance with a first aspect of the invention there is provided a memory as claimed in claim 1. In accordance with a second aspect of the invention there is provided a method for enabling and disabling first and second sense amplifiers of a memory as claimed in claim 6. Brief Description of the Drawings The figure is a block diagram of a memory according to a preferred embodiment of the invention. Detailed Description of the Invention Shown in FIG. 1 is a memory 10 comprised generally of an array 11, a row decoder 12, a column decoder 13, an amplification stage 14, an address transition detector (ATD) 16, a control circuit 17, a preset circuit 18, and a detector 19. Amplification stage 14 comprises an amplifier 21, a level shifter 22, an amplifier 23, a level shifter 24, an amplifier 25, and an output driver 26. Array 11 contains a plurality of static random access memory (SRAM) cells located at intersections of word lines and bit line pairs. Row decoder 12 selects a word line in array 11 as determined by a row address. When memory 10 is in a read mode as indicated by signal WE being at a logic high, column decoder 13 couples a selected bit line pair, as determined by a column address, to amplifier. The data contained in the memory cell coupled to the selected word line and to the selected bit line pair is thereby communicated to amplifier 21 in the form of a voltage differential developed on the selected bit line pair. When enabled by an amplifier enable signal AE1 being active, amplifier 21 amplifies the voltage differential input thereto and provides an amplified voltage differential to level shifter 22. When enabled by a level shift enable signal LE1 being active, level shifter 22 shifts the voltage level of the voltage differential provided by amplifier 21 and outputs the level-shifted voltage differential to amplifier 23. When enabled by an amplifier enable signal AE2 being active, amplifier 23 amplifies the level-shifted voltage differential provided by level shifter 22 and provides an amplified voltage differential to level shifter 24. When enabled by amplifier enable signal AE2 being active, level shifter 24 shifts the voltage level of the voltage differential provided by amplifier 23 and outputs the level-shifted voltage differential to amplifier amplifier 25. When enabled by an amplifier enable signal AE3 being active, amplifier 25 amplifies the level-shifted voltage differential provided by level shifter 24 and provides an amplified voltage differential to output driver 26 which provides a data output signal DO representative of the logic state of the selected memory cell. Amplifier stage 14 is active only when memory 10 is in the read mode and is selected to be active. Memory 10 is placed into the read mode under the control of the write enable signal WE and is selected to be active under the control of a chip select signal CS . Memory 10 is in the read mode when write enable signal WE is a logic high and chip select signal CS is a logic low. Control circuit 17 provides signals PE, AE1, AE2, and LE1 in either an active state or an inactive state. If memory 10 is not in the read mode, control circuit 17 provides signals PE, AE1, AE2, and LE1 in the inactive state. In the read mode control circuit 17 provides signals PE, AE1, AE2, and LE1 in the active state in response to transition pulse TP becoming active. Control circuit 17 responds to a data valid signal DV being active by making signals PE, AE1, AE2, and LE1 inactive. Preset Circuit 18 provides signal AE3 in either an active or an inactive state under the control of transition pulse TP and preset enable signal PE. Preset circuit 18 provides signal AE3 in an inactive state in response to signal PE being provided in an inactive state. For the case in which signal PE is active, signal AE3 will be provided in the active state a predetermined time following transition pulse TP becoming active. This predetermined time is conveniently a delay period following transition pulse becoming inactive. In the read mode preset circuit 18 clamps both outputs of amplifier 25 to ground in response to signal TP being active and releases this clamping so that the output of amplifier 25 can become valid in response to transition pulse TP becoming inactive. ATD circuit 16 provides transition pulse TP in an active state for any address transition, either row or column, for about 5 nanoseconds. Detector 19 detects when the outputs of amplifier 25 provide a sufficient voltage differential to be considered valid data. When the output of amplifier 25 is thus detected as valid, detector 19 provides signal DV in an active state, otherwise detector 19 provides signal DV in an inactive state. Prior to an address transition but after a read has been performed, output driver 26 has latched the logic state of the selected memory cell and is providing output signal DO at the logic state representative of the selected memory cell. In this condition, detector 19 has detected that the output of amplifier 25 had been valid and thus provided signal DV in an active state. Pulse TP is inactive so that control circuit 17 is providing signals AE1, AE2, PE, and LE1 in an inactive state. Thus, amplifier 21, level shifter 22, amplifier 23, and level shifter 24 are disabled. Similarly, preset circuit 18 is providing signal AE3 in an inactive state which results in amplifier 25 being disabled. To select a different memory cell, there will be an address transition which is detected by ATD circuit 16. While the memory cell is being selected, ATD circuit 16 generates transition pulse TP. Control circuit 17 responds by activating amplifier 21, level shifter 22, amplifier 23, and level shifter 24 by providing signals AE1, AE2, and LE1 in an active state. Thus, by the time the newly selected cell is providing a voltage differential to amplifier 21, amplifier 21 is enabled and ready to amplify the newly provided voltage differential. Control circuit 17 also responds by providing signal PE in an active state. Preset circuit 18 is thus simultaneously receiving signal PE and pulse TP in their respective active states. Preset circuit 18 responds by maintaining signal AE3 in the inactive state and clamping the outputs of amplifier 25 to an invalid state. With amplifier 25 providing an invalid output, detector 19 provides signal DV in the inactive state. Amplifiers 21 and 23 and level shifters 22 and 24 provide their respective amplification and level shifting functions while pulse TP is active and amplifier 25 is disabled. After a short delay time following the termination of pulse TP, preset circuit 18 outputs signal AE3 in an active state and terminates the clamping of the output of amplifier 25. Thus, by the time level shifter 24 is providing a valid voltage differential derived from the newly selected cell, amplifier 25 is enabled and can provide an amplified voltage differential to output driver 26. When amplifier 25 does provide a voltage differential detected by detector 19, detector 19 responds by providing signal DV in the active state which causes control circuit 17 to provide signals PE, AE1, AE2, and LE1 in the inactive state which in turn disables amplifiers 21 and 23 and level shifters 22 and 24. Preset circuit 18 responds to signal PE being inactive by providing signal AE3 in the inactive state and thus disabling amplifier 25. Output driver 26 includes a latch which latches the output of amplifier 25 in response to the data provided by amplifier 25 being valid. This latching action of output driver 26 is released in response to a new address transition. This latch of output driver 26 is disabled in response to an address transition and enabled in response to the output of amplifier 25 which is thus complementary in operation to the operation of amplifiers 21 and 23 and level shifters 22 and 24 which are active in response to an address transition and disabled in response to the output of amplifier 25 being valid. The control of this latching operation of output driver 26 is not shown in the figure. Amplification stage 14 can thus be viewed as divided into three stages. Amplifiers 21 and 23 and level shifters 22 and 24 can be viewed as a first stage of amplification that begins amplifying in response to an address transition. Amplifier 25 can be viewed as a second stage of amplification which is disabled for a predetermined delay time after the first stage is enabled and then enabled. There is thus a time during which the first stage is enabled and the second stage is disabled. During this time period, the output of the second stage is clamped to an invalid state and released thereafter. Output driver 26 can be viewed as the the third stage which responds to the output of the second stage and provides an output of the memory. Both the first and second amplification stages are disabled in response to the output of the second stage becoming valid. This saves substantial current in the first and second amplification stages. Furthermore, the timing of the enabling of amplifier 25 can be adjusted so there is no delay in the propagation of the differential signal to the output of amplifier 25 but also that the first amplification stage has resolved which direction the differential voltage will be provided. Thus, although there may be an initial imbalance through the first amplification stage, that imbalance will not be provided to the output of amplifier 25 because amplifier 25 is disabled and its output is clamped during the initial time period. By the time the second amplification stage is enabled and its output released, the first amplification stage has fully resolved the output that is to be provided. Thus, amplifier 25 never provides an output that is invalid except when it is clamped to the particular known invalid state. Thus, detector 19 can be made as sensitive as desirable in detecting a differential at the output of amplifier 25 without concern that the output would be providing a false voltage differential. While the invention has been described in a specific embodiment, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than those specifically set out and described above. For example, more or less stages of amplification could be employed. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the scope of the invention.

Claims: A memory (10) having an array of memory cells (11), each memory cell for containing data therein; decoder means (12, 13) for selecting a memory cell in response to an address; a first sense amplifier (21) for receiving data from the selected memory cell and for providing an output representative of the data received from the selected memory cell; a second sense amplifier (25) for receiving the output of the first sense amplifier (21) and for providing an output; and an output driver (26) for receiving the output of the second sense amplifier (25) and for providing an output of the memory; detection means (19) for providing a detection signal in response to the output of the second sense amplifier (25) being valid; first control means (17), coupled to the detection means and the first sense amplifier (21), for enabling the first sense amplifier (21) in response to a transition of the address and disabling the first sense amplifier (21) in response to the detection signal, the memory being characterized by: the first sense amplifier (21) providing an output representative of the data received from the selected memory cell when enabled and for providing an invalid output when disabled; and second control means (18), coupled to the second sense amplifier (25), for disabling the second sense amplifier (25) by causing the second sense amplifier to provide an invalid output for at least a predetermined time when the first sense amplifier (21) is enabled and enabling the second sense amplifier (25) after the predetermined time, whereby the output of the first sense amplifier (21) is representative of the data received from the selected memory cell before the second sense amplifier (25) is enabled. The memory of claim 1, wherein the second control means (18) is further characterized as clamping the output of the second sense amplifier to the invalid state in response to an address transition. The memory of claim 2, wherein the second control means (18) is further characterized as releasing the output of the second sense amplifier (25) when the second sense amplifier (25) is enabled. The memory of claim 1 or 2, wherein the second control means (18) is further characterized as disabling the second sense amplifier (25) in response to the detection signal. The memory of claim 1 wherein the output of the first sense amplifier (21) is coupled to the second sense amplifier (25) via a first level shifter (22), a third sense amplifier (23) and a second level shifter (24). A method for enabling and disabling a and a second sense amplifier in a memory (10) having: an array of memory cells (11), each memory cell for containing data therein; decoder means (12, 13) for selecting a memory cell in response to an address; said first sense amplifier (21) for receiving data from the selected memory cell and for providing an output representative of the data received from the selected memory cell; said second sense amplifier (25) for receiving the output of the first sense amplifier (21) and for providing an output; and an output driver (26) for receiving the output of the second sense amplifier and for providing an output of the memory; said method comprising the steps of: enabling the first sense amplifier (21) in response to a transition of the address; further characterized by: disabling the second sense amplifier (25) by causing the second sense amplifier to provide an invalid output for at least a predetermined time when the first sense amplifier (21) is enabled; enabling the second sense amplifier (25) after the predetermined time; and disabling the first sense amplifier (21) in response to detecting that the output of the second sense amplifier (25) is valid. The method of claim 6 further comprising the step of disabling the second sense amplifier (25) in response to detecting that the output of the second sense amplifier (25) is valid.

Inventors: BADER MARK DOUGLAS, WANG KARL LIN, BADER, MARK DOUGLAS, WANG, KARL LIN
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1990
Main classification: G11C7
IPC codes: G11C11, G11C7