Circuit for limiting the output voltage of a monolithic semiconductor power device which drives a resonant load connected to a power supply

Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

Description: The present invention relates to a circuit for limiting the output voltage of a monolithic semiconductor power device which drives a resonant load connected to a power supply. For driving resonant loads, such as an ignition coil or a transformer, use is made of a semiconductor power device, say, of the darlington type, which is periodically switched on and off by means of a control circuit operated by an appropriate input signal. The power device in substance operates like a switch that is opened or closed by the input signal provided by the control circuit. When the switch is closed, a current flows through the load. When the switch is opened, a positive overvoltage is established between the load and the switch followed by a series of negative voltage peaks which depend on the parasitic capacities of the load and on how the energy, which is stored in the load itself during the switch's closing step, is discharged. Such negative voltage peaks can bring the output voltage of the power device below ground by several volts. In the case wherein the control circuit and the power device are accomplished in the form of an integrated circuit, parasitic components are associated with the active components of the control circuit which, when the above voltage falls below ground, enter into conduction and shortcircuit the active components of the control circuit and jeopardize the operation of the same. US-A-4 471 237 discloses an output protection circuit as defined in the preamble of the independent claim. The object of the present invention is to a new circuit which prevents the output of the power device, that is, its collector connected to the load, from going to a negative voltage with respect to ground thus triggering the parasitic components. According to the invention such object is attained with a circuit for limiting the output voltage of a monolithic semiconductor power device which drives a resonant load connected to a power supply, as defined in the independent claim 1. In this way the negative voltage peaks on the collector of the power device are avoided ensuring the operation of the control circuit. The features of the present invention shall be made more evident by the following detailed description of its embodiments, illustrated as a non-limiting example in the enclosed drawings, wherein: Fig. 1 shows a diagram of the control circuit and of the power device with its corresponding driven load; Fig. 2 shows a partial circuit embodiment of the circuit diagram shown in Fig. 1: Fig. 3 is an example of an embodiment in the form of an integrated circuit of part of the control circuit and of the power device; Fig. 4 is a circuit embodiment of the control circuit and of the power device with an associated limiting circuit; Fig. 5 illustrates the curves of the input signal, of the output voltage and of the collector current of the power device; Fig.s 6 and 7 illustrate examples of circuit embodiments of the circuit according to the invention; Fig. 8 shows the curve of the output voltage in the circuits illustrated in Fig.s 6 and 7; Fig. 9 illustrates a variant of Fig. 3 accomplished in MOS Technology; Fig. 10 illustrates a circuit embodiment according to Fig. 9. With reference to Fig. 1, a load L, in particular a transformer, connected to a node at a voltage Vb of a battery is driven by a power device, in particular a switch A, which is opened and closed by an input signal Vi provided by a control circuit C supplied with a voltage Vs. With Vc there is indicated the output voltage of the power device. With reference to Fig. 2, the power device A is accomplished in a circuit form such as a darlington T5, T6. Moreover, control circuit C comprises, among other things, a transistor T4 in series with a resistor R. With reference to Fig. 3, the accomplishment in a monolithic integrated form of the circuit illustrated in Fig. 2 provides for a substrate with n+ doping, region 1, connected to the voltage Vc, inside which there are obtained transistors T5, T6 of the power darlington A, both of the npn type, whose collectors, bases, emitters occupy regions 2, 5, 6 and 2, 3, 4, respectively. Inside region 1 there is also obtained the control device C of the power device A, in particular the transistor T4 of the npn type, whose base, collector, emitter occupy regions 7, 8, 9 and whose collector, region 8, is connected to resistance R, region 10 of the p type, which in turn is connected to the power supply Vs. The monolithic accomplishment illustrated above determines the presence of a first parasitic transistor T1, whose base is accomplished in a region 11 of the pwell type, while the collector is accomplished in a region 12 of the n+ type and is connected to region 8 which constitutes the collector of transistor T4, and the emitter is accomplished in region 2 of the n- type. There are also present a second and a third parasitic transistor T2, T3. The base of transistor T2 is connected to the collector of transistor T3, obtained in a region 13 of the n+ type, the emitter is accomplished in the region 10 of the p type, the collector is connected to the base of transistor T3, region 11 of the pwell type, lastly the emitter of transistor T3 is accomplished inside region 2 of the n- type. The circuit connection of parasitic transistors T1, T2, T3 is indicated in Fig. 2. With reference to Fig. 4, which represents the schematic diagram of a prior art circuit, the power device A, accomplished by means of a pair of transistors T5, T6 in a darlington configuration, is driven on the base by control circuit C, kept on or off by means of input signal Vi. The emitter of the power device is grounded, the collector is connected to a load L, in particular a coil or a transformer. Between the collector and the base of the power device there is a voltage limiter, in particular a zener Z1. To the collector of the power device there is associated a circuit L1 limiting the output voltage corresponding to it. Said limiting circuit L1 comprises a comparator B, which at its non-inverting input has a voltage Vrif, while its inverting input is supplied with the voltage Vc. A diode D1 is placed between the output U of comparator B and the voltage node Vc. With reference to Fig,s 4, 5, in the absence of the limiting device according to the invention, that is, in the configuration of Fig. 2, the circuit operates as follows: Assume that the main device consisting of the control device C and of the power device T5, T6 drives a load L, in the specific case the primary of a transformer. Initially Vi = 0, T5, T6 is off and Vc = Vb. When a positive voltage step of an amplitude such as to cause the conduction of T5 and T6 is applied to the node at voltage Vi, at the voltage node Vc there shall be exhibited a voltage peak which is negative with respect to ground and subsequently Vc goes to a voltage equal to the saturation voltage Vcesat of T5, T6, while a linearly rising current flows through winding L. When a quenching signal is sent to the node at voltage Vi, darlington T5, T6 interdicts itself and there shall be an overvoltage on Vc whose maximum value is controlled by zener Z1. Subsequently there is the discharge on the secondary of the transformer and Vc falls quickly below ground with some negative peaks, before positioning itself at Vb. The addition of the limiting device L1 (Fig. 4) allows the avoidance of the negative voltage peaks Vc at instants tl and t2. In particular comparator B is switched on when Vc is less than or equal to Vrif and supplies to the node at a voltage Vc the current necessary to avoid the undesired voltage peaks. There is illustrated in Fig. 6 a first circuit embodiment of the limiting circuit according to the invention. According to such embodiment, provision is made for the introduction of a series of three diodes D3, D4, D5 between ground and a node at a voltage V1, which is in turn connected to the power supply Vs through a resistance R2. The node V1, which constitutes the input at the reference voltage of comparator B, is then connected to the base of a transistor T7, whose emitter is connected to a diode D2 and whose collector is connected to a resistor R3 in turn connected to the power supply Vs. An intermediate node V2, between the collector of transistor T7 and resistor R3, is connected to the base of a transistor T13, whose emitter is connected to the power supply Vs and whose collector is connected to the base of a transistor T9. The collector of transistor T9 is connected to the power supply Vs and the emitter to diode D1; in addition, between the base and the emitter of transistor T9 there is a resistor R6. It can be deduced from the circuit diagram that V1 = 3Vbe, where Vbe is the voltage of each diode D3, D4, D5. Since V1 - Vc = Vbe(T7) + Vbe(D2), as soon as Vc tends to fall below Vbe T7 is switched on which switches on T13 and T9; the latter causes a current to flow through D1 which is not limited on Vc thus preventing the collector of darlington T5, T6 from falling below Vbe with respect to ground. This circuit is conservative since to avoid switching on the parasitic components T1, T2, T3 of Fig. 3 it is sufficient to prevent Vc from falling below ground by a voltage whose absolute value is greater than or equal to Vbe. Thus voltage V1 could be constituted by 2Vbe. In this case the circuit according to the invention becomes active when Vc is less than or equal to 0. However, in the circuit of Fig 6 it is preferred to have V1 = 3Vbe since, apart from the negative voltage peaks, Vc is always greater than or equal to Vcesat(T5, T6) = Vbe(T6) + Vcesat(T5), greater than Vbe, and thus the circuit is only active when Vc is less than or equal to Vbe. With reference to Fig. 7, in the circuit of Fig. 6 it is possible to replace the diode chains D3, D4, D5, with the series of a resistance R7 connected to ground, at one of its extremities, and at the other extremity connected to a resistance R12 which is connected to the node at a voltage V1, respectively. To the intermediate node between resistances R7, R12 there is connected the base of a transistor T11, whose emitter is connected to ground and whose collector is connected to the node V1. With this circuit solution there is obtained a variation of V1 that is continuous and not in multiples of Vbe, in particular V1 = Vbe(T11) x (R12 + R7)/R7 = KVbe. If this modification is introduced into the circuit of Fig. 6, V1 must be greater than Vbe and less than 2Vbe + Vsat(T5, T6) and thus the circuit according to the invention becomes consequently active when Vc is greater than -Vbe and less than Vsat(T5, T6). In the circuit of Fig. 6 the limitation of Vc thus occurs exclusively at two discrete values equal to Vbe and 0, while with the modification introduced in Fig. 7 Vc can be limited in a continuous manner, varying the values of R7 and R12, in an interval of values ranging from Vcesat(T5, T6) to - Vbe, excluding the extremes; this is shown in the graph of Fig. 8, where the thicker line refers to the preferred solution and the dotted lines indicate the upper and lower limits of such interval of values. The circuits according to the invention previously described may be accomplished with components of the MOS type or of the mixed type (bipolar + MOS) and they can be integrated in the structure shown in Fig. 9. In this case the power darlington T5, T6 is replaced by a power MOS transistor, indicated in Fig. 9 with 30 whose gate is accomplished at polysilicon strips 43 while the source is accomplished in regions 42 of the type n 1 and the drain is accomplished in the substrate, region 2 of type n; the components of the control circuit are also of the MOS type, such as, say, M4, or they may be of the mixed type. The same reference numbers of Fig. 3 are used in Fig. 9 to indicate corresponding parts. There is represented in Fig. 10 a circuit embodiment of the mixed type of the circuit illustrated in Fig. 6 with the variant of the voltage divider illustrated in Fig. 7. The bipolar transistors T13, T7 have been replaced here with MOS transistors M8, M7, an MOS transistor M31 has been introduced whose drain is connected to node V1, while the source is connected to the collector of transistor T11 and the gate is connected to the drain and thus to node V1; in addition, the power darlington T5, T6 has been replaced by the MOS power transistor M30.

Claims: Output voltage limiting circuit for a monolithic semiconductor power device (T5, T6; M30) having an input terminal receiving an input signal (Vi) and having an output terminal for controlling a resonant load (L), said output voltage limiting circuit comprising a comparator (B) for comparing an output voltage (Vc) at said output terminal of the power device (T5, T6; M30) with a predetermined reference voltage and for supplying current to the load (L) when said output voltage (Vc) becomes lower than said reference voltage so as to maintain said output voltage (Vc) substantially equal to said reference voltage, and first diode means (D2) interposed between said output terminal and the comparator (B) to protect the comparator (B) against output overvoltages of the power device (T5, T6; M30), said comparator (B) comprising a first transistor (T7, M7) having a first terminal connected to a voltage supply (Vs), a second terminal connected to said output terminal of the power device (T5, T6) through said first diode means (D2) and a control terminal connected to a source (G1, R2, D3-D5, R12, R7, T11, M31) of said reference voltage, characterized in that said comparator (B) further comprises second transistor (T9) having a first terminal connected to said voltage supply (Vs) and a second terminal connected to said output terminal of the power device (T5, T6) through second diode means (D1), and a third transistor (T13, M8) having a first terminal connected to said voltage supply (Vs), a second terminal connected to a control terminal of the second transistor (T9) and a control terminal connected to the first terminal of the first transistor (T7) to cause switching on of the second transistor (T9) simultaneously with switching on of the first transistor (T7) as caused by lowering of the output voltage (Vc) of the power device (T5, T6; M30) under said reference voltage. Circuit according to claim 1, characterized in that said first, second and third transistors (T7, T9, T13; M7, T9, M8) are bipolar transistors (T7, T9, T13). Circuit according to claim 2, characterized in that said source (G1, R2, D3-D5, R12, R7, T11, M31) of reference voltage consists of a voltage divider (R2, D3-D5) having an intermediate node (V1) connected to the control terminal of said first transistor (T7), said voltage divider (R2, D3-D5) including a plurality of serially connected diodes (D3-D5) interposed between said intermediate node (V1) and ground. Circuit according to claim 2, characterized in that said source (G1, R2, D3-D5, R12, R7, T11, M31) of reference voltage consists of a voltage divider (G1, R2, R12, R7, T11) having an intermediate node (V1) connected to the control terminal of said first transistor (T7), said voltage divider (G1, R2, R12, R7, T11) including a bipolar transistor (T11) interposed between said intermediate node (V1) and ground and having a control terminal resistively connected to said intermediate node (V1) and ground. Circuit according to claim 1, characterized in that said first and third transistors (T7, T13; M7, M8) are MOS transistors (M7, M8) and said second transistor (T9) is a bipolar transistor. Circuit according to claim 5, characterized in that said source (G1, R2, D3-D5, R7, R12, T11, M31) of reference voltage consists of a voltage divider (G1, R2, R7, R12, T11, M31) having an intermediate node (V1) connected to the control terminal of said first transistor (M7), said voltage divider (G1, R2, R7, R12, T11, M31) including a series of an additional MOS transistor (M31) and of a bipolar transistor (T11) having a control terminal resistively connected to said additional MOS transistor (M31) and ground.

Inventors: PALARA SERGIO, PAPARO MARIO, PELLICANO' ROBERTO, PALARA, SERGIO, PAPARO, MARIO, PELLICANO', ROBERTO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H03K17
IPC codes: H03K17, H01F7, G05F1, G05F3