Delay circuit having stable delay time

Abstract: A delay circuit comprises a first inverter including a first MOSFET of a P-channel type (P₁) having a gate connected to an input terminal (IN), a drain connected to a first node (1) and a source connected to a high voltage supply line (V CC ); and a second MOSFET (N₃) of an N-channel type having a gate connected to the input terminal, a drain connected through a first resistor (R₁) to the first node and a source connected to ground. There is provided a current mirror circuit having an input side current path (i₁) connected in parallel to the first MOSFET, and an output side current path (i₂) connected between the first voltage supply line and a second node (2). A capacitor (C) is connected between the second node and the ground, and there is provided a third MOSFET (N₅) of the N-channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal, a drain connected to the second node and a source connected to the second voltage supply line (ground). A second inverter includes a fourth MOSFET (P₆) of the P-channel type having a gate connected to the second node, a drain connected to an output terminal (OUT) and a source connected to the high voltage supply line, and a fifth MOSFET (N₇) of the N-channel type having a gate connected to the input terminal, a drain connected through a second resistor (R₂) to the output terminal and a source connected to the ground.

Description: Background of the Invention Field of the invention The present invention relates to a delay circuit, and more specifically to a delay circuit which is suitable for installation in a MOS (metal oxide semiconductor) integrated circuit. Description of related art In the prior art, one typical delay circuit implemented in a MOS integrated circuit is composed of a first CMOS (complementary MOS) inverter having an input connected to an input terminal, a second CMOS inverter having an output connected to an output terminal and an integration circuit formed of a resistor and a capacitor and connected between an output of the first CMOS inverter and an input of the second CMOS inverter. In this delay circuit, a delay time is determined by a resistance and a capacitance of the integration circuit and a logical threshold of the second CMOS inverter. The logical threshold of the second CMOS inverter is greatly dependent upon a transconductance g m and a threshold V T of each of a P-channel transistor and an N-channel transistor which form the second CMOS inverter. However, the transconductance g m and the threshold V T cannot be precisely controlled in an integrated circuit manufacturing process. Therefore, it has been difficult to obtain a desired delay time in the conventional MOS delay circuit. In other words, the delay time will vary dependently upon variation of characteristics of MOS transistors. In EP-0 315 385 there is described a delay circuit which uses a constant current source and a current mirror to control the current charging a capacitor in such a way that the time delay produced by the circuit is independent of manufacturing variations of transconductance characteristics of the MOSFETs used, and therefore threshold characteristics of the circuit. In this way manufacturing tolerances of the MOSFET devices have no net effect on the delay obtained. In IBM Technical Disclosure Bulletin Vol. 27, No. 12, May 1985, p. 7134 - 7135 there is described a delay circuit comprising only two CMOS inverters that is able to generate different delays for the rising and the falling pulse slopes and that can influence the gradients of the output pulse. In The Art of Electronics, P. Horowitz, W. Hill, Cambridge University Press, Cambridge 1980, p. 71 - 72, there are described current mirror circuits. Summary of the Invention Accordingly, it is an object of the present invention to provide a delay circuit which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a delay circuit which is suitable for installation in a MOS integrated circuit and which can obtain a precisely controlled stable delay time which will not vary even if characteristics of MOS transistors forming the delay circuit vary. The above and other objects of the present invention are achieved in accordance with the present invention. The invention is described in the appended claims. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of a typical conventional delay circuit composed of CMOS circuits; Figure 2 is a waveform diagram illustrating the characteristics of the conventional delay circuit shown in Figure 1; Figure 3 is a graph illustrating an input-output characteristics of an inverter; Figure 4 is a circuit diagram of a first embodiment of the delay circuit in accordance with the present invention; Figure 5 is a waveform diagram illustrating the characteristics of the delay circuit shown in Figure 4; and Figure 6 is a circuit diagram of a second embodiment of the delay circuit in accordance with the present invention. Description of the Preferred embodiments Referring to Figure 1, there is shown a circuit diagram of a typical conventional delay circuit composed of CMOS circuits. The shown delay circuit includes an input terminal IN and an output terminal OUT. The delay circuit also includes a first CMOS inverter INV₁₁ including a P-channel MOSFET P₁₁ and an N-channel MOSFET N₁₂ connected in series between a first voltage supply line Vcc and ground, namely, a second voltage supply line GND. An input of the first CMOS inverter INV₁₁ is connected to the input terminal IN and an output of the first CMOS inverter INV₁₁ is connected to a first node 11. A resistor R₁₁ is connected between the first node 11 and a second node 12, and a capacitor C is connected between the second node 12 and the second voltage supply line GND. The delay circuit further includes a second CMOS inverter INV₁₂ including a P-channel MOSFET P₁₃ and an N-channel MOSFET N₁₄ connected in series between the first voltage supply line Vcc and the second voltage supply line GND. An input of the second CMOS inverter INV₁₂ is connected to the second node 12 and an output of the second CMOS inverter INV₁₂ is connected to the output terminal OUT. Operation of the circuit shown in Figure 1 will be described with reference to Figure 2 which is a waveform diagram illustrating the characteristics of the conventional delay circuit shown in Figure 1. Assume that the circuit is in an initialized condition that a low level signal is applied to the input terminal IN and the first and second nodes 11 and 12 are at a high level, respectively, so that a low level signal is outputted from the output terminal OUT. Under this condition, if a high level signal is applied to the input terminal IN, a potential V₁₁ of the first node 11 is brought to a low level (the level of the second voltage supply line GND) at the same time as the high level signal is applied to the input terminal IN. Thereafter, a potential V₁₂ of the second node 12 will gradually decrease in accordance with the following equation (1): V₁₂ = Vcc · e -t/C·R 11 When the potential V₁₂ becomes equal to a logical threshold V Loth of the second inverter INV₁₂, the output of the second inverter INV₁₂ is inverted so that the high level signal output is outputted from the output terminal OUT, with the result that the delay time t D is obtained. The delay time t D obtained in the delay circuit of Figure 1 is expressed in the following equation (2): t D = C · R₁₁ · ln (Vcc / V Loth ) As seen from the equation (2), the delay time obtained in the delay circuit of Figure 1 is dependent upon the value of the capacitor C and the value of the resistor R₁₁ and the logical threshold V Loth of the second inverter INV₁₂. The logical threshold V Loth of the second inverter INV₁₂ varies when a transconductance g m and a threshold Vth of each of MOSFETs forming the second inverter INV₁₂ vary. For example, assume that a logical threshold is set to V thb as shown in Figure 3. However, the transconductance g m and the threshold Vth will inevitably vary due to variation or dispersion in fabrication. Therefore, if the transconductance gm of the MOSFET P₁₃ becomes small or if the threshold V T of the MOSFET P₁₃ becomes high, or if the transconductance gm of the MOSFET N₁₄ becomes large or if the threshold V T of the MOSFET N₁₄ becomes low, the input/output characteristics of the inverter becomes as shown in a curve "a" in Figure 3, and therefore, the logical threshold will be lowered to V tha . On the other hand, if the transconductance gm of the MOSFET P₁₃ becomes large or if the threshold V T of the MOSFET P₁₃ becomes low, or if the transconductance gm of the MOSFET N₁₄ becomes small or if the threshold V T of the MOSFET N₁₄ becomes high, the input/output characteristics of the inverter becomes as shown in a curve "c" in FIgure 3, and therefore, the logical threshold will be raised to V thc . Accordingly, if the transconductance g m and the threshold Vth of each of MOSFETs forming the second inverter INV₁₂ vary, the logical threshold V Loth of the second inverter INV₁₂ will vary, and therefore, the delay time t D will also vary. Referring to Figure 4, there is shown a circuit diagram of a first embodiment of the delay circuit in accordance with the present invention. The shown delay circuit includes an input terminal IN and an output terminal OUT. The delay circuit also includes a first MOSFET P₁ of the P-channel type having a gate connected to the input terminal IN, a drain connected to a first node 1 and a source connected to a first voltage supply line Vcc; a second MOSFET P₂ of the P-channel type having a gate and a drain connected commonly to the first node 1 and a source connected to the first voltage supply line Vcc; a third MOSFET N₃ of the N-channel type having a gate connected to the input terminal IN, a drain connected through a resistor R₁ to the first node 1 and a source connected to a second voltage supply line GND; a fourth MOSFET P₄ of the P-channel type having a gate connected to the first node 1, a drain connected to a second node 2 and a source connected to the first voltage supply line Vcc; a capacitor C connected between the second node 2 and the second voltage supply line GND; a fifth MOSFET N₅ of the N-channel type having a gate connected through an inverter INV to the input terminal IN, a drain connected to the second node 2 and a source connected to the second voltage supply line GND; a sixth MOSFET P₆ of the P-channel type having a gate connected to the second node 2, a drain connected to the output terminal OUT and a source connected to the first voltage supply line Vcc; and a seventh MOSFET N₇ of the N-channel type having a gate connected to the input terminal IN, a drain connected through a resistor R₂ to the output terminal OUT and a source connected to a second voltage supply line GND. Now, operation of the circuit shown in Figure 4 will be described with reference to Figure 5 which is a waveform diagram illustrating the characteristics of the delay circuit shown in Figure 4. Assume that the circuit is in an initialized condition that a low level signal is applied to the input terminal IN, so that the transistors P₁, N₅ and P₆ are on and the transistors P₂, N₃, P₄ and N₇ are off, and therefore, a potential V₁ of the first node 1 is at a high level (Vcc) and and a potential V₂ of the second node 2 is at a low level (GND), with the result that a high level signal is outputted from the output terminal OUT. Under this condition, if a high level signal is applied to the input terminal IN, the transistor N₃ and N₇ are turned on, and the transistors P₁ and N₅ are turned off. Here, if a transconductance g mN3 of the transistor N₃ is set to be greater than a factor 1/R₁ (g mN3 » 1/R₁), the potential V₁ of the first node 1 assumes a potential Vth which is determined by a transconductance g mP2 of the transistor P₂ and a resistance of the resistor R₁. Therefore, a current i₁ flowing through the transistor P₂ is expressed in the following equation (3): i₁ = V th /R₁ Since a mirror circuit is formed by the transistors P₂ and P₄, if a transconductance g m of the transistor P₄ is called "g mP4 ", when the transistor P₄ operates in a saturation region, a current i₂ flowing through the transistor P₄ is expressed in the following equation (4): i₂ = {g mP4 / g mP2 } × i₁ Since the capacitor C is charged up by the current i₂, the potential V₂ of the second node 2 can be expressed in the following equation (5): V₂ = i₂ · t/C = {V th · t / R₁ · C} · {g mP4 / g mP2 } Here, if it is set that the transconductances of the transistors P₂ and P₆ are the same, the transconductances of the transistors N₃ and N₇ are the same and the resistances of the resistors R₁ and R₂ are the same, an inverter which includes a driver formed of the transistor P₆ and a load formed of the second resistor R₂ and the transistor N₇, will have a logical threshold represented by Vth. The reason for this is that: the same inverter as the inverter which includes the transistor P₆ as a driver and the second resistor R₂ and the transistor N₇ as a load, is formed of the transistor P₂ and the resistor R₁ and the transistor N₃; Since an input of the inverter formed of the transistor P₂ and the resistor R₁ and the transistor N₃, namely the gate of the transistor P₂ is connected to the first node 1 which is an output of the inverter formed of the transistor P₂ and the resistor R₁ and the transistor N₃, the first node 1 is biased to the logical threshold of the inverter formed of the transistor P₂ and the resistor R₁ and the transistor N₃; As mentioned above, the potential V₁ of the first node is Vth. Accordingly, when the potential V₂ of the second node 2 becomes equal to Vth, the inverter composed of the transistors P₆, the resistor R₂ and the transistor N₇ is inverted so as to generate a low level signal to the output terminal OUT. The delay time t D is given a time until the potential V₂ of the second node 2 is charged up from the ground potential GND to Vth. The delay time t D is expressed in the following equation (6): t D = C . R₁ . {g mP4 / g mP2 } Turning to Figure 6, there is shown a circuit diagram of a second embodiment of the delay circuit in accordance with the present invention. In Figure 6, elements similar or corresponding to those shown in Figure 4 are given the same Reference Numerals and Letters, and a suffix "a" is added to Reference Numerals and Letters given to elements having characteristics different from those of corresponding elements of the first embodiment. Therefore, explanation of the construction will be omitted. As seen from comparison between Figures 4 and 6, the second embodiment is different from the first embodiment in that, in the second embodiment, the capacitor C is connected between the second node 2 and the first voltage supply line Vcc. However, operation of the second embodiment is the same as that of the first embodiment, and therefore, detalied explanation of the operation will be also omitted. As can be understood from the first and second embodiments, the capacitor C can exert the same function regardless of whether a one end of the capacitor is connected to the first voltage supply line Vcc or the second voltage supply line GND. Actually, therefore, the one end of the capacitor can be connected to a voltage supply line which is preferred from a viewpoint of a layout. In other words, an increased degree of freedom in the layout can be obtained. In the first embodiment shown in Figure 4, it is set that the transconductances of the transistors P₂ and P₆ are the same, the transconductances of the transistors N₃ and N₇ are the same and the resistances of the resistors R₁ and R₂ are the same. In the second embodiment, consideration can be made by replacing P₆, R₂ and N₇ by P 6a , R 2a and N 7a , respectively, and by setting that a transconductance g m of the transistor P 6a is n × g mP6 , a resistance of the resistor R 2a is R₂/n, and a transconductance g m of the transistor N 7a is n × g mN7 . Under this condition, an inverter composed of the transistor P 6a , the resistor R 2a and the transistor N 7a has the same logical threshold as that of the inverter composed of the transistor P₂, the resistor R₁ and the transistor N₃. Therefore, the same operation as that of the first embodiment can be obtained. In this case, if n > 1, a power for driving a load connected to the output terminal OUT is increased, and if n < 1, a current flowing the inverter composed of the transistor P 6a , the resistor R 2a and the transistor N 7a becomes small, and therefore, a consumed power can be rendered small. In the above mentioned embodiments, each of the resistors R₁ and R₂ can be formed with a depletion FET which is connected to function as a resistive element. As seen from the above, the delay circuit in accordance with the present invention can have the delay time t D given the above mentioned equation (6), which can be set by setting the capacitance of the capacitor and the resistance of the resistor and also by setting a ratio of transconductances of the transistors P₂ and P₄. Here, in a MOS integrated circuit formed on a single substrate, a ratio of transconductances of MOSFETs of the same conduction or channel type can be set with a very high degree of precision, and therefore, the precision of the delay time is substantially governed by only the precision in the capacitance of the capacitor and in the resistance of the resistor. Accordingly, there can be obtained a delay circuit having the delay time t D which will never vary even if the characteristics (absolute precision) of the MOSFETs varies. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A delay circuit comprising: an input terminal (IN) and an output terminal (OUT); a first MOSFET (P₁) of a first channel type having a gate connected to the input terminal (IN), and a drain-source path connected at its one end to a first node (1) and at its other end to a first voltage supply line (Vcc); a second MOSFET (P₂) of the first channel type having a gate connected to the first node (1) and a drain-source path connected at its one end to the first node (1) and at its other end to the first voltage supply line (Vcc); a third MOSFET (N₃) of a second channel type opposite to the first channel tvpe, the third MOSFET (N₃) having a gate connected to the input terminal (IN), and a drain-source path connected at its one end through a first resistive element (R₁) to the first node (1) and at its other end to a second voltage supply line (GND); a fourth MOSFET (P₄) of the first channel type having a gate connected to the first node (1), and a drain-source path connected at its one end to a second node (2) and at its other end to the first voltage supply line (Vcc); a capacitive element (C) connected between the second node (2) and a predetermined voltage supply line (GND; Vcc); a fifth MOSFET (N₅) of the second channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal (IN), and a drain-source path connected at its one end to the second node (2) and at its other end to the second voltage supply line (GND); a sixth MOSFET (P₆) of the first channel type having a gate connected to the second node (2), and a drain-source path connected at its one end to the output terminal (OUT) and at its other end to the first voltage supply line (Vcc); and a seventh MOSFET (N₇) of the second channel type having a gate connected to the input terminal (IN), and a drain-source path connected at its one end through a second resistive element (R₂) to the output terminal (OUT) and at its other end to the second voltage supply line (GND), wherein the transconductances of the second, third, sixth and seventh MOSFETs (P₂, N₃, P₆, N₇) and the resistances of the first and second resistive elements (R₁, R₂) fulfil the following conditions: g m2 = n x g m6 g m3 = n x g m7 R₁ = R₂/n where g m2 , g m3 , g m6 and g m7 are transconductances of the second, third, sixth and seventh MOSFETs (P₂, N₃, P₆, N₇), respectively, R₁ and R₂ are resistances of the first and second resistive elements (R₁, R₂), respectively, and n is a positive number. A circuit as claimed in claim 1 wherein the capacitive element (C) is connected between the second node (2) and the second voltage supply line (GND). A circuit as claimed in claim 1 wherein the capacitive element (C) is connected between the second node (2) and the first voltage supply line (Vcc). A circuit as claimed in claims 1 to 3 wherein the second and fourth MOSFETs (P₂, P₄) form a current mirror circuit. A circuit as claimed in claims 1 to 4 wherein the first channel type is a P-channel type and the second channel type is an N-channel type.

Inventors: KOBATAKE HIROYUKI C O NEC CORP, KOBATAKE, HIROYUKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: H03H11
IPC codes: H03H11, H03K5