Semiconductor memory device

Abstract: In a semiconductor memory device having plural pairs of bit lines sense plural sense amplifiers, a gate electrode of a sense amplifier transistor for sensing potential of a first side of a first bit line pair is formed with an extension portion extending under and along the first side of a second bit line pair, and a capacitance C B formed between the extension of the gate electrode and the first side of the second bit line pair is determined to be equal or larger than that C A formed between the first side of the first bit line pair and the gate electrode. Since the potential of the first side of the bit line pair fluctuates roughly in phase with that of the second side of the same bit line pair, the harmful influence due to interference noise can be reduced, without increasing the chip layout area, by only modifying the shapes of the gate electrodes of the sense amplifier transistors.

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device provided with sense amplifiers. Fig. 2 shows a core portion of a DRAM (dynamic random access memory) as an example of the semiconductor memory device provided with sense amplifiers, in which a pair of bit lines BLi and BLi are connected to one of the sense amplifiers SAi (i=0, 1, 2 ... ), respectively. Coupling capacitances between two of these two adjacent bit lines can be represented, for example, by C₀ between a pair of two bit lines BL1 and BL1 , C₁ between two adjacent bit lines BL1 and BL0 , and C₂ between two adjacent bit lines BL2 and BL1 . Further, Fig. 3 shows transistors which constitute sense amplifiers, respectively, in which each electrode 1, 2, 3 or 4 of each transistor is formed under and along each bit line BL0 , BL1, BL1 or BL2 and connected to the bit line at each contact portion 5, 6, 7 or 8, thereof, respectively. In the prior-art semiconductor memory device provided with sense amplifiers as described above, however, since the distance between two adjacent bit lines (e.g. BL1 and BL0 ) is shorter than a distance between a pair of bit lines (e.g. BL1 and BL1 ) in general, there exists a problem in that interference noise is easily generated via each coupling capacitance. In addition, since the pitch distance between the two adjacent bit lines is increasingly shortened with the increasing integration rate of integrated circuits, the larger the coupling capacitances between the two adjacent bit lines is, the more the interference noise increases. However, when the potential between two adjacent bit lines fluctuates due to noise, since the potential between a pair of bit lines also fluctuates due to the interference noise via the coupling capacitances, the data-read potential generated when data are read out of each memory cell via a pair of the bit lines also fluctuates, thus resulting in a problem in that erroneous data may be amplified when the data-read potential is amplified by the sense amplifier. In practice, an assumption is made that high level data is read through the bit line BL1 and the potential of the bit line BL1 is at 1/2 V cc and that of BL1 is at a level a little lower than 1/2 V cc , where V cc denotes the supply voltage. Under these conditions, if the potential of the adjacent bit line BL0 fluctuates downward to the ground potential (V SS ) due to noise, since the potential of the bit line BL1 drops below the potential of the bit line BL1 according to the noise level, so that an erroneous data is read out of the memory in case the data is amplified by the sense amplifier under those abnormal conditions. In this case, if the same level noise is superposed upon another adjacent bit line BL2 simultaneously, since the difference in potential between a pair of the bit lines BL1 and BL1 does not change, the above-mentioned erroneous operation can be prevented. However, if noise is superposed upon only one of the two adjacent bit lines BL0 and BL2 into unbalanced conditions, erroneous operation is liable to occur. To overcome the problem caused by the above-mentioned interference noise between two bit lines, there has been proposed a method of canceling two in-phase noise superposed upon the two adjacent bit lines by crossing a pair of bit lines as shown in Fig. 4. Such a prior art memory is disclosed for instance in US-A-3 942 164. In this prior-art memory, however, since the two bit lines are crossed, there arise other problems in that the chip area increases and therefore the device core forming process is complicated. SUMMARY OF THE INVENTION With these problems in mind, therefore, it is the object of the present invention to provide a semiconductor memory device which can minimize interference noise due to capacitance coupling between two bit lines without increasing the chip layout area. To achieve the above-mentioned object, in the semiconductor memory device according to the present invention a gate electrode ( G₁ ) of a transistor constituting a part of the sense amplifier for sensing a potential of a first line ( BL1 ) of a first pair of bit lines ( BL1 and BL1) is formed with an extension portion (14) extending under and along a corresponding first line ( BL0 ) of a second pair of bit lines ( BL0 , BL0) arranged adjacent to the second line (BL1) of the first pair of bit lines; and a capacitance (C B ) formed between the extension portion (14) of the gate electrode ( G₁ ) and the corresponding first line ( BL0 ) of the second pair of bit lines is determined to be equal or larger than a capacitance (C A ) formed between the first line ( BL1 ) of the first pair of bit lines and the gate electrode ( G₁ ). With the present invention, since the potential of the bit line BL1 fluctuates roughly in phase with that of the bit line BL1, it is possible to reduce the interference noise due to capacitance coupling between the two bit lines as much as possible, without increasing the chip layout area, by only modifying the shapes of the gate electrodes of the sense amplifier transistors. BRIEF DESCRIPTION ON THE DRAWINGS Fig. 1 is a bit line arrangement diagram showing an embodiment of the semiconductor memory device according to the present invention; Fig. 2 is a prior-art bit line arrangement diagram for assistance in explaining sense amplifier configuration; Fig. 3 is a prior-art bit line arrangement for showing transistor gate electrodes of the memory device; and Fig. 4 is a prior-art bit line arrangement for assistance in explaining the method of canceling interference noise between two bit lines. DETAILED DESCRIPTION ON THE PREFERRED EMBODIMENTS Fig. 1 shows an embodiment of the semiconductor memory device according to the present invention, in which two gate electrodes G₁ and G₁ of two transistors connected to a pair of bit lines (e.g. bit lines BL1 and BL1 ) as a sense amplifier are improved in shape. In Fig. 1, the bit lines BL0 , BL1, BL1 , BL2, ... are all formed on an insulating film (not shown) formed on an element such as transistors, for instance. The gate electrode G₁ connected to the bit line BL1 at a contact portion 11 is composed of a first straight portion 12 extending under and along the bit line BL1 , a second straight portion 13 extending from the contact portion 11 at a right angle with respect to the bit line BL1 to under the adjacent bit line BL0 passing through under the bit line BL1, and a third straight portion 14 extending under and along the adjacent bit line BL0 . Further, the gate electrode G₁ connected to the bit line BL1 at a contact portion 21 is composed of a first straight portion 22 extending from the contact portion 21 at a right angle with respect to the bit line BL1 to under the adjacent bit line BL2 passing through under the bit line BL1 , and a second straight portion 23 extending under and along the bit line BL2. In general, since the gate electrodes are formed of polysilicon and the bit lines are formed of aluminium and further these electrodes and bit lines have a specific resistivity, respectively, there exists a capacitance between each electrode and each bit line, respectively. For instance, in Fig. 1, a parasitic capacitance C A is formed between the gate electrode G₁ and the bit line BL1 and a parasitic capacitance C B is formed between the gate electrode G ₁ and the bit line BL0 with respect to the gate electrode G₁ . Further, a parasitic capacitance C C is formed between the gate electrode G₁ and the bit line BL2 with respect to the gate electrode G₁. In other words, two bit lines are to be coupled to each other via these capacitances. Therefore, it is possible to prevent erroneous operation of the sense amplifier by selectively determining these parasitic capacitances of the gate electrode G₁ so that the capacitance C A is equal to or smaller than C B (C A ≦ C B ). Using this condition, when the potential of the bit line BL0 fluctuates due to noise, the potential of the bit line BL1 fluctuates to the same direction as that of the bit line BL0 due to coupling with the bit line BL0 . At that time, since the bit line BL1 is positively coupled with the bit line BL0 through the gate electrode G1, the potential of BL1 fluctuates to the same direction as that of the bit line BL0 . Accordingly, bit lines BL1 and BL1 fluctuate to the same direction. Furthermore, if the parasitic capacities C A and C B are made C A ≦ C B , the fluctuation amount of the two bit lines will be approximately similar value. As a result, the potential difference between the bit lines BL1 and BL1 is balanced with the interference noises of those lines, and therefore the interference noise is regarded as being decreased, which can prevent erroneous operation. In the same way, when the potential of the bit line BL2 fluctuated due to noise, it is possible to prevent the erroneous operation of the sense amplifier in dependence upon the potential fluctuations of the bit line BL1, owing to the presence of the gate electrode G₁. In the above mentioned shown in Fig. 1, two gate electrodes of two different shapes have been adopted to the bit lines BL1 and BL1. Without being limited thereto, however, it is also possible to adopt the same shape to these two gate electrodes. Further, the U-shaped gate electrode G₁ of a transistor as shown in Fig. 1 can prevent transistor characteristics from being unbalanced by positioned mismatching an ion injection angle difference. Further, the capacitance C A , C B and C C can be adjusted by changing the length, width and material of the gate electrode or the thickness of the insulating oxide film formed between the bit line and the gate electrode. Therefore, it is possible to obtain any given capacitance by appropriately adjusting these factors. In the semiconductor memory device according to the present invention, the chip layout area can be reduced as compared with the prior-art device shown in Fig. 4, in which two bit lines are crossed with each other, respectively. Further, it is possible to more effectively reduce the harmful influence upon the device due to the interference noise by determining the capacitors between two bit lines as C₃ ≃ C₁ and C₄ ≃ C₂, where C₁ denotes the capacitance between the two bit lines BL0 and BL1; C₂ denotes that between BL1 and BL2; C₃ denotes that between BL1 and BL0 ; and C₄ denotes that between BL1 and BL2. Further, it is also possible to reduce the influence of the interference noise by increasing the overlap area of the transistor gate electrode and the adjacent bit line BL0 or BL2 to as broad as possible. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory device having a plurality of pairs of parallel-arranged bit lines and a plurality of sense amplifiers for detecting a potential change of each bit line, respectively, characterized in that a gate electrode ( G₁ ) of a transistor constituting a part of the sense amplifier for sensing a potential of a first line ( BL1 ) of a first pair of bit lines ( BL1 and BL1) is formed with an extension portion (14) extending under and along a corresponding first line ( BL0 ) of a second pair of bit lines ( BL0 , BL0) arranged adjacent to the second line (BL1) of the first pair of bit lines; and a capacitance (C B ) formed between the extension portion (14) of the gate electrode ( G₁ ) and the corresponding first line ( BL0 ) of the second pair of bit lines is determined to be equal or larger than a capacitance (C A ) formed between the first line ( BL1 ) of the first pair of bit lines and the gate electrode ( G₁ ). The semiconductor memory device of claim 1, wherein the gate electrode ( G1 ) of the transistor is further formed with an additional extension portion (12) formed under and along the first line ( BL1 ) of the first pair of bit lines ( BL1 , BL1). The semiconductor memory device of claim 1, wherein a first capacitance (C₁) formed between the first line ( BL0 ) of the second pair of bit lines ( BL0 , BL0) and a second side (BL1) of the first pair of bit lines ( BL1 , BL1) is roughly equal to a third capacitance (C₃) formed between the first line ( BL0 ) of the second pair of bit lines and the first line ( BL1 ) of the first pair of bit lines. The semiconductor memory device of claim 1, wherein the second pair of bit lines and a third pair of bit lines ( BL2 , BL2) are arranged adjacent to and on both sides of the first pair of bit lines ( BL1 , BL1); another gate electrode (G1) of another transistor for sensing a potential of a second line (BL1) of the first pair of bit lines ( BL1 and BL1) is formed with an extension portion (23) extending under and along a second line (BL2) of the third pair of bit lines; a first capacitance (C₁) formed between the first line ( BL0 ) of the second pair of bit lines and a second line ( BL1 ) of the first pair of bit lines is roughly equal to a third capacitance (C₃) formed between the first line ( BL0 ) of the second pair of bit lines and the first line ( BL1 ) of the first pair of bit lines; and a second capacitance (C₂) formed between the first line ( BL1 ) of the first pair of bit lines and the second line (BL2) of the third pair of bit lines is roughly equal to a fourth capacitance (C₄) formed between the second line (BL1) of the first pair of bit lines and the second line (BL2) of the third pair of bit lines.

Inventors: KOYANAGI MASARU, TAKEUCHI YOSHIAKI, KOYANAGI, MASARU, TAKEUCHI, YOSHIAKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G11C7
IPC codes: G11C11, H01L27, G11C7, H01L21, G11C5