Adaptive compensating ramp generator for current-mode DC/DC converters

Abstract: A circuit (20, 40, 50, 60) for generating an optimal compensating ramp voltage signal V cramp , with the minimum necessary slope, m c for a current mode DC/DC converter is shown. The adaptive compensating ramp generating circuit (20) is comprised of two voltage dividers (22, 24), the first voltage divider 22 divides an input voltage V IN and the second voltage divider 24 divides an output voltage V OUT . The first voltage divider (22) has two resistors (26, 28) in series: the first resistor (26) has a resistance of (1/B - 1) * R ohms and the second resistor (28) has a resistance of R ohms. V OUT is divided by the second voltage divider (24) having two resistors (29, 30) in series: the first resistor (29) has a resistance of (1/A - 1) * R ohms and the second resistor (30) has a resistance of R ohms. The constants A, B, and C are selected for the particular type of DC/DC converter employed. The divided voltages A * V OUT and B * V IN are input into a voltage controlled current source (32). The voltage controlled current source (32) has a scaling resistor R scale , an amplifier (36), a transistor Q, and a diode D1. The output of the current source (38) is coupled to a capacitor C ramp whose voltage realizes the slope of the compensating ramp signal, V cramp . The capacitor C ramp is charged through R scale .

Description: The present invention relates to a compensating ramp and more particularly the invention relates to an adaptive compensating ramp generator for current mode DC to DC converters. A compensating ramp changes the slope at which a reference voltage intersects with the current sense voltage signal. Conventional current-mode controlled DC to DC (DC/DC) converters operating above 50% duty cycle need a compensating ramp signal superimposed on a current sense signal, which is used as a control parameter, to avoid "open loop instability" or "subharmonic oscillation". To avoid subharmonic oscillation, the slope of the current sense voltage during ON time (m up ) must be greater than the reflected slope (m do ), where the reflected slope is the change between the ending amplitude of the current sense voltage and its starting amplitude at the beginning of the next cycle, divided by the OFF time. m up is usually less than m do for a >50% duty cycle. Therefore, to make m up greater than m do , a ramp signal having additional slope is superimposed onto the current sense signal. In the past, the compensating ramp signal was formed by scaling the system's oscillator timing signal and adding it to the current sense voltage or deducting it from the error amplifier's output voltage. The necessary slope of the compensating ramp signal is dependent upon the input and output voltage of the DC/DC converter and the value of the inductor used. In transformer coupled systems, the necessary slope is also dependent upon the transformer's turn ratio. Traditional systems set the ramp signal's slope to accommodate for the worst case conditions: maximum output voltage (in variable output voltage systems only) and minimum input voltage. By designing the slope to accommodate for the worst case situation, under normal operating conditions, the slope and accordingly the amplitude of the ramp is higher than necessary. For example, in wide input range systems, the amplitude is often two to three times higher than necessary for stability. There are two primary disadvantages associated with having a compensating ramp signal with excessive slope. First, the maximum available output current of the system is limited; the steeper the slope, the lower the amount of current available at current limit. Second, the phase margin of the amplitude control loop is decreased. The independent claims define the concept of the present invention aiming to overcome the drawbacks set forth above. The features in their preambles are known from WO-A-89/0360. Preferably, the present invention provides a circuit for generating a compensating ramp signal in a switching regulator of the type which is responsive to an unregulated input voltage (V in ) and which provides a regulated output voltage (V OUT ). The circuit includes a sense resistor (R s ) which provides a signal proportional to the current flowing through the switch; means for storing energy having an inductance (L); and means for amplifying having a predetermined gain (A I ) to amplify the signal from the sense resistor. The signal from the sense resistor is used to control the operation of the switching regulator. The compensating ramp circuit comprises means for generating a compensating ramp voltage signal having a slope (m c ) which conforms to the equation m c > (A * V OUT - B * V IN ) * C where A ≤ 1, B ≤ 1, and C is a constant dependent upon R s , L, and magnetic coupling parameters associated with the energy storage means. The circuit includes means for superimposing the generated compensating ramp voltage onto the signal from the sense resistor such that the stability of the switching regulator is ensured. Parameters A, B, C are selected according to the type of switching regulator. The means for generating the compensating ramp having the slope m c , in the preferred embodiment, may include means responsive to the output voltage for providing a first signal which is equal to the output voltage divided by a first preselected amount, means responsive to the input voltage for providing a second signal which is equal to the input voltage divided by a second preselected amount, and means for generating a signal proportional to the difference between the first and second signals. According to the present invention it is possible to optimize the amplitude and slope of a compensating ramp signal to have the maximum available current available at current limit. In preferred form, the present invention is to provide an adaptive compensating ramp generator having one external scaling resistor to generate the necessary ramp over the entire input/output voltage range of a DC/DC converter and frequency range, in adjustable frequency systems. Preferably, the present invention employs an internal fixed scaling resistor in a fixed frequency system with a limited range of applicable inductors. These, and further objects and advantages of the present invention will be made clear or will become apparent during the course of the following description of the preferred embodiment of the present invention. In the accompanying drawings: Figure 1 is a functional block diagram of a conventional buck DC to DC converter having a compensating ramp generator; Figure 2 is a timing diagram corresponding to the circuit of Figure 1; Figure 3 is a diagram of the buck converter of Figure 1 having a traditional fixed slope compensating ramp generator circuit. Figure 4 is a circuit diagram of a ramp generator circuit of the present invention; Figure 5 is circuit diagram of another ramp generator of the present invention for a DC/DC boost converter; Figure 6 is a circuit diagram of another ramp generator of the present invention for a DC/DC buck converter; Figure 7 is a block diagram of a DC/DC flyback converter having a ramp generator of the present invention; Figure 8 is a block diagram of a DC/DC buck-boost converter having a ramp generator of the present invention; Figure 9 is a block diagram of a DC/DC forward converter having a ramp generator of the present invention; and Figure 10 is a circuit diagram of still another ramp generator of the present invention. Referring to Figures 1 and 2, Figure 1 is a functional block diagram of a current mode buck (or step down) DC to DC (DC/DC) converter 10 operating at above a 50% duty cycle and having a compensating ramp generator 12. Figure 2 is the timing diagram corresponding to the circuit 10 in Figure 1. Figure 2c illustrates the slope m up and the reflected slope m do of the current sense signal through R s having voltage V s . A DC/DC converter converts one signal having a particular DC level to another DC level. The buck converter 10 includes a power switch 14 which may be a field effect transistor (FET); a sense resistor R s connected between an input voltage source V in and the power switch 14; a ramp scaling resistor R r connected between the resistor R s and the switch 14 where Voltage V c is the voltage drop across R r and V c has a slope of m c ; a current amplifier A I which has V in and voltage V c as its inputs; and filtering components 16 which are connected between the power switch 14 and a load R L . The filtering components 16 include a capacitor C o , an inductor L, and a diode D. The output voltage V OUT is provided at one of the inputs to an error amplifier 11. The error amplifier 11 is comprised of an amplifier A e which compares V OUT with a reference voltage V ref . The current through the power switch 14 I 14 (Figure 2b) is sensed by resistor R s. The sensed current is used to turn the power switch 14 OFF. Resistor R r scales the compensating ramp voltage V c having a slope of m c , and is much greater than sense resistor R s (R r >>R s ). The system clock 18 or oscillator provides a clock pulse V 5 (Figure 2a) to the main flip-flop FF 40 and turns on the switch 14 in each period. As illustrated in Figures 2a, 2b and 2c, the clock pulse V 5 turns on the switch 14 causing current to flow through the swtich I 14 and resistor R s . The voltage V s wave form and power current waveform mirror one another. The compensating ramp generator 12 also receives the system clock 18 timing signal, V osc , and voltages V in and V OUT . The compensating ramp generator 12 generates a compensating ramp signal 21 having a voltage V cramp (Figure 2d) and a slope of m 21 = M C g M * R r where g m is the transconductance of a voltage to current converter 42. V TH , a threshold voltage, adjusts the starting instant of the ramp signal 21 and the voltage to current converter 42 level shifts the compensating ramp signal 21 up to the voltage level of the input signal V in and generates a level shifted compensating ramp signal 43. The voltage of the level shifted compensating ramp signal 43 is V c . V c is the voltage drop across the ramp scaling resistor R r . The compensating ramp generator 12 may also use V IN , V OUT , V OSC , the output signal of the flip-flop 40 and a DC threshold voltage V th to generate the compensating ramp signal 21, depending on the construction of the compensating ramp generator circuit 12 employed. The output signal 15 of the error amplifier 11 is input to a comparator 13 where it is compared with the amplified signal 23 (Figure 2g). The amplified signal 23 is the amplified sum V c + V s of the switch current sense voltage V s and V c (Figure 2f). When the modified current sense signal 23 is equivalent to the output signal 15 out of the error amplifier 11, comparator 13 outputs a comparison signal 17 (Figure 2h) when the current sense signal 23 is equivalent to the output signal 15. The comparison signal 17 is input to flip flop 40 and resets the flip-flop 40. The flip flop 40 outputs a driver control signal 41 (Figure 2i) which turns off the switch 14 through driver 19. Referring in particular to Figures 2h and 2i, when the comparison signal 17 is high, the signal 41 out of the flip flop 40 goes low and the switch 14 is turned OFF. The flip flop output signal 41 remains low until the next clock pulse V 5 is received. The maximum available output voltage of the error amplifier 11 thereby limits the available maximum current from the switch 14 (i.e., the maximum available voltage limit acts as a current limit). In most systems, the error amplifier's maximum output voltage is internally limited to set the current limit to the desired value. The condition for stability of a conventional DC/DC converter's power stage is: m c ≥ m do - m up where m c = slope of the level shifted compensating ramp voltage signal V c m up = slope of the current sense voltages V s during ON-time m do = reflected slope (i.e., the change in amplitude between the ending amplitude of the current sense voltage during an ON-time cycle and the starting amplitude of the current sense voltage at the beginning of the next ON-time cycle, divided by the OFF time.) For a buck DC/DC current-mode converter the slopes of m up and m do of Equation (Eq.) 1 are defined as follows: m up = V IN - V OUT - V SAT L * R s and m do = V OUT + V D L * R s where V SAT is the power FET saturation voltage, and V D is the forward biased diode voltage. Using Eq. 1, the condition for stability of the compensating ramp's slope is: In systems with high efficiency, V D and V SAT are << V OUT and << V IN , and therefore, V D and V SAT can be neglected. Therefore, m c becomes: m c > (A * V OUT - B * V IN ) *C where A ≤ 1 B ≤ 1 C = a constant which is dependent upon the R s , L, n (n = n s /n p the turns ratio of any transformer employed) and L p (primary inductance of any transformer employed in the switching circuit.) The minimum necessary slope of the level shifted compensating ramp signal 43 (Figure 1), for most types of current-mode-controlled DC/DC converters, can be expressed in the format of Equation 5. In particular, for a buck converter, a boost converter, a flyback converter, a forward converter, and a buck-boost converter, the preferred parameters for Equation 5 are summarized below: DC/DC Converter A B C Buck 1 ≤.5 2R S /L Boost ≥.5 1 2R S /L Flyback n ≥ 1 ≥1/n 1 R S / L P n < 1 1 ≤n R S /nL P Forward n ≥ 2 ≥2/n 1 n 2 R S /L n < 2 1 ≤n/2 2nR S /L Buck-Boost 1 ≤1 R S /L The compensating ramp slope m c is meaningful only if it is positive or 0. Referring to Figure 3, a buck converter circuit 31 with a traditional compensating ramp generator circuit 33 is illustrated. Elements in other embodiment which are similar are referred to with the same reference numerals/names. The transistor Q12 and resistor R scale realize the compensating ramp block 12 and the V to I converter block 42 in Figure 1. In the circuit 33 R r /R Scale and the slope of the oscillator's timing signal (V COSC ) set the slope of the compensating ramp voltage V c having a slope m c . Aside from the disadvantage of generating a compensating ramp voltage V c having a fixed slope, the circuit 31 has high temperature sensitivity because of the approximately -0.3%/°K temperature coefficient of the base-emitter voltage of transistor Q12. Referring to Figure 4 in conjunction with Table 1, an adaptive circuit 20 for generating a compensating ramp voltage signal (V cramp ), having a minimum slope, m 21 , where m 21 = M C g m * R r for most types of DC/DC converters, is illustrated. The circuit 20 generates the optimal compensating ramp signal 21 with the minimum slope m 21 , for a specific type of DC/DC converter by selecting the constants A, B, and C according to Table 1. A and B may be varied so long as A and B are selected so that m c is larger or equivalent than necessary (i.e., to ensure the stability of the system). C may also be varied to be greater than the value in Table 1. But, the farther A and B deviate from the preferred values of Table 1, the higher the ramp generated and the less current available at current limit because the error amplifier's maximum output voltage is constant. The adaptive compensating ramp generating circuit 20 is comprised of two voltage dividers 22, 24. The first voltage divider 22 divides an input voltage V IN and the second voltage divider 24 divides an output voltage V OUT , For a boost converter, for example, V IN ≤ V OUT and for a buck converter, V IN ≥ V OUT . The input voltage, V IN , is divided by the first voltage divider 22 having two 26, 28 resistors in series: the first resistor 26 has a resistance of (1/B - 1) * R ohms and the second resistor 28 has a resistance of R ohms such that the divided voltage at point B is V IN * B. Output voltage, V OUT , is divided by the second voltage divider 24 having two resistors 29, 30 in series: the first resistor 29 has a resistance of (1/A - 1) * R ohms and the second resistor 30 has a resistance of R ohms such that the divided voltage at point A is V OUT * A. The divided voltages A * V OUT and B * V IN serve as the two inputs to a voltage controlled current source 32 which has two inputs and an output 38. The voltage controlled current source 32 includes a buffer amplifier 34 connected to a scaling resistor R scale and a feedback loop operational amplifier 36 which is connected between the scaling resistor R SCALE and a transistor Q, and a diode D1. Since the operational amplifier 36 is a feedback loop amplifier, ideally, it does not consume current, so that the current across the scaling resistor R scale is: I RSCALE = A * V OUT - B * V IN R Scale The output of the current source 38 is coupled to a capacitor C ramp whose voltage realizes the slope m 21 of the compensating ramp signal, V cramp . The capacitor C ramp is charged through the I c collector current of the Q transistor. If the transistor Q has a resonably high β, I c = I E = I RScale (for example, a β of about 100 or higher). Resistor R Scale controls the rate at which the voltage increases in the capacitor C ramp (ie. the rate at which the capacitor charges up). The slope of the compensating ramp signal 21 having the voltage V cramp is: m 21 = I C ramp = A V OUT - B V IN R Scale * C ramp = 1 R Scale C ramp (A*V OUT - B*V IN ) where the constant C in Equation 5 is: C = 1 R Scale * C ramp g m R r A switch S across the capacitor C ramp discharges capacitor C ramp at the end of each period. The switch S is ON until the start of the next clock period (when the main switch 14 turns ON again) or almost until half of the next clock period has elapsed. The value of the capacitor C ramp , the resistor R Scale , R r and g m , realize the necessary value of the constant C in Eq. 5. The C constant of Eq. 7 has to be more than equal to the C constant of the converter according to Table 1. For example, for a boost converter, g m R r R Scale * C Ramp > 2R s L Therefore, R Scale < L * g m R r C ramp * 2R s Referring to Figure 5 and to Table 1, for a DC/DC converter either A or B is 1. Hence, the circuit 20 may be simplified by eliminating the buffer amplifier 34 and the operational amplifier 36 and replacing the amplifier 36 by a single transistor Q2. A compensating ramp generator circuit 40 for a boost converter is illustrated in Figure 5. The boost ramp generator circuit 40 is based upon the modified general compensating ramp generator circuit 20 of Figure 4, the general circuit 20 having been modified and simplified to reflect the preferred values of A, B, and C for the boost converter. In the preferred embodiment, for a boost converter circuit 40, A is about equal to 0.5, B is about equal to 1, and C is about equal to 2 R s /L. The boost converter ramp generator circuit 40 has a voltage controlled current source 42 which is comprised of two bipolar transistors Q1, Q2. Transistor Q1 is responsive to the output voltage V OUT and transistor Q2 is responsive to the input voltage V IN . In the preferred embodiment, transistor Q1 is a PNP transistor which is used as an emitter follower. Transistor Q1's base is connected to a first voltage divider 44 having a first resistor R 1 having a resistance of R ohms, in series with a second resistor R 2 having a resistance of R ohms such that the divided voltage at point A is 0.5 V OUT . Transistor Q1's emitter is biased to a first potential V OUT through a resistor R 3 , with a resistance of R ohms, to ensure that transistor Q1 operates in the linear active region. Transistor Q1's collector is connected to ground. The second transistor Q2 is a split collector PNP transistor, in the preferred embodiment. Two transistors having their bases and emitters connected together may be used instead of the split collector PNP transistor. The circuit 40 is responsive to the change in current through transistor Q2's multiple collectors C1, C2. Transistor Q2's emitter is connected to transistor Q1's emitter such that transistor Q2's base voltage is also 0.5 * V OUT . One of Q2's collectors C2 is connected to its base and to a scaling resistor, R scale . Transistor Q2 acts like a current mirror since the current I c which flows through resistor R scale is mirrored and output to the capacitor C ramp . By charging and discharging C ramp , by a switch, S, the compensating ramp voltage V cramp is generated. In a boost converter since B is about 1, the second voltage divider has a division ratio of 1 (i.e., the divider is redundant (non-existent)). Hence voltage V IN is not divided down before being fed to resistor R scale . Voltage V IN is connected to transistor Q2 through resistor R scale . The resistor R scale , capacitor C ramp , the split ratio between the two PNP collectors together with g m and R r realize the C constant of Eq. 5. Referring now to Figure 6, a compensating ramp generating circuit for a buck converter 50 is illustrated. The buck compensating ramp generator circuit 50 is functionally equivalent to the general compensating ramp circuit 20 of Figure 4, however the buck ramp circuit 50 having been designed to account for the preferred parameters identified in Table 1. As shown in Table 1, for a buck converter, A is about equal to 1, B is about equal to 0.5, and C is about equal to 2 R Scale /L. The buck converter ramp generating circuit 50 is similar to the boost converter compensating ramp circuit 40 in that the buck ramp circuit 50 also has one voltage divider 52, and two bipolar transistors Q3, Q4, a capacitor C ramp , and a scaling resistor R scale . However, in the buck compensating ramp circuit 50 transistor Q3's emitter is connected to transistor Q4's collector and base. The voltage divider 52 has a first resistor R 1 and a second resistor R 2 in series each having a resistance of R ohms. The first voltage divider 52 is connected to a first potential V IN such that the voltage at point B is 0.5 * V IN . Hence, the voltage into transistor Q3's base is 0.5 * V IN . Transistor Q3's collector is coupled to V IN . Resistor R 3 has a resistance of R ohms and it ensures that transistor Q3 operates in the linear active region. Since A is about equal to 1 in a buck converter, voltage V OUT is connected directly to transistor Q4 through resistor R scale . In the preferred embodiment, transistor Q4 is a split collector PNP transistor where one of its collectors C2 is connected to transistor Q3's emitter and also to its base. As previously discussed, two transistors may be used instead of a split collector transistor. The other collector C1 of transistor Q4 is coupled to capacitor C ramp . Transistor Q4's emitter is coupled to resistor R scale and transistor Q3's emitter sets the voltage across the resistor R scale and the base-emitter of transistor Q4. Transistor Q4 acts like a diode and functions like a current splitter. It splits its emitter current, which is set up by R Scale , V OUT , and Q3's emitter voltage, into two equivalent parts: I c ′ and I c (if the split ratio of C1 and C2 is 1 / 2 to 1 / 2). I c ′ charges the capacitor C ramp . In this manner, V OUT sets the current in the capacitor C ramp through C1 since the current across resistor R scale is split. Referring to Figure 7 a flyback DC/DC converter circuit 70 is illustrated having a compensating ramp generator 20 of the present invention. The filtering component 16 of the flyback circuit 70 includes a transformer 72. The transformer has n p number of primary turns and n s number of secondary turns such that n = n s /n p (the transformer's turns ratio). In addition, the sense resistor R sense is referenced to ground, the switch's 14 drain is coupled to the primary inductor, and the switch's 14 source is connected to ground through resistor R sense . As shown in Table 1, in the compensating ramp generator circuit 20 for a flyback converter for n > 1, A is about equal to 1/n and B is about equal to 1; for n < 1, A is about equal to 1 and B is about equal to n. The circuit 20 may be modified for these preferred parameters. Referring to Figure 8, a buck boost DC/DC converter circuit 80 is illustrated having a compensating ramp generator 20 of the present invention. The buck boost circuit 80 is similar to the conventional buck converter circuit 10 illustrated in Figure 1 but in the buck boost circuit 80 the inductor and the diode change places. As shown in Table 1, for the ramp generator circuit 20 for the buck boost converter, A is about equal to one, B is about equal to 1, and C is about equal to R s /L. Again the ramp generator circuit may be modified for these preferred parameters. Referring to Figure 9, a forward DC/DC converter circuit 90 is illustrated having a compensating ramp generator 20 of the present invention. The forward circuit 90 is similar to the Figure 7 but the filtering component 16 of the forward circuit 90 further includes an inductor, L, 94 and an additional diode D3 in addition to the transformer 92. In the forward circuit 90, the sense resistor R sense is referenced to ground, and the power switch 14 drain is coupled to the transformer 92. The switch's 14 source is also referenced to ground through resistor R sense . The transformer 92 has a turns ratio of n = n s /n p . As shown in Table 1, for the compensating ramp generator circuit 20 for the forward DC/DC converter for n > 2: A is about equal to 2/n, B is about equal to 1, and C is about equal to n 2 *R s /L. For n < 2, A is about equal to 1, B is about equal to n/2, and C is about equal to 2*n*R s /L. Referring to Figure 10, another circuit diagram of a compensating ramp generator circuit 60 having a multiplier 62 and a constant slope ramp voltage signal 68, is illustrated. The constant slope ramp voltage signal 68 is generated by an oscillator 18, which is present in the switching regulator circuit 10, in conjunction with an energy storage timing element, which in the preferred embodiment is a capacitor C osc . The multiplier 62, which is a differential input multiplier in the preferred embodiment, has two differential input pairs (x1, x2) and (y1, y2) and an output voltage V cramp . Input y1 corresponds to the constant slope ramp voltage signal 68. The gain coefficient D of the multiplier 62 is D = C m osc * g m * R r where m osc = is the slope of the constant slope voltage signal 68 of the energy storage timing element. C = is the C constant of Eq. 5 The first pair of multiplier inputs (x1,x2) is connected to a first and a second voltage divider, 64, 66 respectively. The first voltage divider 64, for dividing a first potential V OUT , and has two resistors (1/A - 1) * R and R 1 in series. The divided voltage V OUT at point A is denoted as x2. The second voltage divider 66, has two resistors (1/B - 1) * R and R 2 , for dividing a second potential V IN . Resistors R 1 and R 2 have substantially the same resistance of R ohms. The divided voltage V IN , at point B, is denoted as x1. One of the second multiplier inputs y1 is connected to the switching regulator circuit 10 oscillator 18 and to the capacitor C osc . As previously discussed, C osc , generates the constant ramp voltage V osc 68. The other one of the multiplier's second input pairs y2 is connected to a DC reference voltage V ref which generates a threshold voltage V th . With voltage V th , the starting instant of the compensating ramp can be adjusted. The value of V ref is less than or substantially the same as the average value of the ramp voltage out of the multiplier V cramp . Resistor R scale is the gain setting resistor of the multiplier 62 that sets the C constant to the appropriate value. The multiplier 62 takes the difference between the (x1, x2) inputs and the difference between the (y1, y2) inputs and multiplies the differences by the multiplier gain coefficient D to generate a compensating ramp signal V cramp . The multiplier 62 operates only when both differential input voltages (x1, x2) (y1, y1) are positive. Otherwise voltage V cramp is approximately 0. Voltage V cramp is about zero if the differential voltage of either of the input pairs (x1,x2) (y1,y2) is negative. No compensating ramp is needed when the duty cycle d ≤ 0.5. This means that V th can be set to threshold voltage V th ≤ (V p - V v )/2 or lower. V p = peak value of the voltage and V v is the minimum value of the voltage.

Claims: A circuit generating a positive compensating ramp signal in a switching DC-DC current mode regulator comprising at least a controlled switching element (14), said regulator being responsive to an unregulated input voltage (V IN ) and which provides a regulated output voltage (V OUT ), the switching regulator having a sense resistor (R S ) that provides a sense signal proportional to the current flowing through said switching element (14), the sense signal being used to control the operation of the switching regulator, and means for storing energy including an inductance (L), the circuit comprising means for superimposing the generated ramp signal to the sense signal, the ramp signal being related to said input and output voltages, characterized by means for generating a ramp voltage having a slope (m c ) which is equal to or exceeds (A*V OUT - B*V IN )*C wherein A is smaller or equals 1, B is smaller or equals 1, and C is a factor dependent upon said sense resistor resistance, said inductance, and magnetic coupling parameters associated with the energy storage means, and wherein A, B, and C are constants greater than zero and selected in accordance with the type of switching regulator. The circuit of Claim 1, wherein A, B, C are selected according to the type of switching regulator as follows: Switching Regulator A B C Buck 1 ≤.5 2R s /L Boost ≥.5 1 2R s /L Buck-Boost 1 ≤1 R s /L The circuit of Claim 1, wherein the switching regulator is a buck converter and A is equal to about one, B is equal to about one-half, and C is equal to about 2*R s /L. The circuit of Claim 1, wherein the switching regulator is a boost converter and A is about equal to one-half, B is about equal to one, and C is about equal to 2*R s /L. The circuit of Claim 1, wherein the means for storing energy is a transformer having a primary winding of n p turns, a secondary winding of n s turns, and a turns ratio of n, where n= ns /n p , and the inductance of the energy storing means is L p . The circuit of Claim 5, wherein A, B, and C are selected according to the type of switching regulator as follows: Switching Regulator A B C Flyback n > 1 ≥1/n 1 R s /L p n < 1 1 ≤n R s /nL p Forward n > 2 ≥2/n 1 n 2 R s /L n < 2 1 ≤n/2 2nR s /L The circuit of Claim 5, wherein the switching regulator is a flyback converter and n is greater than about one such that A is about equal to 1/n, B is about equal to one, and C is about equal to R s /L p . The circuit of Claim 5, wherein the switching regulator is a flyback converter and n is less than about one such that A is about equal to one, B is about equal to n, and C is about equal to R s /(n*L p ). The circuit of Claim 5, wherein the switching regulator is a forward converter and n is greater than about two such that A is about equal to 2/n, B is about equal to 1, and C is about equal to n 2 *R s /L. The circuit of Claim 5, wherein the switching regulator is a forward converter and n is less than about two such that A is about equal to one, B is about equal to n/2, and C is about equal to 2*n*R s /L. The circuit of Claim 1, wherein the switching regulator is a buck-boost converter and A is about equal to one, B is about equal to one, and C is about equal to R s /L. A method for generating a positive compensating ramp signal having a slope (m c ) in a switching current mode DC-DC regulator comprising at least a controlled switching element, the regulator being responsive to an unregulated input voltage (V IN ) and which provides a regulated output voltage (V OUT ), the switching regulator having a sense resistor (R S ) that provides a sense signal proportional to the current flowing through said switching element (14), the sense signal being used to control the operation of the switching regulator, and means for storing energy including an inductance (L), the method including the step of superimposing the generated ramp signal to the sense signal, the ramp signal being related to said input and output voltages, characterized in that a first voltage proportional to the output voltage is generated, a second voltage proportional to the input voltage is generated, the respective constant proportionality factors being greater than zero and smaller than or equal to 1 and being selected in accordance with the type of switching regulator, and that the difference between said first and second voltages is multiplied by a constant factor determined by the resistance of said sense resistor, said inductance, and magnetic coupling parameters associated with the energy storage means to generate a compensating ramp voltage with a slope equal to or exceeding the multiplied difference. A circuit as in claim 1 including means (32) for generating a charging current proportional to the difference between A*V OUT and B*V IN ; and means responsive to the charging current for generating the ramp signal having a slope selected according to the particular type of DC/DC converter. The circuit of claim 13, wherein the means for generating the proportional charging current is a voltage controlled current source (32). The circuit of claim 13, wherein the means responsive to the current includes a capacitive element (C RAMP ) having a value which is a function of R s , and L. The circuit of claim 13 wherein the means for generating a current is comprised of: a first transistor means (Q1) wherein the base of the first transistor means is connected to one of the means for dividing, the emitter of the first transistor means is biased to a first potential, and the collector is connected to a second potential such that the emitter base junction of the first transistor means is forward biased and the collector base junction is reverse biased; and a second transistor means (Q2) having at least two collectors wherein the first collector of the second transistor means is connected to its base, the emitter of the second transistor means is connected to the emitter of the first transistor means, and the second collector of the second transistor means is connected to the other means for dividing via a scaling resistor (R SCALE ) and the second collector of the second transistor means provides the proportional current to the means responsive to the current for generating the ramp signal. The circuit of Claim 13, wherein the means for generating a current is comprised of: a first transistor means (Q3) wherein the base of the first transistor is connected to the means for dividing which is connected to the input voltage, and the collector of the first transistor is connected to the input voltage; and a second transistor means (Q4) having at least two collectors, the first collector of the second transistor means is connected to its base and to the first transistor emitter, the emitter of the second transistor means is connected to the other means for dividing which is connected to the output voltage via a scaling resistor, the other divider is selected so that the output voltage is unchanged, and the second collector provides the proportional current to the means responsive to the current for generating the ramp signal. The circuit of Claim 17, wherein: the emitter of the second transistor means is connected to the output voltage through a scaling resistor (R SCALE ).

Inventors: SZEPESI TAMAS S, SZEPESI, TAMAS S.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1990
Main classification: H02M3
IPC codes: H02M3, H03K4