STAR-WIRED RING LAN

Abstract: A hybrid star LAN has an access unit (1) with a port (30) associated with each terminal (2), the port comprising a port input (8) and output (9). A terminal link (3S, 3R) links the terminal to the port. A bypass link (11) is in parallel with the terminal link, and the time delays of the terminal link and the bypass link are matched by appropriate registers (11, 13). A comparator (14) compares the outputs of the terminal and bypass links to detect errors through the terminal link and controls a selector switch (12). On the LAN, channels are constituted by varying numbers of TDM slots, as defined by a template stored in the access unit. Each terminal stores that part of the template which defines channels which it can use. Each terminal can also store a second or background template which can be swapped in for the current or foreground template when a change of allocation is desired.

Description: STAR-WIRED RING LAN BACKGROUND OF THE INVENTION This invention relates to data transfer networks, especially lo>al area networks (LANs), -and is concerned particularly, but not exclusively, with integrated voice -and data LANs - IVD LANs. Many different types of LANs exist or have been proposed, .and many have been standardised under the aegis of IEEE committee 802. LANs typically- comprise a'number of terminals linked by one of a number of network .arrangements, including point-to-point, ring and bus networks. Each of these geometries has its advantages and drawbacks however. In the proposed IEEE 802.9 star LAN, connected using point-to- point wiring, each terminal (TE) is linked directly to a port of a multi-port access unit AU .and each TE functions substanti-ally independently. This .arrangement is particularly advantageous in terms of fault or error handling. Each TE link is independent and so failure of one does not affect the remainder of the LAN. It is disadvantageous however in that a large amount of hardware is required within the AU. In order to permit ccπirπunication between independent TEs in a fr-a ed time division multiplex (TEM) system the data transfer.to and from each has to be controlled and brought into •alignment. In a point to point LAN this requires as many parallel sets of data-handling hardware as there are TEs -and so is expensive. In ring and bus based IANs all the TEs and any ring or bus master are linked by a single loop or bus. Any master unit therefore requires only one port input and one port output. Various forms of ring and bus LANs exist. For example token rings ■allow only one TE to write data into the ring at a time, which data then circulates the ring and is read by the addressed TE. Only a TE holding the token is permitted to write data, after which the token is passed on around the ring. Much less hardware is required overall in this case than in a multi-port point-to-point star LAN, even though repeater units .are required to repeat the signal at intervals-..around the ring. The propos»sd 802.9 point- to-point star-wired LAN requires approximately double the higher level hardware (e.g. multiplexers, channel and packet hardware) since an instance of this hardware is needed at both ends of each point to point link. A ring or bus network therefore costs less than an equivalent point-to-point network, but leads to serious dis-advantages regarding error or fault tolerance. In a ring, if one terminal or link f»ails, then unlike a point-to-point star the whole LAN fails, affecting all the TEs, and the LAN has to be reconfigured. A star-^wired LAN may be implemented as a hybrid between a point-to-point and a ring LAN. As in a ring LAN all TEs are linked in a continuous loop extending from an access unit (AU) output back to an AU input but the loop also returns to the AU between each pair of TEs. This means that the AU requires less hardware than for a point-to-point LAN since data signals are transmitted around a ring linked to all TEs. Cost is th»srefore low. A hybrid star LAN can also have s ne of the fault tolerance of a point-to-point LAN. If a single terminal or the link to it f-ails, then it may be bypassed within the AD with a simple link to replace the TE. Con-tinuity of the star is thus maintained. It is known to do this in hybrid token star-rings. However, such replacement of a TE may require reconfiguration of the LAN to allow for the changed delay in the star. SUMMARY OF THE INVENTION The invention is defined in the .appended claims to which reference should now be made. In a first aspect the invention relates to hybrid star networks and provides a data transfer network comprising an access unit having a port for a terminal, the port comprising a port input -and a port output for respectively sending signals to -and receiving signals from the terminal, the terminal being linked to the access unit by data transmission means forming a terminal link extending from the port input via a send data line to the terminal and f om the terminal via a receive data line back to the port output, a bypass link between the port input and the port output in parallel with the terminal link, and a switch means for routing data to the terminal port output via either the terminal link or the bypass link, in which the time delays between the port input .and the port output via the terminal link and via the bypass link .are matched. Provision of a bypass link of the same delay time as the corresponding TE link in a hybrid star network considerably enhances fault or error tolerance, since a faulty TE link can be bypassed by means of the switch without any effect on the configuration of the rest of the LAN. The timing of the LAN does not change and all other TEs are unaffected. The bypass link preferably has a fixed time delay which may be the same for all terminals, and the terminal link preferably comprises an adjustable time delay element for matching to this fixed delay. If the adjustable delay element, which may be a FIFO with an adjustable fill level, is controlled by the AU, the delays of the TE link .and its bypass may be mat-died automatically. In a preferred eπtxxiiment the AU comprises an initialisation controller at the port to erøble automatic matching of the delay elements to be carried out. Although the switch means could act at the port input it is much preferred that it shall act on the port output side. According to the invention the data transfer network preferably further comprises a control means responsive to a comparator for controlling the switch means. Data from the port input enters both the terminal link and the bypass link and the comparator compares the data signals after transmission along each link. The addition of a comparator can enhance the f ult or error tolerance of the hybrid star LAN. Within the AU, at each TE link the incoming data signal is fed to both the TE link -and its bypass link. The signals are compared before they reach the switch at the port output, whence they pass on to the remainder of the star, and the switch is controlled accordingly. The bypass link is highly unlikely to introduce any errors into the data and so its output may be considered error free. If the TE has no access to write data into the network and no errors have occurred, a signal returning to the AU from the TE link should be the s«ame as that in the bypass .and thus a comparison should show no differences. •The control means responsive to the comparator can thus count the bit error rate (BER) of its TE link. - ■ It can therefore identify certain error or fault conditions (such as disconnection or non-operation of the TE) -and act accordingly. At some threshold BER the control means may for example permanently connect the bypass link. It will still scan the TE link signal however, and if the TE recommences correct operation, the control means can reconnect it automatically. • The cαπparator may in a preferred embodiment compare the signals in the TE loop and bypass link at a small time delay before those signals reach the switch controlled by the comparator. This would allow more relaxed timing for the control of the switch. The AU may advantageously be implemented for a plurality of TEs using a single VLSI device. In this case the delay elements, the shift register and the FIFO, would require significant areas of the device .and so the time delays required would be advantag-aously reduced as far as possible. A 4-αctet delay for each bypass link should be sufficient to allow for the maximum transmission time via a terminal link in a typical LAN. The FIFO should be long enough to allow for the -maximum variation in TE link delays of the LAN. A greater number of AU ports for connection to TEs could then be implemented,on a single VLSI device. If a small delay time at each port is used however, then the total time of transit of a physical frame (PF) around all the ports in the LAN may be shorter than the length of each PF. To maintain PF ali»gnmeπt, the data transit time around the LAN must be equal to the length of a PF. A further separate shift register may therefore be inserted into the ring of the LAN in order to increase the total data transmission time around the LAN. Further, the TEs required by the LAN of the invention may be so design»ad that they .are no different frcm those required for point to point LANs currently under consideration by TKKF, 802. Each TE communicates directly only with the AU and is independent of all other TEs. For each TE therefore, the LAN of the invention appears identical to a point to point LAN. The invention also provides a system of data transmission which is particularly advantageous when used in combination with the network described above. This data transmission system is bas-ed on the known transmission system of time division multiplexed physical frames (PF) . These are blocks of data of fixed length and defined structure which in existing systems are generated by a PF Generator (PFG) within the AU, .are passed around the network and recovered and terminated in the AU by a PF Aligner (PFA) and an associated PF store (PFS) . If however a LAN has a fixed delay time for a complete circuit, in particular a delay which is an integral multiple of the frame period, then there is no requirement for a PFA and a PFS to maintain alignment of a recovered PF with a subsequent g-anerated PF. However, a PFA may still be required to align PFs in a LAN with PFs in a second IVD-LAN or other transmission system such as an ISDN. Two or more LANs working on compatible systems (for example ISDN systems) may be linked, but PFs sent from one to the other will not necessarily be aligned. A PFA and an associated PF Store (PFS) will therefore be required. It should be noted that only one PFG, PFA and PFS are therefore required in an AU using the hybrid star-wired LAN of the invention. An equivalent point-to-point star-wired LAN using PFs would require a PFG, a PFA and a PFS for each TE and would therefore be considerably more costly. The organisation of each Physical Frame (PF) comprises a number of heirarchical layers. In the lowest physical layer, information bits and a clock are transferred. On the next hicjher heirarchical layer, the information within the PF is subdivided into a number of TCM slots, each typically comprising an octet of 8 bits. The slots may then be group-ed in a higher layer into a series of channels. Each channel may contain .any number of slots .and therefore be of any data capacity. In any TCM network it is necessary to manage allocation of these slots and channels to network devices. This is conventionally done on a call-by-call basis by including slot allocation data in one or more slots of each frame, referred to as the D channel in ISDN telephony. In a conventional system a management unit which in a LAN may be the AU or one of the terminals, supervises slot allocation and hence the data in the D channel, by means of which the terminals are granted access to slots. It is frequently necessary to utilize channels composed of more than one time slot. Thus in an IVD LAN and using τ ~~ ^- 802.9 terminology^ , in addition to single slot channels for voice or data (B channels) there may be e.g. six or twelve slot channels for video (C channels) which can be allocated to devices on a call-by-call basis and a broadband packet channel (P channel) that takes up all otherwise unallocated slots. Various proposals have been made to detail the manner in which allocation of slots to channels should be managed. In the PAC point to point LAN scheme as proposed to IEEE 802.9, there is a semi-permanent (i.e. not call-by-call) allocation of slots to channels controlled by slot -allocation data carried within each frame. This provides s ne flexibility because the allocation can be changed frcm frame to frame to meet changing demands, in particular by adjusting the size of the C channel allocation relative to the size of the P channel allocation. The D channel and a PF boundary control octet then control the apportionment of these slots to P and C channels. One disadvantage of this system is its susceptibility to transmission errors since it relies upon channel allocation data carried by each frame. Furthermore the rigid slot to channel relationship is rather inflexible. The present inventor has proposed a more flexible and robust system to IEEE 802.9 whereby the slot to channel allocation is maintained within a template stored at each network device. Since it is stored, this allocation is substantially una fected by transmission errors. In order to .allow the template to be updated to adapt to changing d-amands, each device stores not only an active template but a background template which can be changed by data sent over the LAN to all devices by the access unit. A protocol operating on a bit in the framing time slot used as a "swap" flag may then be used to cause all devices to swap over the stored active and background templates, thus bringing a new active template into operation. This mechanism ensures that all devices always use the s»ame template; disaster is more or less inevitable if they do not. The stored templates avoid the risks inherent in continual transmission of slot to channel allocation by the access unit. It is a further object f the invention to reduce as far as possible the processing that each TE is required to perform .and to reduce the storage required at each TE. This reduces the total cost of a LAN and reduces any TE modification required to connect a TE to a LAN. Accordingly the invention further provides in a further aspect a data transfer network oαπprising a plurality of terminals and a multipart access unit connected via a data transmission ring, and communicating with each other via channels constituted by varying numbers of time division multiplexed slots, wherein each terminal comprises means for storing indefinitely at least the part of a template relevant thereto, and the access unit comprises means for storing the entire template, which template allocates slots to channels and further allocates at least some channels to specific terminals. In conjunction with the hybrid star network system with bypass links described earlier, it will be seen that the use of this template system is advantageous. The template stored by the AU and controlling channel allocation of the PF contains information as to whether a terminal has access to write to any channel of the PF. The control means used in the AU to control the switch connecting either a TE link or its bypass link to the output port of that section of the LAN can then advantag»30usly use the template stored by the AU. Data corruption during transmission is most likely to occur in the TE link during transmission from an AU port to a TE and back. By contrast, the corresponding bypass link may be considered error free. Since the control means controlling the switch to connect either the TE link or the bypass link to the port output is responsive to the AU template, it may advantag-aously connect the error free bypass link to the port output as much as possible. It is only necessary to pass those slots of a PF to which a TE has write access from the TE link to the port output. All other slots may be passed to the port output via the bypass link. The control πeans may thus use data from the AU template, which defines those slots of a PF to which a TE has write access, to control the switch accordingly. In this way, errors introduced in a TE link may be substanti.ally removed from the signal passed rom that TE port on around the LAN. Further error resilience is provided by the coπparator. By cαrparing data in the TE link and bypass link near the port output in TEM slots to which the TE has no write access, and assuming that the bypass link is error free, the switch control means in response to the coπparator may determine the bit error rate (BER) introduced by data corruption in transmission around the TE link. Using BER • threshold techniques the control means can thus identify certain categories of TE link faults and control the part output switch accordingly. Further, if the comparator detects signal corruption in the TE link of a channel to which that TE has read access, then it may assume that the corruption might have occurred before the signal reached the TE and thus that the TE may not have received the information correctly. The AU can then act accordingly. The combination of PFs, channel allocation and stored templates with autc atic terminal bypass links thus provides a system that is particularly robust and resilient in the face of both hard and soft line errors. In the prior art, a number of physical layer systems for heirarchical organisation of synchronous time division multiplexed physical frames have been employ»sd or proposed. In template based systems, the template comprises information allocating groups of slots in a PF to channels and identifying each channel by a channel number for exaπple. Each type of channel requires a certain number of slots to provide the required data transfer capacity. In an IVD-LAN as described here, channels may be designated for purposes including, for exaπple (following certain IEEE 802 proposals): Channel ID Channel Function F Framing P Packet transfer B Voice or Data (single slot) C Video Conference (six slot channel) D ISDN Signalling In an embodiment of the invention, the PFG generates PFs and 8kHz and operates at a data rate of 8.192 Mbps. Each PF then cont-ains 128 octet wide slots. In the a xDdiment a B channel for voice of data would then require one slot per PF, and a C channel for video 6 slot. It is preferable that a data rate of at least 4 Mbps is used in order to enable IVD networking of a number of terminals, although higher data rates such as 8 or 16 Mbps would be advantageous, allowing greater bandwidth and networking of a larger number of terminals. The teπplate scheme of the invention for dynamic channel allocation provides substantial resilience in the face of errors. The channel allocation for a PF is stored in the AU and at least the relevant part thereof is stored in each TE. The TEs therefore store information as to which slots in a PF each may use, and for what purpose. The stored active teπplate thereby determines channel allocation for all PFs until a new teπplate is brought into operation. This is achieved by a teπplate swap operation, as explained above. The background teπplate nay be determined before being brought into operation by the AU according to a higher level call re-quest mechanism in response to data sent to the AU by TEs requesting channel allocation changes according to their forthcoming r-e irements. The invention is not concerned with this higher level mechanism. The background teπplate is then transmitted around the LAN in PFs in a dedicated channel. In practice this channel may be only a single slot, and only a part of a teπplate may be transmitted in each PF. If the LAN bit rate is 8Mbps and the PF rate is 8kHz, then there are 128 slots per frame. If a single teπplate transfer slot is allocated in each PF, then 128 PFs will be required to transmit the full teπplate. The series of 128 PFs is termed a multiframe. Clearly the teπplate transmission channel may comprise two or more slots, in which case each multiframe will be proportionately shorter. As the multiframe is transmitted, the background template data may thus be received and stored by each TE. In a preferred embodiment, to reduce the storage capacity required at the TEs, each TE may store only those sections of the teπplate relevant to itself, that is the channel numbers of, and the slots -allocated to, those channels to which it has access. It should be noted that the teπplate stored at the AU and at each TE may not then be of the same form. The filtering of the AU teπplate information required to achieve this may be performed either at the AU or at the TE. A number of schemes are possible for reducing the memory and TE processing capability required to store templates at TEs. For exaπple, if all the slots of a teπplate are stored in a TE, it is not necessary to store slot numbers. These are determined unambiguously by memory location. Furthermore TE identifiers for unshared channels may not be stored. If a TE only needs to store the tenplate information relevant to itself, these TE identifiers may be replaced by 'me/not me' bits. If only a partial teπplate is stored, then slot numbers may be stored as well as channel numbers. Only the teπplate information for those slots to which the TE has access need then be stored and so neither TE numbers nor 'me/not me' bits need be stored. Only a set of the relevant matched slot and channel numbers need be stored. In this way, from a multiframe sequence of PFs, ea-h TE can acquire appropriate definitions of a background teπplate, which is to become the new active teπplate, by use of a dedicated teπplate transfer channel of a relatively small data capacity. The useful information carrying data capacity of the LAN is thus maximised. When required, the background teπplate is then swapped with the active teπplate. This may only require each TE to read a swap control bit at the beginning of the first PF to initiate use of the new teπplate as each TE would already contain the new teπplate in meπiory, having read it as the back-ground template in previous PFs. More sophisticated signalling of a swap may be used however to reduce the chance of errors. In this way, a new teπplate may be iπpl-amsnted rapidly and transparently, providing in a single multiframe operation a new teπplate at all TEs. Using this scheme, tenplate information for the control of time division multiplexing of slots within physical frames can be transmitted to TEs of a LAN with a very high level of integrity and entirely within the physi-al layer. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described by way of example with reference to the accαnpanying drawings in which; Figure 1 is a schematic diagram of a hybrid star-wired LAN; Figure 2 is a schematic diagram of a terminal and its bypass link and associated control system; Figure 2A is a schematic diagram of the initialisation control of an AU port; Figure 3 shows the structure of a single empty physical frame; Figure 4 shows the position of the physical sub-layer within an OSI layer heirarchy; Figure 5 is a schematic diagram of a LAN interface of a terminal; .and Figure 6 shows an exaπple of the time division multiplexing of the slots of a PF into channels and the corresponding teπplate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Bypass link system An embodiment of a LAN according to the invention constitutes an iπplementation of the channel multiplexer and physical framing sub-layer of layer 1 of the OSI model, as illustrated in Figure 4. It coπprises a multi-port access unit (AU) 1 and eight IVD terminals 2, denoted TEO to TE7 and each connected to its own port, Figure 1. However, the number of terminals in such a LAN may clearly be more or less than eight. The AU 1 and the terminals 2 are linked by a hybrid star network 3. The network thus forms a continuous ring, but the ring returns via the AU betw-sen each TE to form a hybrid star. The AU 1 comprises a physical frame generator (PFG) 5 for injecting the physical frame structure and a physical frame aligner (PFA) 6 for effecting frame ali-gnment with an external ISDN link 4 and acting as a bridge between the LAN and the ISDN link. In the embodiment, the time taken for a PF to pass around the star is 125 microseconds, and the PFs are generated at a frequency of 8 kHz. The data transfer speed is 8.192 Mbps. The PFs thus each contain 1024 bits, corresponding to 128 octet-wide TCM slots. The delay per terminal may be only 4 octets, or 32 octets for all eight terminals. A shift register delay 7 (whose position in the loop is arbitrary) is included to make up the total delay of 128 octets. Other delays per terminal may be used. In general the smallest feasible value should be selected. The shift register delay 7 realigns each PF received at the AU to the same phase as the next transmitted PF. Each terminal 2 of the LAN is connected to the AU 1 by TTP (telephone twisted pair) cables 3 or optical fibres. A 'send' data line 3S (Fig.2) extends to the terminal 2 from a port input 8 in the AU 1. A 'receive' data line 3R returns from the terminal and can be connected to a port output 9 by a switch 12. Each port 30 is provided with a parallel bypass link extending from the port input 8 and throuigh a shift register 11 whose output can be connected to the port output 9 by the switch 12. When a signal is -transmitted around the ring it enters the section of the network shown in Figure 2 at the port input 8. It is then split into two and passes via the send line 3S to the IVD terminal 2 and also along the bypass link directly into the shift register 11. The signal sent to the IVD terminal 2 returns to the AU 1 via the receive line 3R and enters a FIFO variable length buffer 13. Either the signal output frcm the FIFO (FO) or the signal output from the shift register (SO) may then be connected by means of the switch 12 to the port output 9 to be transmitted from this section of the network on around the ring 3. The way in which the switch 12 is controlled is explained below. The data transmission times throu-gh the IVD terminal link and through the bypass are equal. The transmission time around the network is set first by the lengths - which .are preferably equal - of the bypass shift registers 11 on each port of the AU. These may be say 4 octets, i.e. 4 slots each and the delay 7 (Fig. 1) has a delay of 128 - ( 8) = 96 slots. Alternatively, for an AU with eiφt ports using frames of 128 octet-wide slots for data, the delay evenly divided at each port will be 16 slots. The bypass shift registers 11 must then provide this delay and the delay 7 is not necessary. There will be a delay in transmitting the PF from the send line 3S around the IVD terminal loop to the receive line 3R, depending on the type of line code encoder/decoder used, the line propagation delay, and the delay within the IVD terminal itself. The total delay can then be matched to the 4 or 16 slots delay of the bypass shift register 11 by adjustment of the FIFO elastic buffer 13 which is an asynchronous fall-through FIFO with clocked output. Such a FIFO automatically re-establishes bit synchronisation of the signal at its output while being tolerant of jitter on its input. The FIFO 13 is set during an initialisation mode of a port. This mode is controlled by an initialiser 15 (shown in detail in Figure 2A) which may be shared by a plurality of ports. The initialiser 15 sends an initialisation mode flag (IM) to a port to start initialisation of that port. In the initialising mode the port switch 16 directs "Idle" slots (A5 hex) from the initialiser 15 out to the IVD-TE, except at framing slot (slot 0) time when a framing pattern (D8 hex) is sent. The 'idle' and 'framing' patterns are chosen so that misalignment by any number of bits is detectable and identifiable. When the framing pattern is detected at the input to the FIFO 13 by framing detector 40, the '.and' gate 41 outputs a clear (CLR) signal to clear the FIFO 13 to an empty state. The 'idle' slots following the framing slot then progressively fill the FIFO 13 since the FIFO output clock is disabled (edge reset) when the initialisation mode is entered. The FIFO output (FO) is not clocked until the framing slot (slot 0) is clocked out of the shift register 11 and detected by framing detector 42. The framing detector 42 output then operates a latch 43 via a gate 44 to re-enable the FIFO output clock via gate 45. Clock pulses (CLK) are then passed to the FIFO 13 to clock data FO out of the FIFO 13 in synchronisation with the shift register output SO. The detector 42 may be replaced by a counter which counts off the known number of clock pulses corresponding to the delay of the shift register 11. In a preferred embodiment, a more rigorous test for synchronisation may be employed, which verifies that 3 consecutive framing patterns are correctly received at the input to the FIFO 13 (FI) at the correct times, one PF apart, before the port is considered to have been properly initialised. The outputs from the IVD terminal link and the bypass link are then synchronised so that signals from either may be transmitted on around the network via the switch 12 with identical delays. The switching by the switch 12 of either the signal SO or the signal 'FO to the port output 9 is performed tinder the control of the port control 17 which is sensitive to the template 18 and to a comparator 14 which compares the signals FO and SO. 2. Template System The operation of the switch 12 is related to the structure of the transmitted data, which will be considered before reverting to description of operation of the control 17 etc. In the embodiment, the data is transmitted as a series of 125 microsecond physical frames generated at 8 kHz. With a bit rate of 8.192 Mbps each PF contains 128 byte-wide slots. A typical arrangement of a PF is shown in Figure 3. The first two slots are required to contain framing and ∞ntrel/status information, essentially in accordance with conventional TDM practice. The t-hird and fourth slots contain at least a portion of a teπplate, for updating the background template. The teπplate describes both the channel to slot association and also the terminals which may use each channel. It also identifies any unused channels, and defines overhead channels such as framing control, states and teπplate channels. In an alternative exaπple, the first three slots contain framing and control/status inforπation, and the fourth slot contains a portion of the template. The allocation of slots to carry framing, control, status and template updating information may vary according to the requirements of a given LAN. In particular the teπplate channel, allocated one or two slots per PF as described above, may cαπprise more slots especially if the LAN comprises a large number of TEs. As described below, a single slot channel and 128 PF multiframes are adequate far the 8 TE LAN of the embodiment but in a larger LAN, the inforπetion required in a full template will be greater and correspondingly a wider teπplate update transmission channel or longer multiframes would be required. A full template defines for each slot of a PF the channel to which that slot is allocated and the TEs which may write to that slot. A channel may cαπprise a number of slots depending on the data transfer capacity required. In the LAN of the embodiment for example, several types of channel may be allocated to TEs. According to IEEE 802.9 proposals these may include: Channel Channel Channel No.slots Number Type Function required 0 P Packet Traffic * 1 D TE specific ISDN 64kbps signalling 1 2 B Voice channel 1 3 B BRI - Rate Adapted Data 1 4 B Other X.25 channel 1 5 C Video Conference 1 6 6 C Video Conference 2 6 7 S Spare Channel *A11 slots otherwise unallocated In addition, shared channels can be supported. These are shared between two TEs and either TE may write to or read from that channel at any time. Since a PF always travels in the same direction around the ring of the LAN, two-way communication, such as a voice link for -example, may thus be effected in a single channel which may be a single slot. In the embodiment, each PF contains 128 byte-wide slots. Each slot may be allocated a channel number and a TE number. Since there are 8 TEs and 8 channel numbers, 6 bits are required to describe a TE and a channel type for each slot. If one slot per PF is used to transmit teπplate information then, as described below, each PF may carry the tenplate information for 1 slot. 128 PFs are therefore required to transmit a full teπplate, which takes 16 ms. These multi-frames comprising 1288 kHz PFs, repeating 64 times per second, may be flagged in the control/status slot. Alternatively they may be flagged by, for exaπple, inverting the framing pattern at the end of each multiframe. A full teπplate may thus be transferred in a multiframe entirely within the physical layer. An exaπple of a teπplate transmission and storage system will now be described. In the embodiment, a one slot channel in each PF is dedicated to teπplate transmission. A multiframe of 128 frames is therefore required to transmit a complete background teπplate, but the bandwidth remaiiiing for data transmission is maximised. Eiφt bits are therefore available for teπplate transmission in each PF. Since sequential PFs can describe sequential teπplate slots it is unnecessary to transmit the slot number as long as the first PF of each multiframe is identified. Each PF can therefore carry 8 bits of template data to describe one slot. In the ai±xx__Liment, three bits indicate by number the TE which owns the slot. A further two bits indicate an ownership descriptor which is coded as follows: Bit 6 Bit 7 0 0 Shared P channel slot 0 1 Slot uniquely allocated to one TE. 1 0 Slot is shared by 2 TEs on this AU. 1 1 Framing, Control, Status, Template slot. T ■ he use of the remaining three bits depends on the ownership descriptor. If the slot forms part of a channel shared with a second TE, then these three bits indicate the number of that TE. If the slot is a part of a channel uniquely owned by the TE described in the first three bits, then the remaining three bits are used to indicate the number of the channel the slot belongs to. When a teπplate is transmitted by the AU, the relevant parts of it must be stored in each TE. In order to reduce the memory requirement, a filtered or reduced form of the teπplate is stored at each TE. The only teπplate information each TE requires is a definition of the channels to which it may write data or read data. It is only the AU which is required to store a complete teπplate. The filtering of the teπplate for each TE may be performed at the TE itself but is preferably performed at the AU by the teπplate update processor 19 and the port control 17 so that only the required teπplate data is t_ a_nsmitted to each TE. The processing capability required of each TE is thus reduced. It should be noted that the stored form of the teπplate at each TE and at the AU will be different. A simple exaπple of a full teπplate will now be described (Fig. 6), in which the following channels are allocated: IVD-IE 0 has a conventional 2B + D BRI-ISDN organisation. TVD-TE 1 has B + C + D channels IVD-TE 7 has two B channels • Thirteen slots are required to allocate these channels. For exaπple, slots 0-3 always carry control and teπplate information and so slots 4-6 may carry two B channels and a D channel for TE 0, slots 7 and 8 may carry a B and a D channel for TE 1, slots 9-14 may carry a C channel for TE 1 and slots 15 and 16 may carry two B channels for TE 7. The remaining 108 slots will be for packet transfer and accessible at any time by any TE, in accordance with known request/grant .and priority arbitration procedures. With the teπplate system it is thus easily possible to provide certain TEs with dedicated or at least semi-permanent channels of any type while designating other slots of each PF for general packet use by any TE on the LAN. It is also possible to provide TEs with further channels on request. For exaπple, if an IVD-TE requests a voice channel for a certain period, then it can be allocated one by the AU via a new teπplate as long as sufficient data transfer capacity is available. 3. Comparator operation During operation of the network with a TDM transfer system described by such a teπplate therefore, and when in addition a coπparator 14 compares signals SO and FO from a TE link and its bypass link, a considerable degree of error checking can be performed. Since it can be assumed that the data signal SO is error free, then any errors which arise during the passage of the signal around the IVD terminal loop can be detected by comparison in cαπparator 14 of FO with SO, providing that the data has not been changed by the IVD terminal by a 'write' operation. It should be noted however that such writing will be infrequent and so most data passed on around the LAN will pass throuφ the bypass link with .associated low bit error rates. At the AU, the foreground teπplate completely identifies those slots which each IVD terminal has the right to modify by writing to them. This information can then be combined with that from the cαπparator 14 in order to control the switch 12 via the port control 17 so that only the data in the slots allocated to the IVD terminal on that port for writing are switched throu-gh to the next port, the remainder of the slots being switched through from SO. This -ensures that 'error-free' data from- the bypass shift register is passed on as much as possible. In practice, although a TE receives each PF, unless the TE has write access to a slot then all slots passed on by its AU port to the next AU port will have been carried by the bypass link. Therefore the signals received by each TE, wherever a TE is placed in the LAN, will have been carried around the IAN in substantially error free bypass links. This is particularly true for the error- sensitive framing and control/status slots. Using this system each IVD terminal on the LAN is therefore substantially isolated from the effects of any corrupt links to other IVD terminals or of faults in other terminals. Since the number of bit errors at each port can be detected by the comparators, the LAN of the embodiment also -allows faults resulting in unacceptably high bit error rates to be recognised and appropriate action to be taken automatically. For exaπple if seme level of bit error rate (BER) is considered unacceptable and is exceeded, the appropriate bypass link can be permanently connected into the network to shut down the corrupted TE loop -and to avoid any risk of disruption to other terminals. In such a shut down condition the PF signal is still however sent to the IVD terminal and the comparator can still operate. In addition, BER thresholding techniques can distinguish various conditions such as disconnection or switching off of the IVD terminal. If either of these occur for exaπple, the coπparator can determine reconnection or switching on .and thus reconnect the IVD terminal link automatically. Thus the port control means 17 responds to the AU foreground teπplate 18 to select SO via the switcii 12 in all slots to which the TE 2 does not have write access. Normally the switch 12 selects FO in slots to which the TE2 does have write access but the control means 17 will respond to certain error states signalled by the comparator 14 to select SO permanently. When the TE link is reconnected it will be. necessary to reinitialise the port. While the bypass link is permanently linked into the network, the AU port is in an initialisation state and attempts to reinitialise itself by notching the TE link delay to the bypass link delay as described earlier. When the TE is reconnected or any TE link fault is corrected, the AU port will reinitialise automatically and transparently, thus reconnecting the TE to the LAN with no disruption at all to any other part of the LAN. 4. Terminal template storage and data control system An embodiment of the teπplate storage and data control system of a TE is shown in Figure 5. The data is input to the TE via an input line from the send line 3S of the network. Initially the Physical Frame Synchroniser (PFS) 26 locates slot 0 and aligns the timing of the TE with the incoming PF at the input. When synchronised, the PFS enables normal TE Control .and Status Logic 21, which controls all aspects of physical layer logic according to data received in PF slots 1 and 2, the control and status slots. Subsequently all user data for the TE in each PF is demultiplexed by a demultiplexer 20 and the framing, control, status, and data for other TEs are routed directly through the repeat and loop logic 27 by the control unit 21 to the AU receive line 3R. The data bits 0-3 carried in the slot 3 dedicated to teπplate information, and conteining a channel number and a 'me/not me' bit, .are sent to a background teπplate store 25. Each PF carries a portion of a template, and so a succession of PFs making up a multiframe allows a whole teπplate to be built up in the background teπplate store 25. The teπplate so formed is a background teπplate which may be brought into the foreground by a teπplate swap command carried by one or more control slots in subsequent PFs. The template store 22 stores the foreground teπplate which is used by the control unit 21 to determine to which slots of each PF the TE may write. The TE itself may read and write data received and sent from its data control system via the octet-wide data channels 23 under the direction of the foreground template in template store 22. The data received -and sent are timed by the control logic 21 respectively through a PF slot demultiplexer 20.and a PF slot multiplexer 24. The repeat and loop logic 27 passes control slots .and user slots not allocated to the TE directly from the input line 3S to the output line 3R for return to the AU.

Claims: CLAIMS : 1. A data transfer network, comprising: an access unit having a port for a terminal, the port comprising a port input and a port output for respectively sending signals to and receiving signals from the terminal; data transmission means forming a terminal link extending from the port input via a send data line to the terminal and from the terminal via a receive data line back to the port output; a bypass link between the port input and the port output in parallel with the terminal link; and switch means for routing data to the terminal port output via either the terminal link or the bypass link, the time delays between the port input and the port output via the terminal link and via the bypass link respectively being matched. 2. A data transfer network according to claim 1, in which the bypass link has a fixed time delay and the terminal link comprises an adjustable time delay element for matching to the fixed time delay. 3. A data transfer network according to claim 1, wherein the data transmission means forms a closed loop extending from and back to the access unit via a plurality of terminal links, each with its associated bypass link. 4. A data transfer network according to claim 2, wherein the data transmission means forms a closed loop extending from and back to the access unit via a plurality of terminal links, each with its associated bypass link. 5. A data transfer network according to claim 4, wherein all bypass lϊ-nks have the same time delay. 6. A data transfer network according to claim 4, wherein data transmission is effected by physical frames with a predetermined frame period and the total time delay of the closed loop extending from and back to the access unit via the plurality of fixed time delay bypass links is equal to the predetermined frame period. 7. A data transfer network according to claim 6, wherein the time delay of each bypass link is equal to the frame period divided by the total number of the plurality of terminal links. 8. A data transfer network according to claim 6 in which the total delay of the plurality of bypass links in the closed loop extending from and back to the access unit is less than the predetermined frame period, and including a further delay element in the closed loop such that the total loop delay is equal to the predetermined frame period. 9. A data transfer network according to claim 1, in which the switch means selectively connects either the output of the terminal link or the output of the bypass link to the terminal port output. 10. A data transfer network according to claim 8, in which data from the port input is passed to both the terminal link and the bypass link, and comprising a comparator to compare the data signals after transmission via the terminal link and via the bypass link respectively, and switch control means responsive to the comparator to control the switch means. 11. A data transfer network according to claim 10, in which the data signals in each data link are compared by the comparator at some time delay before the switch means. 12. A data transfer network according to claim 10, wherein the switch control means is forced to connect the output of the terminal link to the terminal port output when the terminal may be writing data to the network and to connect the output of the bypass link to the terminal port output when the terminal may not be writing data to the network. 13. A data transfer network according to claim 10, including monitoring means coupled to the output of the comparison means to monitor discrepancies detected by the comparison means between the outputs of the transmission and bypass links. 14. A data transfer network, comprising: an access unit having a port for a terminal, the port comprising a port input and a port output for respectively sending signals to and receiving signals from the terminal; data transmission means forming a terminal link extending between the port and the terminal to provide two-way communication between the port -and the terminal; a bypass link between the port input and the port output in parallel with the terminal link; means for passing data from the port input both to the terminal link and to the bypass link; switch means for selectively connecting either the output of the terminal link or the output of the bypass link to the terminal port output; and comparison means for comparing the data signals after transmission via the terminal link and via the bypass link respectively. 15. . A data transfer network according to claim 14, including switch control means responsive to the output of the comparison means to control the switch means. 16. A data transfer network according to claim 14, including monitoring means coupled to the output of the comparison means to monitor discrepancies detected by the comparison means between the outputs of the transmission and bypass links. 17. A data transfer network comprising: an access unit having at least one terminal port for a terminal, and means for controlling communication on the network in time division multiplexed slots and for allocating to the terminal slots in which it may write data, the terminal port comprising a port input and a port output for respectively sending signals to and receiving signals from the terminal; and wherein the or each port comprises: data transmission means forming a terminal link extending from the port input via a send data line to the terminal and from the terminal via a receive data line to the port output; a bypass link coupled to the port input and having a transmission time delay matching that of the terminal link; switch means coupled between the receive data line and the output of the bypass link as inputs, and the port output; and control means causing the switch means to couple the output of the bypass link to the port output in place of the receive data line in slots in which the terminal may not write data. 18. A data transfer network according to claim 17, further comprising a comparator connected to the receive data line and to the bypass link for detecting discrepancies between data transferred via the terminal link and via the bypass link, and wherein the control means is further responsive to the comparator to cause the switch to connect the output of the bypass link to the port output in all slots in at least one error condition identified by the said discrepancies. 19. A data transfer network comprising: a multiport access unit; a plurality of terminals connected with the access unit via a data transmission ring, the ring providing a plurality of time division multiplexed slots; means at the access unit for defining and storing a template which allocates varying numbers of slots to channels for use by the terminals and which further allocates at least some such channels to specific ones of the terminals; and means at each terminal for storing indefinitely at least a part of the template which is relevant to that terminal. 20. A data transfer network according to claim 19, in which the access unit transmits to each terminal only the part of a transmitted template relevant thereto. 21. A data transfer network according to claim 19, wherein each terminal stores only that part of the template relating to channels assigned to itself or designated as generally available. 22. A data transfer network according to claim 19 wherein each terminal stores both an active template or part template and a background template or part template which may be modified in response to updating data transmitted round the network, and comprises means responsive to a predetermined signal protocol to swap the active and background templates or part templates, wherein the updating data is carried in a dedicated one of the said channels. 23. A ultiport access unit for a hybrid star LAN, comprising: a plurality of ports each for connection to a data send line and a data receive line to provide two-way communication with corresponding terminal equipments, the ports being coupled together in series with the port output of one port being connected to the port input of the next port, whereby the access unit and terminals form a data transmission ring; and wherein each port comprises: a bypass link including a first port delay means; means coupling the port input to the data send line and to the bypass link; means connected to the port output and comprising selector means having a first input coupled to the bypass link and a second input, for selectively connecting its first and second inputs to the port output, and a second port delay means coupling the data receive line to the second input of the selector means; and comparison means coupled to the outputs of the first and second port delay means to detect discrepancies between the outputs of the first and second port delay means. 24. A terminal station for a data transfer network, comprising: an input and an output for connection to a two-way data transmission link; terminal equipment receive and send means for two-way communication with associated terminal equipment; a demultiplexer coupled between the input and the terminal equipment receive means; a multiplexer coupled between the terminal equipment send means and the output; first template store means for storing a first template relevant to that terminal and defining channels available to that terminal and slots allocated to those channels; second template store means for storing a second template for future use by the terminal; and control means coupled at least to the input, the demultiplexer and multiplexer, and the first and second store means and adapted: (a) to load templates into the template store means; (b) to control the demultiplexer and multiplexer in accordance with the first template stored in the first template store means; and (c) in response to a received command to swap the control of the demultiplexer and multiplexer from the first template to the second template.

Inventors: BOAL JOHN HILL, BOAL, JOHN, HILL
Applicants: RACAL MILGO LTD, RACAL-MILGO LIMITED
Application year: 1990
Main classification: H04L12
IPC codes: H04L12