PLL speed control circuit

Abstract: The invention concerns with a PLL speed control circuit for controlling the speeds of two or more objects. It includes pulse generators for generating reference pulses, first counters for counting each of these reference pulses, encoders for detecting relative travelling distances of the objects, second counters for counting encoder pulses from the encoders, first subtracters for subtracting the outputs of the second counters from those of the first counters, second subtracters for subtracting the encoder pulses from the reference pulses, corrector sections for correcting the differences output by the first and the second subtracters, and adjusting sections for adjusting the movements of the objects based on the corrected differences.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) speed control circuit which serves to control two or more objects based on a predetermined speed ratio. 2. Description of the Related Art As an example, an electronic duplicating machine employing two or more document platforms requires the circuit for controlling two or more objects at a predetermined speed. This type of electronic duplicating machine is required to keep constant an optical distance from a document surface to a photosensitive drum irrespective of the scanning position. It, of course, includes a first mirror platform mounting a light source for radiating light on a document and a second mirror platform mounting a light mirror and a lens for guiding the light reflected from the document surface to the photosensitive drum. The former platform is adapted to be driven in the document-scanning direction at a speed twice as fast as the latter one. Traditionally, the travelling speeds of both platforms have been mechanically arranged to be a ratio of 2 to 1. That is, a wire-pulley mechanism has been used for the arrangement so that a rotary motor connected to the wire pulley is controlled to drive the first and the second mirror platforms at a ratio of 2 to 1. This wire-pulley mechanism disadvantageously cannot adapt to a high-speed-driven electronic duplicating machine, because the mechanism entails an elastic material, that is, a wire included in a transmission system for the driving force. In order to overcome this disadvantage, the newly-developed electronic duplicating machine has employed two linear motors. This type of duplicating machine includes two PLL speed control circuits. These circuits serve to control the two linear motors so that these motors can stably drive the first mirror platform at a speed twice as fast as the second mirror platform, respectively. The foregoing art is, however, designed to allow two PLL speed control circuits to respectively control the linear motors. It brings about the following disadvantage. That is, though the art is able to properly control the speeds of the linear motors, it does not offer an automatic modification function of any slippage caused about the positional relation between the first and the second mirror platforms, that is, an optical distance between the document surface and the photosensitive drum, which slippage results in shifting a duplicated image out of focusing. This is because these linear motors are individually arranged in speed and phase so that they disallow those platforms to return to their proper tracking positions even if they are shifted out of their locking ranges. It will be easily understood that this adverse effect increases more as time passes. The electronic duplicating machine employing two linear motors is, in essence, suitable for a high-speed-driven machine, but has the foregoing great disadvantage which becomes an obstacle of upgrading the performance of the electronic duplicating machine. JP-A-59-117 489 describes a synchronous rotation controller including two PLL-controller circuits for controlling the speed of two motors. Utilizing the known controller it is difficult to keep the synchronous rotation when an external torque is supplied to one of the motors. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a PLL speed control circuitd which is capable of controlling a first and a second objects at a predetermined speed ratio as well as driving these objects in synchronization. In carrying out the foregoing and other objects, a PLL speed control circuit is provided having the features of appended claim 1. In operation, at first, the circuit for controlling a speed of the object 10a (control section A for the first object) will be described with reference to Fig.1. The clock pulse generator 1 serves to output a clock pulse T to the reference pulse generator 2a at which the clock pulse T is divided at a dividing ratio matched to a desired speed of the object 10. The stroke position instruction section 3a serves to count the divided reference pulse T REFa . The counted digital value is assumed as data indicating a desired stroke position of the object 10a. The linear encoder 4a, on the other hand, serves to detect a relative travelling distance of the object 10a and supply the encoder pulse X FBa to the stroke position detecting section 5a in which the pulse X FBa is counted. The counted digital value is assumed as data to be a current stroke position of the object 10a. The position deviation deriving section 6a serves to subtract the data about the current stroke position from the data about the desired stroke position and then supply the resulting position-deviation digital value X 1ER . This digital value is assumed as data indicating the position deviation of the object 10. Further, the reference pulse T REFa and the encoder pulse X FBa are led to the phase-difference deriving section 7a in which a phase difference between both pulses is derived. The phase difference is supplied as a number of clock pulse T, which is supplied as data P 1ER to the phase-difference correcting section 8a in which the equation of 2πX 1ER + P 1ER (= P ERa ) is operated. Figs. 2a to 2c are timing charts showing T REFa , X FBa , and P ERa assumed when the position-deviation digital value X 1ER is 0, 1, or -1 respectively. As shown in Figs. 2a to 2c, the parentheses are given to indicate how the reference pulse T RE is phase-shifted from the encoder pulse X FBa for convenience and t denotes a pulse time width of the reference pulse T REFa . Fig. 2a shows the state in which the encoder pulse X FBa does not reach a point t based on the reference pulse T REFa . In this case, since the position deviation digital value X 1ER is zero, P ERa results in giving P ERa = 2π·0+P 1ER . Fig. 2b shows the state in which the encoder pulse X FBa reaches a point between t to 2t based on the reference pulse T REFa . In this case, since the position-deviation digital value X 1ER is one (1), P ERa results in giving P ERa = 2π·1+P 1ER . That is, P ERa is P 1ER plus 2π. Fig 2c shows the state in which the encoder pulse X FBa is delayed by t to 2t based on the reference pulse T REFa . In this case, since the position-deviation digital value X 1ER is -1, P ERa results in giving P ERa = 2π·(-1)+P 1ER . That is, P ERa is P 1ER pluse -2π. When the position-deviation digital value X 1ER is an integer n, P ERa results in giving P ERa = 2πn+P 1ER . P ERa means the data indicating a magnitude of an absolute phase difference between the reference pulse T REFa and the encoder pulse X FBa . This data is supplied as a feedback amount to the adjusting section 9a for adjusting the control amount of the object 10a. Hence, a magnitude of an absolute phase difference between the reference pulse T REFa and the encoder pulse X FBa is reduced to zero. The circuit for controlling a speed of the object 10b (Control section B for controlling the object), as shown in Fig.1, has the same arrangement as the foregoing control section A. Hence, no description will be directed to the control section B. Yet, the clock generator 1 is commonly used for the control sections A and B, so that no time shift is brought about between the reference pulses T REFa and T REFb , resulting in driving the objects 10a and 10b at a predetermined speed ratio in synchronization. As has been understood from the above description, the PLL speed control circuit of the invention is designed to generate the first and the second reference pulses assumed as the desired speeds or the reference phases of the first and the second objects based on the clock pulse generated in the clock pulse generator and reduce each phase difference between the first or the second reference pulse and the first or the second encoder pulse to zero in the returning process irrespective of any magnitude of the phase difference. The PLL speed control circuit, thus, makes it possible to drive the first and the second objects at a predetermined speed ratio and in synchronization. It results in improving circuit efficiency and expanding the scope of the circuit. Further objects and advantages of the present invention will be apparent from the following description, reference being had to the accompanying drawings wherein preferred embodiments of the present invention are clearly shown. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 which is composed of Figs. 1A and 1B is a block diagram showing a PLL speed control circuit according to the present invention; Figs. 2a to 2c are timing charts showing essential data and signals for describing an operating principle of the PLL speed control circuit; Fig.3 is a perspective view showing an embodiment where the PLL speed control circuit is applied to an electronic duplicating machine; Fig.4 is a front face view showing a core-less coil contained in a linear motor used for the electronic duplicating machine; Fig.5 is a partial block view showing a permanent magnet contained in the linear motor; Fig.6 is a side view showing the relation between a first mirror platform and a second mirror platform; Fig.7 is a graph showing a speed pattern characteristic of each linear motor; Fig.8 which is composed of Figs. 8A to 8C is a circuit diagram showing an electronic duplicating machine; Figs.9a and 9b are timing charts showing essential signals used in the PLL speed control circuit; Fig.10 is a flowchart showing a waiting state routine; Fig.11 is a flowchart showing an interrupt routine I included in the waiting state routine; Fig.12 is a flowchart showing an interrupt routine J included in the waiting state routine; Fig.13 is a flowchart showing an accelerating routine; Fig.14 is a flowchart showing a timer-interrupt routine A included in the accelerating routine; Fig.15 is a flowchart showing an interrupt routine A included in the accelerating routine; Fig.16 is a flowchart showing an interrupt routine B included in the accelerating routine; Fig.17 is a flowchart showing a constant state routine; Fig.18 is a flowchart showing a timer-interrupt routine B included in the constant state routine; Fig.19 is a flowchart showing an interrupt routine E included in the constant state routine; Fig.20 is a flowchart showing an interrupt routine F included in the constant state routine; Fig.21 is a flowchart showing an in-return accelerating routine; Fig.22 is a flowchart showing an interrupt routine G included in the accelerating state in return routine; and Fig. 23 is a flowchart showing an interrupt routine H included in the accelerating state in return routine. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description will be directed to an electronic duplicating machine employing a fixed document platform to which machine a preferred embodiment of a PLL speed control circuit according to the invention is applied. With reference to Fig.3, the description will be directed to linear motors 10a and 10b driving a first mirror platform 14 and a second mirror platform 15 in a document-scanning direction (indicated by an arrow in Fig.3) which platforms are included in the electronic duplicating machine. In Fig.3, small characters a and b attached to part numbers and signal numbers, as a rule, concern with the linear motors 10a and 10b, respectively. The linear motor 10a employs a three-phase brushless D.C. linear motor, which consists of movable elements 11a located on both sides of a first mirror platform 14 and stators 12 vertically located against the movable elements 11a with a predetermined gap. The linear motor 10b employs the same type motor and consists of movable elements 11b located on both sides of the second mirror platform 15 and the stators 12 vertically located against the movable elements 11b. For smoothly travelling the first mirror platform 14, the movable elements 11a are guided along a guide shaft 13. For the second mirror platform 14, the movable elements 11b are guided along the guide shaft 13 as well. Further, the linear motor 10a provides a linear encoder 4a for detecting a stroke position of the first mirror platform 14 and the linear motor 10b provides a linear encoder 4b for detecting a stroke position of the second mirror platform 15. (41 denotes a fixed-element scale attached near the fixed element 12) Then, with reference to Figs.4 and 5, the three-phase brushless linear motors will be described in detail. The movable element 11a contains core-less coils U 1a , V 1a , W 1a , which match to each phase in the three-phase brushless linear motor. The core-less coils U 1a , V 1a , W 1a have hole elements Hu, Hv, Hw respectively disposed in the air-core central portions of the coils as shown in Fig.4. The hole elements Hu, Hv, Hw are magnetic-field detecting elements for detecting the excitation change-over in the three-phase brushless linear motor. Reference numeral 28 denotes a reflection type detector which is provided on the bottom portion of a yoke plate 27. The other core-less coils have the same construction. The core-less coils U 1a , V 1a , W 1a and the core-less cores U 1a ′, V 1a ′, W 1a ′ and the yoke plates 27 constitute a rotor of the first linear motor 10a. The core-less coils U 1b , V 1b , W 1b and the core-less cores U 1b ′, V 1b ′, W 1b ′ and the yoke plates 27 constitute a rotor of the second linear motor 10b. The stator 12, as shown in Fig.5, contains a permanent magnet 29 and a yoke 20. The permanent magnet 29 is so arranged as to confront the respective core-less coils U a , V a , W a of the first linear motor 10a or the respective core-less coils U b , V b , W b of the second linear motor 10b, with a slight interval being provided with respect to the core-less coils. As shown, the permanent magnet 29 is alternately magnetized, with the N polarity and the S polarity in the face opposite to the respective core-less coils U a , V a , W a or U b , V b , W b . The magnetized pitch is arranged to 3/5 times as big as the pitch among the respective coil-less coils U a , V a , W a or U b , V b , W b as shown in Fig.4. Also, a linear scale 20a with black and white patterns being repeatedly drawn thereon is formed on the side face of the yoke 13 located in the lower portion (in a Z-direction) of the magnetized face of the permanent magnet 29. The linear scale 13a is adapted to detect the position and speed of the first mirror platform 14 and the second mirror platform 15 by the detector 28. And, the linear scale 20a is used in common by the detectors 28, provided in the first and the second mirror platforms 14 and 15. Next, with reference to Fig.6, the constructions of the first and the second mirror platforms 14, 15 will be schematically described. The first mirror platform 14 includes a halogen lamp 142 and a reflecting mirror 143 mounted on a platform body 141, while the second mirror platform 15 includes reflecting mirrors 152, 153 mounted on a platform body 151. Further, a zoom lens 16 and a reflecting mirror 17 are located at a position where the first mirror platform 14 is disallowed to come into contact with the second mirror platform 15. In operation, at first, the halogen lamp 142 radiates light to a document surface 19. Then, the light reflected from the document surface 19 is passed sequentially through the reflecting mirrors 141, 152, 153, the zoom lens 15, and the reflecting mirror 17 and then radiated to a photosensitive drum 18. The first mirror platform 14 stably travels at a speed twice as fast as the second mirror platform 15 so that an optical path between the document surface 19 and the photosensitive drum 18 is kept constant at any scanning position. Fig.7 indicates each speed pattern of the first mirror platform 14 (the speed of the linear motor 10a) and the second mirror platform 15 (the speed of the liner motor 10b). As is understood from the pattern, the first mirror platforms 14, 15 change their speed state in cyclic fashion from an initial waiting state α, an accelerating state β, a constant speed state γ, a accelerating state in return ε, and finally to the initial waiting state. Next, with reference to Fig.8, a description will be directed to a circuit for controlling the speed of the linear motor 10a or 10b (referred to as a linear motor control circuit). The linear motor control circuit shown in Fig.8 is a circuit mainly consisting of a one-chip microcomputer C known as a software servo system. It is pre-programmed in a manner to consistently control the speed of each of the linear motors 10a, 10b from the waiting α, an accelerating state β, a constant speed state γ, and an in-return accelerating state ε. In the constant speed state γ, it can be operative as a PLL speed control circuit according to the invention. At first, a peripheral circuit of the one-chip microcomputer C will be discussed. The one-chip microcomputer C incorporates an I/O ports 103a, 103b therein, which are respectively connected to the linear motors 10a, 10b through three-phase drivers 9a, 9b (matching to the adjusting sections). The I/O ports 103a, 103b output an PWM signal, an F/R signal, and a BRK signal, which are respectively used for adjusting a magnitude of thrust generated in the linear motor 10a or 10b, switching of driving direction, and a magnitude of damping force. The linear encoder 4a or 4b for detecting a relative speed of the linear motor 10a or 10b has a resolution of 400µm and outputs an a-phase and a b-phase signals each consisting of an approximately sin wave (shown in Figs. 9a and 9b) and a Z signal assumed as an origin. These signals are all supplied to a waveform shaping section 40b. In opposition to the waveform shaping section 40b, awaveform shaping section 40a is provided as shown in Figs. 9a and 9b. The waveform shaping section 40a performs the operations of re-shaping the a-phase signal and the b-phase signal into a U pa signal and a D na signal, adding the U pa signal into the D na signal, and generating a U pa signal (matching to an encoder pulse X FBa ). The other operations the waveform shaping section 40a performs is to produce an analogue position signal x a consisting of a pseudo-sawtooth wave from the a-phase and b-phase signals as well as to differentiate the a-phase and the b-phase signals and then to synthesize these signals into an analogue speed signal v a . The analogue position signal x a , the analog speed signal v a and the U pa signal are all supplied to a stroke position counter 5a, an analog-to-digital converter (referred to as an A/D converter) 104a, and a counter 70a. The description of the foregoing waveform shaping section 40b will be left out since it has the same construction as the waveform shaping section 40a. In addition, as a rule, the signal names and data names with capital letters indicate digital data quantized at a pitch of 400 µm (resolution). Those with small letters indicate analog data or digital data quantized at a smaller pitch than 400 µm. Then, a description will be directed to the stroke position counter 5a, the counter 70a, and the A/D converter 104a incorporated in the one-chip microcomputer C. The stroke position counter 5a serves to count up or down in response to the U pa signal or the D na signal and clear up in response to the Z a signal (meaning the reshaped Z signal sent from the linear encoder 4a). The stroke position counter 5a offers digital position data X₀₁ indicating a stroke position of the linear motor 10a (first mirror platform 14). And, the counter 70a serves to trigger the U pa signal at its leading edge for counting a clock pulse T (6MHz) supplied from the clock pulse generator 1. The counting data offered by the counter 70a indicates a pulse interval of the U pa signal, which is the digital speed data V₀₁ assumed as the speed of the linear motor 10a. Data TCK dentes the time taken in travelling an object, which corresponds to one pitch defined in the linear encoder 4a or 4b. The data TCK is represented by the number of clock pulse T. It is thus understood that the digital desired speed data V i1 equals to the data TCK. The data is also effective as a timer-setting data used for generating a reference pulse T REFa . The counter 70a serves to count a phase difference between the U pa signal and the reference pulse T REFa sent from a timer section 101 (described later) and output it as a count number of the clock pulse T (phase difference data P 1ER ). This function offered by the counter 70a corresponds to the phase difference deriving section shown in Fig.1. The A/D converter 104a serves to sequentially analog to-digital convert the analog position signal x a to a digital signal (the data to be converted is the analog position data x₀₁) and the analog speed signal v a into a digital signal (the data to be converted is the analog speed data v₀₁). In addition, no description is directed to the stroke position counter 5b, the counter 70b, and the A/D converter 104b incorporated in the one-chip microcomputer C, because they have the same arrangements and functions as the foregoing components. So are the data and the signals. Next, a description will be directed to a speed table 20a and a stroke position instruction section 2a shown in Fig.8. It concerns with the software function. The speed table 20a is a ROM table which pre-saves a speed pattern of the linear motor 10a shown in Fig.7. The data saved in the speed table 20a is allowed to be properly read out in response to the reference pulse T REFa . The read data is treated as the digital desired speed data V i1 for specifying a digital desired speed of the linear motor 10a and the time-setting data used for generating the reference pulse T REFa on which the digital desired speed is defined. The relevant function of the speed table 20a corresponds to the reference pulse generator shown in Fig.1. This digital desired speed data V i1 is converted into digital position instruction data X i1 in the stroke position instruction section 2a mainly consisting of a register counter. The analog position instruction data x i1 and the digital position instruction data X i1 respectively indicate an instructed value of the stroke position of the linear motor 10a. In addition, no description is directed to a speed table 20b and a stroke position instruction section 2b, because they have the same arrangements and functions as the foregoing ones. In the different respect, however, the speed table 20b and the stroke instruction section 2b receive the reference pulse T REFb which is half as long as that for the sections 20a and 2a from a divider 104. This is because the second mirror platform 15 is allowed to travel at a speed half as fast as the first mirror platform 14. The one-chip microcomputer C incorporates a timer 101 and an arithmetic logic section 102 in it. Then, the operation of the one-chip microcomputer C is described at each stage of the waiting state α, an accelerating state β, a constant speed state γ, and an in-return accelerating state ε. (1) Waiting State α When the linear motors 10a, 10b enters into the waiting state, the waiting routine as shown in Fig.10 is executed. At first, when a switch (not shown) is pressed, the A/D converters 104a and 104b issue A/D interrupt signals for properly executing an interrupt routine I and an interrupt routine J until the start signal enabled by the switch becomes active. That is, as shown in Figs.11 and 12, if the A/D converter 104a issues an interrupt signal when the start signal is still inactive (S1), the process goes to the interrupt routine I. At this routine, it is determined if the digital position data X₀₁ is zero. If the digital position data X₀₁ is one or more (S2), it is further determined if it is four or more. If it is less than four, the analog desired speed data v 1i is derived on this data (S3). If it is four or more, the analog desired speed data v i1 is derived within a given range (S4). Then, the analog speed data v₀₁ is subtracted from the analog desired speed data v i1 to derive the analog speed deviation data v 1ER (S5). Next, CNTL data is derived on the analog speed deviation data v 1ER . If, on the other hand, the digital position data X₀₁ is zero, the analog position data x₀₁ is subtracted from x c (matching to the analog position data x₀₁, x₀₂ given when the linear motors 10a, 10b stay at initial positions) for deriving the analog position deviation data x 1ER (S8). Then, the CNTL data is derived on the analog position deviation data x 1ER and the analog speed data v₀₁ (S9). After the CNTL data is derived as a result of the foregoing process, the interrupt routine I outputs a PWM signal and an F/R signal matching to the magnitude and the sign of the CNTL data (S9) and then finally finishes. If the A/D converter 104b issues an interrupt signal, the process goes to an interrupt routine H. This routine H, however, is not described since it is quite same as the routine I. The waiting routine has an advantage that the origin is far more accurately positioned based on the feedback control of the analog speed than the feedback control of the digital speed utilizing the digital speed data V₀₁ and the digital position data X₀₁. This is because the digital speed has a relatively large time lag. G₁ to G₈ shown in Figs.11 and 12 denote any servo gain. And, when the start signal becomes active while the waiting routine is executed step by step, the accelerating routine, as shown in Fig.13, gets started (S11). In the following description, TBL1(n) and TBL2(n) respectively stand for the contents of the data read out of the linear speed tables 20a, 20b when the digital position instruction data X i1 and X i1 each indicate n. (2) Accelerating State β Proceeding to the accelerating routine, as shown in Fig.13, at an initializing step, the timer 101 is started using the value of TBL1(1) for pre-setting TBL1(2) in preparation for the next timer operation. And, the PWM signal and the F/R signal are output so as to drive the linear motors 10a, 10b in the feeding direction at the maximum thrust (S12). Then, until the digital position instruction data X i1 matches to X p (matching to the digital position data X₀₁ assumed when the linear motor 10a stays at a D point shown in Fig.7), a timer-interrupt routine A, an interrupt routine A, and an interrupt routine B are properly executed. The process will be discussed in detail. When the timer 101 finishes counting the value of TBL1(1), as shown in Fig.14, the process proceeds to the timer-interrupt routine A. At this timer-interrupt routine A, the digital position instruction data X i1 is incremented by one. Then, it is determined if the digital position instruction data X i1 is even. If it is, the digital position instruction data X i2 is incrmented by one. Then, the TBL1(X i1 + 1) data is read out of the speed table 20a based on the one-incremented digital position instruction data and then the timer 101 is started on the read data. Later, the process is repeated until the digital position instruction data X i1 matches to X P . The interrupt routine A is then discussed in detail. As shown in Fig.15, the process updates the digital position data X₀₁ and proceeds to the interrupt routine A. At the routine A, the TBL1(X i1 ) data is read out of the speed table 20a and is assumed as the digital desired speed (S14). Then, it is determined if the digital position data X₀₁ matches to the digital position instruction X i1 . If not matched, the digital position data X₀₁ is subtracted from the digital position instruction data so as to derive the digital position deviation data X 1ER (S15). The corrected digital speed data V i1 ′ is derived using the digital position deviation data X 1ER and the digital desired speed data V i1 . Then, the digital speed data V₀₁ is subtracted from the corrected digital speed data V i1 ′ for deriving the digital speed deviation data V 1ER on which the CNTL data is obtained (S17). After the foregoing process results in deriving the CNTL data, the interrupt routine A serves to output the PWM signal and the F/R signal matching to the magnitude and the sign of the CNTL data (S18) and then finishes. No description will be directed to an interrupt routine B (see Fig.16) interrupted every time the digital position data X₀₂ is updated, because it is the same as the interrupt routine A. In the accelerating routine, when the position deviations of the linear motors 10a, 10b in the accelerating state are ±200 µm or smaller, the routine executes the normal speed feedback control. When the position deviations are more than ±200 µm, the speed is subject to the feedback control done on the speed deviation data V 1ER and V 2ER for converging the speed error faster, both of which data are the resulting signals of the correcting digital speed data V i1 ′, V i2 . This feedback control makes it possible to drive the linear motors 10a, 10b at a high speed in a manner to allow the linear motor 10a to travel twice as fast as the linear motor 10b. In Figs.14 to 16, G₁ to G₆ denote any servo gain. When the digital position instruction data X i1 matches to X p in the accelerating routine, the process proceeds to the constant-state routine as shown in Fig.17 (S19). (3) Constant Speed State γ Proceeding to the constant-state routine as shown in Fig.17, at an initializing step, the digital desired speed data V i1 is read out of the speed table 20a and then the timer 101 is started based on this data. The timer 101 is served as an interval timer. Then, the process serves to iteratively execute a timer-interrupt routine F, an interrupt routine E, and an interrupt routine F unless the digital position instruction data X i1 is equal to X E . X E indicates the digital position instruction data X₀₁ provided when the linear motor 10a is located at the E point shown in Fig.7. This iterative process will be discussed with reference to Fig.18. In this process, each time the timer 101 finishes counting of the digital desired speed data V i1 , the process proceeds to the timer interrupt routine B. At this routine B, the digital position instruction data X i1 is incremented by 1 and then it is determined if the digital position instruction data X i1 is even. Only if it is even, the digital position instruction data X i2 is incremented by 1. This operation is repeated subsequently unless the digital position instruction data X i1 is equal to X E . Then, the interrupt routine E will be discussed with reference to Fig.19. The updated digital position data X₀₁ is sent to the interrupt routine E. At this routine E, it is determined if the digital position data X₀₁ is equal to the digital position instruction data X i1 . If not, the digital position data X₀₁ is subtracted from the digital position instruction data X i1 , resulting in deriving the digital position deviation data X 1ER (S20). Then, the desired speed data V i1 is corrected using the digital position deviation data X 1ER . At the next step, the digital speed data V₀₁ is subtracted from the corrected digital desired speed data V i1 ′ for deriving the digital speed deviation data V 1ER , on which the CNTL data is derived (S21). If, on the other hand, the digital position data X₀₁ is equal to the digital position instruction data X i1 , -TCK/2 is added to the phase difference data P 1ER for offsetting the data P 1ER , thereby deriving the corrected phase difference data P ERa (S22). The function of deriving the data P ERa is carried out in the phase difference correcting section shown in Fig.1. Then, the digital desired speed data V i1 is corrected on this corrected phase difference data P ERa for deriving the corrected digital desired speed data V i1 ′ and the digital speed data V₀₁ is subtracted from the corrected digital desired speed data V i1 ′ for deriving the digital speed deviation data V 1ER . Using the data V 1ER , the CNTL data is derived (S23). The CNTL data is supplied to the next step at which the routine E forces the PWM signal and the F/R signal matching to the magnitude and the sign of the CNTL data to be output. Finally, this interrupt routine E is finished. In addition, no description will be directed to the interrupt routine F (see Fig.20) executed each time the digital position data X₀₂ is updated, because it is the same as the routine E as shown in Fig.19. In the routine for the constant speed state, when the position deviations of the linear motors 10a, 10b in the constant speed stateγ are ±200 µm or smaller, these linear motors are subject to the PLL speed control. When the position deviations are larger than ±200 µm, they are subject to the normal speed control for the purpose of simplifying the program. If it is desirous that these motors are subject to the PLL speed control even when the position deviations are more than ±200 µm, the routine enclosed by a dotted line in Fig.19 should be replaced. In those routines, G₁ to G₈ denote any servo gain. The foregoing process thus allows the linear motor 10a to stably travel at a speed twice as fast as the linear motor 10b without slipping both motors out of the proper positional relation. This is an excellent control characteristic. In other words, this control characteristic enables the optical distance to be kept constant irrespective of the scanning position, resulting in advantageously allowing the duplicating machine to offer a properly-focused duplicating image. When the constant speed state routines are executed step by step, if the digital position instruction data X i1 is equal to X E , the process proceeds to the in-return accelerating routine (S24) as shown in Fig.17. This routine will be discussed with reference to Fig.21. In the discussion, TBL3(n) and TBL4(n) denote the contents of data read out of the linear speed tables 20a, 20b when the digital position instruction data X i1 , X₀₂ respectively denote n. (4) In-return Accelerating State ε When the process proceeds to the in-return accelerating state ε, the PWM signal and the F/R signal are respectively output in a manner to allow these linear motors 10a, 10b to be reversely travelled at the maximum thrust. This routine is designed to iteratively execute an interrupt routine G and an interrupt routine H unless any one of the digital position data X₀₁, X₀₂ is equal to 4 as shown in Fig.21. With reference to Fig.22, the interrupt routine G is discussed in detail. When the updated digital position data X i1 is sent to the interrupt routine G, the TBL3(X₀₁) is read out of the speed table 20a and is assumed as the digital desired speed data V i1 . At the next step, the digital speed data V₀₁ is subtracted from the digital desired speed data V i1 for deriving the digital speed deviation data V 1ER . Then, the CNTL data is derived using the digital speed deviation data V 1ER . At the next step, the PWM signal and the F/R signal matching to the magnitude and the sign of the CNTL data are respectively output and then the interrupt routine G finishes. In addition, no description will be directed to the interrupt routine H (see Fig. 23) executed each time the digital position data X iz is updated, because the routine H is the same as the foregoing interrupt routine G. While the in-return accelerating routine is being executed, if any one of the digital position data X₀₁, X₀₂ is equal to 4, the waiting routine as described above is started. Immediately before each initial position of the linear motors 10a, 10b (the distance from the initial position matching to four pitches of the encoders 4a, 4b), the speed control is switched from a digital to an analog control. It results in advantageously allowing the linear motors 10a, 10b to travel back at a high speed as well as keeping the positioning precision of an origin proper. In Figs.22 and 23, G₁ and G₂ denote any servo gain. The electronic duplicating machine employing the PLL speed control circuit, therefore, makes it possible to speed up duplication and upgrade a duplicating image. It can provide a high-efficient device. Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present is not limited to the specific embodiments described in the specification, except as defined in the appended claims. For example, it may be applied to an X-Y table where 2 or more objects are driven in synchronization. Further, this circuit may employ pure hardware configuration, not the software configuration.

Claims: A phase locked loop speed control circuit for controlling the speed of two or more objects (10a, 10b), comprising; clock pulse generator means for respectively generating reference pulses (T REFa , T REFb ) for said two or more objects (10a, 10b), said clock pulse generator means including a clock pulse generator (1) for generating clock pulses (T) used for a time base and reference clock pulse generators (2a, 2b) for dividing the clock pulses (T) output by said clock pulse generator (1) for producing the reference pulses (T REFa , T REFb ) corresponding to desired speeds of said two or more objects (10a, 10b). encoder means (4a, 4b) for detecting the corresponding relative movements of said objects (10a, 10b) to provide respective encoder pulses (X FBa , X FBb ), and phase difference deriving means (7a, 7b) for subtracting each of encoder pulses (X FBa , X FBb ) of said encoder means (4a, 4b) from each respective reference pulse (T REFa , T REFb ) of said reference clock pulse generators (2a, 2b) for deriving phase differences (P 1ER , P 2ER ) of each of said objects (10a, 10b), characterized in that said phase looked loop speed control circuit further comprises first counting means (3a,3b) for counting the corresponding reference pulses (T REFa , T REFb ) output by said reference clock pulse generators (2a, 2b), second counting means (5a, 5b) for counting the corresponding encoder pulses (X FBb , X FBb ) output by said encoder means (4a, 4b), position deviation deriving means (6a, 6b) for subtracting each count of said second counting means (5a, 5b) from each count of said first counting means (3a, 3b) for deriving position deviations (X 1ER , X 2ER ) of said objects (10a, 10b). correcting means (8a, 8b) for correcting said phase differences (P 1ER , P 2ER ), and adjusting means (9a, 9b) for adjusting the movement of said objects based on the results (P ERa , P ERb ) output by said correcting sections (8a, 8b). The phase locked loop speed control circuit according to Claim 1, characterized in that said objects are linear motors. The phase locked loop speed control circuit according to Claim 1 or 2, characterized in that a number of said objects is two. The phase looked loop speed control circuit according to Claim 3, characterized in that said correcting means (8a, 8b) perform the predetermined equations of 2πX 1ER + P 1ER and 2πX 2ER + P 2ER , where X 1ER and X 2ER denote position deviations derived by said position deviation deriving means (6a, 6b) and P 1ER and P 2ER denote phase differences derived by said phase difference deriving means (7a, 7b). The phase locked loop speed control circuit according to any one of Claims 1 to 4, characterized in that said reference pulse generators (2a, 2b) respectively include ROM tables having saved speed patterns of each of said objects. The phase looked loop speed control circuit according to any one of Claims 1 to 5, characterized in that said phase locked loop speed control circuit further comprises a one-chip microcomputer having a stored program to independently control the speed of eaoh of said objects in a cyclic manner from a waiting state (Fig.10), an accelerating state (Fig.13), a constant speed state (Fig.17) and an accelerating state in return (Fig.21) to the original waiting state. The phase locked loop speed control circuit according to Claim 6, characterized in that for said waiting state (Fig.10), two interrupt routines (Fig.11, Fig. 12) are executed unless a start signal becomes active. The phase locked loop speed control circuit according to Claim 6, characterized in that for said accelerating state (Fig. 13), a timer-interrupt routine (Fig. 14) and two interrupt routines (Fig.15, Fig.16) are executed unless the digital position instruction data becomes equal to a predetermined position data indicating a specified position of said objects. The phase locked loop speed control circuit according to Claim 6, characterized in that for said constant speed state (Fig. 17), a timer-interrupt routine (Fig. 18) and two interrupt routines (Fig. 19. Fig. 20) are executed unless the digital position instruction data becomes equal to another predetermined position data indicating another specified position of said objects. The phase locked loop speed control circuit according to Claim 6, characterized in that for said accelerating state in return (Fig. 21), two interrupt routines (Fig. 22, Fig. 23) are executed unless any one of both said predetermined position data reaches a predetermined value.

Inventors: ISHII HIROSHI, OZAKI MASAAKI, ISHII, HIROSHI, OZAKI, MASAAKI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1990
Main classification: G05D13
IPC codes: G03G15, G05D13, H02P25, G03B27, H02P5