Ceramic multilayer chip capacitor and method for making

Abstract: In a ceramic multilayer chip capacitor (1) comprising alternately stacked internal electrodes of Ni or Ni alloy (21,25) and dielectric layers (3), an oxide layer (4) having a different composition from the dielectric layer is formed on the periphery of each internal (21,25) electrode. The dielectric layer (3) consists essentially of grains and a grain boundary phase, the percent area of the grain boundary phase being up to 2% of the area cross section of the dielectric layer. The capacitor (1) is prepared by alternately stacking Ni or Ni alloy and a dielectric material in layer form, firing and then heat treating the stack under predetermined oxygen partial pressures. The dielectric material is a barium titanate base oxide material.

Description: This invention relates to ceramic multilayer chip capacitors and a method for preparing the same. More particularly, it relates to an improvement in the dielectric layer of ceramic multilayer chip capacitors. BACKGROUND OF THE INVENTION Multilayer ceramic chip capacitors are generally manufactured by alternately applying an internal electrode-forming paste and a dielectric paste in layers by conventional green sheet, printing and other methods and simultaneously firing the resulting layers as an integral stack. Palladium (Pd) and palladium alloys have been widely used as the internal electrodes although relatively inexpensive nickel (Ni) and nickel alloys are now used as a substitute for expensive palladium. Undesirably, internal electrodes of Ni or Ni alloy are oxidized if fired in the ambient air. To prevent oxidation, the stack after binder removal is fired under an oxygen partial pressure lower than the equilibrium oxygen partial pressure of Ni and NiO. The dielectric layer is oxidized again by a further heat treatment. In this case, SiO 2 is added as a mineralizer for densification of the dielectric material while Al 2 O 3 is often added incidentally. The grain boundary phase components including BaO and TiO 2 as well as these components are sources for a loss of insulation resistance upon firing in a reducing atmosphere. Mn addition and Ca substitution are useful measures for preventing a loss of insulation resistance due to reduction of the dielectric layer. From US-A-4,097,911 a base metal electrode capacitor and a method of making the same is known wherein the dielectric layer is based on barium titanate with nickel electrodes interposed therebetween. EP-A-0 183 366 discloses a ceramic capacitor utilizing low-fire ceramic compositions wherein the base metal electrodes are sintered at temperatures less than about 950°C with a lithium fluoride flux and which has a base metal oxide integument at the surface of the electrodes. However, multilayer chip capacitors having internal electrodes of Ni or Ni alloy have an extremely short life of insulation resistance and are less reliable as compared with multilayer chip capacitors having internal electrodes of Pd fired in the atmospheric air. SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a reliable ceramic multilayer chip capacitor having internal electrodes of Ni or Ni alloy in which the effective life is extended by improving the dielectric layer thereof. The present invention provides a ceramic multilayer chip capacitor comprising internal electrodes of nickel or a nickel alloy and dielectric layers stacked alternately with the internal electrodes. According to a first aspect, an oxide layer having a different composition from the dielectric layer is formed on the periphery of each internal electrode. The oxide layer contains 0.1 to 99% by weight, calculated as P 2 O 5 , of phosphorus oxide, or 0.1 to 99% by weight, calculated as Fe 2 O 3 , of iron oxide or a mixture thereof. Preferably, the oxide layer has a thickness of 0.01 to 1 µm. The oxide layer often includes a first layer containing 0.1 to 99% by weight, calculated as P 2 O 5 , of phosphorus oxide and a second layer containing 1 to 99% by weight, calculated as MnO, of manganese oxide. The first layer has a thickness of 0.005 to 0.995 µm and the second layer has a thickness of 0.995 to 0.005 µm. Preferably, the dielectric layer comprises a dielectric oxide of the formula: [(Ba 1-x-y Ca x Sr y )O] m ·(Ti 1-z Zr z )O 2 wherein 0.05 ≤ x ≤ 0.25, 0 ≤ y ≤ 0.05, 0.05 ≤ z ≤ 0.20, and 1.000 ≤ m ≤ 1.020 and may further contain SiO 2 . The present invention also provides a method for preparing a ceramic multilayer chip capacitor, comprising the steps of: alternately stacking a dielectric material and an electrode-forming nickel or nickel alloy material to form a stack of dielectric layers and internal electrodes, said dielectric material containing 0.005 to 2% by weight, calculated as MnO, of a manganese compound and 0.005 to 5% by weight, calculated as P 2 O 5 , of a phosphorus compound based on the weight of the dielectric material, firing the stack under an oxygen partial pressure of 10 -8 atm. or lower, and then heat treating the stack at a temperature of 900 to 1200°C under an oxygen partial pressure of 1.01 x 10 -3 Pa (10 -8 atm) or higher, thereby re-oxidizing the dielectric layers to form an oxide layer having a different composition from the dielectric layers in close proximity to the internal electrodes. BENEFITS OF THE INVENTION The ceramic multilayer chip capacitors of the present invention are manufactured by firing and heat treatment under predetermined conditions after binder removal. These firing and heat treatment steps cause an oxide layer to be formed on the periphery of the internal electrodes of Ni or Ni alloy wherein the oxide layer is composed of oxides of elements from the dielectric material and internal electrode-forming material and an oxide of a separately added material, and has a different composition from the dielectric layer. The ceramic chip capacitors having such an oxide layer on the periphery of internal electrodes are fully reliable and about 2 to 5 times longer in life than the conventional ones. The reason why the oxide layer contributes to a longer life is not fully understood, but one presumed reason is that the oxide layer restrains migration of Ni ions during firing and operation. BRIEF DESCRIPTION OF THE DRAWINGS The structure, operation and advantages of the presently preferred embodiment of this invention will become further apparent upon consideration of the following description, taken in conjunction with the accompanying drawings, wherein: FIGS. 1 and 2 are cross-sectional views of ceramic multilayer chip capacitors according to different embodiments of the present invention; FIG. 3 is an electron micrograph under SEM of a dielectric material portion showing the presence of upper and lower oxide layers; FIGS. 4 and 5 are micrographs under an electron microanalyzer of an electrode adjacent portion of a multilayer chip capacitor showing the Ni concentration distribution; FIGS. 6 and 7 are micrographs under an electron microanalyzer of an electrode adjacent portion of a multilayer chip capacitor showing the Mn concentration distribution; FIGS. 8 and 9 are micrographs under an electron microanalyzer of an electrode adjacent portion of a multilayer chip capacitor showing the P concentration distribution; FIG. 10 is an electron micrograph under SEM of a dielectric layer of a multilayer chip capacitor of the present invention; and FIG. 11 is an electron micrograph under SEM of a dielectric layer of a prior art multilayer chip capacitor. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 and 2, there are illustrated two preferred embodiments of the ceramic multilayer chip capacitor of the present invention. The capacitor generally designated at 1 includes a first plurality of internal electrodes 21, a second plurality of internal electrodes 25, and a plurality of dielectric layers 3 in an alternate layered structure. Every dielectric layer is contiguous to the adjoining dielectric layers at the opposite ends so that the plurality of integrated dielectric layers may be considered as a single dielectric layer. The capacitor 1 further includes a pair of external electrodes 51 and 55 connected to the first and second internal electrodes 21 and 25, respectively. The internal electrodes 21 and 25 are formed of nickel or a nickel alloy. The nickel alloys used herein include alloys of at least 95% by weight of Ni with at least one element selected from the group consisting of Mn, Cr, Co, Al, and equivalent metals. The elemental nickel and nickel alloys may contain a trace amount, typically less than about 0.1% by weight, of P and other incidental elements. The dimensions of the internal electrodes 21 and 25 may be determined for a particular purpose or application without undue experimentation although their thickness generally ranges from about 1 to about 5 µm, especially from about 2 to about 3 µm. In the first aspect of the present invention, oxide layers 4 are formed on the periphery of internal electrodes 21 and 25 as shown in FIG. 2. The oxide layers 4 have a different composition from the dielectric layers 3. The dielectric layers 3 are composed of grains and a grain boundary phase. The material of which the dielectric layers 3 are formed may be selected from various types of material, preferably titanium oxide base materials, titanate composite oxides, zirconate composite oxides and mixtures thereof. The titanium oxide base materials include TiO 2 and mixtures of TiO 2 with at least one member of NiO, CuO, Mn 3 O 4 , Al 2 O 3 , MgO, and SiO 2 , and the titanate composite oxides include BaTiO 3 , SrTiO 3 , CaTiO 3 , MgTiO 3 and mixtures thereof. In the practice of the present invention, preferred among these are titanate composite oxides, especially dielectric oxides of the following formula: [(Ba 1-x-y Ca x Sr y )O] m ·(Ti 1-z Zr z )O 2 wherein 0.05 ≤ x ≤ 0.25, 0 ≤ y ≤ 0.05, 0.05 ≤ z ≤ 0.20, and 1.000 ≤ m ≤ 1.020, preferably 0.06 ≤ x ≤ 0.10, 0 ≤ y ≤ 0.01, 0.15 ≤ z ≤ 0.20, and 1.002 ≤ m ≤ 1.015. The dielectric titanate composite oxides may further contain silicon oxide and/or manganese oxide. Preferably silicon oxide is contained in an amount of about 0.05% to about 0.25% by weight in the form of SiO 2 and manganese oxide is contained in an amount of about 0.01% to about 0.50% by weight in the form of MnO. Inclusion of oxides of Al, Ni, Mg, Co and Hf in amounts of less than about 0.5% by weight is also contemplated. The benefits of the present invention are not available by adding oxides other than the oxides of the above-mentioned elements or by adding any of these oxides in amounts outside the above-defined ranges. The number, dimensions and other parameters of the dielectric layers 3 may be determined for a particular purpose and application. Often, the number of layers ranges from 1 to about 100, preferably from 5 to about 50. The layer thickness ranges from about 5 to about 50 µm, preferably from about 10 to about 20 µm. From a compositional aspect, the oxide layers 4 are formed at the interface between the dielectric layers 3 and the internal electrodes 21 and 25 as shown in FIG. 2, the oxide layers 4 having a different composition from the surrounding dielectric layers 3. The oxide layer 4 consists essentially of at least one oxide. Good results are obtained when the oxide layer contains at least one member selected from oxides of P, and Fe. Good results are also obtained when the oxide layer is of titanate composite oxides, especially of the above-defined formula. The phosphorus oxide is contained in an amount of 0.1 to 99%, more preferably 3 to 30%, most preferably 15 to 25% by weight of the oxide layer, calculated as P 2 O 5 . Where the oxide layer contains phosphorus oxide, Ti, Ba, Fe, Al, Si, Ca, Zr and Mn are co-present usually in the form of oxides. Among these elements in the oxide layer, phosphorus oxide is derived from an incidental impurity in the dielectric material or a P compound added thereto in phosphate salt form, Ti, Ba, Ca, Zr, Si and Mn are derived from the dielectric material, and Fe and Al are derived from incidental impurities in the internal electrode-forming material and the dielectric material. Where manganese and phosphorus oxides precipitate in the oxide layer, the layer acts as a barrier layer for preventing migration of Ni ions during operation. The iron oxide is contained in an amount of 0.1 to 99%, more preferably 0.5 to 30%, most preferably 5 to 20% by weight of the oxide layer, calculated as Fe 2 O 3 . Where the oxide layer contains iron oxide, Al, Si, Ca, Ti, Ni, Ba, Zr, Mn and P are co-present usually in the form of oxides. Among these elements in the oxide layer, iron oxide is derived from incidental impurities in the internal electrode-forming material and dielectric material, Si, Ca, Ti, Ba, Zr and Mn are derived from the dielectric material, Ni is derived from the internal electrode-forming material, and P and Al are derived from incidental impurities in the internal electrode-forming material and the dielectric material. In turn, the grains which constitute the great majority of the dielectric layer 3 contain iron (Fe) components derived from either the dielectric stock material or incidental impurities and these Fe components are detrimental to the life of capacitors. Therefore, unlike manganese and phosphorus oxides, it contributes to capacitor life extension to collect as much iron oxides in the oxide layer to deplete the grains of iron components. Preferably, the oxide layer has a thickness of about 0.01 to about 1 µm, more preferably about 0.05 to about 0.2 µm. Thicker oxide layers beyond the upper limit would cause a lowering of electricity storage ability. Not only a capacitance lowering occurs, but breakdown voltage, life and reliability are adversely affected. The oxide layer 4 may be of a single layer structure although an oxide layer of two-layer structure as shown in FIG. 2 offers additional benefits. The oxide layer 4 shown in FIG. 2 consists of an underlying oxide layer 41 and an overlying oxide layer 45 coextensive with the associated internal electrode. In the case of two-layer structure, one layer is rich in P oxide and the other layer is rich in Mn oxide. Inclusion of Fe oxide is more effective. More particularly, the underlying oxide layer 41 contains P oxide and the overlying oxide layer 45 contains Mn oxide. The underlying oxide layer 41 is a primary layer which can promote formation of the overlying oxide layer 45 so that the two-layer structure as a whole is more easily formed than the single layer structure. In particular, the underlying oxide layer 41 facilitates formation of the overlying Mn oxide-rich oxide layer 45. Iron oxide is often concentrated in the overlying oxide layer 45, but may also be contained in the underlying oxide layer 41. The overlying oxide layer 45 preferably contains about 1 to 99%, more preferably 10 to 50%, most preferably 25 to 40% by weight of manganese oxide, calculated as MnO on the basis of the weight of the overlying layer. Also preferably, the overlying oxide layer 45 contains about 0.1 to 99%, more preferably about 0.1 to 25%, most preferably about 5 to 15% by weight of iron oxide, calculated as Fe 2 O 3 . In addition, Ti, Ni, Ca, Ba, Zr, Al, Si and P may be contained in oxide form. The content of phosphorus oxide in the underlying oxide layer 41 preferably ranges from about 0.1 to 99%, more preferably about 3 to 30%, most preferably about 15 to 25% by weight, calculated as P 2 O 5 . In addition, Ba, Ca, Ti, Zr, Al, Si, Mn and Ni may be contained in oxide form. As to the thickness, both the underlying and overlying layers 41 and 45 range from about 0.005 to 0.995 µm, more preferably from about 0.05 to 0.2 µm, with the total thickness falling in the above-defined range. The oxide layer 4 may have a three or multiple layered structure, if desired. The external electrodes 51 and 55 are generally formed of Cu or Cu alloys as well as Ni or Ni alloys. Also employable are Ag and Ag-Pd alloys. The external electrodes 51 and 55 may have any desired thickness which is determined for a particular purpose and application. Their thickness generally ranges from about 10 to about 50 µm. The multilayer chip capacitor 1 may have any desired configuration and dimensions which are determined for a particular purpose and application. In the case of rectangular configuration, for example, the capacitors are often dimensioned to 1.6-3.2 mm by 0.8-1.6 mm by 0.6-1.2 mm. Now, the method for manufacturing the ceramic multilayer chip capacitor of the invention is described. First, pastes for the dielectric layers 3, internal electrodes 21 and 25, and external electrodes 51 and 55 are separately prepared. The paste for the dielectric layers 3 is prepared by mixing powder stock materials, for example, oxides of Ti, Ba, Sr, Ca and Zr in proportion to the desired composition of dielectric material. Additionally, silicon oxide and/or manganese oxide may be used. Instead of oxides, precursors which can be converted into oxides by firing, for example, carbonates, sulfates, nitrates, oxalates, and organometallic compounds may be used. Use of mixtures of oxides and precursors is also contemplated. The powder stock materials usually have a mean particle size of about 0.1 to about 5 µm. The power mix may further contain about 0.05 to 0.25% by weight of SiO 2 as sintering aids or mineralizer. Preferably, the powder mix contains a manganese compound or a phosphorus compound, more preferably both of them. The content of the Mn compound preferably ranges from about 0.005 to 2%, especially 0.05 to 0.5% by weight of MnO. Any desired manganese compounds may be used, including manganese oxides such as MnO, manganese carbonate, oxalate, hydroxide, nitrate, and sulfate, and organometallic compounds of manganese and mixtures thereof. The content of the P compound preferably ranges from about 0.005 to 5%, especially 0.01 to 0.05% by weight of P 2 O 5 . Any desired phosphorus compounds may be used, including phosphorus oxides such as P 2 O 5 , organic phosphorus compounds and mixtures thereof. A dielectric material is obtained from such a powder mix by the following procedure. First, powder feed materials are blended in the desired proportion and wet milled in a ball mill or the like. The mix is dried by a spray drier, and then calcined, typically at 800 to 1300°C for about 2 to 10 hours in air. The calcined mix is then pulverized to a predetermined particle size in a jet mill or ball mill. The Mn and P compounds may be added either before or after calcination. The calcined mix is then pulverized to a predetermined particle size in a jet mill or ball mill. The paste is prepared by mixing the powdered dielectric material with additives such as a binder, plasticizer, dispersant and solvent. Glass frit may also be added. The binders used herein include ethyl cellulose, abietinic acid, and polyvinyl butyral. The plasticizers used herein include abietinic acid derivatives, diethyl oxalate, polyalkylene glycols such as polyethylene glycol, and phthalate esters such as dibutyl phthalate. The dispersants used herein include glycerine, octadecylamine, trichloroacetic acid, oleic acid, octadiene, ethyl oleate, glycerine monooleate, glycerine trioleate, glycerine tristearate, and menhaden oil. The solvents used herein include toluene, terpineol, butylcarbitol, and methyl ethyl ketone. The paste is prepared by blending about 50 to 80% of the powdered dielectric material with about 2 to 5% of a binder, about 0.1 to 5% of a plasticizer, about 0.1 to 5% of a dispersant and about 20 to 50% of a solvent, based on the total weight of the paste. The powdered dielectric material mix is kneaded with these additives -in a three roll mill or the like to form a paste or slurry. The paste for the internal electrodes 21 and 25 is prepared by blending a conductive material, typically nickel or a nickel alloy or a mixture thereof with an organic vehicle. The conductive material is in finely divided form, but may have any desired shape including spherical granules and flakes and mixtures thereof. Typically it has a mean particle size of 0.1 to 10 µm, preferably 0.1 to 1 µm. The organic vehicle typically contains a binder and a solvent. The binder may be any of well known binders including ethyl cellulose, acrylic resin and butyral resin, and used in an amount of about 1 to 5% by weight of the paste. The solvent may be any of well known solvents including terpineol, butylcarbitol and kerosine, and used in an amount of about 20 to 55% by weight of the paste. In addition, there may be added a dispersant such as sorbitan fatty acid esters and glycerine fatty acid esters, a plasticizer such as dioctyl phthalate, dibutyl phthalate, and butyl phthalylglycolate, and other various dielectric or insulating ceramic powders commonly used for the purposes of preventing delamination and excess sintering. It is also useful to add organometallic resinates. The paste for the external electrodes 51 and 55 may be a conventional paste which is prepared by blending a conductive material with an organic vehicle. The conductive material may be Cu, Ni, Ag, an alloy thereof or any other suitable metal or alloy. The paste for the internal electrodes 21 and 25 and the paste for the dielectric layers 3 are alternately applied in layer form to produce a stack by well-known printing, transfer, green sheet and other methods. The stack is cut to a desired size, removed of the binder, fired, and finally heat treated for re-oxidation of the dielectric layers 3. Binder removal may be carried out under ordinary conditions, preferably under the following conditions: heating rate: 10-300°C/hour, especially 50-100°C/hour, holding temperature: 600-1200°C, especially 700-900°C, holding time: 1/2-5 hours, especially 1-3 hours, oxygen partial pressure: 10.1 to 1.01x10 -1 Pa (10 -4 -10 -6 atm), especially 1.01 to 1.01x10 -1 Pa (10 -5 -10 -6 atm). The atmosphere is preferably humid nitrogen gas. Firing is preferably carried out under the following conditions: heating rate: 50-500°C/hour, especially 200-300°C/hour, holding temperature: 1250-1400°C, especially 1300-1380°C, holding time: 1/2-8 hours, especially 1-3 hours, cooling rate: 50-500°C/hour, especially 200-300°C/hour, The atmosphere is preferably a humid mixture of nitrogen and hydrogen gases. Firing should preferably be carried out under an oxygen partial pressure of 1.01x10 -2 Pa (10 -7 atm) or lower, preferably 1.01x10 -3 to 1.01x10 -7 Pa (10 -8 to 10 -12 atm), especially 3.03x10 -4 to 1.01x10 -7 Pa (3x10 -9 to 10 -12 atm). Firing under a higher oxygen partial pressure would cause the internal electrodes to be oxidized whereas firing under an extremely lower oxygen partial pressure would cause abnormal sintering of the electrodes which can be locally broken. The final heat treatment is carried out at a holding or maximum temperature of 900 to 1200°C, preferably 900 to 1100°C, more preferably 1000 to 1100°C. Outside the range, lower temperatures result in short oxidation of the dielectric material, resulting in capacitors with a shorter life, whereas higher temperatures would cause oxidation of the internal electrodes or undesired reaction thereof with the adjoining dielectric material, resulting in a lowering of capacitance and a shorter capacitor life. The oxygen partial pressure during heat treatment is 1.01x10 -3 Pa (10 -8 atm) or higher, especially 10.1 to 1.01x10 -1 Pa (10 -4 -10 -7 atm). The dielectric and oxide layers 3 and 4 undergo insufficient re-oxidation under a lower oxygen partial pressure, whereas the internal electrodes can be oxidized under a higher oxygen partial pressure. The remaining heat treating conditions include a holding time of 0 to 6 hours, especially 2 to 5 hours and a cooling rate of 50 to 500°C/hour, especially 100 to 300°C/hour. The atmosphere is preferably humid nitrogen gas. Humid nitrogen gas or a humid mixture of nitrogen and hydrogen gases may be obtained by means of a humidifier, for example, by bubbling the gas into water, typically at about 5 to 75°C. The steps of binder removal, firing, and heat treatment may be carried out continuously or separately. In the latter case, a modification is made in the firing step such that the laminate is heated in a nitrogen atmosphere until the holding temperature for binder removal is reached and that after the laminate has been cooled down to the holding or maximum temperature for heat treatment, it is cooled in a nitrogen atmosphere. A modification is also made in the heat treatment step such that heating is carried out in a nitrogen atmosphere until the holding or maximum temperature is reached. A sintered laminate is obtained in this way. The sintered laminate on the surfaces is polished by tumbling or sand blasting. Then the external electrode paste is baked to the opposed surfaces to form the external electrodes 51 and 55. If desired, pads are formed on the external electrodes 51 and 55 by plating or the like. EXAMPLE Examples of the present invention is given below by way of illustration and not by way of limitation. All parts and percents are by weight unless otherwise stated. Example 1 A dielectric layer-forming paste was prepared. There were provided the following powder stock materials. Ingredients % by weight BaCO 3 65.28 TiO 2 23.72 ZrO 2 7.49 CaCO 3 2.88 SiO 2 0.18 MnCO 3 0.20 The powder stock materials were wet milled for 16 hours in an alumina ball mill. The mix was dried through a spray drier, calcined in air at a temperature of 1200°C for 3 hours, and then wet pulverized for 16 hours in a ball mill, obtaining a barium titanate base dielectric material powder having a mean particle size of 1.3 µm. This dielectric material had the following composition. [(Ba 0.92 Ca 0.08 )O] 1.004 ·(Ti 0.83 Zr 0.17 )O 2 99.62% SiO 2 0.18% MnO 0.20% A dielectric layer-forming paste was prepared by kneading the dielectric material powder with the following additives into a slurry by a three roll mill. Ingredients Parts by weight Dielectric material powder 100 Terpineol 28 Toluene 14 Dispersant 0.2 Lacquer 36.5 Separately, an internal electrode-forming paste was prepared by kneading the following ingredients into a slurry by a three roll mill. Ingredients Parts by weight Ni 100 Terpineol 93 Dispersant 1 Lacquer 6 A ceramic multilayer chip capacitor of a structure as shown in FIG. 2 was fabricated using these pastes. First, the dielectric layer and internal electrode-forming pastes were alternately applied in layer form by a printing method. The resulting stack included 4 dielectric layers. After cutting to a predetermined size, the stack was continuously subjected to binder removal, firing, and heat treatment under the following conditions. Binder removal Heating rate: 50°C/hour Holding temperature: 800°C Holding time: 2 hours Atmosphere: humid N 2 gas Oxygen partial pressure: 1.01x10 -1 Pa (10 -6 atm) Firing Heating rate: 200°C/hour Holding temperature: 1320°C Holding time: 4 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 and H 2 gas mixture Oxygen partial pressure: 1.01x10 -5 Pa (10 -10 atm) Heat treatment Holding temperature: 1100°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 gas Oxygen partial pressure: 1.01 Pa (10 -5 atm) The atmosphere gas was moistened by means of a humidifier filled with water at 10-35°C. The sintered stack on the side surfaces was polished by sand blasting. In-Ga alloy was applied to opposed side surfaces to form external electrodes. There was completed a ceramic multilayer chip capacitor having dimensions of 3.2 mm x 1.6 mm x 1.0 mm. The dielectric layers each were 13 µm thick and the internal electrodes each were 2.5 µm thick. The grains in the dielectric layers had a mean particle size of 3.1 µm. An observation under a scanning electron microscope (SEM) revealed the presence of an oxide layer on the periphery of the internal electrodes. The oxide layer was a single layer of 0.11 µm thick. The composition of the oxide layer was analyzed using a scanning transmission electron microscope (STEM), with the following results. (Chemical formulae are basis for calculation.) Mn oxide 38.0% of MnO Al oxide 0.1% of Al 2 O 3 Si oxide 1.4% of SiO 2 Ca oxide 0.7% of CaO Ni oxide 9.5% of NiO Zr oxide 0.1% of ZrO 2 Ti oxide 33.9% of TiO 2 Fe oxide 10.5% of Fe 2 O 3 P oxide 1.4% of P 2 O 5 Ba oxide 4.4% of BaO The capacitor was subjected to an accelerated life test by applying a DC voltage of 200 volts at a temperature of 200°C. The effective life was 1.3 hours. Example 2 A multilayer chip capacitor was fabricated by the same procedure as in Example 1 except for the firing and heat treating conditions. Firing Heating rate: 200°C/hour Holding temperature: 1380°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 and H 2 gas mixture Oxygen partial pressure: 1.01x10- 4 Pa (10 -9 atm) Heat treatment Holding temperature: 1000°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 gas Oxygen partial pressure: 1.01 Pa (10 -5 atm). In the completed capacitor, the dielectric layers each were 13 µm thick and composed mainly of grains having a mean particle size of 3.5 µm and the internal electrodes each were 2.3 µm thick. An observation under SEM revealed the presence of a single oxide layer of 0.12 µm thick on the periphery of the internal electrodes. On STEM analysis, the oxide layer had the following composition. Fe oxide 16.3% of Fe 2 O 3 Al oxide 0.2% of Al 2 O 3 Si oxide 0.3% of SiO 2 Ti oxide 4.5% of TiO 2 Mn oxide 13.0% of MnO Ni oxide 8.5% of NiO P oxide 14.5% of P 2 O 5 Zr oxide 2.3% of ZrO 2 Ba oxide 40.2% of BaO In the accelerated life test, the capacitor had an effective life of 2.3 hours. Example 3 A multilayer chip capacitor was fabricated by the same procedure as in Example 1 except for the firing and heat treating conditions. Firing Heating rate: 200°C/hour Holding temperature: 1340°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 and H 2 gas mixture Oxygen partial pressure: 1.01x10 -4 Pa (10 -9 atm). Heat treatment Holding temperature: 1000°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 gas Oxygen partial pressure: 1.01 Pa (10 -5 atm) In the completed capacitor, the dielectric layers each were 13 µm thick and composed mainly of grains having a mean particle size of 3 µm and the internal electrodes each were 2.4 µm thick. An observation under SEM revealed the presence of a single oxide layer of 0.09 µm thick on the periphery of the internal electrodes. On STEM analysis, the oxide layer had the following composition. P oxide 18.9% of P 2 O 5 Al oxide 0.3% of Al 2 O 3 Si oxide 0.1% of SiO 2 Mn oxide 0.9% of MnO Ni oxide 0.2% of NiO Ca oxide 0.4% of CaO Zr oxide 0.1% of ZrO 2 Fe oxide 0.2% of Fe 2 O 3 Ti oxide 2.2% of TiO 2 Ba oxide 76.7% of BaO In the accelerated life test, the capacitor had an effective life of 1.1 hours. Example 4 A multilayer chip capacitor was fabricated by the same procedure as in Example 1 except for the firing and heat treating conditions. Firing Heating rate: 200°C/hour Holding temperature: 1340°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 and H 2 gas mixture Oxygen partial pressure: 1.01x10 -6 Pa (10 -11 atm). Heat treatment Holding temperature: 1100°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 gas Oxygen partial pressure: 1.01 Pa (10 -5 atm) In the completed capacitor, the dielectric layers each were 13 µm thick and composed mainly of grains having a mean particle size of 3.0 µm and the internal electrodes each were 2.4 µm thick. An observation under SEM revealed the presence of double oxide layers 41 and 45 on the surfaces of the internal electrodes as shown in FIG. 2. The underlying and overlying oxide layers were 0.07 µm and 0.08 µm thick, respectively. FIG. 3 is a photomicrograph of an electrode adjacent portion of the dielectric layer, showing the presence of double oxide layers. In this photo, a lower portion is a nickel electrode, an upper portion occupying the majority of the photo is a dielectric layer, and a narrow curved band therebetween corresponds to oxide layers. The interface between the oxide layers is recognizable. On STEM analysis, the oxide layers had the following composition. Underlying oxide layer 41 Ba oxide 71.2% of BaO P oxide 21.0% of P 2 O 5 Ti oxide 2.8% of TiO 2 Fe oxide 1.9% of Fe 2 O 2 Ni oxide 1.9% of NiO Mn oxide 0.7% of MnO Si oxide 0.2% of SiO 2 Ca oxide 0.1% of CaO Zr oxide 0.1% of ZrO 2 Al oxide 0.1% of Al 2 O 3 Overlying oxide layer 45 Ti oxide 37.5% of TiO 2 Mn oxide 33.0% of MnO Fe oxide 8.0% of Fe 2 O 3 Ni oxide 8.0% of NiO Ba oxide 5.6% of BaO Zr oxide 5.0% of ZrO 2 P oxide 1.8% of P 2 O 5 Si oxide 0.8% of SiO 2 Al oxide 0.2% of Al 2 O 3 Ca oxide 0.1% of CaO The contents of P and Mn oxides in the underlying and overlying oxide layers were also examined by taking photographs under an electron radiation microanalyzer with a magnifying power of X2800. FIG. 4 is a microanalysis photo of focusing on Ni, in which nickel internal electrodes look as two white bands. FIG. 6 is a microanalysis photo focusing on Mn in which Mn rich areas look as four white strips. FIG. 8 is a microanalysis photo focusing on P in which P rich areas look as four white strips. In the accelerated life test, the capacitor had an effective life of 2.6 hours. Comparative Example 1 A multilayer chip capacitor was fabricated by the same procedure as in Example 1 except for the firing and heat treating conditions. Firing Heating rate: 200°C/hour Holding temperature: 1340°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 and H 2 gas mixture Oxygen partial pressure: 1.01x10 -3 Pa (10 -7 atm) Heat treatment Holding temperature: 1000°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere: humid N 2 gas Oxygen partial pressure: 1.01 Pa (10 -5 atm) In the completed capacitor, the dielectric layers each were 13 µm thick and contained grains having a mean particle size of 3.8 µm and the internal electrodes each were 2.5 µm thick. An observation under SEM revealed the absence of an oxide layer on the internal electrodes. In the accelerated life test, the capacitor had an effective life of 0.18 hours. The benefits of the invention are evident from the data of Examples 1-4 in comparison with these data of the comparative sample.

Claims: A ceramic multilayer chip capacitor comprising internal electrodes of nickel or a nickel alloy, and dielectric layers stacked alternately with the internal electrodes, wherein an oxide layer containing at least one member selected from the group consisting of 0.1 to 99 % by weight, calculated as P 2 O 5 , of phosphorous oxide and 0.1 to 99 % by weight, calculated as Fe 2 O 3 , iron oxide having a different composition from said dielectric layer is formed on the periphery of each said internal electrode. The capacitor of claim 1, wherein said oxide layer has a thickness of 0.01 to 1 µm. The capacitor of claim 1, wherein said oxide layer includes a first layer containing 0.1 to 99 % by weight, calculated as P 2 O 5 , of phosphorous oxide and a second layer containing 1 to 99 % by weight, calculated as MnO, of manganese oxide. The capacitor of claim 1, wherein said first layer has a thickness of 0.005 to 0.995 µm and said second layer has a thickness of 0.995 to 0.005 µm. The capacitor of claim 1, wherein said dielectric layer comprises a dielectric oxide of the formula: [(Ba 1-x-y Ca x Sr y )O] m ·(Ti 1-z Zr z )O 2 wherei 0.05 ≤ x ≤ 0.25, 0 ≤ y ≤ 0.05, 0.05 ≤ z ≤ 0.20, and 1.000 ≤ m ≤ 1.020. The capacitor of claim 5, wherein said dielectric layer further contains SiO 2 . A method for preparing a ceramic multilayer chip capacitor, comprising the steps of: alternately stacking a dielectric material and an electrode-forming nickel or nickel alloy material to form a stack of dielectric layers and internal electrodes, said dielectric material containing 0.005 to 2 % by weight, calculated as MnO, of a manganese compound and 0.005 to 5 % by weight, calculated as P 2 O 5 , of a phosphorous compound based on the weight of the dielectric material, firing the stack under an oxygen partial pressure of up to 1.01 x 10 -3 Pa (10 -8 atm), and then heat treating the stack at a temperature of 900 to 1200°C under an oxygen partial pressure of at least 1.01 x 10 -3 Pa (10 -8 atm), thereby re-oxidizing the dielectric layers to form an oxide layer having a different composition from the dielectric layers in close proximity to the internal electrodes.

Inventors: ABE MICHIO, IKEDA MASAAKI, NAKANO YUKIE, NISHIYAMA KOUSUKE, NOMURA TAKESHI, SUMITA SHIGEKAZU, ABE, MICHIO, IKEDA, MASAAKI, NAKANO, YUKIE, NISHIYAMA, KOUSUKE, NOMURA, TAKESHI, SUMITA, SHIGEKAZU
Applicants: TDK CORP, TDK CORPORATION
Application year: 1990
Main classification: H01G4
IPC codes: H01G4