Memory cell having floating gate and semiconductor memory using the same

Abstract: A memory cell (17) for storing data includes a first field effect transistor (Q12) having a source receiving a first voltage (V SE , Vcc), a floating gate, and a drain receiving data to be written into said memory cell and outputting said data, and a second field effect transistor (Q11) having a source receiving a second voltage (Vss), a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor. The second field effect transistor has a conduction type opposite to that of said first field effect transistor. The memory cell also includes a capacitor (C11) which has a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected to the floating gates of said first and second field effect transistors. The data is stored in the floating gates of said first and second field effect transistors.

Description: The present invention generally relates to a memory cell having a floating gate, such as a gate of a metal oxide semiconductor field effect transistor. Further, the present invention is concerned with a semiconductor memory using a plurality of such memory cells, such as an electrically erasable programmable read only memory. Various types of semiconductor memories are known. Erasable read only memories (ROMs) are widely used. It is possible to erase data from the erasable read only memory and then write data therein. As is known, erasable read only memories are classified into erasable programmable read only memories (EPROMs) and electrically erasable programmable read only memories (EEPROMs) in view of data erasing methods. Currently, it is required to reduce electrical power consumed in EPROMs or EEPROMs. Referring to FIG.1, there is illustrated a conventional semiconductor memory having a floating gate. The semiconductor memory shown in FIG.1 is composed of a data input terminal 1, a write amplifier (WA) 2, a sense amplifier (SA) 3, a capacitor C01, an N-type field effect transistor such as a MIS (metal insulator semiconductor) or MOS (metal oxide semiconductor) transistor, and a data output terminal 5. The sense amplifier 3 is made up of an amplifier 4 and a resistor R01. A high-potential side power source (line) Vcc is coupled to an input terminal of the amplifier 4, and an output terminal thereof is connected to the data output terminal 5. A connection node at which the input terminal of the amplifier 4 is connected to the resistor R01 is connected to the drain of the transistor Q01 via a sense line SL. Similarly, an output terminal of the write amplifier 2 is connected to the drain of the transistor Q01 via the sense line SL. A word line WL is coupled to the gate of the transistor Q01 via the capacitor C01. The capacitor C01 and the transistor Q01 form a memory cell of the EPROM. Data is stored, in the form of a charge, in a floating node N01 at which the capacitor C01 is connected to the gate of the transistor Q01. The source of the transistor Q01 is grounded. Generally, the memory cell shown in FIG.1 has two polysilicon layers formed at different layer levels. Recently, there has been proposed a single polysilicon layer structure, as shown in FIG.2. A semiconductor substrate 6 has an impurity diffused layer (region) 7 having a conduction type opposite to that of the semiconductor substrate 6. An oxide film 8 is formed on a surface of the semiconductor substrate 6, and a polysilicon layer 9 is formed on the oxide film 8. Drain and source regions of the transistor Q01 are formed in portions of the semiconductor substrate 6 which are arranged in a direction perpendicular to the drawing sheet and located on both sides of a portion 9a of the polysilicon layer 9. The MOS type field effect transistor Q01 shown in FIG. 1 is made up of the source and drain regions and the portion 9a of the polysilicon layer 9, and the capacitor C01 is made up of the impurity diffused region 7 and the remaining portion of the polysilicon layer 9. The impurity diffused layer 7 functions as a control gate and the word line WL. The polysilicon film 9 is electrically insulated from the other parts by the oxide film 8, and functions as a floating gate or node N01. When data "1" is written into the memory cell, a high-level data signal is applied to the data input terminal 1. This data signal is applied to the drain of the transistor Q01 via the write amplifier 2. On the other hand, the word line WL is set to a high level. Thereby, electrons having a large amount of energy are generated at a pinch-off point of the drain of the transistor Q01, and pass through the oxide film 8. Then, the electrons reach the polysilicon layer 9 which functions as the floating gate 9 (corresponding to the aforementioned floating node N01), and are accumulated therein. The electrons or charges accumulated in the polysilicon layer 9 cannot be discharged because the polysilicon layer 9 is electrically isolated from the other parts. Thus, a threshold voltage V TH of the transistor Q01 is increased. On the other hand, when data "0" is written into the memory cell, no operation is carried out, and no electrons are accumulated in the polysilicon layer 9. The data readout operation is as follows. When data "1" is stored in the memory cell shown in FIG. 1, the transistor Q01 is OFF, and no voltage drop is developed across the resistor R01. Thus, the amplifier 4 outputs a high level to the output terminal 5. On the other hand, when data "0" is stored in the memory cell, the transistor Q01 is ON, and a current passes through the transistor Q01 via the resistor R01. Thus, a voltage drop is developed across the resistor R01, and a low level substantially equal to the ground level is applied to the amplifier 4, which outputs a low level to the output terminal 5. When erasing data "1" in the memory cell, ultraviolet rays are projected onto the polysilicon layer 9, and energy thereof is applied to the charges stored therein. Thereby, a photo current passes from the polysilicon layer 9 to the semiconductor substrate 6 through the oxide film 8, so that the polysilicon layer 9 is discharged. US Patent No. 4,132,904 discloses a memory cell as indicated in the preamble of claim 1. It comprises a series of transistors including a pair of FETs having common drain and gate connections. A floating gate memory cell wherein the source and drain of a floating gate MOSFET and the control gate of said MOSFET are formed in the substrate is disclosed in Integration, the VLSI journal 8, (1989) November, No. 2, Amsterdam, NL. However, conventional memory cells as described above have a problem in that they consume a large amount of electrical power because it is necessary to allow a direct current to pass through the sense amplifier 3 and the sense line SL when data "0" is read out from the memory cell. It is a general object of the present invention to provide an improved memory cell in which the above-mentioned disadvantage is eliminated. A more specific object of the present invention is to provide a memory cell in which a reduced amount of power is consumed. In accordance with the invention there is provided a memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain outputting data stored in said memory cell; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; and a capacitor, being a Metal Oxide Semiconductor capacitor, having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected to the floating gates of said first and second field effect transistors, the material of said second terminal extending over the channel regions of the said first and second field effect transistors to form the floating gates thereof; said data being stored in the floating gates of said first and second field effect transistors, characterised by a third field effect transistor having a drain receiving data to be written into said memory cell, a source receiving said second voltage, and a gate connected to the floating gates of said first and second field effect transistors; and the second terminal of the Metal Oxide Semiconductor capacitor being connected to the gate of the third field effect transistor. The data is stored in the floating gates of the first and second field effect transistors. Another object of the present invention is to provide a semiconductor memory using the above-mentioned memory cell. This object of the present invention is achieved by a semiconductor memory comprising a data input terminal, a memory cell, write amplifier means for writing data applied to the data input terminal into the memory cell, and a data output terminal. The memory cell is configured as described previously. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a circuit diagram of a conventional semiconductor memory; FIG.2 is a cross-sectional view of a memory cell shown in FIG.1; FIG.3 is a circuit diagram of a semiconductor memory according to a first device relevant to the present invention, but Which is not covered by the attached claims; FIGS.4A, 4B and 4C are respectively cross-sectional views of a memory cell shown in FIG.3; FIGS.5A, 5B and 5C are respectively cross-sectional views illustrating another layer structure of the memory cell shown in FIG.3; FIG.6 is a circuit diagram of a semiconductor memory according to a second device relevant to the present invention but which is not covered by the attached claims; FIG.7 is a diagram showing allowable threshold voltages of two transistors in a memory cell shown in FIG.6; FIG.8 is a circuit diagram of a semiconductor memory according to a preferred embodiment of the present invention; FIG.9 is a block diagram illustrating an application of the present invention; FIG.10 is a block diagram illustrating another application of the present invention; FIG.11 is a block diagram illustrating still another application of the present invention; FIG.12A is a circuit diagram illustrating a modification of the memory cell shown in FIG.8; and FIG.12B is a circuit diagram illustrating a sense amplifier shown in FIG.12A. A description will now be given of a semiconductor memory device. Referring to FIG.3, the semiconductor memory shown in FIG.3 has a data input terminal 11, a write amplifier (WA) 12, a sense amplifier (SA) 13, a voltage generator 14, a data output terminal 16 and a memory cell 17. The write amplifier 12 has an input terminal connected to the data input terminal 11, and an output terminal connected to an input terminal of the sense amplifier 13 and the memory cell 17. The sense amplifier 13 has an amplifier 15, which has an input terminal serving as the input terminal of the sense amplifier 13, and an output terminal connected to the data output terminal 16. The memory cell 17 is composed of an N-channel field effect transistor Q11, a P-channel field effect transistor Q12 and a capacitor C11. The source of the transistor Q12 is connected to an output terminal of the voltage generator 14. The voltage generator 14 generates a voltage V SE , which is applied, as a power source voltage, to the source of the transistor Q12. The drain of the transistor Q12 is connected to the drain of the transistor Q11, the output terminal of the write amplifier 12, and the input terminal of the sense amplifier 13 via the sense line SL. The source of the transistor Q11 is grounded and set to a low-potential side power source voltage Vss. The gates of the transistors Q11 and Q12 are connected to each other, and also connected to the word line WL via the capacitor C11. Data is stored in a floating gate (node) N11 formed at a connection where the capacitor C11 and the gates of the transistors Q11 and Q12 are mutually connected. When a voltage higher than the sum total of a threshold voltage V THN of the transistor Q11 and a threshold voltage V THP of the transistor Q12 is applied to the source of the transistor Q12, a direct current will pass through the transistors Q11 and Q12. For this reason, the voltage generator 14 generates, from the power source voltage Vcc, the voltage V SE which is lower than the sum total of the threshold voltage V THN of the transistor Q11 and the threshold voltage V THP of the transistor Q12. Referring to FIG.4A, there is illustrated the layer structure of the memory cell 17 shown in FIG.3. An N⁺-type impurity diffused region 22 is formed in a P-type semiconductor substrate 21. An N-type impurity diffused region (well) 23 is also formed in the semiconductor substrate 21. Further, as shown in FIG.4B, two P⁺-type impurity diffused regions 26S and 26D serving as the source and drain of the transistor Q12 are formed in predetermined portions of the N-type well 23 and located on both sides of the polysilicon layer 25. It will be noted that FIG.4B is a diagram taken along a line extending in the direction perpendicular to the drawing sheet. An oxide film 24 is formed on the surface of the semiconductor substrate 21, and a polysilicon layer 25 is formed on the oxide film 24. A portion of the polysilicon layer 25 forms the aforementioned floating gate N11. A portion 25a of the polysilicon layer 25 above the N-type well 23 functions as the gate of the P-channel MOS transistor Q12. A portion 25c of the polysilicon layer 25 above the N⁺-type impurity diffused region 22, together with the oxide film 24, forms the capacitor C11. An intermediate portion 25b of the polysilicon layer 25 functions as the gate of the N-type MOS transistor Q11. As shown in FIG.4C, two N⁺-type impurity diffused regions 27S and 27D serving respectively as the source and drain of the transistor Q11 are formed in the semiconductor substrate 21 and located on both sides of the intermediate portion 25b. A description will now be given of the operation of the semiconductor memory shown in FIG.3. The word line WL is set to a high level equal to, for example, 12V, when data "1" is written into the memory cell 17. At the same time, a high-level input signal Din coupled to the data input terminal 11 is output to the sense line SL via the write amplifier 12, and applied to the drain of the transistor Q11. The word line WL corresponds to the N⁺-type impurity diffused region 22, which also functions as the control gate. Thus, a drain current passes through the transistor Q11, and a charge is stored in the polysilicon layer 25 which is the floating gate N11. The charge stored in the polysilicon layer 25 increases the threshold voltage of the transistor Q11. On the other hand, when data "0" is written into the memory cell 17, a low-level input signal Din applied to the data input terminal 11 is output to the sense line SL via the write amplifier 21, and at the same time, the word line WL is set to the high level. Although the word line WL is at the high level, the drain voltage of the transistor Q11 is low. Thus, a high electrical field does not occur, and no charge is stored in the floating gate N11, that is, the polysilicon layer 25. The state where no charge is stored in the polysilicon layer 25 means that data "0" is written into the memory cell 17. When data is read out from the memory cell 17, the word line WL is set to a level which is lower than the potential which is set when data is written. For example, the word line WL is approximately set to 5V. When data "1" is in the memory cell 17, the charge is stored in the polysilicon layer 25, and the threshold voltage of the transistor Q11 is maintained at an increased level. Thus, the transistor Q11 is OFF, and the transistor Q12 is ON. Thus, a high-level signal is output to the output terminal 16 via the transistor Q12 and the sense amplifier 13. On the other hand, when data "0" is in the memory cell 17, the threshold voltage of the transistor Q11 is at a level lower than that obtained when data "1" is written. Thus, the transistor Q11 is ON, and the transistor Q12 is OFF. As a result, a low level is output to the data output terminal 16 via the transistor Q11, the sense line SL and the sense amplifier 13. As described above, even if the resistor R01 (FIG.1) is not provided in the sense amplifier 13 and it is not designed to allow the direct current to pass through the sense line SL, it is possible to read out data from the memory cell 17. As a result, it is possible to reduce the power consumed and make the structure of the sense amplifier simple. The memory cell 17 is not limited to the structure shown in FIG.4. Alternatively, it is possible to employ a structure shown in FIGS.5A, 5B and 5C. In these figures, those parts which are the same as those shown in FIGS.4A, 4B and 4C are given the same reference numerals. A floating gate 31 formed of polysilicon is formed on the oxide film 24 formed on a P-type semiconductor substrate 30. An oxide film 32 is formed on the floating gate 31. A control gate 33 formed of polysilicon is formed on the oxide film 32. It will be noted that the N⁺-type impurity diffused region 22 (which serves as the control gate) shown in FIG.4A is not provided in the structure shown in FIGS.5A, 5B and 5C. The floating gate 31 corresponds to the polysilicon film 25 shown in FIGS.4A, 4B and 4C. The control gate 33 also functions as the word line WL. The capacitor Cll is formed of the control gate 33, the oxide film 32 and the floating gate 31. A description will now be given of a second semiconductor memory device, with reference to FIG.6, in which those parts which are the same as those shown in FIG.3 are given the same reference numerals. The power source voltage Vcc is directly applied to the source of the P-type MOS transistor Q12. The configuration shown in FIG.6 does not employ the voltage generator 14 shown in FIG.3. The configuration shown in FIG.6 is capable of generating an output voltage having an amplitude greater than that of the output voltage obtained in the aforementioned first embodiment of the present invention. The output voltage having an increased amplitude is applied to a data output terminal 36. The threshold voltages of the transistors Q11 and Q12 shown in FIG.6 are selected as follows. A threshold voltage V TH (N) of the transistor Q11 is higher than the voltage Vss (ground level) applied to the source of the transistor Q11, and a threshold voltage V TH (P) of the transistor Q12 is lower than the voltage Vcc applied to the source of the transistor Q12. As shown in FIG.7, the transistors Qll and Q12 are ON in a voltage range 39 shown by hatching, so that a direct current passes through the transistors Q11 and Q12. Thus, the threshold voltage V TH (P) is selected in a range 37 defined as being between the power source voltage Vcc and the highest voltage of the voltage range 39, and the threshold voltage V TH (N) is selected in a range 38 defined as being between the lowest voltage of the voltage range 39 and the power source voltage Vcc. As compared with the first device (fig. 3) , the configuration shown in FIG.6 does not need the voltage generator 14, although the threshold voltages of the transistors Q11 and Q12 are limited to the ranges 38 and 37, respectively. A description will now be given of a semiconductor memory according to a preferred embodiment of the present invention with reference to FIG.8, in which those parts which are the same as those shown in the previous drawings are given the same reference numerals. A memory cell 40 has an N-type field effect transistor Q13 such as a MOS transistor in addition to the transistors Q11 and Q12. The gate of the transistor Q13 is connected to the gates of the transistors Q11 and Q12. The drain of the transistor Q13 is connected to a data line DL extending from the output terminal of the write amplifier 12, and the source thereof is grounded. The transistor Q13 is exclusively used when data is written into the memory cell 40. In the aforementioned first and second devices (figs. 3,6) the high voltage is applied to the drain of the transistor Q11. Thus, it is necessary to form the impurity diffused layer 27D functioning as the drain of the transistor Q11 so that it has a thickness (depth) which ensures a high breakdown voltage. Correspondingly, it is necessary to form the impurity diffused layer 26D functioning as the drain of the transistor Q12 so that it has a high breakdown voltage. With the above in mind, in the embodiment of the present invention, the transistor Q13 specifically used when data is written into the memory cell 40 has been provided. By employing the transistor Q13, it is not required to use transistors having a breakdown voltage which is less than that required for the first and second devices. For example, it is sufficient for the transistors Q12 and Q11 to have threshold voltages approximately equal to 5V and 12-13V, respectively. When data is written into the memory cell 40, the high voltage is applied to the drain of the transistor Q13 via the data line DL, and at the same time, the word line WL is set to the high level. Thereby, hot electrons are introduced in the floating gate Nll which is the gate of the transistor Q13, and accumulated therein. When data is read out from the memory cell 40, the transistor Q13 is not used at all. It is also possible to add the transistor Q13 to the configuration shown in FIG.3. A description will now be given of an application of the present invention. FIG.9 is a block diagram of a semiconductor integrated memory device. The device in FIG.9 has defective cell address storage cells FA0 through FA9 formed of memory cells according to the present invention. The defective cell address storage cells FA0 - FA9 respectively store one-bit data of a defective cell address which indicates a defective memory cell array in a main memory array 41. The defective cell address read out from the storage cells FA0 - FA9 is applied to a group of exclusive-OR gates 42₀ - 42₉. For example, the one-bit data read out from the storage cell FA0 is applied to the exclusive-OR gate 42₀. An external address consisting of 10 bits, EA₀ - EA₉ is applied to the group of the exclusive-OR gates 42₀ - 42₉. For example, the address bit EA₀ of the external address is applied to the exclusive-OR gate 42₀. Each of the exclusive-OR gates 42₀ - 42₉ determines whether or not the two input bits coincide with each other. Each of the exclusive-OR gates 42₀ - 42₉ outputs a high-level signal when the input signals do not coincide with each other, and outputs a low-level signal when they coincide with each other. The output signals of the exclusive-OR gates 42₀ - 42₉ are applied to a ten-input OR gate 43. When the external address coincides with the defective cell address read out from the storage cells FA0 - FA9, the OR gate 43 generates a low-level output signal, which is input to a selector circuit 44. In response to the low-level output signal from the OR gate 43, the selector circuit 44 selects a redundant memory array 45 in place of the main memory array 41. Thereby, the use of the defective memory cell in the main memory array 41 is inhibited. On the other hand, when a high-level output signal is applied to the selector circuit 44 from the OR gate 43, the selector circuit 44 selects the main memory array 41. Conventionally, the defective cell storage cells FA0 - FA9 are formed of fuses which can be electrically melted or melted by a laser beam. When the storage cells FA0 - FA9 are formed of fuses which are electrically melted, it is necessary to use transistors having a high breakdown voltage. This leads to an increase in the chip area. On the other hand, when the storage cells FA0 - FA9 are formed of fuses which are melted by the laser beam, it is necessary to provide a laser beam device which emits the laser beam. These problems are eliminated by forming the storage cells FA0 - FA9 of the memory cells according to the present invention. In this case, it is possible to write data in the storage cells FA0 - FA9 without using a large amount of current. Further, no direct current passes through the memory cells of the storage cells FA0 - FA9 when reading out data, so that an increase in the standby current of the memory device is prevented. Furthermore, the storage cells FA0 - FA9 do not need a large chip area. A further description will now be given of another application of the present invention. In actuality, defective cell storage cells are arranged in an array. Referring to FIG.10, EPROM cells 51₀₀ - 51₇₉ according to the present invention are arranged in eight rows and ten columns. One write amplifier is provided in common for 71 memory cells aligned in a column. For example, a write amplifier WA0 is provided in common for the EPROM cells 51₀₀ - 51₇₀. Similarly, write amplifiers WA1 and WA9 are provided. Eight word lines WL0 - WL7 are provided for the respective rows of the array. For example, the word line WL0 is provided in common for the EPROM cells 51₀₀ - 51₀₉. The word line WL0 is set to a high level, and 10 bits of the defective cell address generated by an external device (not shown for the sake of simplicity) are respectively input to the write amplifiers WA0 - WA9. Thereby, the 10 bits of the defective cell address are written into the respective EPROM cells 51₀₀ - 51₀₉. Next, the word line WL1 is set to the high level, and 10 bits of the next defective cell address are respectively input to the write amplifiers WA0 - WA9. Then, the 10 bits of the above next defective cell address are written into the respective EPROM cells 51₁₀ - 51₁₉. In this way, eight defective cell addresses are written into the EPROM cells 51₀₀ - 51₇₉. FIG.11 shows another defective cell address storage cell array. In FIG.11, those parts which are the same as those shown in FIG.10 are given the same reference numerals. Exclusive-OR gates 52₀₀ - 52₇₉ are respectively provided for the EPROM cells 51₀₀ - 51₇₉, and compare the one-bit data of the defective cell address with the corresponding one-bit data of the external address generated by an external device (not shown for the sake of simplicity). For example, the exclusive-OR gate 52₀₀ compares the one-bit data output from the EPROM cell 51₀₀ with the one-bit data EA0 of the external address. N-type field effect transistors 53₀₀ - 53₇₉ are provided for the exclusive-OR gates 52₀₀ - 52₇₉, respectively, and have the gates which receive the output signals from the exclusive-OR gates 52₀₀ - 52₇₉. For example, the output signal of the exclusive-OR gate 52₀₀ is applied to the gate of the transistor 53₀₀. Pull-up resistors 54₀ - 54₇ are respectively provided for the rows of the transistors 53₀₀ - 53₇₉. The drains of the transistors 53₀₀ - 53₇₉ are pulled up to the power source voltage Vcc via the pull-up resistors 54₀ - 54₇. Amplifiers 55₀ - 55₇ are respectively provided for the rows of the transistors 53₀₀ - 53₇₉. Input terminals of the amplifiers 55₀ - 55₇ are connected to the corresponding pull-up resistors 54₀ - 54₇ and the drains of the corresponding transistors 53₀₀ - 53₇₉. The array of the EPROM cells 51₀₀ - 51₇₉ stores eight defective addresses in total. Each of the defective cell addresses is stored in the corresponding EPROM cell arranged in the row. The EPROM cells 51₀₀ - 51₇₉ are used only when data are read out from the main memory array 41 (shown in FIG.9). The defective cell address read out from the EPROM cells (51 j0 -51 j9 where j = 0 - 7) arranged in the row being considered is compared with the external address consisting of EA0 - EA9 by the corresponding exclusive-OR gates 52 j0 - 52 j9 . More specifically, during the time when the external address consisting of EA0 - EA9 is input, the word line WL0 is increased to the high level, and the one-bit data are read out from the EPROM cells 51₀₀ - 51₀₉, which are compared with the address bits EA0 - EA9 by the exclusive-OR gates 52₀₀ - 52₀₉. When the above bits coincide with each other, the corresponding exclusive-OR gate outputs the low-level signal, which turns OFF the corresponding transistor. On the other hand, when the above bits do not coincide with each other, the corresponding exclusive-OR gate outputs the high-level signal, which turns ON the corresponding transistor. For example, when one of the exclusive-OR gates 52 j0 - 52 j9 detects the fact that the input bits do not coincide with each other, the corresponding exclusive-OR gate generates the high-level signal, which turns ON the corresponding transistor. Thus, the drains of all the transistors 53 j0 - 53 j9 are grounded. Thus, the amplifier 55j generates the low-level signal. On the other hand, when all the exclusive-OR gates 52 j0 - 52 j9 detect the fact that the input bits coincide with each other, they output the low-level signals, and all the transistors 53 j0 - 53 j9 are OFF. Thus, the amplifier 55j generates the high-level signal, which is output to the selector circuit 44 shown in FIG.9. Then, the selector circuit 44 selects a corresponding redundant memory cell in the redundant memory array 45. In the above-mentioned way, the word lines WL0 - WL7 are successively selected, and the comparison operation on the corresponding address bits is carried out. It should be appreciated that the configuration shown in FIG.11 uses only eight output lines which carry the signals indicating whether or not the related input address bits coincide with each other. That is, the comparison results of the 10 exclusive-OR gates are grouped for every 10 bits, and one signal indicating whether or not the related input address bits coincide with each other. It will be noted that the configuration shown in FIG.10 uses 80 output lines. It is possible to form each of the EPROM cells 51₀₀ - 51₇₉ shown in FIGS.10 and 11 of a memory cell 60 shown in FIG.13A. The memory cell 60 has a sense amplifier 61 which is substituted for the aforementioned transistor Q12 shown in FIG.8. The sense amplifier 61 may have a configuration which is the same as that of the sense amplifier 3 shown in FIG.1. That is, as shown in FIG.12B, the sense amplifier 61 has a resistor R02 connected between the power source line Vcc and the drain of the transistor Q11 and an amplifier 62 having an input terminal connected to the drain of the transistor Q11, and an output terminal connected to the data output terminal 36. When a charge is in the floating gate N11, the transistor Q11 is OFF, and thus, the high-level signal is output to the data output terminal 36. On the other hand, when no charge is stored in the floating gate N11, the low-level signal is output to the data output terminal 36. The present invention includes not only EPROMs but also EEPROMs. The present invention is not limited to the specifically disclosed embodiment , and variations and modifications may be made without departing from the scope of the claims.

Claims: A memory cell (17) for storing data comprising: a first field effect transistor (Q12) having a source receiving a first voltage (V SE , Vcc), a floating gate, and a drain outputting data stored in said memory cell; a second field effect transistor (Q11) having a source receiving a second voltage (Vss), a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; and a capacitor (C11), being a Metal Oxide Semiconductor (MOS) capacitor, having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected to the floating gates of said first and second field effect transistors, the material (25) of said second terminal extending over the channel regions of the said first and second field effect transistors to form the floating gates thereof; said data being stored in the floating gates of said first and second field effect transistors, characterised by a third field effect transistor (Q13) having a drain receiving data to be written into said memory cell, a source receiving said second voltage, and a gate connected to the floating gates of said first and second field effect transistors; and the second terminal of the Metal Oxide Semiconductor capacitor being connected to the gate of the third field effect transistor. A memory cell as claimed in claim 1 wherein: said first and second field effect transistors (Q12, Q11) and said capacitor (C11) have, in common, a semiconductor substrate (21), an insulator film (24) formed on said semiconductor substrate and the said material (25) being a conduction layer; said first field effect transistor (Q12) has a well region (23) formed in said semiconductor substrate and having a conduction type opposite to that of said semiconductor substrate, and source and drain regions (26S, 26D) formed in said well region; said second field effect transistor (Q11) has source and drain regions (27S, 27D) formed in said semiconductor substrate; said capacitor has an impurity diffused region (22) formed in said semiconductor substrate and having a conduction type which is the same as that of said well region ; and said conduction layer has a first portion (25a) located above said well region of said first field effect transistor and functioning as the floating gate of said first field effect transistor, a second portion (25b) located between the source and drain regions of said second field effect transistor and functioning as the floating gate of said second field effect transistor; and a third portion (25c) located above said impurity diffused region of said capacitor and serving as the second terminal of said capacitor. A memory cell as claimed in any one of claims 1 and 2 wherein; said first and second field effect transistors (Q12, Q11) have, in common, a semiconductor substrate (30), a first insulator film (24) formed on said semiconductor substrate,the said material (25) being a first conduction layer (31) formed on said first insulator film, a second insulator film (32) formed on said first conduction layer, and a second conduction layer (33) formed on said second insulator film; said first field effect transistor has a well region (23) formed in said semiconductor substrate and having a conduction type opposite to that of said semiconductor substrate, and source and drain regions (26S, 26D), formed in said well region; said second field effect transistor (Q11) has source and drain regions (27S, 27D) formed in said semiconductor substrate; said first conduction layer (31) functions as the floating gates of said first and second field effect transistors as well as the second terminal of said capacitor (C11); and said second conduction layer (33) functions as the first terminal of said capacitor. A memory cell as claimed in any preceding claim, wherein said first field effect transistor (Q12) comprises a P-channel field effect transistor; and said second field effect transistor (a11) comprises an N-channel field effect transistor. A semiconductor memory comprising: a data input terminal (11); a memory cell (17) according to any preceding claim; write amplifier means (12) for applying writing data from said data input terminal to the drain of said third field effect transistor (Q13); and a data output terminal (16) connected to the drain of said first field effect transistor (Q12). A semiconductor memory as claimed in claim 5, further comprising voltage generating means for generating said first voltage. A semiconductor memory as claimed in claim 5 or claim 6, further comprising sense amplifier means (13), coupled between said output terminal and the drains of said first and second field effect transistors, for amplifying said data obtained at the drains of said first and second field effect transistors.

Inventors: TAKEMAE YOSHIHIRO, TAKEMAE, YOSHIHIRO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G06F11
IPC codes: G11C29, H01L29, H01L21, G11C17, G11C16, H01L27