Process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide by using differential oxidation

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10′) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10″, 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

Description: The present invention relates to a process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide by using differential oxidation. Cells of this type are known which comprise a floating gate sensing transistor and a selection transistor to select the cell to be programmed in the set of cells of the matrix. The floating gate is capacitively coupled to an N+ diffusion which acts as a control gate. The cell also comprises a thin oxide tunnel area, between the floating gate and the drain of the cell, at which there occurs the passage of electrons in the writing and erasure steps. During a writing pulse the control gate is held grounded while the drain is connected to high voltage by means of the selection transistor. Electrons flow from the floating gate to the drain and at the end of the pulse the sensing transistor is in "on" state. During an erasure pulse the drain is grounded and the control gate is at a high voltage. Electrons flow from the drain to the floating gate and at the end of the pulse the sensing transistor is in "off" state. The writing and erasure efficiency is controlled by the values of the drain coupling coefficients Ad and the gate coupling coefficients Ag, respectively. In particular, if Cd is the sum of the drain capacity and of the sensing transistor capacity, Ctun is the tunnel capacity, Cpp is the control gate capacity, Ctot is the total capacity of the floating gate towards all the nodes, the coefficient Ad is directly proportional to the sum of Cd and Ctun and inversely proportional to Ctot, while the coefficient Ag is directly proportional to Cpp and inversely proportional to Ctot. For a good writing and erasure efficiency coefficient Ag must be high and Ad low. The use of a technology having a single level of polysilicon in the manufacture of EEPROM memory cells has several advantages over the technology having two levels of polysilicon, both in efficiency and in reliability, connected to a greater process simplicity in devices in which a high memory density is not called for but rather process compatibility. In fact this type of approach does not require the use of technological steps which are critical for the definition of the superimposition of the double polysilicon layer. Better reliability is obtained by the absence of oxide between the two polysilicon layers (interpoly oxide) and by the elimination of high-temperature treatments to which the thin oxide is subjected during the growth of the interpoly oxide. A known EEPROM cell having a single level of polysilicon used the same thickness of oxide in the tunnel area and in the coupling area between control gate and floating gate. An EEPROM cell of this type is known from EP-A-0 268 315. In particular, the manufacturing of such cell provides for the introduction of an MOS condenser with thin oxide for the capacitive coupling between the control gate and the floating gate. The above cell is incorporated in a standard process with the addition of one mask only necessary for the definition of the thin oxide areas. The mask is inserted after the growth of the gate oxide and opens both tunnel and coupling areas between the floating gate and the control gate. Such masking is followed by implantation of N dopant (phosphorus 10 14 -10 15 at/cm 3 ), by attack of the gate oxide, by tunnel oxidation and by deposition of polysilicon. With this process architecture, the gate coupling coefficient Ag is substantially determined by the ratio between the coupling thin oxide and drain areas. To obtain a good cell programming efficiency, that is, a sufficiently high value of Ag, it is thus necessary to have a large area of thin oxide coupling (about a factor of 5 with respect to the tunnel area). This type of approach, with respect to the technology having two levels of polysilicon, involves problems and disadvantages introduced by the large thin oxide area used. The disadvantages can be summarized as: a) higher net area consumption; b) reliability problems due to the defectiveness of the thin oxide; c) presence of two tunnel areas in series, which can be configured like two tunnel diodes in series, and thus create problems of sensitivity to overvoltages. The defectiveness of the thin oxide turns out to be a very important parameter for assessing the possibility of the use of the technology having a single level of polysilicon. A high level of defectiveness could cancel out the reliability advantages introduced by the elimination of the technological steps related to the double polysilicon. The selection between the two types of technology is substantially dictated by the level of defect density of the thin oxide. The existence of two tunnel diodes in series, representative of the two thin oxide areas, makes the device sensitive to any overvoltages which could lead to the breakdown of the thin oxide, due to the direct passage of tunnel current between the cell's drain and its control gate. An improvement in the performance of the cell from the point of view of reliability can be introduced by reducing the thin oxide area. The object of the present invention is to accomplish a process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide, which provides for the growth of an oxide at the coupling area between the control gate and the floating gate having a greater thickness with respect to the thickness of the oxide at the tunnel area. According to the invention such object is attained with a proces as defined in claim 1. There is thus obtained, by means of a double ion implantation at the coupling area between the control gate and the floating gate against a single ion implantation at the tunnel area, a higher growth of oxide in the coupling area with the consequent improvement of the performance of the cell from the point of view of reliability, since the area of thin oxide in the tunnel area is reduced on a percentage basis. Differential oxidation eliminates the tunnel diode on the control gate, reducing the device's sensitivity to overvoltages during both writing and erasure of the cell. The features of the present invention shall be made more evident by the following detailed description of an embodiment illustrated as a non-limiting example in the enclosed drawings, wherein: Fig. 1 is a top plan view of an EEPROM cell according to the invention; Fig. 2 is a sectional view of the above cell taken along the line II-II of Fig 1; Fig. 3 is a sectional view of the cell taken along the line III-III of Fig 1; Fig. 4 is a sectional view of the cell taken along the line IV-IV of Fig 1; Fig. 5 shows a succession of steps of the process for manufacturing the cell of Fig.s 1 to 4. With reference to Fig.s 1 to 4, wherein the references 41 and 42 represent the active areas free from field oxide 11, (Fig.s 2 to 4) and references 43, 44 indicate the bit-line contact and earth areas, the EEPROM cell comprises a selection transistor 20 whose gate is represented by a layer of polysilicon 1 having an N type doping (constituting the word-line) superimposed through a gate oxide 21 over a P type substrate 2, while the drains and sources are represented by N+ type areas 3, 4 formed in the substrate 2 (Fig. 2). The cell also comprises a sensing transistor (22) having a floating gate represented by a layer of polysilicon 5 with an N type doping superimposed over the substrate 2 through gate oxide 21, while the drains and sources are represented by regions 6, 7 of N+ type, obtained inside the substrate 2. The floating gate 5 is capacitively coupled to an N+ type area 8 obtained in the substrate 2 by means of a thin oxide layer 9 superimposed over the substrate 2. Said area 9 forms a tunnel area 23 for the acceleration of the negative charges. The floating gate 5 is also capacitively coupled, in an area 24 with oxide 12 having a greater thickness than that of the thin oxide 9, to an area 10 of N+ type, which constituites the cell's control gate. With reference to Fig. 5, formed by cross-sections similar to that of Fig. 2, there are indicated the successive steps 29-35 of the process for the creation of coupling areas 9, 12 between floating gate 5 and said N+ dopant areas 8, 10. A first step 29 provides for the definition of two active areas 41, 42 superimposed over the substrate 2 and separated from one another by field oxide areas 11, accomplished at the tunnel area 23 and at the coupling area 24 between the control gate 10 and the floating gate 5. A second step 30 provides for the preliminary operation of the surface masking of the cell by means of a mask 60 having a window 61 at the coupling area 24 between the control gate 10 and the floating gate 5, followed by a first N+ type ion implantation 10' executed through said window 61. A third step 31 provides for the creation of gate oxide 21 at the active areas 41, 42. A fourth step 32 provides for the preliminary operation of the surface masking of the cell by means of a mask 62 having a pair of windows 63, 61 at the coupling area 24 between the control gate 10 and the floating gate 5 and of the tunnel area 23, followed by a second N+ type ion implantation 10", 8. A fifth step 33 provides for the removal of the gate oxide 21 at the active areas 41, 42. A sixth step 34 provides for an oxidation step causing growth of different thicknesses of coupling oxide 12 and tunnel oxide 9 on the active areas 41, 42 at said coupling area 24 and tunnel area 23, this deriving from the previous different doping doses implanted in the two areas. A seventh step 35 provides for the deposition of a layer of polysilicon 5 constituting the floating gate.

Claims: Process for manufacturing EEPROM memory cells with a single polysilicon level, each said cell comprising a selection transistor (20) and a sensing transistor (22) having a floating gate (5), a control gate (10) formed in a substrate (2) and capacitively coupled with said floating gate (5), and a tunnel area (23) having a thin oxide layer (9) interposed between said floating gate (5) and said substrate (2), said process comprising the following succession of steps: a) forming first and second active areas (41, 42), free of field oxide, on the substrate (2); b) performing a first ion implantation (10') at a portion of said first active area (42) which forms, in the completed cell, a coupling area (24) between the control gate (10) and the floating gate (5); c) creating a gate oxide (21) for said selection and sensing transistors (20, 22) on said active areas (41, 42); d) performing a second ion implantation (10", 8) at said coupling area (24) and at a portion of said second active area (41) which forms, in the completed cell, said tunnel area (23); e) removing the gate oxide (21) from said coupling area (24) and said tunnel area (23); f) growing a coupling oxide (12) and a tunnel oxide (9) at said coupling area (24) and said tunnel area (23) respectively, said tunnel oxide (9) being thin with respect to said coupling oxide (12) as a result of the previous first and second ion implantations (10', 10"; 8) performed at said coupling area (24) and said tunnel area (23); g) depositing a polysilicon layer (5) on said coupling area (24) and said tunnel area (23) to form said floating gate (5). Process according to claim 1, characterized in that the substrate (2) has a P type doping and said first ion implantation (10') causes a first N+ type doping of the control gate (10). Process according to claim 2, characterized in that said second ion implantation (10", 8) causes a second N+ type doping of the control gate (10) and an N+ type doping of the tunnel area (23).

Inventors: GHEZZI PAOLO, RIVA CARLO, VALENTINI GRAZIA, GHEZZI, PAOLO, RIVA, CARLO, VALENTINI, GRAZIA
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H01L21
IPC codes: H01L27, H01L21, H01L29