Method of arranging components in semiconductor device

Abstract: A method of arranging components in a semiconductor device on a substrate (11), comprising provisionally determining a wiring path (3) so that a predetermined wiring capacitance is not exceeded in a specific network (1) and then performing a wiring process of elements (12) in the specific network within a component placement region (2) determined by the wiring path.

Description: The present invention relates to a method of arranging components in a semiconductor device on a substrate. More precisely, it relates to a method of arranging components so that a wiring capacitance (network capacitance) of conductors connecting associated components in a specific network is lower than a predetermined value. In a logic design of an LSI, such as a gate array, the wiring capacitance of a specific network having a high frequency or a large number of fan-outs must be carefully taken into account, and accordingly, the arrangement or location of components constituting the specific network must be carefully taken into consideration so as to satisfy the wiring capacitance of the components. The term "component" is used as a generic term in this specification and covers various logic circuits, semiconductor elements, flip-flops, gate elements, etc., and also embraces terms "element"and "cell" used below. There are two known arrangements of components in a semiconductor device, such as a CMOS gate array. According to a first known arrangement algorithm, a designer designates the arrangement of the cells without considering the wiring capacitance of the specific network, so that the wiring, i.e., the conductor arrangement of the connection of the components, can be automatically determined by a computer. On the other hand, in a second known algorithm arrangement, the arrangement and the electrical connection of the components are automatically determined by a computer, and thereafter, the wiring capacitance is computed to adjust the arrangement of the components and the wiring so that the wiring capacitance cannot exceed a predetermined value. In the first mentioned arrangement, however, since the wiring capacitance in the specific network is not taken into account, the path of the conductors depends on the conductor arrangement of the circumferential components, and this results in a difficulty in obtaining a desired wiring capacitance by a designer. As a result, an electrical defect, such as electromigration, may occur. In the latter arrangement, the arrangements of the components and the wiring must be manually modified, but this is troublesome and time-consuming. Accordingly, it is desirable to provide a method of arranging components in a semiconductor device in such a way that no rearrangement of the components and no rewiring are necessary, and by which the component arrangement can be determined and the wiring can be effectively conducted so as not to exceed a designer's intended wiring capacitance. IBM Technical Disclosure Bulletin, Vol. 30, No. 10, March 1988, page 172, discloses a method for controlling VLSI chip timing constraints. In this method, the most constraining of several competing goals for each chip net is communicated to a circuit placement program. The placement algorithm optimizes these goals along with other goals. IEEE International Conference on Computer-Aided Design, ICCAD-87 Santa Clara, Calif., 9-12 November 1987, includes on page 88-91 a paper "Circuit Placement for Predictable Performance" by P. S. Hauge et al. A method for designing gate array or standard cell chips is disclosed in which precise bounds for the delays of each circuit are developed by using a so-called "zero-slack algorithm". Research Disclosure No. 299, 10 March 1989, disclosure No. 29924, (page 169) discloses a method to achieve equal capacitance on a group of nets during circuit layout and placement. This is an enhancement to a known method of random placement of circuits followed by "annealing". 23rd ACM/IEEE Design Automation Conference, 29 June-2 July 1986, paper 24.3 pages 404-410, IEEE, New York, U.S.A., discloses efficient placement algorithms for optimizing delay in masterslice LSIs, employing an iterative weighted improvement method to improve cell locations and wiring paths. According to the present invention, there is provided a method according to accompanying claim 1. Preferably, the cells in the semiconductor device are flip-flops (F/F elements) of a gate array connected to an associated one of clock I/O elements surrounding the F/F elements. By means of the present invention, since the wiring capacitance of the cell-placement area (component placement region) from the I/O element is lower than a predetermined wiring capacitance, an intended wiring capacitance can be obtained as long as the designer arranges the cells within the component placement region. Furthermore, since the component placement region specifies only the wiring capacitance, it is not necessary to precisely determine the cells constituting the specific network, and thus a degree of freedom exists in the arranging of the cells within the component placement region, taking the connection relationship of other cells into account. Reference is made, by way of example, to the accompanying drawings, in which:- Figs. 1A and 1B are schematic views of a semiconductor device having a substrate on which components are placed in a predetermined arrangement; Fig. 2 is a schematic diagram of a circuit construction of a semiconductor device shown in Fig. 1; Fig. 3 is a schematic diagram of a semiconductor device after the component placement is completed, embodying the present invention, by way of an example; Fig. 4 is a diagram of a map showing an arrangement of components, by way of an example; Figs. 5 to 9 are diagrams showing consecutive steps of a wiring process according to the present invention; Fig. 10 is a flow chart of a placement process of the components according to the present invention; and Fig. 11 is a flow chart of the wiring process of the components according to the present invention. As shown in Figs. 1A, 1B and 2, a substrate 11 has a plurality of arrays of components 12, which are flip-flops (F/F elements, or cells) in this embodiment. The row (horizontal direction) and column (vertical direction) of the array are designated by I and J, respectively. Namely, in the illustrated embodiment, the substrate has 12 rows of F/F elements, and each row has 13 columns of elements (12I x 13J). The substrate 11 also has a plurality of clock I/O cells 5 located in the vicinity of the circumferential edge of the substrate 11 and surrounding the F/F elements 12. The spaces 13 between the rows of F/F element 12 and the I/O elements 5 and the spaces 14 between the rows of F/F elements 12 define wiring regions. Upon determining the placement of the elements 12 constituting a specific network 1 (Fig. 1B) and the wiring of the F/F elements 12 to a specific I/O element 5 associated therewith on the substrate 11, a desired wiring capacitance of the specific network 1 is precalculated to set a component placement region 2 (Fig. 1B). Thereafter, as shown in Fig. 1A, a wiring path 3 is assumed to be such that the wiring capacitance from the specific I/O element 5 (which is usually an I/O element 5 closest to the component placement region 2) is lower than the predetermined value mentioned above, in the wiring regions 13 and 14. Namely, the adjacent cells 12 are successively connected by a conductor 7 until the wiring capacitance reaches but does not exceed the predetermined value. Thereafter, when the wiring path 3 is determined such that the wiring capacitance is lower than and closest to the predetermined wiring capacitance, all of the elements 12 connected to each other by the assumed wiring path 3 define the component placement region 2. Subsequently, as can be seen in Fig. 1B, the wiring of the elements 12 in the specific network 1 is performed within the component placement region 2, and finally, the connection (wiring) of the elements 12 to the specific I/O element 5 is carried out to thereby complete the specific network 1. As can be understood from the above, in the present invention, the component placement region 2 is that in which the wiring capacitance is lower than a predetermined wiring capacitance, and accordingly, as long as a design is such that the placement of the elements 12 in the specific network 1 is within the component placement region 2, neither an adjustment of the placement of the elements 12 nor rewiring are necessary, resulting in an increased efficiency of the component placement and wiring operations. Further, the component placement and the wiring are determined such that the predetermined wiring capacitance is not exceeded. Note, the component placement region 2 specifies only the wiring capacitance, and thus it is not necessary to precisely position the elements 12 constituting the specific network 1. It should be also understood that, although the above description is directed to the determination of one component placement region 2 for a predetermined wiring capacitance, it is also possible to select an optimum component placement region for a predetermined wiring capacitance from among a plurality of component placement regions obtained, by changing the direction of the extension of the conductors of the elements 12 (wiring). The following description provides more details of the component placement process and wiring process. Figure 3 shows the clock I/O elements 5 and the F/F elements 12 on the substrate 11, wherein regions represented by an oblique hatching and vertical hatching designate the associated F/F elements 12 in the objective region (specific network 1) and other F/F elements (forbidden region), which are of no concern, respectively. With reference to the flow chart shown in Figs. 10 and 11, assuming that the F/F elements 12 represented by the oblique hatching in the objective region (specific network) 1 are to be connected to the specific clock 1/O element 5 closest to the objective region 1, as shown in Fig. 3, the number I1 of rows I of the elements 12 needed when placing all of the F/F element 12 when a predetermined number of columns J is used is first calculated at step S101. In the illustrated embodiment, the total number N of the F/F elements 12 (i.e., the number of regions represented by the oblique hatching in Fig. 3) is 34 (N = 34), and the predetermined number of columns, i.e., a total number of columns of the substrate 11, is 13 (i.e., J=13). The necessary number I1 of rows is given by the equation: I1 = N/J. Thereafter, at step S103, it is determined whether I1 is larger than a predetermined number, for example, 4. If I1 is equal to or smaller than 4, the control proceeds to step S105, at which I1 is made 4 (I1 = 4). If I1 is larger than 4 at step S103, the necessary number J1 of columns J needed when placing all of the F/F elements 12 when the necessary number I1 of rows is used, is calculated at step 5107. Subsequently, at step S109, the necessary number J2 of columns J needed when placing all of the F/F elements 12 in accordance with a restriction imposed in view of a predetermined wiring capacitance and a predetermined drive capacitance of the associated clock I/O element 5 when the necessary number I1 of rows is used, is calculated. Then at step S111 it is determined whether J1 is larger than J2. If J1 is equal to or larger than J2, the control proceeds to step S113 and I and J are made I1 and J1, respectively (I = I1, J = J1). If J1 is smaller than J2 at step S111, the control proceeds to step S115 and I1 is incremented by I1 + 2. This is because, as can be seen from Fig. 3, two rows of F/F elements 12 constitute one unit. Thereafter, at step S117, it is determined whether or not I1 is larger than half the total number of rows I (the total number of rows is 12 in the illustrated embodiment). If I1 ≦ I/2,the control returns to step S107. Conversely, if I1 >I/2, at step S119 I and J are made values giving a largest number of F/F elements 12 restricted as mentioned above to within from 4 to I/2. Then, at step S121, the location of the specific network 1 is determined in accordance with the location of the associated clock I/O element 5 on the substrate (semiconductor chip) 11 so that, in step S123, the F/F elements 12 to be connected to the associated clock I/O element 5 are arranged in the thus determined specific network. After the completion of the arrangement of all of the F/F elements 12, the wiring process is performed by the steps shown in Fig. 11. First, at step S201, a wiring map as shown in Fig. 4 is prepared for the objective region (specific network 1). Figure 4 shows rows of F/F elements 12 and wiring channels 20 between the rows of the F/F elements 12. Thereafter, at step S203, the vertical lines (main lines) 21 are drawn on all of the wiring channels 20 in the specific network 1 (Fig. 3), as shown in Fig. 5, and then at step S205, the segments of horizontal lines (branch lines) 23 are extended from the F/F elements 12 to intersect the associated main lines 21 as shown in Fig. 6. The branch lines 23 are extended until they intersect the associated main lines 21, provided that no forbidden region exists on the extension. At step S207, the intersecting points of the branch lines 23 and the main lines 21 are memorized as a choice, and at step S209, one vertical line 21′ most weighted, i.e., having a largest number of intersecting points is provisionally determined, as shown in Fig. 7. The most weighted main line 21′ is the second from the left in the illustrated embodiment. After the provisional determination of the most weighted main line 21′ at step S211, all of the branch lines 23 which intersect the provisionally determined main line 21′ are processed as "have been treated", and thereafter, it is determined at step S213 whether or not all of the branch lines 23 have been treated. Namely, the provisional determination of the most weighted main line is effected for all of the branch lines 23 (i.e., all of the F/F elements 12). If the answer is negative at step S213, the control is returned to step S209, and the processes after step S209 are repeated until the treatment of all of the branch lines 23 is completed. In the illustrated embodiment, the main line 21″ next to the main line 21′ mentioned above is selected as a most weighted main line among the remaining main lines 21, at the second provisional determination of the most weighted main line, as shown in Fig. 8. When all of the branch lines 23 have been treated, at step S215 it is determined whether a branch line 23 exists which extends through more than one wiring channel 20. In the illustrated embodiment, two branch lines 23,23′ extend through more than one wiring channel 20. If the result at step S215 is Yes, the control proceeds to step S217 at which it is determined whether the branch line(s) intersects or intersect more than one main lines 21. If the branch line(s) intersects or intersect more than two main lines, at step S219 the closest main line is selected as shown in Fig. 9. Thereafter, at step S221, the wiring process is carried out to connect the F/F elements 12 to the associated clock I/O element 5 by conductors; these are usually realized by a predetermined pattern of printed conductors. If no branch line extends through more than one wiring channel 20 at step S215, or if no branch line intersects more than one main line at step S217, the provisionally determined main lines are determined (selected) as the formal main lines at step S221, and thereafter, the control fihally proceeds to step S223 at which the necessary wiring is carried out. Although the elements 12 are F/F elements in the illustrated embodiment, the elements are not limited thereto, as mentioned before. Namely, the elements 12 can be logic circuits, gate elements, or other electronic elements. As understood from the foregoing, according to the present invention, the component placement and the wiring thereof can be effectively performed so that a predetermined wiring capacitance is not exceeded, without a replacement and a rewiring of the elements.

Claims: A method of arranging circuit cells in a semiconductor device to form at least one specific network (1), the semiconductor device comprising an array of circuit cells arranged in a plurality of rows and a plurality of columns on a semiconductor substrate with wiring channels (14,20) between the rows and a plurality of signal outputting circuits (5) surrounding the circuit cells (12); wherein the method comprises: a placement process for determining a cell-placement area (2) required to form the specific network (1) and extending over part of the array of circuit cells (12), by: (a) precalculating a desired value of wiring capacitance of the specific network (1); (b) selecting one of the signal outputting circuits to be associated with the specific network(1); (c) assuming that a wiring path (3) extends from the selected signal outputting circuit (5) and is successively connected to circuit cells (12) arranged adjacent to the signal outputting circuit (5) until the wiring capacitance becomes the precalculated value; and (d) defining the cell-placement area (2) as the area which contains all of the circuit cells connected to the signal outputting circuit (5) by the assumed wiring path; and wherein the method further comprises a wiring process for connecting the circuit cells within the cell-placement area (2) so as to form the specific network(1) by: (i) preparing a wiring map in which a plurality of the circuit cells contained in the cell-placement area (2) are associated for use in forming the specific network(1); (ii) drawing a main line (21) along each wiring channel within the cell-placement area (2); (iii) extending branch lines (23) from said associated circuit cells (12) to intersect the main lines orthogonally; (iv) memorizing the intersecting points of the branch lines (23) and the main lines (21); (v) determining a most weighted main line (21') as the main line having the largest number of intersecting points; (vi) designating those branch lines (23) which intersect the most weighted main line (21') as having been treated; (vii) if not all branch lines have been treated, successively repeating steps (v) and (vi) for the next most weighted main line (21") among the remaining main lines (21), until all the branch lines (23) have been treated; (viii) determining whether any branch line extends through more than one wiring channel, and if so, whether it intersects more than one main line; (ix) for any branch line (23) intersecting more than one main line (21), terminating the branch line at its intersection with the main line closest to the circuit cell (12) from which it extends; and (x) connecting the associated circuit cells (12) to the signal outputting circuit (5) by conductors extending along the branch lines and the main lines intersected by the branch lines. A method according to claim 1, wherein the semiconductor device is a gate array, the circuit cells are flip-flop elements, and the signal outputting circuits are clock I/O elements (5).

Inventors: NISHIOKA SEISHI, OKADA ATSUHIKO, NISHIOKA, SEISHI, OKADA, ATSUHIKO
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, G06F17, H01L21