Apparatus for controlling musical sounds in accordance with an input waveform signal

Abstract: An input waveform signal is converted into a digital peak value signal by an A/D converter (8), and the digital peak value signal is input to one input ter­ minal A of a comparator (42). The other input terminal B of the comparator (42) receives a preset digital peak value signal from a memory (43). These input signals are compared by the comparator (42). The content of the memory (43) is reduced at a predetermined rate. If the comparator (42) detects that the currently input wave­ form level is larger than the continuously reduced level of the memory, i.e., if A > B, a new waveform level is loaded in the memory (43). As a result, the output from the comparator is inverted. That is, condition A > B is changed into condition A < B. The timing of this change in condition serves as a peak timing of the input wave­ form signal.

Description: The present invention relates to an electronic apparatus capable of controlling a musical sound to be generated, according to the preamble of claim 1. An electronic apparatus of that type is known from GB-A-2 138 988 . This known apparatus comprises a conversion means for converting an input waveform signal, said input signal for example being a human voice signal or any other tone information signal. This known apparatus further comprises a control means for controlling a musical sound to be outputted in accordance with the respectively converted signal. It thereby is possible to derive a musical sound which has a close relationship to the respectively converted input signal. The a.m. control means, in general, is a digital controller; therefore, the output signal of the conversion means is subjected to an analog/digital-conversion before being applied to the digital controller. In order to save costs, however, the number of bits of the digital processing units is restricted to for example 8 bits. It thus is difficult to process an input signal which comprises a long signal part of low value, like the decreasing signal part of a string envelope signal (see for example Fig.7 of the present invention); namely, the A/D conversion of such a signal will have the effect that a remarkable part of the signal envelope will fall below a threshold value so that the note-on time thereof will be shortened, the generated sound thus being unnaturally. It is therefore the object of the present invention to further develop an electronic apparatus capable of controlling a musical sound according to the preamble of claim 1 in such a way that it is possible to generate natural sounds without remarkably increasing the production costs of the apparatus. This object is solved by the advantageous features indicated in the characterizing part of claim 1. Hence, according to the present invention, the conversion means comprises a waveshape-compression means for converting the input waveform signal into a waveshape-compressed signal by a predetermined waveshape-compression conversion, wherein the control means is coupled to this waveshape-compression means such that the musical sound is controlled in accordance with the waveshape-compressed signal derived from the respective input waveform signal. Therefore, it is easily to process an input signal which comprises a long signal part of low value without the effect that this part of the signal will fall below a threshold value; consequently, the whole envelope of the signal can be digitally processed with a comparatively small number of bits. Thus, the production costs of the apparatus are not increased by a digital design having a great number of bits Further advantageous developments of the present invention are subject-matter of the subclaims. The present invention will be shown in more detail by the description of an embodiment thereof with reference to the accompanying drawings, in which: Fig. 1 is a diagram showing an overall arrangement of an embodiment of the present invention; Figs. 2A and 2B are diagrams showing a detailed arrangement of a pitch extraction analog circuit in Fig. 1; Fig. 3 is a timing chart for explaining the operation of the pitch extraction analog circuit; Fig. 4 is a diagram showing a detailed arrangement of a log converter in Fig. 2B; Fig. 5 is a graph for explaining characteristics of a iog converter in Fig. 4; Fig. 6 is a timing chart for explaining the operation of the pitch extraction analog circuit shown in Figs. 2A and 2B; Figs. 7(a) and 7(b) are graphs for explaining the function of the log converter shown in Fig. 4; Fig. 8 is a block diagram of a pitch extraction digital circuit shown in Fig. 1; Figs. 9(a) and 9(b) are a diagram and a waveform chart, respectively, of a peak detector shown in Fig. 8; Fig. 10 is a diagram showing a detailed arrangement of the peak detector; Fig. 11 is a timing chart showing the operation of the circuit in Fig. 10; Fig. 12 is a diagram showing a detailed arrangement of a time constant conversion control circuit in Fig. 8; Fig. 13 is a diagram showing a detailed arrangement of a zero-crossing time receiving circuit in Fig. 8; Fig. 14 is a diagram showing a detailed arrangement of a peak value receiving circuit in Fig. 8; Fig. 15 is a timing chart for explaining the operation of the circuit shown in Fig. 10; Fig. 16 is a timing chart for explaining the operation of the time constant conversion control circuit in Fig. 12; Fig. 17 is a timing chart for explaining the operation of the circuit shown in Fig. 13; and Figs. 18(a) and 18(b) are timing charts for explaining an operation of the embodiment in response to an input waveform signal. A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. The present invention is applied to an electronic guitar but can also be applied to electronic musical instruments of other types or other electronic systems. Fig. 1 is a block diagram showing an overall circuit arrangement. Pitch extraction analog circuit PA to be described in detail later is arranged for each of six strings which are kept taut on an electronic guitar body (not shown). Circuit PA includes a hexa pickup for converting string vibrations into electrical signals and a converting means such as analog-to-digital converter A/D (to be described in detail later) for outputting zero-crossing signals Zi and waveform signals Wi (i = 1 to 6) on the basis of outputs from the pickup and converting these signals into time-divisional serial zero-crossing signal ZCR and digital output (time-divisional waveform signal) D1. Pitch extraction digital circuit PD will be described later. Digital circuit PD includes peak detector PEDT, time constant conversion control circuit TCC, peak value receiving circuit PVS, and zero-crossing time receiving circuit ZTS, as shown in Fig. 8. Digital circuit PD detects the positive or negative peak value on the basis of zero-crossing signals Zi, serial zero-crossing signal ZCR, and digital output D1, all of which are output from pitch extraction analog circuit PA, generates MAXI and MINI (I = 1 to 6) and outputs interrupt signal INT at a zero-crossing to microcomputer MCP. In addition, pitch extraction digital circuit PD outputs time information and peak value information at the zero-crossing, and an instantaneous value of the input waveform signal to microcomputer MCP through bus BUS. Peak detector PEDT includes a circuit for subtracting previous peak values and holding a subtracted value. Microcomputer MCP includes memories (e.g., a ROM and a RAM) and timer T and controls signals supplied to musical tone generator SOB. Generator SOB comprises sound source SS, digital-to-analog converter D/A, amplifier AMP, and loudspeaker SP and generates a musical tone having a pitch designated by a pitch designation signal for changing a frequency and controlled by the signals of note-on (tone generation) and note-off (muting) which are supplied from microcomputer MCP. Interface MIDI (Musical Instrument Digital Interface) is arranged between the input side of sound source SS and the microcomputer MCP. In response to address read signal AR, address decoder DCD outputs string number read signal RDI , time read signal RDj (j = 1 to 6), and MAX and MIN peak read signals RDAI (I = 1 to 12) to pitch extraction digital circuit PD. Figs. 2A and 2B are circuit diagrams showing a detailed arrangement of pitch extraction analog circuit PA in Fig. 1. Input waveform signals corresponding to the respective strings and output from the hexa pickup are supplied to input terminals 11 to 16 of low-pass filters (LPFs) 21 to 26, respectively. These signals are amplified, and their high-frequency components are removed, so that the fundamental waveforms are extracted. Since a frequency of an output tone of each string falls within a predetermined two-octave range, these LPFs have different cutoff frequencies in units of strings. Outputs from low-pass filters 21 to 26, are supplied as waveform outputs W1 to W6. The outputs from the low-pass filters 21 to 26 are also input to zero-crossing comparators 31 to 36, respectively, and are compared with a reference signal, thereby generating zero-crossing signals Z1 to Z6. Zero-crossing signals Z1 to Z6 are input to an input section of zero-crossing parallel-to-serial converter 4 comprising AND gates a1 to a6 and OR gate 1. More specifically, signals Z1 to Z6 are respectively input to AND gates a1 to a6 which are sequentialiy enabled in response to pulses 1 to 6 (to be described later), so that signals Z1 to Z6 are converted into serial zero-crossing signal ZCR. In this case, converter 4 outputs serial zero-crossing signal ZCR of logic "1" if values of signals Z1 to Z6 are positive. However, converter 4 outputs serial zero-crossing signal ZCR of logic "0" if the values of signals Z1 to Z6 are negative. Waveform outputs W1 to W6 from low-pass filters 21 to 26 are input to the input section of analog parallel-serial converter 5, i.e., analog gates g1 to g6. Analog gates g1 to g6 are sequentially enabled in response to pulses 1 to 6, so that outputs W1 to W6 are converted into an analog serial signal. In this case, gates g1 to g6 are enabled when pulses 1 to 6 are set at high level. However, analog gates g1 to g6 are disabled when pulses 1 to 6 are set at low level. An output from converter 5 is input to inverting amplifier (OP1) 6 connected to resistors r1 and r2. The positive and negative waveforms are converted into positive waveforms. More specifically, serial zero-crossing signal ZCR from converter 4 is directly input to analog gate g7 and to the gate terminal of analog gate g8 through inverter i1. An output from inverting amplifier 6 is input to the input terminal of analog gate g8. Therefore, the output from analog gate g8 always has a positive value. Analog gate g7 is enabled in response to serial zero-crossing signal ZCR of logic "1", and outputs from analog gates g1 to g6 are gated to the output terminal. Therefore, the output signals always have positive values. Outputs from analog gates g7 and g8 are input to log converter 7. The waveform data is log-converted by log converter 7 into compressed data. Necessary memory bits are eliminated. An output from log converter 7 is converted into digital output D1 by analog-to-digital converter (to be referred to as an A/D converter hereinafter) 8 in accordance with a logical state of A/D conversion clock signal ADCK. Fig. 3 is a timing chart for explaining the operation of pitch extraction analog circuit PA in Fig. 2. Sequential pulses 1 to 6 are output from timing generator TG (Fig. 8) (to be described later) and are generated in order upon every interval corresponding to two periods of A/D conversion clock signal ADCK. Serial zero-crossing signal ZCR generated in response to pulses 1 to 6 represents a zero-crossing of each string. Digital output D1 represents peak values (the polarity is inverted to obtain a positive value) of each string. Digital output D1 is delayed by a conversion time of A/D converter 8 from sequential pulses 1 to 6. This delay time can be corrected in a manner to be described later. Referring to Fig. 3, reference symbols Q5 and MO5 denote timing signals output from pitch extraction digital circuit PD shown in Fig. 8, and functions of these signals will be described later. Fig. 4 is a circuit diagram showing a detailed arrangement of log converter 7 in pitch extraction analog circuit PA shown in Figs. 2A and 2B. Log converter 7 comprises a four-polygonal approximation log converter but is not limited thereto. Log converter 7 comprises inverting amplifiers OP3 and OP4, transistors T1, T2, and T3, and resistors R0, R0, R1, R2, R3, R4, R, R, R/2, and R/4. Resistances of resistors R2 to R4 are determined to obtain voltage VOUT below: R2 = (1/2)VDD - 0.6v R3 = (3/4)VDD - 0.6v R4 = (7/8)VDD - 0.6v With this arrangement, (1) If condition VOUT < (1/2)VDD is established, transistors T1 to T3 are kept off. In this case, gain A can be calculated to be 4 according to the following equation: A = VOUT/VIN = R/(R/4) = 4 (2) If condition (1/2)VDD < VOUT < (3/4)VDD is established, transistors T2 and T3 are kept off. However, since the emitter voltage vs. base voltage of transistor T1 exceeds -0.6v, transistor T1 is turned on. Most of the emitter current flows in the collector. For this reasons a feedback resistance of second inverting amplifier OP4 is given as R/2. Gain A is reduced into 1/2 that of case (1), i.e., 2 as follows: A = [1/(1/R + 1/R)]/(R/4) = 2 (3) If condition (3/4)VDD < VOUT < (7/8)VDD is established, transistors T1 and T2 are turned on while transistor T3 is kept off. In this case, gain A can be calculated to be 1 according to the following equation: A = [1/(1/R + 1/R + 2/R)]/(R/4) = 1 (4) If condition (7/8)VDD < VOUT is established, transistors T1 to T3 are turned on. Gain A can be calculated to be 0.5 according to the following equation: A = [1/(1/R + 1/R + 2/R + 4/R)]/(R/4) = 0.5 Fig. 5 is a graph of characteristics showing the relationship between input voltage VIN and output voltage VOUT in log converter 7 arranged as shown in Fig. 4. Fig. 6 is a timing chart showing sequential pulse 1, waveform output W1, input voltage VIN of log converter 7, output voltage VOUT, and serial zero-crossing signal ZCR in the arrangement of Figs. 2A and 2B when the first string is picked. As is apparent from Fig. 6, data is log-compressed by log converter 7 to reduce the number of bits. Figs. 7(a) and 7(b) show string vibration envelopes before and after conversion in log converter 7. When the string vibration envelope shown in Fig. 7(a) is input to log converter 7, the envelope shown in Fig. 7(b) can be obtained. Attention should be paid for a note-on time. When the waveform shown in Fig. 7(a) is converted by A/D converter 8 to obtain a note-off region having a value below a given threshold value, the note-on time is short. However, when a note-off operation is performed with the threshold value after the log conversion, as shown in Fig. 7(b), the note-on time can be prolonged. Therefore, tone generation control can cope with an abrupt attenuation in string vibration in this embodiment. Log converter 7 is not arranged in pitch extraction digital circuit PD, i.e., log conversion is not performed in the digital circuit. Log converter 7 is arranged in pitch extraction analog circuit PA to perform log conversion in the analog circuit due to the following reason. For example, assume that A/D converter 8 comprises an 8-bit converter and a note-off threshold value in Fig. 7(b) is 3. In order to prolong the note-on time in Fig. 7(a) as in Fig. 7(b), a threshold value must be set to be 3/4 = 0.75. This threshold value cannot be set without replacing the A/D converter. It is possible to perform the above setting if a 10-bit converter having the number of bits larger than the currently used converter by 2 bits is used. However, a circuit arrangement becomes expensive by an increase in cost of the converter. Fig. 8 is a schematic block diagram of pitch extraction digital circuit PD in Fig. 1. Pitch extraction digital circuit PD comprises peak detector PEDT for receiving serial zero-crossing signal ZCR and detecting MAX and MIN peaks, time constant conversion control circuit TCC for converting a time constant of peak detector PEDT, zero-crossing time receiving circuit ZTS, peak value receiving circuit PVS, timing generator TG for generating various timing signals, e.g., sequential pulses 1 to 6,and timing signals ADCK, Q5, MO5, and MC. These components will be described in detail below. Figs. 9(a) and 9(b) are a schematic diagram and a waveform chart, respectively, for explaining peak detector PEDT. More specifically, Fig. 9(a) is a circuit diagram of a positive side of the vibrations of one string. In principle, 12 circuits in Fig. 9(a) are required. In practice, however, 12 circuits need not be arranged to process vibrations of a plurality of strings according to a time-divisional technique. This technique will be described in detail later with reference to Fig. 10. A log-converted waveform signal from log converter 7 in pitch extraction analog circuit PA is input to A/D converter 8 and is converted into digital output D1 every time A/D conversion clock signal ADCK from timing generator TG in Fig. 8 is input. Digital output D1 is input to one input terminal of comparator 42 (this input value is defined as A). A/D converter 8 is identical with the one shown in Fig. 2. Its characteristics are also illustrated in Fig. 9(a) for illustrative convenience. A storage value from memory 43 is input to the other input terminal B of comparator 42 (this value is defined as B). If A > B, comparator 42 outputs a signal of "H" level, i.e., logic "1". Otherwise, comparator 42 outputs a signal of "L" level, i.e., logic "0". Memory 43 can store an output from A/D converter 8 or an output from subtracter 44. Output selection is performed by data selection switch 46. That is, if the output from comparator 42 is set at logic "1", switch 46 is switched to the "1" side, so that the output from A/D converter 8 is loaded in memory 43. However, if the output from comparator 46 is set at logic "0", switch 46 is switched to the "0" side, so that the output from subtracter 44 is loaded in memory 43. The storage value from memory 43 is directly input to one input terminal A of subtracter 44. A value obtained by multiplying the storage value of memory 43 with 1/n through, e.g., shifter 45 is input to the other input terminal B of subtracter 44. Subtracter 44 calculates a difference (A - B), and the difference appears at output terminal S. Shifter 45 subtracts, e.g., a 1/256 value of the storage value from the storage value of memory 43. Therefore, subtracter 44 performs the following calculation: S = A - B = A - (1/256)·A Value B may be a constant independently of value A. However, according to the above equation, S is exponentially changed, and good characteristics can be obtained. With the above arrangement, when the waveform signal (input to comparator 42) shown in Fig. 9(b) is input to comparator 42, a MAX peak detection signal shown in Fig. 9(b) is output from comparator 42. That is, when the output from A/D converter 8 which serves as an input to comparator 42 rises, the output from comparator 42 rises and goes to logic "1". When the input to comparator 42 is smaller than the storage value of memory 43, the output from comparator 42 falls and goes to logic "0". An output from A/D converter 8 advances to a negative half wave period and then toward the positive side. When the output from A/D converter 8 reaches the storage value of memory 43, the output from comparator 42 rises and goes to logic "1". When the output from A/D converter 8 reaches the MAX peak, the output from comparator 42 falls and goes to logic "0". In this manner the MAX peak of comparator 42 can be detected. A divider may be used in place of shifter 45. Figs. 18(a) and 18(b) are timing charts for explaining the operations of the circuit in Fig. 9. More specifically, Fig. 18(a) shows the relationship between the peak and zero-crossing when the input waveform signal is large. Fig. 18(b) shows the relationship between the peak and zero-crossing when the input waveform signal is small. Peak and zero-crossing detection can be performed even if the magnitude of the input waveform signal is the one shown in Fig. 18(a) or 18(b). Fig. 18(a) shows a waveform including second harmonic overtones. According to this embodiment, a time interval between zero-crossings immediately after the peaks can be measured, as will be apparent from a subsequent description. Therefore, the harmonic overtones are eliminated and period detection can be performed (T in Fig. 18(a) is the period). Even in the waveform shown in Fig. 18(b), a reduction rate of memory 43 must be taken into consideration in order to eliminate harmonic overtones as in Fig. 18(a). If the input waveform is large, processing must be fast; and if the input waveform is small, processing must be slow. In this embodiment, by attenuating the contents of memory 43 according to an exponential curve, good harmonic overtone elimination can be performed in both the cases in Figs. 18(a) and 18(b). Fig. 10 shows a detailed circuit arrangement of peak detector PEDT shown in Fig. 8. A storage value stored in memory 43, e.g., twelve 12-bit shift registers ( 6[strings] × 2[(maximum (positive) or minimum (negative) peak holding)] = 12 ) is input to gate GATE1, and gate GATE1 is enabled or disabled in response to control signal PR from gate control circuit GATEC. An output from gate GATE1 is input to shifter 45, and an output from shifter 45 is input to one input terminal of subtracter 44. The storage value from memory 43 is directly input to the other input terminal of subtracter 44. Timing signal MO5 from timing generator TG in Fig. 8 is input to clock terminal CK of memory 43. The contents of memory 43 are shifted to the right in response to the leading edge of timing signal MO5. Shifter 45 performs shifting at a rate of, e.g., 1/256 (8-bit shifting) or 1/16 (4-bit shifting). Switching between 8- and 4-bit shifting is controlled by time constant change signal GX. Gate control circuit GATEC comprises 2-bit counter COW1, OR gates OR1 to OR4, and AND gates a10 and a11. Since sequential pulse 1 is input to the input terminal of counter COW1, sequential pulses 1 and 2 input to OR gate OR2 are directly gated therethrough and are supplied as control signal PR, as shown in the timing chart in Fig. 11. Similarly, since pulses 3 and 4 are output through AND gate a11, these pulses are output as one control signal PR per two cycles, i.e., during the period in which the QA output is set at logic "1". Similarly, pulses 5 and 6 are output as one control signal PR per four cycles, i.e., when QA and QB outputs are simultaneously set at logic "1". This control signal serves as a gate enable signal for gate GATE1. A subtraction operation for the first and second strings is performed by subtracter 44 every cycle. A subtraction operation for the third and fourth strings is performed every other cycle. A subtraction operation for the fifth and sixth strings is performed in every fourth cycle due to the following reason. The string vibration of the high-pitch strings (i.e., the first string side) tends to be abruptly attenuated. The string vibration of the low-pitch strings (i.e., sixth string side) tends to be slowly attenuated. The reduction rate of the first- and second-string contents in memory 43 is large, while the reduction rate of the fifth- and sixth-string contents in memory 43 is small. The reduction rate of the third- and fourth-string contents in memory 43 is intermediate. The rate may be changed in units of strings. Alternatively, The change in rate may be performed for string groups, or for a group of first to third strings and a group of fourth to sixth strings. An output from gate GATE1 enabled at high level of control signal PR, that is, an output read out from memory 43, is supplied to shifter 45. The shift amount of shifter 45 can be changed by time constant change signal GX, as described above. Subtracter 44 performs the following operations: If time constant change signal GX is set at logic "0", the following operation is performed: S = R (1 - 1/256) - 1 However, if time constant change signal GX is set at logic "1", the following operation is performed: S = R(1 - 1/16) - 1 Subtracter 44 includes carry-in input terminal CIN. Therefore, an output can be reduced even if the other input terminal, i.e., the B input side, of subtracter 44 is set at logic "0". If the operation of subtracter 44 is strictly synchronized with control signal PR from gate control circuit GATEC, control signal PR is supplied to carry-in input terminal CIN. With this arrangement, "-1" calculations in the above equations are performed whenever the content of memory 43 is supplied to subtracter 44 through gate GATE1 and shifter 45. When a signal of logic "1" is supplied from OR gate OR5, the upper eight bits of an output from subtracter 44 are input to memory 43 through data selection switch 46. The lower four bits are input to memory 43 through AND gates a7 to a10. When a signal of logic "0" is supplied from OR gate OR5, new digital output D1 from A/D converter 8 is supplied to memory 43 through data selection switch 46 due to the following reason. An output from OR gate OR5 is input to input terminal SE of data selection switch 46 and AND gates a7 to a10. Digital output D1 from A/D converter 8 is input to one input terminal A of comparator 42. A storage value (upper eight bits) from memory 43 is input to the other input terminal B of comparator 42. Digital output D1 input to one input terminal A of comparator 44 is also input to the other input terminal of data selection switch 46. An output from comparator 42 is input to one input terminal of OR gate OR5 through inverter IV1. An output from exclusive OR gate EX is input to the other input terminal of OR gate OR5. Serial zero-crossing signal ZCR from pitch extraction analog circuit PA and AD conversion timing signal ADCK from timing generator TG are input to the input terminals of exclusive OR gate EX. Therefore, when signal ZCR coincides with signal ADCK, an output from exclusive OR gate EX is set at logic "0". When the output from exclusive OR gate EX is set at logic "0", i.e., when signal ZCR coincides with signal ADCK and new digital output D1 exceeds a storage value of memory 43 an output from OR gate OR5 is set at logic "0". As described above, new digital output D1 is loaded in memory 43 through data selection switch 46 (in this case, lower four bits are all "0"s). When the output from exclusive OR gate EX is set at logic "1", i.e., when signal ZCR does not coincide with signal ADCK, an output from OR gate OR5 is set at logic "1". The output from subtracter 44 is input to memory 43, but new digital output D1 is not input thereto. Similarly even if signal ZCR coincides with signal ADCK, if condition A < B is established in comparator 42, an output from OR gate OR5 is set at logic "1". Therefore, new digital output D1 is not supplied to memory 43. Serial zero-crossing signal ZCR, the output from comparator 42, and timing signals Q5 and ADCK from timing generator TG are respectively input to AND gates A1 to A4 in the serial-to-parallel converter. Outputs from AND gates A1 to A4 and sequential pulses 1, 2,... 6 from timing generator TG are supplied to AND gates a11max, a12max,... a62max and a11min, a12min,... a62min. Outputs from AND gates a11max, a11min,... a62min are input to flip-flops FF1a, FF1b,... FF6b and converted into parallel peak signals MAXI and MINI (I = 1 to 6). When A/D conversion clock signal ADCK is set at logic "1", outputs from up (positive) AND gates A1 and A2 are set at logic "1". However, if A/D conversion clock signal ADCK is set at logic "0", outputs from down (negative) AND gates A3 and A4 are set at logic "1". When serial zero-crossing signal ZCR is set at logic "1" and the output from comparator 42 is set at logic "0", AND gate A1 supplies a "1" output to AND gate aI1max (I = 1 to 6) to set outputs of MAXI (I = 1 to 6) to be low level while A/D conversion clock signals ADCK and Q5 are set at logic "1". Therefore one of flip-flops FF1a to FF6a is reset. Similarly, AND gate A2 supplies a "1" output to AND gates aI2max (I = 1 to 6) to set outputs of MAXI (I = 1 to 6) to be high level when serial zero-crossing signal ZCR is set at logic "1" and the output from comparator 42 is set at logic "1" while A/D conversion clock signal ADCK and timing signal Q5 are kept at logic "1". Therefore, one of flip-flops FF1a to FF6a is reset. AND gate A3 supplies a "1" output to AND gates aI2min (I = 1 to 6) to set MINI (I = 1 to 6) to be low level when serial zero-crossing signal ZCR is set at logic "0" and the output from comparator 42 is set at logic "0" while A/D conversion clock signal ADCK is set at logic "0" and timing signal Q5 is set at logic "1". One of flip-flops FF1b to FF6b is reset. AND gate A4 supplies a "1" output to AND gates aI2min (I = 1 to 6) to set MINI (I = 1 to 6) to be high level when serial zero-crossing signal ZCR is set at logic "0" and the output from comparator 42 is set at logic "1" while A/D conversion clock signal ADCK is set at logic "0" and timing signal Q5 is set at logic "1". One of flip-flops FF1b to FF6b is reset. Fig. 15 is a timing chart for explaining the operation of Fig. 10 showing the case in which a peak signal of MIN1 is output from flip-flop FF1b. A storage value stored in memory 43 is input to the A input terminal of subtracter 44 at the leading edge of timing signal MO5. In this case, these storage value are input in an order of 1U (positive side of the first string), 1D (negative side of the first string),... 6D (negative side of the sixth string). Values obtained by bit-shifting the storage value of memory 43 by shifter 45 at a predetermined rate after gate GATE1 is enabled in accordance with control signal PR obtained by sequential pulses 1 to 6 are input to the B input terminal of subtracter 44. The output from comparator 42 is set at logic "1" only when digital output D1 from A/D converter 8 is larger than the storage value of memory 43 input to the A input terminal of subtracter 44. Flip-flop FF1b is set due to generation of a set timing signal obtained when timing signal Q5 is set at logic "1" and A/D conversion clock signal ADCK is set at logic "0". In this case, the MIN1 peak signal appears at output terminal Q of flip-flop FF1b. Other flip-flops FF1a, FF2a to FF6a, and FF2b to FF6b are operated in the same manner as in flip-flop FF1b. MAX1 to MAX6 peak signals as parallel signals are output from flip-flops FF1a to FF6a, and MIN1 to MIN6 peak signals as parallel signals are output from flip-flops FF1b to FF6b. Fig. 12 is a block diagram of time constant conversion control circuit TCC (Fig. 8) constituting pitch extraction digital circuit PD (Fig. 1). This circuit arrangement represents a circuit portion corresponding to the first string. In practice, six identical circuits are used for the six strings. When write signal WR1 is input to register (MREG) RG, data from microcomputer MCP is written therein. In this case, waveform vibrations must be immediately detected in the initial duration of the string vibrations. For that reason, tone period data corresponding to the highest fret of the string is written in the register RG during the note-off time. When the string vibration is detected, the open string period data of the string, i.e., the lowest tone period, data of the string is written in the register RG in order not to pick up harmonic overtones. When the vibration period of the picked string is detected, the corresponding period data is written in the register RG. MIN1 (Fig. 16) from peak detector PEDT is input to clear terminal CL of MIN1 timer TM1 through inverter IV4. MAX1 (Fig. 16) from peak detector PEDT is input to clear terminal CL of MAX timer TM2 through inverter IV3. Timers TM1 and TM2 are cleared when MIN and MAX are set at logic "1". Outputs from timers TM1 and TM2 are input to the A input terminals of comparators CO1 and CO2, respectively, and compared with an output from register RG. If inputs at the A and B input terminals coincide with each other, signals output from comparators CO1 and CO2 are input to the CK terminals of D flip-flops F2 and F1, respectively. Outputs from inverters IV4 and IV3 are input to the CL terminals of flip-flops F2 and F1, respectively. Flip-flops F2 and F1 are cleared when the MIN1 and MAX1 peak signals are set at logic "1". Outputs from flip-flops F1 and F2 are input to the first input terminals of 3-input AND gates A5 and A6, respectively. A/D conversion clock signal ADCK is input to the second input terminals of AND gates A5 and A6. Sequential pulse 1 is input to the third input terminals of AND gates A5 and A6. Outputs from AND gates A5 and A6 are input to OR gate OR6. As output from OR gate OR6 is input to OR gate OR7. As shown in Fig. 12, A/D conversion clock signal ADCK is directly input to AND gate A5, and an inverted signal thereof is input to AND gate A6. In this circuit, if A/D conversion clock signal ADCK is set at logic "1", an output from flip-flop F1 is set at logic "1, and sequential pulse 1 is set at logic "1", then a "1" output appears from AND gate A5. If A/D conversion clock signal ADCK is set at logic "0", an output from flip-flop F2 is set at logic "1", and sequential pulse 1 is set at logic "1", then a "1" output appears from AND gate A6. When one of the "1" outputs from AND gates A5 and A6 appears, an output of logic "1" is output from OR gate OR6. Therefore, time constant change signal GX is output from OR gate OR7. Signal GX is normally set at logic "0". However, signal GX goes high when a time set in register RG has elapsed. By switching the number of stages of shifter 45 shown in Fig. 10, the register contents of memory 43, i.e., the positive or negative peak value of the first string in this case, are damped at high speed (Fig. 16). Fig. 13 is a circuit diagram showing a detailed arrangement of zero-crossing time receiving circuit ZTS (Fig. 8) constituting pitch extraction digital circuit PD (Fig. 1). This circuit arrangement represents a only circuit portion for the first string. MAX1 from peak detector PEDT is input to the R input terminal of R-S flip-flop F3. Zero-crossing signal Z1 of the first string is input to the S input terminal of R-S flip-flop F3 through inverter IV5. An output (51 in Fig. 17) from the Q output terminal of flip-flop F3 is input to the D input terminal of D flip-flop F5. MIN1 from peak detector PEDT is input to the R input terminal of R-S flip-flop F4. Zero-crossing signal Z1 of the first string is input to the S input terminal of flip-flop F4. An output (52 in Fig. 17) from the Q output terminal of flip-flop F4 is input to the D input terminal of D flip-flop F6. The CK terminals of flip-flops F5 and F6 receive clock signal MC from timing generator TG in Fig. 8. Flip-flops F5 and F6 receive input signals from their D input terminals in response to the leading edge of clock signal MC. These input signals appear at the Q output terminals of flip-flops F5 and F6 and are input to the first input terminals of AND gates A7 and A8. The second input terminals of AND gates A7 and A8 receive outputs from the Q output terminals of flip-flops F3 and F4, respectively. Outputs (53 and 54 in Fig. 17) from AND gates A7 and A8 are input to NOR gate NOR and to the S and R input terminals, respectively, of R-S flip-flop F7. An output (55 in Fig. 17) from NOR gate NOR is input to the CK terminal of D flip-flop F8 and the CK terminal of D flip-flop F9. An output (56 in Fig. 17) from flip-flop F7 is input to the D0 input terminal of flip-flop F9. Time read signal RD1 (Fig. 17) from decoder DCD in Fig. 1 is input to the CL terminal of flip-flop F8 and the OE terminal of flip-flop F9. An output from time base counter COW2 is input to the D1 to D15 input terminals of flip-flop F9. Reference voltage VDD is input to the D input terminal of flip-flop F8. The input terminal of gate GATE2 receives an output (57 in Fig. 17) from flip-flop F8 (circuit corresponding to the first string) and outputs from flip-flops (not shown) corresponding to the second to sixth strings. String number read signal RD1 is input to the OE terminal of gate GATE2. An output from gate GATE2 is input to microcomputer MCP through bus BUS. The input terminals of AND gate A9 receive an output from NOR gate NOR corresponding to the first string and outputs from NOR gates (not shown) corresponding to the second and sixth strings. Therefore, common interrupt signal INT for all the strings is input to microcomputer MCP. Fig. 17 is a timing chart for explaining the operation of zero-crossing time receiving circuit ZTS in Fig. 13. Reference symbol MC denotes a clock signal input to flip-flops F5 and F6 and counter COW2; MAX1 and MIN1, detection signals from peak detector PEDT; and Z1, a zero-crossing signal for the first string. Reference numeral 51 denotes an output from flip-flop F3; 52, an output from flip-flop F4; 53, an output from AND gate A7; 54, an output from AND gate A8; 55, an output from NOR gate NOR; 56, an output from flip-flop F7; and 57, an output from flip-flop F8. Reference symbol RD1 denotes a time read signal; and INT (the same as 55), an interrupt signal. Referring to Figs. 13 and 17, when flip-flop F3 is reset in response to MAX1 and zero-crossing signal Z1 goes low and is input to flip-flop F3, output 51 from flip-flop F3 is set at logic "1". At the same time, the output from flip-flop F5 goes low (because clock signal MC is enabled). One-shot pulse output 53 having the same pulse width as that of clock signal MC is output from AND gate A7. Therefore, the next MAX1 zero-crossing point to the positive peak determined by MAX1 is detected. When flip-flop F4 is reset in response to MIN1 and zero-crossing signal Z1 input to flip-flop F4 goes high, output 52 from flip-flop F4 is set at logic "1". At the same time, an output from flip-flop F6 goes low (as clock signal MC is input). One-shot pulse output 54 having the same pulse width as that of clock signal MC is output from AND gate A8. Therefore, the next zero-crossing point to the negative peak determined by MIN1 is detected. Flip-flop F7 is set in response to an output from AND gate A7. Flip-flop F7 is reset in response to an output from AND gate A8. An output from flip-flop F7 is input to LSB input terminal D0 of flip-flop F9. Therefore, the polarity of the peak (if the peak is positive, the output is "1"; and if the peak is negative, the output is "0") is determined. NOR gate NOR outputs a "0" output when one of the outputs from AND gates A7 and A8 is set at logic "1". In this case, interrupt signal INT from AND gate A9 is output to microcomputer MCP. Microcomputer MCP supplies string number read signal RDI to gate GATE2 to detect the string number corresponding to the generated interrupt signal INT. Microcomputer MCP detects the string number, and outputs one of time read signals RD1 to RD6 so as to read out the content of flip-flop F9 corresponding to the designated string. At this time, flip-flop F8 is cleared. Time information of the time base counter (i.e., time base counter COW2 in Fig. 13) latched by flip-flop F9 at the zero-crossing is read out and is input to microcomputer MCP through bus BUS. As a result, zero-crossing time (the contents of Q1 to Q15 of flip-flop F9) of the designated string number is read out in units of polarities, i.e., positive signal (U) and negative signal (D). Fig. 14 is a detailed circuit diagram of the peak value receiving circuit (Fig. 8) in pitch extraction digital circuit PD (Fig. 1). Digital output D1 from A/D converter 8 is input to the D input terminals of D flip-flops F11 to F16. If digital output D1 represents an output from the first string, for example, output D1 is input to flip-flop F11 which receives sequential pulse 1 from its CK terminal through inverter IV11. An output from the Q output terminal of flip-flop F11 is input to the D input terminals of D flip-flops F21 and F22 and gate GATE23. The OE terminal of gate GATE23 receives read signal RDA13 from microcomputer MCP. Microcomputer MCP can fetch an instantaneous value of digital output D1 in accordance with its operation. MAX1 from peak detector PEDT is input through inverter IV21 to the CK terminal of flip-flop F21 for receiving the output from flip-flop F11 at a maximum peak timing. In order to read the output from flip-flop F11 at a minimum peak timing, MIN1 from peak detector PEDT is input to the CK terminal of flip-flop F22 through inverter IV22. Outputs from the Q output terminals of flip-flops F21 and F22 are input to gates GATE11 and GATE12, respectively. The OE terminal of gate GATE11 receives MAX value red signal RDA1 , and the OE terminal of gate GATE12 receives the MIN value read signal. Outputs from gates GATE11 and GATE12 are input to microcomputer MCP through bus BUS. Flip-flops F12 to F16, F23 to F32, gates GATE24 to GATE28, and inverters IV12 to IV32 for other strings are arranged in the same manner as for the first string. Referring to Fig. 14, when digital output D1 from A/D converter 8 is commonly supplied to flip-flops F11 to F16 and sequential pulses 1, 2,... 6 go low, digital outputs D1 are latched by flip-flops F11 to F16 corresponding to sequential pulses 1 to 6 at the respective timings. In other words, the waveform signals input time-divisionally in units of strings are set in corresponding flip-flops F11 to F16. Digital output D1 is input to flip-flops F21 to F32 and to gates GATE11 to GATE22 or gates GATE23 to GATE28 through flip-flops F21 to F32. When peak value read signals RDAI (I = 2, 4,... 12) are input, negative peak values MIN1 to MIN16 are read out. However, when peak value read signals RDAI (I = 1, 3,... 11) are input, positive peak values MAX1 to MAX6 are read out. When peak value read signals RDAI (I = 13 to 18) are input, the corresponding instantaneous amplitude values are output to microcomputer MCP through bus BUS. Note that the MAX values, the MIN values, and the peak values are used to control tone generation (note-on operation) and muting (note-off or release operation). Microcomputer MCP reads out the zero-crossing time of a string represented by interrupt signal INT from zero-crossing time receiving circuit ZTS (Fig. 13) whenever microcomputer MCP receives interrupt signal INT from pitch extraction digital circuit PD. Microcomputer MCP also reads out the peak level (this peak level may be positive or negative, so that the polarity of the peak level is designated) immediately preceding interrupt signal INT from peak value receiving circuit PVS (Fig. 14). The above operations are repeated, and microcomputer MCP can calculate a length of time between the zero-crossings. Therefore, the period of string vibrations can be extracted. Microcomputer MCP can also detect the tone generation and muting timings on the basis of the peak level and the instantaneous level. Therefore, microcomputer MCP can designate the pitch, the volume the start of tone generation, the start of muting on the basis of the above-mentioned information. The period information can be obtained after the start of tone generation. Therefore, a change in frequency of tone based on an operation such as checking operation or an operation with a tremolo arm after the starting of tone generation can be accurately detected and processed in a real-time basis. The embodiment described above has the following advantages. (1) The circuit arrangement for supplying the input waveform signal detected by pitch extraction analog circuit PA and supplied to musical tone generator SOB is constituted by a digital circuit, i.e., pitch extraction digital circuit PD. Therefore, inaccurate input waveform signal peak detection caused by variations in circuit components, degradation of durability, and deteriorations over time as in the conventional apparatus can be prevented. (2) Peak detector PEDT in pitch extraction digital circuit PD processes the signals according to the time-divisional multiplex scheme, as shown in Fig. 10. Circuits (hardware) respectively corresponding to the strings need not be arranged, thus reducing the number of circuit components and achieving a compact, inexpensive circuit arrangement. (3) The condition parameters for pitch extraction can be easily changed. For example, the change rate (attenuation rate) of the peak hold level can be easily changed by signal PR or GX. If the same function as in this embodiment is to be obtained by an analog circuit arrangement, different time constant circuits must be used. (4) The peak timing of the input waveform signal from pitch extraction analog circuit PA can be accurately detected in accordance with an output from comparator 42 in Fig. 9. That is, the value obtained by converting the input waveform signal of pitch extraction analog circuit PA into digital waveform signal A by A/D converter 8 is compared with predetermined digital waveform signal B stored in memory 43, and the peak timing is detected on the basis of the comparison result. (5) The maximum and minimum peaks of the input waveform signal can be accurately detected in units of strings. In the above embodiment, the present invention is applied to an electronic guitar. However, the present invention is also applicable to electronic musical instruments of other types or an electronic tuning apparatus. The above-mentioned circuits may be properly modified in accordance with a change in number of strings, and the like. In the above embodiment, the positive (maximum) and negative (minimum) peaks detected. However, period information can be calculated from the positive or negative peaks, and both the positive and negative peaks need not be detected. It is apparent that response and pitch extraction precision are improved if both peak values are used as compared with detection using one of the peak values. In the above embodiment, an interrupt signal (INT) is input to microcomputer MCP at the next zero-crossing (immediately) after the peak point. Pitch extraction of the string vibration is performed on the basis of the time information between the zero-crossings. However, pitch extraction is not limited to this technique. A time interval between the corresponding peak points, i.e., between the adjacent maximum peak points or between the adjacent minimum peak points may be calculated to extract the pitch on the basis of the calculated time information. If a peak point and a corresponding peak point or a waveform point corresponding to the detected peak point are detected and the pitch is extracted the present invention is applicable. In addition, in the above embodiment, peak levels (MAX and MIN) of the respective peak points are detected, and the detection results are used for volume control. However, only the start of tone generation may be designated, and peak value detection is not essential. According to the present invention as has been described above, peak detection can be performed with high precision and condition parameters for pitch extraction can be easily changed in a simple, inexpensive arrangement regardless of variations in circuit components and deteriorations over time.

Claims: An electronic apparatus capable of controlling a musical sound to be generated, said apparatus comprising a conversion means for converting an input waveform signal and a control means for controlling said musical sound in accordance with the respectively converted signal, characterized in that said conversion means comprises a waveshape-compression means (7; Fig.4) for converting said input waveform signal into a waveshape-compressed signal by a predetermined waveshape-compression conversion; and in that said control means (PD, MCP) is coupled to said waveshape-compression means (7; Fig.4) such that said musical sound is controlled in accordance with the waveshape-compressed signal derived from said input waveform signal. Electronic apparatus according to claim 1, characterized in that said waveshape-compression means (7; Fig.4) performs said waveshape-compression conversion with a compression factor which is increased proportionally to an increasing amplitude of said input waveform signal. Electronic apparatus according to claim 2, characterized in that said waveshape-compression means (7; Fig.4) performs said waveshape-compression conversion logarithmically. Electronic apparatus according to one of claims 1 to 3, characterized in that said control means (PD, MCP) controls a note on/off-operation and/or a sound volume of said musical sound in accordance with the waveshape-compressed signal derived from said input waveform signal. Electronic apparatus according to one of claims 1 to 4, characterized by an A/D converting means (8) which is coupled to an output of said waveshape-compression means (7; Fig.4) such that the waveshape-compressed signal derived therefrom is converted to a digital signal which subsequently is supplied to said control means (PD, MCP) . Electronic apparatus according to one of claims 1 to 5, characterized by a pitch extracting means (PD, MCP) for extracting a pitch of said input waveform signal, wherein a pitch of said musical sound is determined in accordance with said extracted pitch. Electronic apparatus according to one of claims 1 to 6, characterized by a compressed peak level signal obtaining means (F21-F32 in Fig.14; 42-46, FF1a-FF6a and FF1b-FF6b in Fig.10) which operates to obtain a compressed peak level signal of said input waveform signal from said waveshape-compression means (7;Fig.4) .

Inventors: UCHIYAMA SHIGERU C O PAT DPT D, UCHIYAMA, SHIGERU, UCHIYAMA, SHIGERU, C/O PAT. DPT. DEV. DIV. HAMURA
Applicants: CASIO COMPUTER CO LTD, CASIO COMPUTER COMPANY LIMITED
Application year: 1990
Main classification: G10H1
IPC codes: G10H1, G10H3, G10H7