Digital signal reproducing apparatus

Abstract: A digital signal reproducing apparatus wherein an analogue signal corresponding to stored digital data is processed to generate a digital data signal, includes an analogue-to-digital converter (4) operative to convert the analogue signal to a digital signal, a decoder (13) to decide the digital signal, and a memory (6) interposed between the converter (4) and the decoder (13) to remove time base components from the digital signal. The analogue signal is converted to the digital signal and the digital signal is read into the memory (6) at a first clock rate. The digital signal is read out from the memory (6) and subsequently decoded at a second clock rate.

Description: This invention relates to digital signal reproducing apparatus. More particularly, but not exclusively, the invention relates to a digital signal reproducing apparatus suitable for use in decoding a digital signal generated by a playback head in a digital video tape recorder (VTR). The invention also relates to associated methods. In a digital VTR, direct current (DC) components in recorded digital data used by a playback head (hereinafter referred to as the 'reproduced signal') to generate a corresponding signal can be lost because of a differential characteristic of the tape-and-head system. For this reason a decoding circuit is used in a reproducing radio frequency (RF) circuit of the digital VTR (hereinafter referred to as the 'reproducing RF circuit') to restore the lost DC components while decoding a digital video signal stored on the tape. In Figure 1 there is illustrated a previously proposed reproducing RF circuit of a digital VTR. As illustrated, a digital signal recorded on a tape 51 is reproduced by a head 52, that is, a representative electrical signal is generated by the head 52 in dependence on a sensed magnetic signal. The signal on the tape 51 can be quantitized by, for example, eight bits. The reproduced signal is supplied to an analogue decoding circuit 54 via an amplifier 53 (hereinafter a 'reproducing amplifier'). The analogue decoding circuit 54 decodes the reproduced signal and generates a digital video signal. However, because of a differential characteristic of the tape-and-head system (that is, the tape 51 and the head 52), DC components can be lost in the reproduced signal. To compensate for this loss of the DC components, after high frequency components in the reproduced signal have been reinforced by the analogue decoding circuit 54, the reproduced signal is integrated. By integrating the reproduced signal, the DC components are restored. Thus, the digital video signal represents a decoded version of the original signal on the tape 51. As further illustrated in Figure 1, the digital video signal is supplied to a time base correction (TBC) circuit 57 via a data latch 56. In parallel, the amplified reproduced signal is supplied from the reproducing amplifier 52 to another input of the TBC circuit 57 via a clock reproducing circuit 55. The TBC circuit 57 is used to eliminate time base variable components in the reproduced signal. The clock reproducing circuit 55 serves to generate a bit clock signal BCK11 from the reproduced signal. It is this signal BCK11 that is supplied to the TBC circuit 57. Additionally, the bit clock signal BCK11 is supplied to the data latch 56. Under control of the bit clock signal BCK11 supplied thereto, the data latch 56 latches the output of the decoding circuit 54 in synchronization with the bit clock signal BCK11. Similarly, the digital video signal is clocked into a memory of the TBC circuit 57 at a rate determined by the bit clock signal BCK11. The TBC circuit 57 is also supplied with an additional reference clock signal SCK11 that is generated by a reference clock generator 59. The TBC circuit 57 can thus eliminate time-base variable components in the reproduced signal because the digital video signal latched into the memory of the TBC circuit 57 is read out with a timing based on the reference clock signal SCK11. The TBC circuit 57 is also capable of detecting a sync pattern in the reproduced signal. This sync pattern is used to determine a conversion rate for converting serial data to parallel data. An output of the TBC circuit 57 is supplied to a signal processing circuit 58. The signal processing circuit 58 is also supplied with the reference clock signal SCK11 by the reference clock generating circuit 59. The signal processing circuit 58 then performs the usual signal processing under control of the reference clock signal SCK11. This reproducing RF circuit in which the decoding circuit 54 is in the form of an analogue circuit, is influenced by, for example, temperature changes. As a result, the operation of the reproducing RF circuit of Figure 1 is unstable. To overcome this instability problem, another circuit arrangement has been employed. This circuit arrangement is illustrated in Figure 2. In the circuit arrangement of Figure 2, instead of using the analogue decoding circuit 54, the reproduced signal is first converted to a digital signal by an A/D converter 60, and then the digital signal is decoded by a digital decoder 61. In this manner, the influence of temperature is eliminated because the digital signal and digital circuits will not be as easily influenced by changes in temperature. Because the reproduced signal includes time base components which are subject to A/D conversion by the AID converter 60, high-speed components must be used. Each time base component must be identified for A/D conversion or it could be lost. To this end, high-speed components such as ECL must be used in the digital decoding circuit 61, in view of the time base variation. However, use of such high speed components in the digital decoder 61 requires large scale technology wherein power consumption is greater. Further, use of such high-speed components can increase manufacturing costs. Patents Abstracts of Japan, Vol. 010, No. 179 (E-414) of 24 June 1986, relating to JP-A-61 026 381, describes a digital signal reproducing apparatus with A/D converter means, memory means having an input clocked in response to a first clock, and an output clocked in response to a second clock, and decoding means. Radio and Electronic Engineer, Vol. 53, No. 10, October 1983, London, at pages 361-368 in an article by Bellis "Introduction to Digital Audio Recording", describes the use of a FIFO for timing correction on replaying a recorded signal. In accordance with a first aspect of the invention, there is provided a digital signal reproducing apparatus, comprising: means for generating an analogue signal corresponding to stored digital data; A/D converter means for converting said analogue signal corresponding to said stored digital data into a digital signal at a rate determined by a first clock signal derived from information contained in said analogue signal; memory means having an input for receiving said digital signal at a rate determined by said first clock signal and an output for supplying said digital signal at a rate determined by a second clock signal; and decoder means for decoding said digital signal supplied by said memory means at a rate determined by said second clock signal thereby to generate a digital data signal, characterised in that: said memory means input and said memory means output are resettable via reset signals applied thereto, and said apparatus includes first circuit means for generating a first reset signal for said memory means input and second circuit means for generating a second reset signal for said memory means output with a time delay relative to said first reset signal. In accordance with a second aspect of the invention, there is provided a method of reproducing a digital signal, the method comprising the steps of: generating an analogue signal corresponding to digital data stored in a recording medium; converting said analogue signal to a digital signal at a rate determined by a first clock signal derived from information contained in said analogue signal; storing said digital data in memory means at a rate determined by said first clock signal; reading said digital signal out from said memory means at a rate determined by a second clock signal; and decoding said digital signal read out from said memory means at said rate determined by said second clock signal to produce a digital data signal, characterised by: resetting said memory means input and said memory means output in response, respectively, to first and second reset signals, said second reset signals being generated with a time delay relative to said first reset signals. In one embodiment, therefore, the invention provides a digital signal reproducing apparatus comprising: an A/D converter that converts a reproduced signal derived from digital data stored on a recording medium to a digital signal at a rate determined by a first clock signal; a digital decoder that decodes the digital signal to produce a digital data signal; and a memory interposed between the A/D converter and the digital decoder for eliminating time-base variable components of the reproduced signal by receiving the digital signal at a rate determined by the first clock signal and by supplying the digital signal to the digital decoder at a rate determined by a reference clock signal. In a particular embodiment, the memory comprises a first-in-first-out (FIFO) register. An advantage of embodiments of the invention is that since the digital decoder is operated at a rate determined by the reference clock signal, which does not include time-base variable components, high-speed electronic devices need not be used in the digital decoder. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figures 1 and 2 show respective previously proposed digital signal reproducing apparatus in block diagrammatic form; Figure 3 is a block diagram of an embodiment of digital signal reproducing apparatus according to the invention; Figures 4A to 4F are timing charts of signals in the apparatus of Figure 3. In Figure 3, an embodiment of the invention is illustrated. As can be seen, data recorded on a tape 1, such as a video tape, is sensed and reproduced by a tape head 2 as an electrical signal hereinafter referred to as the reproduced signal. The reproduced signal is supplied to an A/D converter 4 via an amplifier 3, hereinafter referred to as the reproducing amplifier 3. Simultaneously, the reproduced signal is supplied from the reproducing amplifier 3 to a clock reproducing circuit 5. The clock reproducing circuit 5 generates a clocking signal referred to as the reproducing bit clock signal BCK. The reproducing bit clock signal BCK is also supplied to the A/D converter 4 to provide a clocking signal for clocking data into the A/D converter 4. Thus, at a rate determined by the reproducing bit clock signal BCK, the amplified reproduced signal is converted into a digital signal. The digital signal output of the A/D converter 4 is supplied to a memory 6, preferably a first-in-first-out (FIFO) register. The FIFO register 6 is supplied with the reproducing bit clock signal BCK which determines the rate at which the digital signal output of the A/D converter is written into the FIFO register 6. The FIFO register 6 is also provided with a reference clock signal SCK generated by a reference clock circuit 7. The reference clock signal SCK controls the rate at which the digital signal is read out of the FIFO register 6. The FIFO register 6 is also provided with an input reset pulse signal and an output reset pulse signal. These reset pulse signals are generated from a tape head switching signal RFSW provided at a terminal 8. The input reset pulse signal is generated by a differentiating circuit 10 whose output is coupled to the FIFO register 6. The output reset pulse signal is generated by another differentiating circuit 12 after the tape head switching signal has been subjected to a delay in a delay circuit 11. Figure 4A is a timing diagram for the tape head switching signal RFSW. Figure 4B is a timing diagram for the input reset pulse signal provided to the FIFO register 6. Figure 4C is a timing diagram for the reproducing bit clock signal BCK. Figure 4D is a timing diagram for the tape head switching signal RFSW after being subjected to a delay. Figure 4E is a timing diagram for the output reset pulse signal provided to the FIFO register 6. Figure 4F is a timing diagram for the reference clock signal SCK. As illustrated in Figures 4A to 4F, the tape head switching signal RFSW has a step function. Whenever the tape head switching signal RFSW has a transition, that is at the appearance of the leading or trailing edge thereof, an input reset pulse signal is generated by the differentiating circuit 10 and supplied to the FIFO register 6 (Figure 4B). Thus, whenever the tape head switching signal RFSW transitions, the input buffer of the FIFO register 6 is reset. At that time, the individual data of the digital signal output of the A/D converter 4 are sequentially written into the FIFO register 6 in synchronization with the reproducing bit clock signal BCK (Figure 4C). The delay of the tape head switching signal RFSW induced by the delay circuit 11 as it is supplied to the differentiating circuit 12 is illustrated in Figure 4D. As illustrated, the delay circuit 11 introduces a delay of ta in the tape head switching signal RFSW. As illustrated in Figure 4E, in a manner similar to that of the input reset pulse signal, the output reset pulse signal supplied to the output of the FIFO register 6 is generated at each transition of the delayed tape head switching signal RFSW. Thus, an output reset pulse signal is generated by the differentiating circuit 12 a time ta after generation of an input reset pulse signal by the differentiating circuit 10. As illustrated in Figure 3, the digital signal written into the FIFO register 6 is read out from the FIFO register 6 in synchronization with a reference clock signal SCK. The reference clock signal SCK is appropriately generated by a reference clock generator 7. Because of the use of different clock signals for reading the digital signal into and out from the FIFO register 6, time base variable components in the reproduced signal are eliminated. The digital signal output from the FIFO register 6 are supplied to a decoding circuit 13. As noted above, due to a differential characteristic of the tape-and-head system, low frequency components in the reproduced signal can be lost. However, these low frequency components are restored by the digital decoding circuit 13 in known manner. The decoding circuit 13 is clocked by the reference clock signal SCK generated by the reference clock circuit 7. Since the decoding circuit 13 is operated at a rate determined by the reference clock signal SCK that is free of time-base variation, high speed circuit components need not be used to construct the decoding circuit 13. The output of the decoding circuit 13 is referred to as a digital data signal and is supplied to a sync pattern detecting and byte synchronizing circuit 14 which converts the data in the digital data signal from serial form to parallel data form. The conversion is made in dependence on a detected sync pattern. An output of the synchronizing circuit 14 is supplied to a signal processing circuit 15 for processing in known manner. The signal processing circuit 15 is also supplied with the reference clock signal SCK from the reference clock circuit 7. In this embodiment, the case where a digital video signal is reproduced has been described. However, the invention can be widely applied to cases where other digital signals are reproduced. Moreover, this embodiment concerns a case where data recorded on a magnetic tape are reproduced. However, the invention can be widely applied to other recording media, for example a magnetic reproducing apparatus using a magnetic recording medium. Thus, time-base variable components in the reproduced signal are eliminated by the FIFO register 6 before the reproduced signal is decoded by the digital decoding circuit 13, and the decoding circuit 13 is operated based on the reference clock SCK which does not include time-base variable components. In this way, since the decoding circuit 13 operates with the reference clock SCK free of time-base variable components, a digital decoding circuit using high-speed devices need not be used. Therefore, it is possible to reduce the scale of the circuit, decrease its power consumption and decrease its manufacturing cost.

Claims: A digital signal reproducing apparatus, comprising: means (2) for generating an analogue signal corresponding to stored digital data; A/D converter means (4) for converting said analogue signal corresponding to said stored digital data into a digital signal at a rate determined by a first clock signal derived from information contained in said analogue signal; memory means (6) having an input for receiving said digital signal at a rate determined by said first clock signal and an output for supplying said digital signal at a rate determined by a second clock signal; and decoder means (13) for decoding said digital signal supplied by said memory means (6) at a rate determined by said second clock signal thereby to generate a digital data signal, characterised in that: said memory means input and said memory means output are resettable via reset signals applied thereto, and said apparatus includes first circuit means (10) for generating a first reset signal for said memory means input and second circuit means (11,12) for generating a second reset signal for said memory means output with a time delay relative to said first reset signal. Apparatus according to claim 1, wherein said first circuit means (10) is responsive to a timing signal (RFSW) to generate said first reset signal, and said second circuit means comprises delay circuit means (11) responsive to said timing signal (RFSW) and further circuit means (12) responsive to a delayed timing signal from said delay circuit means (11) to generate said second reset signal. Apparatus according to claim 2, wherein said timing signal is a head switching signal. Apparatus according to any one of the preceding claims, wherein said second clock signal comprises a reference clock signal generated by a reference clock generator (7). Apparatus according to any one of the preceding claims, wherein said memory means is a first-in-first-out register (6). A method of reproducing a digital signal, the method comprising the steps of: generating an analogue signal corresponding to digital data stored in a recording medium (1); converting said analogue signal to a digital signal at a rate determined by a first clock signal derived from information contained in said analogue signal; storing said digital data in memory means (6) at a rate determined by said first clock signal; reading said digital signal out from said memory means (6) at a rate determined by a second clock signal; and decoding said digital signal read out from said memory means (6) at said rate determined by said second clock signal to produce a digital data signal, characterised by: resetting said memory means input and said memory means output in response, respectively, to first and second reset signals, said second reset signal being generated with a time delay relative to said first reset signal. A method according to claim 6, wherein said first reset signal is derived from a timing signal (RFSW), said timing signal is delayed and said second reset signal is derived from said delayed timing signal. A method according to claim 7, wherein said timing signal is a head switching signal. A method according to any one of claims 6 to 8, wherein said second clock signal comprises a reference clock signal generated by a reference clock generator (7). A method according to any one of claims 6 to 9, wherein said memory means is a first-in-first-out register (6).

Inventors: INOUE HAJIME, SEKI TAKAHITO, INOUE, HAJIME, SEKI, TAKAHITO, INOUE, HAJIME, C/O PATENTS DIVISION, SEKI, TAKAHITO, C/O PATENTS DIVISION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H04N9
IPC codes: H04N9, G11B20