Mixed technology intergrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called "smart power" type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: the drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any "level shifting" stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

Description: BACKGROUND OF THE INVENTION 1. Field of the invention The present invention relates to a mixed technology, "smart power", integrated device containing power transistors and control logic and analog driving circuitry combined in a monolithic silicon chip. 2. Description of the prior art The commercial success of so-called "smart power" integrated circuits, wherein the analog signal processing circuitry, the control logic circuitry and the output power devices are conveniently monolithically integrated in a single chip, originated and sprung from the overcoming of compatibility problems among the different fabrication processes relative to the different integrated devices, often necessarily operating under different supply voltages. Most often, even though nonexclusively, the power section of such integrated circuits employs VDMOS transistors which typically require a driving gate voltage level comprised between about 10V - 20V. This makes difficult interfacing the power transistor (e.g. VDMOS) with the driving circuitry. Commonly, in fact, the maximum operating voltage of CMOS transistors used in logic circuitry is 5V. Conversely, the driving circuitry for power transistors operate at about 12V, while in order to ensure a driving level on the gate of a VDMOS power transistor of 10V and if a reasonable process "spread" is accounted for, the supply voltage of CMOS transistors of the relative driving circuit should be at least 15V. Moreover better operating conditions of a VDMOS power transistor (i.e. a lower resistance R on ) may be achieved if the driving voltage level on the gate may be raised to 15-20V, as it is well known to a skilled technician. In "smart power" type integrated circuits, this particular problem is commonly obviated by using a "level shifter" circuit, which necessarily makes the driving circuit more complicated. GB-A-2 186 117 discloses a semiconductor device comprising bipolar transistors, CMOS and vertical DMOS transistors. There is a definite need for the availability of CMOS transistors having an operating voltage of about 20V in a monolithically integrated semiconductor device of the "smart power" type in order to drive directly the output power transistors with a relatively high voltage without employing special level shifter circuits. On the other hand, in these integrated circuits there are other CMOS and bipolar transistors which are employed, because of their peculiar characteristics, in control logic circuitry and in signal processing circuitry, respectively. Also the utility and reliability of these other integrated devices could be advantageously enhanced if also these other integrated devices could be made capable of withstanding a higher supply voltage than the voltage normally allowed by the physical structure of these integrated devices produced through a mixed-technology fabrication process. OBJECTIVE AND SUMMARY OF THE INVENTION In view of this state of the art, the present invention has the main objective of providing, in a monolithically integrated "smart power" type device, CMOS structures and isolated collector, vertical, PNP transistors capable of withstanding a higher operating voltage than the voltage normally withstood by these devices, when they are formed monolithically together in a single chip. This objective is reached by the integrated device of the invention, as defined in the annexed claims. Structurally the device is characterized by the fact that it comprises regions of phosphorus doped, n-type silicon of similar diffusion profile extending from the surface of the n-type epitaxial layer wherein the different devices are formed, respectively, through the drain area of n-channel LDMOS transistors extending between the gate electrode thereof and the adjacent isolating field oxide, the body area of p-channel LDMOS transistors, extending between the gate electrode thereof and the adjacent isolation field oxide, the drain area of n-channel MOS transistors, extending between the gate electrode thereof and the adjacent isolation field oxide, and the emitter area of isolated collector vertical PNP bipolar transistors, and by a depth sufficient to contain, respectively, the n + doped drain region of n-channel LDMOS transistors, the p + doped source region of p-channel LDMOS transistors, the n + doped drain region of n-channel MOS transistors and the p + doped emitter region of the PNP transistors. In the case of an n-channel LDMOS transistor, the presence of this auxiliary n-doped region, obtained by implanting phosphorus through the drain area, increases the breakdown voltage because the field intensity between the drain and the gate is reduced while obtaining a reduction too of the conducting resistance (R on ) of the transistor, which is extremely advantageous when the LDMOS transistor itself is used as an integrated power switching device, as it is often the case in these mixed technology integrated devices. In the case of a p-channel LDMOS transistor, the same auxiliary n - doped region may conveniently constitute a body region which is so formed without other specific additional process steps. The CMOS structures formed by pairs of complementary LDMOS transistors, when provided with such an n-doped region by phosphorus implantation, become capable of operating with a supply voltage of about 20V without requiring special precautions, such as "field plates", thus remaining advantageously compact. In the case of an n-channel MOS transistor belonging to another type of CMOS structure, the n-doped region, obtained by phosphorus implantation in the drain area of the transistor, reduces the sensitivity to electrical stresses due to hot electrons, by acting as a "drain extension" region; this permits to the transistor to withstand a supply voltage of about 12V. In the case of an isolated collector, vertical PNP bipolar transistor, the additional n-doped region obtained by phosphorus implantation through the emitter area of the transistor, permits to improve the transistor's performance transistors by increasing the charge in the base region of the transistor and to increase the "punchthrough" voltage between emitter and collector. The parallel ability of the different CMOS structures and vertical PNP transistors to withstand a specifically increased operating voltage specifically increased permits to build mixed technology integrated circuits (i.e. "smart power" devices) with far less pronounced interfacing problems among the different types of circuits, with enhanced possibilities of fully exploiting the intrinsic peculiarities of the different devices and with a higher degree of reliability. BRIEF DESCRIPTION OF THE DRAWINGS The peculiar aspects and advantages of the present invention, will become evident through the following detailed description of a preferred embodiment illustrated as a non-limitative example in the attached drawings, wherein: Fig. 1 is a partial schematic, sectional view of an integrated circuit made in accordance with the present invention; Fig. 2 shows equimodal, electric field lines in the overlapping region between the gate and the drain region of an n-channel LDMOS transistor of the prior art, without the additional n-doped region of the invention, produced by computer simulation; Fig. 3 shows equimodal electric field lines in the same overlapping region of the preceding figure, in the case of a transistor provided with the additional n-doped region in accordance with the present invention, produced by computer simulation. DESCRIPTION OF THE BEST MODE An hypothetical partial cross section of an integrated "smart power" type integrated device, wherein it is relatively easy to put in evidence, though in a schematic way, the aspects of the invention, is shown in Fig. 1. The depicted cross section does not include VDMOS power transistors, which may be easily imagined present in a different zone of the integrated device from the zone shown in the partial cross section of the figure, wherein two different CMOS structures are depicted, a first structure formed by an n-channel and a p-channel LDMOS transistor and a second structure formed by a p-channel and by an n-channel MOS transistor, and the structure of an isolated collector, vertical PNP bipolar transistor. The device comprises a p-type silicon substrate 1 on which an epitaxial n-type silicon layer 2 has been grown after doping with arsenic and/or with boron certain areas defined on the surface of the monocrystalline silicon substrate 1 in order to form the n + buried layers 3 and the p-type bottom isolations 4. The integrated device further comprises an isolation structure among the different integrated devices which, in the depicted example, is formed by a field oxide layer 5 grown on the surface of the silicon 2, after doping with boron predifined areas on the silicon surface in order to form, in accordance with well known techniques, the p-well regions 6 (i.e. top isolations and p-well) as well as regions with a heavier boron doping charge 11, also known as p-field region, while growing the field oxide 5, according to a known technique. Within active areas destined to the formation of MOS-type devices, gate structures 12, commonly of doped polycrystalline silicon, are formed. Typically the n-channel, LDMOS transistor comprises a p-body region 7, produced in the silicon by implanting boron under self-alignment conditions in the source area extending between the gate 12 and the field oxide 5 and by successively diffusing the implanted boron until obtaining the desired diffusion profile of the region 7, the n + source and drain junctions 10 and the p + region 9 having a relatively high doping level formed in the source region for contacting the body region 7. Similarly a p-channel LDMOS transistor comprises a p-doped region 7 (having substantially the same profile of the n-channel LDMOS body region), formed in the drain region of the transistor, the p + drain and source junctions 9 and the n + region 10, formed in the source area in order to contact an n-body region, the formation of which together with other n-regions in the different integrated structures according to the present invention will be described later. The p-channel MOS transistor forming the second CMOS structure depicted in Fig. 1, comprises, as usual, the source and drain p + junctions 9 and a "back gate" contact, n + region 10, formed in the source zone of the transistor. Similarly the n-channel MOS transistor comprises the n + source and drain junctions 10 and a "back gate" contact, p + region 9, formed in the source zone of the transistor. The structure of the isolated collector PNP vertical transistor comprises the collector (C) and emitter (E) contact p + diffusions 9 and the base (B) n + contact diffusion 10. In accordance with the present invention, an n-type region 8, doped with phosphorus, extends from the surface of the epitaxial layer respectively in the drain area of the n-channel LDMOS transistor extending between the gate electrode and the isolation field oxide, in the source area of the p-channel LDMOS transistor extending between the gate electrode and the isolation field oxide, in the drain area of the n-channel MOS transistor extending between the gate electrode and the adjacent isolation field oxide and in the emitter area of the isolated collector PNP bipolar transistor defined by the surrounding isolation field oxide, for a depth sufficient to contain at least, respectively, the n + drain junction of the n-channel LDMOS transistor, the p + source junctions and n + body contact regions of the p-channel LDMOS transistor, the n + drain junction of the n-channel MOS transistor and the n + emitter junction of the PNP transistor. These n-type regions 8 are made evident in the schematic cross section depicted in Fig. 1 by means of a thick line. As it will be evident to the skilled technician, the distinct regions 8 may be easily formed simultaneously in the indicated zones without requiring critical process steps by simply implanting phosphorus under self-alignment conditions in the indicated areas and by diffusing the implanted phosphorus before proceeding to the formation of the heavily doped n + regions obtained by implanting arsenic and diffusing it and of the heavily doped p + regions obtained by implanting boron and diffusing it, which are contained within said auxiliary regions 8. In a normal fabrication process the doping level of this additional n-region 8 may be comprised between 10 13 and 10 14 (phosphorus) atoms per cubic centimeter. Shown in Fig. 2 are the equimodal electric field lines in the overlapping region between the drain and the gate of an n-channel LDMOS transistor having a 60 nm (600 Angstroms (Å)) thick gate oxide, produced by means of computer model simulation for the case of a transistor without the auxiliary n-doped region (8 of Fig. 1) in accordance with the present invention and subjected to a 20V bias. The maximum electric field intensity is evaluated to be 6 x 10 5 V/cm. Similarly, shown in Fig. 3 are the equimodal electric field lines in the same overlapping region under identical bias conditions (20V) of the example shown in Fig. 2, but wherein the n-channel LDMOS transistor is provided with the auxiliary n-region, doped with phosphorus at 10 14 atoms per cubic centimeter, in accordance with the present invention. As it is easily noted by comparing the Figures 2 and 3, in the latter the equimodal electric field lines are more "distended" than those of Fig. 1 and the maximum field electric intensity may be evaluated to be 5 x 10 5 V/cm. This is 17% less than the maximum intensity evaluated in the case of the transistor of the prior art without the auxialiary phosphorus doped region. The CMOS structure formed by the complementary LDMOS transistors provided with the n-doped region 8 (Fig. 1) in accordance with the present invention may funtions with a supply voltage of 20 V and it may be directly interfaced, as a driving device, with VDMOS power transistors for example, thus eliminating the need for adequate level shifting circuits. Moreover, an LDMOS transistor structure modified according to the invention is intrinsically capable of withstanding voltages in the order of 20V without requiring the formation of "field plates" (according to a known technique for increasing the intrinsic breakdown voltage of integrated transistors) which inevitably clashes with compactness requirements of these integrated structures. Naturally, as it will appear evident to the skilled technician, the complementary LDMOS transistors, depicted as forming a CMOS structure in Fig. 1, may themselves be employed as power transistors through an appropriate layout configuration, exploiting also for such applications, the same improved performance in terms of voltage withstanding ability and reduced resistance (R on ), derived by the presence of said additional n-region 8, in accordance with the present invention. Also the electrical performances of the other CMOS structure shown, formed by the pair of complementary MOS transistors, are improved because the n-region 8 formed in the drain region of the n-channel transistor acts as a drain extension region thus increasing the nominal operating voltage of the relative CMOS structure. Another, non-negligeable advantage is obtained also in terms of improved performance of the isolated collector, vertical PNP bipolar transistor by providing also this integrated device with the n-region 8 doped with phosphorus enchroaching in the base region of the transistor. The consequent increase of the doping level of the base region reduces sensitivity to depletion of the base region thus increasing the punchthrough voltage between emitter and collector. This permits also to this integrated component of the "smart power" device to function under a relatively high voltage, thus broadening the possibility of employing this type of transistor which is outstandingly suited, in respect to other types of transistors, for implementing circuits with a higher cut-off frequency then that which may be obtained by means of lateral PNP transistors.

Claims: A monolithically integrated circuit formed in an n-type epitaxial silicon layer (2) grown on a p-type monocrystalline silicon substrate (1) and comprising at least a first CMOS structure formed by a pair of complementary LDMOS transistors, the first having an n-type channel and the other a p-type channel, a second CMOS structure formed by a pair of complementary MOS transistors, a first having a p-type channel and the other an n-type channel, and at least an isolated collector, vertical PNP bipolar transistor, comprising first, second, third and fourth phosphorus doped n-type silicon regions (8) having the same diffusion profile which extend from the surface of said epitaxial layer, respectively in: a drain area of said n-channel LDMOS transistor defined between a gate electrode (12) of the transistor and an adjacent isolation field oxide (5), a source area of said p-channel LDMOS transistor defined between a gate electrode (12) of the transistor and an adjacent isolation field oxide (5), a drain area of said n-channel LDMOS transistor, defined between a gate electrode (12) of the transistor and an adjacent isolation field oxide (5), and an emitter area of said isolated collector, vertical PNP transistor, defined by a surrounding isolation field oxide (5), thereby extending into said epitaxial layer by a depth such that said regions contain, respectively: an n + drain diffusion (10) of said n-channel LDMOS transistor, a p + source diffusion (9) of said p-channel LDMOS transistor, an n + drain diffusion (10) of said n-channel MOS transistor, and a p + emitter diffusion (9) and further extending beyond said p + emitter diffusion into a base region of said isolated collector, vertical PNP transistor. A monolithically integrated circuit as defined in claim 1, wherein said first CMOS structure is able to withstand a supply voltage of up to 20V and said second CMOS structure is able to withstand a supply voltage of up to 12V. A monolithically integrated circuit as defined in claim 2 wherein said first CMOS structure has no field-plates.

Inventors: CONTIERO CLAUDIO, GALBIATI PAOLA, ZULLINO LUCIA, CONTIERO, CLAUDIO, GALBIATI, PAOLA, ZULLINO, LUCIA
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L29, H01L27