Controllable delay logic circuit for providing variable delay time

Abstract: A controllable delay logic circuit includes a differential circuit having first and second transistors (T1, T2), a first load (R L1 ) coupled between a first power supply line (GND) and the collector of the first transistor, a second load (R L11 ) coupled between the first power supply line and the collector of the second transistor, and a constant-current source connected between a second power supply line (V EE1 ) and the emitters of the first and second transistors. The controllable delay logic circuit also includes a first power source (V E , V CC2 ), a first current path circuit (D1, R L2 ; T6, R L2 ) having a first resistor (R L2 ) and selectively allowing a first current to pass through the first transistor from the first power source via the first resistor, and a second current path circuit (D2, R L21 ; T6, R L21 ) having a second resistor (R L21 ) and selectively allowing a second current to pass through the second transistor from the first power source via the second resistor.

Description: The present invention generally relates to a controllable delay logic circuit, and more particularly to an improvement in an arrangement of an emitter coupled logic circuit. There is known an emitter coupled logic circuit (hereinafter simply referred to as an ECL circuit) which is a high-speed digital logic circuit using a pair of transistors forming a current switch circuit. ECL circuits are widely used, as logic gates, in various large scale integrated circuits. An ECL circuit has an inherent propagation delay time. In some applications, the inherent propagation delay time of the ECL circuit is positively utilized. For example, a signal delay circuit is formed of the ECL circuit. Alternatively a variable length of coaxial tube is known as an element capable of providing a precise signal propagation delay time. Normally, the propagation delay time depends on various factors, such as the type of ECL circuit and device structure thereof, and are inherently determined at the time of completion of the production process. Thus, it is substantially impossible to adjust the propagation delay time after the production process. Nevertheless, there is a need to positively control the propagation delay time from the outside of the ECL circuit. Referring to FIG.1, there is illustrated a general ECL circuit. The ECL circuit in FIG.1 has a pair of transistors T1 and T2 having emitters mutually connected. A constant-current source transistor T3 is connected between a power supply line coupled to a first low-potential side power source V EE1 and a node at which the emitters of the transistors T1 and T2 are mutually connected. Pull-up resistors R L are respectively connected between the collectors of the transistors T1 and T2 and a power supply line having a ground potential GND. A node at which the collector of the transistor T1 is connected to the pull-up resistor R L forms an output terminal x , which is connected to a base of an output transistor T4 which forms an output circuit of an emitter follower on the side of the transistor T1. Similarly, a node at which the collector of the transistor T2 is connected to the pull-up resistor R L forms an output terminal x, which is connected to a base of an output transistor T5 which forms an output circuit of an emitter follower on the side of the transistor T2. An emitter follower circuit is composed of the transistors T4 and T5, resistors R T1 and R T2 respectively connected to the emitters of the transistors T4 and T5, and a second negative-side power source V EE2 . It will be noted that the emitter follower circuit is not needed for the basic operation of the ECL circuit. However, the emitter follower circuit is usually provided in order to obtain a matching between the potential of an input signal and the potential of an output signal and increase load drivability of the ECL circuit. Due to the function of the emitter follower circuit, the voltages of the output terminals x and x are shifted, in parallel form, to signal output terminals X and X of the emitter follower circuit, respectively. The base of the constant-current source transistor T3 is supplied with a reference voltage V cs , which is a fixed potential. Signal input terminals IN, and IN are provided at the bases of the transistors T1 and T2, respectively. When an input signal (H) having a potential higher than a potential of the signal input terminal IN is applied to the signal input terminal IN, the transistor T1 is turned ON. Thus, a constant current I cs passes through the transistor T3. The constant current I cs causes a voltage drop developed across the pull-up resistor R L . The voltage drop decreases the potential of a node (output terminal x ) at which the collector of the transistor T1 and the pull-up resistor R L are connected to each other, so that the potential of the node becomes equal to a low (L) level. This low level is applied to the base of the output transistor T4. Thus, an inverted version of the input signal appears at the emitter of the output transistor T4, that is, the signal output terminal X of the emitter follower circuit. On the other hand, during the above-mentioned operation, the transistor T2 is turned OFF, and there is no voltage drop developed across the pull-up resistor R L connected to the collector of the transistor T2. Thus, the base potential of the transistor T5 is approximately equal to the ground potential GND. As a result, a signal (H) in phase with the input signal appears at the output terminal x and the emitter of the transistor T5, that is, the signal output terminal X. In the case where the potential of the input signal applied to the signal input terminal IN is lower than the potential of the input terminal IN , the circuit operates in a way opposite to the above-mentioned operation. Thus, a high-potential output signal is obtained at the signal output terminals x and X , and a low-potential output signal is obtained at the output terminals x and X. A propagation delay time t pd of the ECL circuit shown in FIG.1 is expressed as follows. t pd = A·rb·C cb + B·rb·C be + C·C bc ·(R L + re) + D·C be ·re + E·C sub ·(R L + re) + F·C L ·(R L + re) + t pd EF where A through E are proportion coefficients, and t pd EF is a propagation delay time provided by the emitter follower circuit. Further, the following symbols denotes parameters of the transistors T1 and T2: C cb : base-collector junction capacitance C be : base-emitter junction capacitance C sub : collector-substrate junction capacitance C L : parasitic capacitance between pull-up resistor R L and wiring lines rb: base resistance re: sum of an emitter resistance and differentiating resistance of the base-emitter forward characteristic. That is, the propagation delay time t pd of the ECL is as follows The term t pd EF is not related to the present invention, and is thus handled so that it is zero. The formula (2) means that the propagation delay time t pd corresponds to the sum of the products of the resistances and the corresponding capacitances, and is thus based on the time constant defined by a formula, τ = R·C. FIG.2 is a waveform diagram illustrating how the propagation delay time t pd of the ECL circuit shown in FIG.1 is generated. In FIG.2, V IN denotes an input voltage applied to the signal input terminal IN shown in FIG.1, and V IN denotes an input voltage applied to the input terminal IN shown in FIG.1. Further, V X denotes an output voltage obtained at the signal output terminal X, and V X denotes an output voltage obtained at the signal output terminal X . The propagation delay time t pd corresponds to a period between a time when the input voltage difference between V IN and V IN corresponds to 50% (that is, 0 volt) of the maximum difference and a time when the output voltages V X and V X correspond to 50% of the maximum amplitudes. As shown in FIG.2, the rise and fall of the output voltages V X and V X lag behind those of the input voltages V IN and V IN by the propagation delay time t pd . The slope of the rise (or fall) of the output voltage obtained at each of the signal output terminals X and X is based on the time constant of the pull-up resistor R L and the parasitic capacitance C L as well as the constant current I cs . In order to adjust the propagation delay time t pd from the outside of the ECL circuit, one may try to change a reference voltage V cs applied to the base of the constant-current transistor T3 so that the constant current I cs is changed and thus the amplitude of the output voltage is changed. However, the above consideration is not effective to control the propagation delay time t pd from the outside of the ECL circuit for the following reasons. First, the aforementioned formula (1) does not include the term of the constant current I cs . That is, the constant current I cs does not contribute to changing the propagation delay time t pd . Although the amplitude of the output voltage V X (V X ) is changed by changing the constant current I cs , the rising slope and falling slope of the output voltage are also changed. As a result, there is less change in the propagation delay time t pd , and the circuit operation is unstable. More specifically, when the reference voltage V cs is controlled so that the current passing through the transistor T3 increases, an increased voltage drop developed across the pull-up resistor R L is obtained and thus an increased amplitude of the output signal is obtained. However, an increase in the current increases the load drivability, which accelerates the circuit operation. Thus, it is possible to control the propagation delay time within only a narrow range. It is a general object of the present invention to provide an improved controllable delay logic circuit in which the above-mentioned disadvantages are eliminated. A more specific object of the present invention is to provide a controllable delay logic circuit having a propagation delay time which can be reliably controlled from the outside of the delay logic circuit in the stable state. According to the invention there is thus provided a controllable delay logic circuit comprising the features recited in claim 1. An embodiment provides the first current path means and the second current path means as first time constant control means, having a first resistor, for varying a first time constant defined by the first resistor and a parasitic capacitance coupled to the collector of the first transistor, and second current path means, having a second resistor, for varying a second time constant defined by the second resistor and a parasitic capacitance coupled to the collector of the second transistor. The aforementioned objects of the present invention are also achieved by respectively replacing the above-mentioned first time constant control means and second time constant control means by first load resistance control means, coupled to the first load, for varying a first load resistance provided by the first load, and second load resistance control means, coupled to the second load, for varying a second load resistance provided by the second load. For a better understanding of the invention and to show how the same may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a circuit diagram of a conventional ECL circuit; FIG.2 is a waveform diagram illustrating the operation of the ECL circuit shown in FIG.1; FIG.3 is a circuit diagram illustrating the outline of an ECL circuit according to the present invention; FIG.4 is a waveform diagram illustrating the operation of the circuit shown in FIG.3; FIG.5 is a circuit diagram of an ECL circuit according to a first preferred embodiment of the present invention; FIG.6 is a waveform diagram illustrating the operation of the ECL circuit shown in FIG.5; FIG.7 is a circuit diagram of an ECL circuit according to a second preferred embodiment of the present invention; FIG.8 is a circuit diagram of an ECL circuit according to a third preferred embodiment of the present invention; FIG.9 is a circuit diagram of an ECL circuit according to a fourth preferred embodiment of the present invention; FIG.10 is a circuit diagram of an ECL circuit according to a fifth preferred embodiment of the present invention; FIG.11A is a circuit diagram of an ECL circuit according to a sixth preferred embodiment of the present invention; FIG.11B is a circuit diagram illustrating a cla circuit formed of a series circuit consisting of a clamp diode and a clamp resistor; FIG.12 is a circuit diagram of a conventional ECL circuit with a clamp circuit; FIG.13 is a waveform diagram illustrating the operation of the ECL circuit shown in FIG.12; and FIG.14 is a circuit diagram illustrating the operation of the ECL circuit according to the present invention. A description will now be given of the outline of an embodiment of the present invention with reference to Fig. 3, in which those parts which are the same as those shown in Fig. 1 are given the same reference numerals or symbols. The present invention has a means for controlling the pull-up resistors R L shown in FIG.1. Referring to FIG.3, an ECL circuit has a current switch circuit composed of an emitter-coupled transistors T1 and T2, two load circuits formed of resistors R L1 and R L11 , and a current source formed of the current-source transistor T3 which supplies the emitters of the transistors T1 and T2 with the current I cs , in the same way as the ECL circuit shown in FIG.1. A series circuit (current path) composed of a diode D1 and a resistor R L2 connected in series is connected between the load resistor R L1 . The cathode of the diode D1 is connected to the resistor R L2 . Similarly, a series circuit (current path) composed of a diode D2 and a resistor R L21 connected in series is substantially connected between the load resistor R L11 . The cathode of the diode D2 is connected to the resistor R L21 . The anodes of the diodes D1 and D2 are connected to control terminals C, to which a control voltage V G is applied. The control terminals C are AC coupled to the ground-potential power supply line By changing the control voltage V G , it is possible to continuously vary the propagation delay time t pd . The diodes D1 and D2 may be respectively formed of diode-connected transistors. It is preferable to use the transistors T4 and T5 in the same way as transistors T4 and T5 shown in FIG.1 in order to obtain a matching between the potential of the input signal and the potential of the output signal and increase load drivability of the ECL circuit. However, it should be noted that the transistors T4 and T5 are not essential to realize the ECL circuit operation. It should also be noted that the circuit shown in FIG.3 functions as a single-end drive type ECL circuit by applying a reference voltage to the signal input terminal IN , and functions as a differential input type ECL circuit by respectively applying input signals having mutually opposite phases to the signal input terminals IN and IN . When the control terminals C are maintained at a positive potential enough to turn ON the diode D1 (or D2), the pull-up resistance R L of the ECL circuit is equivalent to a resistance R LD provided by a parallel circuit composed of the load (pull-up) resistor R L1 and the resistor R L2 . The equivalent pull-up resistance R LD is expressed as follows: R L = R LD = R L1 //R L2 = (R L1 x R L2 )/(R L1 + R L2 ) where symbol // represents a parallel connection. On the other hand, when the control terminals C are maintained at a negative potential enough to turn OFF the diode D1 (or D2), the pull-up resistance R L of the ECL circuit is as follows: R L = R LS , R L1 > (R L1 //R L2 ) = R LD where R LS represents an equivalent pull-up resistance in the state where the resistor R L2 is disconnected from the circuit because of the OFF state of the diode D1 (or D2). From the formula (4), the following is obtained. R LS > R LD From the formula (1), the following is obtained t pds > t pdD where t pds is a propagation delay time obtained when R L = R LS , and t pdD is a propagation delay time obtained when R L = R LD . FIG.4 is a waveform diagram illustrating a waveform of a collector voltage Vc of the transistor T1 observed when the transistors T1 and T2 are turned ON and OFF, respectively. The waveform of the collector voltage Vc is based, in principle, on a discharge characteristic defined by a resistance and a capacitance (collector time constant). The slope of the rise or fall of the collector voltage Vc obtained immediately after the transistor T1 (T2) is switched (turned ON or OFF) does not depend on the control signal voltage V G of the control terminal C (that is, does not depend on the ON/OFF state of the diode D1), but is constant. The amplitude of the collector voltage Vc is small when the diodes D1 and D2 are ON, and large when the diodes D1 and D2 are OFF. Thus, it is possible to vary the time it takes to obtain half the maximum amplitude of the collector voltage Vc, that is, to vary the propagation delay time t pd . The collector voltages Vc of the transistors T1 and T2 are changing momentarily and, in actuality, the bias voltage applied to the diodes D1 and D2 are changing momentarily. Hence, in actuality, the waveforms of the collector voltages Vc will be more complex than those shown in FIG.4. By setting a bias voltage V BS of each of the diodes D1 and D2 to an intermediate voltage which satisfies the formulas (3) and (4) by adjusting the control voltage V G , the control voltages Vc of the transistors T1 and T2 change in accordance with an intermediate curve between the solid line and the broken line shown in FIG.4. As a result, it becomes possible to continuously select an arbitrary propagation delay time between a propagation delay time t pd1 obtained when the diodes D1 and D2 are ON and a propagation delay time t pd2 obtained when the diodes D1 and D2 are OFF. This means that the propagation delay time t pd of the ECL circuit can be controlled outside of the ECL circuit. A description will now be given of an ECL circuit according to a first embodiment of the present invention with reference to FIGS.5 and 6, in which those parts which are the same as those shown in FIG.3 are given the same reference numerals. As shown in FIG.5, the anodes of the diodes D1 and D2 are connected to the control terminal C provided in common. A variable control voltage source Ec is connected between the power supply line having the ground potential GND and the control terminal C. More specifically, the positive terminal of the variable control voltage source Ec is connected to the control terminal C, and the negative terminal thereof is connected to the ground-potential power supply line. The variable control voltage source Ec can be formed of an internal circuit of a device which generates the voltage Ec externally controllable. Alternatively, it is possible to form the variable control signal source Ec of an external source outside of the device. It is now assumed that the level of the input signal V IN applied to the signal input terminal IN becomes higher than that of the input signal V IN applied to the signal input terminal IN . In this case, the transistor T1 is turned ON, and the transistor T2 is turned OFF. A current passes from the ground potential GND to the first low-potential side voltage V EE1 through the pull-up resistor (load resistor) R L1 , the transistor T1 and the constant-current source transistor T3. During this time, if the diode D1 is forward biased by the variable control voltage source Ec, a current passes from the ground potential GND to the first low-potential side voltage V EE1 through the variable control voltage source Ec, the diode D1, the resistor R L2 , the transistor T1 and the constant-current source transistor T3. That is, there are provided two current paths. The current I cs passing through the constant-current source transistor T3 is constant and formed by the currents respectively passing through the above-mentioned two current paths. In this case, from the point of view of an equivalent circuit, it can be considered that the resistor R L2 is connected in parallel to the pull-up resistor R L1 . Thus, the load resistance of the transistor T1 has a decreased value, as compared with the case where only the pull-up resistor (load resistor) R L1 is connected to the transistor T1. As a result, by setting the control voltage V G generated by the variable control voltage source Ec so that the aforementioned condition is satisfied, it is possible to reduce the amplitudes of the output voltages V X and V X , as shown by the broken lines shown in FIG.6-(a). In FIG.6, V IH denotes the "high (H)" level obtained on the input side of the ECL circuit, and V IL denotes the "low (L)" level obtained on the input side thereof. Further, in FIG.6, V OH denotes the "high (H)" level obtained on the output side of the ECL circuit, and V OL and V OL , respectively denote "low (L)" levels obtained on the output side thereof. As shown in FIG.6-(b) and (c), the propagation delay time t pd1 obtained when the output voltages V X and V X have the reduced amplitudes in the state where the diodes D1 and D2 are ON is shorter than the propagation delay time t pd2 obtained when the diodes D1 and D2 are OFF. This fact represents that the propagation delay time t pd of the ECL circuit is controlled by turning ON/OFF the diodes D1 and D2. FIG.6-(d) shows the differences between V X and V X obtained when the diodes D1 and D2 are ON and OFF, respectively . By turning ON the diode D1 and thereby connecting the resistor R L2 to the pull-up resistor R L1 in parallel form in the state where the transistor T1 is ON, it becomes possible to change the propagation delay time t pd of the ECL circuit. In addition, by changing the diode bias voltage V BS based on the control voltage V G , it becomes possible to change the collector voltage Vc and thus continuously change the propagation delay time t pd . The above description is related to the case where the input signal V IN rises. Similarly, the ECL circuit shown in FIG.5 operates when the input signal V IN falls. A description will now be given of an ECL circuit according to a second preferred embodiment of the present invention with reference to FIG.7, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The ECL circuit shown in FIG.7 uses transistors T6 and T7 substituted for the diodes D1 and D2. The collectors of the transistors T6 and T7 are supplied with a high-potential side power voltage V CC2 which is equal to or higher than the ground potential. The bases of the transistors T6 and T7 are connected to the variable control terminal C to which the control voltage V G is applied. The control voltage V G is generated by, for example, the variable control voltage source Ec as shown in FIG.5. The emitter of the transistor T6 is connected to the resistor R L2 , and the emitter of the transistor T7 is connected to the resistor R L21 . It is now assumed that the level of the input signal V IN becomes higher than that of the input signal V IN . In this case, the transistor T1 is turned ON, and the transistor T2 is turned OFF. A current passes from the ground potential GND to the first low-potential side voltage V EE1 through the pull-up resistor (load resistor) R L1 , the transistor T1 and the constant current source transistor T3. During this operation, the second high-potential side voltage V CC2 is being applied to the collectors of the transistors T6 and T7. When the control voltage V G is applied to the bases of the transistors T6 and T7, the transistors T6 and T7 are turned ON and OFF. Since the transistor T1 is ON, a current passes from the second high-potential side voltage V CC2 to the first low-potential side voltage V EE1 through the transistor T6, the resistor R L2 , the transistor T1 and the constant-current source transistor T3. This is equivalent to an arrangement in which the resistor R L2 is connected to the pull-up resistor (load resistor) R L1 in parallel form. Thus, by setting the control voltage V G so that the aforementioned condition is satisfied, the load resistance of the transistor T1 is reduced, and the output voltages V X and V X have reduced amplitudes. As a result, the propagation delay time t pd is reduced. Further, by controlling the control voltage V G applied to the transistor T6, it becomes possible to continuously vary the propagation delay time t pd . A description will now be given of an ECL circuit according to a third preferred embodiment of the present invention with reference to FIG.8, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The ECL circuit shown in FIG.8 has two transistors T6 and T7 as in the structure shown in FIG.7. However, the ECL circuit shown in FIG.8 is different from that shown in FIG.7 in that the collectors of the transistors T6 and T7 shown in FIG.8 are connected to the ground-potential power supply line. It is now assumed that the level of the input signal V IN becomes higher than that of the input signal V IN . In this case, the transistors T1 and T2 are turned ON and OFF, respectively. When the control voltage V G is applied to the bases of the transistors T6 and T7 via the control terminal C, the resistor R L2 is connected to the resistor R L1 in parallel form, so that the load resistance of the transistor T1 is reduced, and the amplitude of the output voltage V X is also reduced. As a result, the propagation delay time t pd is shortened. Further, by changing the control voltage V G , it becomes possible to continuously change the propagation delay time p td . A description will now be given of an ECL circuit according to a fourth preferred embodiment of the present invention with reference to FIG.9. The ECL circuit shown in FIG.9 is different from the ECL circuit shown in FIG.5 in that a level shift diode Ds is provided between the ground-potential power supply line and the pull-up resistors R L1 and R L11 . The level shift diode Ds is directed to reducing the amplitudes of the signals of the ECL circuit and making the ECL circuit operate at a higher speed. The level shift diode Ds can be formed by a transistor which is manufactured during a process in which other transistors, such as T1 and T2, are manufactured. The level shift diode Ds develops a fixed voltage drop. Thus, the voltage drops developed across the pull-up resistors R L1 and R L11 are limited, so that the switching operation speed increases. The amplitude of the output voltages V X corresponds to the sum total of the voltage drop developed across the pull-up resistor R L1 and the voltage drop developed across the level shift diode Ds. Thus, the ECL circuit shown in FIG.9 provides the output voltage V X which is the same as the output voltage V X provided by the ECL circuit shown in FIG.5. It can be said that the controllable range of the control voltage V G is shifted toward the low-potential side by a potential which corresponds to the forward voltage of the level shift diode Ds. A description will now be given of an ECL circuit according to a fifth embodiment of the present invention with reference to FIG.10, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The ECL circuit shown in FIG.10 is different from the ECL circuit shown in FIG.9 in that a level shift resistor Rs is substituted for the level shift transistor Ds. That is, the level shift resistor Rs is connected between the ground-potential power supply line and the pull-up resistors R L1 and R L11 . The level shift resistor Rs may be fabricated in the same production process as other resistors R T1 and R T2 . Of course, it is possible to fabricate the level shift resistor Rs in a production process different from that for producing the other resistors. A description will now be given of an ECL circuit according to a sixth preferred embodiment of the present invention with reference to FIG.11A, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The ECL circuit shown in FIG.11A is different from the ECL circuit shown in FIG.8 in that a level shift element Z is provided between the ground-potential power supply line and the pull-up resistors R L1 and R L11 . The level shift element Z can be formed of the level shift diode Ds shown in FIG.9, the level shift resistor Rs shown in FIG.10, or a series circuit shown in FIG.11b. The series circuit shown in FIG.11 is composed of the level shift diode Ds and the level shift resistor Rs. Finally, a description will be given of the difference between the ECL circuit according to the present invention and a conventional clamp circuit. With reference to FIG.12, there is illustrated a conventional ECL circuit with a clamp circuit. The ECL circuit shown in FIG.12 is a collector dotting type logic circuit. Transistors T6 and T7 form a clamp circuit. Further, transistors T11, T12 and T13 are provided. The transistors T11 and T12 receive input signals IN2 and IN2 , respectively. When the transistors T2 and T11 are ON, and the transistors T1 and T12 are OFF, a current 2I cs twice the constant current I cs passing through the transistor T3 or T13 passes through one of the load resistors R L . Thereby, it becomes possible to prevent the low (L) levels of the input and output signals from decreasing. A circuit arrangement obtained by omitting the transistors T11, T12 and T13 is different from the circuit arrangement shown in FIG.8 in that the resistors R L2 and R L21 shown in FIG.8 are not connected to the emitters of the transistors T6 and T7. It should be noted that the resistors R L2 and R L21 connected to the emitters of the transistors T6 and T7 play the important role to control the propagation delay time. This will be explained with reference to FIGS.13 and FIG.14. When the difference between the input signals V IN and V IN changes as shown in FIG.13, the output voltages V X and V X changes as shown in FIG.13. The output voltages V X and V X are based on the difference between the input voltages V IN and V IN . The output voltages V X and V X are clamped by the transistors T6 and T7, respectively. The bases of the transistors T6 and T7 are supplied with a clamp voltage V CLP which determines a voltage at which the output voltages V X and V X are clamped. When the clamp voltage V CLP is equal to a certain voltage, the output voltages V X and V X are equal to each other. In this case, the difference between V X and V X is continuously equal to zero. In FIG.13, the difference between V X and V X is zero during a period A. It should be noted that the state where there is no difference between V X and V X is an indefinite logic level other than the logically low (L) and high (H) levels. The existence of the indefinite logic level increases jitter (time-width variation), particularly when a high-speed input signal is applied to the ECL circuit, and thus prevents smooth control of the propagation delay time t pd . On the other hand, as shown in FIG.14, no continuous indefinite logic level occurs because of the existence of the resistors R L2 and R L21 . As a result, it becomes possible to smoothly control the propagation delay time t pd without having jitters.

Claims: A controllable delay logic circuit comprising: a differential circuit having first and second transistors (T1, T2) respectively having a collector, an emitter and a base, the emitters of said first and second transistors being connected to each other, the bases of said first and second transistors being respectively supplied with first and second input signals, and first and output signals being drawn from the collectors of the first and second transistors, respectively; a first load (R L1 ) coupled between a first power supply line (GND) and the collector of said first transistor; a second load (R L11 ) coupled between said first power supply line and the collector of said second transistor; a constant-current source (T3) connected between a second power supply line (V EE1 ) and the emitters of said first and second transistors, a first power source (V CC2 ); first current path means (D1, T6, R L2 ) connected to the collector of said first transistor for selectively supplying a first current to pass through said first transistor from said first power source in response to the difference between a control voltage (V G ) and the collector voltage of said first transistor; and second current path means (D2, T7, R L21 ) connected to the collector of said second transistor for selectively supplying a second current to pass through said second transistor from said first power source in response to the difference between the control voltage (V G ) and the collector voltage of said second transistor; characterised in that the said first and second current path means each further comprise a resistor (R L2 , R L21 ) through which their respective currents may flow, connected to the collector of the respective transistor, and wherein each said current path means is supplied with a variable control voltage (VG) which defines a propagation delay time of the circuit. A controllable delay logic circuit as claimed in claim 1, wherein said first current path means further comprises a first diode (D1) connected to said first resistor in series; and said second current path means further comprises a second diode (D2) connected to said second resistor in series. A controllable delay logic circuit as claimed in claim 2, wherein said first diode (D1) has an anode connected to said first, variable, power source (E C ), and a cathode coupled to the collector of said first transistor (T1) via said first resistor; and said second diode (D2) has an anode connected to said first power source and a cathode coupled to the collector of said second transistor via said second resistor. A controllable delay logic circuit as claimed in any of claims 1 to 3, wherein said first power source comprises a variable power source means (E C ) for generating the variable voltage (V G ) which defines the propagation delay time which is the delay between said first input signal and said first output signal and the delay (t pd ) between said second input signal and said second output signal. A controllable delay logic circuit as claimed in claim 1, wherein said first current path means comprises a third transistor (T6) having a collector connected to said first power source (V CC2 ), a base connected to the variable control voltage (VG), and an emitter connected to said first resistor; and said second current path means comprises a fourth transistor (T7) having a collector connected to said first power source (V CC2 ), a base connected to the variable control voltage (VG) and an emitter connected to said second resistor. A controllable delay logic circuit as claimed in claim 1, wherein said first power supply line (GND) has a potential identical to that of said first power source; said first current path means comprises a third transistor (T6) having a collector connected to said first power supply line, an emitter connected to said first resistor, and a base connected to the variable control voltage (VG); and said second current path means comprises a fourth transistor (T7) having a collector connected to said first power supply line, an emitter connected to said second resistor, and a base connected to the variable control voltage (VG). A controllable delay logic circuit as claimed in any of claims 1 to 6, further comprising level shift means (Z, Ds, Rs), provided in common for said first and second loads, for providing said first and second loads with a fixed voltage drop so that the first and second loads are supplied with a level-shifted voltage which is less than a potential of said first power supply line by said fixed voltage drop. A controllable delay logic circuit as claimed in claim 7, wherein said level shift means comprise a resistor (Rs) connected between said first power supply line and said first and second loads. A controllable delay logic circuit as claimed in claim 7, wherein said level shift means comprise a diode (Ds) connected between said first power supply line and said first and second loads. A controllable delat logic circuit as claimed in claim 7, wherein said level shift means comprises a series circuit (Z) which is composed of a diode (D) and a resistor (R) and which is connected between said first power supply line and said first and second loads. A controllable delay logic circuit as claimed in any of claims 1 to 10, wherein said first power supply line (GND) has a potential higher than that (V EE1 ) of said second power supply line. A controllable delay logic circuit as claimed in claim 11, wherein said first power source (E c , V CC2 ) generates a potential higher than that (GND) of said first power supply line. A controllable delay logic circuit as claimed in any of claims 1 to 12, further comprising: a fifth transistor (T4) having a base connected to the collector of said first transistor, a collector connected to said first power supply line, and an emitter through which a first output voltage (V x ) is output; and a sixth transistor (T5) having a base connected to the collector of said second transistor, a collector connected to said first power supply line, and an emitter through which a second output voltage (V x ) is output. A controllable delay logic circuit as claimed in any of claims 1 to 13, wherein said first load comprises a first load resistor (R L1 ); and said second load comprises a second load resistor (R L11 ). A controllable delay logic circuit according to claim 1, wherein the said first and second current path means form respectively first and second time constant control means each having the resistor and a parasitic capacitance (C L ) coupled respectively to the first and second transistors, which resistors and capacitances define the time constant. A controllable delay logic circuit according to claim 1, wherein the said first and second current path means comprise respectively a diode or a transistor forming a first and second load resistance control means for varying the load resistance provided by their respective loads.

Inventors: EMORI SHINJI, TAMAMURA MASAYA, EMORI, SHINJI, TAMAMURA, MASAYA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: H03K5
IPC codes: H03K5, H03K19