Semiconductor memory with metallic interconnection layer of the same potential as the word line and connected thereto outside of the memory cell region

Abstract: Memory cells (21), which serve as basic cells, are arranged in a matrix pattern. The memory cells (21) are each provided with a word line (W′) which is integral with the gate electrode of a switch element (SW) and which is formed of polysilicon. A metallic interconnec­ tion layer (M) is arranged above the word line (W′) and is applied with substantially the same potential as the word line (W′). The metallic interconnection layer (M) and the word line (W′) are connected together via through-holes (23A). The through-holes (23A) are formed in through-hole cells (23), which also serve as basic cells. The through-hole cells (23) and the memory cells (21) are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.

Description: The present invention relates to an improved semiconductor memory which employs a multi-level interconnection structure. In the field of application specific integrated circuits (ASICs), a variable bit type memory wherein the bit length is variable is well known. To obtain this type of memory by use of a standard cell arrangement, memory cells (i.e., basic cells) are arranged on a semi-conductor substrate in a matrix pattern. Each of the memory cells is made up of: a storage portion for storing information; and a switch element which is operated by means of a word line used for the selection of the memory cell. The switch element is inserted between the storage portion and a bit line used for transmitting the information from the memory cell. In order to minimize the area of the memory cell, the word line is made of the same material as that of the gate electrode of the switch element. For example, the word line is made of polysilicon. On the other hand, the bit line is made by a first-level metallic interconnection layer which is formed of aluminum, for example. Fig. 1 shows a circuit diagram of a static memory employing six transistors, and Fig. 2 is a plan view showing the horizontal pattern of that static memory. In Figs. 1 and 2, reference numeral 1 denotes an information storage portion of a flip-flop type, reference 2 denotes a switch element; reference symbols Wl to Wn denote word lines; and B1 and B1 (likewise, B2 and B2 ; B3 and B3 ; etc.) denote a pair of bit lines. In general, two types of arrangements can be selectively employed for the memory mentioned above. Fig. 3 is a plan view showing the pattern of the first type of arrangement, and Fig. 4 is an equivalent circuit diagram corresponding to the first type of arrangement shown in Fig. 3. Referring to Fig. 3, memory cells 11 are arranged in a matrix pattern. A pair of bit lines BIT and BIT used for the memory cells 11 arranged in one column are constituted by first-level metallic interconnection layers formed of aluminum. A word line W is integrally formed with the gate electrodes of the switch elements (not shown) of the memory cells 11 arranged in one row. The material of the gate electrodes (namely, the material of the word line W) is polysilicon, for example. In Fig. 4, R1-R5 denote resistance components of the word line W, and C1-C5 denote capacitance components, such as a gate capacitance and a floating capacitance. In the case where the word line W is formed only of the same material as that of the gate electrodes, the times required for the potential of the word lines W to rise and fall, respectively, are delayed due to the resistance components R1-R5 and the capacitance components C1-C5. This delay is lengthened in proportion to the length of the word line W. Therefore, if the memory has a large memory capacity, the delay is long, thus adversely affecting the performance of the memory. For example, in the circuit shown in Fig. 4, different loads are applied to points B, C, D, etc. which are located away from point Q by the distances L1, (L1+L2), (L1+L2+L3), etc., respectively. Therefore, the voltage applied to point Q is transmitted to points B, C, D, etc. after being delayed by the intervals respectively determined by the time constants of the resistor and capacitor components. In the arrangement, therefore, the time required for accessing the memory is lengthened in accordance with the length of the word line W. Figs. 5 and 6 show the second type of arrangement which can be employed for the memory mentioned above and which is free from the problem entailed in the first type of arrangement. Specifically, Fig. 5 is a plan view showing the pattern of the second type of arrangement, and Fig. 6 is an equivalent circuit diagram corresponding to the second type of arrangement shown in Fig. 5. Referring to Fig. 5, memory cells 11 are arranged in a matrix pattern. A pair of bit lines BIT and BIT used for the memory cells 11 arranged in one column are respectively constituted by first-level metallic interconnection layers, which are formed of e.g. aluminum. A word line W' is integrally formed with the gate electrodes of the switch elements (not shown) of the memory cells 11 arranged in one row. The material of the gate electrodes (namely, the material of the word line W') is polysilicon, for example. A second-level metallic interconnection layer M, which is formed of e.g. aluminum, is located above the word line W'. The second-level metallic interconnection layer M and the word line W' are connected to each other via throughholes 12. In Fig. 6, R11-R15 denote resistance components of the word line W', and C11-C15 denote capacitance components, such as a gate capacitance and a floating capacitance. Reference symbols Q', B', C', etc., and Q", B", C", etc. indicate contact portions between the word line W' and the second-level metallic interconnection layer M. In the second type of arrangement, the second-level metallic interconnection layer M is located above the word line W', and is connected to the word line W' by way of through-holes 12. With this structure, the word line potential is not delayed, as it is in the first type of arrangement. However, the second type of arrangement is faced with another problem. Since the second-level metallic interconnection layer M and the word line W' are connected together via the through-holes 12, contact portions are provided on the respective memory cells 11. As a result, the area of the entire memory is inevitably large, as may be understood from the comparison between Figs. 3 and 5. Thus, in summary, the present invention relates to a variable-bit type semiconductor memory device using a standard cell arrangement. The memory capacity of the memory device of this type is determined on the basis of the request of the user. When the memory capacity increases, the lengths of the word lines and a power supply line also increases inevitably. Due to the increase of the lengths of the lines, the change of the potential of the word lines is delayed and the power supply voltage supplied to the power supply line drops. The present invention has been made to prevent this problem. In particular, the present invention provides the structure and the technical idea that the power supply line and the interconnection layer are connected to each other at an arbitrary position so as to prevent the drop of the power supply voltage. Especially, a semiconductor memory device according to the invention is shown in claim 1. The subclaims 2 to 6 show advantageous further developments according to the invention. Patent Abstracts of Japan, vol. 11, no. 382; & JP-A-62 145 862 disclose a semiconductor device having a structure wherein a first wiring layer and a third wiring layer are interconnected to each other at an arbitrary position. But, this structure does not serve for preventing the drop of the a power supply voltage as it is reached by the present invention by the special connection of the power supply line and the interconnection layer. In the present invention, the word line, which is integral with the gate electrodes of switch elements constituting part of memory cells, is connected to the metallic interconnection layer by use of through-holes, and the number of the through-holes is smaller than that of the memory cells. With this structure, the area of the entire memory can be reduced, and the delay time of the metallic interconnection layer can be as short as possible. In addition, since the through-holes are located in regions other than the memory cells, the area of each memory cell can be reduced. Moreover, the intervals at which the through-holes are arranged can be determined on the basis of the access time the user wants. If the access time the user wants is comparatively long, the through-holes can be arranged at long intervals. In this case, the memory does not operate at a high speed but has a small area. Conversely, if the access time the user wants is comparatively short, the through-holes are arranged at short intervals. In this case, the memory may have a large area but operates at a high speed. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a static memory; Fig. 2 is a plan view of the pattern of the static memory shown in Fig. 1; Fig. 3 is a plan view of the pattern of the first type of arrangement which constitutes the memory shown in Figs. 1 and 2; Fig. 4 shows an equivalent circuit diagram corresponding to the first type of arrangement shown in Fig. 3; Fig. 5 is a plan view of the pattern of the second type of arrangement which constitutes the memory shown in Figs. 1 and 2; Fig. 6 shows an equivalent circuit diagram corresponding to the second type of arrangement shown in Fig. 5; Fig. 7 is a plan view of the pattern of the first embodiment of the present invention; Fig. 8 is a plan view of the pattern of the second embodiment of the present invention; Fig. 9 is a plan view of the pattern of the third embodiment of the present invention; and Fig. 10 shows an equivalent circuit diagram corresponding to the third embodiment shown in Fig. 9. Embodiments of the present invention will now be described, with reference to the accompanying drawings. Fig. 7 shows the first embodiment of the present invention. The basic cells of this embodiment include not only memory cells but also through-hole cells. Each of the through-hole cells has a through-hole which is used for connection between interconnection layers. The through-hole cells and the memory cells are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two. Reference numeral 21 in Fig. 7 denotes memory cells each of which serves as a basic cell. The memory cells 21 are static RAMs which are similar to those shown in Fig. 2, and are arranged on a substrate (not shown) in a matrix pattern. A pair of bit lines BIT and BIT used for the memory cells 21 arranged in one row are respectively constituted by first-level metallic interconnection layers which are formed of aluminum, for example. Word lines W' are formed in such a manner as to be integral with the gate electrodes of the switch elements of the memory cell 21 arranged in one column. The material of the gate electrodes of the switch elements is polysilicon, for example. In Fig. 7, reference symbol SW indicates an area in which the switch element is to be formed. A second-level metallic interconnection layer M, which is formed of e.g. aluminum, is provided above each word line W'. The memory cells 21 are provided with a power supply line 22 which is made by a diffusion layer. A first level metallic interconnection layer M1 is provided above each power supply lines 22. Through-hole cells 23, each serving as a basic cell, are provided with word lines W' which are similar to those provided for the memory cells 21. The second-level metallic interconnection layer M mentioned above is located above each word line W', and is connected to the word line W' via through-holes 23A. Like the memory cells 21, the through-hole cells 23 are provided with a power supply line 22 which is made by a diffusion layer. The first-level metallic interconnection layer M1 mentioned above is located above each power supply line 22. The power supply lines 22 and the first-level metallic interconnection layers Ml are connected together via through-holes 23B. The through-hole cells 23 and the memory cells 21 are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two. Since the through-hole cells 23 can be arranged in accordance with the arrangement of the memory cells 21, the first-level metallic interconnection layers M1 are connected together. It should be noted that the second-level metallic interconnection layers M and the word lines W' are connected together via the through-holes 23A of the through-hole cells, and that the first-level metallic interconnection layers M1 and the power supply lines 22 are connected together via the through-holes 23B of the through-hole cells 23. In the embodiment mentioned above, a through-hole is not formed in each memory cell but in each through-hole cell 23. With this structure, each memory cell is allowed to have a small area. In addition, since the number of rows of the through-hole cells 23 and the number of rows of the memory cells 11 are in the ratio of one to at least two, the area of the entire memory can be small. Further, the word lines W' and the second-level interconnection layer M are connected together via the through-holes 23A. With this structure, the potential variation of the word lines is prevented from being delayed. Still further, the power supply lines 22 and the first-level metallic interconnection layers M1 are connected together via the through-holes 23B. With this structure, the power source voltage is prevented from decreasing, and simultaneously, the noise in the power supply can be suppressed, thus ensuring a stable operation. The intervals at which the through-hole cells 23 are arranged can be determined on the basis of the access time the user wants. If the access time the user wants is comparatively long, the through-hole cells 23 are arranged at long intervals. In this case, the memory does not operate at a high speed but has a small area. Conversely, if a short access time is required, the through-hole cells 23 are arranged at short intervals. In this case, the memory may have a large area but operates at a high speed. Fig. 8 shows the second embodiment of the present invention. The memory of this embodiment is comprised of first memory cells 31 each of which has no through-hole, and second memory cells 32 each of which has a through-hole used for interconnection. The first memory cells 31 and the second memory cells 32 are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two. In the second embodiment shown in Fig. 8, the first memory cells 31 have a similar structure to that of the memory cells 11 shown in Fig. 7. The second memory cells 32 have a similar structure to that of the first memory cells 31, but differ from the first memory cells 31 in that each of them is provided with two through-holes 32A and 32B. The through-hole 32A is used for connecting the second-level metallic interconnection layer M and the word line W' together, while the through-hole 32B is used for connecting the power supply line 22 and the first-level metallic interconnection layer M1 together. As is shown in Fig. 8, the first memory cells 31 are arranged in a matrix pattern, and the second memory cells 32 are provided such that the number of rows of the second memory cells 32 and the number of rows of the first memory cells 31 are in the ratio of one to at least two. Due to this arrangement of the first and second memory cells 31 and 32, the second-level metallic interconnection layers M are connected together, and the word lines W' are connected together. In addition, the power supply lines 22 are connected together, and the first-level metallic interconnection layers M1 are also connected together. It should be also noted that second-level metallic interconnection layers M and the word lines W' are connected via the through-holes 32A of the second memory cells 32, and that the first-level metallic interconnection layers M1 and the power supply lines 22 are connected via the through-holes 32B of the second memory cells 32. In the second embodiment mentioned above, the second memory cell 32 has through-holes 32A and 32B, but first memory cell 31 does not. It should be noted that the first memory cell 31 has a side longer than that of the second memory cell 32. That is, L31 < L32 (L31: the length of one side of the first memory cell, L32: the length of one side of the second memory cell). Accordingly, the area of the first memory cell 31 is smaller than that of the second memory cell 32. It should be also noted that the number of rows of the second memory cells 32 and the number of rows of the first memory cells 31 are in the ratio of one to at least two. Since, therefore, the number of second memory cells 32 used is smaller than that of first memory cells 31, the area of the entire memory can be reduced, accordingly. Moreover, the word lines W' and the second-level metallic interconnection layer M are connected together via the through-holes 32A, while the power supply lines 22 and the first-level metallic interconnection layers M1 are connected together via the through-holes 32B. With this structure, the potential variation of the word lines is prevented from being delayed, and the power supply voltage is prevented from decreasing. Figs. 9 and 10 show the third embodiment of the present invention. Fig. 9 is a plan view of the pattern showing a mask ROM to which the present invention is applied, and Fig. 10 shows an equivalent circuit corresponding to the mask ROM shown in Fig. 9. The mask ROM of the third embodiment is comprised of memory cells 41 each of which has no through-hole, and through-hole cells 42 each of which has a through-hole used for interconnection. The through-hole cells 42 are provided such that the number of rows of the through-hole cells 42 and the number of rows of the memory cells 41 are in the ratio of one to at least two. Referring to Figs. 9 and 10, the memory cells 41 are provided with bit lines B1-B9. These bit lines B1-B9 are constituted by first-level metallic interconnection layers which are formed of aluminum, for example. The memory cells 41 are also provided with word lines W1-W7. These word lines W1-W7 are formed of polysilicon, for example, and are integral with the gate electrodes of switch elements SW. A second-level metallic interconnection layer 43, which is formed of e.g. aluminum, is provided above each word lines W1-W7. The memory cells 41 are further provided with power supply lines 44 which are formed by diffusion layers. The through-hole cells 42 are provided with first-level power supply lines 45, which are formed of aluminum, for example. The above-mentioned word lines W1-W7 and the metallic interconnection layers 43 are located above the first-level power supply lines 45 together. Each of the through-hole cells 42 comprises two through-holes 46 and 47, the former through-hole 46 being used for connecting the power supply lines 44 and 45, and the latter through-hole 47 being used for connecting the word lines W1-W7 and the second-level metallic interconnection layer 43 together. The through-hole cells 42 are arranged such that the number of rows of the through-hole cells 42 and the number of rows of the memory cells 41 are in the ratio of one to at least two. With this structure, the third embodiment produces substantially the same advantages as those of the first and second embodiments. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A variable bit type semiconductor memory by use of standard cell arrangement comprising: a substrate having an area extending in a first plane and a thickness extending substantially orthogonal to the first plane; a matrix of basic memory cells (21) disposed on the substrate and spaced from each other in the first plane, each basic memory cell including a switching element (SW) having a gate electrode parallel to the first plane; a plurality of conductive word lines (W'), each being integral with a plurality of the gate electrodes of the switching elements, for connection to a predetermined potential, wherein each of said plurality of conductive word lines is parallel to the first plane; a plurality of power supply lines (22) each being formed of diffusion layers, wherein each of the said plurality of power supply lines is parallel to said plurality of conductive word lines; a plurality of bit lines (BIT) extending orthogonal to each of the plurality of power supply lines and parallel to the first plane; a plurality of first-level metallic interconnection layers (M1), each being provided above and insulated from each power supply line; a plurality of second-level metallic interconnection layers (M), each being provided above and insulated from a respective one of the plurality of conductive word lines and each of said plurality of second-level metallic interconnection layers extending parallel to said respective conductive word line for connection to said predetermined potential; a plurality of first contact holes (23A), each electrically connecting a respective one of said plurality of second-level metallic interconnection layers (M) to the respective one of said plurality of conductive word lines (W') for decreasing delay in variation of a potential along the respective one of said plurality of conductive word lines; and a plurality of second contact holes (23B) electrically connecting said plurality of power supply lines (22) to said first-level metallic interconnection layers (M1), wherein said first and second contact holes are smaller in number than that of the basic memory cells. A semiconductor memory according to claim 1, characterized in that said word line (W') is formed of polysilicon. A semiconductor memory according to claim 1 or 2, characterized in that said metallic interconnection layers (M1, M) are formed of aluminum. A semiconductor memory according to any of the preceding claims, that said contact holes comprise through-holes (23A, 23B) being formed in second memory cells (23) which are arranged such that one of said second memory cells is provided for a plurality of said basic memory cells (21). A semiconductor memory according to claim 1, characterized in that each of said plurality of first-level metallic interconnection layers (M1) extends parallelly to said respective power supply lines (22). A semiconductor memory according to claim 1, characterized in that each of said plurality of first-level metallic interconnection layers (45) extends orthogonally to each of said power supply lines (44).

Inventors: HASHIMOTO HISASHI, TAKASE SHINSUKE, TANAKA YUTAKA, HASHIMOTO, HISASHI, TAKASE, SHINSUKE, TANAKA, YUTAKA, HASHIMOTO, HISASHI, C/O INTELLECTUAL PROPERTY DIV., TAKASE, SHINSUKE, C/O INTELLECTUAL PROPERTY DIV., TANAKA, YUTAKA, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1990
Main classification: H01L27
IPC codes: H01L27, H01L21, G11C17