Semiconductor device and electronic device by use of the semiconductor

Abstract: A semiconductor devive comprises; a collector region (2,3) of first conductivity type; a base region (4) of second conductivity type; an emitter region (6) of the first conductivity type; a thin film provided on the emitter region (30) and capable of flowing therein a tunnel current; and a polycrystalline layer (8) laminated on the thin film. An energy Δ B of potential barrier formed at a grain boundary is not less than a heat energy kT at a temperature therein.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a semiconductor device and an electronic device by use of said semiconductor device, more particularly to a semiconductor device with a structure of bipolar transistor structure and an electronic device by use of said semiconductor device. Related Background Art There have been known in the art devices having thin films through which tunnel current flows as the emitter, such as bipolar transistor (BPT) with MIS structure, heterobipolar transistor (HBT) by use of micro-crystal (µC) or amorphous semiconductor as the emitter, etc. In this case, in the above-mentioned BPT, by utilizing the difference in tunnel probability between electrons and positive holes, the positive holes from the base are impeded by the above-mentioned thin film, thereby effecting reduction of the base current. However, in the case of the above-mentioned BPT, since the above-mentioned thin film through which tunnel current flows is used, the series resistance of the emitter becomes higher, whereby the reaction is generated between metal and insulation film, whereby reliability may be sometimes lacking. Particularly, since leak of base current occurs in low current region, it is difficult to effect increase of the current amplification ratio. More specifically, the above-mentioned BPT with MIS structure of the prior art, for obtaining characteristics for effecting reduction of the above-mentioned base current, will require a necessary minimum thickness of the above-mentioned thin film, whereby the emitter resistance will be increased. On the contrary, if its thickness is too thin, the inhibition ratio of positive holes will be lowered, whereby no reduction of the base current can be effected to lower the current amplification ratio h FE . Further, since a difference occurs in tunnel probability between positive holes and electrons, positive holes cannot sometimes become carriers, and therefore although application to the npn type transistor may be possible, application to the pnp type transistor is difficult. More specifically, in the case when the difference in transmittance of positive holes and electrons is small, inhibition of positive holes cannot be accomplished. Further, although utilization of such difference in transmittance may be applicable to an npn type transistor, it is not applicable to a pnp transistor which is different in junction type. The tunnel probability between positive holes and electrons is determined by the tunnel film, the thickness is sensitively reflected on the current amplification ratio h FE , whereby variance will readily occur between individual transistors. Further, series resistance may vary similarly in some cases. On the other hand, in HBT by use of micro-crystal (µC) of the prior art, the emitter-base junction, namely the interface between the emitter by use of µc-Si and the base is unstable, and in the low current region of base current, particularly recombination becomes prevailing, whereby the current amplification ratio h FE will be sometimes markedly lowered. In the case of HBT by use of µC or HBT by use of an amorphous semiconductor as mentioned above, both are weak to heat treatment, thus sometimes lacking stability. Further, there sometimes ensure problems such that the reaction between µC or amorphous semiconductor and Si single crystal interface occurs, that the content of hydrogen is high to cause elimination phenomenon of said hydrogen to make the process unstable, or that deterioration may occur during actuation. More specifically, in µc-Si of the prior art, addition of heat treatment will result in reduction of current amplification ratio h FE even at, for example, 450 °C. Preparation temperature of µc-Si is generally frequently 300 °C to 400 °C. Such reduction may be considered to be caused particularly by lowering in band gap and elimination of H (hydrogen) contained in µc-Si, etc. because of increased particle size of µc-Si at the Si interface. In µc-Si of the prior art, a large amount of hydrogen is contained during preparation thereof, and also µc-SiO is stabilized by the presence of hydrogen. The surrounding of µc-Si may be considered to be terminated with hydrogen. In addition, interface defects may sometimes appear, because base current may be leaked in the fine current region, or hetero-junctions are present at the pn junction interface. The BPT with MIS structure having the above-mentioned structure of the prior art is lowered in current amplification ratio h FE (= I C /I B ) on the lower current side until, in an extreme case, it becomes 1 or less, particularly because the recombination current in the oxide film is predominant in the fine current region to increase the base current. In the case of such structure, the reaction between the metal and the insulation film is liable to occur, whereby reliability may be sometimes lacking. Further, since the insulation film has a considerable thickness, the series resistance has become large. Since the tunnel probability between positive holes and electrons is determined according to the thickness of the oxide film, the thickness is sensitively reflected on the above-mentioned h FE , whereby characteristic variance of individual BPT occurs. The series resistance will also vary similarly. Thus, difficulties are accompanied with stable preparation of all the oxide films at A order. On the other hand, in the HBT by use of µC of the prior art, as described above, the emitter-base junction, namely the interface between the emitter by use of µc-Si and the base is unstable to heat treatment and susceptible to change, whereby stable preparation can be done with difficulty. This is because it is based on instability of the µC itself or instability at the interface with the single crystalline silicon, and further containment of a large amount of hydrogen in ordinary µC which further promotes instability of the crystal. In addition, one by use of µC is susceptible to characteristic deterioration not only during preparation steps but also during actuation. A publication of the International Electron Devices Meeting in Washington on December 4-6 1978, IEEE, New York at pages 333-335 discloses a semiconductor device which is provided with a thin insulator film between a monocrystalline emitter region and a polycrystalline layer laminated on the thin film. The purpose of the thin insulator film is to discriminate between electrons and holes as a means of reducing the base current. In this device appreciable electron current is provided as a tunnel current flow whilst the current flow of holes via the thin insulator film is inhibited. US-A-4672413 discloses a bipolar transistor type semiconductor device in which the injection efficiency is greatly increased without significant increase in the emitter resistance of the transistor. To achieve this, an emitter tunnelling barrier is formed within the emitter region of the transistor rather than at the junction between the emitter and base regions. The emitter region adjacent to the barrier is heavily doped resulting in an increased injection efficiency, and the barrier is thin enough to preclude any significant increase in emitter resistance. SUMMARY OF THE INVENTION The present invention aims to alleviate some of the problems with the prior art semiconductor devices described above, and advantages of the present invention will become apparent to those skilled in the art from the following description of exemplary embodiments. For example, some embodiments provide a semiconductor device which (i) can maintain a high current amplification ratio over a broad range of collector currents; (ii) can withstand heat treatment; (iii) can inhibit an increase of base current in the low current region; and (iv) can be incorporated into a photoelectric conversion device. According to a first aspect, the present invention provides a semiconductor device comprising: a collector region of first conductivity type; a monocrystalline base region of second conductivity type; a monocrystalline emitter region of the first conductivity type providing at an interface with the base region an emitter-base junction in single crystal; a thin film provided on the emitter region; and a polycrystalline layer laminated on the thin film; which semiconductor device is characterised in that: the thin film is so thin that it results in an appreciable tunnel current flow for both majority and minority carriers, the tunnelling probabilities of both majority and minority carriers being substantially equal to each other; and the polycrystalline layer provides a potential barrier to the flow of carriers injected from the base region thereby to reduce base current and increase current amplification ratio. According to a second aspect, the present invention provides a photoelectric conversion device incorporating the above semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of a semiconductor device showing the first embodiment of the present invention; Fig. 2A is a diagram showing the energy level of the polycrystalline layer when Q t > L·Ni; Fig. 2B is a diagram showing distributions of crystal grain boundary B c , depleted layer E P in a thin film N-type polycrystalline silicon; Fig. 3A is a diagram showing the energy level of the polycrystalline layer when Q t > L·Ni; Fig. 3B is a diagram showing distributions of crystal grain boundary B c , depleted layer E P in a thin film N-type polycrystalline silicon; Fig. 4 is a graph showing the relationship of specific resistance versus impurity concentration of polycrystalline layer; Fig. 5 is a graph showing the relationship of height of potential barrier versus impurity concentration of polycrystalline layer; Fig. 6 is a diagram showing the potential along the line A-A′ in Fig. 1; Fig. 7A is a schematic view for illustration of the polycrystalline interface in the structure of the prior art; Fig. 7B is a schematic view for illustration of the polycrystalline interface in the structure of the present invention; Fig. 8A is an illustrative diagram showing the relationship between potential and distance for illustration of the tunnel film; Fig. 8B is an illustrative diagram showing the relationship between potential and distance when a considerable voltage is applied on the tunnel film; Fig. 9 is a graph showing the temperature characteristics of reciprocal number of the sheet resistance of a polycrystalline silicon; Fig. 10A and Fig. 10B are diagrams showing the relationship between potential and distance for illustration of tunnel film; Fig. 11 is a graph for comparison of relationships of voltage, current between the transistor of the present invention and the transistor of the prior art; Fig. 12 is a graph showing the relationship between impurity concentration and life of positive holes in the emitter region; Fig. 13A is an illustrative diagram showing the energy level of junction of n-type Si and n-type SiC; Fig. 13B is an illustrative diagram showing the energy level of junction of n-type Si, n-type SiC, n-type Si; Fig. 13C is an illustrative diagram showing the energy level of junction of n-type Si, n-type SiC of thin film, n-type Si; Fig. 14 is a sectional view of a semiconductor device showing the second embodiment of the present invention; Fig. 15 is a sectional view of a semiconductor device showing the third embodiment of the present invention; Fig. 16 is a circuit diagram showing an embodiment of the electronic device by use of the semiconductor device according to the present invention; Fig. 17A through Fig. 17D are views for illustration of quantization of the energy of electrons in polycrystalline layer; Fig. 18 is a graph for illustration of the change of Fermi energy when electrons are packed in a cubic well; Fig. 19 is a diagram showing the potential along the line A-A′ in Fig. 1; Fig. 20 is a sectional view of a semiconductor device showing the fifth embodiment of the present invention; Fig. 21 is a sectional view of a semiconductor device showing the sixth embodiment of the present invention; Fig. 22 is a diagram showing the potential along the line A-A′ in Fig. 1 which is the emitter region; Fig. 23 is a graph showing the relationship of carrier density versus normalized energy in semiconductor silicon; Fig. 24 is a sectional view of a semiconductor device showing the eighth example of the present invention; and Fig. 25 is a sectional view of a semiconductor device showing the ninth example of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention can effect reduction of base current in fine current region to obtain high current amplification ratio by preparing a thin film on the n + emitter region and further laminating a polycrystalline layer thereon, whereby polycrystalline layer will function as the barrier against positive holes. By preparing the emitter-base junction in the single crystal, the base current can be reduced in the fine current region to obtain high current amplication ratio. The thickness of the thin film prepared on the n + emitter region should be preferably made 5nm (50Å) or less. Its film thickness may be desirably as thin as possible. This is because, with thinner thickness, the series resistance in the emitter can be lowered, whereby positive holes can also give rise to tunnel phenomenon similarly as electrons. By formation of a thin film which gives rise to tunnel phenomena of both positive holes and electrons on the emitter region, the series resistance in the emitter region is lowered. By formation of a polycrystalline layer on said thin film, a barrier acting on both positive holes and electrons is formed, whereby reduction of base current can be effected. Further, when the emitter-base junction is formed in the single crystal, increase of base current in fine current region can be inhibited. In addition, by formation of a ultra-thin film on the emitter region, the tunnel probabilities of both positive holes and electrons become equal to each other, whereby increase of current amplification ratio can be realized. By formation of a polycrystalline layer witha high impurity concentration on the ultra-thin film on the emitter region, a barrier of minority carriers injected from the base region is formed, which can contribute to reduction of base current to realize increase of current amplification ratio. Further, since a polycrystal is formed through a ultra-thin film on the single crystal, it is stronger to heat as compared with the case when formed directly on the single crystal, and the grains size becomes constant to give also a stable interface. By formation of a ultra-thin film, positive holes and electrons can be sufficiently tunneled, and therefore current and voltage characteristics of BPT are not affected by the oxide film. More specifically, since the collector current is determined only by the base, and the value of the base current can be determined by the emitter impurity concentration, depth under the tunnel film, no change of h FE of BPT will occur depending on the thickness of the tunnel film. In other words, a BPT with little variance having stable h FE can be obtained. When an emitter-base junction is prepared in the single crystal, increase of the base current in fine current region can be inhibited. Referring now to the drawings, preferred specific embodiments of the present invention are described in detail. Fig. 1 shows the first embodiment according to the semiconductor device of the present invention. In the same Figure, 1 is a silicon substrate, and said substrate 1 is an n-type substrate which has been made n-type by doping of an impurity such as phosphorus (P), arsenic (As), antimony (Sb), etc. or a p-type substrate which has been made p-type by doping of an impurity such as boron (B), aluminium (Al), gallium (Ga), etc. 2 is an n + region (n + embedded region), and said first n + embedded region 2 may be preferably made to have an impurity concentration of 10 16 to 10 20 [cm -3 ]. 3 is an n region as a part of the collector region, and said n region 3 is a region with a low impurity concentration (e.g. about 10 13 to 5 x 10 17 [cm -3 ]) formed by epitaxial technique, etc. 4 is a p-type region as the base region, and said p-type region 4 may be preferably made to have an impurity concentration of 10 15 to 10 20 [cm -3 ]. 5 is a P + region, and said P + region 5 is provided for lowering the base resistance and may be preferably made to have an impurity concentration of 10 17 to 10 20 [cm -3 ]. 6 is a first n + emitter region. 7 is a second n + region, and said second n + region is provided for connecting the collector electrode 202 as described below to the above-mentioned embedded region 2 which is the n + region so as to lower the collector resistance. 8 is a polycrystalline layer which is a semiconductor material layer. Said polycrystalline layer 8 impedes the carriers injected from the base. 30 is a thin film. Said thin film 30 is provided for flowing tunnel current. 101, 102, 103 are insulating films for separation between the electrodes, elements and wirings. 200, 201, and 202 are respectively emitter electrode, base electrode and collector electrode, and the respective electrodes 200, 201 and 202 are formed of metals, silicides, etc. The above-mentioned thin film 30 is made thinner than the film of the MIS type BPT of the prior art. At least positive holes will become the carriers of current. The positive holes passed through said thin film 30 are impeded by the polycrystalline layer 8. In the following, the above-mentioned polycrystalline layer 8 is described. Polycrystal is a mass of single crystals having a distribution of a certain size, and those crystal grains have no constant crystal direction. They have also crystal grain boundaries, and remarkable disorders of lattices occur at those portions. Therefore, presence of crystal grain boundary is the cause of having electrical characteristics different from single crystal. The above-mentioned electrical characteristics are greatly influenced by the crystal grain size and the lattice defect density of the crystal grain boundary. The lattice defect existing at said crystal grain boundary becomes the capturing centre of free carriers as deep acceptor or donor level to capture charges in forbidden gap. By such capturing, a depleted layer region arises around the crystal grain boundary to change the potential, and the change of said potential will act like a barrier against the carriers. Polycrystal is changed in its characteristics depending on its grain size L [cm], the impurity concentration Ni [cm -3 ], the trap level density Q t at the crystal grain boundary [cm -2 ], and referring to polycrystalline silicon as an example, said characteristic change is described below. Figs. 2A, 2B show the energy band diagram when Q t > L·Ni (Fig. 2A), and spreading of the crystal grain boundary B c , the depletion layer E P in the thin film N-type polycrystalline silicon (Fig. 2B). Figs. 3A, 3B show the energy band diagram when Q t < L·Ni (Fig. 3A), and spreading of the crystal grain boundary B c , the depletion layer E P in the thin film N-type polycrystalline silicon (Fig. 3B). More specifically, as shown in Fig. 2B, when Q t > L·Ni, the polycrystalline silicon is internally all depleted. On the other hand, as shown in Fig. 3B, when Q t < L·Ni, the depletion layer region spreads only to the vicinity of the crystal grain boundary, thus representing the state wherein neutral region remains in polycrystalline silicon. In other words, resistance will be extremely higher when Q t > L·Ni. Fig. 4 shows an example of specific resistance ρ versus impurity concentration Ni in the case when the trap level density Q t is made constant, and the grain size L is varied as: 20; 42; 122nm (200 Å, 420 Å, 1220 Å). Here, the region (a) represents the case of Q t > L·Ni and the region (b) the case of Q t < L·Ni. The region (c) is the case when the impurity concentration is high and the barrier  B shown in Fig. 3A becomes extremely thin, and because the carriers pass through the barrier by tunnel phenomenon, there becomes substantially no barrier, whereby the region will have a specific resistance approximate to single crystal. The above-mentioned regions (a), (b) are specific characteristic regions of a polycrystal body, but the region (a) has too high resistance and is not suitable for the semiconductor device. In the present embodiment, it is desirable to use the polycrystal body of the above-mentioned region (b) for the emitter region of the BPT. It is difficult to measure actually how high is the barrier in the above-mentioned (b), and therefore, as shown in Fig. 5, an example determined by calculation is shown. That is, with the crystal grain size being made constant as L=10 -5 [cm], and the respective values of the trap level density Q t (the respective values corresponding to (1) to (7) in Fig. 5 of 1 x 10 -13 , 5 x10- 12 , 2 x 10 -12 , 1 x 10 -12 , 5 x 10 -11 , 2 x 10 -11 , 1 x 10 -11 ) being respectively as parameters, the height  B of the above-mentioned barrier is plotted versus impurity concentration Ni [cm -3 ]. According to the experimental data, the Q t of the polycrystal according to the present embodiment has a value of about 1 x 10 -12 to 1 x 10 -13 [cm -2 ], while the grain size of ordinary crystal is 200 to 1000 [Å], and therefore the height of the barrier  B may be considered to have ordinarily a value as shown in Fig. 5. Therefore, the maximum value of the height of the barrier  B may be sometimes about 0.45 [eV]. However, it is required that the grain size L, the trap level density Q t at the interface, the impurity concentration Ni should be optimized. The current flowing through the region (b) of the polycrystal becomes a hot electron radiation type as one with the carriers flowing over the barrier  B . On the other hand, the width W of the depletion layer E P (see Fig. 3A) is represented approximately by: W = Q t N i For example, if Q t =5 x 10 -12 [cm -2 ] and Ni is 10 18 [cm -3 ], w = 5 x 10 -6 [cm] = 50nm (500 Å), and  B of about 0.35 [eV] will occur. As shown in Fig. 3, if L=100nm (1000 Å), the neutral region n R of 50nm (500 Å) would remain. Fig. 6 shows the potential diagram at the cross-section A-A' in Fig. 1. In the same Figure, E R represents emitter region, B R base region and C R collector region. In the Figure, W B represents the neutral region width of the base, W EB the neutral region width of the emitter in the single crystal, and δ the thickness of the above-mentioned thin film 30. The greatest characteristic function of the above-mentioned thin film 30 is to separate the polycrystalline layer 8 from the first n + region 6 which is the single crystal in the emitter region 6, simultaneously with flattening of its interface, and also stabilize the polycrystal layer 8. More specifically, for example, if the polycrystal layer 8 is deposited directly on the n + region 6 which is merely a single crystal with the structure of the prior art as shown in Fig. 7A, the crystal with about the grain size of a polycrystal is grown epitaxially on the single crystal, whereby the inherent interface with the single crystal (B - B' in Fig. 7A) is changed to become wavy and cannot maintain always a constant shape. In this case, if a polycrystal is deposited on a naturally oxidized film and subjected to heat treatment, the oxide film may be sometimes broken and epitaxial growth may locally occur. In an extreme case, the naturally oxidized film will become shaped like ball, and the polycrystal recrystallized into single crystal. Thus, in the case of the structure of prior art, none of the interfaces between single crystal and polycrystal is flat, thereby causing variance of characteristics of BPT to occur. More specifically, when the carriers injected from the base into the emitter are recombined in the emitter, the emitter will become internally nonuniform, and therefore in the individual BPT prepared, the base current value is not constant, but variance will become greater between the respective BPT. In the present embodiment as shown in Fig. 7B, the thin film 30 is prepared on the first n + region 6 which is a single crystal, the polycrystal layer 8 is formed on said thin film (silicon oxide film in the present embodiment), and therefore its interface is flat on the atomic order. The polycrystal layer 8 is deposited through the stable thin film 30, and therefore rearrangement of the polycrystal by heat treatment will not readily occur, and it is also stable in the later heat treatment. In micro-crystal Si, amorphous Si, etc. of the prior art (deposition temperature 100 to 300 °C), the characteristics changed easily by heat treatment at 400 to 600 °C, whereby deterioration of current amplification ratio h FE will readily occur. In the present embodiment because the crystal is a polycrystal, its deposition temperature is higher, for example, about 550 to 650 [°C] in the case of polycrystalline Si, and therefore in addition to greater crystal grain size, substantially no hydrogen is contained, with the crystal size in the later steps being little, and yet substantially without change by elimination of hydrogen. In the case of polycrystalline Si, it can sufficiently stand a temperature up to about 900 [°C] and an extremely stable BPT can be obtained. The interface of the polycrystal layer 8 exists at the interface with the thin film 30, and therefore the interface with the emitter region which is a single crystal becomes extremely flat. This is an extremely important factor for stabilizing the BPT characteristics. As is apparent from the above description, the material of the above-mentioned thin film 30 is required to be stable, and may be desirably chemically stable materials such as SiO 2 , Si 3 N 4 , SiC, Al 2 O 3 , etc. To add further, the interface between the thin film 30 and the single crystal is also extremely important, and the recombination level at the interface is required to be low. As shown in Fig. 6, within the polycrystal layer 8, a convex potential barrier against electrons is formed. On the other hand, a concave potential barrier is formed against positive holes. As shown in Fig. 8A, when the depth of potential well is defined as - B , and the width as a , the transmission probability T th of the carriers is: T th = [1 + Bh 2 sin 2 αa 4E(E +  B ) ] -1 where α = [ 2m* ( Bh + E) ℎ 2 ] 1/2 As an example, if m*  Bh a 2 /ℎ 2 = 8, the transmission probability T th will be as shown in Fig. 8B. Here, E is the energy of electrons, and when E/ Bh < 1, transmission probability is markedly lowered. Since E is generally about kT, the positive hole impeding effect occurs when  B > kT. Fig. 9 shows the characteristics of reciprocal number (electro-conductivity) of the sheet resistance R of the polycrystalline silicon practiced in the present embodiment versus reciprocal number of temperature T. In the case of (a)′, the impurity concentration of polycrystalline silicon is the highest, and then the concentration becomes lower in the order of (b)′, (c)'. In this case, the deposition temperature, the thickness, the heat treatment are the same conditions. In (b) ', (c) ', the potential as previously mentioned arises, and the mechanism of current flow becomes predominantly hot electron radiation type, whereby characteristics are changed. Improvement of the BPT characteristics is effective if at least 1/R is flat versus temperature, or 1/R is increased by temperature elevation. As contrasted to the emitter by use of the polycrystalline silicon of (a)', the BPT by use of the polycrystalline silicon of (b)', (c)' is reduced in base current successively as 2/3, 1/3. Accordingly, h FE becomes respectively 1.5- and 3-fold. As shown in Fig. 1, the first n + region 6 is formed within a single crystal. In the case of determining base current, the first n + region 6 also becomes an extremely important factor. Next, the above-mentioned tunnel effect is to be described. When electrons from the semiconductor material layer 8 pass through the emitter region E R shown in Fig. 6, it can be described by referring to a model of barrier potential as shown in Fig. 10A. Here, when  B is defined as the barrier height and a as the barrier width, the tunnel probability T te of the electron with an energy E having an effective mass m* becomes as follows from the Schrodinger's wave equation: T te = [1 +  B 2 sinh 2 β a 4E( B - E) ] -1 wherein β = [ 2m* ( Be - E) ℎ 2 ] 1/2 Here, if  B >> E, βa << 1, T t becomes as follows: T t ≃ 16 E  B exp (-2βa) wherein β ≃ (2m* B ) 1/2 / ℎ Next, when a voltage is applied, the potential becomes inclined in the thin film 30 as shown in Fig. 10B, whereby the tunnel probability T t is increased. Here, the total tunnel current I et may be speculated as follows: In the above formula, A is a constant, T t the tunnel probability in the above formula (1) , F c1 , F c2 are Fermi-Dirac distribution functions of the above-mentioned semiconductor material layer 8 and the emitter region E R , and n c1 , n c2 represent the state densities of the conduction bands of said both materials. In the foregoing formula (4), when  B >> E, the item concerned with the thickness of the thin film 30 comes outside of the object to be integrated, becoming as follows: I et ∝ e x p (-2βa) whereby it can be understood that an exponential functional effect occurs in the thickness of the thin film 30. Thus, the thickness contributes most greatly to the electron tunnel current I et . In the foregoing formula (5), another important item is the following item: F c1 (1 - F c1 ) wherein F c1 denotes a probability of existence of electron at a side of A. (1-F c2 ) denotes a probability of an inexistence of electron at a side of B, and a product thereof greatly effects a probability of an electron transition, but for increasing the item of this product, a voltage corresponding to about kT or higher may be applied on the thin film 30, and, for example, it may be about 0.025 V at room temperature. In the case of BPT, the voltage drop in the above-mentioned thin film 30 is about the above-mentioned voltage value and, as shown in Fig. 10B, during voltage application, the existing probability is shifted in energy as shown by A, B, whereby in the energy band having the same energy as the energy of electrons on side of the semiconductor material layer 8 (the left side in Fig. 10B), there exists no electron on the emitter side (right side in Fig. 10B) and transition of electrons can be readily effected. Also, by voltage application on the thin film 30, the barrier height is slightly reduced. In the present embodiment, as shown in Fig. 6, both the thickness W EO of the emitter region E R and the concentration Ni are important factors for reducing the base current. Usually, the above-mentioned thin film 30 has a thickness of 5nm (50 Å) or less, which is comparatively smaller as compared with the thickness of the n + emitter region 6, and the distance W E from the emitter-base junction portion to the polycrystal layer 8 is represented by: W E ≃ W EO + δ and becomes substantially equal to W EO . On the other hand, another important factor in the present embodiment, namely inhibition of minority carriers injected from the base, is effected at the interface between the polycrystal layer 8 and the thin film 30. Of course, since the tunnel probability for electrons and positive holes in the thin film 30 is greater for electrons, the reduction effect of the base current by positive holes is obtained as the overlapping action of the both. Next, the constituents of the current of the above-mentioned BPT are to be described. The collector current J c is approximately represented by the following formula (6): J c = q·D n ·n i 2 N B ·W B {exp( V BE kT ) - 1} wherein the diffusion distance is made longer than the base width. N B is the base concentration, W B the base width, D n the diffusion distance of electrons, n i the intrinsic carrier density of Si and V BE the base-emitter applied voltage. On the other hand, the base current comprises the recombination current J Brec in the base and the diffusion current J Bdiff of the positive holes injected from the base into the emitter. Here, the recombination current J Brec is represented by: J Brec = q·D n ·n i 2 ·W B 2N B ·L n 2 {exp( V BE kT ) - 1} wherein L n is the diffusion distance of electrons. Shortly speaking, in the homo-junction type BPT of the prior art, J Bdiff is the main component, and no high current gain can be obtained. The diffusion current J Bdiff1 in the homo-BPT of the prior art when the diffusion length L P of the positive holes is smaller than the emitter thickness W E (case 1) (L P << W E ) is represented by: J Bdiff1 = q·D P L P · n i 2 N E {exp( V BE kT ) - 1} On the other hand, when shallowing of the emitter junction accompanied by higher integration is effected, the relationship becomes L P >> W E (case 2), whereby the diffusion current J Bdiff2 is represented by: J Bdiff2 = q·D P W E · n i 2 N E {exp( V BE kT ) - 1} Therefore, the diffusion current becomes further greater, whereby the current amplification ratio h FE of BPT is reduced. In the case of the present embodiment, when the recombination speed at the hetero-interface is made a negligible value, the diffusion current J Bdiff3 is represented by the following formula (10) (L P >> W E ): J Bdiff3 = qD P ·W E L P 2 · n i 2 N E {exp( V BE kT ) - 1} In BPT of the present embodiment, in the above-mentioned case 1, the diffusion current J Bdiff becomes W E /L P -fold relative to the homo-junction form BPT of the prior art. Further, for the above-mentioned case 2, the diffusion current J Bdiff becomes (W E /L P ) 2 -fold. Thus, in the present embodiment, the diffusion current J Bdiff can be dramatically reduced. In other words, the current amplification ratio h FE can be dramatically increased. In the MIS structure BPT of the prior art, there exists no diffusion J Bdiff because W E =0, but other current components exist. Fig. 11 is a graph showing schematically the current-voltage characteristics of the transistor, the axis of abscissa showing the applied voltage between the base-emitter, the axis of ordinate the base current I B and the collector current I C represented in logarithmic values. In the BPT of the present embodiment, the collector current I C and the base current I B become substantially in parallel to each other, and also in the fine current region (H P ), the current amplification ratio h FE (=I C /I B ) becomes a constant value. In the MIS structure BPT of the prior art, excessive current flows in the fine current region (H O ). The base current in the BPT according to the present embodiment is primarily the recombination current represented by the above formula (7), and the maximum value h FEmax of the current amplification ratio in this case is as follows: h FEmax = (L n /W B ) 2 and the upper limit of h FE is determined only by the base conditions. According to the present embodiment, h FE can be made 10000 or higher. Fig. 12 shows the relationships between the impurity concentration in the above-mentioned n + emitter region 6 and the diffusion distance L P of the minority carriers (positive holes) and the life τ P of said minority carriers (positive holes). From the condition determined by the formula (10), it is preferable that the emitter depth should be made at least about 1/5 of the diffusion distance of positive holes. Next, the preparation process of the semiconductor device shown in Fig. 1 is to be described. (1) On a substrate 1 of a predetermined conduction type (p-type or n-type) is formed an n + embedded region 2 with an impurity concentration 10 15 to 10 19 [cm -3 ] by ion injection (or impurity duffusion, etc.) of As, Sb, P, etc. (2) By epitaxial technique, etc. an n-type region 3 with an impurity concentration of 10 14 to 10 17 [cm -3 ] is formed. (3) An n + region 7 for reducing the resistance of the collector (with an impurity concentration of 10 17 to 10 20 [cm -3 ]) is formed. (4) An insulation film 102 for element separation is prepared by the selective oxidation method or the CVD method, etc. (5) In the active region, a p + region 5 and a p region 4 which is the base region are formed by the ion injection method, etc. (6) After opening of an emitter contact on the insulation film 101, an n + emitter region doped with As, Sb, P, etc. (impurity concentration 5 x10 17 to 5 x 10 20 [cm -3 ]) 6 is formed by the ion injection method or the thermal diffusion method. (7) A thin film 30 is prepared by oxidation at lower temperature of 500 °C to 650 [°C] or by thermal oxidation by rapid thermal acceleration (RTA). (8) After deposition of a polycrystalline Si doped to n + according to the LPCVD (Low Pressure Chemical Vapor Deposit ion) method, and introduction of impurities by ion injection, diffusion, etc., it is subjected to patterning. (9) An insulation film 103 is deposited, which is annealed and then subjected to opening of contact. (10) An Al-Si (1 %) which becomes the electrode 200 is subjected to sputtering, followed by patterning of the Al-Si. (11) After alloy formation of the Al-Si electrode, a passivation film is formed. According to the procedure as described above, an MIS structure BPT is completed. As the above-mentioned thin film 30, a silicon oxide film is the optimum, because it can be easily formed at low temperature, but an insulation film such as silicon nitride film, alumina film, etc. may be also employed. Also, by use of SiC, etc., a structure which becomes the tunnel type barrier may be formed. For example, single crystal SiC, as compared with Si has a conduction band energy difference ΔEv=0.53 [eV], a valence electron band difference ΔEC=0.55 [eV] and a band gap Eg=2.2 [eV], and when both SiC and Si are junctioned stepwise in n-type, it becomes to have a structure different from the semiconductor/insulator junction. Fig. 13A, 13B, 13C each show a band structure of hetero-junction mutually of the same conduction type (n-type in this case), namely the isotype. Fig. 13A shows the junction of the n-type Si and the n-type SiC, ΔEC, ΔEV appearing respectively above and below, and a barrier  W called notch being formed on the conduction band side, while on the valence electron side, an energy difference of the following is created: ΔEc + ΔEv - ΔEf On the other hand, by junction of the n-type Si, the n-type SiC and the n-type Si, the energy level becomes as shown in Fig. 13B. Further, by forming SiC into a thin film, the SiC will be depleted to become similar to an insulation material, whereby the energy level becomes as shown in Fig. 13C. With the structure shown in Fig. 13C, the electron current can be made-greater. In Fig. 13A to Fig. 13C, an example using SiC is shown, but it will be apparent that other materials with broad forbidden band gap can be also employed. Fig. 14 shows a second semiconductor device according to the second embodiment of the present invention. In this embodiment, an emitter region 6 is formed by epitaxial growth on the base region (p-type region 4), and on the emitter region 6 is formed a thin film 30 for tunnel. By making such structure, it becomes that there is no carrier diffused therearound due to no area distributed within base, whereby it becomes possible to obtain a current amplification ratio which is approximate to the above-mentioned maximum amplification ratio h FEmax . Next, Fig. 15 shows the third embodiment of the semiconductor device of the present invention, and this embodiment is different from the above-described first embodiment in that a semiconductor material layer 8 is formed on the thin film 30 and a semiconductor layer 10 of a material with narrower forbidden band gap than said semiconductor material layer 8 is further formed on said semiconductor material layer 8. With such construction, ohmic resistance between the emitter and the metal is improved. If the semiconductor material layer 8 is a polycrystalline or amorphous SiC, the semiconductor layer 10 should be preferably selected as Si, while if the semiconductor material layer 8 is Si, it is desirable that Ge, etc. should be used as the semiconductor layer 10. The conduction type of the semiconductor layer 10 is the same as that of the semiconductor material layer 8. Fig. 16 is a circuit example showing an example of the electronic device as an application example of the semiconductor device according to the above-mentioned embodiment. It shows the case when the BPT shown in the above-described embodiment 1 is used in the solid image pick-up device disclosed by the present Applicant in Japanese Patent Application No. 62-321423. More specifically, in Fig. 16, the transistor Tr constituting the sensor cells C 11 , C 12 , ... C mn of the area sensor AS employs the MIS type BPT shown in the above-described first embodiment. When the area sensor AS shown in Fig. 16 is used as a colour camera, the actuation of reading optical informations of the same photoelectric converting device for plural times is performed. In this case, for reading for plural times from the same element, the ratio of the electrical output during the first reading to that during the second reading and thereafter is a problem, and correction is required when the value of this ratio has become smaller. When the ratio of the first reading output to the second is defined as the non-destruction degree, the non-destruction degree is represented by the following formula: Non-destruction degree=(C tot x h FE )/ (C tot x h FE + C v ) Here, C tot indicates the total capacity of the transistor Tr connected to the base shown in Fig. 16, which is determined by the base-collector capacity C bc and C ox . C v is the floating capacity of the reading line shown by VL 1 , ... VL n . However, C ox may not sometimes exist depending on the circuit system. Therefore, the above-mentioned non-destruction degree can be easily improved by increasing the current amplification ratio h FE . In other words, the non-destruction degree can be made greater by increasing h FE . Here, in an area sensor corresponding to HD (High Division), namely high vision, since C tot =10 [pF] , C v =2.5 [pF] , for example, for making the non-destruction degree 0.90 or higher, h FE is required to be 2250 or higher. For obtaining sufficient non-destruction degree, it may be estimated that h FE is required to be 2000 or higher. In contrast, in the prior art, for example, in homo-junction BPT, h FE is about 1000, and hence no sufficient non-destruction degree can be obtained, while in the semiconductor device of the preferred embodiments, excellent non-destruction degree can be obtained because h FE can be made sufficiently great. Further, desirably, the non-destruction degree should be 0.98 or higher. In this case, h FE is required to be about 10000 or more, but it is difficult to obtain such a value in the homo-junction BPT of the prior art. In the embodiment shown in Fig. 16, an area sensor was exemplified, but the present invention is also applicable to a line sensor as a matter of course. Also, for the transistor, BPT as described in the second and third embodiments can be employed. Referring now to Fig. 1, the fourth embodiment of the semiconductor device of the present invention is described. In this embodiment, similarly as in the first embodiment, the above-mentioned thin film 30 is formed extremely thinly (thinner than the MIS structure BPT of the prior art) so that there may be little difference in tunnel probability both of the carriers of positive holes and electrons. At least positive holes contribute sufficiently as the carriers of current, and the positive holes passed through said thin film 30 are impeded by the polycrystalline layer 8. 30 is a thin film, and said thin film 30 comprises a thin insulation material for flowing tunnel current therethrough. In a polycrystalline silicon, in the region (b) shown in Fig. 5, when the grain size of the polycrystal becomes smaller, the quantum effect as described in detail below will occur. More specifically, for example, when a n + type polycrystalline silicon is considered, the state in which free electrons are confined within one grain because of the potential barrier formed at its grain boundary may be realized. As the result, fine particles will behave as if like a three-dimensional potential well formed by the grain boundary, and the electrons ordinarily existing continuously in the conduction band will exist scattered by such well. When the above-mentioned well is approximated as a cube with one side of a , the energy of electrons existing at the conduction band may be represented by the following formula: E n1,n2,n3 = π 2 ℎ 2 2a 2 { n 1 2 + n 2 2 m t + n 3 m ℓ } Here, m t , m ℓ are respectively the longer axis and shorter axis effective masses of the electrons, and n i is an integer. When the film thickness of the polycrystalline silicon layer is made, for example, 10nm (100 Å) the above-mentioned formula (14) becomes as follows: Fig. 17A shows schematically the manner of quantization of the energy of electrons. As shown in the same Figure, the energy of the electrons is dispersed in the conduction band (E 111 , E 121 , E 122 , etc.). For example, supposing that they follow the above formula (15), when one side a of the above-mentioned well is a=10nm (100 Å), the lowest energy (base energy) of the electrons will be higher by 20 [meV] than the conduction band. The electrons of the impurities introduced into the polycrystalline silicon will embed successively this level. Fig. 17B shows the state density P 3D of an ordinary semiconductor of the prior art versus energy F. By three-dimensional quantization, the state density P 0D will take a scattered value at energy E 111 , E 211 as shown in Fig. 17C. Having described above by referring to the well as a cube, also in the case of a columnar shape, quantization is effected as its dimensions become smaller. In this case, as shown in Fig. 17D, a scattered state density P 1D is possessed at the energy E 11 , E 21 . More specifically, although electrons can be filled continuously for energy under crystalline state, only incontinuously energy of electrons can be taken by quantization, resulting in change of the Fermi level of the polycrystalline silicon. Thus, also in the materials having the same impurity density, as the well becomes columunar, cubic, the energy level of the electrons will be scattered (Fig. 17C), and when the electrons are filled at this level, if one side is of the same size, the electrons exist even to the place of the cubic material with the highest energy. In other words, in the case of a cubic body, the Fermi level becomes the highest. To further add, in quantization of cubic body, columnar body, the quantization effect will be greater as the dimensions are smaller. According to the experimental data, with a film thickness of the polycrystal layer being about 5 to 10nm (50 to 100 Å), the change in Fermi level can be sufficiently seen. With a thickness of 50nm (500 Å) or higher, there is substantially no effect, and the quantization effect occurs with a thickness of 30nm (300 [Å]) or less. Fig. 18 shows the simulation results of the number of electrons n 100 filled in the well of a cube with one side of 10nm (100 Å) calculated for the change in Fermi energy E F . The curve K 1 shows the case of a crystal, and the curve K 2 the case when quantized. However, Fermi energy on the axis of abscissa is the energy value measured from the bottom of the conduction band, and it can be understood from this Figure that Fermi energy will be introduced into the conduction band as the electrons are increased. Fermi energy will exist on the conduction band, as the impurity concentration is increased, and the dimensions of the cubic body are smaller. When the polycrystalline silicon is of the P-type conduction type, Fermi level exists within the valence electron band. On the other hand, the upper limit and the lower limit of the impurity concentration is determined by the position of the region (b) in Fig. 4, and the region (b) is the most desirable. Since this is determined from the size of the grains of the polycrystal and the interface level of the grain boundary, it should be properly determined from the experimental results. If the size of grain becomes smaller, the region (b) will be shifted toward the higher concentration side. Fig. 19 shows a potential diagram along the line A-A′ in Fig. 1. In Fig. 19, W B shows the neutral region width of base, W EO the neutral region width of the emitter and δ the thickness of tunnel ultra-thin film. To summarize, the most important point in the present embodiment resides in small grain of the polycrystal in the n + emitter region 6 and the polycrystal layer 8 to give rise to the quantization effect, giving different height of Fermi level, whereby the region of the polycrystal layer 8 becomes a barrier against the positive holes injected from the base and therefore diffusion of positive holes is impeded to reduce base current. The tunnel thin film 30 is formed in a ultra-thin film (approximately 1nm (10 Å) or less) so that the both carriers of electrons and positive holes may show the tunnel phenomenon, and the emitter resistance is also lowered. The greatest characteristic function of the above-mentioned thin film 30 is separation of the polycrystal layer 8 from the n + region 6 which is a single crystal, simultaneously with flattening of the interface, and also effects stabilization of the polycrystal layer 8. More specifically, as described above, for example, when surface washing is completely effected by sputtering, heat treatment, etc. on the n + region 6 which is merely a single crystal as in the prior art structure shown in Fig. 7A to deposit the polycrystal layer 8 under the surface state without naturally oxidized film, a crystal with about a grain size of polycrystal is epitaxially grown on the single crystal, whereby the interface with the inherent single crystal (B-B′ in Fig. 7A) changes to become wavy (or epitaxially grown thinly, followed by becoming wavy), and no constant shape can be always maintained. If the cleaning process on the surface is insufficient and a polycrystal is deposited on the naturally oxidized film and subjected to heat treatment at 1000 °C or higher, the oxide film may be partially broken to effect locally epitaxial growth. In an extreme case, the naturally oxidized film becomes shaped like ball, and the polycrystal recrystallized in single crystals. Thus, in the case of the prior art structure, all of the interfaces between single crystal and polycrystal become unflat, thereby causing variance in characteristics of BPT to occur. More specifically, when the carriers injected from the base into the emitter are recombined, the emitter becomes internally nonuniform, and therefore in individual BPT prepared, the base current values are not constant, whereby variance between the respective BPT becomes larger. In the embodiment shown in Fig. 7B, the thin film 30 is formed on the n + region 6 which is a single crystal, and the polycrystal layer 8 formed on said thin film (silicon oxide film in this embodiment), and therefore its interface is flat on the atomic order. The polycrystalline 8, which is deposited through the stable thin film 30, is not susceptible to rearrangement of the polycrystal by heat treatment and also stable in the later heat treatment. In micro-crystal Si, amorphous Si, etc. of the prior art (deposition temperature 100 to 300 °C), their characteristics are readily changed by heat treatment at 400 to 600 °C, whereby deterioration of current amplification ratio h FE will readily occur. In the present embodiment, because the crystal is a polycrystal, the deposition temperature becomes higher. For example, in polycrystalline Si, the temperature is about 550 to 650 [°C], the crystal grain size is large on the surface of the polycrystal, but substantially no hydrogen is contained, and there is little in change of crystal grain size in subsequent steps and also no change by elimination of hydrogen will occur. However, it has been confirmed that the grain size in the vicinity of the interface with SiO 2 is small 5 to 10nm (50 to 100 Å). In the case of the polycrystalline Si in the present embodiment, it can stand sufficiently a temperature up to 900 [°C] to give an extremely stable BPT. Since the interface of the polycrystal layer 8 exists at the interface with the thin film 30, the interface with the emitter region which is a single crystal is extremely flat. This exists an extremely important factor in stabilizing the BPT characteristics. As is apparent from the above description, the material of the above-described thin film 30 is required to be stable, and therefore should be desirably chemically stable materials such as SiO 2 , Si 3 N 4 , SiC, Al 2 O 3 , etc. To add further, the interface between the thin film 30 and the single crystal is also extremely important, and the recombination level of the interface is required to be made low. In the embodiment shown in Fig. 19, the thickness W EO and the concentration Ni of the emitter region E R are also important factors for reducing base current. Fig. 19 shows the potential diagram at the cross-section A-A' corresponding to the present embodiment in Fig. 1, and in the same Figure, E R shows the emitter region, B R the base region, and C R the collector region. Next, the process for preparation of the semiconductor devices of the present embodiment shown in Fig. 1 is described. (1) On a substrate 1 of a predetermined conduction type (p-type or n-type) is formed an n + embedded region 2 with an impurity concentration of 10 15 to 10 19 [cm -3 ] by ion injection (or impurity diffusion, etc.) of As, Sb, P, etc. (2) By epitaxial technique, etc. an n-type region 3 with an impurity concentration of 10 14 to 10 17 [cm -3 ] is formed. (3) An n + region 7 for reducing the resistance of the collector (with an impurity concentration of 10 17 to 10 20 [cm -3 ]) is formed. (4) An insulation film 102 for element separation is prepared by the selective oxidation method or the CVD method, etc. (5) In the active region, a p + region 5 and a p region 4 which is the base region are formed by the ion injection method, etc. (6) After opening of an emitter contact on the insulation film 101, an n + emitter region doped with As, Sb, P, etc. (impurity concentration 5 x 10 17 to 5 x 10 20 [cm -3 ]) 6 is formed by the ion injection method or the thermal diffusion method. (7) A thin film 30 is prepared by oxidation at lower temperature of 500 °C to 650 [°C] or by thermal oxidation by rapid thermal acceleration (RTA). (8) After deposition of polycrystalline Si doped to n + according to the LPCVD method, and introduction of impurities by ion injection, diffusion, etc., it is subjected to patterning. (9) An insulation film 103 is deposited, which is annealed and then subjected to opening of contact. (10) An Al-Si (1%) which becomes the electrode 200 is subjected to sputtering, followed by patterning of the Al-Si. (11) After alloy formation of the Al-Si electrode, a passivation film is formed. According to the procedure as described above, the BPT is completed. As the above-mentioned thin film 30, a silicon oxide film is the optimum, because it can be easily formed at low temperature, but an insulation film such as silicon nitride film, alumina film, etc. may be also employed. Also, by use of SiC, etc., a structure which becomes the tunnel type barrier may be formed. For example, SiC, as compared with Si has a conduction band energy difference ΔEv=0.53 [eV], a valence electron band difference ΔEc=0.55 [eV] and a band gap Eg=2.2 [eV], and when both SiC and Si are junctioned stepwise in n-type, it becomes to have a structure different from the semiconductor/insulator junction. With the structure shown in Fig. 13C, tunnel probability of electrons, positive holes can be made greater according to film thickness, whereby the electron current of positive holes, electrons can be made greater. With the structure in Fig. 13B, a hetero-structure similar to that of the prior art is obtained, through which only one of the carriers can be passed. In the present embodiment, both positive holes and electrons are passed and one of the carriers is impeded by the polycrystal. Si may be monocrystal, polycrystal, or amorphous. Fig. 20 shows a semiconductor device according to the fifth embodiment of the present invention. In this embodiment, on the polycrystal layer 8 having the quantum effect is further formed a low resistance layer 20, and the grain size in the region of said low resistance layer 20 is set greater as compared with that in the region of the polycrystalline layer 8, thereby effecting lower resistance. As is apparent from Fig. 4, the resistance in the region (b) is extremely sensitive to grain size, and the resistance of the metal electrode at the contact side is lowered even at the same concentration to reduce the emitter resistance. In this case, in the preparation steps, first a polycrystal layer 8 is deposited to a thickness corresponding to the thickness of the polycrystal layer 8 and the low resistance layer 20 superposed, and then the region corresponding to the low resistance layer 20 is made amorphous by ion injection, followed by heat treatment to make the grain size only in said amorphous region greater. Other than such preparation method, the above-mentioned low resistance layer 20 may be made amorphous with As, Sb, P, etc. which is n-type impurity, and then heat treatment may be performed, or alternatively it may be differently made amorphous with Ge, Si, etc. rather than injection of an impurity. However, the grain size of the polycrystal layer 8 will become larger, unless the heat treatment is carried out at 900 °C or lower. As another preparation method, there is also a method in which a polycrystalline silicon containing initially an impurity may be deposited, and only the above-mentioned low resistance layer 20 is made amorphous by ion injection with Ge, Si, etc., followed by heat treatment. It is critical that the amorphous region after ion injection should be made so as not to reach the interface between the polycrystalline silicon and the single crystalline silicon. Other constitutions are the same as in the first embodiment as described above, and redundant description is omitted. Fig. 21 shows the sixth embodiment of the present invention. In this embodiment, an n + emitter region 6 is formed by epitaxial growth on the P-type region 4 as the base region, and a thin film 30 for tunnel and a polycrystal layer 8 formed thereon. With such constitution, since the n + emitter region 6 is in contact in plane with the base region, diffusion of the carriers into the base region becomes smaller, whereby the lateral direction current of the emitter current becomes smaller to an advantage of the finely formed BPT. Other constitutions are the same as in the above-described first embodiment, and redundant description is omitted. Referring to Fig. 1, the seventh embodiment of the semiconductor device of the present invention is described. Also, in this embodiment, the above-mentioned thin film 30 is formed extremely thinly (thinner than the MIS structure BPT of the prior art) to make substantially no difference between the both tunnel probabilities of the carriers of positive holes and electrons. At least positive holes also contribute sufficiently as the carriers of current, and the positive holes passed through said thin film 30 are impeded by the polycrystal layer 8. The polycrystal silicon of this embodiment employs the impurity concentration ratio of the region (c), and the depletion layer width W at the grain boundary is represented approximately by the following formula: W = 2Q t Ni Ordinarily, tunnelling phenomena of electrons and positive holes are liable to occur at a film thickness of the thin film of 5nm (50 Å) or less, for example, if the trap level density Q t is made 5 x 10 12 [cm -2 ], the impurity concentration Ni is required to be 4 x 10 19 [cm -3 ] or higher. If the film thickness of the tunnel thin film is made 5nm (50 Å) or less, the impurity concentration Ni depends on Q t , but corresponds to the region (c), when the following relationship is valid: Ni ≧ 2Q t 5 x 10 -7 = 4 x 10 6 Q t [cm -3 ] Fig. 22 shows the potential diagram in this embodiment at the cross-section along the line A-A' in Fig. 1, and the base width is represented by W B , the single crystal emitter depth by W EO and the film thickness of the ultra-thin film by δ. What is the most important is the height Δ B of the barrier between the single crystal emitter and the polycrystal emitter. The height of the barrier Δ B reduces the base current as the barrier of the positive holes injected from the base region. The positive holes injected from the base region, after passing through the tunnel film, is further reduced to exp(-Δ B /kT), and becomes a value of e -1 if the height Δ B of the above-mentioned barrier is kT. Accordingly, if the height A B of said barrier is kT or higher which is the heat energy at said temperature T, there ensues the effect of base current reduction. The height of the barrier Δ B , in the present embodiment, is created by the difference in Fermi level between the emitter region of single crystal and the polycrystal region. Due to such effect, a hetero-junction effect arises in the emitter region, whereby increase of current amplification ratio h FE can be effected. As a problem in designing, the above-mentioned constitution can be realized by making the concentration in the n + emitter region 6 smaller than that in the polycrystal layer 8. The relationship between the energy E i and the Fermi level E F can be represented approximately by the following formula: n-type semiconductor: E F -E i = kTℓn N D n i p-type semidonductor: E i -E F = kTℓn N A n i Here, N D and N A are respectively n-type, p-type impurity densities, and n i intrinsic semiconductor carrier density. Whereas, the above formula is the range to which Boltzman's statistic is applicable, but when the carrier density n i becomes higher concentration, Fermi-Dirac statistic is applied and therefore the above formula cannot be employed. Fig. 23 shows the relationship between Fermi level E F and carrier density n i in semiconductor silicon. The axis of abscissa in the same Figure represents energy normalized with kT, namely (E F - E C )/ kT in the case of n-type semiconductor and (E V -E F )kT in the case of p-type semiconductor, respectively, and its axis of ordinate carrier density n i [cm -3 ]. n i is a value approximately equal to impurity density at normal temperature. In the formula showing the above-mentioned axis of abscissa, E C , E V are respectively energies of the conduction band end, the valence electron band end, and the fact that the normalized energy is zero means that Fermi level E F coincides with E C , E V . As compared with such coincidence, if the carrier density n i is higher, it means that E F is not in the forbidden band but incorporated into the conduction band in n-type, and into the valence electron band in p-type. The impurity concentration at this time becomes 2.1 x 10 19 [cm -3 ] in the case of n-type and 8 x 10 18 [cm -3 ] in the case of p-type. In Fig. 23, the lines shown by chain lines (curved line BD 1 , straight line BD 2 ) are examples to which Boltzman's statistic is applied, and the lines shown by broken lines (curved line FD 1 , straight line FD 2 ) are examples to which Fermi-Dirac statistic is applied, and difference occurs between the both statistics in the range where the normalized energy is larger than 1. More specifically, when the normalized energy is larger than 1, Fermi energy cannot be correctly evaluated unless Fermi-Dirac statistic is used. In the same Figure, the plots of the symbol O show the case of n-type semiconductor, and the plots of x the case of p-type semiconductor. The difference between n-type semiconductor and p-type semiconductor occurs due to difference in band structure, effective mass. Of course, with other materials, this value will be different. When the concentration in the vicinity of the emitter base region is defined as N E1 , and that in the higher concentration polycrystal region as N E2 , then from the above formula (18), the following relationship is approximately valid: N E2 ≥ eN E1 where e is a natural number (= 2.718). Under this condition, Δ B ≥ kT. Correctly, N E1 , N E2 will be determined by use of the data in Fig. 23. When the relationship Δ B ≥ 2kT is valid, the relationship becomes N E2 ≥ e 2 N E1 . In the present embodiment, the thickness W EO and the concentration N D in the emitter region E R shown in Fig. 22 are also important factors for reducing the base current. In the same Figure, E R represents emitter region, B R base region, and C R collector region. Ordinarily, the above-mentioned thin film 30 should preferably have a thickness 2nm (20 Å) or less. Since it is smaller as compared with the thickness of the n + emitter region 6, the distance W E from the emitter-base junction to the polycrystal layer 8 is represented by: W E ≃ W EO + δ thus becoming substantially equal to W EO . On the other hand, another important factor in the present embodiment, namely inhibition of the minority carriers injected from the base is effected at the interface between the polycrystal layer 8 and the thin film 30. Of course, the tunnel probability of electrons and positive holes in tunnel film is greater for electrons, and therefore the above-mentioned inhibition effect has also occurred simultaneously with said tunnel effect. Also in the case of the base current of the BFT according to the present embodiment, it becomes primarily the recombination current represented by the above formula (7), and the maximum value h FEmax of current amplification ratio in this case is as follows: h FEmax = 2 (L n /W B ) 2 whereby the upper limit of h FE is determined only by the base conditions. h FE according to the present embodiment is 10000 or higher. Fig.12 shows the relationship between impurity concentration N D in the above-mentioned n + emitter region 6 and the diffusion distance L P of minority carriers (positive holes) and the life τ P of said minority carriers. From this relationship, the emitter depth should be preferably made at least about 1/5 of the diffusion distance of positive holes. Next, the process for preparation of the semiconductor device of the present embodiment shown in Fig. 1 is described. (1) On a substrate 1 of a predetermined conduction type (p-type or n-type) is formed an n + embedded region 2 with an impurity concentration of 10 15 to 10 19 [cm -3 ] by ion injection (or impurity duffusion, etc.) of As, Sb, P, etc. (2) By epitaxial technique, etc. an n-type region 3 with an impurity concentration of 10 14 to 10 17 [cm -3 ] is formed. (3) An n + region 7 for reducing the resistance of the collector (with an impurity concentration of 10 17 to 10 20 [cm -3 ]) is formed. (4) An insulation film 102 for element separation is prepared by the selective oxidation method or the CVD method, etc. (5) In the active region, a p + region 5 and a p region 4 which is the base region are formed by the ion injection method, etc. (6) After opening of an emitter contact on the insulation film 101, an n + mitter region doped with As, Sb, P, etc. (impurity concentration 5 x 10 17 to 5 x 10 19 [cm -3 ] 6 is formed by the ion injection method or the thermal diffusion method. (7) A thin film 30 is prepared by oxidation at lower temperature of 500 to 650 [C°] or by thermal oxidation by rapid thermal acceleration (RTA). (8) After deposition of a polycrystalline Si doped to n + according to the LPCVD method, n-type impurity of As or P is introduced by the ion injection method at high concentration (5 x 10 19 [cm -3 ] or higher), and subjected to heat treatment for activation. However, heat treatment is carried out at low temperature (850 [°C] or lower) so that it will not be diffused to the n + emitter layer 6 below the polycrystalline silicon layer, or within a short time by rapid thermal heating. Then, the polycrystalline layer 8 is subjected to patterning to form an emitter electrode. (9) An insulation film 103 is deposited, which is annealed and then subjected to opening of contact. (10) An Al-Si (1%) which becomes the electrode 200 is subjected to sputtering, followed by patterning of the Al-Si. (11) After alloy formation of the Al-Si electrode, a passivation film is formed. According to the procedure as described above, the BPT of the present embodiment is completed. What is important in the above-described process concerns preparation of the thin film 30 of (7) and setting of the emitter concentrations of (6), (8). The single crystalline emitter in (6) is required to set the depth of junction and the concentration so as to make the base current determined by the above formula (10) minimum. While shallowing by making higher the emitter concentration is one means, if said concentration becomes 10 19 [cm -3 ] or higher, the band-tailing effect with an impurity occurs to increase minority carriers in proportion to exp (ΔE/kT), whereby the base current represented by the above formula (10) begins to increase. When the concentration becomes higher, it becomes difficult to effect shallow junction also in the preparation process. This is because the impurity diffusion coefficient becomes larger as the impurity concentration is higher. Therefore, the emitter region which is a single crystal is made to have its concentration of a junction depth in the vicinity of 10 19 [cm -3 ]. On the other hand, the concentration of the polycrystal layer is set at least higher by about one cipher than the emitter region. In the BPT having no tunnel thin film of the prior art, diffusion occurred during heat treatment, thereby making preparation difficult, but in the present embodiment, due to the presence of the ultra-thin film 30, the diffusion speed of the impurity in said thin film is slower by 1 to 2 cipher as compared with single crystal, thus solving such problem. On the other hand, diffusion of an impurity with a grain boundary of polycrystal being interposed is faster by 1 to 2 cipher as compared in single crystal, whereby stable preparation of BPT can be performed. Other characteristic functions of the above-mentioned thin film 30 are separation of the polycrystal layer 8 from the n + region 6 which is the single crystal of the emitter region 6, simultaneously with flattening of its interface, and also effecting stabilization of the polycrystal layer 8. More specifically, when a polycrystal layer 8 is formed on the n + region 6 which is a mere single crystal, the crystal which has about the size of the polycrystal on the single crystal is epitaxially grown, whereby the interface with inherent single crystal will change to become wavy and a constant shape cannot be always maintained. In this case, if a polycrystal is deposited on the naturally oxidized film and subjected to heat treatment, the oxide film will be partially broken, whereby epitaxial growth occurs locally, or in an extreme case, the naturally oxidized film will become shaped like ball, resulting in recrystallization of the polycrystal into single crystal. Thus, in the case of all of the prior art structures, the interface between the single crystal and the polycrystal becomes unflat, thereby causing variance of characteristics of BPT. More specifically, when the carriers injected from the base into the emitter are recombined within the emitter, the emitter becomes nonuniform internally, and therefore in the individual BPT prepared, the base current value is not constant, but variance between the respective BPT becomes larger. In the present embodiment, the thin film 30 is formed on the n + region 6 which is a single crystal, and the polycrystal layer 8 formed on said thin film (silicon oxide film in this embodiment), and therefore its interface is flat on the atomic order. The polycrystal layer 8, which is deposited through the stable thin film 30, is not susceptible to rearrangement of the polycrystal by heat treatment and also stable in the later heat treatment. In micro-crystal Si, amorphous Si, etc. of the prior art (deposition temperature 100 to 300 [°C]), their characteristics are readily changed by heat treatment at 400 to 600 [°C], whereby deterioration of current amplification ratio h FE will readily occur. In the present embodiment, because the crystal is a polycrystal, the deposition temperature becomes higher. For example, in polycrystalline Si, the temperature is about 550 to 650 [°C], the crystal grain size is large, and in addition substantially no hydrogen is contained, and there is little in change of crystal grain size in subsequent steps and also no change by elimination of hydrogen will occur. In the case of the polycrystalline Si, it can stand sufficiently a temperature up to 900 [°C] to give an extremely stable BPT. Since the interface of the polycrystal layer 8 exists at the interface with the thin film 30, the interface with the emitter region which is a single crystal is extremely flat. This is an extremely important factor in stabilizing the BPT characteristics. As is apparent from the above description, the material of the above-described thin film 30 is required to be stable, and therefore as described previously should be desirably chemically stable materials such as SiO 2 , Si 3 N 4 , SiC, Al 2 O 3 , etc. To add further, the interface between the thin film 30 and the single crystal is also extremely important, and the recombination level of the interface is required to be made low. Also, by use of SiC, etc., the structure may be made a tunnel type barrier. For example, SiC as compared with Si has a conduction band energy difference ΔE v = 0.53 [eV], a valence electron band difference ΔE C = 0.55 [eV] and a band gap E g = 2.2 [eV], thus having a different structure from semiconductor/insulator junction when SiC and Si are both n-types and junctioned stepwise. As the barrier height  B of the thin film 30 for tunnel is lower, the direct tunnel probability becomes higher, whereby more current will flow. That is, the emitter resistance is lowered to give a preferable device. As the material for said thin film 30, those which are stable and narrow in forbidden band width are desirable. Next, Fig. 24 shows a semiconductor device according to the eighth embodiment of the present invention. This embodiment has the emitter region 6 in the above-described first embodiment formed by epitaxial growth, and further a thin film 30 for tunnel and a high concentration polycrystal layer 8 laminated thereabove. With such constitution, the emitter region 6 is in contact in plane with the base region, and most of diffusion of carriers from the emitter region to the base region is inhibited, whereby the lateral direction current in the emitter region is small and the influence by the dimensional precision on current amplification ratio can be reduced. Accordingly, it is useful for application to fine formation of semiconductor device, highly integrated photoelectric converting device. Other constitutions, actions are the same as in the seventh embodiment as described and therefore redundant description is omitted. Fig. 25 shows the ninth embodiment of the present invention. In this embodiment, between the high concentration polycrystal layer 8 and the electrode 200 in the seventh embodiment, a so called barrier metal layer 10 of TiN, TiW, Mo, W, etc. which acts as the diffusion barrier is formed to inhibit the reaction between the polycrystal and the electrode (Al), whereby a semiconductor which is stable and little in variance can be prepared. Since the electrode (Al) is susceptible to diffusion within the polycrystal, it may have influences on the characteristics of BPT in some cases. Other constitutions and actions are the same as in the above-described first embodiment, and therefore redundant description is omitted. The BPT's according to the first to the ninth embodiments as described above were found to have extremely stable transistor characteristics. The fourth to the ninth embodiment as described above can be applied to the transistors to be used for the sensor portion of the electronic device as shown in Fig. 16 similarly as the first to the third embodiments, as a matter of course.

Claims: A semiconductor device comprising: a collector region (3,7) of first conductivity type; a monocrystalline base region (4,5) of second conductivity type; a monocrystalline emitter region (6) of the first conductivity type providing at an interface with said base region (4,5) an emitter-base junction in single crystal; a thin film (30) provided on said emitter region; and a polycrystalline layer (8) laminated on said thin film (30); which semiconductor device is characterised in that: said thin film (30) is so thin that it results in an appreciable tunnel current flow for both majority and minority carriers, the tunnelling probabilities of both majority and minority carriers being substantially equal to each other; and said polycrystalline layer (8) provides a potential barrier to the flow of carriers injected from said base region (4,5) thereby to reduce base current and increase current amplification ratio. A semiconductor device as claimed in claim 1 wherein said potential barrier is located at the grain boundaries (Bc) of said polycrystalline layer (8). A semiconductor device according to claim 2, wherein said polycrystalline layer has a resistance value, the inverse of which is either approximately constant being independent of temperature, or alternatively an increasing function of temperature. A semiconductor device according to claim 2, wherein the main constituent of said polycrystalline layer (8) is silicon. A semiconductor device according to claim 2, wherein said thin film (30) is of thickness not greater than 5nm. A semiconductor device according to claim 2, wherein there is provided on said polycrystalline layer (8), a semiconductor layer (10) having a band gap narrower than that of said polycrystalline layer (8). A semiconductor device as claimed in claim 1 wherein said potential barrier is a potential barrier between said polycrystalline layer (8) and said emitter region (6) at the interface of said polycrystalline layer (8) and said thin film (30) which is present under the thermal equilibrium condition that the Fermi level of said polycrystalline layer (8) is aligned with the Fermi level of said emitter region (6). A semiconductor device according to claim 7, wherein said polycrystalline layer (8) has a Fermi level shift consequential to quantum confinement of carriers in the grains thereof. A semiconductor device according to claim 8, wherein said polycrystalline layer (8) has a thickness and grain size not greater than 30 nm. A semiconductor device according to claim 7, wherein said polycrystalline layer (8) has an impurity concentration of N, grain size of L, and trap level density Q t at grain boundaries, satisfying the inequality relation N < Q t /L. A semiconductor device according to claim 7, wherein said thin film (30) has a thickness not greater than 1 nm. A semiconductor device according to claim 11, having on said polycrystalline layer (8), a lower resistance polycrystalline layer (20) having a greater grain size. A semiconductor device according to claim 7, wherein said emitter region has an impurity concentration of N E1 , and said polycrystalline layer has an impurity concentration of N E2 , wherein they meet relation N E2 > e.N E1 wherein e denotes a natural number. A semiconductor device according to any of claims 1, 2 or 7, wherein said emitter region (6) has a thickness not greater than the diffusion length of minority carriers injected from said base region (4,5). A semiconductor device according to claim 7, wherein said thin film (30) has a thickness not greater than 2 nm. A semiconductor device according to any of claims 1, 2 or 7, wherein said thin film (30) is of SiO 2 , Si 3 N 4 , SiC, or Al 2 O 3 . A semiconductor device according to claim 7, wherein a barrier metal layer (10) is located between said polycrystalline layer (8) and an electrode (200). A semiconductor device according to claim 17, wherein said barrier metal layer (10) is of TiN, TiW, Mo, or W. A semiconductor device according to any of claims 1, 2 or 7, wherein said emitter region (6) is an epitaxial layer disposed on said base region (4). An electronic apparatus incorporating said semiconductor device according to any of claims 1, 2 or 7 as a photoelectric conversion device.

Inventors: MORISHITA MASAKAZU, MORISHITA, MASAKAZU, MORISHITA, MASAKAZU, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H01L29
IPC codes: H01L29, H01L21