A MOS integrated circuit with switched capacitors, having a full-wave-rectifying and integrating function

Abstract: A switched-capacitor circuit is described, which performs the functions of a full-wave rectifier and of an integrator and has a single operational amplifier (A1) and a comparator (CO1). The circuit is insensitive to the stray capacitances and offsets of the comparator (CO1) and the operational amplifier (A1). In particular, the input signal (V in ) is sampled during only one phase of the clock (CU) which pilots the operation of the switched-capacitance network.

Description: The present invention relates to a circuit for rectifying and integrating an alternating input signal of the kind defined in the first portion of Claim 1. A circuit of the aforementioned type is described in R. Gregorian, G.B. Temes, "Analog MOS Integrated Circuits for Signal Processing", J. Wiley & Sons, 1986, p. 442-444. In devices for detecting alternating signals greatly affected by noise, which are generated, for example, by sensors operating in difficult environments, circuits including a full-wave rectifier and an integrator as basic components are used. A circuit of this type is used, for example, in devices for detecting pinking in Otto engines, as described, for example in EP-A-0 421 952. Figure 1 of the appended drawings shows such a known arrangement including a piezoelectric accelerometric sensor S whose signal is processed by a band-pass filter 1 and then by a full-wave rectifier 2 and an integrator 3 which is activated cyclically for a preset time period Ta. In this application, the signal V₀ output by the integrator 3 provides information relating to the intensity of the sensor signal in the region of the resonance frequencies typical of pinking. A typical problem in the circuit 1 to 3 of Figure 1 is the integration of the inevitable offset voltage affecting the input signal of the integrator and of the offset voltage generated in the integrator itself, which may lead to the saturation of the output signal. This problem leads to the need to use low-offset components or to use techniques for automatically cancelling out the offset. With reference to the circuit of Figure 1, this can be formed by conventional circuitry with discrete components. The following, however, is concerned with solutions which enable the circuit to be produced in integrated form, specifically by CMOS technology and particularly with the use of circuitry of the type with switched capacitors. Figure 2 of the appended drawings shows a prior art embodiment of the rectifier and the integrator of Figure 1 with switched-capacitor circuitry which can be produced in integrated form. In this embodiment, the rectifier circuit 2 has an input, indicated I, and includes a circuit 10 for determining the polarity of the input signal V in and an amplifier circuit, generally indicated 11. The polarity-determining circuit 10 comprises: a comparator CO1, a capacitor C1 between the input terminal I and the inverting input of the comparator CO1, first and second controlled switches S1 and S2 between earth and the plate of C1 which faces the input terminal I and between the input terminal and C1, respectively, a third controlled switch S3 between the inverting input and the output of CO1, a controlled switch S10 between the output of CO1 and the input of a flip-flop circuit, generally indicated 12, whose outputs are indicated A and A . In operation, the switches S1, S3 and S2, S10 respectively are piloted in an on-off manner by two clock signals, indicated, ₁ and ₂ , which have the same frequency but are out of phase so that their respective active periods ("on" times, that is, the periods when the associated switches are closed) alternate and do not overlap, as shown by the corresponding waveforms shown in Figure 3. As experts in the art can immediately confirm, if the input signal V in is of positive (negative) polarity, the output A of the flip-flop 12 is at level "1" ("0"). The amplifier circuit 11 comprises: an operational amplifier A1 with its non-inverting input connected to earth, a capacitor C2 between the input terminal I and the inverting input of A1, a capacitor C3 between the inverting input and the output of A1, two controlled switches S4, S5 connected to C2, two further controlled switches S6 and S8 arranged between the input I and S4 and between I and S5, respectively, two further controlled switches S7 and S9 connected between earth and the connection between S4 and S6 and between earth and the connection between S5 and S8, respectively, two further controlled switches S12 and S13 in series and in parallel with C3 respectively, and a further controlled switch S11 between earth and the connection between C3 and S12. In operation, S4 and S12 are piloted by the clock or phase signal ₁ , whilst S5, S11 and S13 are piloted by the phase signal ₂. S7 and S8 are piloted by the output A of the flip-flop 12, whilst S6 and S9 are piloted by the output A of the flip-flop. When the input signal V in is of positive polarity, the outputs A and A of the flip-flop 12 control the switches S6, S7, S8 and S9 so that the operational amplifier A1 is connected as a non-inverting amplifier: during each "on" period of the phase signal ₂, the capacitor C2 samples the signal V in whilst, during each next "on" period of ₁, it outputs its charge. When the signal V in is of negative polarity, the switches S6, S7, S8 and S9 are controlled so that the operational amplifier A1 constitutes an inverting amplifier: in this case, the capacitor C2 samples the signal V in and outputs its own charge during each "on" period of the phase ₁. The integrator 3 comprises: an operational amplifier A2 with its non-inverting input connected to earth, two capacitors C4, C5 connected between the inverting input of A2 and the output of A1 and between the inverting input and the output of A2, respectively, two controlled switches S16 and S19 in series with C5, two further controlled switches S17 and S18 in parallel between the output and the inverting input of A2, and two further controlled switches S14 and S15 between the output of A1 and C4 and between earth and the connection between S14 and C4, respectively. In operation, S14 and S17 are piloted by the phase signal ₁, whilst S15 and S16 are piloted by the phase signal ₂. S18 and S20 are piloted by a signal R which is normally at level "one" and is at low level during the time period T a corresponding to the period during which the integrator 3 is required to integrate. This signal, like the phase signals ₁ and ₂, is generated by a control circuit, generally indicated CU in Figure 2, the details of which, however, are not essential for the purposes of the present description. An example of the waveform of R is shown in Figure 3. The switch S19 of the integrator 3, however, is piloted by a signal R complementary to R. As has been seen above, in operation, the rectifier 2 outputs its signal during each "on" period of ₁ : during each of these periods, the integrator 3 zeroes its own offset voltage by means of S17 which puts A2 into the voltage-follower configuration. During each "on" period of ₁ , the integrator 3 samples the voltage output by the rectifier 2, by means of the capacitor C4. The capacitor C5 acts as the integrating and memory element. It is discharged only at the end of the integration period T a by means of the switches S18, S19, S20 which are controlled by the signals R (reset) and R (integration signal). Obviously, the switches S19 and S16 can be replaced by a single switch controlled by the conjunction (AND) of the signals R and ₂. The offset voltage of A1 is cancelled out during the "on" times of ₂ by the discharge of the capacitor C3 and the connection of A1 in the "voltage-follower" configuration by means of S13. The solution described above with reference to Figure 2 requires a large number of components. A first considerable simplification of the circuit is possible by incorporating the rectifier and integrator functions in the same circuit, thus eliminating an operational amplifier, as shown in Figure 4 which also relates to a prior art concept. In this drawing, in which the components described above have again been given the same reference symbols, it can be seen that the circuit 10, 12 for determining the polarity of the input signal V in remains unchanged. The full-wave rectification and the integration of the input signal, on the other hand, are achieved with the use of a single operational amplifier A1 with its associated capacitors and controlled switches. The clock signals ₁ and ₂, as well as the integration control signal R, retain the same waveforms, shown by way of example in Figure 3. The capacitor C3 acts as an integrating and memory element which is zeroed at the end of the integration period T a by means of the switches S19 and S20 piloted by the signals R and R. The rectified and integrated signal is available at the output of the amplifier A1. The prior art circuit according to Figure 4 has a much simplified structure but also has a disadvantage. In effect, the input signal V in is sampled during the "on" periods of the phase signal ₁ or ₂ in dependence on its polarity. This presupposes that the signal V in is always available in both the phases ₁ and ₂. In some applications, a useful signal is not always available throughout the clock period of the switched-capacitor system. It is thus convenient always to be able to sample the input signal in the same phase, regardless of its polarity. This would also enable the cancellation, during the other phase, of any offset voltages in the circuit upstream which generates the signal V in . This function is particularly important when signals must be integrated over long periods of time. In fact, in such cases, the minimizing of the offset voltages of the input signal and of the components for processing it (amplifiers, comparators, etc.) becomes one of the main objectives for ensuring the correct operation of the device. Another prior art circuit for converting an a.c. voltage into a d.c. voltage is disclosed in DE-A-2 626 927. The object of the present invention, therefore, is to provide a new circuit in which the full-wave rectification and integration of the input signal are achieved by a single operational amplifier and in which the input signal is always sampled during the same phase, regardless of its polarity. This object is achieved, according to the invention, by means of a circuit whose main characteristics are defined in appended claim 1. As will become clearer from the following, the circuit according to the invention is insensitive to the stray capacitances and offsets of its active components (the comparator and operational amplifier). The input signal is sampled during only one phase of the clock which regulates the operation of the switched-capacitor circuit. Further characteristics and advantages of the invention will become clear from the detailed description which follows with reference to the appended drawings, in which: Figure 1, which has already been described, shows a prior art circuit for processing the signal supplied by a sensor, Figure 2, already described, is a prior art circuit diagram of an embodiment of a rectifier and an integrator with switched-capacitor circuitry, Figure 3, which has also already been described, is a series of graphs showing the waveforms of some signals used for controlling the circuits shown in Figure 2, Figure 4, likewise already described, shows a prior art variant of the circuitry shown in Figure 2, Figure 5 shows a detailed circuit diagram of a rectifier-integrator circuit according to the invention, and Figure 6 is a series of graphs showing the waveforms of some control signals used for piloting the circuit illustrated in Figure 5. With reference to Figure 5, in the circuit according to the invention, the circuit for determining the polarity of the input signal comprises a comparator circuit 10 identical to that described above, connected to a flip-flop circuit 12 which is preferably of the D type. The clock input of the flip-flop is piloted by the signal  ₂ which is complementary to the phase, signal ₂ . The outputs of the flip-flop 12 are indicated Q and Q . The circuit of Figure 5 includes two multiplexers MA and MB each having two inputs for receiving the clock signals ₁ and ₂ respectively, and an output. With reference to MA, two controlled switches S a and S b are provided between its ₁ and ₂ inputs and its output and are piloted by the outputs Q and Q of the flip-flop 12. Similarly, two controlled switches S c and S d are provided between the ₁ and ₂ inputs and the output of MB and are piloted by Q and Q respectively. If ₁ and ₂ have the wave forms shown in Figure 6, two signals, indicated  A and  B ,whose waveform depends on the polarity of the input signal V in , are available at the outputs of MA and MB. In effect, if V in is positive, Q is at level "0" and hence  A is equal to ₁ whilst  B is equal to ₂. If V in is negative, however, Q is at level "1" and hence  A is equal to ₂ and  B is equal to ₁ , as shown in Figure 6. With reference to the diagram of Figure 5, the rectifier-integrator circuit 2, 3 includes a single operational amplifier A1 with associated capacitors C2 and C3 and controlled switches S12, S13, S18, S19 and S20, arranged as in the diagram of Figure 4. it will be noted that in the diagram of Figure 5, however, the switches S12 and S13 are piloted by the signals output by the multiplexers MA and MB. The circuit according to Figure 5 operates as follows. During an integration phase T a , R is at level "1", S19 is closed, and S20 and S18 are open. The input signal V in is sampled during the "on" times of the phase signal ₂ and, in the same time periods, the comparator circuit 10 determines the polarity of the input signal. The signal output by the comparator circuit 10 appears on the line Q of the flip-flop 12 at the end of each "on" time of the phase signal ₂ (the leading edge of  ₂) and is stored for a period. If the input signal V in is of positive polarity, the multiplexers MA and MB cause the phase  A to coincide with the phase ₁ and the phase  B to coincide with the phase ₂. The rectifier-integrator circuit therefore assumes a configuraton such that the input signal V in is integrated by means of the integration capacitor C3 in non-inverting mode during the phase ₁. If the signal V in is of negative polarity, on the other hand, the multiplexers MA and MB cause the phase  A to coincide with the phase ₂ and the phase  B to coincide with the phase ₁ . In this case, the capacitor C2 samples and transfers its charge to the capacitor C3 during the phase ₂ and the latter integrates the signal in inverting mode. The signal output by the rectifier-integrator circuit is available at the output of A1 during the phase  A . The integration capacitor C3 is discharged during the phases in which integration is not being carried out, that is, outside the time window T a or rather when the signal R is at level "1" (S18 and S20 closed, S19 open). This capacitor is thus discharged at the input voltage of the operational amplifier A1 which is equal to the offset of that operational amplifier. The offset is thus automatically cancelled out, eliminating any chance of errors in the next integration phase. The use of a D-type flip-flop synchronised with the phase  ₂ prevents inaccuracies in the levels of the signals output by the multiplexers MA and MB which could destroy the voltage stored in the integration capacitor C3. In fact, because the active periods ("on" times) of the clock signals ₁ and ₂ do not overlap, the signals are transferred to the outputs of MA and MB in time periods during which ₁ and ₂ are both at low level, that is, between a trailing edge of ₂ and the next leading edge of ₁. The switched-capacitor circuit of Figure 5 performs the full-wave rectification and integration functions by means of a single operational amplifier which effects an inverting or non-inverting integration according to the polarity of the input signal. In particular, the input signal is sampled in only one phase, enabling the cancellation in the other phase of the offset in the circuits upstream which output the signal V in to be rectified and integrated.

Claims: A circuit for rectifying and integrating an alternating input signal (V in ), comprising: an input terminal (I), an operational amplifier (A1), a first capacitor (C2) between the input terminal (I) and the inverting input of the amplifier (A1) and a second capacitor (C3) between the inverting input and the output of the amplifier (A1), first and second controlled switches (S7, S6) between earth and the plate of the first capacitor (C2) which faces the input terminal (I) and between the input terminal (I) and the first capacitor (C2), respectively, third and fourth controlled switches (S12, S13) in series and in parallel with the second capacitor (C3), respectively, control circuit means (CU, 10, MA, MB) for generating control signals (₁, ₂,  A ,  B ) for said switches (S7, S6, S12, S13), including a clock-signal generator (CU) adapted to supply first and second clock or phase signals (₁, ₂) which have the same frequency but are out of phase so that the respective active periods alternate and do not overlap: characterised in that said control circuit means (CU,10, 12, MA, MB) are arranged to supply to the first and second switches (S7, S6) the said first and second clock or phase signals (₁, ₂) respectively, and to supply to the third and fourth switches (S12, S13) respective first and second piloting signals ( A ,  B ) which correspond to the first and second clock signals ( ₁, ₂) respectively when the input signal (V in ) has one polarity, but which correspond to the second and first clock signals ( ₂, ₁) respectively when the input signal (V in ) has the opposite polarity. A circuit according to Claim 1, characterised in that the control circuit means comprise: a polarity determining circuit (10, 12) adapted to provide a logic signal indicative of the polarity of the input signal (V in ), and multiplexing circuit means (MA, MB) connected to the clock-signal generator means (CU) and controlled by the polarity-determining circuit (10, 12). A circuit according to Claim 2, characterised in that the polarity-determining circuit (10, 12) comprises: a comparator circuit (CO1) with an inverting input and a non-inverting input, a capacitor (C1) connected between the input terminal (I) and the inverting input of the comparator circuit (CO1), first and second switches (S1, S2) controlled by means of the first and second clock signals ( ₁, ₂ ) respectively and arranged between earth and the plate of the capacitor (C1) which faces the input terminal (I) and between the input terminal (I) and the capacitor (C1), and a third controlled switch (S3) which is intended to be piloted by the first clock signal (₁) and is arranged between the inverting input and the output of the comparator circuit (CO1). A circuit according to Claim 3, characterised in that the output of the comparator circuit (CO1) is connected to a D-type flip-flop (12) to the clock input of which a signal (  ₂) complementary to the second clock signal (₂) is applied. A circuit according to claim 1, characterised in that it also includes: fifth and sixth controlled switches (S18, S19) in parallel and in series with the second capacitor (C3), respectively, and a seventh controlled switch (S20) between the second capacitor (C3) and earth; the fifth and sixth switches (S18, S20) being intended to be piloted so as to be open for each time period (Ta) in which the input signal (V in ) is integrated, whilst the sixth switch (S19) is intended to be piloted in a complementary manner.

Inventors: MALOBERTI FRANCO, POLITO GINO, SALERNO FRANCO, MALOBERTI, FRANCO, POLITO, GINO, SALERNO, FRANCO
Applicants: MARELLI AUTRONICA, MARELLI AUTRONICA S.P.A.
Application year: 1990
Main classification: G01R19
IPC codes: G01R19, G08C13, H03G1, F02B1