Dynamic random access memory cell

Abstract: A method for forming a memory cell for a dynamic random access memory includes the steps of first forming the transistors having gate electrodes (34) and source/­ drain regions (44) on either side thereof. An isolation trench (48) is formed in one of the source/drain regions with a portion (52) remaining. A masking layer (56) is formed over the surface of the substrate and an opening (62) formed therein to expose the source/drain region (52) and associated tungsten layer (50). A conductive plug (62) is formed in the opening followed by formation of an oxide layer (66). The plug (62) comprises the lower plate of the capacitor and then a conformal layer of conductive material (68) is formed over the surface thereof to comprise the upper plate of the capacitor. A planarized layer of oxide (69) is formed over the substrate and an opening (70) formed therein to expose the other of the source/drain regions (44). A contact plug (76) is formed in the opening (70) followed by formation of the interconnect layer (78).

Description: The present invention pertains in general to a method of forming memory cells, and more particularly, to a single transistor cell for a dynamic random access memory. Dynamic random access memories at present utilize what is known as a one transistor (1-T) cell to store bits of data. The 1-T cell has the advantage of low parts count, thus producing high density arrays. These cells are typically fabricated in a planar construction utilizing a single capacitor as a storage element and associated with some type of adjacent gate structure which normally is comprised of an MOS transistor. The area of the cell is therefore defined as the area of the transistor, the area of the capacitor and the area of the field isolation between cells. When the 1-T cell originally came into use, it was fabricated in a planar structure utilizing a diffused region as both the lower plate of the capacitor and the drain of the transistor. The upper plate of the capacitor was fabricated from an upper metal layer separated from the diffused region by a capacitive oxide layer. As photolithographic techniques improved, densities increased without deviating from the planar structure. Although the relative size of the capacitor did decrease somewhat, techniques such as the Hi-C cell enabled the capacity of the capacitor to be increased while the surface area decreased. However, there are limitations to the density that can be achieved with a planar construction due to the minimum size of the transistor, soft error problems, etc. There have been a number of capacitor construction techniques proposed to overcome the limitations of the planar construction sush as trench capacitors and stacked capacitors. Trench capacitors utilize trenches in the substrate in which the capacitors are formed to provide an increased surface area for the capacitor. Stacked capacitors place the capacitor over the transistor to increase the surface area available for the cell. Two prior art documents are JP-A-62286270 and JP-A-5658254 which relate to stacked capacitor cells. To date, the only technique that has been utilized with any success in high density DRAMs is the trench capacitor cell. However, this procedure requires not only fabrication of repeatable trenches, but also formation of the capacitor oxide and upper plate of the capacitor within a trench. At present, no realizable DRAMs allow for fabrication of the memory cell capacitor above the substrate. According to a first aspect of the present invention there is provided a method for forming a memory cell for a dynamic random access memory as defined by the appended claim 1. According to a second aspect of the present invention there is provided a method for forming memory cells in a dynamic random access memory array as defined by the appended claim 4. For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which: Figure 1 illustrates a cross-sectional diagram of a semiconductor substrate wherein a pattern for isolation trenches is defined on the surface thereof; Figure 2 illustrates the substrate of Figure 1 after formation of sidewall oxides layers on poly strips; Figure 3 illustrates the substrate of Figure 2 after etching the poly layer away followed by deposition of a layer of titanium; Figure 4 illustrates the substrate of Figure 3 after formation of the isolation trenches therein; Figure 5 illustrates a cross-sectional view of the substrate of Figure 4 after removal of the titanium, formation of oxide in the trenches, deposition of a layer of poly silicon, and deposition of an oxide layer; Figure 6 illustrates a cross-sectional view of the substrate of Figure 5 taken at a 90° angle with respect to the cross-section of Figure 5 and illustrating the patterning of the transistor gate; Figure 7 illustrates the step of forming the capacitor trench in the substrate of Figure 6; Figure 8 illustrates the step of forming the lower conductive plate of the capacitor; Figure 9 illustrates the step of forming the upper capacitor plate; Figure 10 illustrates the step of forming the contact opening to the source/drain of the transistor; Figure 11 illustrates formation of the conductive plug in the contact opening; Figure 12 illustrates an isometric view of the transistor structure; and Figure 13 illustrates a top view of the transistor structure without the upper connecting layer. It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features and that the cross-sectional diagrams have not necessarily been drawn to scale in order to more clearly show important features of the present invention. Referring now to Figure 1, there is illustrated a cross-sectional diagram of a semiconductor substrate 10 which, in the preferred embodiment, is comprised of a P-type semiconductor material that is doped to a suitable level. A layer of silicon nitride 12 is deposited onto the substrate 10 to a thickness of approximately 2000 Angstroms (10 Å = 1 nm). Thereafter, a conformal layer of polycrystalline silicon (poly) is deposited onto the substrate by chemical vapor deposition (CVD) techniques to a thickness of approximately 6000 Angstroms. This conformal layer is patterned and then etched by conventional techniques to form a plurality of longitudinal poly members 14 on the upper surface of the silicon nitride layer 12. Each of the poly members 14 is separated by a predetermined distance. Thereafter, a conformal layer 16 of silicon dioxide is deposited to a thickness of approximately 3000 Angstroms. With reference to Figure 2, the layer 16 is anisotropically etched to remove all portions of the layer 16 on essentially horizontal surfaces. This results in sidewall oxide layers 18 on the vertical sidewalls of each of the poly members 14. The thickness of these sidewall oxide layers 18 is a function of the thickness of the layer 16. As illustrated in Figure 3, after formation of the sidewall oxide layers 18, the poly members 14 are removed with a selective etch leaving behind the sidewall oxide layers 18. Thereafter, titanium is sputtered onto the substrate to a thickness of approximately 2000 Angstroms. In this process, it is desirable to have the titanium sputtered on in as directional a manner as possible. Therefore, the sputtering operation is performed at low pressure without backfilling with an inert gas such as argon. This results in a much more directional sputtering operation with a layer 20 of titanium approximately 2000 Angstroms thick, both on the substrate between the sidewall oxide layer 18 and a layer 22 disposed on the upper surface of sidewall oxide layers 18. Since the poly members 14 were approximately 6000 Angstroms in height, the height of the sidewall oxide layers 18 is also approximately 6000 Angstroms in thickness. This results in approximately 4000 Angstroms along the vertical edge of the sidewall oxide layers 18 that is not covered by the titanium layer 20 or the titanium layer 22. By wet etching the sidewall oxide layers 18, the oxide is selectively removed, thus removing both the sidewall oxide portions 18 and the layer 22. This wet etching process does not significantly etch the silicon nitride layer 12. As illustrated in Figure 4, the exposed portion of the silicon nitride is selectively etched by a plasma etch process with the titanium layers 20 functioning as a mask to form trenches 24. The etching process utilizes a fluorine base etch such as SF₆. The trench 24 are approximately 8,000 Angstroms in depth, and it can be seen that the width of the trench is approximately equal to the thickness of the sidewall oxide portions 18 or approximately 3000 Angstroms. The width of the active area between the trenches is approximately 0.8 to 1.1 microns. As illustrated in Figure 5, after formation of the trenches 24, the titanium portions 20 are removed, leaving behind the remaining portions of the silicon nitride layer 12 on either side of the trenches 24 (not shown). The substrate is then subjected to a thermal oxidation step, resulting in the formation of oxide 26 internal to the trenches 24. Thereafter, the remaining portions of the silicon nitride layer 12 are removed and then a layer of strip gate oxide (not shown) is grown over the substrate. The substrate is then subjected to a threshold adjust implant which is utilized to adjust the impurity level at the surface of the substrate for later formation of transistors. This is a conventional process. After the threshold adjust implant is performed, the layer of strip gate oxide is removed and then a layer 28 of gate oxide is grown on the surface of the substrate. This is followed by CVD deposition of a layer 30 of poly followed by thermal oxidation thereof to form a layer of oxide 32 on the upper surface of the poly 30. In order to describe the remaining steps of the process, the cross-sectional diagram illustrated in Figures 1-5 is rotated 90° such that the cross-section is taken between two of the trenches 24 along an active area. As illustrated in Figure 6, the gate oxide layer 28, poly layer 30 and oxide layer 32 are patterned and etched to form longitudinal gate electrodes 34 which are separated from the substrate by a layer of gate oxide 36. The layer of gate oxide 36 is formed from the gate oxide layer 28 in Figure 5. Each of gate electrodes 34 has a capping layer 38 of oxide on the upper surface thereof which is the remaining portion of the oxide layer 32 after the patterning and etching process. After formation of the gate electrodes 34 with the capping layer 38 and the gate oxide layer 36, the substrate is subjected to a light implant which is of a dosage sufficient to form a lightly doped drain (LDD) transistor. This is a conventional process. After performing the light implant, the substrate is covered with a conformal layer of silicon oxide (not shown) and then the oxide layer is anisotropically etched to form sidewall layers 40 on either side of the gate electrode 34. The portion of the light implant under the sidewall oxide layers is represented by a region 42 which is sometimes referred to as a reach-through implant. The substrate is then subjected to a heavy source/drain implant of N-type impurities to a concentration suitable to form highly conductive source/drain regions 44. Each of the source/drain regions 44 is connected to the channel region underlying the gate electrodes 34 by the reach-through implants 42. As illustrated in Figure 7, after formation of the source/drain implants 44, tungsten is selectively deposited onto the substrate by CVD techniques. In the selective deposition technique, tungsten is only deposited on bare silicon. Since the upper surface of each of the gate electrodes 34 has a protective capping layer 38 of oxide disposed thereon, the tungsten will only be deposited on the portion of the substrate lying between adjacent gate electrodes 34 and the associated sidewall oxide layers 40. This results in a layer 46 of tungsten being formed over the surface of the source/drain implants 44. After formation of the tungsten layer 46 between adjacent ones of the gate electrodes 34 over the source/drain implants 44, the substrate is patterned to define isolation trenches 48. The isolation trenches 48 are defined between every other gate electrode along a given cross-sectional line between two adjacent ones of the isolation trenches 24. After defining the isolation trenches 48, the substrate is etched to define the trenches 48 with the edges thereof disposed away from the edges of the sidewall oxide layers 40 by a predetermined distance. This results in a portion 50 of the tungsten layer 46 remaining on either side of each of the trenches 48 and also a portion 52 of the source/drain implant 44. It is a necessary to have this portion 50 remaining to provide a conductive surface. After formation of the trench 48, a field implant is performed on the bottom surface thereof, resulting in the formation of a P-type field implant region 54 at the bottom of the trench 48 slightly higher in concentration than the substrate 10. As illustrated in Figure 8, after formation of the trenches 48 and the field implant 54, a layer 56 of silicon nitride is deposited to a thickness of approximately 30,000 Angstroms. Alternatively, a layer of polyimid, can be deposited. The silicon nitride layer 56 is then patterned to define an opening 58 and an opening 60 on either side of the trench 48 extending from approximately the center of each of the adjacent electrodes 34 and the edge of the trench 48. Tungsten is then selectively deposited in the openings 58 and 60, which openings 58 and 60 expose the portions 50 of the tungsten layer. Tungsten is selectively deposited such that it grows upward from the portion 50 to form a tungsten plug 62 in the opening 60 and a tungsten plug 64 in the opening 58. This deposition is performed by CVD techniques at a low pressure for approximately one to two hours to achieve the thickness of the plugs of approximately 25,000-35,000 Angstroms. Although the portions 50 of tungsten were provided, it is possible to deposit the tungsten directly on the silicon surface of the source/drain regions underlying the portions 50. However, this is slower. As illustrated in Figure 8, after formation of the tungsten plugs 62 and 64, the silicon nitride mask 56 is removed and then a layer of titanium dioxide is deposited by CVD techniques to a thickness of approximately 1,000 Angstroms to form an insulating capacitor oxide layer 66 over the entire substrate and conformally covering the surface of the tungsten plugs 62 and 64 and the surfaces of the trench 48. Titanium dioxide is utilized because it has a much higher dielectric constant but a lower breakdown voltage than comparable silicon dioxide dielectric material. Since a much thicker capacitor oxide layer is provided, this allows a considerable amount of tolerance during manufacturing with a resultant improvement in capacitor oxide integrity. After formation of the capacitor oxide layer 66, a layer of tungsten 68 is deposited over the substrate by CVD techniques to a thickness of approximately 2,000 Angstroms. This layer comprises the upper electrode of the capacitor. It can be seen that the lower electrode of the capacitor, represented by the tungsten plug 62 and the portion 50 and also by the tungsten plug 64 and the portion 50, are connected to the source/drain region on one side of gate electrode 34. The portion of the titanium dioxide layer 66 between the layer 68 and the plug 62 comprises the capacitor dielectric. As illustrated in Figure 10, after formation of the layer 66, it is necessary to form a contact with the source/drain region 44 on the opposite side of the gate electrode 34 from the region 50. This typically comprises the bit-line in a memory array. The contact is formed by first forming a layer 69 of spin-on glass (SOG) to a thickness of approximately 40,000 Angstroms over the substrate. This provides a planar surface. A contact opening 70 is formed through the SOG layer 69 to expose the upper surface of the tungsten layer 68 overlying the source/drain region 44 on the opposite side of the gate electrode 34 from the portion 50. The exposed portion of the tungsten layer 68 and the underlying titanium dioxide layer 66 is then etched to expose the surface of the tungsten layer 46 adjacent to the surface of the source/drain region 44. The tungsten layer 68 is typically etched with a chlorine-based plasma etch whereas the titanium dioxide is etched with an F-based etch. A layer 72 of nitride is then deposited in a conformal manner over the substrate to a thickness of approximately 2,000 Angstroms. As illustrated in Figure 11, after deposition of the layer of nitride 72, the nitride layer 72 is anisotropically etched, removing the portion of the nitride layer 72 on the upper surfaces of the SOG layer 69 and also on the horizontal surface of the tungsten layer 46 overlying the source/drain region 44. A sidewall nitride layer 74 remains on the sidewalls of the contact opening 70. The contact opening 70 is then filled with a selective deposition of tungsten to provide a plug 76. Thereafter, an aluminum interconnect layer 78 is formed which comprises the bit line which is then covered by a layer of oxide 80. To form the aluminum interconnect layer 78, the process described above with respect to Figures 1-4 for forming the titanium layers 20 is utilized. A layer of poly is deposited over the substrate by CVD techniques and then an interconnect pattern is defined therein with longitudinal poly lines. This is followed by deposition of oxide to form a conformal layer. This is then anisotropically etched with a plasma etch to leave a sidewall oxide region on each of the longitudinal poly lines. The poly lines are then etched away leaving behind the sidewall oxide layers. Aluminum is then sputtered onto the substrate resulting in aluminum being disposed on the surface of the SOG layer 69 between the sidewall oxide runs and also being disposed on the upper surface of the sidewall oxide runs. The oxide is then etched removing the oxide and the portion of the aluminum on the upper surface of the oxide. This results in the aluminum runs in the interconnect layer 78 being formed which are perpendicular to the gate electrodes 34. The oxide layer 80 is then deposited on the upper surface. Referring now to Figure 12, there is illustrated an isometric view of the capacitor in a cut-away view illustrating the aluminum interconnect layer 78 without the upper layer of oxide 80. It can be seen that the capacitors are staggered such that every other source/drain region along either the x-axis or the y-axis is configured to form a bit-line connection. It can also be seen that the plugs 62 and 64 forming the lower plates of the capacitors are formed in a three-dimensional manner such that there is one upper surface and four essentially vertical surfaces. Therefore, when the titanium dioxide layer 66 is deposited, it is deposited on all exposed surfaces followed by deposition of the upper plate of the capacitor as layer 68. Layer 68 forms the upper plate of all of the capacitors in the array in a continuous sheet, which sheet covers the upper surface and all four exposed substantially vertical surfaces of the titanium dioxide layer 66. This results in a significant increase in the area of the capacitor without substantially increasing the overall area of the cell. This is due to the fact that the capacitor contacts only a portion of one of the source/drain regions 44 and extends upward from the substrate and overlaps the gate electrode. Referring now to Figure 13 there is illustrated a top view of the structure of Figure 12 illustrating six transistors and their associated capacitors. In the top view, it can be seen that the space in between the aluminum lines in the interconnect layer 78 are minimized due to utilizing the above-described process and that each of the cells occupies only a minimal space. Since the capacitor extends upward from the substrate, the conventional "dog bone" configuration need not be utilized. Rather, each cell is essentially a rectangular configuration with the isolation between the cells provided by both the isolation trenches 24 and the isolation trenches 48. The isolation trenches 24 provide isolation along one axis whereas the isolation trenches 48 provide isolation along the other axis.

Claims: A method for forming a memory cell for a dynamic random access memory, comprising: providing a semiconductor substrate (10); forming an MOS transistor on one surface of the semiconductor substrate having a gate electrode (34) separated from the surface of the substrate by a layer of gate oxide (36) and source/drain regions (44,52) on either side of the gate electrode; forming a layer of insulating material (38) over the exposed surfaces of the gate electrode (34); forming a layer of tungsten (46,50) over the source/drain regions (44,52); forming a layer (56) of masking material over the transistor; patterning the masking layer to define an opening (58,60) over at least a portion of one of the source/drain regions (52) to expose the tungsten layer (50) on the surface thereof; depositing tungsten (62,64) in the opening (58,60) such that the tungsten builds up from the exposed surface of the tungsten layer on the surface of the one source/drain region and extending upward through the opening (58,60) to form a plug having an upper surface and at least two side surfaces, which plug comprises the lower plate of a memory cell storage capacitor; removing the masking layer (56); depositing a conformal layer of insulating material (66) over the plug and the transistor; depositing a conformal layer (68) of conductive material over the conformal layer of insulating material, the portion of the conformal layer of conductive material overlying the plug comprising the upper electrode of the capacitor; forming a planarized layer (69) of insulating material over the substrate; forming an opening (70) through the planarized layer of insulating material, the conformal conductive layer and the conformal layer of insulating material to expose at least a portion of the upper surface of the tungsten layer over the other of the source/drain regions; forming a sidewall insulating layer (72) on the sidewalls of the opening in the planarized layer of insulating material to insulate the portion of the conformal conductive layer proximate to the opening; depositing tungsten (76) in the opening such that it is formed upward from the surface of the exposed portion of the tungsten layer overlying the other of the source/drain regions; and forming a conductive pattern (78) on the upper surface of the planarized layer of insulating material. The method of claim 1 wherein the step of forming the opening (58,60) in the masking layer comprises forming the opening such that it overlaps a portion of the gate electrode (34). The method of claim 1 or 2 wherein the conformal layer (66) of insulating material comprises titanium dioxide. A method for forming memory cells in a dynamic random access memory array, comprising: providing a semiconductor substrate (10); forming a plurality of longitudinal gate electrodes (34) on the surface of a substrate and separated from the surface of the substrate by a layer of gate oxide (36) said longitudinal gate electrodes being transversely evenly spaced; forming source/drain regions (44) between the longitudinal gate electrodes; forming isolation trenches (48) in alternating ones of the source/drain regions, a portion of the source/drain region (52) in which each of the isolation trenches is formed remaining on either side of the isolation trench; forming a masking layer (56) over the transistors and the isolation trenches; forming openings (58,60) in the masking layer to expose at least a portion of one of the portions of the source/drain regions (52) adjacent to the isolation trenches; depositing a layer of conductive material (62,64) in the openings and extending upward from the remaining portion of the source/drain regions adjacent each of the isolation trenches to the surface of the masking layer to form a plug in each of the openings (58,60) that comprises the lower plate of a memory cell storage capacitor; removing the masking layer (56); forming a conformal first layer of insulating material (66) over the plugs, the transistors and the isolation trenches; forming a conformal layer (68) of conductive material over the conformal layer of insulating material; forming a planarized layer (69) of insulating material over the conformal layer of conductive material; forming a plurality of openings (70) through the planarized layer of insulating material, the conformal layer of conductive material and the conformal layer of insulating material to expose a portion of each of the other of the source/drain regions on the opposite side of the gate electrodes from the isolation trenches; forming a sidewall insulating layer (72) on the sidewalls of the opening in the planarized layer of insulating material to insulate the portion of the conformal conductive layer proximate to the opening; forming a contact (76) in each of the openings to the exposed portions of the other of the source/drain regions; and forming an interconnect pattern (78) on the upper surface of the planarized layer of insulating material between the contacts and peripheral circuitry on the substrate. A method according to claim 4 and further comprising forming a field implant (54) in the bottom of the isolation trenches prior to forming the masking layer. A method according to claims 4 or 5 and further comprising forming a layer of -tungsten (46,50) over the source/drain regions in which the trenches are formed after formation of the source/drain regions (44,52) and wherein the conductor material of the plug (62,64) is tungsten that is formed by depositing tungsten upward from a portion of the tungsten layer remaining over the source/drain regions (52) adjacent to the isolation trenches. A method according to any one of claims 4-6 and further comprising forming a layer (38) of insulating material over each of the gate electrodes prior to forming the masking layer and wherein each of the openings formed in the masking layer overlap each of the associated gate electrodes. A method according to any one of claims 4-7 wherein the first layer of insulating material (66) is titanium dioxide.

Inventors: TURNER TIMOTHY E, TURNER, TIMOTHY E.
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS, INC. (A DELAWARE CORP.)
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L27