Low bias, high slew rate operational amplifier

Abstract: A bias current source for the output stage (18) of an operational amplifier (10) is controllable. The bias current generator (20) senses the voltage differential on the differential operational amplifier inputs. When an input differential voltage is sensed which generates a rising output signal, additional bias current is provided to the output stage (18). When the output voltage is constant or falling, the bias current to the output stage is decreased.

Description: The present invention relates generally to electronic circuits, and more particularly to operational amplifiers. Operational amplifiers are quite commonly used in electronic circuit design. The circuits considered herein to be operational amplifiers generally are monolithic integrated circuits which implement a high gain amplifier having differential inputs. Variations are sometimes implemented, such as single input operational amplifiers having a second input tied internally to ground. Operational amplifiers are available in a number of different designs which have been optimized for particular uses. Operational amplifiers emphasizing features such as high or low power, fast response time, large bandwidth, or general purpose use, are available. One useful design for an operational amplifier circuit is one that provides a low power drain combined with a high slew rate and good precision. The high slew rate would preferably be greater than approximately 40 V/microsecond, and provide for a minimum amount of overshoot during the settling time. Stability requirements for such a fast operational amplifier imply that a large phase margin, preferably greater than 60°, and large bandwidth be provided. In order to provide a good phase margin, it is preferable to avoid the use of Darlington transistor pairs in the output stage. A simple output stage is therefore preferred in fast operational amplifiers, but the constant current needed to bias such a simple output stage is relatively high. The bias current must be high enough so that the operational amplifier performs properly in the worst case, which occurs when high output current are being sourced and a rising edge occurs. The relatively high bias currents needed to properly bias the output stage against this worst case are inconsistent with the need for a low power operational amplifier. It'would therefore be desirable to provide an operational amplifier which combines a high slew rate with low bias power requirements. Bias-control arrangements in the aforementioned differential amplifiers with Darlington paired output stages, in which one input is tied to ground, are known, especially in the field of audio amplifiers. For example US-A-4077013 discloses an audio amplifier having an input differential stage and a signal sensing circuit for sensing the signal applied to one or other of the inputs. Under quiescient conditions the Darlington output arrangement operates in Class B but when a signal is sensed at the input of concern the bias to the output stage is switched on and increased to provide Class AB operation, eliminating excessive current dissipation in the o/p stages and preventing distortion. According to the present invention there is provided an operational amplifier, comprising: a differential amplifier input stage having a first transistor coupled to an inverting input for receiving a first signal and a second transistor coupled to a non-inverting input for receiving a second signal, an output amplifier stage for generating an output signal, signal providing means connected to said input stage and to said output amplifier stage for providing a signal to said output amplfier stage which is proportional to the difference between said first and second signals applied to the inverting and non-inverting inputs respectively, and a bias current generator for said output amplifier stage connected to said input stage and said output amplifier stage which generator comprises two complementary sensing transistors connected in series, one of said sensing transistors being coupled to said first transistor and the other sensing transistor being coupled to said second transistor to receive signals therefrom, whereby said bias current generator generates a bias current which is a function of the difference between said first and second signals. Therefore, as disclosed, a bias current source for the output stage of an operational amplifier is controllable. The bias current generator senses the voltage differential on the differential operational amplifier inputs. When an input differential voltage is sensed which generates an output signal changing in a selected direction, additional bias current is provided to the output stage. When the output voltage is constant or changing in the other direction, the bias current to the output stage is decreased. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figure 1 is a schematic diagram of an operational amplifier according to the present invention; and Figure 2 is a timing diagram illustrating selected voltages and currents during operation of the circuit of Figure 1. The operational amplifier described below provides a high slew rate amplifier with a simple output stage. In order to minimize the average bias current drain, bias current to the output stage is kept low. It is increased as needed only when operating conditions of the amplifier require a high output stage bias current. As is known in the art, a rising output voltage requires a higher bias current, and the amplifier described below increases the bias current at the time that the output signal is rising. As is also known in the art, the capacitive feedback loop used in operational amplifiers causes them to act as integrators. It is desirable for the output stage bias circuit to predict those times at which higher bias current will be needed. Thus, the bias circuit senses the input differential voltage, which is the derivative of the output voltage. Since the bias current is controlled by the derivative of the output, rapid positive changes in the output voltage are accompanied by increased bias current. Regardless of its actual value, if the output voltage is not changing, the output stage bias current remains constant at a low value. Referring to Figure 1 , an operational amplifier 10 has a differential input stage 12 . The differential input stage 12 is driven by a constant current source 14 . The output of the differential input stage 12 drives a high gain amplifier with feedback 16 . The high gain amplifier 16 in turn drives an output stage 18 . Bias current for the output stage 18 is provided by an output stage bias current generator 20 . The differential input stage 12 includes matching transistors Q1 and Q2 which have base inputs connected to the inverting and noninverting operational amplifier inputs respectively. The collector and base of transistor Q3 are connected to the collector of Q1 , and the emitter of Q3 is connected to the emitter of transistor Q4 . The base and collector of Q4 are connected to the base and collector of Q5 . The base of transistor Q6 is connected to the base of transistor Q5 . Transistors Q5 and Q6 form a current mirror as known in the art. Current limiting resistors R1 and R2 are connected to the emitters of transistors Q1 and Q2 respectively. Resistor R3 is connected to the collectors of transistors Q2 and Q6 . Resistors R4 and R5 are connected between the negative voltage supply V ee and the emitters of transistors Q5 and Q6 , respectively. The output stage bias current generator 20 includes transistors Q7 and Q8 . The base electrodes of transistors Q7 and Q8 are connected to the collectors of transistors Q2 and Q1 respectively. Resistor R6 operates to limit current through transistors Q7 and Q8 . Transistors Q9 and Q10 form a current mirror, with the current through Q10 used to supply bias current to the output stage 18 . The output stage 18 includes transistors Q11 and Q12 connected to function as diodes. Complementary transistors Q13 and Q14 drive the output voltage V out . The signal used to drive the output stage 18 is provided by transistor Q15 . Capacitor C is connected so as to provide feedback to Q15 , and is connected between the base of Q15 and the common point between transistors Q11 and Q12 . The current through capacitor C is a function of the derivative of the voltage signal across it. It is this property which, when used in a feedback loop with transistor Q15 , causes the operational amplifier 10 generally to function as an integrater. The constant current source 14 contains transistors Q16 and Q17 connected so as to form a current mirror. Resistors R7 and R8 have the same value so that the current mirror is balanced. The current through transistor Q16 is constant so long as the supply voltages V cc and V ee do not vary. This means that the current through Q17 , provided to the differential input stage 12 , is also constant. Operation of the circuit of Figure 1 will now be described. The different operating conditions to be described are those which occur during a falling edge of the output signal, a rising output signal, and during a quiescent (steady) state. During a falling output edge, transistor Q2 is turned on, while Q1 is off. Since transistor Q1 is off, transistors Q7 , Q8 , Q9 , and Q10 are also off. This means that no current I bias is supplied to the output stage 18 during a falling output edge. The slew rate of the operational amplifier is determined by the constant current in Q17 flowing through Q2 , R3 , and capacitor C . This is the same situation which occurs in a standard operational amplifier. As is known in the art, the falling edge slew rate for operational amplifiers is good because no bias current I bias is required. When an output rising edge occurs, transistor Q2 is off, while Q1 is on. The constant current supplied by Q17 flows through Q1 , Q3 , Q4 , Q5 , and R4 . This same current is mirrored in Q6 and R5 . The current which flows through Q6 and R5 is supplied from the capacitor C . Also in this situation, transistors Q7 and Q8 are turned on, causing current to flow through Q9 . This current is mirrored in transistor Q10 . The current through Q10 , I bias , will flow into the capacitor C and through transistor Q15 . This ensures that transistor Q15 always remains on. With the relatively large value of I bias supplied through transistor Q10 under these conditions, the operational amplifier works in substantially the same manner as a standard operational amplifier which has a large, constant bias current. The difference is that Q10 does not drive a large bias current unless the output is rising. In the quiescent state, the current through Q17 splits equally between transistors Q1 and Q2 . The currents through transistors Q1 and Q2 also flow through the transistors connected directly or indirectly to their respective collector terminals. Resistors R4 and R5 help to get a lower input offset voltage. It is preferable for all of the transistors Q1-Q10 , and Q15 , to have the same gain and emitter area so that the currents which flow through them match. Under steady state conditions, summing the loop voltages in Figure 1 provides the following equation: V be3 +V be4 +V be5 +I c1 R4=V be8 +V be7 +I c2 R3+V be15 The summation of the base-emitter voltages for transistors Q3 and Q5 must match those for Q8 and Q15 . Also, V be4 matches V be7 , and R4 matches R3 . Since the transistors are the same size, the currents though them match, so that, for example, the collector currents through transistors Q3 , Q8 , and Q15 are the same. If the collector current through transistor 15 tries to change, the base emitter voltage for Q15 also changes. The various voltages and currents in the loops mentioned above, by means of a feedback loop external to the operational amplifier, will bring the collector current for Q15 back to its proper value. Referring to Figure 2 , the relationship between the changes in the output voltage V out and I bias are shown. Figure 2a shows changes in the voltage V out with respect to time, and Figure 2b shows the corresponding changes in I bias . As described above, when V out is changing with a positive going edge, Q10 turns on and increases I bias . During a falling edge, Q10 is turned off and I bias falls. Under steady state conditions, I bias is constant at a low value. It can be seen from Figure 2 that the value of I bias is proportional to the slope of the output voltage curve. This occurs because the value of I bias is controlled by the voltage differential across the inputs, which is proportional to the derivative of the output voltage. Various modifications can be made to the circuit described as will be apparent to those skilled in the art. For example, an MOS operational amplifier can be fabricated using circuitry analogous to that described herein. Implementation of equivalent MOS circuits given a bipolar circuit is well within the skill of those skilled in the art.

Claims: An operational amplifier, comprising: a differential amplifier input stage (12) having a first transistor (Q1) coupled to an inverting input for receiving a first signal and a second transistor (Q2) coupled to a non-inverting input for receiving a second signal; an output amplifier stage (18) for generating an output signal; signal providing means (16) connected to said input stage (12) and to said output amplifier stage (18) for providing a signal to said output amplfier stage (18) which is proportional to the difference between said first and second signals applied to the inverting and non-inverting inputs respectively; and a bias current generator (20) for said output amplifier stage connected to said input stage (12) and said output amplifier stage (18) which generator comprises two complementary sensing transistors (Q7,Q8) connected in series, one of said sensing transistors (Q8) being coupled to said first transistor (Q1) and the other sensing transistor (Q7) being coupled to said second transistor (Q2) to receive signals therefrom, whereby said bias current generator (20) generates a bias current which is a function of the difference between said first and second signals. An operational amplifier according to claim 1, wherein said bias current generator further comprises: a first current mirror transistor (Q9) connected in series with said sensing transistors; and a second current mirror transistor (Q10) connected to said first current mirror transistor (Q9) to said output stage (18), whereby current flowing through said second current mirror transistor (Q10) flows into said output stage to provide a bias current thereto, and wherein the current flowing through said second current mirror transistor (Q10) has the same magnitude as a current flowing through said first current mirror transistor (Q9). An operational amplifier according to claim 1 or 2, wherein said signal providing means comprises: an amplifying transistor (Q15) connected to said input amplifier stage for amplifying a difference signal therefrom; and a capacitor (C) connected to said amplifying transistor for providing a feedback path thereto. An operational amplifier according to any preceding claim, further comprising: an input stage constant current source (14) connected to said input stage, wherein current from said constant current source is directed through the first and second transistors according to the relative values of the first and second signals applied to the inverting and non-inverting inputs. An operational amplifier according to claim 4, wherein said transistors (Q1,Q2,Q7,Q8,Q9,Q10,Q15) are bipolar junction transistors. An operational amplifier according to claim 5, wherein said transistors (Q1,Q2,Q7,Q8,Q9,Q10,Q15) have the same gain and emitter area. An operational amplifier according to claim 1, wherein said signal providing means (Q16) includes capacitive feedback, and wherein said output stage bias generator senses the instantaneous value of an input signal to said input stage and generates the bias signal to be proportional thereto.

Inventors: POLETTO VANNI, POLETTO, VANNI
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS, INC.
Application year: 1990
Main classification: H03F1
IPC codes: H03F1, H03F3