Decoder

Abstract: A decoder has a plurality of outputs (R o -R N ) each associated with a particular output value and is arranged to add together two binary numbers (A, B) and to select one of said outputs in dependence on the result of said sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together said logic circuits being arranged to provide, for each output value, a respective result in dependence on the logic states of said bits and on the logic states of respective bits of binary numbers representing the particular output value of the decoder; and logic means for determining when a predetermined condition is satisfied by all the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected. In the preferred embodiment, for adding together two n bit numbers, there are n+l logic circuits (L), each arranged to receive the ith and i-lth bits (Ai, Ai-l, Bi, Bi-l) of first and second n bit numbers, and each arranged to provide an output in dependence on the logic states of said bits and on the logic states of the ith and i-lth bits (Qi, Qi-l) of respective binary numbers which are the ones complement of binary numbers R o ...R N representing each respective output value of the decoder in accordance with the following expression: Ai ⊕ Bi ⊕ Qi ⊕ (Ai-l-Bi-l + Qi-l. (Ai-l + Bi-l)). The predetermined condition is then satisfied when the above expression has a logic value of ONE. A plurality of AND gates are associated respectively with the outputs of the decoder and are each arranged to receive the outputs of the n+l logic circuits for each output value of the decoder. The decoder performs addition and decoding in one step.

Description: This invention relates to a decoder. There are several circumstances in the digital manipulation of numbers where it is required to perform an addition of two binary numbers and then decode the result. The term decode is used herein to denote the selection of a particular preset output value in dependence on the result of the addition. For example, the digital execution of long division involves a cycle of subtracting from a remainder REM a value M which is a whole multiple of the divisor D. In terms of hardware, the subtraction is performed in an adder by inverting the value M and adding the inverted value -M to the remainder REM. The result X of the addition is passed to a look up table which decodes the result by comparing it with each of a plurality of integers (1-100) to determine a "match". The new value M stored against the matched value is then output to perform the next addition step. The result X becomes the next remainder REM for the subsequent cycle. This procedure is shown diagrammatically in Figure 1. In another example, a computer program frequently requires the loading of an instruction to a particular register which is identified in relation to a base register by an (x + r)-type instruction in the program, where r is the location of the base register and x the number to be added thereto to determine the location of the particular register. Firstly the addition (x + r) must be performed and then the result of the addition must be supplied to a look up table to determine the output value associated with the result of the addition. Reference is made to EP 191452 which relates to a technique for checking the sum or difference of two values by comparison with a third value in a binary arrangement. To avoid the need to compare all of the bits of the resulting sum or difference with the third value, only some of the bits are compared. If these bits do not meet the desired equality, no further comparison is carried out. Thus, comparisons of this nature can be speeded up. This document does not address the problems which arise in executing a decoding operation. The execution of an addition followed by a decoding operation is costly in terms of time. It is an object of the present invention to increase the speed at which such operations can be executed and thereby improve the efficiency of processes using these steps. According to the present invention there is provided a decoder for generating an output signal representative of a sum of two n-bit binary numbers, the decoder comprising: first and second input terminals for receiving respectively first and second binary n-bit numbers; a plurality of output terminals each representing a respective value R ranging from R 0 to R n ; and logic circuitry for providing an output signal to one of said output terminals to select an appropriate one of said values R, said logic circuitry comprising: a plurality of logic circuits, each corresponding to an index value i, where i ranges from 1 to n, each of the logic circuits being coupled to receive the ith and (i-1)th bits of said first and second n-bit numbers, and each arranged to provide an output signal based on the logic states of said bits and on the logic states of the ith and (i-1)th bits of respective binary numbers Q which are the one's complement of binary numbers R representing each respective output value of the decoder in accordance with the following expression: Ri=Ai ⊕ Bi ⊕ Qi ⊕ ((Ai-1.Bi-1) + Qi-1. (Ai-1 + Bi-1)) whereby a set of output signals is produced associated with each output value of the decoder; and logic means (G) coupled to said logic circuits for identifying when that expression has a logic value of ONE for all the output signals in a set, whereby the output value associated with that set is selected. preferably said logic means comprises a plurality of AND gates associated respectively with the outputs of the decoder and each arranged to receive the outputs of the n+l logic circuits for each output value of the decoder. The invention also provides a method of implementing a combined add/decode operation. In an embodiment which is particularly simple to construct each logic circuit is arranged to produce four outputs for each of the four possible alternative sets of Qi and Qi-l by implementing for each of n bits of the binary numbers to be added the following expressions; where Qi = 0, Qi-l = 0 is written Q(0,0) Q(0,0) Ai ⊕ Bi ⊕ (Ai-1.Bi-1) Q(0,1) Ai ⊕ Bi ⊕ (Ai-1+Bi-1) Q(1,0) NOT Ai ⊕ Bi ⊕ (Ai-1.Bi-1) Q(1,1) NOT Ai ⊕ Bi ⊕ (Ai-1+Bi-1) The appropriate Q values are fed into the AND gates associated with each output value in dependence on the output value. For this embodiment, each logic circuit can comprise an NAND gate having first and second inputs for receiving the (i-)th bit (Ai-l,Bi-l) of each number; a NOR gate having first and second inputs for receiving the ith bit (Ai,Bi) of each number; a first exclusive OR gate having a first input coupled to the output of the NOR gate and a second input coupled to the output of a second exclusive OR gate whose inputs are the ith bit (Ai, Bi) of each number; a third exclusive OR gate having a first input coupled to the output of the NAND gate and a second input coupled to the output of the second exclusive OR gate; a first inverter coupled to the output of the first exclusive OR gate; a second inverter coupled to the output of the third exclusive OR gate, the output of the first and second inverter providing directly two of said four outputs the other two of said four outputs being provided by inverting said directly provided two outputs. This implementation has the significant advantage of utilising only a few simple logic gates and enabling a combined add/decode operation to be carried out quickly. It will be appreciated that the invention can be used in circumstances where more than two binary numbers are to be added together since circuits are available which can take three or four binary numbers and reduce them to two binary numbers which when added form the sum of the original three or four binary numbers. Such circuits do not form part of the present invention but are mentioned for the sake of completeness. For a better understanding of the present invention and to show how the same may be carried into effect reference will now be made by way of example to Figures 2 to 4 of the accompanying drawings, in which:- Figure 1 is a block diagram of a prior art circuit for effecting long division; Figure 2 is a block diagram illustrating the principles of the present invention; Figure 3 is a block diagram of one embodiment of the present invention; and Figure 4 is a circuit diagram of one embodiment of the present invention. Suppose that two binary numbers A and B (in twos complement), each having n bits are to be added and the result decoded to select a particular output value R. The invention provides a single circuit 10 to effect this as shown in block diagram in Figure 2. That is, a decoder receives two separate binary numbers A and B and selects an output value from its outputs Ro-RN depending on the result of adding A and B. For the correct output value of the decoder Rx for two particular numbers A, B A plus B = Rx hence A plus B minus Rx =0 The output values R from Ro to RN are preset so for each case Rx is a fixed constant. A normal decoder has N = 2 n outputs for a binary number having n bits. The present decoder can have any number N≤2 n with each output value Rx being different, increasing from 0 to N-1. Consider the ones complement Q of R. That is Q is a binary number corresponding to R but with all the bits inverted. In logic terms Q = -(R plus 1) hence A plus B plus Q = -1 In twos complement binary notation, -1 is written 11111... . Consider the sum Si of each bit i from 0 to n-1 of the left hand side of equation (4). Herein the term + is logic OR, the term . is logic AND, and the term ⊕ is logic EXCLUSIVE OR. Si = Ai ⊕ Bi ⊕ Qi The carry for each bit is Ci = Ai . Bi + Qi . (Ai+Bi) To obtain the final result a further addition is required S plus C * 2 where C*2 denotes a shift to the left, i.e. Si and Ci-1 have the same significance. When the two binary numbers S and 2*C are added together, the result, X is formed from X i = S i ⊕ C i-1 ⊕ Y i-1 where Y is the carry in from respective stages: Y i = S i .C i-1 + Y i-1 .(S i + C i-1 ) If we assume that for Y i-1 = O, and X i = 1, then S i ⊕ C i-1 = 1 This implies that either S i = 0 or C i-1 = 0 which means that S i .C i-1 = 0 and so Y i = 0. We define Y -1 = 0, so by induction, Y i = 0 for every value of i. This shows that the carry values Y i are all zero, and so only equation (10) needs to be evaluated, with Y i-1 = 0. Substituting values for Si and Ci-l from equations (5) and (6) into equation (10) yields: Ai ⊕ Bi ⊕ Qi ⊕ ((Ai-1.Bi-1+Qi-1.(Ai-1+ Bi-1)) = 1. Referring to Figure 3, this equation can be implemented in hardware by providing for each output Rx of the decoder a plurality of logic circuits L (five are shown for each of two outputs in Figure 3 - generally there are n+l for adding two n bit binary numbers), each receiving the inputs Ai, Bi, Qi, Ai-1, Bi-1 and Qi-1 and arranged to execute the simple logic functions expressed in the left hand side of equation (10). The outputs of the plurality of logic circuits associated with each output of the decoder are supplied to an AND gate G. When the output of any particular AND gate is HIGH, that signifies that equation (1) is true for that output. In Figure 3, the notation Qxi indicates the ith bit of the ones complement Qx of the output Rx. For example Q11 is the second bit of the ones complement of the second output R 1 . As can be seen from Figure 3, in each column the same logic values are fed to each of N logic circuits and the same logic manipulations executed thereupon. The only change moving from row to row down a common column is the logic value of Qxi. However, this is preset for each decoder, normally in numerical progression, for example (with the numbers in brackets being binary representations) R o =0 (0000, Qo = 1111); R 1 =1 (0001, Q 1 =1110); R 2 =2 (0011, Q 2 =1100) etc. up to R N 15 for a four bit number. Hence the values for Qxi are known prior to the design of any particular decoder using equation (10) and can be used to produce logic circuits for determining the left hand side of equation (10) in four specific cases of Qi, Qi-1 (where Qi=0, Qi-1=0 is written as Q(0,0) etc.). Q(0,0) Ai ⊕ Bi ⊕ (Ai-1.Bi-1) Q(0,1) Ai ⊕ Bi ⊕ (Ai-1+Bi-1) Q(1,0) NOT Ai ⊕ Bi ⊕ (Ai-1.Bi-1) Q(1,1) NOT Ai ⊕ Bi ⊕ (Ai-1+Bi-1) The implementation of this circuitry is shown partially in Figure 4, where eight outputs are shown for decoding the sum of two four bit words. The circuit of Figure 4 shows circuitry for implementing a decode operation for N=2 n outputs, that is where the number of bits in the binary sum of the binary numbers A+B is n. There are three similar logic circuits for inputs A1,B1; A2,B2; and A3,B3 and a simplified logic circuit for inputs A0,B0. The logic circuit for the inputs A2,B2; A3,B3 is shown outlined in a dotted line in Figure 4. The logic circuit comprises an exclusive OR gate 2' for receiving inputs A2,B2. The logic circuit also comprises a NOR gate 6 and a NAND gate 4 both for receiving inputs A1,B1. An exclusive OR gate 10 receives the output of the NAND gate 4 and the exclusive OR gate 2', while an exclusive OR gate 8 receives the output of the NOR gate 6 and the exclusive OR gate 2'. The outputs of these exclusive OR gates 8,10 are used directly and inverted to form the Q terms Q(0,0),Q(0,1),Q(1,0),Q(1,1) for the case i=3, i-1=2. These are then fed in different combinations (according to the appropriate output value) to output AND gates G.

Claims: A decoder for generating an output signal representative of a sum of two n-bit binary numbers, the decoder comprising: first and second input terminals for receiving respectively first and second binary n-bit numbers (A,B); a plurality of output terminals each representing a respective value R ranging from R 0 to R n ; and logic circuitry (2,4,6) for providing an output signal to one of said output terminals to select an appropriate one of said values R, said logic circuitry comprising: a plurality of logic circuits (L), each corresponding to an index value i, where i ranges from l to n, each of the logic circuits being coupled to receive the ith and (i-1)th bits (Ai,Ai-l ;Bi,Bi-1) of said first and second n-bit numbers, and each arranged to provide an output signal based on the logic states of said bits and on the logic states of the ith and (i-1)th bits (Qi,Qi-1) of respective binary numbers Q which are the one's complement of binary numbers R representing each respective output value of the decoder in accordance with the following expression: Ri=Ai ⊕ Bi ⊕ Qi ⊕ ((Ai-1.Bi-1) + Qi-1. (Ai-1 + Bi-1)) whereby a set of output signals is produced associated with each output value of the decoder; and logic means (G) coupled to said logic circuits for identifying when that expression has a logic value of ONE for all the output signals in a set, whereby the output value associated with that set is selected. A decoder as claimed in claim 1, wherein said logic means comprises a plurality of AND gates associated respectively with the outputs of the decoder and each arranged to receive the set of output signals of the logic circuits for each output value of the decoder. A decoder as claimed in claim 1 or 2, wherein each logic circuit comprises logic gates arranged to produce four outputs for each of the four possible alternative sets of Qi and Qi-1 by implementing the following expressions; where Qi = 0, Qi-1 = 0 is written Q(0,0) Q(0,0) Ai ⊕ Bi ⊕ (Ai-1.Bi-1) Q(0,1) Ai ⊕ Bi ⊕ (Ai-1+Bi-1) Q(1,0) NOT Ai ⊕ Bi ⊕ (Ai-1.Bi-1) Q(1,1) NOT Ai ⊕ Bi ⊕ (Ai-1+Bi-1) A decoder as claimed in claim 1, wherein each of said logic circuits comprises: a NAND gate (4) having first and second inputs for receiving the (i-1)th bit (Ai-1,Bi-1) of each of the two binary numbers (A,B); a NOR gate (6) having first and second inputs for receiving the (i-1)th bit (Ai-1,Bi-1) of each binary number; first and second exclusive OR gates (8,2'), the first exclusive OR gate (8) having a first input coupled to the output of the NOR gate (6) and a second input coupled to the output of the second exclusive OR gate (2'), the inputs to which include the ith bit (Ai,Bi) of each of said n-bit binary numbers; and a third exclusive OR gate (10) having a first input coupled to the output of the NAND gate (4) and a second input coupled to the output of the second exclusive OR gate (2'), and a first inverter coupled to the output of the first exclusive OR gate (8), a second inverter coupled to the output of the third exclusive OR gate (10), the outputs of the first and second inverters providing respectively two output signals of the logic circuit and being inverted to provide two inverted output signals of the logic circuit so as to provide a set of output signals associated with each possible output value of the decoder; and wherein the logic means (2) comprises a plurality of AND gates (G) associated respectively with the outputs of the decoder and each arranged to receive one of said sets of output signals associated with each output value of the decoder. A method of decoding for generating an output signal representative of a sum of two n-bit binary numbers, the method comprising: supplying first and second binary n-bit numbers (A,B) to a decoder; supplying the ith and (i-1)th bits (Ai,Ai-1;Bi,Bi-1) of said first and second n-bit numbers to each of a plurality of logic circuits; at each logic circuit, providing an output signal based on the logic states of said bits and on the logic states of the ith and (i-1)th bits (Qi,Qi-1) of respective binary numbers Q which are the one's complement of binary numbers R, wherein each binary number R represents a respective output value of the decoder; wherein the provision of said output signal is carried out in accordance with the following expression at each logic circuit: Ri=Ai ⊕ Bi ⊕ Qi ⊕ ((Ai-1.Bi-1) + Qi-1. (Ai-1 + Bi-1)) whereby a set of output signals is produced associated with each output value of the decoder; and identifying when that expression has a logic value of one for all the output signals in a set, whereby the output value associated with that set is selected.

Inventors: FORSYTH RICHARD MATTHEW, FORSYTH, RICHARD MATTHEW
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS LIMITED
Application year: 1990
Main classification: G06F1
IPC codes: G06F1, G06F7, H03M7