Circuit for detecting pulses, and video recorder comprising the circuit

Abstract: A circuit for detecting pulses in an electric input signal, which pulses are superposed on a specific reference level (U ref ), has an input terminal (1) for receiving the electric input signal, at least a first and a second comparator device (2, 3), switching means (S₁), an output terminal (8) and control signal generator means (13)″. The control signal generator means supply a control signal to the switching means (S1) to control the position of the switching means. The input terminal (1) is coupled to a first input of the comparator devices (2, 3), whose outputs (6 and 7 respectively) are coupled to a terminal ( c and a respectively) of the switching means (S₁). The output terminal ( b ) of the switching means is coupled to the output terminal (8). The first comparator device (2) transfers only pulses whose relative amplitude in relation to the reference level exceeds a first value (U D1 ). The second comparator device (3) transfers only pulses whose relative amplitude in relation to the reference level exceeds a second value (U D2 ). When input terminal receives N1 consecutive pulses whose amplitude relative to the reference level exceeds a specific (third) value (U D3 ) the switching means (S₁) have been/are set to position c-b in such a manner that the first comparator (2) is coupled to the input terminal (8). When subsequently N2 consecutive pulsews are counted whose relative amplitude lies between a fourth and a fifth value (U D4 and U D5 respectively), such that U D5 < U D4 < U D3 , the switching means (S₁) have been/are set to position a-b in such a manner that the second comparator device (3) is coupled to the output terminal (8). N1 and N2 are integers larger than or equal to 1.

Description: The invention relates to a circuit for detecting pulses in an electric input signal, which pulses are superposed on a specific reference level, the circuit having an input terminal for receiving the electric input signal, the circuit comprising at least a first and a second comparator device, which comparator devices each have a first input coupled to the input terminal, at least a second input, and an output, the second input of each comparator device being coupled to a point of constant potential, the first comparator device being adapted to supply a first electric signal on its output exclusively when the input terminal receives a pulse whose relative amplitude in relation to the reference level exceeds a specific first value, the second comparator device being adapted to supply a second electric signal on its output when the input terminal receives a pulse whose relative amplitude in relation to the reference level exceeds a specific second value, the first value being larger than the second value, the outputs of the first and the second comparator device being coupled respectively to a first input and a second input of switching means, which switching means have an output coupled to an output terminal of the circuit, the circuit further comprising means for generating a control signal on an output, for supplying said control signal to a control signal input of the switching means, the input terminal being coupled to an input of the control signal generator means, and to a videorecorder comprising the circuit. A circuit construction as defined above is known from GB-A-2.120.030 and DE-A-3.030.531 and is used as a demodulator for reproducing a digital signal recorded on a record carrier. The circuit defined above is intended for use in a videorecorder, in particular for reading CTL pulses recorded in a separate track which extends at the edge of and in the longitudinal direction of the magnetic record carrier over this record carrier. These CTL pulses are read in order to achieve that the video heads correctly follow the video tracks which extend obliquely on the magnetic tape. Moreover, these pulses can be read in order to be used in the VISS or VASS option of VHS video recorders (VISS and VASS meaning VHS index/address search system). Reading the CTL pulses sometime presents problems because these pulses may have different amplitudes and pulse widths at different tape speeds. It is an object of the invention to provide pulse-detection circuits which are better capable of correctly detecting pulses whose amplitude and width vary as function of time. The circuit in accordance with the invention is defined in the appended claims. The invention is based on the recognition of the fact that there may be a substantial spread in pulse amplitude for different recorders or different magnetic tapes and for different speeds of transport of the magnetic tape past the read head. Moreover, in the last mentioned case the pulses read are distorted, which distortion manifests itself inter alia in pulse widening in the case of high tape speeds. Therefore, the circuit in accordance with the invention monitors the magnitude of the pulses and on the basis thereof selects a high or a low detection level. The basic idea that it is ascertained whether N1 pulses of a "high level", i.e. of a relative amplitude larger than the third value, are applied. In that the case the high detection level is selected. This means: the first value. Pulses of an amplitude higher than the first value are then detected by the circuit and transferred to the output for further processing of these pulses, and pulses of an amplitude smaller than the first value are not transferred. If N 1 is larger than 1, the N 1 pulses may be N 1 directly succeeding pulses. Another possibility is to check whether N 1 pulses larger than the third value occur in a specific time interval. Yet another possibility is to check whether there are N 1 pulses larger than the third value in cycles of N 1 +x pulses, x being an integer larger than or equal to 1. In the embodiment of the circuit according to claim 2, the N 2 pulses may also be N 2 successive pulses, or N 2 pulse situated within a specific time interval or N 2 pulses within cycles of N 2 +y pulses each, y being an integer larger than or equal to 1. In this embodiment, N2 pulses having a "low level" are then counted, i.e. having a relative amplitude between the fourth and the fifth value, after which a change-over to the low detection level is effected. This means: the second value. Pulses of an amplitude larger than the second value are then transferred by the circuit. Pulses of an amplitude smaller than the second value are not transferred. The third value may be selected to be at least substantially equal to the fourth value. The circuit can be simplified by selecting the first value to be substantially equal to the third value and the second value to be at least substantially to the fifth value. This requires two comparator devices, which can be used both for detecting the pulses and for deriving the control signal. Such a circuit may be characterized further in that the output of the first comparator device is coupled to the input of the first counter and the output of the second comparator device is coupled to the input of the second counter. Moreover, the outputs of the first and the second comparator devices may be coupled, via an AND gate, to the input of the first counter and to a reset input of the second counter, and the output of the second counter may be coupled to a reset input of the first counter. If the circuit should detect pulses which have always one specific polarity relative to the reference level the comparator devices require only one comparator each. A circuit which should detect pulses which may have both a positive and a negative polarity relative to the reference level may be characterized in that the comparator devices each comprise two comparators, each comparator having a first and a second input and an output, in that the first inputs of the comparators are coupled to the input terminal, the second input of the first comparator in the first comparator device is coupled to the second input of the first comparator device, the second input of the second comparator in the first comparator device is coupled to a third input of the first comparator device, the second input of the first comparator in the second comparator device is coupled to the second input of the second comparator device, the second input of the second comparator in the second comparator device is coupled to a third input of the second comparator device, in that the third inputs of the first and the second comparator device are each coupled to a point of constant potential, in that the outputs of the first and the second comparator in each of the comparator devices are coupled to the output of the comparator device via a signal combination element, the first and the second comparator in the first comparator device are adapted to generate a third and a fourth electric signal respectively exclusively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said first value in a positive and a negative sense, respectively, relative to the reference level, and in that the first and the second comparator in the second comparator device are adapted to generate a fifth and a sixth electric signal respectively, when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said second value in a positive sense and in a negative sense, respectively, relative to the reference level. Again the second value may be at least substantially equal to the fifth value. In this case the circuit may be characterized further in that the outputs of the first comparators in the two comparator devices are coupled to a first input of an OR gate via an AND gate, the outputs of the second comparators in the two comparator devices are coupled to a second input of the OR gate via a second AND gate, in that an output of the OR gate is coupled to the input of the first counter and to a reset input of the second counter, in that the outputs of the first and the second comparator in the second comparator device are coupled to an input of the second counter via a second OR gate, and in that an output of the second counter is coupled to a reset input of the first counter. In the embodiment of the circuit according to Claim 13, the third value may be selected to be larger than the fourth value. This introduces a voltage hysteresis in the control signal generator means. Switching back to the low detection level can be achieved by means of a circuit which is characterized in that the second comparator device is further adapted to supply a fifth electric signal when the input terminal receives a pulse whose amplitude relative to the reference level is situated between the fourth and the fifth value, in that after the input terminal has received N 2 pulses whose relative amplitude is situated between the fourth and the fifth value the control signal generator means are adapted to generate a control signal in such a manner that when the input receives a subsequent pulse whose relative amplitude is smaller than the third value the switching means remain in a position in which the second input is coupled to the output. The second embodiment of the circuit according to Claim 13 with voltage hysteresis in the control signal generator means may also be characterized in that N 1 =1, in that the comparator devices each comprise two comparators, each comparator having a first and a second input and an output, in that the first inputs of the comparators are coupled to the input terminal, the second input of the first comparator in the first comparator device is coupled to the second input of the first comparator device, the second input of the second comparator in the first comparator device is coupled to a third input of the first comparator device, the second input of the first comparator in the second comparator device is coupled to the second input of the second comparator device, the second input of the second comparator in the second comparator device is coupled to a third input of the second comparator device, in that the third inputs of the first and the second comparator device are each coupled to a point of constant potential, in that the outputs of the first and the second comparator in the first comparator device are coupled respectively to a first and a second sub-input of the first input of the switching means, the outputs of the first and second comparator in the second comparator device are coupled respectively to a first and a second sub-input of the second input of the switching means,the first and the second comparator in the first comparator device are adapted to generate a sixth and a seventh electric signal exclusively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said first value in a positive or negative sense, respectively, relative to the reference level, and in that the first and the second comparator in the second comparator device are adapted to generate an eighth and a ninth electric signal respectively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said second value in a positive and a negative sense, respectively, relative to the reference level, in that the first and the second comparator devices in the control signal generator means each comprise two comparators, each comparator having at least a first and a second input and an output, in that the first inputs of the comparators are coupled to the input terminal, the second input of the first comparator in the first comparator device is coupled to the second input of the first comparator device, the second input of the second comparator in the first comparator device is coupled to a third input of the first comparator device, the second input of the first comparator in the second comparator device is coupled to the second input of the second comparator device, the second input of the second comparator in the second comparator device is coupled to a third input of the second comparator device, in that the third inputs of the first and the second comparator device are each coupled to a point of constant potential, in that the outputs of the first and the second comparator in each of the comparator devices are coupled, via a signal combination element, to the output of the control signal generator means, the first and the second comparator in the first comparator device are adapted to generate a tenth and an eleventh electric signal respectively exclusively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said third value in a positive and a negative sense, respectively, relative to the reference level, and in that the first and the second comparator in the second comparator device are adapted to generate a twelfth and a thirteenth electric signal respectively when the input terminal receives a pulse whose amplitude, in a positive and a negative sense relative to the reference level respectively, is situated between the third and the fourth value, and in that the signal combination unit is adapted to generate a control signal from the tenth through the thirteenth signal in such a manner that when the input terminal receives a pulse whose relative amplitude exceeds the third value in a positive sense relative to the reference value the switching means have been or are set to a position in which the second sub-input of the first input is coupled to the output, in that when the input terminal receives a pulse whose relative amplitude exceeds the third value in a negative sense relative to the reference value the switching means have been or are set to a position in which the first sub-input of the first input is coupled to the output. In this case the hysteresis effect manifests itself in that after the input terminal has receives a pulse whose relative amplitude in relation to the reference level exceeds the third value in a positive sense relative to said reference level the control signal generator means are adapted to generate a control signal in such a manner that after the input terminal has received a subsequent pulse whose relative amplitude in relation to the reference level exceeds the fourth value in a negative sense relative to said reference level the switching means have been or are set to a position in which the first sub-input of the first input is coupled to the output and in that after the input terminal has received a pulse whose relative amplitude in relation to the reference level exceeds the third value in a negative sense relative to said reference level the control signal generator means are adapted to generate a control signal in such a manner that after the input terminal has received a subsequent pulse whose relative amplitude in relation to the reference level exceeds the fourth value in a positive sense relative to said reference level the switching means have been or are set to a position in which the second sub-input of the first input is coupled to the output. Switching back to the low detection level can then be achieved in that after reception of a positive pulse relative to the reference level the control signal generator means are adapted to generate a control signal such that the switching means have been or are set to a position in which the first sub-input of the second input is coupled to the output, and in that after reception of a negative pulse relative to the reference level the control signal generator means are adapted to generate a control signal such that the switching means have been or are set to a position in which the second sub-input of the second input is coupled to the output. Embodiments of the circuit in accordance with the invention will now be described in more detail, by way of example, with reference to the accompanying drawings. In the drawings Fig. 1 shows an embodiment of the circuit for detecting pulses of a single polarity relative to the reference level, Fig. 1a shows the control signal generator means of the circuit in Fig. 1 in more detail, Fig. 2a shows the electric input signal and Fig. 2b shows the position of the switching means in the circuit shown in Fig. 1, Fig. 3 shows an embodiment of a circuit for detecting pulses of positive and negative polarity relative to the reference level, Fig. 4a shows the electric input signal and Fig. 4b shows the position of the switching means in the circuit shown in Fig. 3, Fig. 5 shows an embodiment of a circuit for detecting pulses of a single polarity relative to the reference level, the control signal generator means exhibiting a voltage hysteresis, Fig. 6 is a Table giving signal values on a number of points in the circuit shown in Fig. 5 and the corresponding positions of the switches in this circuit for a number of amplitude values of the pulses applied to the input terminal, Fig. 7 shows an embodiment of a circuit for detecting pulses of positive and of negative polarity relative to the reference level, the control signal generator means also exhibiting a voltage hysteresis effect, Fig. 8 shows the switch positions of the switches in the circuit shown in Fig. 7 for a number of possible pulse amplitudes applied to the input terminal, Fig. 9 shows the control signal generator means of the circuit shown in Fig. 7 further elaborated, Figs. 10, 11 and 12 show a number of elements for use in the circuit shown in Fig.9, and Fig. 13 shows the circuit in accordance with the invention used in a video recorder. Fig. 1 shows a first embodiment of a circuit having an input terminal 1 coupled to a first inputs (+) of a first and a second comparator device 2 and 3 respectively. The two comparator devices each comprise one comparator. A second input (-) of the first comparator device 2 is coupled to a point 4 of constant potential. A second input (-) of the second comparator device 3 is coupled to a point 5 of constant potential. Outputs 6 and 7 of the comparator device 2 and 3 respectively are coupled to respective inputs c and a of switching means S 1 in the form of a controllable switch. An output b of the switch S 1 is coupled to an output terminal 8 of the circuit. The outputs 6 and 7 are also coupled to inputs of an AND gate 9, which has an output coupled to a count input cl of a counter 10 and to a reset input of a counter 11. Moreover, the output 7 is coupled to a count input cl of the counter 11. An "n=N2" output of the counter 11 is coupled to a reset input of the counter 10 and an "n=N1" output of the counter 10 is coupled to a control signal input 12 of the switch S1. The comparator 2 is adapted to supply a first electric signal (a logic "1" signal) exclusively if the input terminal 1 receives pulses whose relative amplitude in relation to the reference level U ref exceeds a first value. A potential U D1 is how applied to the point 4 of constant potential. The first value is then equal to U D1 -U ref . U ref need not necessarily be zero volts, but may alternatively be a specific non-zero direct voltage. It should be noted here that the word "exclusively" given above, means that the comparator 2 supplies the first electric signal only if the pulse exceeds the first value. The comparator 2 does not supply the first electric signal if the pulse has relative amplitude lower than the first value. The comparator 3 is adapted to supply a second electric signal (a logic "1" signal) if the input terminal 1 receives pulses whose relative amplitude in relation to Uref exceeds a second value. Since the potential U D2 is applied to point 5, the second value will be equal to U D2 -U ref . In this embodiment the third, the fourth and the first value are equal to each other and the second value is equal to the fifth value. In a position of the switch S 1 in which the terminals a and b are coupled to each other the counter N1 counts pulses having a relative amplitude larger than the third value. This means: those pulses which are larger than U D1 , see Fig. 2a. During this time interval, pulses which are detected by the comparator 3 and which consequently have an amplitude larger than U D2 are transferred to the output terminal 8. After N1 successive pulses having an amplitude larger than U D1 have been counted a logic "1" signal appears on the "n=N1" output of the counter 10. Under the influence of this signal, which is applied to the control signal input 12 of the switch S1, the switch S1 is set to the position in which the terminals c and b are coupled to each other, see Fig. 2b. From this instant the pulses which are detected by the comparator 2 and which consequently have an amplitude larger than U D1 are transferred to the output terminal 8. The count of the counter 10 then remains n=N1. How it is assumed that pulses having an amplitude between U D1 and U D2 are applied to the input terminal. The counter 11 can now count because no reset pulses are applied to the reset input of the counter 11 by the AND gate 9. At the instant at which N2 of such pulses have been counted the "n=N2" output of the counter 11 becomes logic "1". As a result of this, a reset signal is applied to the reset input of the counter 10, causing the counter 10 to be reset to "0". The switch S1 is now reset to the position in which the terminals a and b are coupled to each other, see Fig. 2b. The control signal generator means shown in the circuit of Fig. 1 comprises the elements situated within the dashed block 13. It is obvious that the comparators which provide the pulse detection are also used for deriving the control signal which is applied to the control signal input 12 of the switch S1. Fig. 3 shows the circuit of Fig. 1 extended to detect pulses of positive and negative polarity relative to the reference level U ref . Here the first comparator device 2 comprises a first and a second comparator 2.1 and 2.2 respectively and an S-R flip-flop 20. The second comparator device 3′ now comprises a first and a second comparator 3.1 and 3.2 respectively and an S-R flip-flop 21. The input terminal 1 is coupled to the non-inverting inputs (+) of the comparators 2.1 and 3.1 and to the inverting inputs (-) of the comparators 2.2 and 3.2. The inverting inputs (-) of the comparators 2.1 and 3.1 are coupled to a point of constant potential, 4.1 and 5.1 respectively. The non-inverting inputs (+) of the comparators 2.2 and 3.2 are coupled to a point of constant potential, 4.2 and 5.2 respectively. The outputs 6.1 and 6.2 of the comparators 2.1 and 2.2 respectively are coupled to the set input and the reset input respectively of the flip-flop 20. The Q-output of the flip-flop 20 is coupled to the input terminal c of the switch S 1 . The outputs 7.1 and 7.2 of the comparators 3.1 and 3.2 respectively are coupled to the set input and the reset input respectively of the flip-flop 21. The Q-output of the flip-flop 21 is coupled to the input terminal a of the switch S 1 . The outputs 6.1 and 7.1 of the comparators 2.1 and 3.1 respectively are coupled to the inputs of the AND gate 9. The outputs 6.2 and 7.2 of the comparators 2.2 and 3.2 respectively are coupled to inputs of an AND gate 22. The outputs of the two AND gates are coupled to the count input cl of the counter 10 via an OR gate 24. The outputs 7.1 and 7.2 of the comparators 3.1 and 3.2 respectively are coupled to the count input cl of the counter 11 via an OR gate 23. The pulses applied to the comparators 3.1 and 3.2 via the input terminal 1 are first amplified in an amplifier 25. In the case of an appropriate choice of the gain factor of the amplifier 25 equal potentials may be applied to points 4.1 and 5.1 and to points 4.2 and 5.2. It is obvious that the comparator 2.1 supplies a (third) electric signal (logic "1") when the input terminal 1 receives a pulse whose amplitude relative to the reference level U ref exceeds the first value (equal to U D1 -U ref ) in a positive sense relative to U ref . Moreover, it is evident that the comparator 2.2 supplies a (fourth) electric signal (logic "1") when the input terminal 1 receives a pulse whose amplitude relative to the reference level U ref exceeds the first value in a negative sense relative to U ref It is also obvious that the comparator 3.1 supplies a (fifth) electric signal (logic "1") when the input terminal 1 receives a pulse whose relative amplitude in relation to U ref exceeds the second value (equal to U D2 -U ref ) in a positive sense relative to U ref Moreover the comparator 3.2 supplies a (sixth) electric signal (logic "1") when the input terminal 1 receives a pulse whose relative amplitude in relation to U ref exceeds the second value in a negative sense relative to U ref . The operation of the circuit shown in Fig. 3 is similar to that of the circuit shown in Fig. 1. When N1 pulses whose amplitude relative to U ref is larger than U D1 are applied to the input terminal 1, see Fig. 4a, the counter 10 will count these pulses. At this instant the switch S 1 is in position a-b. After N1 of such pulses have been received the switch S 1 changes over to the (other) position c-b in response to the control signal applied to the control signal input 12 of the switch S 1 by the counter 10, see Fig. 4b. If now pulses of a relative amplitude between U D2 and U D1 are applied to the input terminal 1, see Fig. 4a, the counter 11 will count these pulses. This is because in this case the OR gate 24 does not apply any reset pulses to the reset input of the counter 11. If the counter 11 has counted N2 successive pulses of an amplitude between U D1 and U D2 , see Fig. 4a, the "n=N2" output of the counter 11 goes "high" so that the counter 10 is now set to zero, causing the switch S1 to be reset to position a-b. However, since the outputs are followed by the S-R flip-flops 20 and 21 the pulses detected by the comparators are not transferred to the output terminal 8 but instead a squarewave is transferred whose rising and falling edges indicate the detection instants of the detected pulses. It is obvious that in the present embodiment the comparators 2.1, 2.2, 3.1 and 3.2 form part of the control signal generator means 13′. In the embodiment shown in Figs. 1 and 3 the counter 10 counts N 1 pulses of an amplitude larger than U D1 . These pulses need not necessarily be N 1 consecutive pulses of an amplitude larger than U D1 . The control signal generator means 13 and 13′ may be adapted in such a way that the counter 10 can count only N 1 consecutive pulses of an amplitude larger than U D1 before it supplies a "high" control signal to the control signal input 12 of the switching means S 1 . For the embodiment shown in Fig. 1 this is indicated in Fig. 1a. Fig. 1a shows the control signal generator means 13 of Fig. 1 which, in addition comprises a detector 15, an OR gate 16, an AND gate 17 and an inverter 18. The detector 15 is adapted to supply a "high" control signal if a pulse having an amplitude between U D2 and U D1 is applied to the input terminal 1. In the time interval in which the counter counts 10 pulses while the switch S1 is in position a-b the "n=N1" output of the counter 10 will be low. This means that, via the inverter 18, a "high" signal is applied to the AND gate 17. If now a pulse of small amplitude is applied, i.e. of an amplitude between U D2 and U D1 , the detector 15 will supply a "high" control signal, which is applied to the reset input of the counter 10 via the AND gate 17 and the OR gate 16 to reset this counter to zero. The counter 10 reaches its final count only if N1 consecutive pulses of an amplitude larger than U D1 are applied. Fig. 5 shows an embodiment of a circuit for detecting the pulses of a single polarity relative to the reference level U ref and comprising control signal generator means with a voltage hysteresis It is assumed that N1=N2=1. However, it is to be noted that this is not necessary. If N1 and N2 are not equal to 1 the control signal generator means 13″, just like the control signal generator means in the embodiment shown in Figs. 1 and 3, should be provided with counters. In the present case the control signal generator means 13″ comprise a comparator device 30, a comparator device 31, switching means S2 and a D flip-flop 32, the two last-mentioned elements constituting the signal combination unit 45. The input terminal 1 is coupled to a first input (+) of the comparator device 30, which is constructed as a single comparator, and to a first input 33 of the second comparator device 31. The other (-) input of the comparator 30 is coupled to a point 34 of constant potential. A second input 35 and a third input 36 of the comparator 31 are coupled to points of constant potential 37 and 38 respectively. The outputs 39 and 40 of the comparators 30 and 31 are respectively coupled to the inputs c and a of the switch S 2 . The output terminal b of the switch S 2 is coupled to the D input of the flip-flop 32. The Q output of the flip-flop 32 is coupled to the control signal input 12 of the switch S 1 and to the control signal input 41 of the switch S 2 via a delay 32′. If the output signal of the flip-flop 32 is logic "1" the switch S 1 is in position c-b and the switch S 2 is in position a-b. If the output signal of the flip-flop 32 is logic "0", the switches S 1 and S 2 are in positions a-b and c-b respectively. The detection device, comprising the comparators 2 and 3 and the switch S 1 , again operates in the same way as the corresponding components in the circuit shown in Fig. 1. The operation of the control signal generator means 13″ is illustrated by means of the Table in Fig. 6. The comparator 30 outputs a (third) signal (logic "1") if the pulse applied to the input terminal 1 has a relative amplitude in relation to U ref larger than the third value, or if the amplitude of the pulse is larger than U D3 , i.e. the potential on point 34. This is indicated in column A in Fig. 6. This column specifies the output signal of the comparator 30. The comparator 31 delivers a (fourth) electric signal, being logic "1", on its output if a pulse is an amplitude relative to U ref between the third value and the fourth value is applied to the input terminal 1. In other words: if the amplitude of the pulse is situated between U D4 and U D5 . If a pulse having a relative amplitude between the fourth and the fifth value is applied to the input terminal 1 the comparator 31 will supply a (fifth) electric signal, being logic "0". All this is indicated in column B of the Table in Fig. 6. For a correct operation of the comparator 31 potentials equal to U D4 and UDS are applied to the points 37 and 38 respectively. The various potentials comply with U D5 < U D4 < U D3 and U D2 < U D1 . It is obvious that U D1 may be selected to be equal to U D1 and U D5 to be equal to U D2 . Preferably, the choice U D5 ≤ U D2 < U D1 < U D4 < U D3 is made. The circuit operates as follows, assuming that the switches S 1 and S 2 are initially in positions a-b and c-b respectively. This means that the output of the flip-flop 32 is logic "0". It is also assumed that U D5 is equal to U D2 . A pulse having an amplitude between U D2 and U D3 is applied to the input terminal 1. This pulse is transferred to the output terminal 8 via the comparator 3 and the switch S 1 . Substantially at the instant at which the pulse is transferred to the input terminal 1 a clock pulse is derived, which is applied to the clock input cl of the flip-flop 32. Since the output 39 of the comparator 30 is logic "0" under the influence of the applied pulse, the Q output of the flip-flop 32 remains "0" after this clock pulse. If now a pulse of an amplitude larger than U D3 is applied this pulse is also transferred to the output terminal 8 the comparator 3 and the switch S 1 . Moreover, the output of the comparator 30 goes "high". Upon the clock pulse which is now applied to the flip-flop 32 the logic "high" signal on the D input is transferred to the Q output so that the switches S 1 and S 2 change over to position c-b and a-b respectively after the delay time T. T should be such that the switching means do not yet change over during the applied pulse and have changed over before the next pulse. Since U D4 > U D1 the comparator 2 and the switch S 1 will be transfer pulses of an amplitude larger than U D4 to the output terminal. Moreover, the positions of the switches will not be changed. This is because the output of the comparator 31 remains logic "1", the output of this flip-flop will remains "1" and upon application of a clock pulse to the flip-flop 32. If a pulse having an amplitude between U D5 and U D4 is applied to the input terminal 1 the output 40 of the comparator 31 will become logic "0". Upon the clock pulse which is then applied to the flip-flop 32 the Q output goes "low" so that the switches S 1 and S 2 are changed over to positions a-b and c-b respectively after the delay T. Subsequently, pulses of an amplitude between U D5 and U D3 will not affect the positions of the switches S 1 and S 2 . This implies that a hysteresis is obtained in the range between U D4 and U D3 . Depending on the prior situation the switch S 1 will in position c-b or, conversely, in position a-b for pulses in the amplitude range between U D4 and U D3 . The clock pulse cl applied to the flip-flop 32 may be derived, for example, from the output signal of the comparator having the smallest threshold value. If U D5 is equal to U D2 this may therefore be the comparator 3. For this purpose the output of the comparator 3 may be coupled to a monostable via a delay, which monostable has its output coupled to the clock input of the flip-flop 32. It is obvious that the delay should be selected in such a way that the clock pulse cl appears at such an instant that the pulse is still present on the input terminal 1. This means that the positions of the switches S 1 and S 2 in Fig. 6 relate to the pulse which follows the pulse having an amplitude as indicated in the left-hand column "ampl" in the Table given in Fig. 6. Fig.7 shows a circuit for detecting pulses of positive and negative amplitudes relative to the reference level, which circuit also exhibits the hysteresis effect. Again the comparator device 2″ comprises two comparators 2.1 and 2.2 having their outputs 6.1 and 6.2 coupled to respective inputs 51.1 and 51.2 of the switching means S 1 . The comparator device 3″ again comprises two comparators 3.1 and 3.2, whose outputs 7.1 and 7.2 are coupled to respective inputs 52.1 and 52.2 of the switching means S 1 ′ The switching means S 1 ′ comprise two switches S 11 and S 12 and a flip-flop 53. The input 53.1, i.e. the first sub-input of the first input of the switching means S 1 ′, is coupled to the terminal c of the switch S 11 The input 52.1, being the first sub-input of the second input of the switching means S 1 ′, is coupled to the terminal a of the switch S 11 The input 51.2, i.e. the second sub-input of the first input of the switching means S 1 ′, is coupled to the terminal c of the switch S 12 The input 52.2, i.e. the second sub-input of the second input of the switching means S 1 ′, is coupled to the terminal a of the switch S 12 The terminals b of the switches S 11 and S 12 are coupled to the set input and the reset input respectively of the flip-flop 53. The Q output of the flip-flop 53 constitutes the output of the switching means S 1 ′ which output is coupled to the output terminal 8. The control signal generator means 13′′′ now comprise a first comparator device 30′ comprising a first and a second comparator 30.1 and 30.2 respectively, a second comparator device 31′ comprising a first and a second comparator 31.1 and 31.2 respectively, and a signal combination unit 45′. The comparator 30.1 is identical to and operates in a manner similar to the comparator 30 in Fig. 5. The comparator 31.1 is identical to and operates similarly to the comparator 31 in Fig. 5. Likewise, the comparators 2.1 and 3.1 are identical to and operates similarly to the comparators 2 and 3 respectively in Fig. 5. The comparator 2.2 in Fig. 7 operates in the same way as the combination of the comparator 2.2 and the amplifier 25 in Fig. 3. Likewise, the comparator 3.2 in Fig. 7 operates in the same way as the combination of the comparator 3.2 in the amplifier 25 in Fig. 3. The comparator 30.2 has an inverting input coupled to the input terminal 1 and a non-inverting input coupled to the point 34.2 of constant potential. The potential -U D3 , which is referred to the reference level U ref , is applied to said point. This comparator delivers an (eleventh) electric signal, logic "1", on its output 39.2 if a pulse applied to the input terminal 1 has an amplitude which exceeds the third value U D3 in a negative sense relative to U ref . The comparator 31.2 has an input 33.2 coupled to the input terminal 1, has an input 35.2 coupled to the point 37.2 of constant potential (-U D4 relative to U ref ), and has an input 36.2 coupled to the point 38.2 of constant potential (-U D5 relative to U ref ). The comparator 31.2 supplies a (thirteenth) electric signal, logic "1", when the input terminal 1 receives a pulse having an amplitude which, in a negative sense relative to U ref , lies between the third and the fourth value, and supplies a (fifteenth) electric signal, logic "0", when the input terminal 1 receives a pulse having an amplitude which, in a negative sense relative to U ref , lies between the fourth and the fifth value. The outputs 39.1, 39.2, 40.1 and 40.2 of the comparators are coupled to inputs of the signal combination unit 45′. The signal-combination unit 45′ supplies a control signal for the switching means S 11 and S 12 . This control signal comprises two sub-control signals CS 1 and CS 2 , which are applied to the control signal inputs 12.1 and 12.2 respectively via the outputs 46.1 and 46.2 respectively. The sub-control signal CS 1 controls the switch S 11 and the sub-control signal CS 2 controls the switch S 12 . The circuit operates as follows. It is assumed that the switch S 12 is in position a-b, see Fig. 8c. The position of the switch S 11 is irrelevant and may be position "a-b" or position "c-b", see Fig. 8b. At the instant t-t 1 a positive pulse having an amplitude larger than U D3 is applied to the input terminal 1, see Fig. 8a. Under the influence of this pulse the control signal generator means 13′′′ will generate a control signal CS 2 , causing the switch S 12 to be set to position c-b, see Fig. 8c. Moreover, the switch S 11 will be set to position a-b if it is not yet in this position, see Fig. 8b. This is effected each time that a positive pulse having an amplitude larger than U D5 is detected. The negative pulse at the instant t=t 2 having an amplitude larger than U D3 , see Fig. 8a, causes the switch S 11 to be set to position c-b, see Fig. 8b. Moreover, the switch S 12 is reset to position a-b, see Fig. 8c. This switch setting is obtained each time that a negative pulse having an amplitude larger than U D5 is detected. At the instant t 3 a positive pulse of an amplitude larger than U D4 but smaller than U D3 is applied to the input terminal 1, see Fig. 8a. Again the switch S 12 is set to position c-b, see Fig. 8c. The switch S 11 is reset to position a-b, see Fig. 8b. At the instant t 4 a negative pulse of an amplitude larger than U D4 but smaller than U D3 is applied to the input terminal 1, see Fig. 8a. The switch S 11 is set to position c-b, see Fig. 8b and the switch S 12 is set to position a-b. The positive pulse having an amplitude larger than U D5 but smaller than U D4 received at that the instant t 5 only causes the switch S 11 to be set to position a-b, see Fig. 8b. Consecutive pulses of an amplitude between U D5 and U D4 , such as the pulse at the instant t 6 , see Fig. 8a, no longer cause the settings of the switches S 11 and S 12 to change. If subsequently at an instant t 7 a positive pulse having an amplitude between U D4 and U D3 is applied to the input terminal 1, see Fig. 8d, this will not cause the setting of the switch S 12 to be changed. The same applies to the switch S 11 upon reception of the negative pulse at the instant t 8 , which pulses has an amplitude between U D4 and U D3 . It is not until the positive pulse having an amplitude larger than U D3 is received at the instant t 9 , see Fig. 8d, that the switch S 12 is set to position c-b, see Fig. 8f. A negative pulse at the instant t 10 , whose amplitude is larger than U D4 and may be smaller than U D3 , now causes the switch S 11 to be set to position c-b, see Fig. 8c. Again it is evident that depending upon the prior situation a pulse having an amplitude between U D4 and U D3 causes a switch to be changed over to position c-b in the one case and not to be changed over in the other case. Fig. 9 shows an embodiment of the signal combination unit 45′ in Fig. 7. The circuit comprises I 2 L logic devices as illustrated in Fig. 10a. Fig. 10b shows the circuit diagram of the device in Fig. 10a. The input 70 of the device is coupled to the base of an npn transistor 72. The collector of this transistor is coupled to the output 71 of the device. The positive supply voltage (+) is coupled to the base of the transistor 72 via a current source 73, which transistor has its emitter coupled to earth. The device operates as an inverter. When a logic "0" signal is applied to the input 70 the output 71 will be logic "1" and vice versa . The operation of two these devices, see Fig. 11a, having their outputs coupled to one another, is illustrated by means of the Table in Fig. 11b. It is evident that the output of the device which is logic "0" is predominant. This means that only if the input signals X 1 and X 2 are both logic "0" the output signal y will be logic "1". Fig. 12a shows a devive having two outputs 77 and 78. The circuit diagram of this device is shown in Fig. 12b. If the signal on the input 76 is logic "1" all the outputs are logic "0". If the input signal is logic "0" the output state will depend on whether an output is coupled to an output of another device. If the output of this other device is "high" the output of the device in Fig. 12 will also be "high". In the other case the output will be "low". The operation of devices having more than two outputs is identical to the operation of the device shown in Fig. 12. The operation of the circuit shown in Fig. 9 can now be explained in more detail. First, it is to be noted that U D5 is assumed to be equal to U D2 . This means that the comparators 31.1 and 31.2 in Fig.7 can now be constructed in the same way as the comparators 90.1 and 90.2, see Fig. 9: in these comparators the amplitude of the pulses need only be compared with U D4 and -U D4 . Fig. 9 shows not only an example of the signal combination unit 45′ but gives also more details of the two switches S 11 and S 12 and of the output flip-flop 53. Specifically, the gates G1, G2, G3 and G4 constitute the switch S 11 and the gates G16, G17, G18 and G19 constitute the switch S 12 . Further, the gates G27, G28, F29, G3O constitute the output flip-flop 53. The signal C 1 , which is the output signal of the comparator 2.1, is applied to the circuit shown in Fig.9 via the terminal 91. This means that C 1 is logic "1" if a pulse has an amplitude larger than U D1 . The signal C 2 , which is the output signal of the comparator 3.1, is applied to the terminal 92. Consequently, C 2 is logic "1" if the amplitude of the pulse is larger than U D2 . The signal D1, i.e. the output signal of the comparator 2.2, is applied to the terminal 93. This means that D1 is logic "1" if the amplitude of a negative pulse is larger in absolute value than U D1 . The signal D2, which is the output signal of the comparator 3.2, is applied to the terminal 94, D2 consequently being logic "1" if the amplitude of a negative pulse is larger in absolute value than U D2 . The signal A1, which is the output signal of the comparator 30.1, is applied to the terminal 95. This means that A1 is logic "1" if the amplitude of a pulse is larger than U D3 . The signal A2, which is the output signal of the comparator 30.2, is applied to the terminal 96. This means that A2 is logic "1" if the amplitude of a negative pulse is larger in absolute value than U D3 . The signal B1′ is applied to the terminal 97. B1′ logic "0" if the amplitude of a pulse is larger than U D4 . The signal B2′ is applied to the terminal 98. B2′ is logic "0" if the amplitude of a negative pulse is larger in absolute value than U D4 . The circuit operates as follows. Assuming that a positive pulse of an amplitude larger than U D3 is applied to the input terminal 1, the signal A1 on the terminal 95 causes the gate G10 to go to logic "0", so that the gate G18 goes logic "1". S12 is now set. As a result of this, the gate G15 is "low" and the signal D2 cannot influence the output signal of S 12 . In Fig. 7 this means that S 12 is in position c-b. The input signal applied to the gate G30, which constitutes the set input of the flip-flop 53, is now dictated by the signal D1, which can influence the gate G14. Normally, the output signal of the gate G14 is logic "high" and the gate G30 is "low". When a negative pulse appearing on the input terminal 1 has an amplitude whose absolute value is larger than U D1 the gate G14 goes "low" and the gate G30 goes "high", so that the flip-flop 53 is set. In conclusion, this means that setting of the flip-flop 53 is determined by a negative pulse having an amplitude of an absolute value larger than U D1 and not by a negative pulse having an amplitude of an absolute value larger than U D2 (but smaller than U D1 !). Moreover, the gate G12 can go "high" if a negative pulse whose absolute amplitude is larger than U D3 should appear on the input terminal 1. This is because of the signal B2′ applied to the terminal 98. The gate G11 now goes "low", so that the signal A2 can no longer have any effect. The gate G1 goes "high", causing S 11 to be set. In Fig. 7 this means that the switch S 11 is in position c-b. Thus, "setting" of S 11 is achieved by a negative pulse having an amplitude whose absolute value is larger than U D4 and not by a negative pulse having an amplitude whose absolute value is larger than U D3 . If S 12 had not first been set by a pulse having an amplitude larger than U D3 (or U D4 ), the setting of S 11 would have been dependent on the presence or absence of a negative pulse having an amplitude of an absolute value larger than U D3 . Indeed, the gate G 12 would have been low then, regardless of the signal on the terminal 98. When a positive pulse of an amplitude larger than U D2 is applied the flip-flop FF1 will be set on the trailing edge of this pulse. Its output then goes "high". When the output of the flip-flop FF1 goes "high" S 11 is reset. When a negative pulse whose amplitude is larger in absolute value than U D2 is applied the flip-flop FF2 is set, causing S 12 to be reset. FF1 is reset by means of the signal D2 upon a negative pulse whose amplitude is larger in absolute value than U D2 . Likewise, FF2 is reset by means of the signal C2 upon a positive pulse of an amplitude larger than U D2 . When S 11 is reset the signal C2 is inhibited in the gate G6. When S 12 is set the signal D2 is inhibited in the gate G15. This means that a positive pulse of large amplitude is anticipated on account of the fact that the negative pulse preceding it had a large amplitude, and vice versa . A positive pulse larger than U D1 resets the flip-flop 54 by means of the signal C1 in the same way as the negative pulse having an amplitude larger in absolute value than U D1 has set the flip-flop 53 by means of the signal C1. Conversely, if a positive pulse of an amplitude smaller than U D1 is received the flip-flop 53 is not reset. Since B1′ now remains "high" S 12 is not set via the signal path G9, G10. This means that at the negative side the detection level is situated at U D2 . In turn, this means that G15 is no longer inhibited so that a negative pulse having an amplitude larger in absolute value than U D2 , i.e. the signal D2, can set the flip-flop 53. It is to be noted that the flip-flop 53 has already been set because the preceding positive pulse has not caused a reset signal for the flip-flop. This negative pulse does not intersect the -U D3 level. As a result of this, the input A2 remains "low" and the switch S 11 is not set. Upon the next negative pulse the flip-flop 53 is reset by means of the signal C 2 . If subsequently the pulses remain smaller than U D3 the flip-flop 53 is each time set and reset by the signals D2 and C2 respectively. Fig. 13 illustrates the use of the circuit in accordance with the invention in a video recorder during reading of a video signal which has been recorded in tracks 81 which are inclined relative to the longitudinal direction of the record carrier 80. The record carrier 80 also has an auxiliary track 82 at the edge of and in the longitudinal direction of the record carrier. In this track control pulses 83 are recorded, which are used for correctly controlling the speed of transport of the record carrier 80. For this purpose the pulses 83 are read by means of a stationary read head 84. The pulses read by the head 84 are applied to a read amplifier 86. The read amplifier 86 may be, for example, the write/read device described in the Applicants Netherlands Patent Application no. 8902150. The output 87 of the read amplifier 86 is coupled to the input terminal 1 of the circuit 85. Consequently, this circuit may be constructed in the same way as one of the embodiments described with reference to Figs. 1 to 8. For a further explanation of the operation of the video recorder reference is made to the book "Technik der magnetischen Videosignalaufzeichnung" by B. Morgenstern, published by B.G. Tember Stuttgart 1985, in particular Chapter 6 of this book.

Claims: A circuit for detecting pulses in an electric input signal, which pulses are superposed on a specific reference level (U ref ), the circuit having an input terminal (1) for receiving the electric input signal, the circuit comprising at least a first and a second comparator device (2,3), which comparator devices each have a first input (+) coupled to the input terminal, at least a second input (-), and an output, the second input of each comparator device being coupled to a point of constant potential (U D1 ,U D2 ), the first comparator device (2) being adapted to supply a first electric signal on its output exclusively when the input terminal (1) receives a pulse whose relative amplitude in relation to the reference level exceeds a specific first value, the second comparator device (3) being adapted to supply a second electric signal on its output when the input terminal (1) receives a pulse whose relative amplitude in relation to the reference level exceeds a specific second value, the first value being larger than the second value, the outputs of the first and the second comparator device being coupled respectively to a first input (c) and a second input (a) of switching means (S 1 ), which switching means have an output (b) coupled to an output terminal (8) of the circuit, the circuit further comprising means (13) for generating a control signal on an output, for supplying said control signal to a control signal input (12) of the switching means (S 1 ), the input terminal (1) being coupled to an input of the control signal generator means (13), characterized in that the control signal generator means are adapted to generate a control signal to be supplied to the switching means (S 1 ) in such a way that when the input terminal (1) receives N1 pulses whose relative amplitude in relation to the reference level (U ref ) exceeds a third value the switching means (S 1 ) have been or are set to a position in which the first input (c) and the output (b) are coupled to each other, N1 being an integer larger than or equal to 1. A circuit as claimed in Claim 1, characterized in that the control signal generator means (13) are further adapted to generate a control signal for the switching means (S 1 ) in such a way that when the input terminal (1) receives N2 pulses whose relative amplitude in relation to the reference level is situated between a fourth and a fifth value the switching means (S 1 ) have been or are set to a position in which the second input (a) and the output (b) are coupled to each other, N2 being an integer larger than or equal to 1, that the third value is larger than or equal to the fourth value and the fourth value is larger than the fifth value, that the control signal generator means (13) comprises a first and a second counter (10,11), in that the first counter (10) is adapted to count pulses of a relative amplitude larger than the third value and to deliver a signal on an output after N1 of said pulses have been counted, the second counter (11) is adapted to count pulses of a relative amplitude between the third and the fifth value and to deliver a signal on an output after N2 of said pulses have been counted, and in that the output of the first counter (10) is coupled to the output of the control signal generator means. (fig.1,3). A circuit as claimed in Claim 1 or 2, characterized in that the control signal generator means (13) are adapted to generate a control signal for the switching means (S 1 ) in such a way that when the input terminal (1) receives N1 consecutive pulses whose relative amplitude in relation to the reference level exceeds the third value (U D3 ) the switching means (S 1 ) have been or are set to the position in which the first input (c) and the output (b) are coupled to each other, and in that N1 is larger than 1. A circuit as claimed in Claim 2 or 3, characterized in that the control signal generator means (13) are adapted to generate a control signal for the switchi.ng means (S 1 ) in such a manner that upon reception of N2 consecutive pulses whose relative amplitude in relation to the reference level is situated between the fourth and the fifth value the switching means have been or are set to the position in which the second input (a) and the output (b) are coupled to each other, and in that N2 is larger than 1. A circuit as claimed in Claim 4 or 5, characterized in that the second value is at least substantially equal to the fifth value. A circuit as claimed in Claim 4, 5 or 6, characterized in that the third value is at least substantially equal to the fourth value. A circuit as claimed in Claim 6, characterized in that the first value is at least substantially equal to the third value. A circuit as claimed in Claim 7, in which the second value is at least substantially equal to the fifth value, characterized in that the output of the first comparator device (2) is coupled to the input of the first counter (10) and the output of the second comparator device (3) is coupled to the input of the second counter (11). A circuit as claimed in Claim 8, characterized in that the outputs of the first (2,2.1) and the second (3,3.1) comparator device are coupled, via an AND gate (9), to the input of the first counter (10) and to a reset input of the second counter (11), and in that the output of the second counter is coupled to a reset output of the first counter (Fig. 1, 3). A circuit as claimed in any one of the Claims 1 to 9, characterized in that the comparator devices each comprise one comparator (Fig 1). A circuit as claimed in Claim 2, 6 or 7, characterized in that the comparator devices (2',3') each comprise two comparators (2.1,2.2;3.1,3.2), each comparator having a first and a second input and an output, in that the first inputs of the comparators are coupled to the input terminal (1), the second input (-) of the first comparator (2.1) in the first comparator device (2') is coupled to the second input of the first comparator device, the second input (+) of the second comparator (2.2) in the first comparator device (2') is coupled to to a third input of the first comparator device, the second input (-) of the first comparator (3.4) in the second comparator device (3') is coupled to the second input (+) of the second comparator device, the second input of the second comparator (3.2) in the second comparator device (3') is coupled to a third input of the second comparator device, in that the third inputs of the first and the second comparator device are each coupled to a point of constant potential, in that the outputs of the first and the second comparator in each of the comparator devices are coupled to the output of the comparator device via a signal combination element (20,21), the first and the second compator (2.1,2.2) in the first comparator device (2') are adapted to generate a third and a fourth electric signal respectively exclusively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said first value in a positive and a negative sense, respectively, relative to the reference level, and in that the first and the second comparator (3.1,3.2) in the second comparator device (3') are adapted to generate a fifth and a sixth electric signal respectively, when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said second value in a positive sense and in a negative sense, respectively, relative to the reference level. A circuit as claimed in Claim 11, in which the second value is at least substantially equal to the fifth value, characterized in that the outputs of the first comparators in the two comparator devices are coupled to a first input of an OR gate (24) via an AND gate (9), the outputs of the second comparators in the two comparator devices are coupled to a second input of the OR gate (24) via a second AND gate (22), in that an output of the OR gate (24) is coupled to the input of the first counter (10) and to a reset input of the second counter (11), in that the outputs of the first and the the second comparator (3.1,3.2) in the second comparator device (31) are coupled to an input of the second counter (11) via a second OR gate (23), and in that an output of the second counter (11) is coupled to a reset input of the first counter (10) (Fig 3) A circuit as claimed in Claim 1, characterized in that the control signal generator means (13") comprise a first and a second comparator device (30,31), each having a first input (+,33) coupled to the input terminal (1), at least a second input (-,35) coupled to a point of constant potential (U D3 ,U D4 ), and an output, in that the outputs of the first and the second comparator devices in the control signal generator means are coupled to a first and a second input (A,B) of a signal combination unit (45), which has an output coupled to the output of the control signal generator means (13"), in that the first comparator device (30) in the control signal generator means is adapted to supply a third electric signal (39) when the input terminal receives a pulse whose amplitude relative to the reference level exceeds the third value (U D3 ), in that the second comparator device (31) in the control signal generator means is adapted to supply a fourth electric signal (40) upon when the input terminal receives a pulse whose amplitude relative to the reference level is situated between the third and a fourth value (U D3 ,U D4 ), in that after the input terminal has received N1 pulses whose relative amplitude exceeds the third value the control signal generator means are adapted to generate a control signal in such a manner that after the input terminal has received a subsequent pulse whose relative amplitude exceeds the fourth value the switching means (S 1 ) remain in a position in which the first input (c) is coupled to the output (b), and in that the third value is larger than the fourth value. (Fig. 5,6) A circuit as claimed in Claim 13, characterized in that the control signal generator means (13") are adapted to generate a control signal for the switching means (S 1 ) in such a way that when the input terminal (1) receives N1 consecutive pulses whose relative amplitude in relation to the reference level exceeds the third value (U D3 ) the switching means (S 1 ) have been or are set to the position in which the first input (c) and the output (b) are coupled to each other. A circuit as claimed in Claim 13 or 14, characterized in that the control signal generator means (13") are adapted to generate a control signal for the switching means (S 1 ) in such a way that when the input terminal receives N2 pulses whose relative amplitude in relation to reference level is situated between a fourth and a fifth value (U D4 ,U D5 ) the switching means (S 1 ) have been or are set to a position in which the second input (a) and the output (b) are coupled to each other, N2 being an integer larger than or equal to 1, and in that the third value is larger than or equal to the fourth value and the fourth value is larger than the fifth value. A circuit as claimed in Claim 15, characterized in that the control signal generator means (13") are adapted to generate a control signal for the switching means (S 1 ) in such a manner that upon reception of N2 consecutive pulses whose relative amplitude in relation to the reference level is situated between the fourth and the fifth value (U D4 ,U D5 ) the switching means (S 1 ) have been or are set to the position in which the second input (a) and the output (b) are coupled to each other. A circuit as claimed in claim 15 or 16, characterized in that the second comparator device (31) is further adapted to supply a fifth electric signal when the input terminal receives a pulse whose amplitude relative to the reference level is situated between the fourth (U D4 ) and the fifth value (U D5 ), in that after the input terminal has received N 2 pulses whose relative amplitude is situated between the fourth and the fifth value the control signal generator means (13") are adapted to generate a control signal in such a manner that when the input receives a subsequent pulse whose relative amplitude is smaller than the third value the switching means (S 1 ) remain in a position in which the second input (a) is coupled to the output (b). (Fig 5,6) A circuit as claimed in Claim 17, characterized in that N 1 =N 2 =1. (Fig 5,6) A circuit as claimed in Claim 18, characterized in that the signal combination unit (45) in the control signal generator means (13") comprises switching means (S 2 ) and a flip-flop (32), in that the first and the second input (A, B) of the signal combination unit are coupled respectively to a first and a second input (c,a) of the switching means (S 2 ), which have an output (b) coupled to an input (D) of the flip-flop (32), and in that an output (Q) of the flip-flop (32) is coupled both to the output of the control signal generator means and to the control signal input (41) of the switching means (S 2 ) in the control signal generator means (Fig 5). A circuit as claimed in Claim 19, characterized in that the control signal generator means are adapted to generate a control signal for the switching means (S 2 ) in the control signal generator means (13"), in such a manner that when the input terminal receives a pulse whose amplitude relative to the reference level exceeds the third value (U D3 ) said switching means (S 2 ) have been or are set to a position in which the second input (a) is coupled to the output (b), and in that when the input terminal receives a pulse whose amplitude relative to the reference level is situated between the fourth (U D4 ) and the fifth value (U D5 ) said switching means (S 2 ) have been or are set to a position in which the first input (c) is coupled to the output (b). (Fig 5) A circuit as claimed in Claim 13 or 14, characterized in that N 1 =1, in that the comparator devices each comprise two comparators, each comparator having a first and a second input and an output, in that the first inputs of the comparators are coupled to the input terminal, the second input of the first comparator in the first comparator device is coupled to the second input of the first comparator device, the second input of the second comparator in the first comparator device is coupled to a third input of the first comparator device, the second input of the first comparator in the second comparator device is coupled to the second input of the second comparator device, the second input of the second comparator in the second comparator device is coupled to a third input of the second comparator device, in that the third inputs of the first and the second comparator device are each coupled to a point of constant potential, in that the outputs of the first and the second comparator (2.1,2.2) in the first comparator device (2") are coupled respectively to a first and a second subinput (51.1,51.2) of the first input of the switching means (S 1 '), the outputs of the first and second comparator (3.1,3.2) in the second comparator device (3") are coupled respectively to a first and a second sub-input (52.1,52.2) of the second input of the switching means (S 1 '), the first and the second comparator (2.1,2.2) in the first comparator device are adapted to generate a sixth and a seventh electric signal exclusively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said first value (U D1 ) in a positive or negative sense, respectively, relative to the reference level, and in that the first and the second comparator (3.1,3.2) in the second comparator device are adapted to generate an eighth and a ninth electric signal respectively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said second value (U D2 ) in a positive and a negative sense, respectively, relative to the reference level, in that the first and the second comparator devices (30',31') in the control signal generator means (13''') each comprise two comparators, each comparator having at least a first and a second input and an output, in that the first inputs of the comparators are coupled to the input terminal, the second input (-) of the first comparator (30.1) in the first comparator device (30') is coupled to the second input of the first comparator device, the second input (+) of the second comparator (30.2) in the first comparator device (30') is coupled to a third input of the first comparator device, the second input of the first comparator (31.1) in the second comparator device (31') is coupled to the second input of the second comparator device, the second input of the second comparator (31.2) in the second comparator device (31') is coupled to a third input of the second comparator device, in that the third inputs of the first and the second comparator device are each coupled to a point of constant potential, in that the outputs of the first and the second comparator in each of the comparator devices are coupled, via a signal combination element (45'), to the output of the control signal generator means (13'''), the first and the second comparator (30.1,30.2) in the first comparator device (30') are adapted to generate a tenth and an eleventh electric signal respectively exclusively when the input terminal receives a pulse whose amplitude relative to the reference level exceeds said third value (U D3 ) in a positive and a negative sense, respectively, relative to the reference level, and in that the first and the second comparator (31.1,31.2) in the second comparator device (31') are adapted to generate a twelfth and a thirteenth electric signal respectively when the input terminal receives a pulse whose amplitude, in a positive and a negative sense relative to the reference level respectively, is situated between the third and the fourth value (U D3 ,U D4 ), and in that the signal combination unit (45') is adapted to generate a control signal from the tenth through the thirteenth signal in such a manner that when the input terminal receives a pulse whose relative amplitude exceeds the third value (U D3 ) in a positive sense relative to the reference value the switching means (S 1 ') have been or are set to a position in which the second sub-input (51.2) of the first input is coupled to the output (8), in that when the input terminal receives a pulse whose relative amplitude exceeds the third value (U D3 ) in a negative sense relative to the reference value the switching means (S 1 ') have been or are set to a position in which the first sub-input (51.1) of the first input is coupled to the output (8) (Fig 7) A circuit as claimed in Claim 21, characterized in that after the input terminal has receives a pulse whose relative amplitude in relation to the reference level exceeds the third value in a positive sense relative to said reference level the control signal generator means (13''') are adapted to generate a control signal in such a manner that after the input terminal has received a subsequent pulse whose relative amplitude in relation to the reference level exceeds the fourth value (U D4 ) in a negative sense relative to said reference level the switching means (S 1 ') have been or are set to a position in which the first sub-input (51.1) of the first input is coupled to the output (8) A circuit as claimed in Claim 21, characterized in that after the input terminal has received a pulse whose relative amplitude in relation to the reference level exceeds the third value (U D3 ) in a negative sense relative to said reference level the control signal generator means (13''') are adapted to generate a control signal in such a manner that after the input terminal has received a subsequent pulse whose relative amplitude in relation to the reference level exceeds the fourth value in a positive sense relative to said reference level the switching means have been or are set to a position in which the second sub-input (51.2) of the first input is coupled to the output (8). A circuit as claimed in Claim 21, characterized in that after reception of a positive pulse relative to the reference level the control signal generator means are adapted to generate a control signal in such a manner that the switching means (S 1 ') have been or are set to a position in which the first sub-input (52.1) of the second input is coupled to the output (8). A circuit as claimed in Claim 21, characterized in that after reception of a negative pulse relative to the reference level the control signal generator means are adapted to generate a control signalin such a manner that the switching means (S 1 ') have been or are set to a position in which the second sub-input (52.2) of the second input is coupled to the output (8). A circuit as claimed in any one of the Claims 21 to 25, characterized in that the switching means comprise a first and a second switch (S 11 ,S 12 ) and a flip-flop (53), each switch has a first and a second input (c,a) and an output (b), the first input (c) of one switch (S 11 ) is coupled to the first sub-input (51.1) of the first input of the switching means (S 1 '), the second input (a) of said switch is coupled to the first sub-input (52.1) of the second input of the switching means, the first input (c) of the other switch (S 12 ) is coupled to the second sub-input (51.2) of the first input of the switching means, the second input (a) of the second switch is coupled to the second sub-input (52.2) of the second input of the switching means, the outputs of the two switches are coupled respectively to the set input and the reset input of the flip-flop (53), which has an output coupled to the output (8) of the switching means (Fig 7) A video recorder, comprising a read unit for reading CTL pulses from a track (82) on a magnetic record carrier (80), which read unit comprises a read head (84), characterized in that the read unit comprises a circuit (85) as claimed in any one of the preceding Claims, which circuit has its input terminal (1) coupled to an output of the read head (84) (Fig 13).

Inventors: BAETEN CHRISTIAN HENRICUS PETR, INGHELS JOHANNES, VAN LEEUWEN PIETER GERRIT, VAN LOO EDUARD, BAETEN, CHRISTIAN HENRICUS PETRUS, INGHELS, JOHANNES, VAN LEEUWEN, PIETER GERRIT, VAN LOO, EDUARD
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: G11B20
IPC codes: G11B27, G11B15, G11B20