Instruction unit logic management apparatus included in a pipelined processing unit and method therefor

Abstract: A pipelined processing unit which includes an instruction unit stage containing logic management apparatus for processing a set of complex instructions. The logic management apparatus includes state control circuits which produce a series or sequence of control states used in tracking the different types of instructions of the complex instruction set being processed. Different ones of the states are used for different types of instructions so as to enable the different pipeline stages to operate both independently and jointly to complete the execution of different instructions of the complex instruction set.

Description: RELATED APPLICATIONS 1. The patent application of Ming-Tzer Miu and Thomas F. Joyce entitled, "Production Line Method and Apparatus for High Performance Instruction Execution," bearing number EP 378,816 , which is assigned to the same assignee as this patent application. 2. The patent application of David E. Cushing, Romeo Kharileh, Jian-Kuo Shen and Ming-Tzer Miu entitled, "A Dual Port Read/Write Register File Memory," bearing number EP 374,829 , which is assigned to the same assignee as this patent application. 3. The patent application of Jian-Kuo Shen, Richard P. Kelly, Robert V. Ledoux and Deborah K. Staplin entitled, "Control Store Addressing from Multiple Sources," bearing number EP 374,598 , which is assigned to the same assignee as this patent application. 4. The patent application of Richard P. Kelly, et al. entitled "Means for Transferring Firmware Signals Between a Control Store and a Microprocessor Means through a Reduced Number of Connections by Transfer According to Firmware Signal Function", issued as U.S. Patent No. 4 916 601 on April 10, 1990, which is assigned to the same assignee as this patent application. 5. The patent application of Richard P. Kelly and Robert V. Ledoux entitled, "Control Store Address Generator for Developing Unique Instruction Execution Starting Address," bearing number EP 374,830 , which is assigned to the same assignee as this application. 6. The patent application of David E. Cushing, Richard P. Kelly, Robert V. Ledoux and Jian-Kuo Shen entitled, " A Mechanism for Automatically Updating Multiple Unit Register File Memories," now US Patent 4,980,819 , which is assigned to the same assignee as this application. 7. The patent application of Richard P. Kelly, et al. entitled "Apparatus for Generating First and Second Selection Signals for Aligning Words of an Operand and Bytes Within these Words Respectively", issued as U.S patent No 5 179 671 on January 12, 1993, which is assigned to the same assignee as this application. 8. The patent application of Robert V. Ledoux, Richard P. Kelly and Forrest M. Philips entitled, "Ring Reduction Logic," bearing number EP 389,886, which is assigned to the same assignee as this application. 9. The patent application of Deborah K. Staplin, Jian-Kuo Shen and Ming-Tzer Miu entitled, "Resource Conflict Detection Method and Apparatus Included in a Pipelined Processing Unit," bearing number EP 405,489, which is assigned to the same assignee as this application. BACKGROUND OF THE INVENTION Field of Use This invention relates to pipelined data processing systems and more particularly to apparatus for decoding instructions within such systems. Prior Art Many techniques have been developed in order to improve the performance of high performance systems. These have involved the development of so-called pipelined processors which process instructions stored in cache memories in such a manner that more than one instruction is actually being processed at any one given time. In such a system, one instruction might be completed within a given machine cycle at the same time as another instruction had only been partially completed. While such systems achieve high performance, instructions are placed serially into the pipeline and as soon as the stage has completed its operation, the instruction is passed onto the next processing stage. Therefore, instructions are executed in the order in which they enter the pipeline. In order to improve system performance, some systems overlap the operations being executed by certain stages within the pipeline. An example of this type of system is described in U.S. Patent No. 4,760,519. While the above improves performance, instructions are still required to be executed in the order in which they are introduced into the pipeline. The performance of a pipelined system has been improved by having the processing unit operate in a production line fashion in which earlier stages are able to complete the execution of certain types of instructions ahead of earlier introduced instructions. This processing unit is subject of related copending application titled "Production Line Method and Apparatus for High Performance Instruction Execution." While pipelined processing units provide high performance, their performance still depends greatly on the efficient processing of a large number of different types of instructions. This is complicated when there is a requirement for compatibility and where more than one stage within the pipeline is designed to execute instructions to enhance performance such as in the referenced patent application. One approach used in handling a complex instruction set which is described in U.S. Patent No. 4,179,736 is to use a microprogrammed data processing unit having first and second control stores and hardwired sequence circuits. The first control store includes locations which store address and control sequence fields while the second control store includes sequences of microinstructions for executing different portions of the operations specified by the program instructions. The control sequence field is used to designate which one of a number of hardware control sequences is to be carried out by the hardwired control circuits in processing the instruction through the use of control state circuits. While this arrangement is capable of processing a complex instruction set, the two-level control store arrangement requires additional processing time and space which do not lend themselves to VLSI construction. Further, the arrangement is designed for use in a CPU containing a small number of pipeline stages having a single execution unit. Other prior art documents, such as EP-A-0 173 466, discloses in a data processing system an instruction apparatus comprising two units for controlling the execution of instructions, wherein said instructions are received, in succession, by the first of said units, with each unit for performing a different operation on each received instruction. However, execution of instructions is not in a pipelined mode. EP-A-0 180 227 discloses an instruction execution controller wherein, in a multi-program mode, a first operation unit is under the control of microinstructions stored in a first program memory and a second operation unit is under control of microinstructions stored in a second program memory. EP-A-0 198 214 relates to branch instructions and discloses that branch instructions may be executed at the end of the decoding stage which usually is the first stage. There is only one class of branch instructions mentioned. Accordingly, it is the main object of this invention to provide apparatus and method for managing the processing of a complex instruction set within a pipelined data processing system thereby maximizing system performance and requiring a minimum of system complexity. The above and other objects are solved by applying the features laid down in the independent claims 1 and 8. Further features and aspects of the apparatus and method as well as enhancements thereof are defined in the associated subclaims. SUMMARY OF THE INVENTION According to the teachings of the present invention, there is provided an apparatus including state control circuits which produce a series or sequence of control states used in tracking the different types of instructions of the complex instruction set being processed. Different ones of the states are used for different types of instructions so as to enable the different pipeline stages to operate both independently and jointly to complete the execution of different instructions of the complex instruction set. In more particular terms, certain states are used to enable an early pipeline stage to complete the execution of (branch and register) certain types of instructions such as, for example, branch and register instructions. Other states are used to enable the first and early pipeline stages to complete the cracking of other types of instructions such as, for example, instructions which include remote descriptors. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying drawings. It is to be expressly understood, however, that each of the drawings are given for the purpose of illustration and description only and are not intended as a definition of the limits of the present invention. DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of the pipelined processing unit which includes the apparatus and method of the present invention. Figure 2 shows in greater detail, the instruction unit of Figure 1. Figures 3 through 5c are diagrams used to explain the operation of the preferred embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 shows in block diagram form, a production data processing system 10. As shown, the system includes a central processing unit (CPU) 20, a virtual memory management unit (VMMU) 40 and a cache unit 60. The cache unit 60 couples to a system bus 80 through a bus interface unit (BIU) 100. The processing unit (CPU) is constructed according to the principles of the present invention. As shown, the main elements of CPU 10 include an instruction unit 20-2, an A-unit 20-4 and a number of execution (E) units 20-6. In the preferred embodiment, the execution units 20-6 include a scientific instruction processing unit (S-Unit) and a commercial instruction processing unit (C-Unit). The cache unit includes an instruction cache (I-cache) 60-2 for storing instructions which are to be executed and an execution cache unit (E-cache) 60-4 for storing operands or data which are to be operated on according to the instructions being executed. The I-unit 20-2 performs two main functions. It prefetches instructions from I-cache unit 60-2 and cracks or decodes those instructions to determine how the other units, namely the A-unit 20-4 and the E-unit 20-6 will further process those instructions. In addition, the I-unit 20-2 executes certain branch instructions which are then removed from the production line. The A-unit 20-4 generates addresses from instructions it receives from the I-unit 20-2. Additionally, it executes certain types of instructions such as register-to-register type instructions removing them from the production line. When the instruction is a type of instruction which is to be executed by the E-unit 20-6, the A-unit 20-4 sends a virtual address to VMMU 40 which translates it into a physical address for fetching the specified operands from the E-cache unit 60-4. The operands fetched from the E-cache unit 60-4 are then transferred to the E-unit 20-6 for completing the execution of the instruction originally received by the I-unit 20-2 from the I-cache unit 60-2. The A-unit 20-4 will also confirm the execution of a branch instruction and send the branch address back to the I-unit 20-2 which will have already requested the next instruction from I-cache unit 60-2 specified by the I-unit 20-2 prefetch branch address. Both the A-unit 20-4 and E-unit 20-6 include register files which store the contents of the registers which are programmer accessible, as explained in greater detail herein. Both the I-cache unit 60-2 and E-cache unit 60-4 are updated with instructions and operands fetched from main memory via system bus 100 and BIU 80. Production Line Mode of Operation Instructions are executed in a production like fashion by the elements of CPU 20. That is, the I-unit 20-2 receives each instruction from I-cache unit 60-2, cracks it and then sends the instruction to the A-unit 20-4. The A-unit 20-4 either executes the instruction or sends the virtual address to the VMMU 40 for translation in order to fetch the required operands from E-cache unit 60-4 which are in turn sent to E-unit 20-6. While the A-unit 20-4 is executing its portion of a first instruction received from I-unit 20-2, the I-unit 20-2 is fetching a second instruction and subsequent instructions from I-cache unit 60-2. When the A-unit 20-4 sends the virtual address specified by the first instruction to VMMU 40 and notifies the I-unit 20-2 of that event, the I-unit 20-2 sends the second instruction to A-unit 20-4. The VMMU 40 addresses E-cache unit 60-4 while the A-unit 20-4 is processing the second instruction introduced into the production pipeline. When the E-unit 20-6 is executing the first instruction, VMMU 40 may be fetching operands from the E-cache unit 60-4 specified by the second instruction while the A-unit 20-4 is generating a virtual address for a third instruction. At the same time, the I-unit 20-2 is cracking a fourth instruction and fetching a next instruction. Thus, there could be five instructions progressing down the production line at a given instant of time. However, since the I-unit 20-2 can execute certain branch instructions and the A-unit 20-4 can execute certain software visible register instructions, these instructions are removed from the production line as soon as the execution of these instructions are completed. Also, when the A-unit 20-4 is processing a branch instruction and the conditions of the branch are met, the A-unit 20-4 immediately confirms the branch address received from the I-unit 20-2 and the branch instruction is removed from the production line. Accordingly, it is important that the production line operation proceed without interruption. However, there are situations in which there may be conflicts in the resources specified by the instructions being introduced into the production line. The arrangement of the present invention utilizes the fact that certain units of the production line execute a subset of the total number of instructions. Therefore, it takes advantage in terms of performance that only certain registers and indicator resources will never be in conflict between the A-unit 20-4 and E-unit 20-6. The reduction in resources is reflected in the resource control word(s) generated by the I-unit 20-2 as a result of cracking each instruction as explained herein. Additionally, complex instructions are specially handled. A complex instruction is an instruction which can have many potential trap conditions which make it very difficult to predict with sufficient certainty, the operating state of the pipeline before the trap took place. Such complex instructions are detected by the I-unit and cause it to stop the pipeline. This has the advantage of reducing substantially, chip circuit complexity which is important for the reasons previously mentioned. I-UNIT 20-2 Figure 2 shows the I-unit 20-2 in greater detail. The I-unit 20-2 includes an I chip 20-20 and glue logic circuits 20-22 which interconnect the I chip to the other chips of the CPU. The I chip 20-20 is logically divided into an I fetch unit (IFU) 20-200 for fetching instructions from the I-cache unit 60-2 and an I crack unit (ICU) 20-250 for "cracking" or decoding the fetched instructions. The IFU 20-200 includes the adder, multiplexer and register elements 20-202 through 20-218 arranged as shown. The IFU 20-200 uses a local program counter 20-208 to generate branch addresses. Initially, the P counter 20-208 is loaded with a virtual address received from A-unit 20-4 via multiplexer circuit 20-206 in response to a load signal A-P-LD also received from the A-unit 20-4. The virtual address points to the location in I-cache unit 60-2 which stores the next instruction that is to enter the pipeline. During an I fetch cycle, the virtual address is transferred to I-cache unit 60-2 via multiplexer circuit 20-210 from either VA0 register 20-212 or VA1 register 20-214 through multiplexer circuit 20-218. Either VA0 register 20-212 or VA1 register 20-214 is used to furnish the virtual address until a branch instruction is decoded by the I-unit 20-2. At that time, it will switch the VA register such that if VA0 register is active, then the address called for by the branch instruction is then stored in VA1 register 2-214. If the ICU 20-250 detects a small (seven or sixteen bit) displacement branch instruction, then the I-unit will generate the branch address by sending a 16- bit displacement value to IFU 20-200 via multiplexer circuit 20-204. This value is added via adder 20-202 to the contents of the P counter 20-208 to create the branch address. It is then loaded into the VA register selected by the VA pointer. The ICU 20-205 includes two sets of string buffers (SBA and SBB) which correspond to blocks 20-252 and 20-254. Each buffer includes eight 16-bit registers and receives data from the I-cache unit, thirty-two bits at a time. As shown, each instruction read out of I-cache unit 60-2 is loaded into either buffer 20-252 or 20-254. The ICU 20-250 maintains a current string pointer denoting which of the two string buffers is in use, in addition to input and output pointers for each buffer. One of the string buffers receives a stream of successive instructions from I-cache unit 60-2 until there is a branch instruction. The instructions of the stream following the branch instruction are stored in the other string buffer. As shown, each instruction of the instruction stream being processed is transferred via multiplexer 20-256 to the I crack logic circuits of block 20-260 and to the A- and E-units via multiplexer 20-258. The I crack logic circuits of block 20-260 include three cracking or decoding circuit areas ICKHI, ICKMD and ICKLO. Each of the crack areas decode or crack in parallel, a different group of bits of each instruction. The results of the first stage are applied to a second stage of cracking or decoding which corresponds to the block labeled ICRK. The ICRK stage determines exactly what instruction is being processed with which address syllable, etc. That is, it determines the specific kind of instruction which is to be executed. For example, if it is a software visible register to register instruction, it will be executed by the A-unit 20-2, and if it is a memory instruction, it will be executed by the E-unit 20-6. The ICRK stage provides signals to update the string buffer counters 20-270 and the resource control pointer circuits of the resource control area block 20-280. The I crack circuits 20-260 also apply the instruction word signals to the control store I/A address generation circuits 20-220 of the glue logic circuits 20-22. The generation circuits 20-220 address the A-unit control store which reads out a microinstruction word into the A-unit RDR register for executing the instruction. The last part of ICU 20-250 is the state control circuits of block 20-290 which is constructed according to the teachings of the present invention. These circuits control the sequencing of the I-unit 20-2 in cracking the different types of instructions of the complex instruction set of Figure 3. It also generates output signals, such as signals state 0, 4 and 6, which are applied to the control store address generation circuits 20-220 which generates the addresses of firmware/microinstruction words used by A-unit 20-4 in executing instructions. Additionally, the state control circuits 20-290 control the states of string buffer pointers and their associated string buffers as explained herein. The circuits 20-290 include a plurality of state flip-flops ISTATE0 through ISTATE7. These flip-flops include circuits which set and reset the flip-flops as a function of the type of instruction and size as described herein. The equations for setting and resetting each of these state flip-flops are included in the Appendix. INSTRUCTION SET OF FIGURE 3 As mentioned, the state control apparatus of the present invention enables I-unit 20-2 to control efficiently, the processing of the complex instruction set of Figure 3 by a plurality of pipeline stages capable of completing the execution of different types of instructions within such set. As seen from Figure 3, the instruction set is divided into several categories of instructions. These include: a general or basic instruction set; an extended integer (EII) instruction set; a commercial instruction set, and a scientific instruction set. The basic instruction set includes seven types of instructions, such as generic, branch on indicators, branch on registers, shift short and shift long, short value immediate, input/output, single operand and double operand. The generic instructions executable by the E-unit 20-6 include a halt instruction, a diagnostic instruction, a memory-to-memory move instruction and a load stack instruction. They also include other instructions which allow programmers to build and control a software stack. These instructions are executable by I-unit 20-2, A-unit 20-4 and E-unit 20-6. The EII instruction set is executed by the E-unit 20-6 and provides access to any one of seven K registers. As shown, this instruction set includes instructions for loading an operand into a specified K register, comparing the value in a specified K register with an operand, etc. The commercial instruction set is executed by the C-unit of block 20-6. These instructions include numeric, alphanumeric and edit. As shown, certain ones of these instructions can use in-line data descriptors which describe the one-to-three operands used by the instruction with the number of operands being a function of instruction type. The same instructions can also specify remote data descriptors to describe the same one-to-three operands used by the instruction. The bits 12-15 of the first word of a data descriptor is coded to distinguish between in-line and remote data descriptors. For a further description of the formatting of these types of instructions, reference may be made to U.S. Patent No. 4,638,450. The scientific instruction set is executed by the scientific unit apparatus included in E-unit 20-6. These instructions include single operand and double operand instructions. These different instruction sets are cracked by the I crack logic circuits 20-260 and the resulting information signals are applied to the control state circuits 20-290. Figure 4 shows the assignment of states to the different types of instructions of the four instruction sets. The I-unit 20-2 starts instruction cracking in state 0 which serves as an idle state. Based on the instruction type and size, it sequences to the other states as shown. For example, if the instruction being cracked is not a commercial, not I/O, not generic with address syllable and not a branch, and its size is less than or equal to two words, the control state circuits 20-290 remain in state 0. If the instruction being cracked is not commercial, I/O, generic or a branch, and its size is larger than two words, the control state circuits 20-290 sequence to state 1. If the instruction is a branch other than an unconditional branch, or an unconditional branch with other than small displacement or with trace trap enabled, the control state circuits 20-290 sequence to state 2. For unconditional branch instructions with small displacements and trace trap disabled, the control state circuits 20-290 sequence to state 3. For commercial, I/O or those types of new generic instructions which have an address syllable, the control state circuits 20-290 sequence to state 4 as shown. The circuits 20-290 remain in state 4, except when the instruction being cracked is a commercial instruction with a remote data descriptor. When the E-unit 20-6 completes the execution of the instruction and sends an E-unit done signal, the control state circuits 20-290 return to state 0. If the instruction being cracked is a commercial instruction with a remote data descriptor, the control state circuits 20-290 sequence through states 5 and 6 or states 5, 6 and 7 as a function of the size or number of words in the data descriptor. DESCRIPTION OF OPERATION In accordance with the teachings of the present invention, the states used by the circuits 20-290 are selected to enable the execution of certain types of instructions to be completed solely by one specific pipeline stage or jointly by more than one stage in a manner which improves performance and minimizes complexity. With reference to Figures 1-4, the operation of the apparatus will now be described relative to the examples illustrated in Figures 5a through 5c. The Figures 5a and 5b illustrate the manner in which I-unit 20-2 and A-unit 20-4 work together in processing commercial instructions containing remote data descriptors. A remote data descriptor is a descriptor that is inaccessible to I-unit 20-2 in that the I-unit 20-2 does not have enough information to access it. However, the A-unit 20-4 includes the necessary circuits for generating the required descriptor address. This address is transferred to the I-unit, which can then fetch the remote descriptor. It is assumed that the instruction being cracked is a commercial numeric type instruction such as a decimal add (DAD) instruction which has two data descriptors. The first descriptor is in-line and includes a displacement to be added to the P counter. The second descriptor is a remote data descriptor and includes a "big displacement" (BD) of two words to be added to the P counter. The DAD instruction is cracked by I-unit 20-2 when in state 0 as shown in Figure 5b. Thereafter, the control state circuits 20-290 sequence to state 4. When in that state, the control state circuits 20-290 crack the first data descriptor which is determined to be an in-line descriptor (i.e., bits 12-15 are not all ZEROS). The I-unit 20-2 remains in state 4 and transfers the descriptor to the A-unit. At such time as the A-unit is ready for the second data descriptor, it sends a CPCK firmware code to the I-unit 20-2. Then the I-unit moves to the second data descriptor word and cracks it. In this case, it determines that this word is not a data descriptor but a pointer to a remote memory location. The I-unit transfers the pointer to the A-unit along with the strobe I-NXTCK. As seen from Figure 5b, the state circuits 20-290 move from state 4 to state 5 and allow the A-unit 20-4 to generate the address of the remote data descriptor. Thus, state 5 is a wait state for the I-unit 20-2. As seen from Figure 5b, when the I-unit 20-2 moves to state 5, it toggles the string buffer pointer SP so that it points to the alternate set of string buffer registers. It also toggles to the alternate virtual address register. This provides storage for the remote data descriptor address to be generated by the A-unit 20-4 and the descriptor itself. That is, when the remote data descriptor words have been stored in instruction cache unit 60-2, A-unit 20-4 forces a remote data descriptor signal RDDLD to a binary ONE, enabling the descriptor address to be loaded into the alternate virtual address register. This causes the state circuits 20-290 to move from state 5 to state 6. In state 6, the virtual address is sent to the I cache 60-2. The descriptor is then fetched from I cache to the alternate string buffer. The I-unit 20-2 transfers the first two words from the alternate string buffer and cracks the words. These words are transferred to the A-unit via an instruction bus along with the strobe I-NXTCK. In the present example, it is assumed that the remote data descriptor is three words. Therefore, the control state circuits 20-290 move to state 7 before returning to state 4 to transfer the second and third descriptor words to A-unit 20-4. Note that the second data descriptor word is transferred twice. It is transferred once with the first word, which the A-unit expects to be left justified on the instruction bus, and again with the third word, which the A-unit expects to be right justified on the bus. In the case where the remote data descriptor is two words long, the control state circuits 20-290 move from state 6 to state 4. Upon returning to state 4, the control state circuits 20-290 toggle the string pointer back to the original string buffer to continue the processing of the current instruction stream. From the above, it is seen how the I-unit 20-2 and A-unit 20-4 operate together under the control of state circuits 20-290 in processing commercial type instructions containing remote data descriptors. Through this joint effort, the I-unit 20-2 is able to crack this type of complex instruction, eliminating the need to include additional circuits within the C-unit of block 20-6 to carry out such operations. Figure 5c illustrates the manner in which the I-unit 20-2 processes branch types of instructions under the control of state circuits 20-290. As discussed, two different states are used for branch instructions. In the case of an unconditional branch instruction with a small displacement and trace trap disabled, the I-unit 20-2 is able to generate the branch address through IFU 20-200. Since the result of the branch is known (i.e., it is unconditional), the I-unit 20-2 can both prefetch the next instruction stream and begin cracking instructions within the stream while the A-unit 20-2 executes in parallel the same branch instruction. Following the A-unit's completion of the unconditional branch instruction, it generates the A-BRANCH signal, enabling the branch address to be loaded into the P counter. By allocating a separate state (i.e., state 3) for unconditional branch instructions, it is possible to eliminate an extra cycle of operation. That is, it eliminates the need to wait for the A-unit to complete execution of the branch before cracking the next instruction. Thus, the control state circuits 20-290 move to state 1 and return immediately to state 0. In the case of conditional branch instructions, the control state circuits 20-290 move from state 0 to state 2. The circuits 20-290 remain in state 2 until signal A-P-LD is received from A-unit 20-4 indicating that it has generated the branch address and completed the branch. From the above, it is seen that through the efficient use of control state circuits, in cracking branch type instructions, increased performance is attained. Since unconditional branch instructions are frequently used, the savings in cycles could prove to be substantial. APPENDIX The mnemonics of the instructions are given in the publication entitled, "Hardware Version of DPS6 Programmers Pocket Guide," Order No. CU75-02 (August 1984) and subsequent updates. The notations in the Boolean equations are as follows: EQ 0100 EQUAL TO HEXADECIMAL 0100 GT 3 GREATER THAN HEXADECIMAL 3 EQ 2 NOT EQUAL TO HEXADECIMAL 2 NLT 018 NOT LESS THAN HEXADECIMAL 018 NGT 01E NOT GREATER THAN HEXADECIMAL 01E LT 3 LESS THAN HEXADECIMAL 3. The I-BEGIN signal is generated by the Boolean equation: I-BEGIN = CRACK & ^STALL & ^HOLD wherein CRACK = STATE0 & ^NONELEFT & ADONE & (^ONELEFT + STATE0SIZ1). The ^ signifies a negated signal, i.e., ^HOLD should be read as the "NOT HOLD" signal. The Boolean equation for the I-EFIRST signal is: I-EFIRST = CRACK & ^STALL & EINSTR. The Boolean equation for signal EINSTR is generated as a function of combinations of bits of the different types of instructions that require execution by the E-unit 20-6. The Boolean equation is: EINSTR = GCS + (IO + IOLD + SC + MASK + BIT4 + LB + LEV + INCDEC & ^RAS + MTM + MUL + DIV + STM + SSBP) & ^EII + (BSTORE + EBIM0) & IMO + EMSK & EII + MLV & (SI + ESI & EII1) + (ESO+EDO) & (^ERAS&(EII1 + EII23) + AS3EII45) + EEII & (EII1 + EII23) + (SDO + SO) & ^RAS & ^IMO & ^EII. DESCRIPTION OF EQUATION TERMS GENERIC, COMMERCIAL, OR SCIENTIFIC INSTRUCTIONS GCS = I-INST (0-8).EQ.0; IO INSTRUCTION IO = (I-INST (0-8).EQ.0100) IOLD INSTRUCTION IOLD = I-INST (0-8).EQ.0103 SINGLE OPERAND INSTRUCTIONS SO = (I-INST (0-3).EQ.8 & ((I-INST (4-8).EQ.1) + (I-INST (4-8).GT.3)) SINGLE OPERAND INSTRUCTION THAT USES B REGISTERS IN THE E-UNIT 2-6 SSBP = I-INST (0-8).EQ.0106 SINGLE OPERAND INSTRUCTIONS THAT USE OVERFLOW: (NEG, CAD, AID, SID, INC., DEC. INSTRUCTIONS) SOV = SO & ((I-INST (4-8).EQ.4) + (I-INST (4-8).EQ.01D) + (I-INST (4-7).EQ.4)) + INCDEC LB INSTRUCTION LB = SO & (I-INST (4-8).EQ.05) BIT INSTRUCTIONS (LBF, LBT, LBC, LBS) BIT4 = (I-INST (0-5).EQ.022) & (I-INST (8).EQ.0) BASIC DOUBLE OPERAND OR SCIENTIFIC INSTRUCTIONS SDO = (I-INST (0-3).GT.8) & (I-INST (4-8).NEQ.2) BASIC INSTRUCTIONS WITH IN-LINE MASK WORD: (SRM, NSAVE, NRSTR, SAVE, RSTR ) MASK = (I-INST (0).EQ.1) & (RLBP.NEQ) & I-INST (4-8). EQ.015) + (I-INST (0-7).EQ.085) + (I-INST (0-7).EQ.08F) SCIENTIFIC SINGLE AND DOUBLE OPERAND INSTRUCTIONS SC = ((I-INST (0-3).GT.8) & ((I-INST (4-8).EQ.011) + (I-INST (4-8).EQ.013) + (I-INST (4-8).EQ.018) + (I-INST (4-8).EQ.01A))) & ^EII1 & ^EII23 & ^AS3EII45 DOUBLE OPERAND INSTRUCTION THAT USES M REG AND DOES NOT STOP PIPELINE STM = (I-INST (O).EQ.1) & (RLBP.NEQ.0) & (I-INST (4-8) .EQ OE) WHERE RLBP = I-INST (1-3) MULTIPLY INSTRUCTION MUL = (I-INST (0).EQ.1) & (RLBP.NEQ.0) & (I-INST (4-8) .EQ 016) DIVIDE INSTRUCTION DIV = (I-INST (0).EQ.1) & (RLBP.NEQ.0) & (I-INST1 (4-8) .EQ 06) MODIFY OR TEST M REGISTER INSTRUCTION MTM = (I-INST (0-3).GT.8) & (I-INST (4-8).EQ.0) SO, DO STORE INSTRUCTIONS NEG, SSBP, CPL, CALL, CL, CLH, LBF, DEC, LBT, LBS, INC, LBC, STS,SDI, CAD (ALSO LEN) STM, STH, SRM, SWR, SWB, STR, STB BSTORE = SO & ((I-INST(4-8).EQ.4) + (I-INST(4-8).EQ.6) + (I-INST(4-6).EQ.3) + (I-INST(4-7).EQ.OA) + (I-INST(4-7).EQ.8) + (I-INST(4-8).EQ.018) + (I-INST(4-8).EQ.01A) + (I-INST(4-7).EQ.OE)) + BIT4 + SDO & ((I-INST(5-7).EQ.7) + (I-INST(4-8).EQ.015) + (I-INST(4-6).EQ.7)) SHORT VALUE IMMEDIATE INSTRUCTIONS SI = (I-INST(0).EQ.0) & (RLBP.NEQ.O) & (I-INST(4-7).GT.OB) IMO INSTRUCTIONS THAT USE B REG IN E-UNIT 2-6 (LDB, LAB, STB, SWB) EBIMO = (I-INST(0-3).GT.8) & ((I-INST(4-8).EQ.019) + (I-INST(4-8).EQ.017) + (I-INST(4-8).EQ.01D) + (I-INST(4-8).EQ.01F)) LEV INSTRUCTION LEV = SO & (I-INST(4-8).EQ.01C) INC AND DEC INSTRUCTIONS INCDEC = SO & ((I-INST(4-8).EQ.011) + (I-INST (4-8) .EQ 015)) MLV OR MLVK INSTRUCTION MLV = I-INST(6-7).EQ.3 EXTENDED INTEGER SINGLE OPERAND INSTRUCTIONS ESO = (I-INST(0-3).EQ.8) & (I-INST(4-8).NLT.018) & (I-INST(4-8).NEQ.01B) & (I-INST(4-8).NGT.01E) EII SO THAT USE OVERFLOW & DOES NOT STOP PIPELINE: KINC, KDEC, KNEG, KNEGB INSTRUCTIONS ESOV = ESO & (I-INST(6-7).LT.3) & (I-INST(6-8).NEQ.1) EII SHORT VALUE IMMEDIATE INSTRUCTIONS ESI = EBK & (I-INST(8).EQ.1) EXTENDED INTEGER DOUBLE OPERAND INSTRUCTIONS EDO = (I-INST(0-3).GT.8) & (I-INST(4-7).NLT.4) EXTENDED INTEGER INSTRUCTION (EII) INSTR WITH IN-LINE MASK DOUBLEWORD EMSK = (I-INST(0).EQ.1) & (RLBP.NEQ.0) & (I-INST(4-8) .EQ.OF) WHERE RLBP = I-INST (1-3) EII INSTRUCTIONS EXECUTED IN E-UNIT 2-6 THE INSTRUCTION INCLUDES A REGISTER ADDRESS SYLLABLE (RAS) OR AN (IMO) (KDIV, KMUL, KMULP, KDIVP INSTRUCTIONS) EEII = KDIV + KMUL + KDIVP + KMULP KDIV = (I-INST(0).EQ.1) & (RLBP.NEQ.0) & (I-INST(4-8) .EQ.017) KMUL = (I-INST(O).EQ.1) & (RLBP.NEQ.0) & (I-INST(4-8) .EQ.01F) KDIVP = (I-INST(0) & (RLBP.NEQ.0) & (I-INST(4-8) .EQ.01C) KMULP = (I-INST(0).EQ.1) & (RLBP.NEQ.0) & (I-INST(4-8) .EQ.01E) EII1 = I-INST(9-15).EQ.06C EII23 = I-INST(9-15).EQ.07C AS3EII45 = I-INST(9-15).EQ.058 RAS = (I-INST(9-11).EQ.5) & (I-INST(12).EQ.0) & (I-INST(13-15).NEQ.0) IMO = I-INST(9-15).EQ.070 KAS = (I-INST(23-28).EQ.01A) & NC ERAS = (I-INST(24-28).EQ.01A) & NC NC = I-INST (29-31).NEQ.0 EII = EII1 + EII23 + AS3EII45 The STALL signal is generated according to the following Boolean equations: STALL = STALL1 + STALLX (external) + EMPTY (no instruction in buffers); STALL1 = LOCK + (LESTOP + RT6A + RT6E) & CRACK + EFULL & EINSTR & CRACK + (STORCNT.EQ.2) & EINSTR & CRACK &^EC-STCOMP + STATE4 & ADONE & ^CPCK & ^GNCK & ^RSCK & ^CSCK + RTV02 + RTV05 + RTV06 + RTV12 + RTV13 + RTV14 + RTV16 + ISTL + CRACK & (SCB & RE-DONE1-E +LAOUT + LEOUT) + (RINT + RUN-OUT) & CRACK. The ISTATE signals are generated according to the following case statements: The STRING POINTER is updated according to the following "If" statements: The remote descriptor load signal RDDLD is generated by A-unit 20-4 according to the following Boolean equation: The I-NXTCK strobe signal, which accompanies the second and following descriptors, is generated by the Boolean equation: where CPCK, CSCK, RSCK and GNCK are generated by the A-unit firmware control store bits for indicating when the next descriptor is to be cracked by the I-unit for commercial, I/O and generic instructions. It will be obvious to those skilled in the art that many changes may be made to the preferred embodiment of the present invention without departing from its teachings. For example, different states and different instruction sets may be used. Other changes will be readily apparent to those skilled in the art.

Claims: Instruction control apparatus for a pipeline processor comprising a plurality of serially coupled stages (20-2, 20-4, 20-6) for performing different operations in the execution of an instruction, the instructions being of a first and of a second type are received in succession by the first stage (20-2), and addresses being generated from said instructions by the second stage of said plurality of stages, comprising: an instruction decoder (20-250) for decoding the fetched instructions and for generating a plurality of signals in response to each instruction which signals are characteristic for the type of instruction, said decoder (20-250) comprising: a control state means (20-290) for operating in a plurality of different machine states which are determined, in part, by said plurality of signals, said control state means (20-290) generating at any time one of a plurality of different machine state control signals (ISTATE ⊘ .... ISTATE7) which represent the current state of operation of said control state means (20-290); characterized in that said first type of instructions are branch instructions of either a first class comprising unconditional branch instructions with a small displacement and trace trap disabled or of a second class comprising all other branch instructions which two classes of branch instructions are processed differently, the first class of said branch instructions being executed by the first stage (20-2) of the pipeline, and the second class of said branch instructions being executed by both the first (20-2) and the second (20-4) stage of said pipeline; said control state means (20-290) are switched in response to said plurality of signals received from said instruction decoder (20-250) in the case of a second type instruction from a first to a fourth machine state to effect the decoding of said second type instruction, and from said fourth to a fifth machine state to effect the decoding of a predetermined second type instruction by said first (20-2) or second ones (20-4 or 20-6) of said stages in which said second one of said stages (20-4 or 20-6) fetches other portions of said predetermined instruction to effect their decoding in said first stage (20-2); and said machine state control signals (ISTATE ⊘ .... ISTATE 7) are selectively applied to said first stage (20-2) and to a second one (20-4 and/or 20-6) of said pipeline stages for completing the execution of said instruction. The apparatus of claim 1, characterized in that it comprises buffer storage means (20-252, 20-253) coupled to the instruction cache unit (60-2) which is associated with said first stage (20-2), said buffer storage means having first and second string buffers (SBA⊘-SBA7; SBB⊘-SBB7) and a string pointer for designating which of said string buffers is currently in use. The apparatus of claim 2, characterized in that said control state means (20-290) are capable of toggling said string pointer for enabling said other portions of said predetermined instruction fetched from a remote memory location to be loaded into the string buffer currently not in use for decoding. The apparatus of claim 1, characterized in that said plurality of signals is generated as a function of instruction type and size enabling instruction decoding and execution of certain types of instructions to be completed jointly by said first (20-2) and second ones (20-4 or 20-6) of said stages and, for increased performance, independently by said first (20-2) and second ones (20-4 or 20-6) of said stages. The apparatus of claim 1, characterized in that an instruction is decoded while said control state means (20-290) is in a first one (ISTATE ⊘) of said machine states. The apparatus of claim 1, characterized in that said control state means (20-290) in response to a decoded branch instruction is switched from said first one of said machine states to second and third ones of said machine states, respectively, for causing said first and second ones of said stages (20-2, 20-4) to execute said different operations which complete the execution of branch instructions. The apparatus of claim 6, wherein said different operations executed by the first one (20-2) of said stages correspond to executing said first class of branch instructions only when said control state means (20-290) is in said second state and said different operations executed by said second one (20-4) of said stages correspond to executing said second class of branch instructions when in said third state. A method for controlling the execution of a plurality of different types of instructions of an instruction set in a pipelined mode of operation by a plurality of serially coupled stages (20-2, 20-4, 20-6) of a pipeline processor, each stage for performing a different operation on each instruction received by said processor, said successively received instructions being of a first and of a second type, wherein said first type instructions are branch instructions of either a first class or a second class, and addresses being generated from said instructions by the second stage of said plurality of stages, characterized by processing the two classes of branch instructions differently, said first class of said branch instructions comprising unconditional branch instructions with a small displacement and trace trap disabled and being executed by said first stage (20-2) of the pipeline, and said second class of said branch instructions comprising all other branch instructions and being executed by both the first (20-2) and the second (20-4) stage of the pipeline; in response to a plurality of signals received from an instruction decoder in the case of a second type instruction, switching a control state means (20-290) from a first to a fourth machine state to effect the decoding of said second type instruction, and switching said control state means from said fourth to a fifth machine state to effect the decoding of a predetermined second type instruction by said first (20-2) or second ones (20-4 or 20-6) of said stages, and fetching other portions of said predetermined instruction by said second one of said stages (20-4) to effect their decoding in said first stage (20-2); whereupon machine state control signals are selectively applied to said first stage (20-2) and to a second one of said stages (20-4 or 20-6) for completing the execution of said second type instruction. The method of claim 8, characterized by performing the decoding of each instruction of said instruction set by said first one of said stages (20-2) when operating in a first one of said machine states.

Inventors: SHEN JIAN-KUO, STAPLIN DEBORAH K, SHEN, JIAN-KUO, STAPLIN, DEBORAH K
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS INC.
Application year: 1990
Main classification: G06F9
IPC codes: G06F9