Integrated circuit optoelectronic toggle flip-flop

Abstract: A pulse converter includes a set-reset flip/flop (10), having a pair of cross-coupled switching devices such as transistors (Q₁, Q₂) or logic gates (G₁, G₂). The circuit operates by coupling pulses of optical radiation to each of the devices for causing the devices to alternately toggle between an on-state and an off-state. Optical inputting devices such as photodiodes or photoconductors, or the gates of FET transistors themselves, are integrally formed upon a common substrate with the switching devices for minimizing stray inductive and capacitive reactances to substantially eliminate temporal jitter in an electrical output signal. A pulsed laser source and a fiber optic or optical waveguide provide non-overlapping optical pulses to each of the switching devices. In accordance with one embodiment each of the switching devices(Q₁, Q₂) is a GaAs MESFET device having a gate terminal comprised of a substantially transparent layer of electrical conductor having an interdigitated geometry and an overlying anti-reflection coating.

Description: This invention relates generally to optoelectronic devices and, in particular, to a high-speed, low-jitter toggle Flip-Flop (F/F) device coupled to an optical pulse source for converting an optical pulse into electrical signals. This application is related to the commonly assigned copending European Patent Application EP 90 107 579.6. BACKGROUND OF THE INVENTION: The electrical transmission of fast timing signals introduces timing skew problems resulting from the limited bandwidth associated with the transmission and reception of the electrical signals through conventional electrical cables and transmission lines. One especially deleterious effect of the limited bandwidth is a degradation of fast risetime pulses. As a result, a variation in pulse receiver sensitivity or threshold causes an uncertainty or jitter as to an actual time of the arrival of electrical pulse. If the electrical pulse is being employed as a timing signal in, for example, a high-speed data processing system the presence of pulse jitter is especially detrimental. Fig. 1 illustrates a simplified diagram of a conventional toggle circuit constructed as a set-reset flip-flop (SR F/F). The SR F/F includes two transistors Q A and Q B interconnected in a cross-coupled manner as shown. Each transistor is further coupled to a source of operating power (V dd ) through an associated load resistance R A and R B . In operation an electrical pulse to INPUT A sets OUTPUT logically HIGH, while an electrical pulse to INPUT B resets the OUTPUT logically LOW. The complementary signal OUTPUT is LOW when OUTPUT is HIGH and vice versa. One advantage of such a SR F/F circuit is that the output is always in a known logical state, as is important in the clocking of a computer system. That is, the OUTPUT signal may be employed as a clocking signal for logic circuitry of a computer system. However, as was previously stated the electrical transmission of fast timing signals introduces timing skew problems resulting from the limited bandwidth associated with the transmission and reception of the electrical signals through conventional electrical cables and transmission lines. That is, if the electrical pulse signals coupled to INPUT A and INPUT B are transmitted through conventional electrical signal transmission means there is a limitation on an upper useable frequency that can be provided to the SR F/F before the degradation of output pulses and increased output jitter become unacceptable. A problem is created if this upper usable frequency is below a frequency at which it is desired to clock associated logic circuits. One proposed solution to this problem involves transmitting the input pulses as an optical signal instead of an electrical signal. For example, due to the inherently much wider bandwidth of an optical fiber the transmission of a fast rise time optical pulse through the fiber occurs without significant signal degradation. However, a problem is created when it is required to convert the optical pulse into an electrical signal for interfacing to logic circuits such as the SR F/F in that optoelectronic circuits generally include electrical switching circuitry coupled to an optical receiver. The receiver typically includes a photosensor followed by several gain stages with output of the gain stages being applied to the associated switching circuitry. A problem with this conventional arrangement relates to the propagation delay between a time light is incident upon the photosensor and a time at which the switching circuit responds by changing state. Another problem relates to temporal jitter resulting from uncertainty in the propagation delay produced by the gain stages proceeding the logic circuitry. In U.S. Patent 3,686,645, entitled "Charge Storage Flip-Flop" and issued August 22, 1972, Brojdo teaches a semiconductor memory array using a pair of bipolar transistors arranged as a F/F wherein a base of each transistor is connected to a high impedance when a power supply voltage is removed. As the high impedance forces slow decay of charge stored in the transistors, the state of the F/F can be maintained by a pulsed power supply, thereby reducing the average power dissipation of the F/F. Using the photosensitive nature of the transistors, the memory can be written optically by photogenerating charge in the base of one of the transistors, thereby unbalancing the transistors. A laser is employed to address a hologram for providing a desired light pattern for illuminating the memory array. This device specifically uses the low speed nature of the high impedance circuits to integrate the optical signals being applied. Thus, although a F/F circuit configuration is used the application and nature of operation do not address the problem converting optical pulses into fast rise-time, low jitter electrical logic signals. In U.S. Patent 4,023,887, entitled "Optical Communication, Switching and Control Apparatus and Systems and Modular Electro-optical Logic Circuits, and Applications thereof" and issued May 17, 1977, Speers discloses optical communication, switching and control apparatus and system, including modular electro-optical logic circuits. An optical F/F depicted in Figs. 38a and 38b and described at Col. 23, lines 3-53 has one optical input and one optical output, and functions basically an optical "repeater" amplifier. It is noted that Speers teaches a binary device wherein the output frequency is one half of the input frequency and individual pulse timing is not preserved. This device is not believed to be suitable for fast rise-time/fall-time, low jitter applications. A fiber-optic flip-flop receiver of the present type is known from IBM Technical Disclosure Bulletin Vol 25 No 7B Dec 82. pp 3887-3888. The following U.S. Paten, No ts are noted of being of general interest. U.S. Patent 4,223,330, entitled "Solid-State Imaging Device", describes a solid-state image pickup device for use in a TV camera and the like. U.S. Patent 4,295,058, entitled "Radiant Energy Activated Semiconductor Switch", describes various power switching circuits using a light sensor such as photodiode coupled to a gate of a depletion-mode FET. U.S. Patent 4,390,790, entitled "Solid State Optically Coupled Electrical Power Switch", relates to optically isolated switching devices such as solid-state relays for power switching or analog switches for signal switching. U.S. Patent 4,521,888, entitled "Semiconductor Device Integrating a Laser and a Transistor", teaches an integrated semiconductor device including a diode laser and a transistor for modulating the laser. U.S. Patent 4,739,306, entitled "Calibrated-Weight Balance and an Analog-to-Digital Converter in which the Balance is Employed", discloses a calibrated-weight balance for the construction of very- high-speed analog- to - digital converters (ADC). The circuit includes a multivibrator comprising cross- coupled FETs 15 and 16. However, this patent does not disclose the provision of optical inputs for driving the multivibrator. Optical switched flip flops are also known from EP- A- 0 345 494 and US- A- 3 624 419. In particular the EP- A- 345 494 discloses a memory cell comprising a pair of cross-coupled switching means fabricated on a substrate and means for receiving pulses of optical radiation integrally formed on the substrate with each of the switching means comprising a first optical receiver and a second optical receiver, each being coupled to an input of an associated one of the switching means for causing the switching means to alternately toggle between an on state and an off state. However, no one of these teaches, that one of these memory cells can be advantageously used to create a low jitter toggle device for transforming optical pulses to electrical pulses. Those memory cells are usually optical written and read out. The problem of the invention is, to provide an optoelectronic pulse converter for converting an optical pulse into an electrical pulse having a fast risetime and a minimum of timing uncertainty. Unexpectedly the solution was solved not by improving circuits according to the state of the art mentioned, that output electrical pulses. Instead of this, a memory cell according to EP- A- 0 345 494 was used. The adaptation of the memory cell to the desired device for converting optical pulses to electrical pulses is specified in present claim 1. The dependent claims contain technical teaching for further improvements of such a structure. The invention also meets the following objects: It provides a timing generation circuit that provides for the transmission of optical pulses of ultrafast risetime through extremely high- bandwidth optical fibers and which further converts these optical pulses into an electrical timing signal having leading and trailing edges exhibiting minimal timing uncertainty. A further object of the invention is met in providing clock generation circuitry for a high-speed, short cycle time data processor that employs the transmission of optical clock synchronization pulses of ultrafast risetime through extremely high- bandwidth optical fibers and which further converts these optical pulses into an electrical clock signal having a minimum pulse skew. The device according to the invention operates as a pulse converter and converts optical pulses to electrical pulses. The pulse converter includes a set-reset flip/flop, or OPTOGLE, having a pair of cross-coupled switching devices such as transistors or logic gates. The converter operates by coupling pulses of optical radiation to each of the switching devices for causing the switching devices to alternately toggle between an on-state and an off-state. Optical inputting devices such as photodiodes or photoconductors, or the gates of FET transistors themselves, are integrally formed upon a common substrate with the switching devices for minimizing stray inductive and capacitive reactances to substantially eliminate temporal jitter in an electrical output signal. A pulsed laser source and a fiber optic or optical waveguide provide non-overlapping optical pulses to each of the switching devices. In accordance with one embodiment each of the switching devices is a GaAs MESFET device having a gate terminal comprised of a substantially transparent layer of electrical conductor having an interdigitated geometry and an overlying anti-reflection (AR) coating. In this embodiment the transistors are each constructed of a semiconductor material having a characteristic energy bandgap for absorbing the optical pulse and generating sufficient charge carriers therefrom to induce a current flow though the transistor. The semiconductor material may be comprised of Group III-V material, of silicon, of other Group IV materials such as germanium or of combinations of these materials. BRIEF DESCRIPTION OF THE DRAWINGS The above set forth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention when read in conjunction with the attached Drawing, wherein: Fig. 1 is a schematic diagram of a conventional two-input, two-output toggle circuit implemented as set-reset F/F; Fig. 2 is a schematic diagram of a prior art toggle circuit also implemented as set-reset F/F but which includes first and second optical inputs for changing the state of the F/F; Fig. 3 illustrates the illumination of an inter-digitated gate of a GaAs MESFET with an optical input signal for changing the state of the set-reset F/F of which the MESFET is a part; Fig. 4 is a block diagram illustrating experimental apparatus for coupling high speed optical pulses to the optical toggle circuit of the invention; Fig. 5 illustrates graphically an output electrical pulse of the optical toggle circuit in response to an input optical pulse, the x-axis divisions each indicating 500 picoseconds (500 X 10 -12 sec.); Fig. 6 illustrates graphically the OUTPUT signal changing state in response to the optical pulses applied to OPTICAL INPUTs A and B; Fig. 7a-7d illustrate various methods for coupling optical pulses to inputs of the optical toggle circuit; Fig. 8a is a schematic diagram of a prior art toggle circuit implemented as a set-reset F/F and including integrated photodiodes for coupling first and the second optical inputs to associated switching transistors for changing the state of the F/F; Fig. 8b is a schematic diagram of a toggle circuit implemented as a set-reset F/F and including integrated photoconductors for coupling first and the second optical inputs to associated switching transistors for changing the state of the F/F; and Fig. 9 is a schematic diagram of a toggle circuit implemented as a set-reset F/F including integrated photodiodes for coupling the optical inputs and further incorporating cross-coupled NOR-gate function devices in place of cross-coupled switching transistors. DETAILED DESCRIPTION OF THE INVENTION Referring now to Fig. 2 there is shown a conventional SR F/F known from EP-A-0 345 494. The SR F/F is an optically-toggled device and is referred to herein as an OPTOGLE 10. OPTOGLE 10 is constructed in some respects in a similar manner to the circuit of Fig. 1. OPTOGLE 10 includes two transistors Q 1 and Q 2 having their respective gate terminals interconnected in a cross-coupled manner as shown. Each transistor further has a drain terminal coupled to a source of operating power (V dd ) through an associated load, such as a resistance R 1 and R 2 , and a source terminal coupled to a common potential. While the OPTOGLE 10 may be implemented in a wide variety of semiconductor device technologies, in a presently preferred embodiment of the invention the transistors are MESFET devices comprised of semiconductor material having a high electron mobility, such as GaAs. By example, C. Baack et al. in a journal article entitled "GaAs M.E.S.F.E.T.: A High-Speed-Optical Detector", Electron. Lett., 13, 193(1977) report a GaAs MESFET photoresponse of less than 75 picoseconds. In accordance with one embodiment of the invention a region between the source and drain of each MESFET is illuminated with a light pulse of narrow pulse width to achieve a high frequency of operation. Preferably the source of the light is a laser source such as a mode-locked gas laser, a mode-locked solid-state laser, or a gain-switched semiconductor diode laser as disclosed in the aforementioned European Patent Application EP 90 107 579.6. Due to the nature of the optical input, the MESFETs have an equivalent fourth port that is highly isolated from the gate, drain and source terminals. This equivalent fourth port is shown schematically in Fig. 2 and is referred to as OPTICAL INPUT A and OPTICAL INPUT B. If the incident photon energy is greater than the semiconductor bandgap, a large density of charge carriers is generated. These charge carriers produce fast electrical pulses between the drain and source terminals of the FET by means of photoconductivity. In that the optical pulsewidth is preferably much shorter than the charge carrier lifetime, this effect is transient. In general, a risetime of the photoconductive signal is approximately the same as a risetime of the optical pulse while the fall time of the photoconductive signal is a function of the charge carrier lifetime. The photoconductive gain, defined as the number of charge carriers crossing a sample per second divided by the number of photons absorbed per second, is approximately the ratio of optical pulse duration to the transit time of the charge. As a result a large gain may be realized. The light-induced electrical pulse controls the output state of the OPTOGLE 10 in substantially the same manner as the electrical inputs INPUT A and INPUT B, and may be used interchangeably if desired. It should be noted that both electrical and optical inhibit capability is implicit in the circuit in that toggle activity can be inhibited by the application of a long duration pulse, or level, through either the electrical or the optical inputs. In general the transistor gates serve several purposes including providing positive feedback during changes of state and also providing external electrical terminals. As shown in Fig. 6 an optical pulse applied to OPTICAL INPUT A sets OUTPUT logically HIGH, while an optical pulse applied to OPTICAL INPUT B resets the OUTPUT logically LOW. As was stated, electrical pulses could be substituted for some of the optical pulses or could be used to inhibit the operation of the optical pulses. The optical pulses may be derived from separate sources or from a common source. If the latter approach is employed one of the pulses is passed through an optical delay device, such as longer path length optical fiber, so that the second pulse is temporally offset from the first pulse by a desired amount. The amount of temporal offset affects the output electrical signal duty cycle as shown. One significant advantage of directly coupling the light pulse to the gates of the transistors of the OPTOGLE 10 is the resulting simplicity of the circuit. That is, the MESFET itself functions as a photosensor and, with no signal amplifying or conditioning stage(s) required as with conventional types of optoelectronic devices, the propagation delay and the temporal jitter is minimized. Thus, the OPTOGLE 10 significantly reduces pulse skew characteristics which are especially critical in data processing clock signal distribution. The operation of the OPTOGLE 10 has been experimentally demonstrated with commercially available GaAs digital integrated circuits constructed with depletion-mode MESFETs. Fig. 3 illustrates an enlarged view of a portion of an interdigitated MESFET. In this device the gate electrode 12a is disposed between the source electrode 12b and the drain electrode 12c. An illuminating laser beam spot 14 has a diameter of approximately 30 microns. The interdigitated geometry of the gate electrode 12a beneficially reduces shadow effects of the electrodes, thus improving light coupling, while also providing for a low interelectrode capacitance. The provision of an anti-reflection (AR)-coating 18 over the gate electrode 12a further improves light coupling efficiency, the AR coating being optimized for the wavelength of the incident optical radiation. Coupling efficiency may be further improved with transistor gates constructed of semitransparent electrodes such as electrodes comprised of a relatively thin layer of metal having a thickness of approximately 10 nanometers. In accordance with an aspect of the invention the MESFETs Q1 and Q2, associated electrodes 12a, 12b, 12c and other components are formed on a common substrate 16. The characteristics of the GaAs OPTOGLE 10 were determined with the experimental apparatus 20 schematically shown in Fig. 4. The apparatus 20 includes a pair of optical fibers 22a and 22b each of which conveys light from an associated source 24a and 24b. Sources 24a and 24b are preferably each a coherent source. An output end of each the fibers 22 is coupled to a collimating lens 26 from which the light energy is relayed to a dichroic mirror 28. Optically coupled to one side of the dichroic mirror 28 is a focusing lens 30 for focusing the outputs of the sources 24 onto respective gate electrodes of an integrated circuit device 32 containing the OPTOGLE 10. Optically coupled to the opposite side of the dichroic mirror 28 is a beamsplitter 34. An illuminator 36 for camera 40 provides illumination through a collimating lens 38. Camera 40 views the scene through a focusing lens 42. This arrangement permits the optical stimulation of the OPTOGLE 10 and the simultaneous viewing by the camera 40. Fig. 5 illustrates the OUTPUT signal of the OPTOGLE 10. Each time division along the x-axis represents 500 picoseconds. The input pulse is the input electrical pulse applied to a laser diode source in order to generate the optical pulse that was applied to the OPTOGLE 10. Suitable sources of radiation include mode-locked Nd:Yag lasers, Nd:YLF lasers, AlGaAs any source capable of generating ultrashort, fast risetime, high-peak-power optical pulses at a high repetition rate. The wavelength of the pulse is preferably within a range of wavelengths strongly absorbed by the semiconductor material. For example, both GaAs and silicon strongly absorb visible and near-infrared radiation. With known types of optical pulse compression techniques using optical fibers and gratings a duration of the optical pulses can be reduced to the subpicosecond range. The GaAs MESFET-based OPTOGLE 10, although not entirely optimized for such operation, has been found to require a pulse energy of 4 pJoules. As an example, operation at 250 MHz requires an average optical power of 1mWatt at each of the two OPTOGLE 10 receiving sites. Thus, a mode-locked laser with average output power of 1 Watt has sufficient power to simultaneously address approximately 500 of the OPTOGLE pulse converters. For example, the gate electrodes of two MESFET devices were illuminated with laser beam pulses having an approximately 30 micron spot size. The light pulses were produced by injecting a train of 250 picosecond electrical pulses into an AlGaAs diode laser having a nominal wavelength of 780 nanometers. The optical pulses were provided through fiber optics as depicted in Fig. 4. In addition to the photo-FET implementation described in detail above the SR F/F may be implemented in various technologies. By example, Fig. 8a shows a FET flip-flop with photodiode inputs. A circuit of this type is known from US-A-3 624 419. Preferably, the photodiodes D1 and D2 are integrated into the same substrate as the FETs Q1 and Q2 and the other components of the SR F/F. One important advantage of this technique is the reduction of required circuit dimensions with a corresponding reduction of stray circuit reactances, both capacitive and inductive, at the photosensor leads. As a result optical input pulses are efficiently received and circuit speeds are very fast. Of course, any of the SR F/F embodiments may implemented with bipolar transistor technology, instead of the FET technology shown. Also, the SR F/F may be implemented by more general logic devices, such as the NOR gates (G1 and G2) shown in Fig. 9. This embodiment also includes integrally formed photodiodes D1 and D2 and is implemented as an integrated photosensor/logic circuit combination to achieve fast switching times. If desired, the use of photovoltaic optical sensors such as the photodiodes D1 and D2 may be replaced, as in Fig. 8b, by integrated photoconductive sensors (S1 and S2). Such devices, such as those constructed of Group III-V, silicon and other materials exhibit very fast (picosecond) response times and are well suited for this use. In all embodiments of the invention an important aspect is the integration of the photosensor devices with the cross-coupled switching circuitry, with no additional amplifier circuits being required or deployed, thereby significantly reducing temporal jitter in the output pulse stream. It should be noted that for application of the OPTOGLE to a data processor that the optical pulses may be applied, as depicted in Figs. 7a-7d, through optical fibers 50a and 50b having flat, polished ends (Fig. 7a) or integral focusing optics (Fig. 7b). In these two embodiments the fiber 50a and 50b ends are bonded or otherwise fixedly coupled to the appropriate electrode region of each of the transistors Q1 and Q2 or to the associated one of the photodiodes D1 or D2 or photoconductors S1 or S2. Either single mode or multi-mode optical fibers are suitable for this task. Fig. 7c illustrates the fibers 50a and 50b having a beveled end and coupled to a v-block. The beveled fiber ends serve as reflectors for coupling the optical inputs to, for example, the photodetectors D1 and D2. Fig. 7d illustrates an optical waveguide 54 fabricated upon the substrate 16 and having an end in optical communication with the SR F/F for coupling optical pulses thereto. It is also within the scope of the invention to convey the optical radiation to the transistors by integrating, for example, a plurality of AlGaAs laser devices onto an integrated circuit device with the OPTOGLE 10. OPTOGLEs may be constructed with silicon FET technology although such devices exhibit a slower response due to relatively lower carrier mobility than similar devices constructed with GaAs and/or other Group III-V materials such as InP. By example and referring to the embodiment of Figs. 2 and 3 with GaAs material electron mobility is approximately 8600cm 2 /Vs and electron transit time is approximately 15 picoseconds for an electrode 12 spacing of five microns and an applied voltage of two volts. The gain is approximately 10 for laser pulses of 150 picoseconds in duration. Modulation of the gate 12a voltage during operation also results in a current amplification.

Claims: High speed clock generator for transmission purposes to interface optical signals to logical circuits : comprising: a circuit (10) as known from memory cells to convert optical pulses to electrical pulses, the circuit (10) comprising a pair of cross-coupled switching means fabricated on a substrate (16) and receiving means for receiving pulses of optical radiation integrally formed on the substrate (16) with each of the switching means comprising a first optical receiver (D1, Q1) and a second optical receiver (D2, Q2) , each being coupled to an input of an associated one of the switching means for causing the switching means to alternately toggle between an on state and an off state, the clock generator further including fiber optic (50a, 50b) and/or optical waveguide (54) means to couple the optical pulses to the receiving means, wherein these receiving means comprise a mesfet for receiving the light, the mesfet having a gate terminal (12a) with an interdigitated geometry to improve light coupling, and an output terminal (Output) at one of the switching means, to provide the converted electrical pulses. High speed clock generator according to claim 1, characterized in, that the optical pulse is coupled to the first optical receiver (D1, Q1) and delayed by an optical delay device before coupling it also to a second optical receiver (D2, Q2). High speed clock generator according to claims 1 or 2, characterized in, that fibers (50a, 50b) are provided to couple the optical pulse to the receiving means, the fibers (50a, 50b) having a beveled end and are coupled by a V-block to the substrate. High speed clock generator according to claims 1 or 2, characterized in, that fibers (50a, 50b) are provided to couple the optical pulse to the receiving means, the fibers (50a, 50b) having flat polished ends or integral focus optics. High speed clock generator according to claim 4, characterized in, that the fibers (50a, 50b) are bonded to the first and second optical receivers (D1, D2, Q1, Q2) in the receiving means. High speed clock generator according to claim 1 or 2, characterized in, that the receiving means are coupled to a pulsed laser source through an intervening optical waveguide means (54) being integrally formed upon the substrate (16) . High speed clock generator according to anyone of claims 1 to 6, characterized in, that the switching means comprise a transistor device (Q1, Q2) fabricated from a semiconductor material having a characteristic bandgap for absorbing the optical pulse and generate sufficient charge carriers therefrom to induce a current flow through the transistor. High speed clock generator according to anyone of claims 1 to 7, characterized in, that the substrate (16) is a semiconductor material chosen from the group comprising III-V material and silicon. High speed clock generator according to anyone of claims 1 to 8, characterized in, that the switching means is a field effect transistor (Q1, Q2) fabricated from a semiconductor material having a characteristic energy bandgap for absorbing the optical pulse and generating sufficient charge carriers to induce current flow through the field effect transistor (Q1, Q2) and wherein the receiving means provide a gate terminal region of the field effect transistor (Q1, Q2). High speed clock generator according to claim 9, characterized in, that the gate terminal (12a) is disposed adjacent to an anti-reflection coating (18) . High speed clock generator according to anyone of claims 1 to 8, characterized in, that the switching means is comprised of a field effect transistor (Q1, Q2) device, wherein the receiving means is comprised of a photovoltaic or photoconductive device (D1, D2, S1, S2) coupled to a gate terminal of the field effect transistor (Q1, Q2) device. High speed clock generator according to anyone of claims 1 to 8, characterized in, that the switching means comprise a logical element (G1, G2), preferably having at least two inputs and operating in accordance with a NOR function . High speed clock generator according to claims 1 to 12, characterized by first and second transistor means (Q1, Q2) each having an output terminal coupled to an associated load (R1, R2) and a control terminal, the first and second transistor means being cross-coupled such that the control terminal of one of the transistor means is coupled to the output terminal of the other transistor means, wherein the first and second transistor means are fabricated upon a common substrate and means for inputting pulses of optical radiation to the control terminal of the first transistor means and for inputting pulses of optical radiation to the control terminal of the second transistor means (Q2), wherein the inputting means is comprised of a first photodiode (D1) or photoconductor (S1) coupled to the control terminal of the first transistor means (Q1) and a second photodiode (D2) or photoconductor (S2) coupled to the control terminal of the second transistor means (Q2) and wherein the inputting means further is comprised of at least a portion of the control terminal of each of the first and the second transistor means. High speed clock generator according to anyone of claims 1 to 13, characterized in, that the switching means include each a bipolar transistor or a field effect transistor comprised of silicon, germanium, group III-V material or combinations thereof.

Inventors: BUNSEN FAN, RICKY ALLEN RAND, BUNSEN, FAN, RICKY, ALLEN RAND
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: H03K3
IPC codes: H03K3, H03K17