Power saving drive circuit for TFEL devices

Abstract: A power saving voltage drive circuit for a TFEL edge emitter device of the type having a plurality of pixels, with each pixel having a first terminal and all pixels on a device sharing a common second terminal, is comprised of a demultiplexing channel driver being select­ ively connected to the second terminal. A bidirectional switch selectively connects one of the first terminals to a source of voltage thereby enabling current to flow into and out of the pixel. A transformer has a primary winding connected between the first terminal and the bidirectional switch for enabling the pixel to charge to an operating voltage, and a secondary winding connected in series with a diode across the source voltage and ground for limiting the value of that operating voltage. The bidirectional switch is operated so that a substantial portion of the energy used to charge the pixel is returned to the source of voltage at the end of the pulse duration.

Description: The present invention is directed to drive circuits for thin film electroluminescent (TFEL) edge emitter devices. US-A-4 707 692 discloses a drive circuit according to the preamble of claims 1, 8 and 10. TFEL elements emit light when a changing electric field is present across the element. TFEL elements are thin film structures comprised, for example, of a phosphor layer situated between dielectric composite layers and electrodes located on the outside of the dielectric layers. Examples of the structure of TFEL elements are found in US-A-4,535,341, US-A-4,734,723 and European Patent Application EP-A-369755 published on 23.05.90. TFEL edge emitted devices are typically configured in arrays utilizing multiplexed common drive circuitry to control many TFEL devices from a single source. A common driver circuit generates the peak to peak voltage necessary to illuminate the TFEL edge emitter device, and a demultiplexing channel driver directs that signal to the individual devices are desired. Work is being performed to improve edge emitter structures so that fewer physical connections between the individual pixels carried on each device and the driver circuitry are required. An example of such work is European Patent Application EP-A-395 327 published on 31.10.90. TFEL devices require large operating voltages on the order of five hundred volts peak to peak. Not only is a high voltage required for operating the device, but the voltage must be precisely regulated to obtain consistent, reproducible, light emission from the TFEL device. Presently, the common driver circuits use current steering transistors to charge the capacitive TFEL load. The voltage stored in the TFEL load is then discharged by dissipating the power through resistive circuitry. See, for example, Fig 6 of the aforementioned European Patent Application EP-A-395 327 and the accompanying description thereof. As the applications for TFEL devices increase, and with the potential for portable applications, the need exists for an efficient common drive circuit. In addition to achieving efficient use of power supply, the drive circuit must also be capable of precisely regulating the applied voltage whenever the supply voltage is not precisely controlled. The present invention consists in a power saving voltage drive circuit for a thin film electroluminescent (TFEL) edge emitter device of the type having a plurality of pixels, each having a first terminal and all pixels sharing a common second terminal, said drive circuit comprising demultiplexing means selectively connectable to the second terminal, characterized by a transformer having a primary winding and a secondary winding, said secondary winding inductively coupled to the primary winding; a diode connected in series with the secondary winding between a voltage source and a ground for limiting the value of operating voltage; bidirectional switch means connected in series with the primary winding; and steering means for selectively connecting one of the first terminals to said voltage source through said primary winding and said bidirectional switch means thereby enabling current to flow into the pixel to charge the pixel to an operating voltage and enabling current to flow out of the pixel back to the voltage source. The present invention also consists in a method of multiplexed thin film electroluminescent (TFEL) edge emitter array and power saving drive circuit therefor, comprising a plurality of TFEL edge emitter devices, each device having a plurality of pixels, each pixel of each device having a first terminal and sharing a common second terminal with the other pixels of that device, characterized by transformer means having a primary and secondary winding; bidirectional switch means connected in series with said primary winding; steering means for selectively connecting certain of said first terminals through said primary winding and said bidirectional switch means to a voltage source; diode means connected in series with said secondary winding between said voltage source and ground for limiting the value of an operating voltage; and demultiplexing means selectively connectable to certain of said second terminals of said devices to enable a pixel on the selected device to charge to said operating voltage and discharge from said operating voltage through said bidirectional switch means and said primary winding. The invention also consists in a method of delivering multiplexed power to a thin film electroluminescent (TFEL) edge emitter array of the type constructed of a plurality of TFEL devices each device having a plurality of pixels, each pixel having a first terminal, and all pixels on a device sharing a common second terminal, said method comprising the steps of selectively supplying a data signal to at least one of the second terminals from a demultiplexing driver; and selectively connecting at least one of the first terminals to a source of voltage through a bidirectional switch and a primary winding of a transformer thereby enabling current to flow into the selectively connected pixel to enable the pixel to charge to an operating voltage; characterized by the steps of: inductively coupling a secondary winding of said transformer to said primary winding and a diode, said secondary winding and said diode being connected in series between a voltage source and a ground for limiting the value of the operating voltage; disconnecting said at least one of the first terminals from the voltage source thereby preventing the pixel from discharging; reconnecting said at least one of the first terminals to the voltage source after an appropriate pulse duration to enable current to flow from the charged pixel to the voltage source; disconnecting said at least one of the first terminals from the voltage source after substantially all of the energy stored in the pixel is returned to the voltage source; and removing the data signal from said at least one of the second terminals. The circuit and method of the present invention represent a dramatic improvement over the prior art. Experimentally, without circuit optimization, a 66% power saving has been observed. Additionally, due to the particular characteristics of the present invention, the power saving drive circuit automatically stabilizes the operating voltage available to the TFEL devices independently of the characteristics of the TFEL load. Therefore, the present invention achieves uniformity of illumination across TFEL edge emitter array. In order to make the invention more clearly understood, the invention will now be described with reference to the accompanying drawings which are given by way of example and in which: Fig 1 is a schematic representation of a multiplexed, thin film, electroluminescent (TFEL) edge emitter array comprised of a plurality of TFEL edge emitter devices and a power saving drive circuit therefor; Figs 2A through 2D illustrate various signals helpful in understanding the operation of the array and drive circuit illustrated in Fig 1; Fig 3 is a schematic representation of the common driver circuit; Figs 4A through 4I illustrate various signals helpful in understanding the operation of the common driver circuit illustrated in Fig 3; Fig 5 is a simplified representation of a portion of the common driver circuit; Figs 6A through 6E illustrate various signals helpful in understanding the operation of the circuit illustrated in Fig 5; Fig 7 is an electrical schematic of one embodiment of the bidirectional switch illustrated in Fig 5; and Fig 8 is a graph illustrating the power savings achieved by the present invention. Figure 1 is a schematic representation of a multiplexed, thin film, electroluminescent (TFEL) edge emitter array 9 and a power saving drive circuit 10 therefor. The array 9 is made up of a plurality of identical TFEL devices or pixel groups of which three (12, 14 and 16) are shown. Each of the devices 12, 14, 16 is comprised of a plurality of pixels. In the example shown in Fig 1, four pixels 18-21 are illustrated on device 12. Each pixel 18-21 has a first terminal 22-25, respectively. All of the pixels 18-21 of the device 12 share a common second terminal 27. All of the TFEL devices 12, 14 16 comprising the array 9 are constructed in an identical fashion. Thus, for example, the TFEL device 14 has a plurality of pixels 18′-25′, each having a first terminal 22′-25′, respectively, and each sharing a common second terminal 27′. The construction of such TFEL devices 12, 14, 16 is believed to be well known to those of ordinary skill in the art such that no further description of such devices is necessary. Each of the common second terminals 27, 27′, etc. is connected to a channel driver 30. The channel driver 30 is a commercially available combination shift register, latch, driver device, having a plurality of outputs 32, 32′, etc. connected to the common second terminals 27, 27′, etc., respectively. Channel driver 30 has a data input terminal 34 for receiving data from a data bus 35, a clock input terminal 36 for receiving clock pulses from a clock bus 37, a latch input terminal 38 for receiving latching commands from a latch bus 39, and a polarity input terminal 40 for receiving polarity signals from a polarity bus 42. The provision of data, clock pulses, latching instructions, and polarity signals to the channel driver 30 is well known in the art. The reader desiring more information concerning the construction and operation of the channel driver 30 is directed to the aforementioned European Patent Application EP-A-395 327. The drive circuit 10 illustrated in Fig 1 also includes a common driver circuit 41. The common driver circuit 41 has a first output terminal 43 connected to a first bus bar 48, a second output terminal 44 connected to a second bus bar 49, a third output terminal 45 connected to a third bus bar 50, and a fourth output terminal 46 connected to fourth bus bar 51. Each of the bus bars 48-51 is connected to one of the first terminals of each of the TFEL devices 12, 14, 16. For example, first bus bar 48 is connected to first terminals 23, 23′, etc., second bus bar 49 is connected to first terminals 24, 24′, etc., third bus bar 50 is connected to first terminals 24, 24′, etc., and fourth bus bar 51 is connected to first terminals 25, 25′, etc. In that manner, the common driver circuit 41 can provide power to all of the pixels of each of the TFEL devices. In that manner, the common driver circuit 41 can provide power to all of the pixels of each of the TFEL devices. The common driver circuit 41, when operated in conjunction with the channel driver 30, which acts as a demultiplexer, enables individual pixels to be energized as is known. The construction and operation of the common driver circuit 41 forms an important part of the present invention and will now be described in detail in conjunction with Figs 3, 4A-4I and 6A-6E. Turning to Figure 3, the common driver circuit 41 is illustrated in detail. The circuit to the left of capacitors 53 and 54 provides positive and negative voltage pulses which are then steered by the circuitry to the right of capacitors 53 and 54 such that trilevel signals as shown in Fig 4A are available at output terminal 43, trilevel signals as shown in Fig 4B are available at output terminal 44, trilevel signals as shown in Fig 4C are available at output terminal 45, and similar trilevel signals (not shown) are available at output terminal 46. The circuit to the left of capacitors 53 and 54 is a dual circuit with the top half and bottom half being identically constructed. The top half may be used to provide the positive portion of the trilevel signals while the bottom half may be used to provide the negative portion of the trilevel signals. The operation of the circuitry to the left of capacitors 53 and 54 is described in greater detail in conjunction with Fig 5. In Figure 5, the upper half of the circuit to the left of capacitors 53 and 54, which is responsible for producing the positive portion of the trilevel signal, is illustrated in detail. The circuitry to the right of capacitors 53 and 54 has been simplified and is represented simply by the capacitive load C L . The capacitive load C L is connected to a source of positive voltage V s through the series combination of winding 60 of a transformer 58. A secondary winding 62 of the transformer 58 is series connected with a diode 64 between the positive voltage source V s and ground. The load capacitor C L is connected to ground through the series combination of a resistor 66 and switch 68. The operation of the circuitry shown in Fig 5 will now be described in combination with Figs 6A-6E. At time t 0 in Figure 6D, bidirectional switch 56 is closed. The load capacitor C L begins to charge due to the flow of current i p (shown in Fig 6B) through the inductance of the primary winding 60 of the transformer 68. The load capacitor C L begins to charge as an ordinary LC circuit as shown in Fig 6A. At this time, diode 64 is back biased such that no current i c flows through the secondary or control winding 62 of the transformer 58 as shown in Fig 6C. The current flowing through the primary winding 60 continues to increase until time t 1 when the voltage of the load capacitor C L equals the source voltage V s . Thereafter, the value of the current i begins to decrease as shown in Fig 6B. At time t 2 , the voltage across the load capacitor C L has achieved an operating potential as shown by V op in Fig 6A. As the voltage across the load capacitor C L reaches the operating voltage V op , the voltage V c across the control winding 62 exceeds the source voltage V s resulting in the flow of current i c shown in Fig 6C. That flow of current diverts the energy remaining in the transformer 58 back to the power source thereby limiting the amplitude of the operating voltage V op . At time t 2 , the switch 56 is open as shown in Fig 6D to prevent the discharge of the capacitive load C L . The maximum value of the operating voltage V op is independent of the various in capacitive load characteristics and therefore stable regardless of the number of pixels in the "on" state at any given time. V op is the sum of the voltage across the primary winding, which is determined by the equation for an ideal transformer, and the source voltage V s as follows: V op = (1 + N p /N c )V s where N p equals the number of turns on primary winding 60 and N c equals the number of turns on secondary winding 62. From time t 2 until t 3 , the operating voltage is maintained due to switch 56 being open as shown by figs 6A and 6D. After the desired pulse duration, switch 56 is closed s shown by Fig 6D. That allows the current to flow in the opposite direction from the capacitive load C L as shown in Fig 6B which results in the discharging of the load as shown by Fig 6A. A substantial portion of the energy stored in the capacitive load C L is returned to the source of voltage. However, due to losses in the circuit, C L may not be completely discharged. Therefore, at time t 4 switch 56 is open and switch 68 is closed as shown in Figs 6D and 6E, respectively. When switch 68 is closed, the load capacitor C L is grounded through the resistor 66 thereby allowing the residual energy to be dissipated and the charge on the capacitor reduced to zero as shown in Fig 6A. When the residual energy remaining in the load capacitor C L has been dissipated, the switch 68 is closed at time t 5 as shown in Fig 6E. It is also possible to recover a portion of the residual energy dissipated by resistor 66 although no circuitry is shown in Fig 5 to implement such a recovery. Those of ordinary skill in the art will recognise that from time t 0 to time 5 5 , channel driver 30 is operative to appropriately connect the common second terminal of the pixel being illuminated. As previously discussed, the circuit shown in Fig 5 generates one-half of a cycle of the trilevel peak-to-peak waveform necessary for the illumination of a pixel. For that reason, and as shown in Fig 3, the common driver circuit 41 consists of two circuits of the type shown in Fig 5 operating out of phase, in a complimentary fashion, to generate the necessary trilevel signal. In Fig 3, the components providing the negative half cycle of the trilevel waveform are given like reference numerals and are distinguished by the prime designation. After the positive and negative portions of the trilevel signal are generated, appropriate circuitry is provided to steer those signals to the appropriate output terminals. Such steering circuitry is shown to the right of capacitors 53 and 54 and may be comprised of a sequence decoder 70, responsive to external logic, for operating a plurality of switches 72 through 75. A sequence decoder 70′ for operating a plurality of switches 72′-75′ is similarly provided for the negative portion of the cycle. The switches 72-75 and 72′-75′ are operated by sequence decodes 70 and 70′ respectively, to provide the waveforms illustrated in Figs 4A-4C. At time t 0 , switch 72 is closed as shown in Fig 4D thereby allowing the positive portion of the waveform to be conducted to output terminal 43. All of the other switches are open such that the voltage available at output terminals 44 and 45 is zero as shown in Figs 4B and 4C. At time t 1 switch 72 is open and switch 72′ is closed as shown in Figs 4D and 4E, respectively, thereby allowing the negative half cycle of the waveform to be conducted to output terminal 43. At time t 2 , switch 72′ is open and switch 72 closed thereby allowing another positive half cycle of the waveform to be conducted to output terminal 43. At time t 3 , the positions of the switches are again reversed enabling another negative half cycle to be conducted to the output terminal 43. At time t 4 , switches 73 and 73′ are similarly operated while switches 72, 72′, 74, 74′, etc. remain open. Thus, through appropriate manipulation of the steering switches, the trilevel waveforms shown in Figs 4A-4C appear at output terminals 43-45, respectively. One cycle of the signal shown, for example, in Fig 4A, form time t 0 to time t 2 is approximately thirteen microseconds. Therefore, the bidirectional switch 56, in addition to being capable of conducting current in both directions, must also be capable of extremely rapid switching. One example of a high speed, bidirectional switch, which may be used for switch 56, is illustrated in Fig 7. In Figure 7, switch 56 is comprised of two back-to-back MOSFET transistors 72 and 74, with appropriate blocking diodes 76 and 78, respectively. The gate of the transistor 72 is connected to the junction between a resistor 80 and a capacitor 82 which are connected in series across the voltage source V s . Similarly, the gate of the transistors 74 is connected to the junction between a resistor 84 and a capacitor 86 which are connected in series across the voltage source V s . Appropriate control signals are provided to render one or the other transistors 72, 74 conductive. Also shown in Fig 7 is a MOSFET transistor 88 used for the switch 68. The MOSFET transistors 72 and 74 were used to demonstrate the feasibility of the present invention because such components are cheap and readily available whereas high-speed thyristors and silicon controlled rectifiers (SCRs) are not so readily available. However, those of ordinary skill in the art will recognise that a suitable high-speed, bidirectional switch 56 may also be constructed of a triac, a photo-triac (both of which are bidirectional devices), two back-to-back silicon controlled rectifiers, or two back-to-back photo-silicon controlled rectifiers. Results achieved with the circuit shown in Fig 7 are illustrated in Fig 8. Pertinent data is as follows: the number of primary turns equals twenty; the number of secondary turns equals thirdly-six; pulse repetition rate is fifty microseconds (20 kHz), and the pulse duration period is five microseconds. The value for the parameter D, which is representative of the efficiency of the circuitry, is represented by the following equation: D=(2V s I s T)(C L V op 2 ) where V s = supply voltage in volts I s = supply current in milliamps T = pulse repetition period C L = capacitive value of the load V op = operating voltage In an experiment under conditions similar to those for present edge emitter common drivers, the edge emitter common driver 41 of the present invention, without circuit optimization, dissipated approximately 66% less power than currently used prior art drivers for which the D value is grater than two. Returning now to Figure 1, for TFEL edge emitter arrays 9 where low power consumption is important, a considerable amount of energy can be saved by inhibiting the common driver 41 during periods when all the TFEL devices are in the "off" state. Such a condition can exist in an edge emitter printer-type application during the blank period between lines on a page or during the printing of a gray scale area. Such an energy saving concept is possible because during any burst period, the information for the next burst period is already being supplied form the data source to the channel driver 30. In Fig 2A, the latching signal available on latch bus 39 is illustrated. At the time one burst (n) is being displayed, information for the next burst (n+1) is being serially loaded into the hold devices within channel driver 30. Thus, the composition of the next burst (n+1) is known. If it is determined that all the pixels during the next burst (n+1) will not be required to emit light, then the production of the signal shown in Fig 2B corresponding to that burst can be inhibited. Because the common driver circuit 41 and channel driver 30 operate synchronously, implementation of a common driver 41 disabling circuit can be achieved with minimal modifications. Such a disabling circuit can be constructed a shown in Fig 1 of an OR gate 90 which is responsive to the data on data bus 35. Whenever the data indicates that all of the pixels are to be blank, a signal is provided to a first flip-flop 92, which propagates through a second flip-flop 94, to inhibit the common driver circuit 41. The flip-flops 92 and 94 are reset by the latch signal shown in Fig 2A. In that manner, whenever all of the pixels are to be blank, the common driver circuit 41 is inhibited from producing the trilevel output signal on one of the buses 48-51. That represents a significant power savings. The present invention is also directed to a multiplexed method of delivering power to the TFEL edge emitter array 9 of the type constructed of a plurality of TFEL devices 12, 14 16, wherein each device carries a plurality of pixels 18-21, 18′-21′, etc. Each pixel has a first terminal 22-25, 22′-25′, etc. and all pixels on a device share a common second terminal 27, 27′, etc. The method is comprised of the steps of selectively supplying a data signal to at least one of the second terminals, for example, second terminal 27, from the demultiplexing channel driver 30. At the same time, at least one of the first terminals, for example, first terminal 22, is selectively connected to the source of voltage through the bidirectional switch 56 and primary-winding 60 of the transformer 58, thereby enabling current to flow into the selectively connected pixel, pixel 18. When the pixel 18 has charged substantially to the operating voltage V op , the switch 56 is open thereby preventing the pixel 18 from discharging. After an appropriate pulse duration, the selected first terminal, in this example terminal 22, is reconnected to the source of voltage through bidirectional switch 56 to enable current to flow from the charged pixel to the source of voltage. Thereafter, bidirectional switch 56 is open and the switch 68 is closed thereby grounding the pixel 18 after substantially all of the energy stored to the pixel has been returned tot he source of voltage. Finally, switch 68 is open and the data signal is removed from second terminal 27 by demultiplexing driver 30. The edge emitter common driver 41 of the present invention utilizes reactive circuitry to conserve the energy stored in the TFEL load during charging by redirecting the energy back into the power source when discharging the load instead of dissipating the power through resistive circuitry. Novel operation of the drive circuit 10 to disable the common drive circuit 41 during blank periods enables additional power savings. The power savings achieved by the present invention opens up new applications for TFEL arrays. As such, the present invention represents a substantial advance over the prior art.

Claims: A power saving voltage drive circuit (10) for a thin film electroluminescent (TFEL) edge emitter device (9) of the type having a plurality of pixels (18-21), each having a first terminal (22-25) and all pixels sharing a common second terminal (27), said drive circuit comprising demultiplexing means (30) selectively connectable to the second terminal, characterized by a transformer (58) having a primary winding (60) and a secondary winding (62), said secondary winding inductively coupled to the primary winding; a diode (64) connected in series with the secondary winding between a voltage source and a ground for limiting the value of operating voltage; bidirectional switch means (56) connected in series with the primary winding; and steering means (70) for selectively connecting one of the first terminals to said voltage source through said primary winding and said bidirectional switch means thereby enabling current to flow into the pixel to charge the pixel to an operating voltage and enabling current to flow out of the pixel back to the voltage source. A drive circuit as claimed in claim 1, further characterized by a switch means (68) for grounding the pixel after a substantial portion of the energy stored in the pixel has been returned to the voltage source. A drive circuit as claimed in claim 1, wherein the bidirectional switching means includes first and second transistors (72,74) and first and second diodes (76,78) interconnected such that said first transistor is conductive when said second transistor is nonconductive to enable current to flow into the TFEL device and said first transistor is nonconductive when said second transistor is conductive to enable current to flow out of the TFEL device. A drive circuit as claimed in claim 1, wherein said bidirectional switch means includes a triac. A drive circuit as claimed in claim 1, wherein said bidirectional switch means includes a phototriac. A drive circuit as claimed in claim 1, wherein said bidirectional switch means includes first and second SCR's interconnected such that said first SCR is conductive when said second SCR is nonconductive to enable current to flow into the TFEL device and said first SCR is nonconductive when said second SCR is conductive to enable current to flow out of the TFEL device. A drive circuit as claimed in claim 1, wherein said bidirectional switch means includes first and second photo SCR's interconnected such that said first photo SCR ie conductive when said second photo SCR is nonconductive to enable current to flow into the TFEL device and said first photo SCR is nonconductive when said second photo SCR is conductive to enable current to flow out of the TFEL device. A multiplexed thin film electroluminescent (TFEL) edge emitter array (9) and power saving drive circuit (10) therefor, comprising a plurality of TFEL edge emitter devices (12, 14, 16), each device having a plurality of pixels (18-21), each pixel of each device having a first terminal (22-25) and sharing a common second terminal (27) with the other pixels of that device, characterized by transformer means (58) having a primary (60) and secondary winding (62); bidirectional switch means (56) connected in series with said primary winding; steering means (70) for selectively connecting certain of said first terminals (22-25) through said primary winding (60) and said bidirectional switch means (56) to a voltage source; diode means (64) connected in series with said secondary winding between said voltage source and ground for limiting the value of an operating voltage; and demultiplexing means (30) selectively connectable to certain of said second terminals (27, 27', 27") of said devices (12, 14, 16) to enable a pixel on the selected device to charge to said operating voltage and discharge from said operating voltage through said bidirectional switch means and said primary winding. An array and drive circuit as claimed in claim 8, wherein said operating voltage is determined by the turns ratio of said transformer means and the source voltage. A method of delivering multiplexed power to a thin film electroluminescent (TFEL) edge emitter array (9) of the type constructed of a plurality of TFEL devices (12, 14, 16), each device having a plurality of pixels (18-21), each pixel having a first terminal (22-25), and all pixels on a device sharing a common second terminal (27), said method comprising the steps of selectively supplying a data signal to at least one of the second terminals from a demultiplexing driver (30); and selectively connecting at least one of the first terminals to a source of voltage through a bidirectional switch and a primary winding (60) of a transformer (58) thereby enabling current to flow into the selectively connected pixel to enable the pixel to charge to an operating voltage; characterized by the steps of: inductively coupling a secondary winding (62) of said transformer to said primary winding and a diode (64), said secondary winding and said diode being connected in series between a voltage source and a ground for limiting the value of the operating voltage; disconnecting said at least one of the first terminals from the voltage source thereby preventing the pixel from discharging; reconnecting said at least one of the first terminals to the voltage source after an appropriate pulse duration to enable current to flow from the charged pixel to the voltage source; disconnecting said at least one of the first terminals from the voltage source after substantially all of the energy stored in the pixel is returned to the voltage source; and removing the data signal from said at least one of the second terminals. A method as claimed in claim 10, further characterized by the step of grounding the pixel after substantially all of the energy stored in the pixel has been returned to the voltage source.

Inventors: ASARS JURIS ANDREJS, ASARS, JURIS ANDREJS
Applicants: WESTINGHOUSE ELECTRIC CORP, WESTINGHOUSE ELECTRIC CORPORATION
Application year: 1990
Main classification: H05B33
IPC codes: G09G3, H05B33