AN AD CONVERTER

Abstract: Second order sigma-delta sections are cascaded to form high order A/D converters suitable for CMOS realisation. Compared to the cascade of first order sigma-delta sections approach, the new structure requires less comparators and less complex digital circuits. The structure is also less sensitive to low frequency amplifier noise, which is important at 16-bit resolution level. A fourth-order integration noise shaping sigma-delta A/D converter front end is disclosed capable of achieving 16-bit resolution and converting up to 64kHz baseband signals.

Description: AN AD CONVERTER The present invention relates to an analogue to digital (AD) converter which employs sigma-delta modulators. Sigma-delta modulators are used in oversampled AD conversion and operate by integrating the difference between a sampled signal and a previously quantized signal. The result of the integration is compared with a reference voltage to determine whether a digital output line is to be set high or low. Noise is introduced into the modulators by the 1 bit quantization process and integrating amplifiers, and it is necessary to employ some form of noise shaping to remove the noise from the band of interest. Oversampled analogue to digital converters offer high precision conversion without requiring precision elements or accurate component matching. One method of achieving high order noise shaping, or shifting, is to employ a relative high oversampling ratio, which is the ratio of sampling clock frequency to input signal bandwidth. There is, however, a practical limit to the maximum clock-rate which can be employed for a given integrated circuit technology and, thus, a relatively high oversampling ratio will invariably give rise to the converter having a relatively small bandwidth, or baseband. This method is therefore limited by the competing desire to use moderate oversampling ratios to improve the width of the baseband. High order noise shaping may also be achieved by using high order integration in the modulators. Direct realisation of high order sigma-delta modulators, however, is generally avoided as they are regarded as being unstable, as discussed in a paper entitled "Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators" IEEE Transactions on acoustics,- speech, and signal processing, vol 36, no. 12, December 1988. Realisation of high order sigma-delta modulators is normally achieved, as described in that paper, by cascading perfectly matched first order sections. The paper further discloses a technique of achieving quantization noise suppression wherein the quantization noise of the first stage is removed by signal subtraction. For high resolution AD conversion, such as the 16-bit level, the noise performance of the amplifiers used in the modulators is very important. In MOS structures, amplifiers generate considerable noise, especially low frequency flicker noise. In a first order sigma-delta modulator, the noise of the amplifier making up the integrator is not shaped by the feedback structure and is added directly to the output signal. High power consumption and a large chip area are needed to keep the amplifier noise at a sufficiently low level. Although invariably the quantization noise of cascaded first order sections subtract and cancel each other, except that of the last stage, the noise and offset due to the amplifiers are added together at the output of the converter. They are added together in the rms sense as the noise and offset from different amplifiers are uncorrelated. This places a practical limit on the number of first order sigma-delta sections that can be cascaded. Also in using a two phase clocking system it is difficult to apply circuit techniques such as correlated double sampling to first order sections to reduce low frequency noise and offset. Increasing the number of phases for a given clock frequency on the other hand, reduces the settling period for the integrators, which is equivalent to increasing the sampling frequency. In accordance with the present invention there is provided an analogue to a digital converter comprising at least two cascaded second order sigma-delta modulators. This has several advantages compared to using first order sections. The number of comparators utilized is half what cascaded first order sections would require for the same order noise of shaping. The digital hardware immediately following each modulator section, such as delay flip-flops and digital adders, is also approximately only half as complicated as what would be required for cascaded first order sections. Preferably said modulators are connected such that at a digital output of said converter the noise generated by the first of said modulators is substantially removed and the noise generated by the second of said modulators has undergone high order noise shaping. Preferably each modulator includes two integrators and a comparator in series, whereby high order noise shaping is performed whilst using a relatively low oversampling ratio. In this construction the transfer function from the second integrator's input of each second order section to that sections output contains a zero at DC. The offset and low frequency flicker noise of the second integrator of each section is therefore naturally suppressed. Higher order noise shaping can thus be achieved before the amplifier noise limits the resolution. Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings wherein: Figure 1 is a circuit diagram of a first preferred embodiment of an AD converter according to the present invention; Figure 2 is a circuit diagram of switch control circuitry of the converter of Figure 1; Figure 3 is a schematic circuit diagram of an output stage or a converter according to the above embodiment; Figure 4 is a schematic block diagram showing one exemplary output processing stage to produce a 16 bit digital output for the above embodiments; Figure 5 illustrates schematically the operation of correlated double sampling used in a second preferred embodiment of the invention, and Figure 6 is a circuit diagram of this second preferred embodiment. An AD converter 2, as shown in Figure 1, includes two second order sigma-delta modulators 4 and 6 which are cascaded so as to provide a 4th order modulator. The first modulator 4 includes two integrators 8 and 10 and a comparator 12 connected in series. The inputs to the integrators 8 and 10 and the comparator 12 are received from switched capacitors which are controlled by complimentary HOS transistors. The MOS transistors are, in turn, controlled by a two phase clock, CLE being one phase and CL0 being the other . phase, as shown in Figure 1. The analogue signal to be converted, V. , is sampled onto an input capacitor 14, having a value G. The difference between the quantized output of the comparator 12 and the sampled signal is integrated by the first integrator 8 and is sampled onto a coupling capacitor 16, having a value A. The first integrator 8 has a feedback capacitor 18 of value D and the quantized output is fed to the inverting input of the integrator 8 after being stored on a second feedback capacitor 20 of value C. The second feedback capacitor 20 stores a signal representative of the complement of the quantized output, in response to signals CLA and CLB used to control a pair of switching transistors 22 and which are received on enabling lines 24 and 26, respectively. The switching transistors 22 selectively couple the second feedback capacitor 20 to a low or high voltage source, + V f . The signals CLA and CLB are generated by a switch control circuit 28 which is connected to the two complimentary outputs 30 and 32 of the comparator 12. The switch control circuit 28, as shown in Figure 2, includes two storage capacitors 34 and 36 coupled to the outputs 30 and 32 of the comparator 12, respectively. An AND gate array 38 is connected to the storage capacitors 34 and 36 and is controlled by the two phase clock to cause the first enabling line 24 (CLA) to receive the signal stored in the second storage capacitor 36 whenever CLE is high. Similarly, the second enabling line 26 (CLB) receives the signal stored on the first storage capacitor 34 when CLE is high. The integrated sampled signal outputted to the coupling capacitor 16 is inputted to the second integrated 10, together with a signal representative of the quantized output received from a third feedback capacitor 40, having a value F. Another pair of switch transistors 42 controlled by the enabling lines 24 and 26 are used to place the quantized output signal on the feedback capacitor 40. The difference between the sampled signal and the quantized output is further integrated by the second integrator 10 and the result is submitted to the comparator 12 and compared with a predetermined threshold level. The quantized output D Q , which appears on output line 32 is high or low depending on the relationship between the output of the second integrator 10 and the predetermined threshold level. A further feedback capacitor 19, of value B, connects the output of the second integrator 10 to its inverting input. The second sigma-delta modulator 6 is same as the first - b - sigma-delta modulator 4 and the above description is equally applicable to the second sigma-delta modulator 6. The input signals, however, are different as the second sigma-delta modulator 6 receives the output of the second integrator 10 of the first modulator 4, V , on line 50 and a signal representative of the quantized output D , of the first modulator 4 on line 52, which is connected to the third feedback capacitor 40 of the first modulator 4. The input signals are combined at the inverting input of the first integrator 8 of the second modulator stage 6 so as to remove any component of the input signal V. . The second modulator 6 is used primarily as a means which enables suppression and shaping of any noise generated in the modulators 4 and 6. The transfer function of each modulator 4 and 6 is low pass to the signal input thereto. The outputs V . (i = 1,2) of the second integrators 10 are quantized by the comparators 12, as described above, into +1 or -1, and quantization error Q. is added to the signals by the comparators 12, such that D . = V . + Q.. For the transfer function from the quantization error Q. to the digital output D ., the integrators 8 and 10 of the modulators 4 and 6 appear in the feedback branch and the transfer function is second order high pass. Second order noise shaping is performed by each modulator 4 and 6. An expression for D . in the z-domain can be derived by first considering the sum of the currents at the input of the first integrator 8 of the first modulator 4 when CLO is active. This gives equation 1 below. " v ύι G + D ol C + D (1 - z "1 ) '11 = 0 (1) Considering the sum of the currents at the input to the second integrator 10 gives equation 2 below. Substituting an expression for the output of the first integrator 8, V,,, derived from equation 1 into equation 2 gives the result shown in equation 3 below. AG/DB + (1 - Z -1 ) 2 Qi Dθl = 1 + (-2 + AC/DB + F/B) Z" 1 + (1 - F/B) Z" 2 (3) The expression for D , is simply obtained by substituting in equation 3 the quantization error Q, of the first modulator 4 for V. to give: AG/DB Z -1 Qx + (1 - Z -1 ) 2 Q2 Dθ2 = 1 + (-2 + AC/DB + F/B) Z -1 + (1 - F/B) Z" 2 The final output D of the AD converter 2 is obtained by delaying once the quantized output D , of the first modulator 4 and subtracting the quantized output of the second modulator 6 therefrom after the second quantized output D Q2 has been subjected to the transfer function - a - —12 DB/AG (1-z ) . Thus, the final output D can be expressed as set out below in the equation 4. D = z-1 DQI ~ (DB/AG)(1-Z-l) 2 D 02 (AG/DB) Z" 2 V in - (DB/AG)(1 - Z~l)4 Q 2 = 1 + (-2 + AC/DB + F/B) Z -1 + (1 - F/B) z -2 (4) A circuit for combining the outputs D Q1 and D Q2 according to this transfer function to produce a final output D is schematically illustrated in Figure 3. For other embodiments of modulator architecture according to the invention, different ways of combining the two outputs D Q , and D Q2 may be employed; derivable using analogous expressions to those given above. Referring to Figure 4, the combined output bitstream D of the sigma-delta modulator is converted to the desired digital output by a digital output stage incorporating a low pass digital filtering stage 100 and a decimation filter stage 102 (which may be a comb filter). From equation 4 it is apparent that the quantization noise of the first modulator 4 is removed and the quantization noise of the second modulator 6 is subjected to 4th order noise shaping. The denominator of equation 4 can be designed to be Butterworth, which gives a smooth passband for the input signal. At low frequency the signal gain can be determined by setting z to unity in equation 4 which gives D/V. = G/C. The comparators 12 are connected to the second integrators 10 during the settling phase of the integrators 10. The output of each comparator 12 is sampled on the relatively large capacitors 34 and 36 and held for the following clock phase. The switch control circuit 28 following each comparator 12 only operates during the hold phase. This gives the comparators 12 maximum settling time. The accuracy of the gain depends on the matching between the second feedback capacitor 20 and the input capacitors 14. Ideally the ratio DB/AG should.be as small as possible to reduce the noise term in equation 4. In practice, the capacitance ratios G/D, C/D and A/B are determined by the maximum amplifier signal swing requirements. Preferably DB/AG is arranged to be a power of 2 so that digital multiplication by DB/AG can be easily performed by simple data shifts. Higher order AD converters can be constructed by cascading more second order modulators. If further noise reduction is required, correlated double sampling or autozeroing can be applied to the first integrators 8 of the modulators 4 and 6. This suppresses the offset and low frequency flicker noise of the first integrator 8 and is easily arranged for a second order modulator as the first integrator is idle during one of the clock phases. Referring to Figure 5, double sampling is a circuit technique which reduces low frequency noise or interference. The noise voltage V is sampled twice, once together with the input signal V. as discussed above and once without V. (on the idle clock phase), and the second sample is subtracted from the first sample. The output voltage V QUt contains the sampled version of V and digitally differentiated noise: 'out = [ Vm. + V„ (l-z '1/2 ) ] A - lό - -1/2 At low frequencies, z - 1 and (1 - z ' ) → 0, so that the low frequency (or highly correlated) noise is substantially reduced by this technique. Figure 6 shows how the circuit of Figure 1 is simply modified to incorporate double-sampling; the switching transistor pair following the input capacitor 14 are repositioned in the feedback network of integrator 8. Correlated double sampling is much more difficult to arrange for known cascaded first order sections having a two phase clock. It is known that the quantization noise spectrum of a first order modulator has strong peaks in the baseband for inactive input signals. These peaks also exist in second order modulators but are considerably reduced. When second order modulators are cascaded, according to the present invention, the input to each, except the first modulator, is the quantization noise of the preceding stage (which is not inactive). The output noise spectrum of these sections therefore do not contain significant peaks. The first modulator's quantization noise is cancelled by the second section, so the weak peaks of the first modulator's noise spectrum do not appear in the output. No dither is needed and the design is less complex. The feedback of + V f in a sigma-delta modulator should be done through the same feedback capacitors 20 and 40. In some prior proposals, the feedback of + V is done via different capacitors with the same nominal value. In practice the mismatch between the two capacitances will be around 0.1°/o to 0.5°/o. This means the converters low frequency gain for positive input will differ from the low frequency gain for negative input also by 0.1°/o to 0.5°/o giving rise to a transfer function which is non-linear and degrades the total harmonic distortion of the AD converter. - li - For high performance, the sigma-delta AD converter should have 16 bit resolution and a signal baseband of 64kHz. This resolution requirement translates into a signal to noise plus total harmonic distortion ratio of 96dB. The rms quantization noise, N, of an ideal Nth order noise shaping sigma-delta AD converter is given by equation 5 below. v ref re P resents half tne quantization step and f c and f are the signal baseband and clock frequency, respectively. If the maximum peak to peak rms signal amplitude is limited to V f , the maximum signal to noise ratio is given by equation 6. From equation 6 it can be calculated that if quadruple integrated is used, a minimum over sampling ratio of only 48.72 is required to achieve a 96dB signal to noise ratio, or 16 bit resolution. Considering that at a successive approximation AD converter needs at least K clock periods for K-bit resolution, a sigma-delta AD converter with quadruple integration is ideally only three times slower than a successive approximation converter. In practice, if DB/AG is larger than 1, the signal noise ratio given by 2 equation 6 will be reduced by (DB/AG) . Determination of the oversampling ratio should take this into account. For example, for V f = + 1.2V and DB/AG being two, the maximum amplifier output swing is close to + 2V. This is adequate for a standard 2αm CMOS process, whose power supply is +2.5V. A 12dB loss of signal to noise ratio can be compensated by using a higher oversampling ratio. Choosing a 5HHz clock frequency ensures a 102 dB signal to noise ratio for the 64kHz baseband, giving a 6dB margin. o Further increasing the clock frequency is difficult as the amplifier settling requirements become excessive. The capacitances ratios G/D, C/D and A/B are determined by the amplifier output swing requirements as 0.707. In one preferred embodiment, capacitances G, C and A are chosen 5 to be 2pF, capacitances D and B to be 2.828pF and capacitance F is chosen to be ^A to produce a Butterworth denominator. The four operational transconductance amplifiers (OTAs) in the converter are modeled as voltage controlled o current sources in parallel with a large resistor and load capacitor. For the preferred embodiments, the load capacitor is chosen to be 0.5pF to balance the actual capacitive load of each amplifier during different clock phases. For such a capacitive load, it is found that the •? D _; OTAs total transconductance G„m should not be less than 400μA/V. It is possible meet such a requirement in 2αm CMOS technology. A/D convertors according to the invention may be fabricated as a complete package including the modulator 30 and also the output circuitry. However, it is also envisaged that the higher-order modulator (which produces digital output and is thus, broadly speaking, also an AD convertor) may be fabricated as a discrete package, either producing separate modulator section outputs D . or including combining circuitry similar to that of Figure 3 to produce a single output D. This offers greater flexibility to the chip designer in designing his digital applications.

Claims: - If - CLAIMS 1. An analogue to digital convertor comprising at least two cascaded second order sigma-delta modulators. 2. A converter as claimed in claim 1, wherein said modulators comprise two integrators and a comparator connected in series, with the input of said integrators coupled, in use, to signals representative of the output of said comparator. 3. A converter as claimed in claim 2, wherein said modulators are connected such that at a digital output of said converter the noise generated by the first of said modulators is substantially removed and the noise generated by the second of said modulators has undergone high order noise shaping. 4. A converter as claimed in claim 3, wherein said high order noise shaping is performed whilst using a relatively low oversampling ratio. 5. A converter as claimed in claim 4, wherein at least one of said modulators inputs the quantization noise of the preceding modulator and is used to perform high order noise shaping on the quantization noise of the .preceding modulator and its own quantization noise. 6. A converter as claimed in claim 5, further comprising an output stage which performs further noise shaping to ensure the quantization noise of the last modulator undergoes 4th order noise shaping and to enable the quantization noise of the penultimate modulator to be removed. 7. A converter as claimed in claim 6 further comprising means for applying correlated double sampling or autozeroing to the first integrators of said modulators. - la - 8. A converter as claimed in any one of the preceding claims realised in CMOS. 9. An analogue to digital converter substantially as hereinbefore described with reference to the accompanying drawings.

Inventors: HUANG QIUTING, HUANG, QIUTING
Applicants: BRITISH TELECOMM, BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY
Application year: 1990
Main classification: H03M1
IPC codes: H03M3