Nonvolatile semiconductor memory apparatus

Abstract: In a nonvolatile semiconductor memory apparatus of a reference type comprising a memory circuit (1), reference circuit (4) and differential amplifier (3), a drain current of a reference cell transistor (41) is formed such that it becomes almost half a drain current of a memory cell transistor (15), thereby enabling the memory circuit (1) to be in symmetric relation with the reference circuit (4). Therefore, a parastic capacitance in the memory circuit is made to be almost the same as that of the reference circuit, and thus a difference in noise level between a noise input to one input (+) of the differential amplifier (3) and a noise input to the other input (-) of the differential amplifier is made to be almost zero, thereby speeding up the data read-out operation of the semiconductor memory apparatus.

Description: Background of the Invention Field of the Invention This invention relates to a nonvolatile semiconductor memory apparatus, e.g., an EPROM, an EEPROM or a mask ROM, adopting a reference method pertaining to the data reading. That is, this invention relates to a nonvolatile semiconductor apparatus comprising a memory circuit part equipped with a memory cell transistor, a reference circuit part equipped with a reference cell transistor, and a differential amplifier for outputting the content of the memory cell transistor by comparing the output from the memory cell transistor with the output from the reference cell transistor. Generally, the operation of a nonvolatile semiconductor device can be speeded up by adopting a reference method, and a further speed up is possible with a reduction in noise effect in a differential amplifer. Related Art A nonvolatile semiconductor memory apparatus adopting a reference method has been proposed, as detailed in Figure 1. This nonvolatile semiconductor memory apparatus is an EPROM. It comprises a memory circuit part 1, a reference circuit part 2 and a differential amplifier 3, and reads out data by comparing the output voltage V MEM of the memory circuit part 1 with the output voltage V REF of the reference circuit part 2. The memory circuit part 1 comprises a power source line 11 supplied with a power source voltage V CC , e.g. 5V, an n channel MOS transistor (hereafter referred to as nMOS) 12 for a load, an nMOS 13 for bit line bias, a sense line SL, nMOS 14₀ through 14 m for bit line selection, bit lines BL₀ through BL m , word lines WL₀ through WL n and EPROM cells 15₀₀ through 15 nm making up a memory cell transistor. nMOS 12 is a depletion type nMOS whose drain is connected with the power source line 11. Its gate and source are commonly connected, and its common connection point (hereafter referred to as node N MEM ) is connected to one of the input terminals 31 of the differential amplifer 3 (turnover input terminal ⊖ ) and a drain of nMOS 13. nMOS's 13 and 14₀ through 14 m are enhancement type nMOS's. nMOS's 14₀ through 14 m , in particular, are the same size and have the same characteristics. Here, the source of nMOS 13 is connected to the drain of nMOS's 14₀ through 14 m via the sense line SL. The respective sources of nMOS's 14₀ through 14 m are connected to the drains of the first-line EPROM cells 15₀₀ through the (n-1)th line 15 n0 , the drains of the second-line EPROM cells 15₀₁ through the (n+1)th line 15 n1 , ...., and the drains of the (m+1)th line EPROM cells 15 0m through the (n+1)th line 15 nm via bit lines BL₀ through BL m . The control gates of the first-line EPROM cells 15₀₀ through the (m+1)th line 15 0m , the second-line EPROM cells 15₁₀ through the (m+1)th line 15 1m , ...., and the (n+1)th line EPROM cells 15 n0 through the (m+1)th line 15 nm are connected to word lines WL₀ through WL n , and the sources of all the EPROM cells 15₀₀ through 15 nm are earthed. EPROM cells 15₀₀ through 15 nm are all the same size. Their plan view and cross section are as shown in Figures 2 and 3. Here, 16 is a p type silicon substrate, 17 is a field oxide film, 15 00C is a channel region, 18 and 19 are SiO₂ (silicon dioxide) films, 15 00FG is a floating gate, 15 00CG is a control gate in the word line WL₀, 15 00D is a drain region, and 15 00S is a source region. This EPROM cell 15₀₀ has a channel width W of 1.5 µm (micro meters), a channel length L of 1.0 µm (1 micrometer = 10,000 angstroms), an overhang length A from the channel region 15 00C of the floating gate 15 00FG of 0.6 µm, an oxide film thickness t CF between the control gate 15 00CG and the floating gate 15 00FG of 0.03 µm(300 angstroms) and an oxide film thickness t FS between the floating gate 15 00FG and the channel region 15 00C , also of 0.03 µm (300 angstroms). Here, the capacitance C CF between the control gate 15 00CG and the floating gate 15 00FG is expressed as, C CF = εSiO₂ · ε₀ · L (A + W + A) t CF and the capacitance C FS between the floating gate 15 00FG and the channel region 15 00C is expressed as, C FS = εSiO₂ · ε₀ · L · W t FS where ε Si02 is the relative permittivity of SiO₂ films 18 and 19, and ε₀ is the dielectric constant. Also, the voltage V FG of the floating gate 15 00FG is expressed as, V FG = C CF C CF + C FS · V CG + Q FG C CF + C FS where V CG is the voltage of the control gate 15 00FG and Q FG is the charge of the floating gate 15 00FG . Therefore, if there is no charge in the floating gate 15 00FG, V FG = C CF C CF + C FS · V CG Substituting equations (1) and (2) into equation (4), V FG = A + W + A A + W + A + W · V CG = 2 A + W 2 A + 2 W · V CG Substituting W = 1.5µm and A = 0.6µm into equation (5), V FG = 0.64 V CG Therefore, when V CG =5V, V FG =3.2V In the memory circuit part 1 thus configured, the gate of nMOS 13 is supplied with V BIAS , such as 2.5V, and bit lines BL₀ through BL m , i.e., the drains of EPROM cells 15₀₀ through 15 nm , are biased at about 1V. This is purported to prevent a writing due to a so-called soft write phenomenon while data are read, if the drain voltages of EPROM cells 15₀₀ through 15 nm are too high. Word lines WL₀ through WL n are each supplied with word line selection signals X₀ through X n so that a row is selected, and the gates of n MOS 14₀ through 14 m are each supplied with bit line selection signals Y₀ through Y m so that a column is selected. These word-line selection signals X₀ through X n and bit line selection signals Y₀ through Y m are all either 5V (the power source voltage V CC at a selection time) or 0V (the earth voltage V SS at a non-selection time). If the EPROM cell selected from among 15₀₀ through 15 nm memorizes the "ON" status, i.e., logical "1", a drain current flows through it. Conversely, if the selected EPROM cell memorizes the "OFF" status, i.e., logical "0", the drain current does not flow through it. Since nMOS's 12 and 13, as well as the nMOS selected from among 14₀ through 14 m and the EPROM cell selected from among 15₀₀ through 15 nm , configure a current - voltage conversion circuit, the existence of a drain current appears as a change in voltage V MEM of the node N MEM . Figure 4 shows the I DS - V FG characteristic of of EPROM cells 15₀₀ through 15 nm when the drain bias V DS is 1V. When V FG = 3.2V in the "ON" status in this EPROM, as described earlier, I DS =60 [µA] (micro amperes). The reference circuit part 2 comprises a power source line 21 supplied with a power voltage V CC , nMOS's 22 and 23 for a load, nMOS 24 for bit line bias, a reference sense line RSL, nMOS's 25₀ through 25 m for reference bit line selection (of which of nMOS's 25₀ through 25 m-1 are selected as dummy nMOS's), a reference bit line RBL, and EPROM cells 26₀ through 26 n making up a reference cell transistor. nMOS's 22 and 23 are depletion type nMOS's the same size and having the same characteristics as nMOS 12. nMOS's 22 and 23 are connected in parallel. That is, their respective drains are connected to the power source line 21. Their respective gates and sources are commonly connected, and their respective common connection points (hereafter referred to as a node N REF ) are connected to the other input terminal 32 (nonturnover input terminal ⊕) of the differential amplifier 3 and the drain of nMOS 24. nMOS 24 is an enhancement type nMOS of the same size and having the same characteristics as nMOS 13. The source of nMOS 13 is connected to the drains of nMOS's 25₀ through 25 m via the reference sense line RSL. nMOS's 25₀ through 25 m are enhancement type nMOS's the same size and having the same characteristics as nMOS's 14₀ through 14 m . The sources of nMOS 25₀ through 25 m-1 , are earthed, and the gates thereof are supplied with 0V so that they are always in the "OFF" status. The source of nMOS 25 m , however, is connected to the drains of EPROM cells 26₀ through 26 n via the reference bit line RBL, and the gates thereof are supplied with 5V so that they are always in the "ON" status. As for nMOS 13, the gate of nMOS 24 is supplied with V BIAS , e.g., 2.5 V, and the reference bit line RBL, i.e., the drains of EPROM cells 26₀ through 26₀, is biased at about 1V. EPROM cells 26₀ through 26 n are EPROM cells the same size and having the same characteristics as EPROM cells 15₀₀ through 15 nm . Their respective gates are connected to word lines WL₀ through WL n and their respective sources are earthed. Electrons are not injected into the respective floating gates of EPROM cells 26₀ through 26 n , which are configured to be in the "ON" status when the power source voltage V CC is supplied to the control gate and to have the same drain current as that which flows when any of EPROM cells 15₀₀ through 15 nm of the memory circuit part 1 is turned to the "ON" status. In the reference circuit part 2 thus configured, nMOS's 22, 23 and 24, plus any one of EPROM cells 26₀ through 26 n , configure a current - voltage conversion circuit. Since nMOS's 22 and 23 are parallel connected and their load resistance values are set at half that of the memory circuit part 1, the voltage V REF of the node N REF is set at the medium of the maximum and minimum values of the voltage V MEM of the node N MEM . Such an EPROM uses this voltage V REF as a reference voltage. Because the node N MEM of the differential amplifier 3 is connected with one of the input terminals 31 (turnover input terminal ⊖) and the node N REF thereof is connected with the other of the input terminals 32 (nonturnover input terminal ⊕), when V MEM > V REF the differential amplifier 3 outputs a low level "L" (the earth voltage 0V) to its output terminal 33, and when V MEM < V REF the differential amplifier 3 outputs a high level "H" (the power source voltage V CC ). In this case, a voltage difference between V MEM and V REF of 50mV suffices, and there is no need to change the output voltage from the memory circuit part 1 to either the high level "H" (power source voltage V CC ) or the low level "L" (the earth voltage 0V). In other words, if the node N MEM has a voltage change as low as 100mV, data can be read out. Therefore, access time of the EPROM adopting the reference method can shorten the access time. Incidentally, in an EPROM adopting such a reference method, even when the voltage difference between V MEM and V REF is smaller than 50mV, as long as the differential amplifer 3 can detect the difference, its response can be further speeded up. However, in an EPROM of the prior art, shown in Figure 1, when data are read, since the memory circuit part 1 and the reference circuit part 2 configure asymmetric circuits, a difference arises between the stray capacitance to the input terminal 31 of the differential amplifier 3 and that to the input terminal 32 thereof. Therefore, when a noise generated from an output circuit (not shown in the drawing) is inputted to input terminals 31 and 32 of the differential amplifer 3, a difference arises between the levels of the noises respectively inputted to the two input terminals 31 and 32. As a result, if a further speed up of an action of a nonvolatile semiconductor memory apparatus is aimed at with a difference between V MEM and V REF smaller than e.g. 50mV, the apparatus tends to be affected by noise and to read data erroneously. The problem is that no speed-up can be achieved unless this point is solved. To solve such a problem, this invention provides a nonvolatile semiconductor memory apparatus which adopts a reference method having a higher action speed with a smaller level difference between the noise inputted to each of the two input terminals of the differential amplifier by making the stray capacitance to the memory circuit part and that of the reference circuit part as near equal as possible. Summary of the Invention The nonvolatile semiconductor memory device of this invention is a nonvolatile semiconductor memory device comprising a memory circuit part having at least a memory cell transistor, a reference circuit part having at least a reference cell transistor, and a differential amplifier. The differential amplifier outputs the memory content of the memory cell transistor by comparing its output with that of the reference cell transistor, where the drain current of the reference cell transistor approximates the median of the drain current of the memory cell transistor when the memory cell transistor is conducting and that when it is not. A means for setting the drain current of the reference cell transistor at midpoint between the drain current at a conducting time and that at a non-conducting time as described earlier can be realized by heightening the threshold voltage of the reference cell transistor e.g. by injecting impurity boron ions into a channel region of the reference cell transistor, or by thickening the gate oxide film of the reference cell transistor. Alternatively, it can be realized by making the capacitive coupling ratio of the reference cell transistor C CF /(C CF +C FS ) smaller than that of the memory cell transistor, with the reference cell transistor comprising an authentic channel region and a dummy channel region. C CF is the capacitance between the control gate and the floating gate. C FS is the capacitance between the floating gate and the substrate. Since the reference cell transistor in this invention is configured so that its drain current approximates a half of the drain current of the memory cell transistor when the memory cell transistor is conducting and that when it is not, by matching the load resistance value of the reference circuit part with that of the memory circuit part. Thus a reference voltage can be generated as where the load resistance of the reference circuit part is set equal to half the load resistance of the memory circuit part, as in the prior art (refer to Figure 1), and the drain currents of the reference cell transistor and the memory cell transistor are the same. That is, it becomes possible to set load resistances (e.g. transistors for a load,) of the same number, of the same size and having the same characteristics in the reference circuit part as in the memory circuit part. Hence, this invention enables the level difference between the noises inputted to both input terminals of a differential amplifier to be minimized by making the stray capacitance of the memory circuit part and the stray capacitance of the reference circuit part equal. This invention is realized by heightening the threshold voltage of the reference cell transistor by injecting impurity ions into the channel region of the reference cell transistor or by thickening the gate oxide film of the reference cell transistor. Thus, there is no need to newly design the size of the reference cell transistor. Otherwise, the reference cell transistor is formed in the same process as the memory cell transistor. Brief Description of the Drawings Figure 1 is a circuit diagram that details an exemplary EPROM of the prior art. Figure 2 is a plan view of the EPROM cell configuring a memory cell transistor. Figure 3 is a cross section Figure 2 across line VIII-VIII′. Figure 4 shows the I DS -V FG characteristic of the EPROM cell. Figure 5 is a circuit diagram that details the first embodiment when this invention is applied to an EPROM. Figure 6 is a plan view of a part of the memory circuit part and the reference part of the second embodiment of this invention. Figure 7 is a plan view of the EPROM cell configuring the reference cell transistor of the second embodiment of this invention. Figure 8 is a cross section of Figure 7 across line IV-IV′. Figure 9 is a plan view of part of the memory circuit part and the reference circuit part of the third embodiment of this invention. Preferred Embodiments of this Invention The preferred embodiments of this invention are explained below by referring to Figures 5 through 9. Like the prior art shown in Figure 1, the first preferred embodiment is an application of this invention to an EPROM. Numbers shown in Figures 5 through 9 which are the same as those shown in Figure 1 indicate the same parts, and their explanations are omitted. First Embodiment of this Invention: Figure 5 is a circuit diagram that details the first embodiment which comprises a memory circuit part 1, a reference circuit part 4 and a differential amplifier 3. The part that is different from the EPROM shown in Figure 1 as the prior art, is the reference circuit part 4. The reference circuit part 4 comprises a power source line 21, an nMOS 22 for a load, an nMOS 24 for reference bit line bias, a reference sense line RSL, nMOS's 25₀ through nMOS 25 m for reference bit line selection, a reference bit line RBL, and EPROM cells 41₀ through 41 m configuring a reference cell transistor. The parts that are different from those of the prior art shown in Figure 1 are the parts relation to nMOS 22 for a load and EPROM cells 41₀ through 41 n . That is, in this first embodiment, only one nMOS 22, the same size and characteristics as nMOS 12 in the memory circuit part 1 is established as an nMOS for a load. The load resistance value of this nMOS 22 is set equal to that of the memory circuit part 1. Although EPROM cells 41₀ through 41 n are formed the same size as EPROM cells 15₀₀ through 15 nm shown in Figure 1 of the prior art, the threshold voltage V th41 of EPROM cells 41₀ through 41 n is set higher than the threshold voltage V th15 of EPROM cells 15₀₀ through 15 nm . Thus, their drain current approximates half that of EPROM cells 15₀₀ through 15 nm in the "ON" status. At this time, the necessary threshold voltage V th differs, depending on the component characteristics. For example, if the threshold voltage V th26 of EPROM 26₀ through 26 n is 2V, the threshold voltage V th41 of EPROM cells 41₀ through 41 n is higher, e.g., between 2.5V and 3.5V. One way to increase the threshold voltage V th is to inject boron ion into the channel region. When the threshold voltage is heightened by a boron ion injection, the size of EPROM cells 41₀ through 41 n need not be newly redesigned. That is, as with the existing EPROM cells 26₀ through 26 n , they can be designed to be the same size as EPROM cells 15₀₀ through 15 nm . Also at this time, other than the process of ion injection to the channel region, the control gates, the floating gates, the drains and the sources of EPROM cells 41₀ through 41 n can be respectively formed in the same process as that of EPROM cells 15₀₀ through 15 nm . In this first embodiment, although the nMOS for a load in the reference circuit part 4 comprises only one nMOS, i.e., nMOS 22, whose load resistance value is set equal to that of the memory circuit part 1, since the drain current of EPROM cells 41₀ through 41 n is set at approximately half of that of EPROM cells 15₀₀ through 15 nm . However, the voltage V REF of the node N REF is equal to that the prior art shown in Figure 1. That is, the voltage V REF of the node N REF is set at the median of the maximum and minimum of voltage V MEM of the node N MEM . Consequently, the memory data in EPROM cells 15₀₀ through 15 nm can be read, as in the prior art shown in Figure 1. Also in this first embodiment, when nMOS 14 m is turned to the "ON" status and bit line BL m is selected, for example, since nMOS's 14₀ through 14 m-1 are in the "OFF" status, the memory circuit part 1 and the reference circuit part 4 become virtually entirely symmetric circuits. Accordingly, the stray capacitance of nMOS 12 for a load, the stray capacitance of nMOS 22 for a load, the stray capacitance of the sense line SL, the stray capacitance of the reference sense line RSL, the stray capacitance of n MOS 14₀ through 14 m for the selection among bit lines BL₀ through BL m , the stray capacitance of nMOS's 25₀ through 25 m for selection of the reference bit line RBL, the stray capacitance of bit line BL m , and the stray capacitance of the reference bit line RBL are all the same. That is, the stray capacitance of the memory circuit part 1 measured from one input terminal 31 of the differential amplifier 3 and that of the reference circuit part 4 measured from the other input terminal 32 of the difference amplifier 3 are approximately the same. This is similar to the case where any one of nMOS's 14₀ through 14 m-1 is selected to be turned to the "ON" status. Hence, according to this first embodiment, the level difference between the noise inputted to one input terminal 31 (turnover input terminal ⊖) of the differential amplifier 3 and the noise inputted to the other input terminal 32 (nonturnover input terminal ⊕) thereof becomes small. These noises are offset by the differential amplifier and has very little effect on the data reading. That is, erroneous data reading is prevented. As explained, since the noise effect is made insignificant, even if the voltage change at node N MEM is made smaller than in the prior art, the data reading of EPROM cells 15₀₀ through 15 nm is easily done. Therefore, this first embodiment has the effect of attaining a higher action speed than the prior art shown in Figure 1. Second Embodiment of this Invention: The circuit configuration of the second embodiment is the same as that shown in Figure 5. However, the component structure of EPROM cells 41₀ through 41 n is different. A plan view of EPROM cells 41₀ through 41 n is shown in Figure 6. Hence, 41 0C through 41 3C , 41 0DC though 41 3DC , 41 0FG through 41 3FG , and 41 0CG through 41 3CG are the authentic channel regions, the dummy channel regions, the floating gates, and the control gates, respectively, of EPROM cells 41₀, 41₁, 41₂, and 41₃. 42 is a drain region, 43 is a source region and 44 is a contact hole. EPROM cells 41₀ through 41 n are all made the same size. EPROM cell 41₀ is explained in detail as being representative of EPROM cells 41₀ through 41 n . A plan view is shown in Figure 7 and a cross section is shown in Figure 8. 45 and 46 are SiO₂ films. 41 0D is a drain region. 41 0S is a source region. 47 and 48 are N⁺ diffused layers. The exemplary dimensions of this EPROM cell 41₀ are as follows. The channel width W of the authentic channel region 41 0C is 1.5 µm. The channel length L of the authentic and dummy channel region 41 0C and 41 0DC is 1.0 µm. The channel width X of the dummy channel region 41 0DC is 40 µm. The overhang length A from the authentic and dummy channel regions 41 0C and 41 0DC is 0.6 µm. The space B between the authentic channel region 41 0C and the dummy channel region 41 0DC is 2.8 µm. The oxide film thickness t CF between the control gate 41 0CG and the floating gate 41 0FG and the oxide film thickness t FS between the floating gate 41 0FG and the channel regions 41 0C or 41 0DC are both 0.03 µm (300 angstroms). In this a configuration, the capacitance C CF between the control gate and the floating gate of EPROM cells 41₀ through 41 n is expressed as, C FC = εSiO₂ · ε₀ · L (A + W + B + X + A) t CF and the capacitance C FS between the floating gate and the substrate is expressed as, C FS = εSiO₂ · ε₀ · L (W + X) t FS When equations (7) and (8) are substituted into equation (4), V FG = A + W + B + X + A A + W + B + X + A + W + X · V CG = 2 A + W + B + X 2 A + 2 W + B + 2 X · V CG Substituting W=1.5 µm, A=0.6 µm, B=2.8 µm, and X=40 µm into equation (9), V FG =0.52V CG That is, the capacitive coupling ratio C CF /(C CF +C FS ) of EPROM cells 41₀ through 41 n at 0.52 is smaller than the capacitive coupling ratio of EPROM cells 26₀ through 26 n of the prior art shown in Figure 1 (which is the same as the capacitive coupling ration of EPROM cells 15₀₀ through 15 nm in the memory circuit part 1) at 0.64 (Refer to equation (6)). Therefore, if V CG =5V then, V FG =2.6V and the drain current I DS of EPROM cells 41₀ through 41 n becomes 35 µA, which is approximately a half the drain current of EPROM cells 15₀₀ through 15 nm (refer to Figure 4). The capacitive coupling ratio of 0.52 of EPROM cells 41₀ through 41 n in this case is only an example. It generally depends on the component characteristics. However, given the capacitive coupling ratio of EPROM cells 26₀ through 26 n of the prior art being at 0.6, the capacitive coupling ratio of EPROM cells 41₀ through 41 n of the second embodiment of this invention is desired to be, e.g., in the range of 0.3 through 0.5. Thus, also in the second embodiment, the number of nMOS's for a load of the reference circuit part 4 is the same as the number of nMOS's for a load of the memory circuit part 1 (i.e., one) and their load resistance value is also the same. Also, the drain current of EPROM cells 41₀ through 41 n are configured to approximate a half of the drain current of EPROM cells 15₀₀ through 15 nm . Therefore, as in the first embodiment, each of the stray capacitances measured from the differential amplifier 3 of the memory circuit part 1 or the reference circuit part 4 become almost equal. Thus, the action speed is improved from that of the prior art, because the noise effect on the differential amplifier 3 is greatly reduced. Third Embodiment of This Invention: Figure 9 is a detailed plan view of a part of the third embodiment of this invention. In this embodiment, a reference bit line RBL and a ground line 51 are drawn between the (k+1)th bit line BL k and the (k+2)th bit line BL k+1 among (m+1) pieces of the bit lines BL₀ through BL m (where k<m), and the dummy channel regions 41 0DC through 41 nDC of cells 41₀ through 41 n along a reference bit line RBL are set under the ground line 51 for the contact with the source region 43 by avoiding the contact hole part of the ground line 51. A similar action action and effect to the earlier described second embodiment is also obtained, since dummy channel regions 41 0DC through 41 nDC of EPROM cells 41₀ through 41 m are set under the ground line 51. Thus, the third embodiment of this invention has the advantage that the entire memory cell array is smaller than that of the second embodiment. Incidentally, although the application of this invention to an EPROM is explained in these preferred embodiments, this invention is applicable to various nonvolatile semiconductor memory devices, such as EEPROM's and mask ROM's. However, for those devices in which the capacitive coupling ratio of the reference cell transistor is made smaller, as in the second and third embodiments, this invention is applicable where a memory cell transistor and a reference cell transistor comprise an EPROM cell having a floating gate. Also, although a transistor is used for a load resistance in the above embodiments, basically an ordinary resistance can be used. As explained, this invention enables load resistances of an equal number, of an equal size and having the same characteristics to be built in the reference circuit part and the memory circuit part. The stray capacitance of the memory circuit part and the reference circuit part are made almost the same. Thus, the level difference of the noise inputted to the input terminals of the differential amplifier becomes small. Therefore, this invention reduces the noise effect on the differential amplifier and enable faster data reading.

Claims: A nonvolatile semiconductor memory device comprising: a memory circuit part (1) comprising at least a memory cell transistor (15); a reference circuit part (2) comprising up at least a reference cell transistor (26,41); and a differential amplifier means (3) for outputting the memory content of said memory cell transistor by comparing the output from said memory cell transistor with the output from said reference cell transistor; characterized in that the drain current of said reference cell transistor approximates the median between the drain current of said memory cell transistor when said memory cell transistor is conducting and the drain current of said memory cell transistor when said memory cell transistor is not conducting. The nonvolatile semiconductor memory device according to claim 1, wherein: the drain current of said reference cell transistor is made to be the median between each of said drain currents of said memory cell transistor, by making said reference cell transistor and said memory cell transistor of the same size and by heightening the threshold voltage of said reference cell transistor. The nonvolatile semiconductor memory device according to claim 2, wherein: said threshold voltage is heightened by an impurity ion injection into the channel region of said reference cell transistor. The nonvolatile semiconductor memory device according to claim 2, wherein: said threshold voltage is heightened by thickening the gate oxide film of said reference cell transistor. The nonvolatile semiconductor memory device according to claim 1, wherein: said memory cell transistor and said reference cell transistor both comprise an EPROM cell having a control gate and a floating gate. The nonvolatile semiconductor memory device according to claim 5, wherein: the drain current of said reference cell transistor is set at the median between each of said drain currents of said memory cell transistor, by having said reference cell transistor comprise an authentic channel region (410C) and a dummy channel region (410DC), and by making the capacitive coupling ratio of said reference cell transistor C CF /(C CF +C FS ), where C CF is the capacitance between the control gate and the floating gate and C FS is the capacitance between the control gate and the substrate, smaller than the capacitive coupling ration of said memory cell transistor. The nonvolatile semiconductor memory device according to any of claims 1 through 6, wherein: said memory circuit part comprises multiple memory cell transistors arranged in a matrix form, multiple bit lines to which the source or the drain of said multiple memory cell transistors is commonly connected in one direction of said matrix, multiple word lines to which the gate of said multiple memory cell transistor is commonly connected in the other direction of said matrix, a transistor (14) for selecting the bit line connected to each terminal of said multiple bit lines, a transistor (13) for biasing the bit line connected to said bit line via said transistor for said bit line selection, and a transistor (12) for a load connected to said transistor for biasing said bit line whose connecting point is connected to one input terminal of said differential amplifier; and wherein: said reference circuit part comprises multiple reference cell transistors to whose gate each of the word line is connected, being arranged corresponding to each of said word lines, a reference bit line with which the source and drain of said multiple reference cell transistor is commonly connected, a group of transistors (25) for selecting said reference bit line, one of whose transistors is connected to one terminal of said reference bit line, a transistor (24) for biasing a reference bit line connected to said reference bit line via said transistor for selecting a reference bit line, and a transistor (22) for a load connected to said transistor for biasing said reference bit line and its connecting point is connected to the other input terminal of said differential amplifier. The nonvolatile semiconductor memory device according to claim 7, wherein: said memory circuit part and said reference circuit part are virtually configured mutually symmetrically when data are read. The nonvolatile semiconductor memory device according to claim 8, wherein: said memory cell transistors (15) in said bit line direction and said reference cell transistors (41) are of the same number, said transistors (14) for selecting a bit line and said transistors (25) for selecting a reference bit line are of the same size, characteristics and number; said transistors (13) for biasing said bit line and said transistors (24) for biasing reference bit lines are of the same size, characteristics and number; and said transistors (12) for a load within the memory circuit part and said transistors (22) for a load within the reference circuit part are of the same size, characteristics and number.

Inventors: YOSHIDA MASANOBU, YOSHIDA, MASANOBU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G11C16
IPC codes: G11C16, H01L27