A phase locked loop circuit

Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (221) capable of outputting a variable oscillation frequency signal. A phase detector (222) compares the output signal of the voltage control oscillator (221) with a reference signal and outputs an error signal. An integrator (223) integrates the error signal and extracts a direct current variable component which is fed by a loop filter (224) from the integrator (223) to the voltage controlled oscillator (221) as a control signal. An alternate current coupling circuit (230) is provided for adding only an alternate current component contained in the output error signal to the control signal for feeding same to the voltage controlled oscillator (221). A compensating circuit (231) is inserted in the signal path of the alternate current coupling circuit (230), the compensating circuit (231) having a cut-off frequency exceeding the cut-off frequency of the integrator (223).

Description: The present invention relates to circuit devices for implementing a generator of highly pure signals. More specificallyl the present invention relates to a phase locked loop (PLL) for use in the frequency synthesizer. Recent synthesized signal generators for a quasi-microwave region of, for example, 10 KHz to 2,700 MHz are requested not only to be multifunctional but also to suppress SSB phase noise (C/N) as low as possible in order to implement a generator of highly pure signals. To this end, a set of circuit devices, such as a frequency synthesizer, a VCO, a ALL, (a SG,) a mixer and a frequency and phase detector, which are used in a synthesized signal generator must be configured to be effective in suppressing noise individually or in combination. Moreover, the set of circuit devices must be configured to meet requirements for low noise, miniaturization and simplification. The United States Patent US-A-4,885,553 discloses a phase locked loop synthesizer in which error correction pulses from a phase detector are separated into narrow pulse width and wide pulse width pulses. The wide pulse width pulses are coupled to the loop filter to enable a rapid charge of the loop filter to provide VCO control. The narrow pulse width pulses are filtered by a narrow band filter before being applied to the loop filter, thus enabling a slow charge of the loop filter which causes only slow changes in the VCO frequency. The United States Patent US-A-4,590,602 discloses a variable rate clock recovery circuit having a PLL and a frequency synthesizer which share control of a common VCO in single loop configuration. Narrow PLL band widths and short acquisition time may be achieved by employing the frequency synthesizer to initially control the VCO to produce an estimate of the data frequency which is accurate within the bandwidth of the PLL. Once this VCO frequency is attained, the PLL disables the frequency synthesizer control of the VCO and provides fine tuning control of the VCO output frequency itself. The PLL is adapted to synchronize an oscillation signal frequency with a reference signal and finds extensive applications in frequency synthesizers, demodulators and so on. An exemplary of another known PLL is illustrated in Fig. 1. As illustrated, an output signal of a voltage controlled oscillator (VCO) 41 is applied to a phase detector 42 along with a reference signal. The phase detector 42 produces an error signal which is, in turn, amplified by a direct current amplifier 43 for application to a loop filter 44. A control voltage from the loop filter 44 always forces the frequency and phase of the VCO 41 to vary in a direction that synchronizes with the reference signal. For this reason, the VCO frequency Fo will track frequency variations of the reference signal while maintaining lock with its frequency Fr. To vary the frequency of the VCO 41 over a wide frequency band in this type of PLL, it is required that the slope of the voltage versus free-running frequency characteristic (hereinafter referred to as the VF characteristic) of the VCO 41 itself be constant over its full frequency band. However, the VF characteristic of VCOs usually has a tendency that the higher the frequency range, the smaller the slope becomes as illustrated in Fig. 2. Its gain coefficient varies as the frequency range varies as illustrated in Fig. 3. When a PLL is formed with such a VF characteristic of the VCO maintained, the loop gain varies greatly with the frequency range, thereby disabling the loop response characteristic from becoming optimized. For this reason, the gain of the direct current amplifier 43 is varied externally for each of the frequency ranges (the magnitude of a feedback resistor Rf is varied with respect to an input resistor Ri) so that the apparent gain coefficient of the VCO 41 within the loop may be constant. However, the broadband PLL with a compensating circuit consisting of the direct current amplifier 43 suffers from a problem that high frequency SSB phase noise cannot be suppressed sufficiently. This problem will be discussed below. It is generally known that the SSB phase noise characteristic of a VCO extends over a predetermined range centered at a carrier frequency and there is a difference of 6 dB between the characteristic (a) when the carrier frequency is F1 and the characteristic (b) when the carrier frequency is 2F1 as shown in Fig. 4. In controlling the VCO having such a noise characteristic with the PLL loop, a loop gain of 20 dB is required in order to obtain -120 dBc/Hz phase noise at the carrier frequency F1 and an offset frequency (a deviation from the carrier frequency) of, for example, 10 KHz. When this loop gain is maintained, the SSB phase noise of an output signal of the VCO is suppressed as shown by (c) in Fig. 4. With the direct current amplifier 43, however, its cutoff frequency lowers as its gain increases as illustrated in Fig. 5. Thus, a sufficient gain cannot be obtained in a frequency range in which a high gain is needed for compensation of the gain coefficient so that a loop gain of 6 dB needed when the carrier frequency is 2F1 becomes difficult to obtain. For this reason, the phase noise when the carrier frequency is high is not suppressed on the side of high frequencies (higher than 100 KHz in this case) in offset frequency, thereby considerably degrading the signal purity. An object of the present invention is to provide a PLL which permits a highly pure signal to be obtained over a wide range of frequencies, such that the PLL is well suited for use in a frequency synthesizer. According to the present invention, a PLL circuit is provided as defined in Claim 1. Embodiments of the PLL circuit are given in the dependent Claims 2 to 4. The invention will become more fully understood from the following detailed description of embodiments when taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of a conventional PLL circuit; Figures 2 and 3 illustrate general characteristics of the VCO used in the PLL of Figure 1; Figure 4 is a diagram illustrating noise suppression by a conventional PLL circuit; Figure 5 illustrates characteristics of a main section of a conventional PLL; Figure 6 is a block diagram of a PLL circuit according to an embodiment of the present invention; Figures 7 and 8 illustrate characteristics of the PLL circuit of Figure 6; Figure 9 is a diagram illustrating the noise suppression by the PLL circuit of Figure 6. A PLL circuit according to a preferred embodiment of the present invention will now be discussed in conjunction with Figure 6, which shows a block diagram of a frequency synthesizer using the present PLL. In the Figure, 210 designates a frequency control circuit for determining an output frequency of the PLL 220, which performs switching of frequency dividing factors of a frequency coarse adjustment circuit 225 to be described later and switching of a compensation circuit. It is assumed that a VCO 221 of the PLL 220 has the characteristics illustrated in Figs. 2 and 3. An output of the VCO 221 and a reference signal are applied to a mixer type phase detector 222. This reference signal is supplied from a separate circuit which generates a signal of a frequency Fr equal to frequency data set in the frequency control circuit 210. Reference numeral 223 designates an integrator which integrates an error signal from the phase detector 222 to output a direct current voltage and consists of an operational amplifier. The integrator 223 is made up its output phase coinciding with that of an output of an AC coupling circuit as later described. Therefore, assuming integration is performed with a single state operational amplifier, another stage operational amplifier needs to correct a converted phase of integration output. A lag-lead filter 224 is a loop filter which determines the loop response of the PLL 220 and produces a control voltage for the VCO 221. The frequency detector 225 is adapted to coarsely adjust the frequency of the VCO 221 to a specified frequency. More specifically, the frequency detector 225 comprises a frequency divider 226 for dividing the VCO output frequency and a frequency comparator 227 for making comparison between the divided VCO frequency and the reference signal frequency Fz to charge or discharge the output of the integrator 223 so that their frequency difference may become smaller than a predetermined value. 230 designates an alternating current coupling circuit which capacitively couples between the phase comparator 222 and the lag-lead filter 224 by means of capacitors C2 and C3 to send only alternating current components contained in the error signal output from the phase detector 222 to the VCO 221 via the lag-lead filter 224. Between the capacitors C2 and C3 is connected a compensation circuit 231 for uniformly compensating the gain coefficient in the loop of the VCO 221. The switching of the compensation circuit 231 is made by the frequency control circuit 210. For example, when the desired frequency Fr is set between Fa and Fb in Fig. 2, both switches Sb and Sc are kept open. With Fr set between Fb and Fc the switch Sb is closed. with Fr set between Fc and Fd, the switches Sb and SC are both closed. Resistance values Ra, Ra//Rb and Ra//Rb//Rc are set such that the gain of the VCO 221 in the vicinity of its upper and lower limits may be equal to that in the center as shown in Fig. 7. Capacitors Ca, Cb and Cc paralleled with resistors Ra, Rb and Rc are phase compensating capacitors for stabilizing the phase in the loop. The values of the capacitors C1, C2 and C3 are determined such that the AC signal passing range of the alternate current coupling circuit 230 shown at f in Fig. 8 lies above the passing range of the integrator 223 indicated at e. Thus, the pass band of signals between the phase detector 222 and the lag-lead filter 224 is substantially constant over a wide range exceeding the cutoff frequency of the integrator 223 as indicated at g in Fig. 8. Next, the operation of the frequency synthesizer will be described. When a frequency Fr (for example, Fc < Fr < Fd) is set in the frequency setting circuit 210, a frequency dividing factor N is set in the frequency divider 226 in the frequency detector 225 such that Fr = N x Fz. For this reason, the frequency Fo of the VCO 221 is forcibly controlled to fall within a range from (N-1)Fz to (N+1)Fz close to Fr, compared with the reference signal with frequency Fr in phase by the phase detector 222 and then is locked to the reference signal frequency Fr by the pull-in of the PLL. Since, at this time, the switches Sb and Sc of the compensating circuit 231 are both turned on, the apparent gain of the VCO 221 in the loop is increased by the parallel resistance value (Ra//Rb//Rc) of the resistors Ra, Rb and Rc and compensated to the same level as in the center region (Fig. 7). The gain does not depend on the characteristic of the DC loop of the integrator 223 side but remains substantially constant over a wide range of offset frequencies because of the AC loop of the AC coupling circuitry 230 side. The SSB phase noise characteristics (a) and (b) at the free-running time of the VCO 21 which vary over a range an octave or more wide are suppressed sufficiently and to a constant level as indicated at (C), thereby producing highly pure output signals. In the above embodiment, three compensating resistors Ra, Rb and Rc are used according the VF characteristic of the VCO 221. This is because the actual VF characteristic of the VCO is approximated by three straight lines. To compensate the gain more finely, the frequency range may be divided into more than three subranges to switch resistors for each of the subranges. In this case, instead of connecting resistors in parallel as in the above embodiment, an independent resistor may be connected for each of the frequency subranges. Though a lag-lead filter is used as the loop filter in the above embodiment, another type of filter may be used. In the above embodiment, the frequency detector 225 is used to synchronize the VCO output to the reference signal frequency.- This is not essential to the present invention. In the above embodiment, the VCO output is directly applied to the phase detector 222. The VCO output may be applied to the phase detector after heterodyne conversion. As described above, the PLL according to the embodiment of the present invention employs AC coupling as well as DC coupling between the phase detector and the VCO and a compensation circuit for compensating the apparent gain of the VCO in the AC loop. Therefore, the SSB phase suppression band relative to the offset frequency can easily be widened in the state in which the loop gain of the whole system is uniform, and highly pure signals can be output over a wide frequency variable range.

Claims: A PLL circuit comprising: a voltage controlled oscillator (221) responsive to a control signal to output an output signal having a variable oscillation frequency; and a phase detector (222) for making a phase comparison between the output signal from said voltage controlled oscillator (221) and a reference signal, and for outputting an output error signal; an integrator (223) for integrating the output error signal from said phase detector (222) to extract a direct current variable component contained in the output error signal, said integrator (223) having a first cutoff frequency; a loop filter (224) for feeding the direct current variable component from said integrator (223) to said voltage controlled oscillator (221) as the control signal to synchronize the output signal from said voltage controlled oscillator (221) with the reference signal; an alternate current coupling circuit (230) for adding only an alternate current component contained in the output error signal from said phase detector (222) to the control signal for feeding to said voltage controlled oscillator (221); and a compensating circuit (231) inserted in an alternate current signal path of said alternate current coupling circuit (230), said compensating circuit (231) having a second cutoff frequency exceeding the first cutoff frequency of said integrator (223), characterized in that said compensating circuit (231) includes: a plurality of parallel-connected capacitors (Ca, Cb, Cc) and resistors (Ra, Rb, Rc); and a plurality of switches (Sb, Sc) for selectively switching the plurality of parallel-connected capacitors (Ca, Cb, Cc) and resistors (Ra, Rb, Rc) into open and closed states in accordance with switching signals. A PLL circuit according to Claim 1, further comprising a frequency detector (225) for receiving the output signal from said voltage controlled oscillator (221), and coarsely adjusting the frequency of the output signal of said voltage controlled oscillator (221) in accordance with a designated frequency. A PLL circuit according to Claim 2, wherein said frequency detector (225) includes: a frequency divider (226) for dividing the frequency of the output signal from said voltage controlled oscillator (221); and a frequency comparator (227) for making a comparison between the frequency of a frequency divided signal from said frequency divider (226) and the frequency of a reference signal to control an output from said integrator (223) so that the frequency difference of the compared signals becomes smaller than a predetermined value. A PLL circuit according to one of Claims 1 to 3, wherein said loop filter (224) includes a lag-lead filter.

Inventors: MOTOYAMA HATSUO, SAEKI HIROSHI, MOTOYAMA, HATSUO, SAEKI, HIROSHI, SAEKI, HIROSHI, ANRITSU OKIHARA-RYOU
Applicants: ANRITSU CORP, ANRITSU CORPORATION
Application year: 1990
Main classification: H03L7
IPC codes: H03L7, H03B5, H03B1, H03B19, H03B21