Method of manufacturing a semiconductor integrated circuit device

Abstract: There is disclosed a method of manufacturing an integrated circuit, comprising: the first step of growing a first epitaxial crystal on a compound semiconductor substrate (1), removing an unnecessary region of the first epitaxial crystal to form a residual portion (5), and covering the residual portion (5) with a selective growth mask (6), the second step of growing a second epitaxial crystal on an exposed substrate portion (1), removing an unnecessary portion of the second epitaxial crystal to form a residual portion (15) of the second epitaxial crystal, and covering the residual portion (15) of the second epitaxial crystal with a selective growth mask (19), and the third step of growing a third epitaxial crystal (11) on an exposed substrate portion (1) and removing an unnecessary region of the third epitaxial crystal (11), wherein the first to third epitaxial crystal (5,15,11) form any one of a pin photodiode crystal (16), a heterojunction bipolar transistor crystal (17), and a high electron mobility transistor crystal (18), and are different from each other.

Description: BACKGROUND OF THE INVENTION (Field of the Invention) The present invention relates to a method of manufacturing a semiconductor integrated circuit device having, as basic elements, optical and electronic elements integrated to form an opto-electrical semiconductor integrated circuit used for optical fiber communication and the like. (Related Background Art) A structure obtained by integrating pin photodiodes (PIN-PDs) as light-receiving elements and field effect transistors (FETs) as electronic elements on a substrate is known as a reception front end in optical fiber communication. Another conventional structure is also known in which PIN-PDs and FETs are monolithically formed on an InP substrate. DE-A-3 712 864 shows an integrated PIN-PD and HEMT structure, and its fabrication. The structure having the light-receiving and electronic elements formed on a substrate is formed by soldering the respective elements on the substrate. Reliability of this structure is poorer than a monolithic structure, and the hybrid type structure is not suitable for mass production. The conventional monolithic structure described above does not have bipolar transistors. A reception front end in optical fiber communication preferably has FETs having a high input impedance and low shot noise at its first signal amplification stage. In the subsequent stages, bipolar transistors having a large transconductance are preferably used. Therefore, strong demand has arisen for a monolithic semiconductor integrated circuit in which PIN-PDs, FETs, and bipolar transistors are formed on a single substrate, but such a semiconductor integrated circuit has not yet been developed. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit in which PIN-PDs, FETs, and bipolar transistors are monolithically formed on a single semiconductor substrate. This object of the present invention is achieved by a method according to claim 1 or claim 2. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view showing an example of a semiconductor integrated circuit device which can be obtained by a method of manufacturing a semiconductor integrated circuit device according to the present invention; Figs. 2A to 2I are sectional views for explaining the steps in manufacturing a semiconductor integrated circuit device according to figure 1; Figs. 3A to 3I are sectional views for explaining alternative steps in manufacturing a semiconductor integrated circuit device according to figure 1; Figs. 4A to 4I are sectional views for explaining the steps in a third process for manufacturing a semiconductor integrated circuit device according to figure 1; Figs. 5A to 5D are sectional views for explaining the steps in a fourth process for manufacturing a semiconductor integrated circuit device according to figure 1; Figs. 6A to 6D are sectional views for explaining the steps in a fifth process for manufacturing a semiconductor integrated circuit device according to figure 1; Figs. 7A to 7D are sectional views for explaining the steps in manufacturing a semiconductor integrated circuit device according to a method of the first embodiment of the present invention; and Figs. 8A to 8D are sectional views for explaining the steps in manufacturing a semiconductor integrated circuit device according to a method of the second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1 shows a sectional structure of an example of a semiconductor integrated circuit device which can be manufactured by a method of manufacturing a semiconductor integrated circuit device according to the present invention. As shown in Fig. 1, epitaxial crystals for a PIN-PD 16, a high electron mobility transistor (HEMT) 18 as a kind of FET, and a heterojunction bipolar transistor (HBT) 17 are monolithically formed on an indium phosphide (InP) substrate 1. The epitaxial crystals for PIN-PD 16, HEMT 18 and HBT 17 are respectively constructed by semiconductor layers 2,3 and 4, semiconductor layers 13 and 14, and semiconductor layers 7, 8, 9 and 10. Further electrodes 22 and 23 for PIN-PD 16 are as shown in Fig. 1 formed on the semiconductor layers 4 and 2, electrodes 24, 25 and 26 for HEMT 18 are formed on the layer 14, and electrodes 27, 28 and 29 are formed on the epitaxial layers 10, 9 and 7. Organic metal vapor phase epitaxy (OMVPE) as an epitaxial growth method of forming the above epitaxial crystals is performed at a low pressure of 100 Torr or less (1 Torr = 133.3 Pa) which exhibits good selective growth. A substrate temperature is set to be about 600 °C to 700 °C, and reaction gases are properly selected in accordance with semiconductor layers to be formed. Semiconductor layers formed by epitaxial growth are an InP layer, a gallium-indium arsenide (GaInAs) layer, and an aluminum-indium arsenide (AlInAs) layer. These semiconductor layers are selectively used in accordance with the types of elements. Thrimethylindium (TMI), phosphine (PH 3 ), and arsine (AsH 3 ) are used as reaction gases in epitaxial growth of an InP layer. Trimethylgallium (TMG), trimethylindium (TMI), and arsine (AsH 3 ) are used as reaction gases in epitaxial growth of a GaInAs layer. Trimethylaluminum (TMA), trimethylindium (TMI), and arsine (AsH 3 ) are used as reaction gases in epitaxial growth of an AlInAs layer. The epitaxial crystals for PIN-PD 16, HEMT 18 and HBT 17 are independently formed and when one of the crystals is formed, the others are covered by a selective growth mask. A silicon nitride (SiN x ) film or a silicon oxide (SiO 2 ) film is used as the selective growth mask to be described below. The steps in manufacturing a semiconductor integrated circuit device shown in Fig. 1 according to one possible method will be described with reference to Figs. 2A to 2I. In this method, the PIN-PD 16, the HEMT 18, and the HBT 17 are formed in the order named. Epitaxial growth for PIN-PD formation is performed on the prepared InP substrate 1. In this case, an n-type GaInAs layer 2, an i-type GaInAs layer 3, and a p-type GaInAs layer 4 are formed in the order named (Fig. 2A). Mesa etching is performed such that the epitaxial layers 2 and 3 are left on only a prospective PIN-PD formation region 5 (Fig. 1). For this purpose, a silicon nitride film is formed on the entire surface of the substrate by, e.g., electron cyclotron resonance plasma chemical vapor deposition (ECR plasma CVD). A resist pattern is formed on the surface of the prospective PIN-PD region 5, and the silicon nitride film is etched with hydrofluoric acid (HF) by using the resist pattern as a mask. The epitaxial layers 2 and 4 are sequentially etched using the residual silicon nitride film and the residual resist pattern on the prospective PIN-PD region 5 as masks. The resist pattern and the residual silicon nitride film which are used as the masks are removed to form the PIN-PD crystal 16 (Fig. 2B). A selective growth mask 6 made of a silicon nitride or oxide film is formed in the PIN-PD region 5. This mask 6 is formed by growth by means of ECR plasma CVD and patterning using a resist pattern in the same manner as the silicon nitride masks as in the above mesa etching (Fig. 2C). Selective epitaxial growth for an HEMT is then performed. More specifically, an i-type GaInAs layer 13 serving as an active layer and an n-type AlInAs layer 14 serving as an electron donor layer are sequentially formed on the entire surface except for the selective growth mask 6 (Fig. 2D). Mesa etching is performed to leave the epitaxial layers 13 and 14 on only a prospective HEMT formation region 14, thereby forming an HEMT crystal 18 (Fig. 2E). This mesa etching is the same as that in the PIN-PD region 5 and includes the step of forming a silicon nitride or oxide film by ECR plasma CVD, the step of patterning the silicon nitride or oxide film, and the etching step using the patterned film. A selective growth mask 19 consisting of a silicon nitride or oxide film is formed in the prospective HEMT region 15. The selective growth mask 6 is left in the PIN-PD region 5. The selective growth mask 19 is also formed by film formation by means of ECR plasma CVD and patterning using a resist pattern as a mask (Fig. 2F). Selective epitaxial growth for an HBT is then performed. An n + -type GaInAs layer 7, an n-type GaInAs layer 8, a p-type GaInAs layer 9, and an n-type InP layer 10 are formed on the entire surface except for the selective growth masks 6 and 19(Fig. 2G). Mesa etching is performed to leave an HEMT crystal 17 in an HBT region 11 as in the HEMT region 15 (Fig. 2H). Finally, the selective growth masks 6 and 19 are removed to form the PIN-PD crystal 16, the HBT crystal 17, and the HEMT crystal 18 respectively in the regions 5, 11, and 15. (Fig. 2I). The respective epitaxial layers of the crystals 16, 17 and 18 are selectively etched to form the PIN-PD, HBT and HEMT device and thereafter electrodes 22 to 29 are, as shown in Fig. 1 formed to finish the semiconductor integrated circuit. A p-type base layer (i.e., the p-type GaInAs layer 9 in the first embodiment) of the HBT is generally doped with an impurity at a concentration of 10 18 cm -3 or more. The impurity used as a p-type dopant such as zinc (Zn) and berrylium (Be) can be easily diffused at a high temperature. When the p-type dopant of the HBT is diffused in the n-type emitter (i.e., the n-type InP layer 10 in this embodiment), a p-n junction, i.e., an emitter-base junction is formed in the emitter. High emitter injection efficiency by a heterojunction may be disadvantageously lost. When the p-type dopant is diffused in the collector (i.e., the n-type GaInAs layer 8 in this embodiment), the thickness of the base layer is substantially increased, and the carrier travel time in the base layer may be prolonged, thereby often degrading the high-frequency characteristics (i.e., a decrease in cutoff frequency f T ). According to this method, the HBT crystal 17 is formed after formation of the PIN-PD crystal 16 and the HEMT crystal 18. In other words, no epitaxial growth for other elements is performed after formation of the HBT crystal 17. Therefore, the HBT crystal 17 is not exposed to high temperatures. The p-type dopant is not diffused from the base layer to the emitter and collector layers, and the high-frequency characteristics are not degraded. According to this method of manufacturing the semiconductor integrated circuit, the HBT crystal does not receive heat generated in epitaxial growth for forming other element crystals. The dopant in the base layer is not diffused into the emitter and collector layers. Therefore, the HBT can be monolithically formed together with the PIN-PD and the HEMT on a single substrate without degrading high emitter injection efficiency and high-frequency characteristics of the HBT. Another method of manufacturing the semiconductor integrated circuit device shown in Fig. 1 will be described with reference to Figs. 3A to 3I. An order of formation of epitaxial crystals 16 to 18 for PIN-PD, HBT, and HEMT is different from that in the first embodiment. More specifically, the HEMT epitaxial crystal 18, the PIN-PD epitaxial crystal 16, and the HBT epitaxial crystal 17 are formed in the order named. The alternative steps in manufacturing the semiconductor integrated circuit device of Fig. 1 will be described in detail with reference to Figs. 3A to 3I. Epitaxial growth for forming an HEMT 18 is performed on a prepared InP substrate 1. An i-type GaInAs layer 13 serving as an active layer and an n-type AlInAs layer 14 serving as an electron donor layer are sequentially formed on the substrate 1 (Fig. 3A). Mesa etching is performed to leave the epitaxial layers 13 and 14 only in a prospective HEMT region 15. More specifically, a silicon nitride film is formed on the entire surface of the substrate by electron cyclotron resonance plasma chemical vapor deposition (ECR plasma CVD). A resist pattern is formed on the surface of the prospective HEMT region 15, and the silicon nitride film is etched with hydrofluoric acid (HF) by using the resist pattern as a mask. The epitaxial layers 13 and 14 are sequentially etched using the residual silicon nitride film and the resist pattern left on the prospective HEMT region 15 as masks. The resist pattern and the residual silicon nitride film used as the masks are removed to form an HEMT crystal 18 (Fig. 3 B). A selective mask 19 made of a silicon nitride or oxide film is formed in the HEMT region 15. This selective growth mask 19 is formed by the growth by means of ECR plasma CVD and patterning using a resist pattern as in the silicon nitride mask in the above mesa etching (Fig. 3C). Selective epitaxial growth for a PIN-PD is performed. More specifically, an n-type GaInAs layer 2, an i-type GaInAs layer 3, and a p-type GaInAs layer 4 are sequentially formed except for the selective growth mask 19 (Fig. 3D). Mesa etching is performed to leave the epitaxial layers 2 and 4 in only a prospective PIN-PD region 5, thereby forming a PIN-PD crystal 16 (Fig. 3E). This mesa etching method is the same as that for the HEMT 18 and includes the step of forming a silicon nitride or oxide film by ECR plasma CVD, the step of patterning the silicon nitride or oxide film, and the etching step using the patterned film as a mask. A selective growth mask 6 consisting of a silicon nitride or oxide film is formed in the PIN-PD region 5. In this case, the selective growth mask 19 is left in the HEMT region 15. The selective growth mask 6 is formed by film formation by means of ECR plasma CVD and patterning using a resist pattern as in the selective growth mask 19 (Fig. 3F). Selective epitaxial growth for an HBT is then performed. More specifically, an n + -type GaInAs layer 7, an n-type GaInAs layer 8, a p-type GaInAs layer 9, and an n-type InP layer 10 are sequentially formed on the entire surface except for the selective growth masks 6 and 19 (Fig. 3G). Mesa etching is performed to leave an HBT crystal 17 in an HBT region 11 in the same manner as in the PIN-PD region 5 (Fig. 3H). Finally, the selective growth masks 6 and 19 are removed to form the PIN-PD crystal 16, the HBT crystal 17, and the HEMT crystal 18 in the regions 5, 11, and 15 (Fig. 3I). The respective epitaxial layers of the crystals 16, 17 and 18 are selectively etched to form the PIN-PD, HBT and HEMT device and thereafter the electrodes 22 to 29 are, as shown in Fig. 1, formed to finish the semiconductor integrated circuit. When epitaxial growth is performed on the entire surface of the substrate, the surface is etched by an appropriate etchant (e.g., sulfuric acid for an InP substrate) to expose a clean surface, and then crystal growth is performed. For this reason, a good epitaxial layer having a concentration of 1 x 10 15 cm -3 or less can be obtained. To the contrary, when selective growth is performed, a selective growth mask consisting of silicon nitride or oxide is already formed on the surface of the substrate. For this reason, the selective growth mask becomes a contamination source, and it is not easy to set an impurity concentration of 1 x 10 16 cm -3 or less. In an HEMT having an n-type AlInAs/GaInAs epitaxial layer, when the impurity concentration in the GaInAs layer exceeds 1 x 10 16 cm -3 , a current tends to flow in not only the secondary electron layer but also the GaInAs layer. There is a fear of an increase in drain conductance in the drain I-V characteristics and degradation of pinch-off characteristics. As compared with this degradation, an influence of the selective growth mask on other elements, i.e., the HBT and the PIN-PD is smaller than that on the HEMT. In this second method, epitaxial growth of the HEMT crystal is performed prior to epitaxial growth of the HBT and PIN-PD crystals. That is, the HEMT crystal is formed on a clean substrate on which a selective growth mask is not formed. Therefore, the impurity concentration in the GaInAs layer can be decreased to a sufficiently low level, an good drain I-V characteristics can be obtained. In the second method, after the HEMT crystal 18 is formed, the PIN-PD crystal 16 and the HBT crystal 17 are formed in the order named. However, if the HEMT crystal 18 is formed prior to other element crystals, the formation order of the PIN-PD crystal 16 and the HBT crystal 17 may be reversed. According to the second method of manufacturing the semiconductor integrated circuit, the HEMT, the HBT, and the PIN-PD having different epitaxial structure are monolithically formed. In addition, since epitaxial growth for the HEMT crystal is performed on a clean substrate on which a selective growth mask is not formed, the impurity concentration of the active layer of the HEMT crystal can be reduced to a low level. Therefore, a semiconductor integrated circuit comprising an HEMT having a low drain conductance and good pinch-off characteristics can be obtained. A still further method of manufacturing the semiconductor integrated circuit device shown in Fig. 1 will be described in detail with reference to Figs. 4A to 4I. A formation order of a PIN-PD, an HBT, and an HEMT is different from those of the first and second embodiments. That is, a PIN-PD epitaxial crystal 16, and HBT epitaxial crystal 17, and an HEMT epitaxial crystal 18 are formed in the order named. The steps in manufacturing the semiconductor integrated circuit device according to the third method will be described with reference to Figs. 4A to 4I. Epitaxial growth for forming a PIN-PD is performed on a prepared InP substrate 1. More specifically, an n-type GaInAs layer 2, an i-type GaInAs layer 3, and a p-type GaInAs layer4 are sequentially formed on the InP substrate 1 (Fig. 4A). Mesa etching is performed to leave the epitaxial layers 2 and 3 in only a prospective PIN-PD region 5. A silicon nitride film is formed on the entire surface of the substrate by, e.g., electron cyclotron resonance plasma chemical vapor deposition (ECR plasma CVD). A resist pattern is formed on the surface of the PIN-PD region 5, and the silicon nitride film is etched with hydrofluoric acid (HF) by using this resist pattern as a mask. The epitaxial layers 2 and 4 are sequentially etched using the residual silicon nitride film and the resist pattern left in the PIN-PD region 5 as masks. The resist pattern and the residual silicon nitride film used as the mask are removed to form a PIN-PD crystal 16 (Fig. 4B). A selective growth mask 6 consisting of a silicon nitride or oxide film is formed in the PIN-PD region 5. This selective growth mask 6 is formed by growth by means of ECR plasma CVD and patterning using a resist pattern (Fig. 4C). Selective epitaxial growth for an HBT is performed. More specifically, an n + -type GaInAs layer 7, an n-type GaInAs layer 8, a p-type GaInAs layer 9, and an n-type InP layer 10 are sequentially formed on the entire surface except for the selective growth mask 6 (Fig. 4D). Mesa etching is performed to leave the epitaxial layers 7 to 10 on a prospective HBT region 11, thereby forming an HBT crystal 17 (Fig. 4E). This mesa etching method is the same as that for the PIN-PD region 5 and includes the step of forming a silicon nitride or oxide film by ECR plasma CVD, the step of patterning the silicon nitride or oxide film, and the etching step using the pattern film as a mask. A selective growth mask 12 consisting of a silicon nitride or oxide film is formed in HBT region 11. In this case, the selective growth mask 6 is left in the PIN-PD region 5. The selective growth mask 12 is formed by film formation by means of ECR plasma CVD and patterning using a resist pattern as in the selective growth mask 6 (Fig. 4F). Selective epitaxial growth for an HEMT is performed. More specifically, an i-type GaInAs layer 13 serving as an active layer and an n-type AlInAs layer 14 serving an electron donor layer are sequentially formed on the entire surface except for the selective growth masks 6 and 12 (Fig. 4G). Mesa etching is performed to leave the HEMT crystal 18 in an HEMT region 15 as in the HBT region 11 (Fig. 4H). Finally, the selective growth masks 6 and 12 are removed to form the PIN-PD crystal 16, the HBT crystal 17, and the HEMT crystal 18 respectively in the regions 5, 11, and 15 (Fig. 41). The respective epitaxial layers of the crystals 16, 17 and 18 are selectively etched to form the PIN-PD, HBT and HEMT device and thereafter the electrodes 22 to 29 are, as shown in Fig. 1, formed to finish the semiconductor integrated circuit. The electrodes formed on the surface of the HBT crystal 17 and the surface of the PIN-PD crystal 16 are ohmic contacts. More specifically, an emitter electrode is formed on the surface of the n-type InP layer 10 as the uppermost layer of the HBT crystal 17, and an electrode serving as an anode is formed on the p-type GaInAs layer 4 as the uppermost layer of the PIN-PD crystal 16. In addition to the source and drain electrodes as ohmic contact electrodes, a Schottky gate electrode is formed on the n-type AlInAs layer 14 as the uppermost layer of the HEMT crystal 18. The characteristics of the Schottky gate electrode are very sensitive to crystallinity of the crystal surface. That is, when quality of the crystal surface is poor, a reverse current (i. e., a gate leakage current) may be increased, and shot noise of the semiconductor integrated circuit may be increased. When a silicon nitride or oxide film serving as a selective growth mask is formed, crystal defects are formed in this film. When selective growth of an epitaxial layer is performed in a state wherein a selective growth mask is formed, crystal defects are formed due to a difference between thermal expansion coefficients of the silicon nitride or oxide film and the epitaxial layer during heating or cooling. The silicon nitride or oxide film may react with the epitaxial layer by heat during the growth to cause diffusion of atoms. In this manner, the selective growth mask may degrade the crystal quality of the surface on which it is formed. In the third method, since the HEMT crystal 18 is formed after the PIN-PD crystal 16 and the HBT crystal 17 are formed, the selective growth mask is not formed on the HEMT crystal 18 which causes surface quality to adversely affect element characteristics. Degradation of crystal quality caused by a selective growth mask does not occur on the surface of the HEMT crystal. Therefore, the gate leakage current of the Schottky gate electrode can be minimized. According to the third method of manufacturing the semiconductor integrated circuit, since no selective growth mask is formed on the HEMT crystal, the surface crystal state can be kept excellent. Therefore, a reverse current of the Schottky gate electrode formed on the surface crystal can be minimized, and a semiconductor integrated circuit having good noise characteristic can be obtained. A fourth method of manufacturing a semiconductor integrated circuit device will be described with reference to Figs. 5A to 5D. According to the fourth method, as shown in Fig. 5A, epitaxial crystal layers constituting an HEMT epitaxial crystal are formed on an indium phosphide (InP) semiconductor substrate 1, and then a PIN-PD region 5 and an HBT region 11 are selectively etched. A PIN-PD epitaxial crystal 16 and an HBT crystal 17 are formed in the regions 5 and 11, respectively. An HEMT epitaxial crystal 18 is formed in an HEMT region 15. The HEMT crystal 18 consists of a GaInAs layer 13 serving as an active layer and an n-type AlInAs layer 14 serving as an electron donor layer. The PIN-PD crystal 16 consists of an n-type InP layer 2 serving as an n-type layer, an i-type GaInAs layer 3 serving as an i-type layer, and a p-type InP layer 4 serving as a p-type layer. The HBT crystal 17 consists of an n-type InP layer 7 serving as a subcollector layer, an n-type GaInAs layer 8 serving as a collector layer, a p-type GaInAs layer 9 serving as a base layer, and an n-type Inp layer 10 serving as an emitter layer. At the time of formation of the HEMT crystal 18, the GaInAs layer and the n-type AlInAs layer which constitute the HEMT crystal are also formed in an HEMT unnecessary region 30. A technique for forming the above epitaxial crystals is the same as those described with reference to the first to third methods above. That is, a conventional epitaxial growth technique and a conventional selective growth technique can be used. In the fourth method, the HEMT epitaxial crystal is formed first. However, the PIN-PD or HBT epitaxial crystal layer may be formed first. A resist is applied to the substrate, the entire surface of which is deposited with a silicon nitride film. The resist is patterned using a photolithographic technique. The silicon nitride film is then patterned using the resist pattern as a mask, thereby forming etching masks 16a and 17a consisting of the patterned silicon nitride and resist films, respectively. The masks 16a and 17a may consists of silicon oxide in place of silicon nitride. The p-type layer 4 of the PIN-PD crystal 16 and the emitter layer 10 of the HBT crystal 17 are etched while parts of them are shielded by the masks 16a and 17a (Fig. 5B). At this time, an etchant such as HCl:H 3 PO 4 having selectivity for etching InP but not etching GaInAs and AlInAs is used. That is, selective etching is performed, so that etching of the p-type layer 4 and the emitter layer 10 is automatically stopped. Masks 20 and 21 each consisting of a silicon nitride patter (or a silicon oxide pattern) and a resist pattern are formed in predetermined portions of the HEMT region 15 and the HBT region 11, respectively. Etching is performed by shielding predetermined portion with the masks 16a, 20, and 21, thereby selectively removing the i-type layer 3 of the PIN-PD crystal 16, the base layer 8 of the HBT crystal 17, and the electron donor layer 14 and the active layer 13 of the HEMT crystal 18 (including the HEMT unnecessary region) (Fig. 5C). At this time, an etchant such as H 2 SO 4 :H 2 O 2 having selectivity for etching GaInAs and AlInAs but not etching InP is used. That is, selective etching is performed, so that etching of the i-type layer 3, the base layer 8, the collector layer 9, the electron donor layer 14, and the active layer 13 is automatically stopped. If the subcollector layer 7 of the HBT crystal 17 and the n-type layer 2 of the PIN-PD crystal 16 do not consist of InP but GaInAs, the above etching operation must be stopped when either of the layers 7 and 2 is exposed. Since the thickness of the i-type layer of the PIN-PD crystal is generally 2 µm or more, and a total thickness of the base and collector layers of the HBT crystal is generally 1 µm or less, a time required for exposing the n-type layer of the PIN-PD crystal is different from that required for exposing the subcollector layer of the HBT crystal. The n-type layer of the PIN-PD crystal and the subcollector layer of the HBT crystal cannot, therefore, be simultaneously exposed. More specifically, in the fourth method, since the n-type layer of the PIN-PD crystal and the subcollector layer of the HBT crystal consist of InP and the electron donor and active layers of the HBT crystal respectively consist of n-type AlInAs and GaInAs, so-called selective etching can be performed. The i-type layer 3 of the PIN-PD crystal 16, the base layer 8 of the HBT crystal, and HEMT crystal portions corresponding to the collector layer 9 and the unnecessary region 30 can be selectively and simultaneously etched. After the etching process described above is completed, a p- and n-type electrodes 22 and 23 of the PIN-PD crystal, source, drain, and gate electrodes 24, 25, and 26 of the HEMT crystal, and emitter, base, and collector electrodes 27, 28, and 29 of the HBT crystal are formed (Fig. 5D), and necessary wiring is performed to finish a desired semiconductor integrated circuit. Figs. 6A to 6D are sectional views showing the steps in manufacturing a semiconductor integrated circuit according to a fifth method. The semiconductor integrated circuit obtained by the fifth method is substantially the same as that by the fourth method above except that a p-type layer of a PIN-PD crystal does not consist of InP but GaInAs. The same reference numerals as in the fourth method denote the same parts in the fifth method, and a detailed description thereof will be omitted. A PIN-PD crystal 105, an HEMT crystal 18, and an HBT crystal 17 are formed on an InP substrate 1 (Fig. 6A), and a mask 17a including a resist film and a silicon nitride film is formed on an emitter layer 10 of the HBT crystal 17. Selective etching is performed while a predetermined portion is shielded by the mask 17a, thereby exposing a base layer 8 of the HBT crystal 17(Fig. 6B). Masks 16a, 20, and 21 each including a resist film and a silicon nitride film are formed, and selective etching is performed while a desired portion is shielded by these masks. An i-type layer 3 of the PIN-PD crystal 105, the base layer 8 of the HBT crystal, and the HEMT crystal portion in an unnecessary region 30 are selectively etched (Fig. 6C). Electrodes 22 to 29 are formed (Fig. 6D), and finally wiring is performed to finish a desired semiconductor integrated circuit. According to each of the fourth and fifth methods of manufacturing the integrated circuits of figure 1, the i-type layer (both the p- and i-type layers if the p-type layer consists of GaInAs) of the PIN-PD crystal, the base and collector layers of the HBT crystal, and the HEMT crystal portion of the unnecessary region can be simultaneously etched without strictly controlling the etching time. Therefore, a semiconductor integrated circuit including PIN-PDs, HEMTs, and HBTs can be manufactured within a short period of time. Note that the materials for a substrate and epitaxial growth layer are not limited to the particular embodiments described above, but can be arbitrarily selected. A method of manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to Figs. 7A to 7D. Following the same procedures as in the fourth method above, a PIN-PD epitaxial crystal 16, an HEMT epitaxial crystal 18, and an HBT epitaxial crystal 17 are respectively formed in a PIN-PD region 5, and HEMT region 15, and an HBT region 11 on an indium phosphide (InP) semiconductor substrate 1 in the first embodiment, as shown in Fig. 7A. The thicknesses of the epitaxial crystals formed in these regions satisfy the following inequalities: 0.9d 1 < d 2 + d 3 < 1.1d 1 d 4 + d 5 < d 1 Where d 1 is the thickness of an i-type layer 3 of the PIN-PD crystal 16, d 2 is the thickness of a base layer 8 of the HBT crystal 17, d 3 is the thickness of a collector layer 9 of the HBT crystal 17, d 4 is the thickness of an electron donor layer 14 of the HEMT crystal 18, and d 5 is the thickness of an active layer 13 of the HEMT crystal 18. Inequality (1) indicates that epitaxial growth is performed such that a total thickness of the base layer 8 and the collector layer 9 is set to be almost equal to the thickness of the i-type layer 3. Inequality (2) indicates that a total thickness of the electron donor layer 14 and the active layer 13 is set to be smaller than the thickness of the i-type layer 3. Following the same procedures as in the fourth method described with reference to Fig. 5B, a semiconductor integrated circuit device (Fig. 7A) having a sectional shape (Fig. 7B) is manufactured. Following the same procedures as in the fourth method described with reference to Fig. 5B, a semiconductor integrated circuit device (Fig. 7A) having a sectional shape (Fig. 7C) is manufactured. In this case, an etchant such as H 2 SO 4 :H 2 O 2 is used for both GaInAs and AlInAs. The etching time must be controlled in accordance with the thicknesses of the epitaxial layers and their etching rates. However, since the thicknesses of the epitaxial layers to be etched are determined to satisfy inequalities (1) and (2), the n-type layer 2 of the PIN-PD crystal 16 and the subcollector layer 7 of the HBT crystal 17 are almost simultaneously exposed. Upon exposure of the layers 2 and 7, the HEMT crystal portion of an unnecessary region 30 is perfectly removed. After the etching process is completed, a p-type electrode 22 and an n-type electrode 23 of the PIN-PD crystal, a source electrode 24, a drain electrode 25, and a gate electrode 26 of the HEMT crystal, and an emitter electrode 27, a base electrode 28, and a collector electrode 29 of the HBT crystal are formed (Fig. 7D), and necessary wiring is performed to finish a desired integrated circuit. Figs. 8A to 8D are sectional views for explaining the steps in manufacturing a semiconductor integrated circuit device according to a method of the second embodiment of the present invention. This embodiment is substantially the same as the first embodiment except that a p-type layer of a PIN-PD crystal does not consist of InP but GaInAs. The same reference numerals as in Figs. 7A to 7D denotes the same parts in Figs. 8A to 8D, and a detailed description thereof will be omitted. A PIN-PD crystal 105, an HEMT crystal 18, and an HBT crystal 17 are formed on an InP substrate 1 (Fig. 8A). At this time, the thicknesses of epitaxial layers are determined to satisfy the following inequalities: 0.9d 6 < d 2 + d 3 < 1.1d 6 d 4 + d 5 < d 6 where d 6 is the total thickness of an i-type layer 3 and a p-type layer 112 of the PIN-PD crystal 105, d 2 is the thickness of a base layer 8 of the HBT crystal 17, d 3 is the thickness of a collector layer 9 of the HBT crystal 17, d 4 is the thickness of an electron donor layer 14 of the HEMT crystal 18, and d 5 is the thickness of an active layer 13 of the HEMT crystal 18. The meanings of these inequalities are the same as those of inequalities (1) and (2) described above. A mask 17a including a resist film and a silicon nitride film is formed on an emitter layer 10 of the HBT crystal 17, and selective etching is performed while a predetermined area is shielded with the mask 17a, thereby exposing the base layer 8 of the HBT crystal 17 (Fig.8B). Masks 16a, 20 and 21 each including a resist film and a silicon nitride film are formed, and etching is performed while a desired area is shielded with these masks, thereby selectively etching the p- and i-type regions 112 and 3 of the PIN-PD crystal 105, the base and collector layers 8 and 9 of the HBT crystal 17, and an HEMT crystal portion of an unnecessary region 30 are simultaneously and selectively etched (Fig. 8C). Since the thicknesses of the respective epitaxial layers are determined to satisfy inequalities (3) and (4), the n-type layer 2 of the PIN-PD crystal 105 and the subcollector layer 7 of the HBT crystal 17 are almost simultaneously exposed. Upon exposure of these layers 2 and 7, the HEMT crystal portion corresponding to the unnecessary region 30 can be perfectly removed. thereafter, necessary electrodes 22 to 29 are formed (Fig. 8D), and finally wiring is performed to finish a desired semiconductor integrated circuit. According to the methods of the first and second embodiments, the i-type layer (p- and i-type layers if the i-type layer of the PIN-PD crystal consists of GaInAs), the base and collector layers of the HBT crystal, and the electron donor and active layers of the HEMT crystal are set to satisfy the predetermined relations. When these layers are almost simultaneously etched, the n-type layer of the PIN-PD crystal is exposed almost simultaneously with the subcollector layer of the HBT crystal. At the same time, the HEMT crystal portion corresponding to the unnecessary region is perfectly removed. That is, exposure of the n-type layer of the PIN-PD crystal, exposure of the subcollector layer of the HBT crystal, and removal of the HBT crystal portion corresponding to the unnecessary region are achieved by one etching process. Therefore, a semiconductor integrated circuit including PIN-PDs, HEMTs, and HBTs can be manufactured within a short period of time.

Claims: A method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming a pin photodiode crystal (16), the p-type layer (4) of which consists of InP and n- and i-type layers (2, 3) of which consist of GaInAs, a high electron mobility transistor crystal (18), the electron donor layer (14) of which consists of AlInAs and the active layer (13) of which consists of GaInAs, and a heterojunction bipolar transistor crystal (17), the emitter layer (10) of which consists of InP, and the subcollector, collector, and base layers (7, 8, 9) of which consist of GaInAs, the pin photodiode, the high electron mobility transistor, and heterojunction bipolar transistor crystals (16, 18, 17) being formed on an InP semiconductor substrate (1) so as to satisfy the following conditions: 0.9d 1 < d 2 + d 3 < 1.1d 1 d 4 + d 5 < d 1 where d 1 is the thickness of the i-type layer (3); d 2 is the thickness of the base layer (9); d 3 is the thickness of the collector layer (8); d 4 is the thickness of the electron donor layer (14); and d 5 is the thickness of the active layer (13); partially etching the p-type and emitter layers (4, 10) simultaneously to partially expose the i-type and base layers (3, 9); partially etching the i-type layer (3), the base layer (9), the collector layer (8), the electron donor layer (14), and the active layer (13) simultaneously to expose the n-type and subcollector layers (2, 7) and leave only a necessary region of the high electron mobility transistor; and forming necessary electrodes (22, 23; 24 to 26; 27 to 29) on the p- and n-type layers (4, 2), on the electron donor layer (14), and on the emitter, base, and subcollector layers (10, 9, 7). A method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming a pin photodiode crystal (105), the p-, i- and n-type layers (112, 3, 2) of which consist of GaInAs, a high electron mobility transistor crystal (18), the electron donor layer (14) of which consists of AlInAs and the active layer (13) of which consists of GaInAs, and a heterojunction bipolar transistor crystal (17), the emitter layer (10) of which consists of InP, and the subcollector (7), collector (8), and base layers (9) of which consist of GaInAs, the pin photodiode, high electron mobility transistor, and heterojunction bipolar transistor crystals (105, 18, 17) being formed on an InP semiconductor substrate (1) so as to satisfy the following conditions: 0.9d 6 < d 2 + d 3 < 1.1d 6 d 4 + d 5 < d 6 where d 2 is the thickness of the base layer (9); d 3 is the thickness of the collector layer (8); d 4 is the thickness of the electron donor layer (14); d 5 is a thickness of the active layer (13); and d 6 is a total thickness of the p- and i-type layers (112, 3); partially etching the emitter layer (10) to partially expose the base layer (9); partially etching the p-type layer (112), the i-type layer (3), the base layer (9), the collector layer (8), the electron donor layer (14), and the active layer (13) simultaneously to partially expose the n-type layer (2) and the subcollector layer (7) and to leave only a necessary region of the high electron mobility transistor crystal (18); and forming necessary electrodes (22, 23; 24 to 26; 27 to 29)on the p- and n-type layers (112, 2), on the electron donor layer (14), and on the emitter, base, and subcollector layers (10, 9, 7).

Inventors: SASAKI GORO, SASAKI, GORO, SASAKI, GORO, C/O YOKOHAMA WORKS
Applicants: SUMITOMO ELECTRIC INDUSTRIES, SUMITOMO ELECTRIC INDUSTRIES, LTD.
Application year: 1990
Main classification: H01L27
IPC codes: H01L21, H01L27, H01L31