Modulator

Abstract: In a modulator for converting two digital signals of I channel and Q channel in base band into analog signals and for converting a component of the signals whose phase is the same as a carrier and another component of the signals whose phase is orthogonal to the carrier so as to produce an orthogonally modulated wave, the two digital signals are connected to one signal train by time-sharing and multiplexing them and the converted analog signals are separated to two analog signals for the I channel and the Q channel and thereby a digital modulator can be structured by using only one digital/analog converter (15) resulting in reducing the adjustment points and the production cost.

Description: The present invention relates to a digital modulator. Thus far, modulators for modulating carriers using digital signals in the base band and for obtaining IF (RF) band modulation signals use an analog signal process. Figure 12 is view showing general structure of an orthogonal modulator for processing analog signals, such as that disclosed in EP-A-0144083. Digital input signals which are input from an I channel data input point I and a Q channel data input point 2 are converted into analog signals by D/A converters 4 and 5 via digital signal processing section 3, respectively. After that, the signals pass through (operational) amplifiers 6 and 7 and low pass filters 8 and 9, respectively. Then, a component of the signals, whose phase is the same as a reference carrier 12, and another component of the signals, whose phase is orthogonal to the reference carrier 12 via a phase shifting device 13 are modulated by multipliers 10 and 11, respectively. These output signals are mixed by an adder 14 and an orthogonally modulated wave is obtained. However, when the orthogonal modulation is conducted with the orthogonal modulator for processing analog signals, there are many adjustment points. First, when an input digital signal is converted into an analog signal by the D/A converters 4 and 5, an DC offset takes place. In other words, although the input digital signal should be a waveform whose amplitude is based on 0 V, the waveform varies from a particular DC level due to the nature of the D/A converters 4 and 5. When such a DC offset is present, the DC component also causes the carrier to be modulated and thereby a correct modulation wave cannot be obtained. Thus, in the modulator described above, the operational amplifiers 6 and 7 are disposed downstream of the D/A converters 4 and 5. By adjusting the operational amplifiers 6 and 7, the DC offset is removed. Second, unless the amplification of the I channel signal which is input to the adder 14 is balanced with that of the Q channel signal, a correct orthogonal modulation wave cannot be obtained. In other words, the amplitude of the I channel signal which passes through the low pass filter 8 should accord with that of the Q channel signal which passes through the low pass filter 9. However, each amplitude is deflected by individual fluctuation of the characteristics of the D/A converters 4 and 5 and the low pass filters 6 and 7. Thus, in such a modulator, to balance the amplitudes, the operational amplifiers 6 and 7 downstream of the D/A converters 4 and 5 are adjusted. Third, the input impedance of the I channel of the digital input signal should be precisely matched with that of the Q channel thereof. Thus, when the circuit is made, these impedances should be adjusted. In the orthogonal modulator for processing an analog signal, there are many points to adjust and thereby much adjustment work is required. Thus, the cost of the modulator becomes expensive. In addition, for adjusting each input impedance of the I channel and the Q channel of the digital input signal, an impedance matching circuit which consumes large power is required and thereby the modulator becomes a large power consumption type. The invention provides a modulator as defined in Claim 1. In such a modulator, the number of adjustments may be small, to provide a modulator free from the adjustments for operational amplifiers. The modulator may also be free from the adjustment of a DC offset, and free from the adjustment of each input impedance of I channel and Q channel of an input signal. The number of output lines from a digital signal processing section accommodated in the LSI can also be reduced. Preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:- Figure 1 is a block diagram showing the structure of a modulator according to an embodiment of the present invention; Figure 2 is a time chart describing the operation of the embodiment shown in Figure 1; Figure 3 is a block diagram showing the structure of a digital signal pocessing sectionof an modulator of another embodiment of the present invention; Figures 4 and 5 are time charts describing the operation of the embodiment shown in Figure 3; Figure 6 is a block diagram showing the structure of a modulator of a third embodiment of the present invention; Figure 7 is a time chart describing the operation of the embodiment shown in Figure 6; Figure 8 is a block diagram showing the structure of a modulator of a fourth embodiment according to the present invention; Figure 9 is a block diagram showing the structure of a digital signal pocessing sectionof the modulator of the fourth embodiment according to the present invention; Figure 10 is a time chart describing the operation of the embodiment shown in Figures 8 and 9; Figure 11 is a block diagram showing the structure of a modulator of a fifth embodiment according to the present invention; and Figure 12 is a block diagram showing the structure of a conventional modulator. By referring to the attached drawings,embodiments of the present invention will be described in detail. Figure 1 is a block diagram showing the structure of a modulator of an embodiment according to the present invention. As shown in Figure 1, I channel data and Q channel data which are input from data input points 1 and 2 are mapped and filtered by a digital signal processing section 3. Thus, digital I channel signal(Figure 2 (a)) and digital Q channel signal (Figure 2(b)) take place. Although these signals are discrete to the time axis, since their computation time periods by D/A converters and the like are required, the output signal from the digital signal processing section 3 is held until the next signal is output as shown in Figure 2 (a) and (b). When a particular sampling time period (T) is mapped by the digital signal processing section 3, the signal output becomes the sampling point and thereby the interval between the signals becomes equal to the sampling time period (T). As shown in Figure 2(c) and (d), at the first half of the sampling time period (T), an input switch 16 and an output switch 17 which are connected to a D/A converter 15 on the I channel side are turned on and an input switch 18 and an output switch 19 which are connected to the D/A converter 15 on the Q channel side are turned off. Conversely, at the last half of the sampling time period (T), the input switch 16 and the output switch 17 which are connected to the D/A converter 15 on the I channel side are turned off and the input switch 18 and the output switch 19 which are connected to the D/A converter 15 on the Q channel side are turned on. The D/A conversion of the two channels is conducted by one D/A converter 15. The positions of the switches 16, 17, 18, and 19 are changed by a switch control section 21. An operational amplifier 20 is placed between the D/A converter 15 and the output switches 17 and 19 to remove the DC offset which is produced by the D/A converter 15. After that, the signals of the two channels separated by the output switches 17 and 19 pass through low pass filters 8 and 9. After that, the component of the signals whose phase is the same as a reference carrier 12 is modulated by a multiplier 10. The component whose phase is orthogonal to the reference carrier 12 is modulated by a multiplier 11 via a 90° phase shifter. Both the output signals are mixed by an adder 14 and thereby an orthogonally modulated wave is obtained. As described above, according to the present invention, since the conventional two D/A converters are reduced to one D/A converter, the adjustment work for adjusting the operational amplifier 20 for removing the DC offset is halved. In addition, the conventional balance adjustment for the operational amplifiers is not required because the amplitude of the I channel signal from the D/A converter 15 is the same as that of the Q channel therefrom. Then, a second embodiment of the present invention will be described. The modulator of the second embodiment uses a different digital signal pocessing section from the digital signal processing section 3 in Figure 1. Figure 3 is a block diagram showing the structure of the digital signal pocessing section22. As shown in the figure, I channel data and Q channel data which are input to the digital signal processing section 22 are mapped by mapping circuits 23 and 24, respectively. In this structure, the signals are mapped at 4 cycles per symbol (see Figures 4 (c) and (d)). There is an offset of 1/2 of the sampling clock time period τ between the sampling point of the mapping of the I channel and that of the Q channel (Figure 4 (e) and (f)). The offset is produced in the following manner. A clock 27 is directly supplied to a mapping circuit 23, a digital filter 25, a D flip flop 26, and so forth for the I channel, while the clock 27 which is supplied to a mapping circuit 24, a digital filter 28, a D flip flop 29, and so forth for the Q channel is delayed for τ/2 by a delay circuit 30. After that, the signals are filtered by the digital filters 25 and 28 which are offset according to the sampling points described above and then digital signals of the I channel and the Q channel are obtained (Figure 4 (g) to (j)). The digital signals are held by the D flip flops 26 and 29 from a particular sampling point to the next sampling point so that the D/A converter can compute them (Figure 4 (k) and (l). The I channel signal and the Q channel signal where 1/2 of the sampling clock time period τ is offset are passed through the input switches 16 and 18, the D/A converters 15, the operational amplifier 20, the output switches 17 and 19, the low pass filters 8 and 9, and the multipliers 10 and 11. After that, the signals are mixed by the adder 14 and thereby an orthogonally modulated wave is obtained. The input and output switches 16 to 19 are changed as shown in Figure 5. In other words, as described in the embodiment shown in Figure 1, when the sampling point of the I channel is not offset to that of the Q channel, since the signal where data of the Q channel or the I channel is delayed for 1/2 of the data sampling time period of the I channel or the Q channel is input to the D/A converter 15, a correct analog signal for the Q channel or the I channel may not be obtained. However, in this embodiment, since the signals are offset and sampled while they are mapped, analog signals without a delay can be obtained for both the I channel and the Q channel. Then, a third embodiment of the present invention will be described. Figure 6 is a block diagram showing the structure of a modulator of the third embodiment according to the present invention. The modulator in the figure uses input switches 32 and 33 which differ from the input switches 16 and 17 shown in Figure 1. In this embodiment, the output signals, whose sampling points of the I and Q channels are offset, from the digital signal pocessing section 22 are multiplexed by input switches 32 and 33. The structure of the third embodiment differs from that of the embodiment shown in Figure 1 as described in the following. As shown in Figure 7 (a) and (c), assuming that the sampling time period for mapping the signals is r, the input switch 32 is connected to the position a τ/8 after the I channel signal is sampled and the digital data of the I channel is input to the D/A converter 15. Assuming that the computation time period of the D/A converter 15 is smaller than τ/4, after the input switch 32 is connected to the position a for τ/4, the switch is connected to the position b which is connected to a ground 34 (0 is input) while τ/8 elapses from the next sampling point, namely,for 5 τ/8. On the Q channel, the signal is processed as shown in Figure 7 (b) and (d). Figure 7(e) shows the I channel signal and the Q channel signal which are input to the D/A converter 15. In this embodiment, the point where the input signal to the D/A converter 15 becomes 0 is provided by using the input switches 32 and 33. Thus, even if an offset is present in the input switches 32 and 33 to some extent, it is possible to prevent the I channel signal and the Q channel signal from being mixed and entered in the D/A converter 15. In addition, since a digital signal which always varies from 0 V is input to the D/C converter 15, no DC offset is present in the output signal of the D/A converter 15. Thus, no adjustment for removing the DC offset is required. Then, a fourth embodiment according to the present invention will be described. Figure 8 is a block diagram showing the structure of a modulator of the fourth embodiment according to the present invention. As shown in the figure, the I channel data and the Q channel data which are input from the data input points 1 and 2 are input to the digital signal processing section 35. Figure 9 is a block diagram showing the structure of the digital signal pocessing section 35. In the digital signal processing section 35, the frequency of the clock 38 of the D flop flops 36 and 37 (Figure 10 (e)) is twice that of the clock 27 of the digital filters 25 and 28 (Figure 10 (c) and (d)). From the digital filters 25 and 28, discrete digital signals for the I channel and the Q channel are output. The sampling points of the digital signals of the I and Q channels are offset (Figure 10 (a) and(b)). On the I channel, in the input signal to the D flip flop 36, one clock is used as the digital signal and the later 3 clocks of the signal are grounded by the switch 39 (Figure 10 (f)). On the Q channel, this operation is conducted in the same manner as on the I channel by the switch 40 (Figure 10 (g)). The I channel signal and the Q channel signal are passed through the adder 41, the D/A converter 15, the operational amplifier 20, the output switches 17 and 19, the low pass filters 8 and 9, the multipliers 10 and 11 and then mixed by the adder 14. Thus, an orthogonally modulated wave is obtained. Figure 10(h) shows an input signal to the D/A converter 15, the I channel output signal and the Q channel signal being mixed by the adder 41 as the input signal. In this embodiment, the input side switch of the D/A converter 15 shown in Figure 1 and so forth can be replaced with the adder 41 and thereby the apparatus can be of a compact structure. Then, a fifth embodiment of the present invention will be described. Figure 11 is a block diagram showing the structure of the modulator according to the fifth embodiment. In the modulator shown in the figure, the input switches 16 and 18 and the switch control section 21 shown in Figure 1 are accommodated in an LSI 42 as well as the digital signal processing section 3. Since the input switches 16 and 18 and the switch control section 21 are accommodated in the LSI 42 as well as the digital signal processing section 3, the number of output lines for the I channel and the Q channel from the digital signal processing section 3 (Figure 1) is reduced, respectively. Namely, when the LSI 42 is of 16 bit type, the number of output lines is reduced from 32 lines to 16 lines. Thereby the number of output pins can be reduced. In addition, the D/A converter 15, the operational amplifier 20, the input and output switches 17 and 18, the low pass filters 8 and 9 can be accommodated in the LSI. Particularly, when the low pass filters 8 and 9 are accommodated in the LSI, the clock 27 used in the digital signal processing section 3 can be supplied to a switched capacitor filter that the low pass filters 8 and 9 have and which requires a particular clock.

Claims: A modulator for converting two digital signals (1, 2) for an I channel and a Q channel in the base band into analog signals and for modulating a component of the signals whose phase is the same as a carrier (12) and another component of the signals whose phase is orthogonal to the carrier (12), comprising a digital/analog converter (15) for converting the signals into analog signals; characterized by: signal connection means (21, 16, 18) for connecting the two signals of said I channel and said Q channel to one signal train by time-sharing and multiplexing them; the digital/analog converter (15) being for converting the signal from said signal connection means into an output analog signal; and signal separation means (21, 17, 19) for separating said output analog signal into two analog signals of said I channel and said Q channel. A modulator according to Claim 1, comprising means (23, 24) for mapping the digital signals and offsetting sampling points in the base band of said digital signals between the time axis of said I channel and that of said Q channel. A modulator according to Claim 1, wherein said signal connection means (21, 16, 18) causes said adjacent digital signal trains to be grounded for a particular time period when connecting the two digital signals to one signal train by time-sharing and multiplexing them. A modulator according to Claim 1, wherein a digital signal processing section (3) is provided at least for mapping and filtering signals, said signal connection means (21, 16, 18) being accommodated in said digital signal processing section. A modulator according to Claim 1, wherein a digital signal processing section (3) is provided at least for mapping and filtering signals, said digital signal processing section (3) and at least one of said signal connection means (21, 16, 18), said digital/analog converter (15) and said signal separation means (21, 17, 19) being accommodated in the same LSI.

Inventors: OGURA KOJI, SERIZAWA MUTSUMU, OGURA, KOJI, SERIZAWA, MUTSUMU, OGURA, KOJI C/O INT PROPERTY DIV, SERIZAWA, MUTSUMU C/O INT PROPERTY DIV
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H04L27
IPC codes: H04L27