Switched-mode power supply circuit

Abstract: A power supply circuit having a controllable switch in series with an inductive element between the terminals of a DC input voltage is described. A control circuit renders the switch alternately conducting and non-conducting. A rectifier for making a DC output voltage available is coupled to the inductive element. To prevent the inductive element from being saturated, a switching element is coupled to the control circuit for maintaining the controllable switch in its blocked state only during a time interval which immediately follows an interval of conductance of the said switch and during which the voltage across the inductive element has the same polarity as when the rectifier is conducting.

Description: The invention relates to a switched-mode power supply circuit as defined in the precharacterizing part of Claim 1. A power supply circuit of this type is known from WO-A-86/07214. A switch is arranged between a DC voltage source and the primary windings of a transformer. During the time intervals in which the switch is conducting, a current flows through the primary windings of the transformer which magnetizes the transformer, i.e. charges it with energy (the charge periods). During the time intervals in which the switch is non-conducting, the energy stored in the transformer is delivered to a load via a rectifier (the de-charge periods). The switch is controlled by a pulse width modulated clock signal. The pulse width modulation of the clock signal depends on the DC voltage available at the rectifier. In normal operation, such a control keeps the DC output voltage of the power supply circuit substantially constant. However, the power supply circuit will malfunction if the transformer becomes saturated. To prevent saturation of the transformer, the switch is forcedly maintained non-conducting during each de-charge period, until the transformer has been fully demagnetized. The polarity of a voltage across a secondary winding of the transformer, indicates the magnetization of the transformer. As long as the transformer is still magnetized and the switch is non-conducting, the voltage across the secondary winding is positive. This is detected by a threshold voltage detector which in response to this polarity, inhibits a closing of the switch by the pulse width modulated clock signal . However, instability may attend such a measure to prevent saturation. It is therefore, inter alia , an object of the invention to improve the operation of a switched-mode power supply circuit in which saturation of the transformer is prevented as in the known circuit. To that end, the invention provides a power supply circuit as defined in Claim 1. Advantageous embodiments are defined in the dependent Claims. The invention is based on the following recognition. The inductances of the transformer and the capacitances coupled thereto, cause ringing effects in the secondary winding voltage. Due to ringing, the polarity of this voltage may alter without this involving a change in the magnetization of the transformer. Then, the secondary winding voltage falsely indicates the magnetic state of the transformer, leading to instability and/or other improper operation. In the invention, a usable distinction is made between the two possible states of the switch. An instability, which could otherwise be caused by ringing effects, then does not occur. The control circuit ignores false indications and the state of the switch is controlled in accordance with the actual magnetization of the transformer. The circuit means for the measure according to the invention are fairly simple and can be integrated. The demagnetization protection will be operative in a satisfactory way in the case where a number of windings is coupled to the inductive element if the threshold voltage detector is connected to the winding having the largest number of turns. The supply circuit is preferably characterized in that a delay element for delaying the reset signal applied to the reset input of the bistable element is coupled between the threshold voltage detector and the said input. It is thereby prevented that the controllable switch is rendered conducting at the start of a blocking interval, while ringing effects occur which are caused by parasitic capacitances and leakage inductances so that under circumstances the voltage across the inductive element could become zero and could subsequently assume the other polarity. It is noted that a switched-mode power supply circuit having a bistable element is known from DE-A-3,226,213. The bistable element prevents saturation of the transformer during the start-up period of the power supply circuit. The bistable element is set when a current flowing through the primary winding exceeds a predetermined value, indicating that the transformer is nearly saturated. In the set state, the bistable element inhibits a pulse width modulated clock signal from closing a switch in series with the primary winding. This gives the transformer the opportunity to demagnetize itself. When the transformer is fully demagnetized the bistable element is reset and a new start-up period, during which the transformer is magnetically charged, is effectuated. This is shown in figure 2 of DE-A-3,226,213. It is evident that if saturation does not occur during the start-up period, the bistable element will not affect the control of the switch. Then, the state of the switch is solely determined by the pulse width modulated clock signal. The invention will be described in greater detail by way of example with reference to the accompanying drawings in which Fig. 1 is a block-schematic diagram of the power supply circuit according to the invention, Fig. 2 shows some details of the circuit diagram of Fig. 1, Fig. 3 shows diagrams relating to the circuit, and Fig. 4 shows waveforms occurring in the circuit. The power supply circuit of Fig. 1 comprises a controllable switch in the form of an NPN switching transistor Tr whose collector is connected to the primary winding L1 of a transformer T and whose emitter is connected to ground. The other end of winding L1 is connected to the positive terminal of a DC input voltage source V i whose negative terminal is also connected to ground and which is, for example, a mains rectifier. The base lead of transistor Tr is connected to a control circuit 1 for turning the transistor alternately on and off. Transformer T has a plurality of secondary windings. One of these windings, L2, has one end connected to ground. The other end is connected to the anode of a rectifier D o whose cathode is connected to a smoothing capacitor C o and a load represented by a resistor R. The terminals of capacitor C o and resistor R which are not connected to rectifier D o are connected to ground. The winding sense of windings L1 and L2, which is conventionally denoted by dots, as well as the direction of conductivity of rectifier D o are chosen to be such that in operation a current flows through the one winding while the other is currentless. A DC output voltage V o is present across load R. The said elements form part of a switched-mode power supply circuit of known type, in which a control of the duration of the time intervals in which transistor Tr is turned on ensures that voltage V o has a substantially constant value which is independent of the values of voltage V i and of load R. The circuit of Fig. 1 may be, for example, a supply circuit for a television receiver. The loads on the secondary windings of transformer T are formed by the consumption by a plurality of circuits in the receiver. A current flows through one of these windings, L3, during the same period when a current flows through winding L1. The output voltage V o is applied to a function generator 2, to a starting circuit 3 and to a safety circuit 4. The other ends of generator 2 and circuit 3 are connected to a selection circuit 5. Windings L2 and L3 are connected to a sawtooth generator 6. The sawtooth-shaped signal generated thereby and an output signal from circuit 5 are applied to a pulse duration modulator 7, an output signal of which is applied to a control circuit 8. A secondary winding L4 of transformer T is connected to a stand by circuit 9. Circuit 9 has its other end coupled to stage 8 and stage 8 is coupled to circuit 1. Fig. 2 shows details of the supply circuit of Fig. 1. The series arrangement of two resistors 11 and 12 is connected between voltage V o and ground. The function generator 2 comprises a differential amplifier 23, an inverting input of which is connected to the junction point of the resistors. This point conveys a voltage V fb which is proportional to voltage V o . In another embodiment the voltage divider 11, 12 may be dispensed with. An input of an adder stage 24 is connected to the same point. A current source 25 is connected to another input of stage 24 and a resistor 26 is arranged between this input and ground. A reference voltage is connected to a non-inverting input of amplifier 23. The difference between the negative feedback voltage V fb and the reference voltage is amplified by amplifier 23 and stage 24 adds voltage V fb to the voltage caused by source 25 across resistor 26. The sum voltage obtained at an output of stage 24 is applied to a limiter 27. The voltage thus obtained and the voltage which is present at an output of amplifier 23 are applied to a minimum value transmission circuit 28. This circuit passes on the lowest of said voltages to the selection circuit 5. Circuit 5 receives also a voltage which originates from the starting circuit 3. Circuit 5 is also a minimum value transmission circuit and the lowest of the two input voltages of circuit 5 is passed on to an inverting input of the modulator 7 formed as a differential amplifier for controlling the modulator as a function of the output voltage V o . In the normal operating condition of the supply circuit the voltage at the output of circuit 28 is always lower than the voltage which originates from circuit 3, so that the first-mentioned voltage is passed on to circuit 5. In practice such a minimum value transmission circuit can be formed by means of two emitter-coupled PNP transistors whose bases are connected to the respective voltages to be compared, the lowest of these voltages turning on the associated transistor. A solid line in Fig. 3a denotes the transfer characteristic of elements 2 and 5, i.e. the diagram of the variation of the voltage V r passed on by circuit 5 as a function of voltage V o in the case where the starting circuit 3 is not operative. If voltage V o is zero, voltage V r has a given value V ro which can be set by means of elements 25 and 26 (point A in Fig. 3a). The characteristic curve is linear up to a given value V r1 which is reached for V o = V o1 (point B). If voltage V o is higher than V o1 , limiter 27 becomes operative, resulting in voltage V o no longer increasing. At values of voltage V o which are lower than a value V o2 (point C), which is higher than V o1 , the voltage at the output of amplifier 23 is higher than the voltage of limiter 27, so that circuit 5 further passes on the last-mentioned voltage. At values of voltage V o which are higher than V o2 the voltage at the output of amplifier 23 is lower than that of limiter 27, so that the voltage at the said output is further passed on. This voltage decreases very steeply at increasing values of voltage V o and becomes zero at a point D. The sawtooth generator 6 includes a capacitor 61 which is charged by a current source 62. The value of the current of source 62 is determined by a resistor 63 which is connected to winding L3. Since winding L3 conveys a current simultaneously with winding L1, source 62 is operative during the interval of conductance of transistor Tr. The voltage of winding L2 is compared with a reference voltage of, for example, 100 mV by means of a differential amplifier 64. If the voltage across winding L2 exceeds this value, which takes place during the period when transistor Tr is turned off, a switch 65 arranged parallel to capacitor 61 becomes conducting so that the capacitor is discharged. The starting instant of charging is delayed by means of a delay element 66. The reason for this will be explained hereinafter. Under these circumstances a sawtooth-shaped voltage, whose peak value is a measure of the peak value of the collector current of transistor Tr and of the value of voltage V i , is produced across capacitor 61. A voltage of approximately 100 mV is added to the sawtooth by means of an adder stage 67 and the voltage V s obtained is applied to a non-inverting input of amplifier 7. In another embodiment the sawtooth generator may be an oscillator. In operation amplifier 7 compares the output voltage V r passed on by the selection circuit 5 to the control input of the amplifier with voltage V s . The control circuit 8 has an OR gate 81, an input of which is connected to an output of amplifier 7. Via a second OR gate 82 the output signal of amplifier 7 reaches a control stage 83 which drives a light-emitting diode 84. Diode 84 is optically coupled to a photosensitive element which forms part of the control circuit 1 of transistor Tr. At an instant when voltage V r is lower than V s , the output signal of amplifier 7 is high, so that diode 84 conveys a current. Circuit 1 is adapted in such a known manner that transistor Tr is then turned off. However, at an instant when voltage V r is higher than V s , transistor Tr is turned on. The lower the voltage V r with respect to voltage V s , the shorter the conductivity time of transistor Tr, and conversely. As a result, a control of voltage V o is obtained. If, for example, the load decreases, voltage V o increases. Voltage V r decreases (line section CD in Fig. 3a). As a result, diode 84 starts conducting at an earlier instant than would otherwise be the case so that transistor Tr is turned off at an earlier instant. The peak value of the collector current decreases. The energy stored in transformer T during the conductivity time of the transistor decreases, which counteracts the increase of voltage V o . At a larger load the opposite applies, i.e. the conductivity time of transistor Tr increases. If voltage V i increases, so that voltage V o would increase, voltage V s also increases, resulting in the said conductivity time becoming shorter, which stabilizes V o . A solid line in Fig. 3b shows the output characteristic of the supply circuit, i.e. the diagram of the variation of the output voltage V o as a function of the output current I o flowing through the load R. The characteristic has a given shape due to the fact that voltage V r has the variation shown in Fig. 3a as a function of voltage V o . The characteristic of Fig. 3b is a substantially horizontal straight line between the value 0 and a given value of current I o (between points K and L in Fig. 3b). At higher values of the current the voltage slightly decreases, while the current slightly increases and reaches a maximum value I omax (point M), whereafter both the voltage and the current decrease steeply. The characteristic is then a substantially straight line reaching the I o axis at a point P which corresponds to a low value of I o , i.e. the value at a short-circuited load (V o = 0). Such a characteristic is known under the name of current fold-back characteristic. The diagrams of Figs. 3a and b correspond to each other, more specifically such that point A corresponds to point P, B corresponds to M, C corresponds to L and D corresponds to K. Fig. 3b also shows the straight line representing resistor R at the nominal value of this resistor. This line intersects the line section KL at a point W which represents the nominal working point and which corresponds to a point E located on the line section CD in Fig. 3a. The control of the period of conductance of transistor Tr implies that, in operation, the working point is displaced along the line section KL around point W. A straight line, which would have been drawn between the origin O of the system of coordinates and point L, indicates the minimum value of resistor R. Point A determines the minimum period of conductance of transistor Tr in the case of a short-circuited output and its setting influences both characteristics: this is denoted in Fig. 3 by means of broken lines in accordance with a line running parallel to the solid lines AB and MP, respectively. The maximum value of the collector current of the transistor is determined by means of limiter 27 and therefore the maximum value of voltage V r and of current I o is determined. It is achieved by means of stage 67 that the level of voltage V r may be lower than voltage V s , for example, in unloaded operation at which it must be possible for the working point to be displaced to point D, i.e. the point for which the period of conductance of transistor Tr is zero. The starting circuit 3 comprises a current source 31 for charging a storage element in the form of a capacitor 32. The junction point of elements 31 and 32 is connected to a non-inverting input of a differential amplifier 33, an inverting input of which is connected to the junction point of resistors 11 and 12. An output of amplifier 33 is connected to an input of an AND gate 34. An input of an adder stage 35 is connected to the junction point of elements 25 and 26, another input is connected to the junction point of elements 31 and 32 and an output is connected to the second input of circuit 5. An output of gate 34 operates a switch 36 arranged parallel to capacitor 32. Circuit 4 is an overvoltage protection circuit. The voltage at the junction point of two resistors 13 and 14, which are arranged in series between voltage V o and ground, is compared with a reference voltage of, for example, 2.5 V by means of a differential amplifier 41. An output of amplifier 41 is connected to a set input of a flip-flop 42. A non-inverting output Q of flip-flop 42 controls a discharge current source 43 for capacitor 32 and is connected to a second input of gate 82. An inverting output Q of flip-flop 42 is connected to a second input of gate 34. The voltage across capacitor 32 is compared with a reference voltage of, for example, 100 mV by means of a differential amplifier 44 and an output of amplifier 44 is connected to a reset input of flip-flop 42. In the normal operating condition of the supply the voltage at the junction point of resistors 13 and 14 is lower than approximately 2.5 V. The signal applied by flip-flop 42 to gate 34 is a 1, while source 43 is inoperative. If the voltage V ss generated by source 31 across capacitor 32 is higher than voltage V fb , switch 36 starts conducting so that the capacitor is quickly discharged. Voltage V ss decreases. In the opposite case the switch is blocked so that the said voltage increases. It is apparent therefrom that voltage V ss is always clamped at substantially the value of voltage V fb . This value is substantially constant in the normal operating condition and it is higher than the voltage applied by generator 2 to circuit 5 and therefore has no influence on the control of the output voltage. A resistor 39, shown in broken lines, may be arranged parallel to capacitor 32. The voltage across the capacitor is thereby decreased to the value of the voltage drop produced by source 31 across the resistor. The resistor can be chosen to be such that the voltage applied by stage 35 to circuit 5 is the lowest of the input voltages of this circuit so that transistor Tr is turned off at an earlier instant than would otherwise be the case. It is apparent therefrom that the provision of the said resistor ensures that the peak value of the collector current of the transistor can be set to a given value by means of the starting circuit 3. When switching on the television receiver of which the described power supply circuit forms part, all voltages are initially zero. The voltage at the output of amplifier 23 becomes high. A voltage drop is produced across resistor 26 by source 25 and is added to the slowly increasing voltage across capacitor 32 by means of stage 35. The said voltage drop determines the minimum period of conductance of transistor Tr via circuit 5, in which period energy is applied to transformer T. The output voltages of the supply thus increase. A minimum value detector 37 compares a direct voltage V b , which is derived from winding L3 by means of a rectifier D b and which is present across a smoothing capacitor C b (Fig. 1), with a reference value of, for example 6 V. As long as voltage V b is lower than this value, stage 83 is blocked by detector 37, which makes a soft start possible. Source 31 charges capacitor 32 so that voltage V ss increases slowly, i.e. more slowly than the voltage at the output of generator 2 so that the voltage applied by circuit 3 to circuit 5 is lower than the voltage of generator 2. The voltage of circuit 3 is passed on as voltage V r by circuit 5 to modulator 7 so that the period of conductance of transistor Tr slowly increases. The said period of conductance is shorter than would be the case under the influence of the output voltage of generator 2. The rate at which voltage V ss increases is set by the choice of the capacitance of capacitor 32. The normal operating condition starts as soon as the voltage applied by stage 35 to circuit 5 exceeds the voltage applied by circuit 28 to circuit 5, which takes place when V o has reached the value V o2 , in which state the voltage of the function generator 2 is passed on by the selection circuit 5 to modulator 7 for controlling the duration of the period of conductance of transistor Tr, while voltage V ss which no longer has any influence on the said duration remains substantially constant. In Fig. 3 the characteristic curve of the starting circuit is plotted in broken lines AE and PW, respectively. Voltage V b is the supply voltage of an integrated circuit comprising most parts of the circuit of Fig. 2. It will be noted that the value of voltage V b , which is derived from winding L3, is not dependent on the value of V o , but on that of V i , more specifically because the integrated circuit must also be active in the case of a short-circuited voltage V o . If in operation voltage V b becomes lower than 5 V, at which value the integrated circuit cannot function properly, diode 84 remains currentless and transistor Tr is continuously conducting, resulting in the transistor being damaged. This is avoided because the control circuit 1 has a facility for releasing the control of the transistor when voltage V b is higher than 6 V. Capacitor 32 is also reset because a switch 38, which is arranged parallel to switch 36, becomes conducting under the influence of detector 37. If voltage V o becomes considerably lower than the value in the normal operating condition, voltage V fb decreases proportionally. Voltage V ss decreases accordingly to the value of V fb so that the voltage at the output of stage 35 becomes lower than that of generator 2 and is thus passed on to modulator 7. This condition occurs in the case of an overload at which resistor R assumes a smaller value R′ such that the load line in Fig. 3b intersects the characteristic curve at a working point J which is located on the line section MP. However, if voltage V o increases to such an extent that the protection level at the junction point of resistors 13 and 14 becomes higher than 2.5 V, flip-flop 42 is set. A 1 is present at the output Q of flip-flop 42 so that source 43 becomes active and discharge capacitor 32 slowly. Voltage V ss decreases. Simultaneously gate 34 is blocked by a 0 at the output Q so that switch 36 is not operated. Voltage V o does not have any influence on the starting circuit. Otherwise voltage V ss would be equal to V fb and the discharge of capacitor 32 would be influenced by the load current. Stage 83 is controlled by flip-flop 42 via gate 82 for causing diode 84 to conduct continuously and thus for turning off transistor Tr. Both in the case of the overload and in the case of the overvoltage the starting voltage V ss is low. At the instant when voltage V ss becomes lower than 100 mV, flip-flop 42 is reset by amplifier 44 so that the discharge of capacitor 32 is discontinued, while gate 34 again receives a 1 and transistor Tr is released. A new start can then begin. The stand-by circuit 9 comprises a stage 91 which is connected to winding L4 and which ensures, under the influence of a switching signal, that the output voltages of the supply are decreased considerably. Stage 91 is connected to a comparison stage 92, an output of which is connected to a third input of gate 82. In the stand-by state a periodically interrupted oscillation is generated at a low frequency (burst mode). Such a circuit is described in Netherlands Patent Application 8502338 (PHN 11.471) which is herein incorporated by reference. If the voltage across winding L4 exceeds a given level, diode 84 conducts so as to turn off transistor Tr so that the said voltage decreases again. If under these circumstances another level is reached which is lower than the first-mentioned level, stage 83 is again blocked so as to turn on transistor Tr. If an overload occurs at an instant during the period of conductance of transistor Tr, energy, which cannot immediately disappear, is present in transformer T at that instant. The working point follows the characteristic curve along the points L and M and the line section MP towards the new position J. If the overload occurs at an instant during the period when the transistor is turned off, the transformer has no or little energy at that instant so that for reaching point J the working point follows a path shorter than the characteristic curve. Also in the case of an overvoltage and when setting the stand-by state the working point is displaced to a point located on the line section PM of the characteristic curve in the vicinity of point P. In all these cases the supply remains operative in the normal manner, be it that the output voltage and the output current have low values. Since voltage V ss is always clamped at the value of voltage V fb , a soft start is created at which the output voltages of the supply increase gradually until the nominal position W on the characteristic curve is reached again, unless the disturbance or the stand-by state occurs again. It is apparent therefrom that small and short-lasting disturbances cannot render the supply inactive for a long time. If, for example, the overload is a short circuit of voltage V o , the working point is located at point P. If the short circuit is eliminated, at which the load is again formed by resistor R, the current I o initially flowing therethrough produces a voltage drop which is denoted in Fig. 3b by a broken vertical line between point P and the load line representing R. The point of intersection formed on the characteristic curve PW of the starting circuit corresponds to a point which is denoted by a horizontal line. This new point yields a new value of current I o . It is apparent therefrom that the working point is displaced along a staircase-shaped curve and reaches point W without large values of current I o occurring. The same applies to the start after switching on the receiver, at which the working point reaches the position W from point O. Both in Fig. 3a and in Fig. 3b the working point follows a path shorter than the original characteristic curve. For the purpose of comparison Fig. 3b shows as a dotted line the staircase shape along which the working point would be displaced without the starting circuit, which staircase shape reaches the line section PM. The last vertical line of this staircase shape, the third line in the Figure, intersects the line section KL in the characteristic curve at a point which is located to the right of point W and which represents a situation with a larger output current. Under circumstances the maximum value I omax can be reached. After reaching the line section KL the control is activated so that the working point is no longer displaced along the vertical line but moves to the left along the line section KL until it assumes the position W. It will be clear that the dissipation is then larger than is the case due to the starting circuit. The operation of the supply circuit is improved by the delay element 66 referred to hereinbefore and by parts of the control circuit 8 which will now be described. Firstly, an AND gate 85 is concerned, an output of which is connected to a second input of the OR gate 81. An input of gate 85 is connected to a non-inverting output Q of a flip-flop 86. The output of element 66, which controls switch 65, is connected to a reset input of flip-flop 86 and to another input of gate 85. Connected to a set input of flip-flop 86 is the output of an OR gate 87, a first input of which is connected to the output of modulator 7, a second input is connected to an output of a differential amplifier 88 and a third input is connected to detector 37. The output of stage 67 is connected to a non-inverting input of amplifier 88 and an inverting input of this amplifier is connected to a reference voltage of, for example, 1.5 V. During the time interval in which the switching transistor Tr is turned off, decreasing currents flow through a plurality of secondary windings of transformer T, in this embodiment L2 and L4. The transformer is demagnetized thereby. If the transistor were turned on again in this interval, it would not be possible for the transformer to be discharged and it might consequently become saturated. This is undesirable. The control of the transistor must therefore be such that the transistor Tr is not turned on again before the secondary current has become zero. A usable measure in this case is the fact that the voltage across a secondary winding quickly assumes a given polarity after transistor Tr is turned off, for example, the voltage becomes positive across winding L2 and this polarity is maintained as long as the rectifier connected thereto is conducting and passes the demagnetizing current, whereafter the said voltage decreases, becomes zero and then negative. If the transistor is still turned off, there is the difficulty that ringing effects may occur which are caused by the inductance of the transformer and by parasitic capacitances so that the said voltage may be positive without this situation involving a demagnetization. An instability may be produced if no difference is made in the control of the transistor between the intervals in which demagnetization and those in which oscillation takes place. The measures taken for this purpose are elucidated with reference to the diagrams of Fig. 4 which are also useful for clarifying the foregoing description. These diagrams apply to the case of a supply circuit tuned by a capacitor arranged parallel to transistor Tr. Fig. 4a shows the secondary voltage as a function of time. In Fig. 4b the collector current of transistor Tr is denoted by a solid line and the secondary current transformed to the primary side is denoted by a broken line. The transistor is turned on between instants t₁ and t₂. It is apparent from these diagrams that only the secondary current flowing between instant t₂ and the first zero-crossing of the secondary voltage at instant t₃ is demagnetizing and that an oscillation occurs after t₃. Amplifier 64 fixes the instants when the voltage across winding L2 does not become zero, but exceeds the value 100 mV so as to make a distinction between the rest state, in which this voltage is zero, and the state with short-circuited output voltage in which diode D o conducts with a voltage drop of several tenths of one Volt thereacross. If the voltage across winding L2 is higher than 100 mV, the signal at the output of amplifier 64 becomes high (Fig. 4c). The falling edges of this signal, which occur when this voltage becomes lower than 100 mV, are delayed by means of element 66 having a delay d set by means of a capacitor 68. The falling, delayed edges of the signal obtained at the output of element 66 (Fig. 4d) are applied to flip-flop 86 for resetting this flip-flop and to switch 65 for rendering this switch non-conducting. In Fig. 4e a solid line denotes the sawtooth-shaped voltage generated across capacitor 61 and a broken line denotes voltage V s . The output signal of modulator 7 is shown in Fig. 4f. Without amplifier 88 the rising edges of this signal would set flip-flop 86. The diagram of Fig. 4g represents the signal at the output Q of flip-flop 86 and the diagrams of Figs. 4h and 4i represent the signal at the output of gate 85 and the signal at the output of gate 81. It is apparent from the diagrams of Fig. 4 that diode 84 is blocked at the instant t₁ which is determined by the delay d, so that transistor Tr is turned on. At the instant when V r and V s cross each other in Fig. 4e, diode 84 becomes conducting again. After this instant the transistor is turned off at instant t₂ after an interval which is determined by the storage time of the transistor and by delays which may be caused by the control process. After transistor Tr has been turned off, ringing effects may be produced which are caused by leakage inductances and parasitic capacitances. As a consequence thereof the secondary voltage (Fig. 4a) does not immediately assume the value V o but oscillates around this value. At a low value of voltage V o the first of these oscillations might come below zero so that the signal of Fig. 4c would have a falling edge and transistor Tr would be turned on. This is prevented in that this edge is delayed by means of element 66. Similarly, the transistor would be turned on at instant t₃. The signal of Fig. 4i ensures that this is not effected until after the delay d. An improvement of the described facilities for demagnetization protection is that the information applied to amplifier 64 about the secondary voltage originates from the secondary winding, in this example L2, which has the largest number of turns. The properties of the supply during the start are improved in that the demagnetizing signal from element 66 activates stage 83 only if flip-flop 86 is set, which is effected via gate 87 if the output signal of modulator 7 is positive, or if voltage V s is higher than 1.5 V, which is established by means of amplifier 88, or if detector 37 supplies the information that voltage V b is not lower than 5 V. The latter two criteria are added to guarantee demagnetization if transistor Tr does not convey enough base current during the start so that the sawtooth in Fig. 4e does not reach the level V r and modulator 7 does not yet supply a signal for setting flip-flop 86. Fig. 4g shows that the flip-flop is set at the instant when voltage V₁ exceeds the value 1.5 V. A plurality of parts of the supply of Fig. 1 has extensively been described in the foregoing. It will be evident that many modifications are possible within the scope of the claims. For example, the type of supply, for example self-oscillating or not self-oscillating, constant switching frequency or no constant switching frequency, tuned or not tuned are irrelevant to the invention. The same applies to the switching element used and to a number of details in Fig. 2, for example the generation of the sawtooth which may also be effected at the primary side if a DC separation is not required, for example, with the aid of an emitter-resistor of transistor Tr.

Claims: A switched-mode power supply circuit comprising a series arrangement of a switch (Tr) and an inductive element (T) coupled between the terminals of a DC input voltage (Vi), a rectifier (Do) coupled to the inductive element (T) for making a DC voltage available at a load (R) connected thereto, a control circuit (8) for rendering the switch (Tr) alternately conducting and non-conducting, and a threshold voltage detector (64) for inhibiting conductivity of the switch (Tr) when the voltage across the inductive element (T) has a polarity indicating that said rectifier (Do) is conductive, characterized in that the control circuit (8) comprises a bistable element (86) and means (61, 62, 63, 65, 67, 88) for setting the bistable element (86) during each interval of conductance of the switch (Tr), an input (R) of the bistable element (86) being coupled to an output of the threshold voltage detector (64) for resetting the bistable element (86) when said polarity alters. A switched-mode power supply circuit as claimed in Claim 1, characterized in that a delay element (66, 68) is arranged between said output of the threshold voltage detector (64) and said input (R) of the bistable element (86). A circuit as claimed in Claim 1 or 2, characterized by a sawtooth generator (61, 62, 63, 65) for generating a sawtooth-shaped signal during each interval of conductance of the switch (Tr) and for setting the bistable element (86) when the sawtooth-shaped signal exceeds a predetermined value. A circuit as claimed in Claim 3, characterized in that the sawtooth generator (61, 62, 63, 65) is connected to a winding (L₃) coupled to the inductive element (T), through which winding a current flows during the same interval when a current flows through the inductive element (T). A circuit as claimed in any one of the preceding claims, in which a plurality of windings (L₁, L₂, L₃, L₄) is coupled to the inductive element, characterized in that the threshold voltage detector (64) is connected to the winding (L₂) having the largest number of turns. A circuit as claimed in Claim 3, characterized in that the sawtooth generator (61, 62, 63, 65) comprises a storage element (61) and a charge source (62) for the storage element (61), the resetting of the storage element (61) coïnciding with the resetting of the bistable element (88). A circuit as claimed in any of the preceding claims, characterized by a gate having an AND function (85) for receiving the reset signal of the bistable element (86) and an output signal of said element (86), and for passing on a signal for blocking the controllable switch (Tr). A circuit as claimed in Claim 7, comprising a control circuit for generating a control signal which is dependent on the output voltage for controlling the conductivity time of the controllable switch (Tr), characterized by a gate (81) having an OR function for receiving the signal originating from the AND gate (85) and the control signal and for passing on a signal for blocking the controllable switch (Tr). A circuit as claimed in Claim 8, characterized by a second gate (82) having and OR function for receiving the signal of the first OR gate (81) and a signal for decreasing the output voltage, and for passing on a signal for blocking the controllable switch (Tr). A circuit as claimed in any of the preceding claims, characterized by a gate (87) having an OR function for receiving a set signal from said means (61, 62, 63, 65, 67, 88) and a signal of a minimum value detector (37) for establishing that an output voltage of the circuit is not lower than a further predetermined value, an output of the gate (87) being connected to the set input (S) of the bistable element (86).

Inventors: DE BONDT GUY LOUIS PAUL, MARINUS ANTONIUS ADRIANUS MARI, DE BONDT, GUY LOUIS PAUL, MARINUS, ANTONIUS ADRIANUS MARIA
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1990
Main classification: H02M3
IPC codes: H02M1, H02M3