Method of making complete dielectric isolation structure in semiconductor integrated circuit

Abstract: For controlling unwanted production of crystal defects from corners (6, 7) of isolated regions in a complete dielectric isolation structure, after at least one trench (5) or groove is provided through a mask of an insulating film (4) in a semiconductor substrate (3) adhered to an insulating film (2) of a base substrate (1), the mask (4) is side-etched and the insulating film (2) of the base substrate (1) is selectively etched at the same time to expose corners (6, 7) of the semicon­ ductor substrate (3). The exposed corners (6, 7) of the semiconductor substrate (3) is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate (3) exposed within the trench (5) is oxidized to provide an insulting film (8) for dielectric isolation which has rounded corners.

Description: The present invention relates to a method of making a complete dielectric isolation structure in a semiconductor device. As dielectric insulating isolation techniques for electrically isolating circuit elements in an integrated circuit from one another, it has been known to provide a field oxide film on a semiconductor substrate by LOCOS techniques. A complete dielectric isolation structure which is obtained in the following manner has been also known. That is, a first semiconductor substrate is adhered to a second semiconductor substrate through an insulating layer, and trenches reaching the insulating film are provided in the first semiconductor substrate. Thereafter, side walls of the trenches are oxidized to form an oxide film, and the trenches are filled with a dielectric material. In such a complete dielectric isolation technique, it is necessary to round corners of the trenches. If the trenches do not have rounded portions at corners, an unwanted stress will occur at corners of each trench in the step of forming the oxide film on the side walls thereof, depending upon a difference of thermal expansion coefficient between the insulating film on the second semiconductor substrate and the first semiconductor substrate, e. g. between silicon dioxide and silicon. As a result, a dislocation density of silicon crystal will be increased in proportion to the stress, thereby producing crystal defects at the corners of the trenches. A conventional technique for rounding corners of a trench, as known e. g. from DE-A-3829015 will be described below with reference to Figs. 4A to 4D. As shown in Fig. 4A, an oxide film 12, a nitride film 13 and an oxide film 14 are successively formed on a silicon semiconductor substrate 11, and then these films are patterned to obtain a mask for forming a trench. Using the mask, the semiconductor substrate 11 is etched by RIE (Reactive Ion Etching) techniques to provide a trench 15 therein. As shown in Fig. 4B, the oxide films 12 and 14 in the mask are side-etched by a diluted HF solution by several 10 nm to expose corners 16 of the semiconductor substrate 11 in the trench 15. As shown in Fig. 4C, the corners 16 of the semiconductor substrate 11 are removed by CDE (Chemical Dry Etching) techniques, using the oxide film 12 as a mask. Finally, as shown in Fig. 4D, after the oxide film 12, the nitride film 13 and the oxide film 14 are removed, the entire surface of the substrate including side walls of the trench 15 is oxidized to form an oxide film 17, thereby rounding the corners 16. In the above method of rounding the corners of the trench, important parameters for controlling the conditions of rounding the corners are both the side-etching quantity of the mask, i. e., the oxide film 12, by the diluted HF solution in Fig. 4B and the etching quantity of the corners 16 of the semiconductor substrate 11 by the CDE in Fig. 4C. In this case, the corners are rounded under conditions of both the side-etching quantity of the oxide film 12 of about 50 nm and the etching quantity of about 100 nm by the CDE: On the other hand, in relation to the complete dielectric isolation structure, a trench reaching the insulating film is provided in a semiconductor substrate adhered to a base substrate through an insultion film. When the side walls of the trench are oxidized, corners of the semiconductor substrate adhered to the insulating film, i.e., the oxide film are present at upper and lower corners thereof. For this reason, the parameters for controlling the conditions of rounding the corners depends on the upper and lower corners. However, when a desired complete dielectric isolation structure is to be arranged, using the conditions that the side-etching quantity of the oxide film for forming the mask is about 50 nm and that the etching quantity by the CDE is about 100 nm, the upper corners can be rounded, but it is difficult to round the lower corners. As a result, unwanted stress will be concentrated at the lower corners of the trench to increase the dislocation density of silicon crystal. Therefore, crystal defects will be produced at the lower corners of the trench. As described above, when such a conventional technique for rounding the upper corners of the trench is intended to be applied to the complete isolation structure in which portions of the trench to be rounded are present at the uppper and lower corners, it will be difficult to round the lower corners, and unwanted crystal defects will be produced in the semiconductor substrate. From EP-A-0296754 a method for forming a trench is known. This trench only reaches up to the isolation layer and not into said isolation layer. The corner portions are not formed by selective side etching and isotropic etching. From EP-A-0181188 it is known to provide a recess portion slightly underetching an oxide layer. It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device having a trench isolation region having no crystal defects in corners of said trench region. According to the present invention, this object is solved by providing the method according to claim 1. Further improvements of this invention are specified in the sub-claims being dependent on said claim 1. For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. In this case, the side-etching quantity and the isotropic etching quantity are controlled so as to provide desired rounded corners in respective isolated regions. Thereafter, side surfaces of the semiconductor substrate exposed within the trench are oxidized to provide an insulting film for dielectric isolation which has rounded corners. The invention and advantages thereof may best be understood by reference to the following description and accompanying drawings in which: Figs. 1A to 1F are sectional views showing sequential steps of making a complete dielectric isolation structure according to an embodiment of the present invention; Fig. 2 is a graph for explaining a relationship between a side-etching quantity of an oxide film for forming a mask and an etching quantity of trench corners according to the present invention; Fig. 3 is a sectional view for explaining crystal defects which are produced by defectively rounding the corners of the trench; and Figs. 4A to 4D are sectional views showing the conventional sequential steps of rounding corners of a trench. A method of making a complete dielectric isolation structure according to the embodiment of the present invention will be described below with reference to Figs. 1A to 1F. As shown in Fig. 1A, an insulating film 2 is formed on a silicon base substrate 1 to a thickness of the order of 1.5 µm by thermal oxidation techniques or the like, on which a silicon substrate 3 having a thickness of the order of 20 µm is adhered. Thereafter, an oxide film 4 formed on the silicon substrate 3 by the thermal oxidation techniques or the like is patterned to a desired configuration, and a trench 5 having a width of the order of 1 to 2 µm and a depth of the order of 20 µm is formed in the substrate 3 by RIE (Reactive Ion Etching) techniques so as to reach the insulating film 2, using the oxide film 4 as a mask. As shown in Fig. 1B, the resultant structure is dipped in a diluted HF solution to side-etch the oxide film 4 used as the mask. In this case, the insulating film 2 of the silicon oxide film is etched at the same time to expose upper and lower corners 6 and 7 of the silicon substrate 3. In this step, it is necessary to side-etch the oxide film 4 by 3,000 Å or more, but the upper limit of the etching quantity is defined by 1,000 nm or less which is smaller than the thickness of the oxide film 4 after the trench etching is completed. Thereafter, as shown in Fig. 1C, the silicon substrate 3 is isotropically etched by CDE (Chemical Dry Etching) techniques to remove the exposed corners 6 and 7. In this step, the corners 6 and 7 must be etched by 150 nm or more, but the upper limit is set to 500 nm or less in consideration of the area of isolation regions and a filling process of polysilicon. As shown in Fig. 1D, the resultant structure is heat-treated in an oxidizing atmosphere at a temperature of 1,050°C for 150 minutes to form a side wall oxide film 8 having a thickness of the order of 800 nm on the side walls of the trench 5, thereby rounding the corners 6 and 7. As shown in Fig. 1E, a polysilicon layer 9 is deposited on the resultant structure to a thickness of the order of 1.8 µm by low pressure CVD techniques to fill the inner portion of the trench 5 therewith. As shown in Fig. 1F, the surface of the resultant structure is etched back by the CDE technique to leave the polysilicon layer 9 inside the trench 5. Thereafter, the resultant structure is heat-treated in an oxidizing atmosphere at a temperature of 1,050 for 150 minutes to form an oxide film 10 on the polysilicon layer 9. Thus, isolated regions 11 which are dielectric-isolated from each other are provided. According to the method of the embodiment, the reliability of the semiconductor device of the present invention depends greatly on the parameters for controlling the conditions of rounding of the corners, which are given by both the side-etching quantity in the case where the oxide film 4 is side-etched by the diluted HF solution in the step in Fig. 1B, and the etching quantity of the corners 6 and 7 by the CDE in the step in Fig. 1C. Fig. 2 shows a relationship between the side-etching quantity X of the oxide film 4 and the etching quantity Y of the trench corners 6 and 7 when each thickness of the side wall oxide films 8 is given by 800 nm. According to the drawing, it is apparent that unwanted crystal defects are not produced at corners of isolated regions within a range of X ≦ 300 nm and Y ≦ 150 nm. As shown in Fig. 3, in other ranges, when the side wall oxide films 8 each having a thickness of about 800 nm on the side walls of the trench are formed in the same manner as in the step of Fig. 1D, the lower corners 7 cannot be rounded to produce crystal defects 12 therefrom. Therefore, in order to round the corners of the trench, the side-etching quantity of the oxide film serving as the mask and the etching quantity of the corners are important factors. As described above, according to the present invention, highly reliable semiconductor devices will be obtained since the production of crystal defects is eliminated from the isolated regions. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A method of making a complete dielectric isolation structure in a semiconductor device, comprising the steps of (a) forming a first oxide film (2) on a base substrate (1); (b) adhering a semiconductor substrate (3) on said oxide film (2); (c) forming a second oxide film (4) on said adhered semiconductor substrate (3); (d) patterning said second oxide film (4) to provide a mask on said semiconductor substrate (3); (e) selectively etching said semiconductor substrate (3) through said mask to provide at least one trench (5) reaching said first oxide film (2), said trench (5) having upper and lower corners (6, 7) on said semiconductor substrate (3); (f) oxidizing said side surfaces of said semiconductor substrate (3) exposed within said trench (5) to provide a third oxide film (8); and (g) filling said trench (5) with a polysilicon layer (9); characterized in that, before the step (f), (h) said mask of said second oxide film (4) is side-etched in an amount ranging from 0.3 µm to 1 µm, thereby exposing said upper corners (6), and simultaneously said first oxide film (2) is selectively etched to expose said lower corners (7); and (i) said exposed first and second corners (6, 7) of said semiconductor substrate (3) are subjected to isotropic etching by an amount ranging from 0.15 µm to 0.5 µm; (j) thereby providing rounding of said first and second corners (6, 7) so as to avoid producing of crystal defects near said first and second corners (6, 7) in a process of subsequent oxidation. A method according to claim 1, characterized in that a thickness of said third oxide film (8) is of the order of 800 nm. A method according to claim 1 or 2, characterized in that an exposed portion of said polysilicon layer (9) is oxidized. A method according to any of the preceding claims, characterized in that said first oxide film (2) is formed by thermal oxidation. A method according to any of the preceding claims, characterized in that said second oxide film (4) is formed by thermal oxidation. A method according to any of the preceding claims, characterized in that said trench (5) is formed by reactive ion etching (RIE). A method according to claim 1, characterized in that said side-etching according to step (h) is performed by dipping the structure in a diluted HF-solution. A method according to claim 1, characterized in that said isotropic etching according to step (i) is performed by chemical dry etching (CDE). A method according to claim 1, characterized in that said oxidizing according to step (j) is performed by a heat-treatment in an oxidizing atmosphere. A method according to claim 1, characterized in that said filling of said trench (5) according to step (g) is performed by a low pressure chemical vapor deposition (CVD). A method according to any of the preceding claims, characterized in that said polysilicon layer (9) is also deposited over said second oxide film (4). A method according to claim 11, characterized in that said polysilicon layer (9) is etched back by a chemical dry etching (CDE) step to leave the polysilicon layer (9) in said trench (5). A method according to claim 12, characterized in that said etched-back structure and said exposed portion of said polysilicon layer (9) are heat treated in an oxidizing atmosphere for forming an oxide film (10) on said exposed portion. A method according to any of the preceding claims, characterized in that said third oxide film (8) is so formed as to form a continuous isolation layer with said first and second oxide films (2, 4), with said polysilicon layer (9) filled therebetween. A method according to claims 13 and 14, characterized in that said oxide film (10) is so formed as to contact said continuous isolation layer to encapsulate said polysilicon layer (9) in said trench (5). A method according to claim 1, characterized in that etching quantities respectively provided in said selective etching according to step (h) and said isotropic etching according to step (i) are selected to a predetermined ratio, such that no crystal defects occur in corner portions of said trench (5).

Inventors: BABA YOSHIRO, KOSHINO YUTAKA, OSAWA AKIHIKO, YANAGIYA SATOSHI, BABA, YOSHIRO, KOSHINO, YUTAKA, OSAWA, AKIHIKO, YANAGIYA, SATOSHI, BABA, YOSHIRO, C/O INTELLECTUAL PROPERTY DIVISION, KOSHINO, YUTAKA, C/O INTELLECTUAL PROPERTY DIV., OSAWA, AKIHIKO, C/O INTELLECTUAL PROPERTY DIV., YANAGIYA, SATOSHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: H01L21
IPC codes: H01L21