A programmable semiconductor memory apparatus

Abstract: A programmable semiconductor memory apparatus comprises a memory cell array (1, 2, 3), a data sense circuit (4) for reading data from the memory cell array, and a bus line (B u1 ,...) connected to a common node of a plurality of bit lines (B₁, B₂,...) forming the memory cell array and to the data sense circuit (4), a circuit (Q 1D ,...) for storing an identifying code for identifying the programmable semiconductor memory apparatus is connected to the bus line, thereby enabling the identifying code to be read externally.

Description: Background of the Invention The present invention relates to a programmable semiconductor memory apparatus (called an RWM: Read/Write Memory) and more particularly to an RWM with a circuit for storing a device identifying code. An RWM can be generally divided into a RAM (Random Access Memory) and a ROM (Read Only Memory). A programmable ROM corresponds to an RWM. A programmable ROM is classified from the viewpoint of structure into a bipolar-type, a FAMOS (Floating-gate Avalanche Injection MOS) or an MNOS (Metal Nitride Oxide Semiconductor), and classified from the viewpoint of whether it is applied into a fuse ROM (programmable ROM), an EP-ROM(Erasable Programmable ROM), an EEP-ROM (Electrically Erasable and Programmable ROM), or an EA-ROM (Electrically Alterable ROM). An RWM is forwarded from the manufacturer in a blank state, i.e., in a state where the data is not written, the user-side writes data by ROM writer. A ROM writer has a function of automatically setting a condition for writing data into an RWM device. Therefore, a circuit for storing a self device identifying code and enabling the self device identifying code to be read upon writing data into RWM is generally provided on the device side. The self device identifying code represents the conditions for writing data into an RWM such as the name of a manufacturer memory capacity, the kind of writing algorithm and chip revision of the RWM. Figure 1 shows the structure of a prior art RWM circuit for explaining the operation of the RWM. An RWM generally comprises a first memory cell array 1 to a k-th memory cell array 3, and data sense circuits 4. More precisely, a RWM comprises bit lines B 1 to B m , word lines W 1 to W n and W c , memory transistors Q 11 to Q mn , bit line selection transistors Q 1s to Q ms , device identifying code storing transistors Q 1c to Q kc and bus lines B u1 to B uk . When a memory write is performed in the RWM, an address signal is produced to select one word line (for example W 1 ) and one bit line (for example B 1 ) to select a predetermined memory transistor Q 11 , and data is written by applying an "H" signal or an "L" signal to memory transistor circuit Q 11 . When data is read, a predetermined memory transistor Q 11 is selected by the same operation as above, thereby outputting the stored data. Generally, the device identifying code is stored in device identifying code storing transistors Q 1c to Q kc connected to the bit line. In the prior art shown in Figure 1, a device identifying code storing transistors Q 1c to Q kc is provided for respective memory cell arrays and as k device identifying code storing transistors Q 1c to Q kc are used, the number of device identifying codes comprises k bits. In a device of this type, only the exclusive word line W c may be selected to enable the device identifying code to be read out. This makes a device of this type easy to pattern and thus it is widely used. In accordance with a recent increase in the degree of LSI integration, a redundant bit line is generally provided to increase yield. A redundant bit line is provided by preparing several spare bit lines in the memory. Thus, even if a faulty bit line, word line or memory cell exists in a memory, a spare bit line is selected when an address signal selecting the faulty portion enters the memory. Thus, a device containing a fault can be used as if it were fault-free. When a redundant bit line is embodied, there is always a possibility of replacing a discretional bit line by a spare bit line. In this case the replaced bit line is not used thereafter. When the device identifying code storing transistor Q ic is connected to the replaced bit line, an element of the device identifying code stored in the device identifying code storing transistor Q ic , for example, the i-th element of the k-bit code, is lacking and thus cannot be read out. This prevents the device identifying code from performing an effective function. Therefore, when the bit line redundancy is embodied, the type with the device identifying code stored in the device identifying code storing transistor connected to the bit line cannot be used. Summary of the Invention From Patent Abstracts of Japan, vol. 8, no. 282 (P-323), Dec. 1984, & JP-A-59 146 498, a semiconductor memory having bit lines, spare bit lines and a bus line as described in the preamble of claim 1 is known. Document US-A-4,055,802 discloses a configuration with the purpose to provide a technology by which a circuit configuration can be electrically identified. A cathode of a diode is connected to respective input lines (or output lines) of a chip in a ROM and an electrical switch is provided at an anode side of the diode for switching over the coupling to ground or an emitter of the transistor. When an electrical interrogation signal is applied to the input lines an unique pattern appears representative of the particular circuit. Thus, from this document, a semiconductor memory is known having identifying code storing means connected to input lines or output lines. SUMMARY OF THE INVENTION An object of the present invention is to provide an improved RWM capable of storing the device identifying code to enable the device identifying code to be easily read out even when a bit line redundancy is adopted. According to the invention, this object is achieved by a programmable semiconductor memory apparatus according to claim 1. Brief Description of the Drawings Figure 1 shows a circuit diagram of an example of a conventional RWM, Figure 2 shows a circuit diagram of a first embodiment of the RWM of the present invention, Figure 3 shows a circuit diagram of a second embodiment of the RWM of the present invention, Figure 4 shows another embodiment of the present invention, Figure 5 shows a further embodiment of the present invention, and Figure 6 shows a still further embodiment of the present invention. Preferred Embodiments An embodiment of the present invention will be explained by referring to the drawings. Figure 2 shows the first embodiment of the present invention. In Figure 2, the same parts as those in the prior art shown in Figure 1 are provided with the same reference numbers, and detailed explanations of such parts are omitted. A programmable semiconductor memory apparatus comprises memory cell arrays 1,2,3, data sense circuits 4 for writing data into and reading data from said memory cell arrays 1,2,3, bus lines B u1 to B uk connected to a common node of a plurality of bit lines B 1 to B m , B s1 to B sj forming the memory cell arrays 1,2,3, and a means for storing an identifying code for identifying said programmable semiconductor memory device being coupled to said bus lines B u1 to B uk , thereby enabling said identifying code to be read externally. In the present invention with the above structure, even when a bit line redundancy is embodied in an RWM, a discretional spare bit line is selected in place of a faulty bit line. The device identifying code is not stored in device identifying code storing transistors Q 1c to Q kc connected to the bit line as in the case of the prior art RWM, but in a memory circuit connected to bus lines B u1 to B uk provided between the common node of the bit lines B 1 to B m and B s1 to B sj and the data sense circuits 4. Therefore, even if one of the faulty bit lines is disposed of, and instead any spare bit line is selected, a device identifying code can be correctly read out without being affected. In Figure 2, the portions which are different from those in Figure 1 are as follows. Spare bit lines B s1 to B sj are provided, the device identifying code storing transistors Q 1c to Q kc connected to the bit lines B 1 to B m are deleted and instead the device identifying code storing transistors Q 1D to Q kD connected to bus lines B u1 to B uk are newly provided. The number of spare bit lines is not limited to 1 per respective memory cell array. G ss to G sj represent gate terminals of spare bit line selecting transistors Q ss to Q sj . When the address signal for selecting a faulty bit line, for example B 2 , enters gate G 2s , an "H" signal for selecting a spare bit line, for example B s1 , is applied to gate G ss and bit line B 2 is replaced by spare bit line B s1 . A device identifying code is programmed in device identifying code storing transistors Q 1D to Q kD upon the manufacturing of an RWM. Device identifying code storing transistors Q 1D to Q kD are turned on when an (H) signal more than threshold voltage V TH is applied to the gates G 1D to G kD thereof and they are turned off when an (L) signal less than the threshold voltage V TH is applied to G 1D to G kD thereof. Thus, the device identifying storing transistors Q 1D to Q kD are of the enhancement type. Device identifying code storing transistors Q 1D to Q kD are of the type having a threshold voltage V TH changed by an electric operation. For example, the transistors Q 1D to Q kD are formed such that in accordance with an electrical operation, they have two threshold voltages comprising a voltage V 1 which is higher than the source voltage Vcc and a voltage V 2 which is lower than the source voltage Vcc. Codes determined as being logic "0" or "1" depending on voltages V 1 and V 2 are provided for respective device identifying code storing transistors Q 1D to Q kD . When the power source voltage Vcc is applied to gates G 1D to G kD , the transistor with the threshold voltage of V 1 is turned off and the transistor with the threshold voltage V 2 is turned on. Namely, k bits of device identifying code can be stored by determining that logic "0" corresponds to voltage V 1 and logic "1" corresponds to voltage V 2 , depending on whether the threshold voltage of the transistors Q 1D to Q kD is determined as being V 1 or V 2 . Conversely, k bits of device identifying code may be stored by determining that logic "1" corresponds to voltage V 1 and logic "0" corresponds to voltage V 2 . In other words, the device identifying code can be programmed based on threshold voltages V 1 and V 2 of device identifying storing transistors Q 1D to Q kD . Address signals A Do to A Dn and signature signal SGH are applied to NAND circuit 11. The output of NAND circuit 11 is applied to gates G 1s to G ms of bit line selecting transistors Q 1s to Q ms and gates G ss to G sj of spare bit line selecting transistors Q ss to Q sj through inverter 12. Next, the operation of the present invention will be explained. When a memory write and memory read is performed, the same operation as in the ordinary RWM is conducted and one memory transistor, for example, Q 11 , is selected and the data to be stored is input to the RWM. When the device identifying code is read out, an "L" signal is applied to all the gates of G 1s to G ms of bit line selecting transistors Q 1s to Q ms and gates G ss to G sj of spare bit line selecting transistors Q ss to Q sj from inverter 12, as signature singal SGH is turned high. Thus all the bit lines are electrically disconnected from the bus lines B u1 to B uk . Next, source voltage V cc is applied to gates G 1D to G kD of device identifying code storing transistors Q 1D to Q kD and thus the device identifying code can be read out. Alternatively, NMOS transistors may be provided between the common nodes of bit lines and a spare bit line forming memory cell arrays 1, 2 and 3 and drains of NMOS transistors Q 1D to Q kD . The signature signal SGH may be applied to gates of the NMOS transistors to read the device idintifying code. The Second Embodiment Figure 3 shows the second embodiment of the present invention. This embodiment is different from that in Figure 2 in that device identifying storing transistors Q 1E to Q kE are provided in place of device identifying code storing transistors Q 1D to Q kD shown in Figure 2, and electric switching means S 1E to S kE are provided on a line connecting device identifying code storing transistors Q 1E to Q kE and bus lines B u1 to B uk . Device identifying code storing transistor Q 1E to Q kE are different from device identifying code storing transistors Q 1D to Q kD in that the threshold voltage V TH may not be variable in accordance with an electric operation. Transistors Q 1D to Q kD turn on when an (H) signal is applied to gates G 1E to G kE . In the second embodiment the threshold voltage V TH is made less than or equal to power source voltage Vcc. In the second embodiment, the device identifying code is programmed by using electric switching means S 1E to S kE . Electric switching means S 1E to S kE may be of the so-called fuse type which are conductive before programming but are melted to be cut out or made nonconductive by an application of a current upon programming. Electric switching means S 1E to S kE may also be of the type which are nonconductive before programming but, are made conductive by an application of a current upon programming when connected through melting. It is possible to program the device identifying code by determining logic "1" for ON and determining logic "0" for OFF, depending on whether the electric switching means is conductive (ON) or nonconductive (OFF). Conversely, the program of the device identifying code may be performed so that logic "1" is determined for OFF and logic "0" for ON for electric switching means S 1E to S kE . In this case, the device identifying code comprises k-bit code, as the number of the electric switching means is k. Next, the operation will be explained. In case of a memory write or read, the same operation as in the first embodiment may be performed. When the device identifying code is read, an (L) signal is applied to all the gates of bit line selection transistors Q 1S to Q ms and gates G ss to G sj of spare bit line selection transistors Q ss to Q sj and all the bit lines are cut off from bus lines B u1 to B uk . Next, when the source voltage Vcc is applied to gate G 1E to G kE of device identifying code storing transistors Q 1E to Q kE , the device identifying code is programmed depending on the on-and-off electric switching means S 1E to S kE . Figure 4 shows an embodiment in which device identifying code transistor Q 1E is provided with a data sense circuit 4. A sense amplifier comprises transistor T 1 , T 2 , T 3 , T 4 and T 6 . When the data is not stored in a cell connected to the bus line B u1 , the voltage of the bus line B u1 is made low and NMOS transistor T 3 is turned off, thus the NMOS transistors T 4 and T 6 are turned on, thus the current is deprived from a line sense amplifier OUTPUT through NMOS transistor T6, and thus the voltage of the line sense amplifier OUTPUT is made low. As a result, low data is read from the cell. When a signature signal SGH is high, PMOS transistor T 1 is turned off and thus the sense amplifier does not operate. When the signature signal SGH applied to the device identifying code NMOS transistor Q 1E is high, the device identifying code is read out from the line sense amplifier OUTPUT of the sense amplifier, depending on whether the switch S 1E provided between the device identifying transistor Q 1E and the line sense amplifier OUTPUT is on or off. That is, when the switch S 1E is opened, the logic "0" is output from sense amplifier OUTPUT and when the switch S 1E is closed, the logic "1" is output. In this embodiment, when the device identifying code is read out, it is necessary both to apply an "L" signal to all the gates of the bit line selection transistors and spare bit line selection transistors and to apply a high signature signal SGH "H" to the gate of the device identifying NMOS transistor Q 1E . Figure 5 shows an embodiment in which a device identifying code circuit element is provided in an output buffer. When the signature SGH becomes "H" the device identifying code is read out. When switch A is connected to V ss and switch B is connected to the signal SGH, then output transistor T 19 produces "H" through a NOR circuit comprising transistors T 11 , T 12 , T 13 and T 14 and a NOR circuit comprising transistors T 15 , T 16 , T 17 and T 18 . That is, when switch B is connected to signature SGH and is high, NMOS transistor T 18 is turned on and line L 1 becomes low, enabling the output of output transistor T 19 to be "H". Next, in order to make the data output "L", the switch A is connected to signature SGH and the switch B is connected to Vss. Therefore, NMOS transistor T 14 becomes conductive and line L 2 becomes low, thereby enabling NMOS transistor T 17 to be nonconductive and PMOS transistor T 16 to be conductive. Therefore, line L 1 becomes high and thus the output of output transistor T 19 becomes "L". When the signature SGH is low, switch A is connected to Vss and switch B to SGH, both NMOS transistors T 14 and T 18 become nonconductive and thus, the signature SGH for obtaining the device identifying code is cut off from a signal transmission line from sense amplifier OUTPUT, line L 2 , line L 1 , and DATA OUTPUT. In this case, PMOS transistor T 11 is turned on and when sense amplifier OUTPUT is "H", PMOS transistor T 12 is nonconductive and line L2 is "L". Then, PMOS transistors T 15 and T 16 become conductive, thereby allowing line L 1 to be "H" and DATA OUTPUT of transistor T 19 to be "L". Thus, when the signature SGH is "L", the output of the sense amplifier is provided at the DATA OUTPUT after the output of the sense amplifier is inverted. In this embodiment the output of the data sense circuit is applied to the sense amplifier output line sense amplifier OUTPUT and the device identifying code is read out from the data output through the output transistor T 19 . As shown in Figure 6, instead of replacing a faulty bit line by a spare bit line, a block comprising a plurality of bit lines can be replaced by a spare block. Respective blocks 1 to 4 correspond to the output of the device for producing 4 bit output. If a block 1 is faulty, then signal SP1 turns "H" and SP1 turns "L" and then the block 1 corresponding to one output bit of 4 bit output is replaced by a spare block. More specifically, an address signal is applied to blocks 1 to 4 and spare block through row decoder 13 and column decoder 14 and is also applied to a redundant control circuit 15, in which an address corresponding to a faulty cell is stored, for example. Thus, when the address signal corresponding to the faulty cell is applied to redundant control circuit 15, switch 16 is turned to Vcc . Thus, SP n becomes high and SP n becomes low through inverter 17, thereby selecting the spare block. Device identifying code storing transistors are respectively connected to blocks 1 to 4 and spare block through electric switching means and bus lines in the same manner as shown in Figure 2 and 3. Data D 1 to D 4 are read out from the data sense circuit. Therefore, the present invention can be applied to the embodiment shown in Figure 6 in which the faulty bit line block among the respective blocks 1 to 4 can be replaced by a spare block. The present invention is also applicable to the case where each of respective blocks 1 to 4 comprise one bit line. The embodiments of the RWM as shown in Figures 2 to 6 are designated as being the present invention. However, the RWM circuit structure is not limited to these embodiments as the RWM having other circuit structures is within the scope of the present invention. For example, as the RWM of the present invention is useful where bit line redundancy does not exist, an RWM which does not have a spare bit line is within the scope of the present invention. The device identifying code storing circuit connected to the bus line may be formed of other means for storing the code. The circuit structure of the present invention is not limited to the embodiments shown in Figures 2 and 3. The other circuit structure may be within the scope of the present invention. In the above embodiments, one cell for storing logic "1" or "0" comprises one transistor, for example Q 1n , but it may comprise a plurality of transistors. As described above, according to the present invention, even if bit line redundancy exists in the RWM, the device identifying code can be stored in the RWM by programming a program using the device identifying code storing circuit connected to the bus line. Thus, even if the fault bit line is disposed and the spare bit line is selected, the device identifying code can be read out without it being affected by a selection of the spare bit line.

Claims: A programmable semiconductor memory apparatus in which bit line redundancy is adopted comprising: a memory cell array (1, 2, 3); a plurality of bit lines (B 1 , B 2 , ...) connected to said memory cell array; at least one spare bit line (B S1 , B S2 , ...) which is switched and used if said plurality of bit lines (B 1 , B 2 , ...) includes faulty bit lines; at least a bus line (B u1 , B u2 , ...) connected to one of said bit lines (B 1 , B 2 , ... ) or said at least one spare bit line (B s1 , B s2 , ...) in response to an address signal (G ms , G sj ) ; a data sense circuit (4) connected to said at least one bus line for reading data from said memory cell array, characterized by at least a storing means (Q 1E , Q 2E , ...) for storing an identifying code for identifying said programmable semiconductor memory apparatus, said storing means being coupled to the output of the data sense circuit (4), thereby enabling said identifying code to be read externally without lack of bits of said identifying code if faulty bit lines (B 1 , B 2 , ...) are replaced by spare bit lines (B s1 , B s2 , ...); a switch means (T1, T2) connected to said data sense circuit (4), for receiving a signature signal (SGH) designating that the identifying code has been read out from said storing means (Q 1E , Q 2E , ...) and for producing the identifying code regardless of the input of the data sense circuit (4), said switch means (T1, T2) affecting said data sense circuit (4) such that the identifying code appears at the output of said data sense circuit (4). The programmable semiconductor memory apparatus according to claim 1, characterized in that all word lines (W1, W2, ...) of said memory cell array (1, 2, 3) are made non-active when the identifying code is read out. The programmable semiconductor memory apparatus according to claim 1 or 2, characterized in that said storing means comprises a transistor having a first threshold voltage or a second threshold voltage; and the transistor becomes conductive or non-conductive when a gate voltage is applied to said transistor, thereby providing logic "1" and "0", respectively. The programmable semiconductor memory apparatus according to claim 1 or 2, characterized in that said storing means comprises a transistor (Q 1E , Q 2E , ...) connected to the bus line (B u1 , B u2 , ...) through a fuse (S 1E , S 2E , ...) provided between the drain and the bus line (B u1 , B u2 , ...). The programmable semiconductor memory apparatus according to anyone of claims 1 - 4, characterized in that said storing means is provided within said data sense circuit (4). The programmable semiconductor memory apparatus according to anyone of the claims 1 - 4, characterized in that said storing means is provided within an output buffer circuit. The programmable semiconductor memory apparatus according to anyone of claims 1 to 6, characterized in that said switching means controls a gate of a pull-up transistor to determine whether a data from said data sense circuit (4) is output or said identifying code is output. The programmable semiconductor memory apparatus according to anyone of the claims 1 to 4, characterized in that said memory cell array (1, 2, 3) is divided into respective blocks connected to bit lines and spare blocks connected to spare bit lines, one of said bit lines and one of said spare bit lines of each block being connected to one of said bus lines, each one of said bus lines being connected to one of said storing means; and switching means are provided between said respective block and said bus line and between said spare block and said bus line, and switch and connect said spare block to said bus line in place of said respective blocks when said respective blocks are faulty.

Inventors: AKAOGI TAKAO, AKAOGI, TAKAO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G06F11
IPC codes: G11C29, G11C16, G11C5, G06F11, G11C17