Testing method, testing circuit and semiconductor integrated circuit having testing circuit

Abstract: A testing method tests functions of a semiconductor integrated circuit which has a plurality of blocks (A₁-A m ) each having a main block circuit part (B₁-B m ) and an output part (C₁-C m ). The testing method comprises the steps of supplying a control signal (TM₁-TM m ,TMODE) to the output part of each of the blocks in a normal mode so that each output part outputs an output data (I₁-I n ) of the main block circuit part of a corresponding one of the blocks, supplying the control signal and a test data (T₁-T n ,T) to the output part of each of the blocks in a test mode so that each output part outputs the test data which is supplied to the main block circuit part of another block, and comparing the output data and the test data in the output part of each of the blocks in the test mode and outputting a failure detection signal (SO₁-SO m ) which is indicative of a failure in a corresponding one of the blocks when the compared output data and test data do not match in the one block.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to testing methods, testing circuits and semiconductor integrated circuits having a testing circuit, and more particularly to a testing method, a testing circuit and a semiconductor integrated circuit having the testing circuit for testing blocks of the semiconductor integrated circuit. Recently, there are demands to develop a standard-cell LSI in which blocks having the functions of the conventional LSI chips are integrated, so as to provide systems such as computers on chips. Similarly to the conventional system design in which the LSI is often treated as a black box, the block is often treated as a black box when the user makes the circuit design of the standard-cell LSI. For this reason, the manufacturer of the standard-cell LSI must test each of the blocks to guarantee the functions of the blocks. However, it is difficult to make direct access to the blocks from the external signal pins of the LSI because the number of signal pins on the LSI is limited. Hence, there is a demand to provide a means within the LSI that would enable testing of each block. In the conventional LSI chip, when testing a part of the LSI to which a direct access cannot be made from the external signal pin of the LSI, flip-flops or the like are used to read and write the test data. When using the flip-flops to test each block, the flip-flops are connected to input and output terminals of each block, for example. The flip-flops connected to the input terminals are used for writing the test data, and the flip-flops connected to the output terminals are used for reading the test data. As methods of writing and reading the test data, there basically are two methods. According to a first method, scan-in and scan-out functions are provided in each latch circuit and the test data is selectively written and read out based on the scan address. On the other hand, according to a second method, a shift register is formed by connecting the flip-flops in series and the test data is written and read out by a shift operation of the shift register. According to the conventional testing method, the latch circuits or flip-flops are provided at the input and output terminals of each block. By the provision of the latch circuits or flip-flops, the scale of the circuit of each block becomes large. As a result, there are problems in that the area occupied by each block increases, the power consumption of each block increases, the propagation delay time increases and the like, thereby deteriorating the performance of the LSI. Furthermore, when the first method described above is employed to write and read out the test data, it is necessary to connect address and clock signal lines to each latch circuit, and the number of interconnections which must be connected to each block increases. That is, there is a need to widen the channel region for the interconnections between the blocks, and this leads to a further decrease in the integration density. FIG.1 schematically shows the interconnections between the blocks when the first method is employed. In FIG.1, a semiconductor integrated circuit includes a block 100 i having an input part 101 i and an output part 102 i , where i = 1, 2 and 3 in this case. A group of interconnections made up of an address line, a clock signal line and the like for the latch circuits forms a test bus 104. As may be seen from FIG.1, the test bus 104 is connected to both the input part 101 i and the output part 102 i of each block 100 i and the number of interconnections is extremely large. FIG. 1 also shows an input terminal group 106 and an output terminal group 107. On the other hand, when the second method described above is employed to write and read out the test data, it takes a long time to write and read out the test data as the number of flip-flops becomes large. As a result, the test time becomes long and the efficiency of the test process becomes poor. There is disclosed in document DE-A-3 832 113 a circuit for testing functional blocks within an IC, based on scanning flip-flops that are interconnected to form a single shift register path. Signal propagation times are reduced by providing selection circuits connected to respective control inputs of the shift registers so that the registers associated to un-tested blocks pass the data through without clocking. Finally, there is disclosed in document DE-A-3 832 440 a testing circuit adapted for RAM devices, in which long propagation delay times resulting from serially-connected scan latches used for testing the functional blocks are reduced by means of an expected value generator. This generator is responsive to the test data fed to the functional blocks and provides a reference for comparison with the data outputted by the functional block. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a novel and useful testing method, a testing circuit and a semiconductor integrated circuit having the testing circuit in which the problems described above are eliminated. This object is achieved by a method of testing functions of a semiconductor integrated circuit which has a plurality of blocks each having a main block circuit part and an output part, said testing method comprising the provision of selector means in the output part of each of the blocks and sending thereto a test control signal, test data, and the main block output data coming from the main block circuit part of a corresponding one of the blocks; arranging for said selector means to output the main block output data in the normal mode; further providing said selector means with comparison means provided in each block for comparing the main block output data and the test data in each of the blocks in the test mode; whereby : if the compared data are equal said selector means is caused to output the main block output data, which are identical to the test data, directly from the output of the block to the input of the normal operation circuitry in the next block without any intermediate circuitry; if the compared data are not equal, said selector means is caused to output the inverted main block output data, which are identical to the test data, directly from the output of the block to the input of the normal operation circuitry in the next blocks; and a failure detection signal, the failure detection signals of all blocks being fed into an OR-gate, the output of which is connected to an IC output pin. According to the testing method of the present invention, there is no need to connect interconnections for use during the test mode. For this reason, it is possible to suppress the increase in the area which is occupied by the blocks as well as the power consumption Furthermore, the propagation delay time is also reduced. The object is also achieved by a semiconductor integrated circuit which has a plurality of blocks each having a main block circuit part and an output part, said testing circuitry comprising : selector means in the output part of each of the blocks receiving a test control signal, test data, and the main block output data coming from the main block circuit part of a corresponding one of the blocks; said selector means being arranged to output the main block output data in the normal mode; said selector means further comprising comparison means provided in each block for comparing the main block output data and the test data in each of the blocks in the test mode; whereby : if the compared data are equal said selector means outpout the main block outpout data, which are identical to the test data, directly from the output of the block to the input of the normal operation circuitry in the next block without any intermediate circuitry; if the compared data are unequal, said selector means output the inverted main block output data, directly from the output of the block to the input of the normal operation circuitry in the next block; and a failure detection signal, the failure detection signals of all blocks being fed into an OR-gate, the output of which is connected to an IC output pin. Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 schematically shows conventional interconnections between blocks when a first, known, method is employed; FIG.2 is a circuit diagram showing an essential part of a semiconductor integrated circuit for explaining an embodiment of a testing method, a testing circuit and a semiconductor integrated circuit having the testing circuit according to the present invention; FIG.3 is a circuit diagram showing an embodiment of an output part of one block shown in FIG.2; FIG.4 generally shows connections of a shift register when a first system is employed; FIG.5 generally shows connections of a shift register when a second system is employed; FIG.6 is a circuit diagram showing a selector of the output part shown in FIG.3; FIG.7 is a system block diagram showing an embodiment of one block shown in FIG.2; FIG.8 is a circuit diagram showing an embodiment of an output part of the block shown in FIG7; FIG.9 is a circuit diagram showing an embodiment of a latch circuit shown in FIG.8; and FIG.10 is a diagram showing an embodiment of an arrangement of blocks on a chip. DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.2 is a circuit diagram showing an essential part of a semiconductor integrated circuit for explaining an embodiment of a testing method, a testing circuit and a semiconductor integrated circuit having the testing circuit according to the present invention. In FIG.2, the semiconductor integrated circuit includes m blocks A 1 through A m which are all arranged within one chip. Each block A i has a main block circuit part B i and an output part C i which receives an output data I (I 1 through I n ) from the main block circuit part B i and outputs this output data I as it is in a normal mode, where i = 1, ..., m. An input terminal 16 of the chip is connected to the main block circuit part B 1 of the block A 1 , and input signals 18 and 20 from other blocks are supplied to the main block circuit part B 1 . An output terminal 22 of the chip is connected to the output part C 1 of the block A 1 , and the output part C 1 supplies output signals 24, 26 and 28 to other blocks. For example, the output part C 1 of the block A 1 supplies the output signal 28 to the main block circuit part B 2 of the other block A 2 . Similarly, input signals 30 and 32 from other blocks are supplied to the main block circuit part B 2 of the block A 2 , and the output signal 28 from the output part C 1 of the other block A 1 is supplied to the main block circuit part B 2 of the block A 2 . In addition, an output terminal 34 of the chip is connected to the output part C 2 of the block A 2 , and the output part C 2 supplies output signals 36 and 38 to other blocks. An output signal 40 is supplied directly from the main block circuit part B 2 to an output terminal 42. A TMODE terminal 44 is included in the input terminals of the chip. The operation mode of the output parts C 1 through C m of the blocks A 1 through A m are switched between the normal mode and a test mode depending on a control signal TM which is received from the TMODE terminal 44. First, when the output parts C 1 through C m are set to the normal mode, each output part C i outputs the output data I (I 1 through I n ) of the corresponding main block circuit part B i as it is. On the other hand, when the output parts C 1 through C m are set to the test mode, each output part C i receives a test data T (T 1 through T n ) and each output part C i outputs the test data T. In addition, each output part C i compares the test data T and the output data I from the corresponding main block circuit part B i and outputs a failure detection signal SO i when the two do not match. The failure detection signals SO 1 through SO m output from the output parts C 1 through C m are output via the output terminals 22, 34 and the like. In the semiconductor integrated circuit shown in FIG.2, all of the inputs of each block A i are connected to the input terminals of the chip or to the outputs of other blocks, and the blocks A 1 through A m are mutually independent. Accordingly, when the output parts C 1 through C m are set to the test mode, it is possible to test only the block of interest regardless of whether or not a failure exists in other blocks. Furthermore, when a failure is detected in the block A j of interest, the failure detection signal SO j is output from the output terminal 22, 34 or the like so that it is possible to accurately detect the block in which the failure exists. Normally, latch circuits or flip-flops are used to write and read out the test data T. As methods of writing and reading the test data, there basically are two methods. According to the first method, scan-in and scan-out functions are provided in each latch circuit and the test data is selectively written and read out based on the scan address. On the other hand, according to the second method, a shift register is formed by connecting the flip-flops in series and the test data is written and read out by a shift operation of the shift register. For the sake of convenience, a description will first be given of a case where the second method is employed to write and read out the test data. FIG.3 shows the structure of the output part C 1 as one embodiment of the output parts C 1 through C m of the blocks A 1 through A m . In FIG.3, the output part C 1 has a shift register part SR and a selector part SEL. The shift register part SR includes a plurality of D flip-flops 12 1 through 12 n which are connected in series. A scan data from a scan data input terminal 50 of the chip is supplied to a data input terminal D of the flip-flop 12 1 . A scan clock from a scan clock input terminal 52 of the chip is supplied to a clock input terminal C of each of the flip-flops 12 1 through 12 n . The data output from the output terminals D of the flip-flops 12 1 through 12 n are supplied to the selector part SEL as the test data T 1 through T n . The selector part SEL has a plurality of selectors 14 1 through 14 n , and each selector 14 k includes elements E k , G k , and F k , where k = 1, ..., n. The elements E1 through En respectively obtain an inverse (NOT) of an exclusive-OR. The elements F1 through Fn respectively obtain an inverse (NOT) of a logical sum (OR). The elements G1 through Gn respectively obtain an exclusive-OR. The output data I 1 through I n from the main block circuit part B 1 are supplied to the corresponding elements E1 through En and the corresponding elements G1 through Gn. In addition, output data O 1 through O n from the elements G1 through Gn are output as outputs of the selectors 14 1 through 14 n . A logical sum of outputs of the elements F1 through Fn are obtained by a wired-OR, and a failure detection signal SO 1 is output to the SOUT1 terminal 22. In addition, the elements F1 through Fn receive the control signal TM 1 from the TMODE terminal 44, and the operation mode of the selectors 14 1 through 14 n are set to the normal mode or the test mode. As systems of generating the test data T 1 through T n , there is a first system in which the shift register parts SR of the output parts C 1 through C m of the blocks A 1 through A m are connected in series to form one shift register, and a second system in which one shift register is formed for every shift register part SR of each of the output parts C 1 through C m of the blocks A 1 through A m . FIG.4 generally shows the connection of the shift register parts SR for four blocks A 1 through A 4 when the first system is employed. In this case, i = 1, 2 and 3 and the output terminal Q of the flip-flop 12 n of the shift register part SR in the output part C i is connected to the data input terminal D of the flip-flop 12 1 of the shift register part SR in the output part C i+1 . FIG.5 generally shows the connection of the shift register parts SR for four blocks A 1 through A 4 when the second system is employed. In this case, the data input terminals D of the flip-flops 12 1 of the shift register parts SR in the output parts C 1 through C 4 are respectively connected to input terminals 50, 54, 56 and 58. When the input terminals 50, 54, 56 and 58 are independently provided with respect to each of the blocks A 1 through A 4 , the number of pins of the chip becomes large. For this reason, it is possible to provide an input switching circuit (not shown) within the chip so that the input terminals 50, 54, 56 and 58 become the input terminals for the scan data only during the test mode and become the input terminals for other data during the normal mode, that is, multiple uses are assigned to the input terminals. Returning to the description of the operation of the output part C 1 shown in FIG.3, a high-level control signal TM 1 is supplied from the TMODE terminal 44 to the selectors 14 1 through 14 n of the selector part SEL in the normal mode. For this reason, one input to each of the elements F1 through Fn has a high level, and a low-level output is obtained from the elements F1 through Fn regardless of whether the other input to each of the elements F1 through Fn has a high level or a low level. Accordingly, one input to each of the elements G1 through Gn has a low level, and the other input to each of the elements G1 through Gn, that is, the output data I 1 through I n of the main block circuit part B 1 are output as they are as the output data O 1 through O n . On the other hand, the control signal TM 1 from the TMODE terminal 44 has a low level in the test mode. Hence, one input to each of the elements F1 through Fn has a low level. When the output data I 1 through I n match the corresponding test data T 1 through T n , that is, when the output data I 1 through I n and the test data T 1 through T n both have the high level or the low level, high-level signals are output from the elements E1 through En and low-level signals are output from the elements F1 through Fn. Thus, one input to each of the elements G1 through Gn has a low level, and the test data T 1 through T n are output from the elements G1 through Gn as the output data O 1 through O n . In addition, because the low-level signals are output from the elements F1 through Fn, the failure detection signal SO 1 has a low level. Therefore, the low-level failure detection signal SO 1 indicates that no failure exists in the block A 1 . On the other hand, when the output data I 1 and the test data T 1 do not match, for example, that is, when the output data I 1 has a high level and the test data T 1 has a low level or vice versa, a low-level signal is output from the element E1 and a high-level signal is output from the element F1. Accordingly, one input to the element Gl has a high level, the output data I 1 is inverted and the test data T 1 is output as the output data O 1 . In addition, because the high-level signal is output from the element F1, the failure detection signal SO 1 has a high level. Therefore, the high-level failure detection signal SO 1 indicates that a failure exists in the block A 1 . As described above, it is possible to discriminate whether or not a failure exists in the block A 1 from the level of the failure detection signal SO 1 that is, whether the failure detection signal SO 1 has a high level or a low level. The output terminals (SOUT) for the failure detection signals SO 1 through SO m may be provided for each of the blocks A 1 through A m as shown in FIG.2, or may be used in common for the blocks A 1 through A m by providing a selector (not shown) or the like. In addition, when there is no need to detect the failure for each of the blocks A 1 through A m , it is possible to obtain a logical sum of the failure detection signals SO 1 through SO m by a wired-OR and output a single failure detection signal from one output terminal (SOUT) of the chip. FIG.6 shows the circuit structure of the selector 14 n of the output part C 1 shown in FIG.3 when the selector 14 n is formed by an emitter coupled logic (ECL) circuit having two stages of series connected gates. In the above described embodiment, the chip includes m blocks A 1 through A m . However, the embodiment is similarly applicable to a chip which includes only one block, and in such a case, the failure of the block can be detected similarly to detect the failure of the chip. When the second method is employed to write the test data T, there is no need to provide flip-flops for the test within an input part of each block and it is possible to reduce the length of the shift register part. In addition, since there is no need to read out the test data, it is possible to reduce test time by considerably reducing the time it takes to write and read out the test data. Further, in the semiconductor integrated circuit which includes a large number of blocks, it is possible to efficiently discriminate the existence of failure for each block. Next, a description will be given of a case where the first method is employed to write the test data T. FIG.7 shows an embodiment of the block A 1 shown in FIG.2, and FIG.8 shows the circuit structure of the output part C 1 of the block A 1 shown in FIG.7. In FIG.7, a test bus 62 is connected to the output part C 1 of the block A 1 . The test bus 62 includes address lines, a clock signal line and a reset signal line. The address lines receive an address (2 s address locations) which is obtained by decoding an s-bit scan address Add-1 in a decoder 64 and an address (2 t address locations) which is obtained by decoding a t-bit scan address Add-2 in a decoder 66. These scan addresses Add-1 and Add-2 may be supplied from outside the chip via input terminals to which multiple uses are assigned, or may be generated from an address generating circuit (not shown) which is provided within the chip. A 1-bit scan clock SCK is supplied to the clock signal line, and a 1-bit scan reset signal SRST is supplied to the reset signal line. In FIG.8, those parts which are the same as those corresponding parts in FIG.3 are designated by the same reference numerals, and a description thereof will be omitted. In FIG.8, the output part C 1 has a scan latch part SL and the selector part SEL. The scan latch part SL includes a plurality of latch circuits 72 1 through 72 n . A bit A-11 of the scan address Add-1 is supplied to address input terminals AD1 of each of the latch circuits 72 1 through 72 n . In addition, bits A-21 through A-2n of the scan address Add-1 are supplied to address input terminals AD2 of the corresponding latch circuits 72 1 through 72 n . The scan clock SCK and the scan reset signal SRST are respectively supplied to a clock input terminal SCK and a reset terminal SRST of each of the latch circuits 72 1 through 72 n . Outputs from output terminals Q of the latch circuits 72 1 through 72 n are supplied to the selector part SEL as the test data T 1 through T n . FIG.9 shows the circuit structure of the latch circuit 72 1 as an embodiment of the latch circuits 72 1 through 72 n . In FIG.9, the latch circuit 72 1 includes OR circuits 82 and 84 and an AND circuit 86. The scan reset signal SRST and an output signal of the AND circuit 86 are supplied to the OR circuit 82. The scan clock SCK and the scan address bits A-11 and A-21 are supplied to the OR circuit 84. An output signal of the AND circuit 86 is output from the output terminal Q as the output of the latch circuit 72 1 . FIG.10 shows an embodiment of the arrangement of the blocks on the chip when nine blocks are provided. In FIG.10, those parts which are the same as those corresponding parts in FIGS.2 and 7 are designated by the same reference numerals, and a description thereof will be omitted. In addition, the illustration of the normal interconnections between the blocks is omitted in FIG.10 for the sake of convenience. When the first method is employed to write and read out the test data T as described above, it is necessary to connect to the output parts of each of the block to the test bus (interconnections for the test) which includes the address line, the clock signal line and the like. However, no interconnections for the test need to be connected to the input parts of each of the blocks. For this reason, it is possible to suppress the decrease in the integration density which would be caused by a widening of the interconnections between the blocks in the channel region. In addition, in the semiconductor integrated circuit which includes a large number of blocks, it is possible to efficiently discriminate the existence of the failure for each block. Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.

Claims: A method of testing functions of a semiconductor integrated circuit which has a plurality of blocks (A 1 -A m ) each having a main block circuit part (B 1 -B m ) and an output part (C 1 -C m ), said testing method comprising: the provision of selector means (14 1 -14 m ) in the output part (C 1 -C m ) of each of the blocks (A-A m ) and sending thereto a test control signal (TM 1 ), test data (T 1 -T n ), and the main block output data (I 1 -I n ) coming from the main block circuit part (B 1 -B m ) of a corresponding one of the blocks; arranging for said selector means (14 1 -14 m ) to output the main block output data in the normal mode; further providing said selector means (14 1 -14 m ) with comparison means (E 1 -E m ) provided in each block for comparing the main block output data (I 1 -I n ) and the test data (T 1 -T n ) in each of the blocks in the test mode; whereby: if the compared data are equal, said selector means (14 1 -14 m ) is caused to output the main block output data. which are identical to the test data, directly from the output of the block to the input of the normal operation circuitry in the next block without any intermediate circuitry; if the compared data are not equal, said selector means (14 1 -14 m ) is caused to output : the inverted main block output data directly from the output of the block to the input of the normal operation circuitry in the next block; and a failure detection signal (SO 1 -SO m ), the failure detection signals of all blocks being fed into an OR-gate, the output of which is connected to an integrated circuit IC output pin. The testing method as claimed in claim 1, characterized in that each of said output parts (C 1 -C m ) include a shift register (SR), said test data (T 1 -T n ) is supplied to the shift register of the output part (C 1 ) of a first stage, and the shift registers of the output parts (C 2 -C m ) of second and subsequent stages are respectively supplied as the test data an output of the shift register of the output part (C 1 -C m-1 ) in a previous stage. The testing method as claimed in claim 1, characterized in that each of said output parts (C 1 -C m ) include a shift register (SR), and said test data (T 1 -T n ) is independently supplied to each of the shift registers of the output parts (C 1 -C m ) of the blocks (A 1 -A m ). The testing method as claimed in claim 1, characterized in that a scan address (Add-1, Add-2) is supplied to the output part (C 1 -C m ) of each of the blocks (A 1 -A m ) to designate an output part which is to be tested. A testing circuit in a semiconductor integrated circuit which has a plurality of blocks (A 1 -A m ) each having a main block circuit part (B 1 -B m ) and an output part (C 1 -C m ), said testing circuit comprising selector means (14 1 -14 m ) in the output part (C 1 -C m ) of each of the blocks (A-A m ) receiving a test control signal (TM 1 ), test data (T 1 -T n ), and the main block output data (I 1 -I n ) coming from the main block circuit part (B 1 -B m ) of a corresponding one of the blocks; wherein : said selector means (14 1 -14 m ) are arranged to output the main block output data in the normal mode; said selector means (14 1 -14 m ) further comprises comparison means (E 1 -E m ) provided in each block for comparing the main block output data (I 1 -I n ) and the test data (T 1 -T n ) in each of the blocks in the test mode; whereby : if the compared data are equal said selector means (14 1 -14 m ) output the main block output data, which are identical to the test data, directly from the output of the block to the input of the normal operation circuitry in the next block without any intermediate circuitry; if the compared data are unequal, said selector means (14 1 -14 m ) output : the inverted main block output data, directly from the output of the block to the input of the normal operation circuitry in the next block; and a failure detection signal (SO 1 -SO m ), the failure detection signals of all blocks being fed into an OR-gate, the output of which is connected to an integrated circuit IC output pin. The semiconductor integrated circuit as claimed in claim 5, characterized in that said test data (T 1 -T n ) is supplied to the output part (C 1 ) of a first stage, and the output parts (C 2 -C m ) of second and subsequent stages are respectively supplied as the test data an output of the output part (C 1 -C m-1 ) in a previous stage. The semiconductor integrated circuit as claimed in claim 5 or 6, characterized in that each output part (C 1 -C m ) includes a shift register part (SR) which receives the test data (T 1 -T n ) and a selector part (SEL) which receives the output data (I 1 -I n ) of the main block circuit part (B 1 -B m ) of the corresponding one of the blocks (A 1 -A m ) and the test data via the selector part. The semiconductor integrated circuit as claimed in claim 7, characterized in that said shift register part (SR) comprises a plurality of flip-flops (12 1 -12 n ) which are connected in series. The semiconductor integrated circuit as claimed in claim 5, characterized in that said test data (T 1 -T n ) is independently supplied to each of the output parts (C 1 -C m ) of the blocks (A 1 -A m ). The semiconductor integrated circuit as claimed in claim 5 or 9, characterized in that each output part (C 1 -C m ) includes a shift register part (SR) which receives the test data (T 1 -T n ) and a selector part (SEL) which receives the output data (I 1 -I n ) ot the main block circuit part (B 1 -B m ) of the corresponding one of the blocks (A 1 -A m ) and the test data via the selector part. The semiconductor integrated circuit as claimed in claim 10, characterized in that said shift register part (SR) comprises a plurality of flip-flops (12 1 -12 n ) which are connected in series. The semiconductor integrated circuit as claimed in claim 5, characterized in that a scan address (Add-1, Add-2) is supplied to the output part (C 1 -C m ) of each of the blocks (A 1 -A m ) to designate an output part which is to be tested. The semiconductor integrated circuit as claimed in claim 12, characterized in that each output part (C 1 -C m ) includes a scan latch part (SL) which receives the scan address (Add-1, Add-2) together with a scan clock signal (SCK), and a selector part (SEL) which receives the output data (I 1 -I n ) of the main block circuit part (B 1 -B m ) of the corresponding one of the blocks (A 1 -A m ) and an output of the scan latch part as the test data (T 1 -T n ). The semiconductor integrated circuit as claimed in claim 13, characterized in that said scan latch part (SL) comprises a plurality of latch circuits (72 1 -72 n ) for receiving corresponding bits of the scan address (Add-1, Add-2) and the scan clock signal (SCK). The semiconductor integrated circuit as claimed in any of claims 5 to 14, characterized in that there are further provided a test bus (62) including address lines, a clock line and a reset signal line operative in the test mode, said bus being only connected to the output part (C 1 -C m ) of each of the blocks (A 1 -A m ). The semiconductor integrated circuit as claimed in claim 5, characterized in that each of said output parts (C 1 -C m ) include a shift register (SR), said test data (T 1 -T n ) is supplied to the shift register of the output part (C 1 ) of a first stage, and the shift registers of the output parts (C 2 -C m ) of second and subsequent stages are respectively supplied as the test data an output of the shift register of the output part (C 1 -C m-1 ). The semiconductor integrated circuit as claimed in claim 5, characterized in that each of said output parts (C 1 -C m ) includes a shift register (SR), and said test data (T 1 -T n ) is independently supplied to the shift register of each of the output parts (C 1 (C m ) of the blocks (A 1 A m ). The semiconductor integrated circuit as claimed in claim 5, characterized in that a scan address (Add-1, Add-2) is supplied to the output part (C 1 -C m ) of each of the blocks (A 1 -A m ) to designate an output part which is to be tested.

Inventors: TANIZAWA TETSU, TOKUDA HIDEO, TANIZAWA, TETSU, TOKUDA, HIDEO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1990
Main classification: G06F11
IPC codes: G06F11, G01R31