Fabrication method for biMOS semiconductor device with improved speed and reliability

Abstract: To create bipolar and MOS transistors, a substrate is covered with polysilicon. The polysilicon is patterned to form gate electrodes in MOS transistor regions, and to form polysilicon patterns surrounding central openings in bipolar transistor base-and-emitter regions. Lightly-doped source and drain layers are created by implanting impurities into the MOS transistor regions, using the gate electrodes as masks. Active bases are formed in the base-and-emitter regions below the central openings. Then sidewalls are added to the polysilicon, narrowing the central openings and widening the gate electrodes. Impurities are implanted into the MOS transistor regions, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. The active base areas are doped below the narrowed central openings to create emitters.

Description: BACKGROUND OF THE INVENTION This invention relates to a method of fabricating high-speed bipolar transistors and highly reliable MOS field-effect transistors on the same semiconductor substrate. Semiconductor devices fabricated in this way are generally referred to as biMOS devices. When MOS transistors of both the p-channel type (PMOS transistors) and n-channel type (NMOS transistors) are formed, the device is referred to as a biCMOS device. By combining the high-speed performance of bipolar transistors with the low power dissipation and high integration density of CMOS technology, biCMOS devices offer significant advantages in semiconductor applications such as interface logic, static random-access memory, mixed analog/digital circuits, and gate arrays. The speed and integration level of a biMOS device can be increased by reducing the widths of the emitters of the bipolar transistors and lengths of the channels in the MOS transistors. The channel length of a MOS transistor is substantially equal to the length of its gate electrode. The attainable emitter width and gate length are determined by the smallest dimension that can be consistently resolved on the semiconductor fabrication line, which dimension is generally referred to as the design rule. Design rules in the neighborhood of one micrometer are typical at present. The speed of a bipolar transistor is commonly measured by its cut-off frequency f T . To maximize f T it is desirable to make the emitter width equal to the design rule, or even smaller. To maximize the integration level of MOS transistors, it is similarly desirable to make the gate length equal to the design rule, but in the prior art this has proven difficult to do without adverse effects on reliability. The problem is that as the gate length is reduced, the strength of the electric field ε in the channel tends to increase. For the standard 5-V power supply voltage, when the channel is shorter than about 1.5 µ m, the electric field becomes strong enough to inject so-called hot carriers into the substrate below and the gate oxide above the channel. Carriers injected into the substrate create an unwanted substrate current. Carriers injected into the gate oxide may become trapped and degrade the characteristics of the transistor. More specifically, carriers trapped in the gate oxide generate a surface potential that degrades such characteristics as the threshold voltage V T and transconductance g m , and causes increased leakage in the subthreshold region. Another problem faced by manufacturers of biMOS semiconductor devices is the inherent complexity of the fabrication process, which raises the cost of the devices. To reduce the complexity, it is desirable to combine bipolar transistor fabrication steps with MOS transistor fabrication steps as far as possible. SUMMARY OF THE INVENTION It is accordingly an object of the present invention to fabricate bipolar transistors with a high f T value. Another object of the invention is to fabricate highly reliable MOS transistors with a short gate length. A further object of the invention is to combine fabrication steps for improving the speed of bipolar transistors with fabrication steps for improving the reliability of MOS transistors. These objects are solved by the method of claim 1. The invented fabrication method begins with the creation of suitably doped bipolar transistor regions and MOS transistor regions in a semiconductor substrate. The bipolar transistor regions are further subdivided into base-and-emitter regions and collector regions. Polysilicon gate electrodes are formed in the MOS transistor regions. Each base-and-emitter region is covered with polysilicon except for a central opening. The MOS transistor regions are lightly doped, using the gate electrodes as masks, to create lightly-doped source and drain layers. The base-and-emitter regions are doped to form an active base under each central opening, and an extrinsic base under the portion covered by polysilicon. Then sidewalls are formed on the polysilicon, thereby narrowing the central openings in the base-and-emitter regions and widening the gate electrodes in the MOS transistor regions. The MOS transistor regions are heavily doped, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. Active base areas disposed below the narrowed central openings in the base-and-emitter regions are doped to create emitters. EP-A-0 250 721 discloses a method of fabricating biMOS circuits comprising a semiconductor substrate divided into bipolar transistor regions and MOS transistor regions. The bipolar transistor regions comprise base and emitter regions arranged in a plane of the circuit and consisting of silicide and polysilicon. The base- and emitter-polysilicon is patterned by a local oxidation. The above method aims to shorten the emitter lengths. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1R are sectional views illustrating steps in a first novel biMOS fabrication process. Figs. 2A to 2W are sectional views illustrating steps in a second novel biMOS fabrication process. Fig. 3 is an oblique view illustrating the structure of a MOS transistor fabricated by prior-art methods. Fig. 4 is a graph illustrating simulated electric field intensity in the transistor in Fig. 3. Fig. 5 is a graph illustrating simulated electric field intensity in an NMOS transistor fabricated by the novel method. DETAILED DESCRIPTION OF THE INVENTION Two novel fabrication methods embodying the present invention will be described below with reference to the drawings. Both methods fabricate biCMOS devices. The drawings illustrate the fabrication of a representative part of a biCMOS device, comprising one bipolar transistor, one NMOS transistor, and one PMOS transistor. It should be understood that these form only one portion of a semiconductor wafer on which a large number of bipolar, NMOS, and PMOS transistors are fabricated simultaneously. These two methods are shown to illustrate the invention, not to restrict its scope, which is set forth in the appended claims. It will be obvious that these methods are capable of modification without departing from the spirit of the invention. For example, biMOS devices having only bipolar and PMOS (or NMOS) transistors can be fabricated, omitting those steps which serve solely for the of NMOS (or PMOS) transistors. Where specific dimensions are mentioned, a design rule of 1 µ m will be assumed. The invention is not restricted to this design rule, however; it is applicable to other design rules as well. With reference to Fig. 1A, the first novel fabrication method starts from a p-type (100) monocrystalline silicon wafer substrate 41 having a specific resistance in the range of 10 to 20 Ω ·cm. An n-type buried layer 42 with a sheet resistance of substantially 40 Ω /square and junction depth of substantially 2.0 µ m is created by implanting antimony ions at a dose of 1.5 x 10¹⁵ cm⁻² and accelerating voltage of 40 keV, then heating the wafer to 1150°C to drive the antimony in. A p-type buried layer 43 is then formed by selectively implanting boron ions with a dose of 5 x 10¹² cm⁻² and accelerating voltage of 120 keV and driving the boron in. After formation of the buried layers 42 and 43, an n-type epitaxial layer 44 with a specific resistance of substantially 1.5 Ω ·cm and thickness of substantially 1.4 µ m is deposited on the substrate 41. Phosphorus ions are selectively implanted into the epitaxial layer 44 above the n-type buried layer 42 at a dose of 2 x 10¹² cm⁻² and accelerating voltage of 170 keV and driven in at 1000°C for 20 minutes to simultaneously create bipolar transistor regions 45 and PMOS transistor regions 46. These regions 45 and 46 are n⁻ regions having a surface concentration of 5 x 10¹⁶ cm⁻² and diffusion depth of 1.5 µ m. Next boron ions are implanted into the epitaxial layer 44 above the p-type buried layer 43 at a dose of 4.5 x 10¹² cm⁻² and accelerating voltage of 100 keV and driven in at 1000°C for 20 minutes to simultaneously create p-type isolation regions 47 for the bipolar transistors, and NMOS transistor regions 48. The regions 47 and 48 are p-type regions having a surface concentration of 5 x 10¹⁶ cm⁻² and diffusion depth of 1.5µm. The transistor regions 45, 46, and 48 are now isolated from each other and from peripheral regions by selectively forming field oxides 49 on the surface of the epitaxial layer 44, using the well-known localized oxidation of silicon (LOCOS) method. Field oxides 49 are moreover formed within the bipolar transistor regions 45, dividing each into a base-and-emitter region 50 and a collector region 51. An oxide layer 52 with a thickness of 15 nm (150 angstroms) is now grown on the surface of the transistor regions 46, 48, 50, and 51 by thermal oxidation in a dry O₂ atmosphere at 900°C for 30 minutes. Then a thin nitride (Si₃N₄) layer 53, having a thickness of substantially 10 nm (100 angstroms), is formed on the entire surface by the well-known low-pressure chemical vapor deposition (LPCVD) method. Next, with reference to Fig. 1B, the nitride layer 53 and the oxide layer 52 are removed from the bipolar transistor base-and-emitter regions 50 by well-known photolithographic etching techniques. Then a non-doped polysilicon layer 54 is grown to a thickness of 300 nm (3000 angstroms) overall by the LPCVD method. Next, with reference to Fig. 1C, the surface of the polysilicon layer 54 is oxidized at 900°C in a dry oxygen atmosphere for 30 minutes to create an oxide layer 55 with a thickness of 20 nm (200 angstroms). A thick nitride layer, having a thickness of substantially 150 nm (1500 angstroms), is grown on the oxide layer 55 by the LPCVD method and patterned as follows. The nitride layer is removed to create central openings 56 centered over the bipolar transistor base-and-emitter regions 50, the remaining parts of which are left covered by nitride layers 57. The nitride layer is entirely removed from the bipolar transistor collector regions 51. In the MOS transistor regions 48 and 46, nitride layers 58 and 59 are left over centrally located gate regions. The nitride is removed from all other regions. The central openings 56 and the nitride layers 58 and 59 should preferably have the design-rule dimension. Next, with reference to Fig. 1D, the wafer is oxidized in a wet O₂ atmosphere under high pressure (substantially seven times standard atmospheric pressure) at a temperature of substantially 1030°C. Where not masked by the nitride layers 57, 58, and 59, the polysilicon layer 54 is thus converted to an oxide 60 substantially 800 nm (8000 angstroms) thick. In the bipolar transistor base-and-emitter regions 50, oxide 60 is created in the central area where the emitter will be formed, a polysilicon pattern 54a being left therearound. In the MOS transistor regions 48 and 46, polysilicon gate electrodes 54b are left, all the rest of the polysilicon being converted to oxide 60. The edges of the oxide 60 are tapered and extend under the edges of the nitride (the so-called bird's-beak effect), as can be seen in the drawing. Next, with reference to Fig. 1E, boron ions are implanted through the polysilicon patterns 54a into each of the base-and-emitter regions 50 at a dose of 2 x 10¹⁵ cm⁻² and accelerating voltage of 100:keV, forming an extrinsic base 61. This boron implant is restricted to the base-and-emitter regions 50 by means of a patterned resist, not shown in the drawing, which is removed after the implant. Next, with reference to Fig. 1F, the oxide 60 is entirely removed by wet etching, creating central openings 62 defined by the polysilicon patterns 54a in the base-and-emitter regions 50, and exposing the thin nitride layer 53, except where it is covered by the gate electrodes 54b and the edges of the polysilicon patterns 54a. Next, with reference to Fig. 1G, the exposed thin nitride layer 53 is removed with hot phosphoric acid, leaving a nitride covering only on the polysilicon patterns 54a and the polysilicon gate electrodes 54b. The nitride covering somewhat overhangs the edges of the polysilicon patterns 54a and the gate electrodes 54b. These edges are now oxidized by a wet oxidation process, performed at 800°C for 15 minutes. An oxide layer 63 with a thickness of substantially 18 nm (180 angstroms) is thus formed on the lateral walls of the polysilicon gate electrodes 54b, on the outside edge surfaces of the polysilicon patterns 54a, and on the inner surfaces of the central openings 62, including both their lower surface, which is the monocrystalline silicon surface of the region 50, and their lateral walls, which are lateral surfaces of the polysilicon patterns 54a. Next, with reference to Fig. 1H, boron ions are implanted at a dose of 1.5 x 10¹³ cm⁻² and accelerating voltage of 40 keV into the bipolar transistor base-and-emitter regions 50 and the PMOS transistor regions 46. In the bipolar transistor base-and-emitter regions 50, the boron passes only through the central openings 62, creating an active base 64 below each. In the PMOS transistor regions 46, the boron ions are masked by the gate electrodes 54b and create p⁻ lightly-doped source and drain layers 65 on either side of the gate electrodes 54b. Next, with reference to Fig. 1I, phosphorus ions are selectively implanted at a dose of 1.5 x 10¹³ cm⁻² and accelerating voltage of 33 keV into the NMOS transistor regions 48 to n⁻ lightly-doped source and drain layers 66, the gate electrodes 54b acting as masks. Next, with reference to Fig. 1J, a CVD SiO₂ layer 67 100 nm, (1000 angstroms) thick is grown on the entire surface by the LPCVD method. Next, with reference to Fig. 1K, a polysilicon layer 68 200 nm (2000 angstroms) thick is grown on the entire surface by the same LPCVD method. Next, with reference to Fig. 1L, the polysilicon layer 68 and the CVD SiO₂ layer 67 are etched by a continuous, anisotropic, reactive ion etching (RIE) process. All parts of the polysilicon layer 68 and the CVD SiO₂ layer 67 are thus removed except for sidewalls 69 left on the lateral surfaces: in particular, on the lateral walls of the central openings 62 and the lateral walls of the gate electrodes 54b. The widths W₃ and W₇ of the sidewalls is substantially 0.2 µm, although this value can be varied according to the gas flow, pressure, and other etching parameters. The original width W₄ of the central openings 62 was the design-rule dimension of 1 µm, so the width W₅ of the openings left after addition of the 0.2-µm sidewalls 69 is: W₅ = W₄ - 2 x W₃ = 0.6 µm In this way it is possible to obtain an emitter width smaller than the design rule of 1.0 µm. The original width W₆ of the gate electrodes 54b of the NMOS and PMOS transistors was the design-rule dimension of 1.0 µm. Addition of the 0.2 µm sidewalls 69 establishes an offset zone with a width W₇ of 0.2 µm around the gate electrodes 54b. The reactive ion etch also removes the oxide layer 63 on the lower surface of the central openings 62, except where it underlies the sidewalls 69, thus exposing the surface of the active base 64. The oxide layer 52 is also etched, except in the MOS transistor gate areas, exposing the surfaces of the bipolar transistor collector regions 51 and the source and drain surfaces in the MOS transistor regions 48 and 46. Next, with reference to Fig. 1M, a polysilicon layer 70 is grown over the entire surface to a thickness of 300 nm (3000 angstroms) by LPCVD, and an oxide layer 71 with a thickness of substantially 16 nm (160 angstroms) is formed on the surface of the polysilicon layer 70 by wet oxidation at 800°C for 15 minutes. Next, with reference to Fig. 1N, a resist 72 is applied and patterned to create a mask over the PMOS transistor regions 46. Arsenic ions are then implanted at a dose of 1 x 10¹⁶ cm⁻² and accelerating voltage of 40 keV into the polysilicon layer 70 overlying the bipolar transistor regions 45 and the NMOS transistor regions 48. Next the resist 72 is removed, a new resist mask (not shown in the drawing) is created over the bipolar transistor regions 45 and the NMOS transistor regions 48, and boron ions are implanted at a dose of 2.5 x 10¹⁵ cm⁻² and accelerating voltage of 100 keV into the polysilicon layer 70 over the PMOS transistor regions 46. Next, with reference to Fig. 1O, the oxide layer 71 and polysilicon layer 70 are patterned by photolithographic etching techniques. The remaining part of the polysilicon layer 70 becomes emitter electrodes 73 filling the central openings 62, collector electrodes 74 in the collector regions 51, source and drain electrodes 75 in the NMOS transistor regions 48, and source and drain electrodes 76 in the PMOS transistor regions 46. Next, with reference to Fig. 1P, wet oxidation is performed at 800°C for 15 minutes to create an oxide layer 77 on the sides of the electrodes 73, 74, 75, and 76. Next, with reference to Fig. 1Q, the nitride layers 57, 58, and 59 exposed on the polysilicon patterns 54a and the gate electrodes 54b are removed by wet etching with phosphoric acid. Next, with reference to Fig. 1R, a layer of borophosphosilicate glass (BPSG) 78 is grown over the entire surface to a thickness of 700 nm (7000 angstroms) by the CVD method, using 20 wt. % P₂O₅ and 8 wt. % B₂O₃, and the wafer is annealed at 920°C for 30 minutes in a nitrogen atmosphere. Besides planarizing the surface of the BPSG 78, this annealing step causes arsenic to diffuse from the emitter electrodes 73, the collector electrodes 74, and the source and drain electrodes 75 to form emitters 79 in the active bases 64, collectors 80 in the collector regions 51, and n⁺ heavily-doped source and drain layers 81 in the NMOS transistor regions 48. Similarly, boron diffuses from the source and drain electrodes 76 to form p⁺ heavily-doped source and drain layers 82 in the PMOS transistor regions 46. Because the heavily-doped source and drain layers 81 and 82 are offset from the gate electrodes, the source and drain areas near the gate electrodes 54b comprise the lightly-doped layers 65 and 66. This combination of heavily-doped and lightly-doped source and drain layers is known as the lightly-doped drain (LDD) structure. Both the source and drain of each MOS transistor have an LDD structure. Finally, the wafer is metalized to interconnect the electrodes and form the desired circuits. The metalization process, which is well known and accordingly not illustrated in the drawings, comprises steps of opening contact holes over the electrodes, then depositing and patterning one or more layers of a metal such as aluminum. Next, a second novel fabrication method will be described with reference to Figs. 2A to 2W. The second novel fabrication method differs from the first in that a layer of tungsten silicide is formed on the gate electrodes of the MOS transistors to reduce their resistance. Another difference is that polysilicon electrodes are formed only in the gate and emitter regions. The sources and drains of the MOS transistors arid the collectors of the bipolar transistors are accordingly created by direct ion implantation rather than by diffusion of implanted ions from overlying polysilicon. With reference to Fig. 2A, the second novel fabrication method starts from a p-type (100) monocrystalline silicon wafer substrate 91 having a specific resistance in the range of 10 to 20 Ω ·cm. An n⁺ buried layer 92 with a sheet resistance of 40 Ω /square and diffusion depth of 2.5 µm is created by implanting antimony ions at a dose of 1.5 x 10¹⁵ cm⁻² and accelerating voltage of 40 keV and driving them in at 1150°C for substantially 480 minutes. Then a p-type buried layer 93 with a sheet resistance of 4k Ω /square and diffusion depth of 1 µ m is formed by selectively implanting boron ions at a dose of 5 x 10¹² cm⁻² and accelerating voltage of 120 keV into the same substrate 91 and driving them in at 1000°C for substantially 60 minutes. Next, an n-type epitaxial layer 94 with a specific resistance of 4 Ω ·cm and thickness of 1.4 µ m is formed on the substrate 91 by the CVD method. Next bipolar transistor regions 95, PMOS transistor regions 96, bipolar transistor isolation regions 97, and NMOS transistor regions 98 are created by implantation of phosphorus ions and boron ions, using the same process as described in Fig. 1A. The n-layers in the regions 95 and 96 have a sheet resistance of 6k Ω/square, while p-layers in the regions 97 and 98 a sheet resistance of 150 Ω /square. All regions 95, 96, 97, and 98 have a diffusion depth of substantially 1.5 µm. Next field oxides 99 are created by the LOCOS method to isolate the transistor regions 95, 96, and 98 from each other and from peripheral areas, and to divide the bipolar transistor regions 95 into base-and-emitter regions 100 and collector regions 101. Then an oxide layer 102 with a thickness of 20 nm (200 angstroms) is formed on the surface of the transistor regions (the regions 96, 98, 100, and 101) by oxidation at 950°C for substantially 30 minutes. Next, with reference to Fig. 2B, the oxide layer 102 is removed from the bipolar transistor base-and-emitter regions 100 and the collector regions 101 by photolithographic etching techniques, leaving the oxide layer 102 present only on the surface of the MOS transistor regions 96 and 98. Then a non-doped polysilicon layer 103 is grown to a thickness of 300 nm (3000 angstroms) on the entire surface by the LPCVD method. Next, with reference to Fig. 2C, the surface of the polysilicon layer 103 is oxidized to create an oxide layer 104, over which a nitride layer 150 nm (1500 angstroms) thick is grown. The nitride is patterned to create central openings 105 surrounded by nitride layers 106 in the bipolar transistor base-and-emitter regions 100, and leave nitride layers 107 in the MOS transistor regions 96 and 98. This step is similar to the step in Fig. 1D in the first novel fabrication method except that the nitride layers 107 entirely cover the MOS transistor regions 96 and 98. Next, with reference to Fig. 2D, the polysilicon layer 103 is oxidized under high pressure (substantially seven atmospheres) at a temperature of 1030°C for substantially 30 minutes, using the nitride layers 106 and 107 as a mask. This produces an oxide layer 108 substantially 800 nm (8000 angstroms) thick in central parts of the bipolar transistor base-and-emitter regions and in the collector regions and peripheral regions, but not in the MOS transistor regions 96 and 98. Next, with reference to Fig. 2E, an oxide layer 109 with a thickness of 50 nm (500 angstroms) is formed on the entire surface by the LPCVD method. Next, with reference to Fig. 2F, the oxide layer 109, nitride layer 106, and oxide layer 104 are left intact in the bipolar transistor base-and-emitter regions 100, while the oxide layer 109, nitride layer 107, and oxide layer 104 are removed from all other regions by photolithographic etching techniques. Then arsenic ions are implanted at a dose of 1 x 10¹⁶ cm⁻² and accelerating voltage of 40 keV into the polysilicon layers 103 over the MOS transistor regions 96 and 98. No arsenic is introduced into the polysilicon patterns 103a in the bipolar transistor base-and-emitter regions 100 at this time, due to the presence of the oxide layers 109 and 104. Next, with reference to Fig. 2G, a tungsten silicide layer 110 with a thickness of 150 nm (1500 angstroms) is created on the entire surface. Next, with reference to Fig. 2H, the tungsten silicide layer 110 and the polysilicon 103 left on the MOS transistor regions 98 and 96 are continuously patterned by photolithographic etching techniques to create gate electrodes 111 comprising the remaining parts of these two layers on the NMOS transistor regions 98 and the PMOS transistor regions 96. Next, with reference to Fig. 2I, the MOS transistor regions 96 and 98 are masked by a resist 112 and the oxide layer 109 is etched away from over the bipolar transistor base-and-emitter regions 100. Then boron ions are implanted into the polysilicon patterns 103a over the bipolar transistor base-and-emitter regions 100 at a dose of 2 x 10¹⁵ cm⁻² and accelerating voltage of 100 keV. Next, with reference to Fig. 2J, the exposed oxide is etched to a depth of 90 nm (9000 angstroms) by wet etching, using the resist 112 as a mask. This etch entirely removes the oxide layer 108 that was created earlier from portions of the polysilicon layer 103, leaving central openings 113 surrounded by the polysilicon patterns 103a, and exposing the surface of the bipolar transistor collector regions 101. The resist 112 is now removed. Next, with reference to Fig. 2K, oxidation is performed at 800°C for substantially 20 minutes to form an oxide layer 114 with a thickness of 18 nm (180 angstroms) on the inner surface of the openings 113, the outside surfaces of the polysilicon patterns 103a, the surfaces of the collector regions 101, and the upper and lateral surfaces of the gate electrodes 111. Then boron ions are implanted at a dose of 1.5 x 10¹³ cm⁻² and accelerating voltage of 10 keV through the central openings 113 into the base-and-emitter regions 100, other regions being masked at this time by a resist not shown in the drawing. The wafer is now annealed at 800°C for substantially 30 minutes to activate the boron just implanted and create an active base 115 having a sheet resistance of 1.5k Ω/square and diffusion depth of 0.15 µm in the base-and-emitter region 100 of each bipolar transistor. The annealing also causes the boron implanted in Fig. 2I to diffuse from the polysilicon patterns 103a into the the base-and-emitter regions 100, forming an extrinsic base 116 with a sheet resistance of 200 Ω/square and diffusion depth of 0.2 µm. Next, with reference to Fig. 2L, boron ions are selectively implanted at a dose of 1.0 x 10¹³ cm⁻² and accelerating voltage of 30 keV into the PMOS transistor regions 96 with the gate electrodes 111 as masks, forming p⁻ lightly-doped source and drain layers 117 similar to the p⁻ lightly-doped source and drain layers 65 in Fig. 1H. Next, with reference to Fig. 2M, phosphorus ions are selectively implanted at a dose of 1.5 x 10¹³ cm⁻² and accelerating voltage of 30 keV into the NMOS transistor regions 98 with the gate electrodes 111 as masks, forming n⁻ lightly-doped source and drain layers 118 similar to the n⁻ lightly-doped source and drain layers 66 in Fig. 1I. Next, with reference to Fig. 2N, an oxide layer 119 with a thickness of 100 nm (1000 angstroms) is formed on the entire surface of the substrate by the LPCVD method. Then a polysilicon layer 120 with a thickness of 200 nm (2000 angstroms) is formed on the entire surface. Next, with reference to Fig. 2O, an anisotropic reactive ion etch is performed to remove all of the polysilicon layer 120 and the oxide layer 119 except for sidewalls 121, which are formed in particular on the lateral walls of the central openings 113 and the gate electrodes 111. As in Fig. 1L, the sidewalls 121 narrow the central openings 113 to less than the design rule, and establish a 0.2 µm offset zone on both sides of the gate electrodes 111 of the NMOS and PMOS transistors. This reactive ion etch also etches the oxide layers 114, exposing the surface of the active base regions 115 at the bottom of the central openings 113, the surfaces of the collector regions 101, the upper surfaces of the gate electrodes 111, and the surfaces of the source and drain regions of the MOS transistor regions 96 and 98. Next, with reference to Fig. 2P, an oxide layer 122 with a thickness of 20 nm (200 angstroms) is formed on these exposed surfaces and the lateral surfaces of the sidewalls 121 by oxidation at 900°C for substantially 30 minutes. The oxide layer is then selectively removed from the base-and-emitter regions 100 by photolithographic etching. Next, with reference to Fig. 2Q, arsenic ions are selectively implanted at a dose of 5 x 10¹⁵ cm⁻² and accelerating voltage of 40 keV into the NMOS transistor regions 98 and the bipolar transistor collector regions 100, using a patterned resist not shown in the drawing, the gate electrodes 111 and sidewalls 121 also serving as a mask. This creates n⁺ layers that form the collector regions 123 of the bipolar transistors, and the n⁺ heavily-doped source and drain layers 124 of the NMOS transistors, completing the LDD structure of the NMOS transistors. Next, with reference to Fig. 2R, a polysilicon layer 125 with a thickness of 300 nm (3000 angstroms) is formed overall by the LPCVD method, and its surface is oxidized at 800°C for substantially 20 minutes to form an oxide layer 126 with a thickness of 16 nm (160 angstroms). Then arsenic ions are implanted at a dose of 1.0 x 10¹⁶ cm⁻² and an accelerating voltage of 40 keV through the oxide layer 126 into the polysilicon layer 125. Next, with reference to Fig. 2S, the oxide layer 126 and polysilicon layer 125 are patterned by photolithographic etching techniques to form emitter electrodes 125a comprising the remaining polysilicon layer 125 in the openings 113. Next, with reference to Fig. 2T, boron ions are selectively implanted at a dose of 2 x 10¹⁵ cm⁻² and accelerating voltage of 40 keV into the PMOS transistor regions 96, using the gate electrodes 111 and sidewalls 121 as a mask, to form p⁺ heavily-doped source and drain layers 127. This completes the LDD structure of the PMOS transistors. Next, with reference to Fig. 2U, oxidation is performed at 800°C for substantially 20 minutes to form an oxide layer 128 with a thickness of 90 nm (900 angstroms) on the entire surface of the wafer, except where it is covered by the nitride layer 106. Next, with reference to Fig. 2V, the exposed portions of the nitride layers 106 are removed by etching with phosphoric acid, using the oxide layer 128 as a mask. Next, with reference to Fig. 2W, a 700 nm (7000-angstrom) layer of BPSG 129 is formed over the entire surface by the CVD method, using 20 wt. % P₂O₅ and 8 wt. % B₂O₃, and the wafer is annealed at 920°C for substantially 30 minutes. This annealing process planarizes the BPSG layer 129 and causes arsenic to diffuse from the emitter electrodes 125a into the active bases 115, forming emitters 130 therein with a sheet resistance of 20 Ω/square and diffusion depth of 0.1 µm. Finally, contact holes are opened over the gate and emitter electrodes and over the source, drain, and collector regions, and a metalization process is carried out to interconnect the transistors into the desired circuits. These final steps are not illustrated in the drawings. Both novel fabrication methods described above fabricate bipolar transistors having an emitter width less than the design rule, resulting in a high cut-off frequency f T , and MOS transistors with an LDD structure, resulting in high reliability. Experiments carried out by the inventors have demonstrated f T = 12 GHz in bipolar transistors with an emitter area of 0.6 x 3 µm², and lifetimes of τ = 1 x 10⁵ seconds for NMOS transistors with gate lengths of 1.4 µm and gate widths of 20 µm. The quantity τ is the expected time for a 10% variation in g m at V DS = 8 V, V GS = 4 V. The improved MOS transistor lifetime τ can be explained as follows. Fig. 3 shows the structure of a MOS transistor fabricated by prior-art methods, in which heavily-doped source and drain layers 131 extend all the way to the gate oxide 132 and even slightly thereunder. The effective length L eff of the channel 133 is thus less than the gate length L. When the transistor operates in the triode region, the electric field in the depletion layer at the bottom of the channel 133 is given by the formula: ε = V DS /L eff where V DS is the voltage between source and drain. A short gate length, resulting in a small L eff , tends to increase the electric field and produce hot carriers. When the transistor operates in the saturation region, the electric field becomes highly concentrated in the depletion layer near the drain, as shown in fig. 4, reaching a maximum value much higher than the value given by the preceding formula, thus causing even more production of hot carriers. When the transistor has an LDD structure as in the present invention, however, the electric field does not peak near the drain as in Fig. 4. Fig. 5 shows the result of a simulation of the electrical field strength in the vicinity of the drain of an NMOS transistor fabricated by the novel method. The electric field rises only slightly in the n⁻ lightly-doped layer, not reaching the excessive values shown in Fig. 4. Accordingly, the novel method has significantly less tendency than the prior art to produce hot carriers. Another advantage of the novel method is that the same fabrication step forms both the sidewalls that narrow the emitters of the bipolar transistors and the sidewalls that create offset zones around the gate electrodes of the MOS transistors. That is, the same step improves the speed performance of the bipolar transistors and the reliability of the MOS transistors. Another feature of the novel method is that since the oxidation step illustrated in Figs. 1D and 2D is performed under high pressure, it can be performed at a comparatively low temperature. Oxide can thus be formed without altering the diffusion profiles of the underlying layers. A further advantage of high-pressure oxidation is that the resulting oxide/polysilicon interface has a sharper taper than when oxidation is performed at standard atmospheric pressure. This results in a larger cross-sectional area for the gate electrodes, when the gate electrodes are defined by this oxidation step as in Fig. 1D. The order of the two steps shown in Figs. 1H and 1I can obviously be reversed. The order of the steps in Figs. 2Q to 2V can also be altered in various ways. The invention can also be summarized by the following features: To create bipolar and MOS transistors, a substrate is covered with polysilicon. The polysilicon is patterned to form gate electrodes in MOS transistor regions, and to form polysilicon patterns surrounding central openings in bipolar transistor base-and-emitter regions. Lightly-doped source and drain layers are created by implanting impurities into the MOS transistor regions, using the gate electrodes as masks. Active bases are formed in the base-and-emitter regions below the central openings. Then sidewalls are added to the polysilicon, narrowing the central openings and widening the gate electrodes. Impurities are implanted into the MOS transistor regions, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. The active base areas are doped below the narrowed central openings to create emitters.

Claims: A biMOS fabrication method, comprising steps of: (a) dividing a semiconductor substrate (41 or 91) into mutually isolated bipolar transistor regions (45 or 95) and MOS transistor regions (46 and 48, or 96 and 98), and subdividing said bipolar transistor regions into mutually isolated base-and-emitter regions (50 or 100) and collector regions (51 or 101); (b) forming gate electrodes (54b or 111) in said MOS transistor regions (46 and 48, or 96 and 98), and forming polysilicon patterns (54a or 103a) having central openings (62 or 113) in said base-and-emitter regions (50 or 100); (c) doping said emitter-and-base regions (50 or 100) to create extrinsic bases (61 or 116) below said polysilicon patterns (54a or 103a) and active bases (64 or 115) below said central openings (62 or 113), and doping said MOS transistor regions (46 and 48, or 96 and 98), using said gate electrodes (54b or 111) as masks, thereby creating lightly-doped source and drain layers (65 and 66, or 117 and 118); (d) covering all regions with a first oxide layer (67 or 119) and a first polysilicon layer (68 or 120) and anisotropically etching said first oxide layer (67 or 119) and said first polysilicon layer (68 or 120), thereby forming sidewalls (69 or 121) comprising remaining parts of said first oxide layer (67 or 119) and said first polysilicon layer (68 or 120) on lateral walls of said central openings (62 or 113) and lateral walls of said gate electrodes (54b or 111); and (e) doping said base-and-emitter regions (50 or 100) with said polysilicon patterns (54a or 103a) and said sidewalls (69 or 121) as masks, thereby creating emitters (79 or 130) within said active bases (64 or 115), and doping said MOS transistor regions (46 and 48, or 96 and 98) with said gate electrodes (54b or 111) and said sidewalls (69 or 121) as masks, thereby forming heavily-doped source and drain layers (81 and 82, or 124 and 127). The method of claim 1, wherein said first oxide layer (67 or 119) and first polysilicon layer (68 or 120) are formed by low-pressure chemical vapor deposition. The method of claim 1, wherein said MOS transistor regions (46 and 48, or 96 and 98) comprise PMOS transistor regions (46 or 96) and NMOS transistor regions (48 or 98), and said step (a) comprises: doping said bipolar transistor regions (45 or 95) and said PMOS transistor regions (46 or 96) with n-type impurities; and doping said NMOS transistor regions (48 or 98) with p-type impurities. The method of claim 1, wherein said step (b) comprises: covering said MOS transistor regions (46 and 48, or 96 and 98) with a second oxide layer (52 or 102); covering all regions with a second polysilicon layer (54 or 103); covering said second polysilicon layer (54 or 103) with a nitride layer (57 and 58, or 106 and 107) in at least central parts of said MOS transistor regions (46 and 48, or 96 and 98) and non-central parts of said base-and-emitter regions (50 or 100); oxidizing all portions of said second polysilicon layer (54 or 103) where not covered by said nitride layer (57 and 58, or 106 and 107); and removing all oxidized portions of said second polysilicon layer (54 or 103). The method of claim 4, wherein said oxidizing of said second polysilicon layer (54 or 103) where not covered by said nitride layer is performed at a pressure of substantially seven atmospheres. The method of claim 4, wherein said nitride layer (57 and 58) is formed only in said central parts of said MOS transistor regions (46 and 48) and said non-central parts of said base-and-emitter regions (50), so that said oxidizing of said second polysilicon layer (54) where not covered by said nitride layer (57 and 58) and removing of said oxidized portions results in the forming of said gate electrodes (54b). The method of claim 6, wherein step (c) of claim 1 comprises: implanting ions through said polysilicon patterns (54a) before removing of said oxided portions of said second polysilicon layer (54), to form said extrinsic bases (61); implanting ions through said central openings (62) after said removing of saidoxidized portions of said second polysilicon layer (54), to form said active bases (64); and implanting ions into said MOS transistor regions (46 and 48) after said removing of said oxidized portions of said second polysilicon layer (54), to form said lightly-doped source and drain layers (65 and 66). The method of claim 4, wherein said nitride layer (106 and 107) covers said second polysilicon layer (103) everywhere except in central parts of said base-and-emitter regions (100), and step (b) of claim 1 further comprises: removing said nitride layer (107) from said MOS transistor regions (96 and 98) after said oxidizing of said second polysilicon layer (103); forming a refractory-metal-silicide layer (110) on said second polysilicon layer (103) in said MOS transistor regions (96 and 98); and patterning said second polysilicon layer (103) and said refractory-metal-silicide layer (110) in said MOS transistor regions (96 and 98) to form said gate electrodes (111) in said central parts of said MOS transistor regions (96 and 98). The method of claim 8, wherein said refractory-metal-silicide layer (110) is a tungsten-silicide layer. The method of claim 8, wherein step (c) of claim 1 comprises: implanting ions into said polysilicon patterns (103a) implanting ions through said central openings (113) after said removing of said oxidized portions of said second polysilicon layer (103), to form said active bases (115); annealing said substrate (91), thereby causing the ions implanted into said polysilicon patterns (103a) to diffuse into said substrate (91) and form said extrinsic bases (116); and implanting ions into said MOS transistor regions (46 and 48) after said annealing, to form said lightly-doped source and drain layers (117 and 118). The method of claim 1, wherein said step (e) comprises: covering all regions with a third polysilicon layer (70); implanting ions into said third polysilicon layer (70); patterning said third polysilicon layer (70) to create emitter electrodes (73) in said central openings (62) within said sidewalls (69), and source and drain electrodes (75 and 76) adjacent to said sidewalls (69) on respective sides of said gate electrodes (54b) in said MOS transistor regions (46 and 48); and annealing said substrate (41), thereby diffusing said ions from said emitter electrodes (73) into said active bases (64) to create said emitters (79), and from said source and drain electrodes (75 and 76) into said MOS transistor regions (46 and 48) to create said heavily-doped source and drain layers (81 and 82). The method of claim 11, wherein the ions implanted into said third polysilicon layer (70) comprise arsenic and boron ions. The method of claim 1, wherein said step (e) comprises: forming emitter electrodes (125a) comprising polysilicon doped with impurities in said central openings (113) within said sidewalls (121); implanting ions into said MOS transistor regions (96 and 98) to form said heavily-doped source and drain layers (124 and 127): and annealing said substrate (91), thereby diffusing said impurities from said emitter electrodes (125a) into said active bases (115), to form said emitters (130). The method of claim 13, wherein said emitter electrodes are formed by: depositing a third polysilicon layer (125) over all regions; implanting arsenic ions into said third polysilicon layer (125); and patterning said third polysilicon layer (125) to form emitter electrodes (125a) filling said central openings (113) within said sidewalls (121).

Inventors: SHIMODA KOUICHI OKI ELECTRIC I, TSUBONE KO OKI ELECTRIC INDUST, UMEMURA YOSHIO OKI ELECTRIC IN, SHIMODA, KOUICHI, OKI ELECTRIC INDUSTRY CO., LTD., TSUBONE, KO, OKI ELECTRIC INDUSTRY CO., LTD., UMEMURA, YOSHIO, OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1990
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27