Context switching system

Abstract: A data processing device (11) includes an electronic processor (15) responsive to a context signal (INT) and operable in alternative processing contexts identified by the context signal (INT). First and second registers (851,855) are connected to the electronic processor (15) to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit (231,853,857) is connected to the first and second registers (851,855) and operates to selectively control input and output operations of the registers to and from the electronic processor (15) depending on the processing context. Other devices, systems and methods are also disclosed involving a parallel logic unit and an arrangement for series minimum/maximum function computing.

Description: (C) Copyright 1989 Texas Instruments Incorporated. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. This invention relates to data processing devices, electronic processing and control systems and methods of their manufacture and operation. BACKGROUND OF THE INVENTION A microprocessor device is a central processing unit or CPU for a digital processor which is usually contained in a single semiconductor integrated circuit or "chip" fabricated by MOS/LSI technology, as shown in U. S. Patent US-A-3 757 306, issued to Gary W. Boone and assigned to Texas Instruments Incorporated. The Boone patent shows a single-chip 8-bit CPU including a parallel ALU, registers for data and addresses, an instruction register and a control decoder, all interconnected using the von Neumann architecture and employing a bidirectional parallel bus for data, address and instructions. U. S. Patent US-A-4 074 351, issued to Gary W. Boone and Michael J. Cochran, assigned to Texas Instruments Incorporated, shows a single-chip "microcomputer" type device which contains a 4-bit parallel ALU and its control circuitry, with on-chip ROM for program storage and on-chip RAM for data storage, constructed in the Harvard architecture. The term microprocessor usually refers to a device employing external memory for program and data storage, while the term microcomputer refers to a device with on-chip ROM and RAM for program and data storage. In describing the instant invention, the term "microcomputer" will be used to include both types of devices, and the term "microprocessor" will be primarily used to refer to microcomputers without on-chip ROM. Since the terms are often used interchangeably in the art, however, it should be understood that the use of one of the other of these terms in this description should not be considered as restrictive as to the features of this invention. Modern microcomputers can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microcomputers/microprocessors. General purpose microprocessors, such as the M68020 manufactured by Motorola, Inc. are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central processing unit in equipment such as personal computers. Such general-purpose microprocessors, while having good performance for a wide range of arithmetic and logical functions, are of course not specifically designed for or adapted to any particular one of such functions. In contrast, special-purpose microcomputers are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microcomputer. By knowing the primary function of the microcomputer, the designer can structure the microcomputer in such a manner that the performance of the specific function by the special-purpose microcomputer greatly exceeds the performance of the same function by the general-purpose microprocessor regardless of the program created by the user. One such function which can be performed by a special-purpose microcomputer at a greatly improved rate is digital signal processing, specifically the computations required for the implementation of digital filters and for performing Fast Fourier Transforms. Because such computations consist to a large degree of repetitive operations such as integer multiply, multiple-bit shift, and multiply-and-add, a special-purpose microcomputer can be constructed specifically adapted to these repetitive functions. Such a special-purpose microcomputer is described in U. S. Patent US-A-4 577 282, assigned to Texas Instruments Incorporated and incorporated herein by reference. The specific design of a microcomputer for these computations has resulted in sufficient performance improvement over general purpose microprocessors to allow the use of such special-purpose microcomputers in real-time applications, such as speech and image processing. Digital signal processing applications, because of their computation intensive nature, also are rather intensive in memory access operations. Accordingly, the overall performance of the microcomputer in performing a digital signal processing function is not only determined by the number of specific computations performed per unit time, but also by the speed at which the microcomputer can retrieve data from, and store data to, system memory. Prior special-purpose microcomputers, such as the one described in said US-A-4 577 282, have utilized modified versions of a Harvard architecture, so that the access to data memory may be made independent from, and simultaneous with, the access of program memory. Such architecture has, of course, provided for additional performance improvement. The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, application systems and methods of operation and manufacture. US-A-4 434 461, on which the preamble of claim 1 is based, and US-A-4 287 560 describe microprocessors in which various registers are duplicated. During interrupts, the microprocessor switches over to the duplicate registers, while the main registers retain their original contents until the microprocessor switches back to them. US-A-4 091 445, US-A-4 218 739, US-A-3 221 309 and US-A-4 689 739 all deal with the problem of suppressing the interruptions (or delaying execution of their service routines) for a sufficient time to allow certain functions of the currently proqram or context - be it the "main" proqram or a previous interrupt routine - to be completed. According to US4091445, "in many prior art devices the problem is solved by arbitrarily inserting a delay prior to switching between successive programs"; rather than inserting a fixed delay before another program is allowed to take over control, this patent provides an apparatus wherein "switching may occur only when a response has been received for all commands issued under the existing program". According to US-A-4 218 739, while an "interrupt must be handled in an expeditious manner ... on the other hand it is important that at certain times, such interrupts be suppressed so that certain functions in process may be carried out". Hence certain interrupts "may be suppressed for one or two instruction times". The invention provides a data processing system comprising: an electronic processor having an instruction set and having an interrupt signal input and being arranged to execute a predetermined series of instructions in response to said interrupt signal; and an electronic processor being responsive to a context signal and operable in alternative processing contexts identified by the context signal; a main and a counterpart register connected to said electronic processor, said main register being arranged to participate in a first processing context and one of said main and counterpart registers being arranged to participate in a second processing context while the other of said main and counterpart registers retains information from the first processing context until a return thereto; and a context switching circuit connected to said main and counterpart registers operative selectively to control input and output operations of said registers to and from said electronic processor depending on the processing context; characterised in that said context signal is derivable from said interrupt input signal and said instruction set includes an instruction which inhibits interrupts during execution of instructions following said return. In general, one form of the invention is a data processing device that includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to particiapte in one processing context while retaining information from another processing context until a return thereto. A contact switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other system forms of the invention are also disclosed and claimed herein. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the appended claims. The preferred embodiments of the invention as well as other features and advantages thereof will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein: FIGS. 1A and 1B are two halves of an electrical diagram in block form of an improved microcomputer device including a CPU or central processor unit formed on a single semiconductor chip ; FIG. 2 is a block diagram of an improved industrial process and protective control system; FIG. 3 is a partially pictorial, partially block electrical diagram of an improved automotive vehicle system; FIG. 4 is an electrical block diagram of an improved motor control system; FIG. 5 is an electrical block diagram of another improved motor control system; FIG. 6 is an electrical block diagram of yet another improved motor control system; FIG. 7 is an electrical block diagram of an improved robotic control system; FIG. 8 is an electrical block diagram of an improved satellite telecommunications system; FIG. 9 is an electrical block diagram of an improved echo cancelling system for the system of FIG. 8; FIG. 10 is an electrical block diagram of an improved modem transmitter; FIG. 11 is an electrical block diagram equally representative of hardware blocks or process blocks for the improved modem transmitter of FIG. 10; FIG. 12 is an electrical block diagram equally representative of hardware blocks or process blocks for an improved modem receiver; FIG. 13 is an electrical block diagram of an improved system including a host computer and a digital signal processor connected for PCM (pulse code modulation) communications; FIG. 14 is an electrical block diagram of an improved video imaging system with multidimensional array processing; FIG. 15 is an electrical block diagram equally representative of hardware blocks or process blocks for improved graphics, image and video processing; FIG. 16 is an electrical block diagram of a system for improved graphics, image and video processing; FIG. 17 is an electrical block diagram of an improved automatic speech recognition system; FIG. 18 is an electrical block diagram of an improved vocoder-modem system with encryption; FIG. 19 is a series of seven representations of an electronic register holding bits of information and illustrating bit manipulation operations of a parallel logic unit improvement of FIG. 1B; FIG. 20 is an electrical block diagram of an improved system for high-sample rate digital signal processing; FIG. 21 is an electrical block diagram of architecture for an improved data processing device including the CPU of FIGS. 1A and 1B; FIG. 22 a schematic diagram of a circuit for zero-overhead interrupt context switching; FIG. 23 is a schematic diagram of an alternative circuit for zero-overhead interrupt context switching; FIG. 24 is a schematic diagram of another alternative circuit for zero-overhead interrupt context switching; FIG. 25 is a flow diagram of a method of operating the circuit of FIG. 24; FIG. 26 is a process flow diagram illustrating instructions for automatically computing a maximum or a minimum in the data processing device of FIGS. 1A and 1B. Corresponding numerals and other symbols refer to corresponding parts in the various figures of drawing except where the context indicates otherwise. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS An architectural overview first describes a preferred embodiment digital signal processing device 11. The preferred embodiment digital signal processing device 11 of Figs. 1A and 1B implements a Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. Instructions are included to provide data transfers between the two spaces. The device 11 has a program addressing circuit 13 and an electronic computation circuit 15 comprising a processor. Computation circuit 15 performs two's-complement arithmetic using a 32 bit ALU 21 and accumulator 23. The ALU 21 is a general-purpose arithmetic logic unit that operates using 16-bit words taken from a data memory 25 of Fig. 1B or derived from immediate instructions or using the 32-bit result of a multiplier 27. In addition to executing arithmetic instructions, the ALU 21 can perform Boolean operations. The accumulator 23 stores the output from the ALU 21 and provides a second input to the ALU 21 via a path 29. The accumulator 23 is illustratively 32 bits in length and is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high and low order accumulator words in data memory 25. For fast, temporary storage of the accumulator 23 there is a 32-bit accumulator buffer ACCB 31. In addition to the main ALU 21 there is a Peripheral Logic Unit (PLU) 41 in Fig. 1B that provides logic operations on memory locations without affecting the contents of the accumulator 23. The PLU 41 provides extensive bit manipulation ability for high-speed control purposes and simplifies bit setting, clearing, and testing associated with control and status register operations. The multiplier 27 of Fig. 1A performs a 16 x 16 bit two's complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three elements: a temporary TREG0 register 49, product register PREG 51 and multiplier array 53. The 16-bit TREG0 register 49 temporarily stores the multiplicand; the PREG register 51 stores the 32-bit product. Multiplier values either come from data memory 25, from a program memory 61 when using the MAC/MACD instructions, or are derived immediately from the MPYK (multiply immediate) instruction word. Program memory 61 is connected at addressing inputs to a program address bus 101A. Memory 61 is connected at its read/write input/output to a program data bus 101D. The fast on-chip multiplier 27 allows the device 11 to efficiently perform fundamental DSP operations such as convolution, correlation, and filtering. A processor scaling shifter 65 has a 16-bit input connected to a data bus 111D via a multiplexer (MUX) 73, and a 32-bit output connected to the ALU 21 via a multiplexer 77. The scaling shifter 65 produces a left-shift of 0 to 16 bits on the input data, as programmed by instruction or defined in a shift count register (TREG1) 81. The LSBs (least significant bits) of the output are filled with zeros, and the MSBs (most significant bits) may be either filled with zeros or sign-extended, depending upon the state of the sign-extension mode bit SXM of the status register ST1 in a set of registers 85 of Fig. 1B. Additional shift capabilities enable the processor 11 to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention. Up to eight levels of a hardware stack 91 are provided for saving the contents of a program counter 93 during interrupts and subroutine calls. Program counter 93 is selectively loaded upon a context change via a MUX 95 from program address bus 101A or program data bus 101D. The PC 93 is written to address bus 101A or pushed onto stack 91. On interrupts, certain strategic registers (accumulator 23, product register 51, TREG0 49, TREG1, TREG2, and in register 113: ST0, ST1, PMST, ARCR, INDX and CMPR) are pushed onto a one deep stack and popped upon interrupt return; thus providing a zero-overhead, interrupt context switch. The interrupts operative to save the contents of these registers are maskable. The functional block diagram shown in Figures 1A and 1B outlines the principal blocks and data paths within the processor. Further details of the functional blocks are provided hereinbelow. Refer to Table A-1, the internal hardware summary, for definitions of the symbols used in Figures 1A and 1B. The processor architecture is built around two major buses (couples): the program bus 101A and 101D and the data bus 111A and 111D. The program bus carries the instruction code and immediate operands from program memory on program data bus 101D. Addresses to program memory 61 are supplied on program address bus 101A. The data bus includes data address bus 111A and data bus 111D. The latter bus 111D interconnects various elements, such as the Central Arithmetic Logic Unit (CALU) 15 and an auxiliary register file 115 and registers 85, to the data memory 25. Together, the program and data buses 101 and 111 can carry data from on-chip data memory 25 and internal or external program memory 61 to the multiplier 27 in a single cycle for multiply/accumulate operations. Data memory 25 and registers 85 are addressed via data address bus 111A. A core register address decoder 121 is connected to data address bus 111A for addressing registers 85 and all other addressable CPU core registers. The processor 13, 15 has a high degree of parallelism; e.g., while the data is being operated upon by the CALU 15, arithmetic operations are advantageously implemented in an Auxiliary Register Arithmetic Unit (ARAU) 123. Such parallelism results in a powerful set of arithmetic logic, and bit manipulation operations that may all be performed in a single machine cycle. The processor internal hardware contains hardware for single-cycle 16 x 16-bit multiplication, data shifting and address manipulation. Table A-1 presents a summary of the internal hardware. This summary table, which includes the internal processing elements, registers, and buses, is alphabetized within each functional grouping. Internal Hardware UNIT SYMBOL FUNCTION Accumulator ACC(32) ACCH(16 ACCL(16) A 32-bit accumulator accessible in two halves: ACCH (accumulator high) and ACCL (accumulator low). Used to store the output of the ALU. Accumulator Buffer ACCB(32) A register used to temporarily store the 32-bit contents of the accumulator. This register has a direct path back to the ALU and therefore can be arithmetically or logically operated with the ACC. Arithmetic Logic Unit ALU A 32-bit two's complement arithmetic logic unit having two 32-bit input ports and one 32-bit output port feeding the accumulator. Auxiliary Arithmetic Unit ARAU A 16-bit unsigned arithmetic unit used to calculate indirect addresses using the auxiliary, index, and compare registers as inputs. Auxiliary Register Compare ARCR A 16-bit register used in use as a limit to compare indirect address against. Auxiliary Register File AUXREGS A register file containing eight 16-bit auxiliary registers (AR0-AR7), used for indirect data address pointers, temporary storage, or integer arithmetic processing through the ARAU. Auxiliary Register Pointer ARP A 3-bit register used as a pointer to the currently selected auxiliary register. Block Repeat Counter Register BRCR A 16-bit memory-mappped counter register used as a limit to the number of times the block is to be repeated. Block Repeat Counter Register PAER A 16-bit memory-mapped register containing the end address of the segment of code being repeated. Block Repeat Address Start Register PASR A 16-bit memory-mapped register containing the start address of the segment of code being repeated. Bus Interface Module BIM A buffered interface used to pass data between the data and program buses. Central Arithmetic Logic Unit CALU The grouping of the ALU, multiplier, accumulator, and scaling shifters. Circular Buffer Control Register CBCR An 8-bit register used to enable/disable the circular buffers and define which auxiliary registers are mapped to the circular buffers. Circular Buffer End Address CBER1 Two 16-bit registers indicating circular buffer end addresses. CBER1 and CBER2 are associated with circular buffers one and two respectively. Circular Buffer Start Address CBSR1 CBSR2 Two 16-bit registers indicating circular buffer start addresses. CBSR1/CBSR2 are associated with circular buffers one and two respectively. Data Bus DATA A 16-bit bus used to route data. Data Memory DATA MEMORY This block refers to data memory used with the core and defined in specific device descriptions. It refers to both on and off-chip memory blocks accessed in data memory space. Data Memory Address Immediate Register DMA A 7-bit register containing the immediate relative address within a data page. Data Memory Page Pointer DP(9) A 9-bit register containing the address of the current page. Data pages are 128 words each, resulting in 512 pages of addressable data memory space (some locations are reserved). Direct Data Memory Address Bus DATA ADDRESS A 16-bit bus that carries the direct address for the data memory, which is the concatenation of the DP register and the seven LSBs of the instruction (DMA). Dynamic Bit Manipulation Register DBMR A 16-bit memory-mapped register used as an input to PLU. Register PLU. Dynamic Bit Pointer TREG2 A 4-bit register that holds a dynamic bit pointer for the BITT instruction. Dynamic Shift Count TREG1 A 5-bit register that holds a dynamic prescaling shift count for data inputs to the ALU. Global Memory Allocation Register GREG(8) An 8-bit memory-mapped register for allocating the size of the global memory space. Interrupt Flag Register IFR(16) A 16-bit flag register used to latch the active-low interrupts. The IFR is a memory mapped register. Interrupt Mask Register IMR(16) A 16-bit memory mapped register used to mask interrupts. Multiplexer MUX A bus multiplexer used to select the source of operands for a bus or execution unit. The MUXs are connected via instructions. Multiplier MULTIPLIER A 16 x 16 bit parallel multiplier. Peripheral Logic Unit PLU A 16-bit logic unit that executes logic operations from either long immediate operands or the contents of the DBMR directly upon data locations without interfering with the contents of the CALU registers. Prescaler Count Register COUNT A 4-bit register that contains the count value for the prescaling operation. This register is loaded from either the instruction or the dynamic shift count when used in prescaling data. In conjunction with the BIT and BITT instructions, it is loaded from the dynamic bit pointer of the instruction. Product Register PREG(32) A 32-bit product register used to hold the multiplier product. The high and low words of the PREG can also be accessed individually using the SPH/SPL (store P register high/low) instructions. Product Register Buffer BPR(32) A 32-bit register used for temporary storage of the product register. This register can also be a direct input to the ALU. Program Bus PROG DATA A 16-bit bus used to route instructions (and data for the MAC and MACD instructions). Program Counter PC(16) A 16-bit program counter used to address program memory sequentially. The PC always contains the address of the next instruction to be executed. The PC contents are updated following each instruction decode operation. Program Memory PROGRAM MEMORY This block refers to program memory used with the core and defined in specific device descriptions. It refers to both on and off-chip memory blocks accessed in program memory space. Program Memory Address Bus PROG ADDRESS A 16-bit bus that carries the program memory address. Prescaling Shifter PRESCALER A 0 to 16-bit left barrel shifter used to prescale data coming into the ALU. Also used to align data for multi-precision operations. This shifter is also used as a 0-16 bit right barrel shifter of the ACC. Postscaling Shifter POST-SCALER A 0-7 bit left barrel shifter used to post scale data coming out of the CALU. Product Shifter P-SCALER A 0, 1, 4-bit left shifter used to remove extra sign bits (gained in the multiply operation) when using fixed point arithmetic. A 6-bit right shifter used to scale the products down to avoid overflow in the accumulation process. Repeat Counter RPTC(16) An 8-bit counter to control the repeated execution of a single instruction. Stack STACK A 8 x 16 hardware stack used to store the PC during interrupts and calls. The ACCL and data memory values $ay also be pushed onto the popped from the stack. Status Registers ST0,ST1, PMST, CBCR Three 16-bit status registers that contain status and control bits. Temporary Multiplicand TREG0 A 16-bit register that temporarily holds an operand for the multiplier. Block Move Address Register BMAR A 16-bit register that holds an address value for use with block moves or multiply accumulates. Memory Mapped Registers NAME ADDRESS DESCRIPTION DEC HEX 0-3 0-3 RESERVED IMR 4 4 INTERRUPT MASK REGISTER GREG 5 5 GLOBAL MEMORY ALLOCATION REGISTER IFR 6 6 INTERRUPT FLAG REGISTER PMST 7 7 PROCESSOR MODE STATUS REGISTER RPTC 8 8 REPEAT COUNTER REGISTER BRCR 9 9 BLOCK REPEAT COUNTER RGISTER PASR 10 A BLOCK REPEAT PROGRAM ADDRESS START REGISTER PAER 11 B BLOCK REPEAT PROGRAM ADDRESS END REGISTER TREG0 12 C TEMPORARY REGISTER USED FOR MULTIPLICAND TREG1 13 D TEMPORARY REGISTER USED FOR DYNAMIC SHIFT COUNT TREG2 14 E TEMPORARY REGISTER USED AS BIT POINTER IN DYNAMIC BIT TEST DBMR 15 F DYNAMIC BIT MANIPULATION REGISTER AR0 16 10 AUXILIARY REGISTER ZERO AR1 17 11 AUXILIARY REGISTER ONE AR2 18 12 AUXILIARY REGISTER TWO AR3 19 13 AUXILIARY REGISTER THREE AR4 20 14 AUXILIARY REGISTER FOUR AR5 21 15 AUXILIARY REGISTER FIVE AR6 22 16 AUXILIARY REGISTER SIX AR7 23 17 AUXILIARY REGISTER SEVEN INDX 24 18 INDEX REGISTER ARCR 25 19 AUXILIARY REGISTER COMPARE REGISTER CBSR1 26 1A CIRCULAR BUFFER 1 START ADDRESS REGISTER CBER1 27 1B CIRCULAR BUFFER 1 END ADDRESS REGISTER CBSR2 28 1C CIRCULAR BUFFER 2 START ADDRESS REGISTER CBER2 29 1D CIRCULAR BUFFER 2 END ADDRESS REGISTER CBCR 30 1E CIRCULAR BUFFER CONTROL REGISTER BMAR 31 1F BLOCK MOVE ADDRESS REGISTER The processor 13, 15 addresses a total of 64K words of data memory 25. The data memory 25 is mapped into the 96K data memory space and the on-chip program memory is mapped into a 64K program memory space. The 16-bit data address bus 111A addresses data memory 25 in one of the following two ways: 1) By a direct address bus (DAB) using the direct addressing mode (e.g. ADD 010h), or 2) By an auxiliary register file bus (AFB) using the indirect addressing mode (e.g. ADD*) 3) Operands are also addressed by the contents of the program counter in an immediate addressing mode. In the direct addressing mode, a 9-bit data memory page pointer (DP) 125 points to one of 512 (128-word) pages. A MUX 126 selects on command either bus 101D or 111D for DP pointer register portion 125. The data memory address (dma) specified from program data bus 101D by seven LSBs 127 of the instruction, points to the desired word within the page. The address on the DAB is formed by concatenating the 9-bit DP with the 7-bit dma. A MUX 129 selectively supplies on command either the ARAU 123 output or the concatenated (DP, dma) output to data address bus 111A. In the indirect addressing mode, the currently selected 16-bit auxiliary register AR(ARP) in registers 115 addresses the data memory through the AFB. While the selected auxiliary register provides the data memory address and the data is being manipulated by the CALU 15, the contents of the auxiliary register may be manipulated through the ARAU 123. The data memory address map can be extended beyond the 64K-word address reach of the 16-bit address bus by paging in an additional 32K words via the global memory interface. By loading the GREG register with the appropriate value, additional memory can be overlaid over the local data memory starting at the highest address and moving down. This additional memory is differentiated from the local memory by the BR- pin being active low. When an immediate operand is used, it is either contained within the instruction word itself or, in the case of 16-bit immediate operands, the word following the instruction word. Eight auxiliary registers (AR0-AR7) in the auxiliary registers 115 are used for indirect addressing of the data memory 25 or for temporary data storage. Indirect auxiliary register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are pointed to by a three-bit auxiliary register pointer (ARP) 141 that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. A MUX 144 has inputs connected to data bus 111D and program data bus 101D. MUX 144 is operated by instruction to obtain a value for ARP 141 from one of the two buses 111D and 101D. The auxiliary registers 115 and the ARP 141 may be loaded either from data memory 25, the accumulator 23, the product register 51, or by an immediate operand defined in the instruction. The contents of these registers may also be stored in data memory 25 or used as inputs to the main CPU. The auxiliary register file (AR0-AR7) 115 is connected to the Auxiliary Register Arithmetic Unit (ARAU) 123 shown in Figure 1B. The ARAU 123 may autoindex the current auxiliary register in registers 115 while the data memory location is being addressed. Indexing by either +/-1 or by the contents of an index register 143 or AR0 may be performed. As a result, accessing tables of information by rows or columns does not require the Central Arithmetic Logic Unit (CALU) 15 for address manipulation, thus freeing it for other operations. The index register 143 or the eight LSBs of an instruction register IR are selectively connected to one of the inputs of the ARAU 123 via a MUX 145. The other input of ARAU 123 is fed by a MUX 147 from the current auxiliary register AR (being pointed to by ARP). As described above, the Central Arithmetic Logic Unit (CALU) 15 contains a 16-bit prescaler scaling shifter 65, a 16 x 16-bit parallel multiplier 27, a 32-bit Arithmetic Logic Unit (ALU) 21, a 32-bit accumulator (ACC) 23, and additional shifters 169 and 181 at the outputs of both the accumulator 23 and the multiplier 27. This section describes the CALU components and their functions. The following steps occur in the implementation of a typical ALU instruction: 1) Data is fetched from the RAM 25 on the data bus. 2) Data is passed through the scaling shifter 65 and the ALU 21 where the arithmetic is performed, and 3) The result is moved into the accumulator 23. One input to the ALU 21 is provided from the accumulator 23, and the other input is selected from the Product Register (PREG) 51 of the multiplier 27, a Product Register Buffer (BPR) 185, the Accumulator Buffer (ACCB) 31 or from the scaling shifters 65 and 181 that are loaded from data memory 25 or the accumulator 23. Scaling shifter 65 advantageously has a 16-bit input connected to the data bus 111D via MUX 73 and a 32-bit output connected to the ALU 21 via MUX 77. The scaling shifter prescaler 65 produces a left shift of 0 to 16 bits on the input data, as programmed by loading a COUNT register 199. The shift count is specified by a constant embedded in the instruction word, or by a value in register TREG1. The LSBs of the output of prescaler 65 are filled with zeros, and the MSBs may be either filled with zeros or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1. The same shifter 65 has another input path from the accumulator 23 via MUX 73. When using this path the shifter 65 acts as a 0 to 16 bit right shifter. This allows the contents of the ACC to be shifted 0 to 16 bits right in a single cycle. The bits shifted out are lost and the bits shifted in are either zeros or copies of the original sign bit depending on the value of the SXM status bit. The various shifters 65, 169 and 181 allow numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention. The 32-bit ALU 21 and accumulator 23 implement a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle in the preferred embodiment. Once an operation is performed in the ALU 21, the result is transferred to the accumulator 23 where additional operations such as shifting may occur. Data that is input to the ALU may be scaled by the scaling shifter 181. The ALU 21 is a general-purpose arithmetic unit that operates on 16-bit words taken from data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can even perform Boolean operations. As mentioned hereinabove, one input to the ALU is provided from the accumulator 23, and the other input is selectively fed by MUX 77. MUX 77 selects the Accumulator Buffer (ACCB) 31 or secondly the output of the scaling shifter 65 (that has been read from data RAM or from the ACC), or thirdly, the output of product scaler 169. Product scaler 169 is fed by a MUX 191. MUX 191 selects either the Product Register PREG 51 or the Product Register Buffer 185 for scaler 169. The 32-bit accumulator 23 is split into two 16-bit segments for storage via data bus 111D to data memory 25. Shifter 181 at the output of the accumulator provides a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus 111D for storage. The contents of the accumulator 23 remain unchanged. When the post-scaling shifter 181 is used on the high word of the accumulator 23 (bits 16-31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0-15). When the post-scaling shifter 181 is used on the low word, the LSB's are zero filled. Floating-point operations are provided for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed point numbers contained in the accumulator 21 by performing left shifts. The four bits of temporary register TREG1 81 define a variable shift through the scaling shifter 65 for the LACT/ADDT/SUBT (load/add-to/subtract from accumulator with shift specified by TREG1) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized, i.e., floating-point to fixed-point conversion. They are also useful in applications such as execution of an Automatic Gain Control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of a temporary register TREG2 195. Registers TREG1 and TREG2 are fed by data bus 111D. A MUX 197 selects values from TREG1, TREG2 or from program data bus 101D and feeds one of them to a COUNT register 199. COUNT register 199 is connected to scaling shifter 65 to determine the amount of shift. The single-cycle 0-to-16-bit right shift of the accumulator 23 allows efficient alignment of the accumulator for multiprecision arithmetic. This coupled with the 32-bit temporary buffers ACCB on the accumulator and BPR on the product register enhance the effectiveness of the CALU in multiprecision arithmetic. The accumulator buffer register (ACCB) provides a temporary storage place for a fast save of the accumulator. ACCB can be also used as an input to the ALU. ACC and ACCB can be stored into each other. The contents of the ACCB can be compared by the ALU against the ACC with the larger/smaller value stored in the ACCB (or in both ACC and ACCB) for use in pattern recognition algorithms. For instance, the maximum or minimum value in a string of numbers is advantageously found by comparing the contents of the ACCB and ACC, and if the condition is met then putting the minimum or maximum into one or both registers. The product register buffer (BPR) provides a temporary storage place for a fast save of the product register. The value stored in the BPR can also be added to/subtracted from the accumulator with the shift specified for the provided shifter 169. System control is provided by the program counter 93, hardware stack 91, PC-related hardware, the external reset signal RS-, interrupts to an interrupt control 231, the status registers, and the repeat counters. The following sections describe the function of each of these components in system control and pipeline operation. The processor has 16-bit Program Counter (PC) 93, and an eight deep hardware stack 91 provides PC storage. The program counter 93 addresses internal and external program memory 61 in fetching instructions. The stack 91 is used during interrupts and subroutines. The program counter 93 addresses program memory 61, either on-chip or off-chip, via the Program Address Bus (PAB) 101A. Through the PAB, an instruction is addressed in program memory 61 and loaded via program data bus 101D into the Instruction Register (IR) for a decoder PLA 221. When the IR is loaded, the PC 93 is ready to start the next instruction fetch cycle. Decoder PLA (programmable logic array) 221 has numerous outputs for controlling the MUXes and all processor elements in order to execute the instructions in the processor instruction set. For example, decoder PLA 221 feeds command signals to a pipeline controller 225 which also has various outputs for implementing the pipelined processing operations so that the processor elements are coordinated in time. The outputs of pipeline controller 225 also include CALL, RET (RETURN), IAQ (interrupt acquisition) and IACK (interrupt acknowledge). Data memory 25 is addressed by the program counter 93 during a BLKD instruction, which moves data blocks from one section of data memory to another. The contents of the accumulator 23 may be loaded into the PC 93 in order to implement "computed GOTO" operations. This can be accomplished using the BACC (branch to address in accumulator) or CALA (call subroutine indirect) instructions. To start a new fetch cycle, the PC 93 is loaded either with PC+1 or with a branch address (for instructions such as branches, calls, or interrupts). In the case of special conditional branches where the branch is not taken, the PC is incremented once more beyond the location of the branch immediate. In addition to the conditional branches, the processor has a full complement of conditional calls and returns. The processor 13, 15 operates with a four deep pipeline. The Peripheral Logic Unit (PLU) 41 of Fig. 1B is used to directly set, clear, toggle or test multiple bits in a control/status register or any data memory location. The PLU provides a direct logic operation path to data memory values without affecting the contents of the accumulator or product register. It is used to set or clear multiple control bits in a register or to test multiple bits in a flag register. The PLU 41 operates by fetching one operand via data bus lllD from data memory space, fetching the second from either long immediate on the program bus 101D or a DBMR (Dynamic Bit Manipulation Register) 223 via a MUX 225. The DBMR is previously loaded from data bus 111D. Then the PLU executes its logic operation, defined by the instruction on the two operands. Finally, the result is written via data bus 111D to the same data location that the first operand was fetched from. The PLU allows the direct manipulation of bits in any location in data memory space. This direct bit-manipulation is done with by ANDing, ORing, XORing or loading a 16-bit long immediate value to a data location. For example, to initialize the CBCR (Circular Buffer Control Register) to use AR1 for circular buffer 1 and AR2 for circular buffer 2 but not enable the circular buffers, execute: SPLK 021h, CBCR Store Peripheral Long Immediate To later enable circular buffers 1 and 2 execute: OPLK 088h, CBCR Set bit 7 and bit 3 in CBCR Testing for individual bits in a specific register or data word is still done via the BIT instruction, however, a data word can be tested against a particular pattern with the CPLK (Compare Peripheral Long Immediate) instruction. If the data value is equal to the long immediate value, then the TC bit is set to one. If the result of any PLU instruction is zero then the TC bit is set. The bit set, clear, and toggle functions can also be executed with a 16-bit dynamic register DBMR value instead of the long immediate value. This is done with the following three instructions: XPL (XOR DBMR register to data); OPL (OR DBMR register to data); and APL (AND DBMR Register to data). The processor has sixteen external maskable user interrupts (INT16-INT1) available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), by parity checkers (PNTL and PNTH), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS-) having the highest priority and INT15 having the lowest priority. An interrupt control block 231 feeds program data bus 101D. Vector locations and priorities for all internal and external interrupts are shown in Table A-5. The TRAP instruction, used for software interrupts, is not prioritized but is included here since it has its own vector location. Each interrupt address has been spaced apart by two locations so that branch instructions can be accommodated in those locations. Interrupt Locations and Priorities NAME LOCATION PRIORITY FUNCTION DEC HEX RS- 0 0 1 (highest) EXTERNAL RESET SIGNAL INT1- 2 2 3 EXTERNAL USER INTERRUPT #1 INT2- 4 4 4 EXTERNAL USER INTERRUPT #2 INT3- 6 6 5 EXTERNAL USER INTERRUPT #3 INT4- 8 8 6 EXTERNAL USER INTERRUPT #4 INT5- 10 A 7 EXTERNAL USER INTERRUPT #5 INT6- 12 C 8 EXTERNAL USER INTERRUPT #6 INT7- 14 E 9 EXTERNAL USER INTERRUPT #7 INT8- 16 10 10 EXTERNAL USER INTERRUPT #8 INT9- 18 12 11 EXTERNAL USER INTERRUPT #9 INT10- 20 14 12 EXTERNAL USER INTERRUPT #10 INT11- 22 16 13 EXTERNAL USER INTERRUPT #11 INT12- 24 18 14 EXTERNAL USER INTERRUPT #12 INT13- 26 1A 15 EXTERNAL USER INTERRUPT #13 INT14- 28 1C 16 EXTERNAL USER INTERRUPT #14 INT15- 30 IE 17 EXTERNAL USER INTERRUPT #13 INT16- 32 20 18 EXTERNAL USER INTERRUPT #14 TRAP 34 22 N/A TRAP INSTRUCTION VECTOR NMI 36 24 2 NON-MASKABLE INTERRUPT In Fig. 1B, a Bus Interface Module BIM 241 is connected between data bus 111D and program data bus 101D. BIM 241 on command permits data transfers between buses 101D and 111D and increases the architectural flexibility of the system compared to either the classic Harvard architecture or Von Neumann architecture. Inventive systems including processing arrangements and component circuitry made possible by improvements to the processor 13, 15 are discussed next. For general purpose digital signal processing applications, these systems advantageously perform convolution, correlation, Hilbert transforms, Fast Fourier Transforms, adaptive filtering, windowing, and waveform generation. Further applications involving in some cases the general algorithms just listed are voice mail, speech vocoding, speech recognition, speaker verification, speech enhancement, speech synthesis and text-to-speech systems. Instrumentation according to the invention provides improved spectrum analyzers, function generators, pattern matching systems, seismic processing systems, transient analysis systems, digital filters and phase lock loops for applications in which the invention is suitably utilized. Automotive controls and systems according to the invention suitably provide engine control, vibration analysis, anti-skid braking control, adaptive ride control, voice commands, and automotive transmission control. In the naval, aviation and military field, inventive systems are provided and improved according to the invention to provide global positioning systems, processor supported navigation systems, radar tracking systems, platform stabilizing systems, missile guidance systems, secure communications systems, radar processing and other processing systems. Further systems according to the invention include computer disk drive motor controllers, printers, plotters, optical disk controllers, servomechanical control systems, robot control systems, laser printer controls and motor controls generally. Some of these control systems are applicable in the industrial environment as robotics controllers, auto assembly apparatus and inspection equipment, industrial drives, numeric controllers, computerized power tools, security access systems and power line monitors. Telecommunications inventions contemplated according to the teachings and principles herein disclosed include echo cancellers, ADPCM transcoders, digital PBXs, line repeaters, channel multiplexers, modems, adaptive equalizers, DTMF encoders and DTMF decoders, data encryption apparatus, digital radio, cellular telephones, fax machines, loudspeaker telephones, digital speech interpolation (DSI) systems, packet switching systems, video conferencing systems and spread-spectrum communication systems. In the graphic imaging area, further inventions based on the principles and devices and systems disclosed herein include optical character recognition apparatus, 3-D rotation apparatus, robot vision systems, image transmission and compression apparatus, pattern recognition systems, image enhancement equipment, homomorphic processing systems, workstations and animation systems and digital mapping systems. Medical inventions further contemplated according to the present invention include hearing aids, patient monitoring apparatus, ultrasound equipment, diagnostic tools, automated prosthetics and fetal monitors, for example. Consumer products according to the invention include high definition television systems such as high definition television receivers and transmission equipment used at studios and television stations. Further consumer inventions include music synthesizers, solid state answering machines, radar detectors, power tools and toys and games. It is emphasized that the system aspects of the invention contemplated herein provide advantages of improved system architecture, system performance, system reliability and economy. For example, in Figure 2, an inventive industrial process and protective control system 300 according to the invention includes industrial sensors 301 and 303 for sensing physical variables pertinent to a particular industrial environment. Signals from the sensors 301 and 303 are provided to a signal processor device 11 of Figs. 1A and 1B which include the PLU (parallel logic unit) improvement 41 of Fig. 1B. An interface 305 includes register locations A, B, C, D, E, F, G and H and drivers (not shown). The register locations are connected via the drivers and respective lines 307 to an industrial process device driven by a motor 311, relay operated apparatus controlled by relays 313 and various valves including a solenoid valve 315. In the industrial process and protective control environment, various engineering and economic considerations operate at cross purposes. If the speed or throughput of the industrial process is to be high, heavy burdens are placed on the processing capacity of device 11 to interpret the significance of relatively rapid changes occurring in real time as sensed by sensors 301 and 303. On the other hand, the control functions required to respond to the real-world conditions sensed by sensors 301 and 303 must also be accomplished swiftly. Advantageously, the addition of PLU 41 resolves conflicting demands on device 11, with negligible additional costs when device 11 is fabricated to a single semiconductor chip. In this way, the industrial processing rate, the swiftness of protective control and the precision of control are considerably enhanced. In Figure 3, an inventive automotive vehicle 321 includes a chassis 323 on which is mounted wheels and axles, an engine 325, suspension 327, and brakes 329. An automotive body 331 defines a passenger compartment which is advantageously provided with suspension relative to chassis 323. An active suspension 335 augments spring and absorber suspension technique and is controlled via an interface 341 having locations for bits A, B, C, D, E, F, G, H, I, J, K, L, M and N. A parallel computation processor 343 utilizes computation units of the type disclosed in Figures 1A and 1B and includes at least one parallel logic unit 41 connected to data bus 351D and prcgram data bus 361D. Numerous sensors include sensors 371, 373 and 375 which monitor the function of suspension 335, engine operation, and anti-skid braking respectively. An engine control system 381 is connected to several of the locations of interface 341. Also an anti-skid braking control system 383 is connected to further bits of interface 341. Numerous considerations of automotive reliability, safety, passenger comfort, and economy place heavy demands on prior automotive vehicle systems. In the invention of Figure 3, automotive vehicle 321 is improved in any or all of these areas by virtue of the extremely flexible parallelism and control advantages of the invention. The devices such as device 11 which are utilized in the systems of Figs. 2 and 3 and further systems described herein not only address issues of increased device performance, but also solve industrial system problems which determine the user's overall system performance and cost. A preferred embodiment device 11 executes an instruction in 50 nanoseconds and further improvements in semiconductor manufacture make possible even higher instruction rates. The on-chip program memory is RAM based and facilitates boot loading of a program from inexpensive external memory. Other versions are suitably ROM based for further cost reduction. An inventive digitally controlled motor system 400 of Figure 4 includes a digital controller 401 having a device 11 of Figs. 1A and 1B. Digital controller 401 supplies an output u(n) to a zero order hold circuit ZOH 403. ZOH 403 supplies control output u(t) to a DC servomotor 405 in industrial machinery, home appliances, military equipment or other application systems environment. Connection of motor 405 to a disk drive 406 is shown in Fig. 4. The operational response of servomotor 405 to the input u(t) is designated y(t). A sensor 407 is a transducer for the motor output y(t) and feeds a sampler 409 which in its turn supplies a sampled digitized output y(n) to a subtractor 411. Sampler 409 also signals digital controller 401 via an interrupt line INT-. A reference input r(n) from human or automated supervisory control is externally supplied as a further input to the subtracter 411. An error difference e(n) is then fed to the digital controller 401 to close the loop. Device 11 endows controller 401 with high loop bandwidth and multiple functionality for processing and control of other elements besides servomotors as in Fig. 2. Zero-overhead interrupt context switching in device 11 additionally enhances the bandwidth and provides an attractive alternative to polling architecture. In Figure 5, a multi-variable state controller 421 executes advanced algorithms utilizing the device 11 processor. State controller 421 receives a reference input r(n) and supplies an output u(n) to a motor 423. Multiple electrical variables (position x1, speed x2, current x3 and torque x4) are fed back to the state controller 421. Any one or more of the four variables x1-x4 (in linear combination for example) are suitably controlled for various operational purposes. The system can operate controlled velocity or controlled torque applications, and run stepper motors and reversible motors. In Figure 6, a motor 431 has its operation sensed and sampled by a sampler 433. A processor 435 including device 11 is interrupt driven by sampler 433. Velocity information determined by unit 433 is fed back to processor 435 improved as described in connection with Figs. 1A and 1B. Software in program memory 61 of Fig. 1A is executed as estimation algorithm process 437. Process 437 provides velocity, position and current information to state controller process 439 of processor 435. A digital output u(n) is supplied as output from state controller 439 to a zero order hold circuit 441 that in turn drives motor 431. The motor is suitably a brushless DC motor with solid state electronic switches associated with core, coils and rotor in block 431. The systems of Figs. 4-6 accommodate shaft encoders, optical and Hall effect rotor position sensing and back emf (counter electromotive force) sensing of position from windings. In Figure 7, robot control system 451 has a motor-driven grasping mechanism 453 at the end of a robot arm 455. Robot arm 455 has a structure with axes of rotation 457.1, 457.2, 457.3 and 457.4 Sensors and high response accurately controllable motors are located on arm 455 at articulation points 459.1, 459.2, 459.3 and 459.4. Numerous such motors and sensors are desirably provided for accurate positioning and utilization of robot arm mechanism 455. However, the numerous sensors and motors place conflicting demands on the system as a whole and on a controller 461. Controller 461 resolves these system demands by inclusion of device 11 of Figs. 1A and 1B and interrupt-driven architecture of system 451. Controller 461 intercommunicates with an I/O interface 463 which provides analog-to-digital and digital-to-analog conversion as well as bit manipulation by parallel logic unit 41 for the robot arm 455. The interface 463 receives position and pressure responses from the navigation motors 467 and sensors associated with robot arm 455 and grasping mechanism 453. Interfacer 463 also supplies control commands through servo amplifiers 465 to the respective motors 467 of robot arm 455. Controller 461 has associated memory 467 with static RAM (SRAM) and programmable read only memory (PROM). Slower peripherals 469 are associated with controller 471 and they are efficiently accommodated by the page boundary sensitive wait state features of controller 461. The controller 461 is also responsive to higher level commands supplied to it by a system manager CPU 473 which is responsive to safety control apparatus 475. System manager 473 communicates with controller 461 via I/O and RS 232 drivers 475. The digital control systems according to the invention make possible performance advantages of precision, speed and economy of control not previously available. For another example, disk drives include information storage disks spun at high speed by spindle motor units. Additional controls called actuators align read and write head elements relative to the information storage disks. The preferred embodiment can even provide a single chip solution for both actuator control and spindle motor control as well as system processing and diagnostic operations. Sophisticated functions are accommodated without excessively burdening controller 461. A digital notch filter can be implemented in controller 461 to cancel mechanical resonances. A state estimator can estimate velocity and current. A Kalman filter reduces sensor noise. Adaptive control compensates for temperature variations and mechanical variations. Device 11 also provides on-chip PWM pulse width modulation outputs for spindle motor speed control. Analogous functions in tape drives, printers, plotters and optical disk systems are readily accommodated. The inventive digital controls provide higher speed, more precise speed control, and faster data access generally in I/O technology at comparable costs, thus advancing the state of the art. In missile guidance systems, the enhanced operational capabilities of the invention provide more accurate guidance of missile systems, thereby reducing the number of expensive missiles required to achieve operational objectives. Furthermore, equivalent performance can be attained with fewer processor chips, thus reducing weight and allowing augmented features and payload enhancements. In Figure 8, a satellite telecommunication system according to the invention has first stations 501 and 503 communicating by a satellite transmission path having a delay of 250 milliseconds. A far end telephone 505 and a near end telephone 507 are respectively connected to earth stations 501 and 503 by hybrids 509 and 511. Hybrids 509 and 511 are delayed eight milliseconds relative to the respective earth stations 501 and 503. Accordingly, echo cancellation is necessary to provide satisfactory telecommunications between far end telephone 505 and near end telephone 507. Moreover, the capability to service numerous telephone conversation circuits at once is necessary. This places an extreme processing burden on telecommunications equipment. In Figure 9, a preferreed embodiment echo canceller 515 is associated with each hybrid such as 511 to improve the transmission of the communications circuit. Not only does device 11 execute echo cancelling algorithms at high speed, but it also economically services more satellite communications circuits per chip. Another system embodiment is an improved modem. In Figure 10, a process diagram of operations in device 11 programmed as a modem transmitter includes a scrambling step 525 followed by an encoding step 527 which provides quadrature digital signals I[nT b ] and Q[nT b ] to interpolation procedures 529 and 531 respectively. Digital modulator computations 533 and 535 multiply the interpolated quadrature signals with prestored constants from read only memory (ROM) that provide trigonometric cosine and sine values respectively. The modulated signals are then summed in a summing step 537. A D/A converter connected to device 11 converts the modulated signals from digital to analog form in a step 539. Gain control by a factor G1 is then performed in modem transmission and sent to a DAA. In Figure 11, a modem receiver using another device 11 receives analog communications signals from the DAA. An analog-to-digital converter A/D 521 digitizes the information for a digital signal processor employing device 11. High rates or digital conversion place heavy burdens on input processing of prior processors. Advantageously, DSP 11 provides zero-overhead interrupt context switching for extremely efficient servicing of interrupts from digitizing elements such as A/D 521 and at the same time has powerful digital signal processing coputational facility for executing modem algorithms. The output of device 11 is supplied to a universal synchronous asynchronous receiver transmitter (USART) 523 which supplies an output D[nT]. In Figure 12, a process diagram of modem reception by the system of Fig. 11 involves automatic gain control by factor G2 upon reception from the DAA supplying a signal s(t) for analog-to-digital conversion at a sampling frequency fs. The digitized signal is s[nTs] and is supplied for digital processing involving first and second bandpass filters implemented by digital filtering steps BPF1 and BPF2 followed by individualized automatic gain control. A demodulation algorithm produces two demodulated signals I'[nTs] and Q'[nTs]. These two signals I' and Q' used for carrier recovery fed back to the demodulation algrithm. Also I' and Q' are supplied to a decision algorithm and operated in response to clock recovery. A decoding process 551 follows the decision algorithm. Decoding 551 is followed by a descrambling algorithm 555 that involves intensive bit manipulation by PLU 41 to recover the input signal d[nT]. As shown in Figure 12, the numerous steps of the modem reception algorithm are advantageously accomplished by a single digital signal processor device 11 by virtue of the intensive numerical computation capabilities and the bit manipulation provided by PLU 41. In Figure 13, computing apparatus 561 incorporating device 11 cooperates with a host computer 563 via an interface 565. High capacity outboard memory 567 is interfaced to computer 561 by interface 569. The computer 561 advantageously supports two-way pulse code modulated (PCM) communication via peripheral latches 571 and 573. Latch 571 is coupled to a serial to parallel converter 575 for reception of PCM communications from external apparatus 577. Computer 561 communicates via latch 573 and a parallel to serial unit 579 to supply a serial PCM data stream to the external apparatus 577. In Figure 14, a video imaging system 601 includes device 11 supported by ROM 603 and RAM 605. Data gathering sensors 607.1 through 607.n feed inputs to a converter 609 which then supplies voluminous digital data to device 11. Figure 14 highlights ALU 21 accumulator 23, multiplier array 53, product register 51 and has an addressing unit including ARAU 123. A control element 615 generally represents decoder PLA 221 and pipeline controller 225 of Figure 1A. On-chip I/O peripherals (not shown) communicate with a bus 617 supplying extraordinarily high quality output to a video display unit 619. Supervisory input and output I/O 621 is also provided to device 11. Owing to the advanced addressing capabilities in device 11, control 615 is operable on command for transferring the product from product register 51 directly to the addressing circuit 123 and bypassing any memory locations during the transfer. Because of the memory mapping, any pair of the computational core-registers of Figs. 1A and 1B are advantageously accessed to accomplish memory-bypass transfers therebetween via data bus 111D, regardless of arrow directions to registers on those Figures. Because the multiplication capabilities of device 11 are utilized in the addressing function, the circuitry establishes an array in the electronic memory 605 wherein the array has entries accessible in the memory with a dimensionality of at least three. The video display 619 displays the output resulting from multi-dimensional array processing by device 11. It is to be understood, of course, that the memory 605 is not in and of itself necessarily multi-dimensional, but that the addressing is rapidly performed by device 11 so that information is accessible on demand as if it were directly accessible by variables respectively representing multiple array dimensions. For example, a three dimensional cubic array having address dimensions A1, A2 and A3 can suitably be addressed according to the equation N 2 x A3 + N x A2 + A1. In a two dimensional array, simple repeated addition according to an index count from register 199 of Fig. 1A is sufficient for addressing purposes. However, to accommodate the third and higher dimensions, the process is considerably expedited by introducing the product capabilities of the multiplier 53. Figures 15 and 16 respectively show function-oriented and hardware block-oriented diagrams of video processing systems according to the invention. Applications for these inventive systems provide new workstations, computer interfaces, television products and high definition television (HDTV) products. In Figure 15, a host computer 631 provides data input to numeric processing by device 11. Video pixel processing operations 633 are followed by memory control operations 635. CRT control functions 637 for the video display are coordinated with the numeric processing 639, pixel processing 633 and memory control 635. The output from memory control 635 operations supplies frame buffer memory 641 and then a shift register 643. Frame buffer memory and shift register 641 and 643 are suitably implemented by a Texas Instruments device TMS 4161. A further shift register 645 supplies video information from shift register 643 to a color palette 647. Color palette 647 drives a display 649 which is controlled by CRT control 637. The color palette 647 is suitably a TMS 34070. In Figure 16, the host 631 supplies signals to a first device 11 operating as a DSP microprocessor 653. DSP 653 is supported by memory 651 including PROM, EPROM and SRAM static memory. Control, address and data information are supplied by two-way communication paths between DSP 653 and a second device 11 operating as a GSP (graphics signal processor) 655. GSP 655 drives both color palette 647 and display interface 657. Interface 657 is further driven by color palette 647. Display CRT 659 is driven by display interface 657. It is to be understood that the devices 11 and the system of Fig. 16 in general is operated at an appropriate clock rate suitable to the functions required. Device 11 is fabricated in micron level and sub-micron embodiments to support processing speeds needed for particular applications. It is contemplated that the demands of high definition television apparatus for increased processing power be met not only by use of higher clock rates but also by the structural improvements of the circuitry disclosed herein. In Figure 17, an automatic speech recognition system according to the invention has a microphone 701, the output of which is sampled by a sample-and-hold (S/H) circuit 703 and then digitally converted by A/D circuit 705. An interrupt-driven fast Fourier transform processor 707 utilizes device 11 and converts the sampled time domain input from microphone 701 into a digital output representative of a frequency spectrum of the sound. This processor 707 is very efficient partly due to the zero-overhead interrupt context switching feature, conditional instructions and auxiliary address registers mapped into memory address space as discussed earlier. Processor 707 provides each spectrum to a speech recognition DSP 709 incorporating a further device 11. Recognition DSP 709 executes any appropriately now known or later developed speech recognition algorithm. For example, in a template matching algorithm, numerous computations involving multiplications, additions and maximum or minimum determinations are executed. The device 11 is ideally suited to rapid execution of such algorithms by virtue of its series maximum/minimum function architecture. Recognition DSP 709 supplies an output to a system bus 711. ROM 713 and RAM 715 support the system efficiently because of the software wait states on page boundaries provided by recognition DSP 709. Output from a speech synthesizer 717 that is responsive to speech recognition DSP 709 is supplied to a loudspeaker or other appropriate transducer 719. System I/O 721 downloads to document production devices 723 such as printers, tapes, hard disks and the like. A video cathode ray tube (CRT) display 725 is fed from bus 711 as described in connection with Figures 15 and 16. A keyboard 727 provides occasional human supervisory input to bus 711. In industrial and other process control applications of speech recognition, a control interface 729 with a further device 11 is connected to bus 711 and in turn supplies outputs for motors, valves and other servomechanical elements 731 in accordance with bit manipulation and the principles and description of Figures 2, 3, 4, 5, 6 and 7 hereinabove. In speech recognition-based digital filter hearing aids, transformed speech from recognition DSP 709 is converted from digital to analog form by a D/A converter 735 and output through a loudspeaker 737. The same chain of blocks 701, 703, 705, 707, 709, 735, 737 is also applicable in telecommunications for speech recognition-based equalization, filtering and bandwidth compression. In advanced speech processing systems, a lexical access processor 739 performs symbolic manipulations on phonetic element representations derived from the output of speech recognition DSP 709 and formulates syllables, words and sentences according to any suitable lexical access algorithm. A top-down processor 741 performs a top-down processing algorithm based on the principle that a resolution of ambiguities in speech transcends the information contained in the acoustic input in some cases. Accordingly, non-acoustic sensors, such as an optical sensor 743 and a pressure sensor 745 are fed to an input system 747 which then interrupt-drives pattern recognition processor 749. Processor 749 directly feeds system bus 711 and also accesses top-down processor 741 for enhanced speech recognition, pattern recognition, and artificial intelligence applications. Device 11 substantially enhances the capabilities of processing at every level of the speech recognition apparatus of Figure 17, e.g., blocks 707, 709, 717, 721, 725, 729, 739, 741, 747 and 749. Figure 18 shows a vocoder-modem system with encryption for secure communications. A telephone 771 communicates in secure mode over a telephone line 773. A DSP microcomputer 773 is connected to telephone 771 for providing serial data to a block 775. Block 775 performs digitizing vocoder functions in a section 777, and encryption processing in block 781. Modem algorithm processing in blocks 779 and 783 is described hereinabove in connection with Figs. 10 and 12. Block 783 suppliea and receives serial data to and from A/D, D/A unit 785. Unit 785 provides analog communication to DAA 787. The substantially enhanced processing features of device 11 of Figs. 1A and 1B make possible a reduction in the number of chips required in block 775 so a cost reduction is made possible in apparatus according to Fig. 18. In some embodiments, more advanced encryption procedures are readily executed by the remarkable processing power of device 11. Accordingly, in Figure 18, device 11 is used either to enhance the functionality of each of the functional blocks or to provide comparable functionality with fewer chips and thus less overall product cost. Three Texas Instruments DSPs are described in the TMS 320C1x User's Guide and TMS 320C2x User's Guide and Third Generation TMS 320 User's Guide. See also coassigned U. S. patent US-A-4 577 282 and US-A-4 713 748. Figure 19 illustrates the operations of the peripheral logic unit 41 of Fig. 1B. The parallel logic unit (PLU) allows the CPU to execute logical operations directly on values stored in memory without affecting any of the registers such as the accumulator in the computation unit 15. The logical operations include setting, clearing or toggling any number of bits in a single instruction. In the preferred embodiment, the PLU accomplishes a read-modify-write instruction in two instruction cycles. Specifically, PLU 41 accesses a location in RAM 25 either on-chip or off-chip, performs a bit manipulation operation on it, and then returns the result to the location in RAM from which the data was obtained. In all of these operations, the accumulator is not affected. The product register is not affected. The accumulator buffer and product register register buffers ACCB and BPR are not affected. Accordingly, time consuming operations which would substantially slow down the computation unit 15 are avoided by the provision of this important parallel logic unit PLU 41. Structurally, the PLU is straight-through logic from its inputs to its outputs which is controlled by decoder PLA 221, enabling and disabling particular gates inside the logic of the PLU 41 in order to accomplish the instructions which are shown below. APL,K and the DBMR or a constant with data memory value CPL,K Compare DBMR or constant with data memory value OPL,K or DBMR or a constant with data memory value SPLK,K store long immediate to data memory location XPL,K XOR DBMR or a constant with data memory value Bit manipulation includes operations of: 1) set a bit; 2) clear a bit; 3) toggle a bit; and 4) test a bit and branch accordingly. The PLU also supports these bit manipulation operations without affecting the contents of any of the CPU registers or status bits. The PLU also executes logic operations on data memory locations with long immediate values. In Figure 19, Part A shows a memory location having an arbitrary number of bits X. In Part B, the SPLK instruction allows any number of bits in a memory word to be written into any memory location. In Part C, the OPL instruction allows any number of bits in a memory word to be set to one without affecting the other bits in the word. In Part D, the APL instruction allows any number of bits in a memory word to be cleared or set to zero, without affecting the other bits in the word. In Part E, the XPL instruction allows any number of bits in a memory word to be toggled without affecting the other bits in the word. In Part F, the CPL instruction compares a given word (e.g., 16 bits) against the contents of an addressed memory location without modifying the addressed memory location. The compare function can also be regarded as a non-destructive exclusive OR (XOR) for a compare on a particular memory location. If the comparison indicates that the given word is equal to the addressed memory word, then a TC bit is set to one. The TC bit is bit 11 of the ST1 register in the registers 85 of Figure 1B. A test of an individual bit is performed by the BIT and BITT instructions. Structurally, the presence of PLU instructions means that decoder PLA 221 of Fig. 1A and the logic of PLU 41 include specific circuitry. When the various PLU instructions are loaded into the instruction register (IR), they are decoded by decoder PLA 221 into signals to enable and disable gates in the logic of PLU 41 so that the operations which the instructions direct are actually executed. To support the dynamic placement of bit patterns, the instructions execute basic bit operations on a memory word with reference to the register value in the dynamic bit manipulation register DBMR 223 instead of using a long immediate value. The DBMR is memory mapped, meaning structurally that there is decoding circuitry 121 (Fig. 1B) which allows addressing of the DBMR 223 from data address bus 111A. A suffix K is appended to the instruction (e.g. APLK) to indicate that the instruction operates on a long immediate instead of DBMR. Absence of the suffix (e.g. APL) indicates that the instruction operates on the DBMR. Selection of the DBMR is accomplished by MUX 225 of Figure 1B which has its select input controlled from decoder PLA 221 with pipeline timing controlled by pipeline controller 225. A long immediate is a value coming from the program data bus as part of an instruction. "Immediate" signifies that the value is coming in from the program data bus. "Long immediate" means that a full word-wide value is being supplied. A long immediate often is obtained from read-only memory (ROM) and thus is not alterable. However, when it is desired to have the logical operation be alterable in an instruction sequence, tho dynamic bit manipulation bit register is provided for that purpose. PLU 41 allows parallel bit manipulation on any location in data memory space. This permits very high efficiency bit manipulation which accommodates the intensive bit manipulation requirements of the control field. Bit manipulation of the invention is readily applicable to automotive control such aa engine control, suspension control, anti-skid braking, and process control, among other applications. Bit manipulations can switch on and off at relay by setting a bit on or off, turn on an engine, speed up an engine, close solenoids and intensify a signal by stepping a gain stage to a motor in servo control. Complicated arithmetic operations which are needed for advanced microcontrol applications execute on device 11 without competition by bit manipulation operations. Further applications of bit manipulation include scrambling in modems. If certain bit patterns fail to supply frequency or phase changes often enough in the modem, it is difficult or impossible to maintain a carrier in phase clock loops and modem receivers. The bit patterns are scrambled to force the bits to change frequently enough. In this way, the baud clock and carrier phase lock loop in the modem are configured so that there is adequate but not excessive energy in each of the digital filters. Scrambling involves XORing operations to a serial bit stream. The PLU 41 does this operation extremely efficiently. Since the other CPU registers of device 11 are not involved in the PLU operations, these registers need not be saved when the PLU is going to execute its instructions. In the case of the scrambling operation, the bits that are XORed into data patterns are a function of other bits so it takes more than one operation to actually execute the XORs that are required in any given baud period. With the parallel logic unit, these operations can be performed concurrently with computatioal operations without having to use the register resources. As thus described, the PLU together with instruction decoder 221 act as an example of a logic circuit, connected to the program bus for receiving instructions and connected to the data bus, for executing logic operations in accordance with at least some of the instructions. The logic operations affect at least one of the data memory locations independently of the electronic computation unit without affecting the accumulator. In some of the instructions, the logic operations include an operation of setting, clearing or toggling particular bits to one in a data word at a selected data memory location without affecting other bits in the data word at the selected data memory location. With the DBMR 223, a further logic circuit improvement is provided so that PLU 41 has a first input connected for receiving data from the data bus, an output for sending data to the data bus and a second input selectively operable to receive a word either from the data bus or program bus. The multiplexer 225 acts as a selectively operable element. For example, the contents of any addressable register or memory location can be stored to the DBMR. When MUX 275 selects the DBMR, then the PLU sends to data bus 111D the contents of a word from data bus 111D modified by a logical operation based on the DBMR such as setting, clearing or toggling. When MUX 225 selects program data bus 101D, a long immediate constant is selected, on which to base the logical operation. Turning now to the subject of interrupt management and context switching, Figure 20 illustrates a system including DSP device 11 having four interfaces 801, 803, 805 and 807. An analog signal from a sensor or transducer is converted by A/D converter 809 into digital form and supplied to DSP 11 through interface 801. When each conversion is complete an interrupt signal INT1-is supplied from analog to digital converter 809 to DSP 11. DSP 11 is supported by internal SRAM 811, by ROM and EPROM 813 and by external memory 815 through interface 803. The output of DSP 11 is supplied to a digital-to-analog converter 817 for output and control purposes via interface 807. An optional host computer 819 is connected to an interrupt input INT2- of DSP 11 and communicates data via interface 805. Other interrupt-based systems herein are shown in Figs. 4, 6, 11, 14 and 17. Operations of device 11 on interrupt or other context change are now discussed. Referring to Figures 1A and 1B, it is noted that several of the registers are drawn with a background rectangle. These registers are TREG2 195, TREG1 81, TREG0 49 , BPR 185, PREG 51, ACC 23, ACCB 31, INDX 143, ARCR 159, ST0, ST1, and PMST. These registers have registers herein called counterpart registers associated with them. Any time an interrupt or other context change occurs, then all of the aforementioned registers are automatically pushed onto a one-deep stack. When there is a return from interrupt or a return from the context change, the same registers are automatically restored by popping the one-deep stack. Advantageously, the interrupt service routines are handled with zero time overhead on the context save or context switching. The registers saved in this way are termed "strategic registers". These are the registers that would be used in an interrupt service routine and in preference to using any different register in their place. If a context save to memory were executed register-by-register to protect the numerous strategic registers, many instruction cycles would be consumed. Furthermore, the relative frequency at which these context save operations occurs depends on the application. In some applications with 100 KHz sampling rates in Figure 20, the frequency of interrupts is very high and thus the cycles of interrupt context save overhead could, without the zero-overhead improvement be substantial. By providing the zero-overhead context switching feature of the preferred embodiment, the interrupt service routine cycle count can be reduced to less than half while obtaining the same functionality. It is advantageous to execute on the order of 100,000 samples per second in multiple channel applications of a DSP or to process a single channel with a very high sampling frequency such as 50 KHz or more. The remarks just made are also applicable to subroutine calls, function calls and other context switches. When an interrupt occurs, status registers are automatically pushed onto the one-deep stack. In support of this feature, there is an additional instruction, return from interrupt (RETI), that automatically pops the stacks to restore the main routine status. The preferred embodiment also has an additional return instruction (RETE) that automatically sets a global interrupt enable bit, thus enabling interrupts while popping the status stack. An instruction designated as delayed return with enable (RETED) protects the three instructions following the return from themselves being interrupted. The preferred embodiment has an interrupt flag register (IFR) mapped into the memory space. The user can read the IFR by software polling to determine active interrupts and can clear interrupts by writing to the IFR. Some applications are next noted in which the zero-overhead context switching feature is believed to be particularly advantageous. Improved disk drives are thus made to be faster and accommodate higher information density with greater acceleration and deceleration and faster read alignment adjustment. The processor can service more feedback points in robotics. In modems, a lower bit error rate due to software polling of interrupts is made possible. Vocoders in their encoding are made to have higher accuracy and less bit error. Missile guidance systems have more accurate control and require fewer processors. Digital cellular phones are similarly improved. The zero-overhead context save feature saves all strategic CPU registers when an interrupt is taken and restores them upon return from the service routine without taking any machine cycle overhead. This frees the interrupt service routine to use all of the CPU resources without affecting the interrupted code. Figure 21 shows a block diagram of device 11 in which the subject matter of Figs. 1A and 1B is shown as the CPU block 13, 15 in Fig. 21. A set of registers are shown broken out of the CPU block and these are the strategic registers which have a one-deep stack as described hereinabove. Figure 21 is useful in discussing the overall system architecture of the semiconductor chip. A set of interrupt trap and vector locations 821 reside in program memory space. When an interrupt routine in program memory 61 of Figs. 1A and 21 is to be executed, the interrupt control logic 231 of Fig. 21 causes the program counter 93 of Fig. 1A to be loaded with appropriate vector in the interrupt locations 821 to branch to the appropriate interrupt service routine. Two core registers IFR and IMR are an interrupt flag register and interrupt mask register respectively. The interrupt flag register gives an indication of which specific interrupts are active. The interrupt mask register is a set of bits by which interrupts to the CPU can be disabled by masking them. For example, if there is an active interrupt among the interrupts INT2-, INT1-, and INTO-, then there will be a corresponding bit in the IFR that is set for a "1". The flag is cleared by taking an interrupt trap by which it will automatically be cleared. Otherwise, the interrupt is cleared by ORing a one into the respective interrupt flag register that clears the interrupt. All active interrupt flags can be cleared at once also. The program and data buses 101 and 111 are diagrammatically combined in Figure 21 and terminate in peripheral ports 831 and 833. Peripheral port 833 provides a parallel interface. Port 831 providos an interface to the TI bus and serial ports for device 11. Figures 22, 23 and 24 illustrate three alternative circuits for accomplishing zero-overhead interrupt context switching. It should be understood all the strategic registers are context-switched in parallel simultaneously, and therefore the representation of all the registers by single flip flops is a diagrammatic technique. In Figures 22 and 23, the upper register and lower register represent the foreground and background rectangles of each of the strategic registers of Figs. 1A and 1B. Fig. 24 shows the parallelism explicitly. In Figure 22, a main register 851 has its data D input selectively supplied by a MUX 853. MUX 853 selectively connects the D input of register 851 to either parallel data lines A or parallel data lines B. Lines B are connected to the Q output of a counterpart register 855. Main register 851 has a set of Q output lines that are respectively connected to corresponding D inputs of the counterpart register 855. In an interpretive example, the arrow marked input for line A represents the results of computations by ALU 21, and accumulator 23 includes registers 851 and 855. The output of main register 851 of Fig. 22 interpreted as accumulator 23 is supplied, for example, to post scaler 181 of Fig. 1A. It should be understood, however, that the register 851 is replicated as many times as required to correspond to each of the strategic registers for which double rectangles are indicated in Figs. 1A and 1B. In Fig. 22, each of the registers 851 and 855 has an output enable (OE) terminal. An OR gate 857 supplies a clock input of main register 851. OR gate 857 has inputs for CPU WRITE and RETE. RETE also feeds a select input of MUX 853 and also the OE output enable terminal of counterpart register 855. Main register 851 has its OE terminal connected to the output of an OR gate 859, the inputs of which are connected to interrupt acknowledge IACK and CPU READ. IACK also clocks counterpart register 855 and all other counterpart registers as indicated by ellipsis. In operation, in the absence of a return from interrupt (RETE low), MUX 853 selects input line A for main register 851. Upon occurrence of CPU WRITE, main register 851 clocks the input from the CPU core into its D input. The CPU accesses the contents of register 851 when a CPU READ occurs at OR gate 859 and activates OE. When an interrupt occurs and is acknowledged (IACK) by device 11, the output Q of register 851 is enabled and the counterpart register 855 is clocked, thereby storing the Q output of main register 851 into register 855. As the interrupt service routine is executed, input lines A continue to be clocked by CPU WRITE into main register 851. When the interrupt is completed, RETE goes low, switching MUX 853 to select lines B and activating line OE of counterpart register 855. RETE also clocks register 851 through OR gate 857 to complete the transfer and restore the main routine information to main register 851. Then upon completion of the return from interrupt RETE goes low reconnecting main register 851 to input lines A via MUX 853. In this way, the context switching is completed with zero overhead. Fig. 22 thus illustrates first and second registers connected to an electronic processor. The registers participate in one processing context (e.g. interrupt or subroutine) while retaining information from another processing context until a return thereto. MUX 853 and the gates 857 and 859 provide an example of a context switching circuit connected to the first and second registers operative to selectively control input and output operations of the registers to and from the electronic processor, depending on the processing context. The electronic processor such as the CPU 13, 15 core of Figs. 1A and 1B is responsive to a context signal such as interrupt INT- and operable in the alternative processing context identified by the context signal. Figure 23 illustrates a bank switching approach to zero overhead context switching. A main register 861 and a counterpart register 863 have their D inputs connected to a demultiplexer DMUX 865. The Q outputs of registers 861 and 863 are connected to respective inputs of a MUX 867. Input from the CPU core is connected to the DMUX 865. Output back to the CPU core is provided from MUX 867. Both select lines from MUXes 865 and 867 are connected to a line which goes active when an interrupt service routine ISR is in progress. In this way, in a main routine, only register 861 is operative. During the interrupt service routine, register 863 is operated while register 861 holds contents to which operations are to return. A pair of AND gates 871 and 873 also act to activate and deactivate registers 861 and 863. A CPU WRITE qualifies an input of each AND gate 871 and 873. The outputs of AND gates 871 and 873 are connected to the clock inputs of registers 863 and 861 respectively. In a main routine with ISR low, register 873 is qualified and CPU WRITE clocks register 861. AND gate 871 is disabled in the main routine. When ISR is high during interrupt, CPU WRITE clocks register 863 via qualified AND gate 871, and AND gate 873 is disabled. In Figure 24, two registers 881 and 883 both have D inputs connected to receive information simultaneously from the processor (e.g. ALU 21). The registers are explicitly replicated in the diagram to illustrate the parallelism of this context switching construction so that, for example, ALU 21 feeds both D inputs of the registers 881 and 883, wherein registers 881 and 883 illustratively act as accumulator ACC 23. Correspondingly, multiplier 53, for example, feeds the P register 51 including registers 891 and 893. (Register 893 is not to be confused with BPR 185 of Fig. 1A). A MUX 895 has its inputs connected respectively to the Q outputs of registers 881 and 883. A MUX 897 has its inputs connected respectively to the Q outputs of registers 891 and 893. The clock inputs of registers 881 and 891 are connected in parallel to an A output of an electronic reversing switch 901. The clock inputs of register 883 and 893 are connected in parallel to a B output of reversing switch 901. Interrupt hardware 903 responds to interrupt acknowledge IACK to produce a low active ISR- output when the interrupt service routine is in progress. Interrupt hardware 903 drives the toggle T input of a flip flop 905. A Q output of flip flop 905 is connected both to a select input of switch 901 and to the select input of both MUXes 895 and 897 as well as MUXes for all of the strategic regisers. A CPU WRITE line is connected to an X input of switch 901 and to an input of an AND gate 907. The low active ISR- output of interrupt hardware 903 is connected to a second input of AND gate 907 the output of which is connected to a Y input of switch 901. In operation, a reset high initializes the set input of flip flop 905 pulling the Q output high and causing MUX 895 to select register 881. Also, switch 901 is thereby caused to connect X to A and Y to B. In a main routine, ISR- is inactive high qualifying AND gate 907. Accordingly, activity on the CPU WRITE line clocks all registers 881, 883, 891 and 893 in a main routine. This means that information from ALU 21 is clocked into both registers 881 and 883 at once and that information from multiplier 53 is clocked into both registers 891 and 893 at once, for example. Then, upon a context change of which the interrupt service routine is an example, ISR- goes low and disables AND gate 907. Subsequent CPU WRITE activity continues to clock registers 881 and 891 for purposes of the interrupt routine, but fails to clock registers 883 and 893, thus storing the contents of the main routine in these two latter registers by inaction. Therefore, a context switch occurs with no time overhead whatever. Upon a return to the original context, such as the main routine, ISR- once again goes high enabling AND gate 907. The low to high transition toggles flip flop 905 causing MUXes 895 and 897 to change state and automatically select registers 883 and 893. This again accomplishes an automatic zero-overhead context switch. Since flip flop 905 is toggled, switch 901 changes state to connect X to B and Y to A. Then activity on CPU write clocks both flip flops at once and registers 883 and 893 are active registers. A further interrupt (ISR- low) disables registers 881 and 891 while registers 883 and 893 remain active. Thus, in Figure 24 there is no main register or counterpart register, but instead the pairs of registers share these functions alternately. In this way, Figure 24 provides a switching circuit connecting the arithmetic logic circuit to both of two registers until an occurrence of the interrupt signal. The switching circuit temporarily disables one of the registers from storing further information from the arithmetic logic unit in response to the interrupt signal. Put another way, this context switching circuit like that of Figs. 22 and 23 is operable to selectively clock first and second registers. Unlike the circuits of Figures 22 and 23, the circuit of Fig. 24 has first and second registers, both having inputs connected to receive information simultaneously from the processor. The processor has a program counter as already discussed and is connected to these registers for executing a first routine and a second routine involving a program counter discontinuity. In Figs. 22-24, a stack is, in effect, associated with a set of registers and the processor is operative upon a task change to the second routine for pushing the contents of the plurality of registers onto the stack. Similarly, upon return from interrupt, the processor pops the stack to allow substantially immediate resumption of the first routine. The second routine can be an interrupt service routine, a software trap, a subroutine, a procedure, a function or any other context changing routine. In Figure 25, a method of operating the circuit of Fig. 24 initializes the Q output of flip flop 905 in a step 911. Operations proceed in a step 913 to operate the output MUXes 895 and 897 based on the state of the Q output of flip flop 905. Then a decision step 915 determines whether the context is to be switched in response to the ISR- signal, for example. If not, operations in a step 917 clock all registers 881, 883, 891 and 893 and loop back to step 913 whence operations continue indefinitely until in step 915 a context switch does occur. In such case, a branch goes from step 915 to a step 919 to clock only the registers selected by the MUXes (e.g. 895 and 897). When return occurs, Q is toggled at flip flop 905 whence operations loop back to step 913 and continue indefinitely as described. Figure 26 is a process diagram for describing the operation of two instructions CRGT and CRLT. These two instructions involve a high speed greater-than and less-than computation which readily computes maximums and minimums when used repeatedly. Operations commence with a start 981 and proceed to determine whether the CRGT or CRLT instruction is present. When this is the case, operations go on to a step 985 to store the ALU 21 to accumulator 23 in Fig. 1A. Then in a step 987, the ALU selects the contents of ACCB 31 via MUX 77 of Fig. 1A. In a step 989, the ALU is coactively operated to compare the contents of accumulator 23 to ACCB 31, by subtraction to obtain the sign of the arithmetic difference, for instance. In step 991, the greater or lesser value depending on the instruction CRGT or CRLT respectively is supplied to ACCB 31 by either storing ACC 23 to ACCB 31 or omitting to do so, depending on the state of the comparison. For example, if ACC 23 has a greater value then ACCB 31 and the instruction is CRGT, then the ACC is stored to ACCB, otherwise not. If ACC 23 has a lesser value then ACCB and the instruction is CRLT, then the ACC is stored to ACCB. In some embodiments, when ACCB already holds the desired value, a transfer writes ACCB into ACC. Subsequently, a test 993 determines whether a series of values is complete. If not, then operations loop back to step 983. If the series is complete in step 993, operations branch to a step 995 to store the maximum or minimum value of the series which has been thus computed. The capacity to speedily compute the maximum of a series of numbers is particularly beneficial in an automatic gain control system in which a multiplier or gain factor is based on a maximum value in order to raise or lower the gain of an input signal so that it can be more effectively processed. Such automatic gain control is used in radio receivers, audio amplifiers, modems and also in control systems utilizing algorithms such as the PID algorithm. PID is a proportional integral and differential feedback control system. Still another application is in pattern recognition. For example, in a voice or recognition system, solid hits of recognition by comparison of pre-stored voice patterns to incoming data are determined by looking at a maximum in a template comparison process. Also, in image processing, edge detection by a processor analyzes intensities in brightness and in color. When intensities rise and then suddenly fall, a maximum is detected which indicates an edge for purposes of image processing. In this way, an arithmetic logic unit, an instruction decoder, an accumulator and an additional register are combined. The additional register is connected to the arithmetic logic unit so that the arithmetic logic unit supplies a first arithmetic value to the accumulator and then supplies to the register in response to a command from the instruction decoder the lesser or greater in value of the contents of the additional register and the contents of the accumulator. Repeated execution of the command upon each of a series of arithmetic values supplied over time to the accumulator supplies the register with a minimum or maximum value in the series of arithmetic values. It is critically important in many real time systems to find a maximum or minimum with as little machine cycle overhead as possible. The problem is compounded when temporary results of the algorithm are stored in accumulators that have more bits than the word width of a data memory location where the current minimum or maximum might be stored. It is also compounded by highly pipelined processors when condition testing requires a branch. Both cases use extra machine cycles. Additional machine cycles may be consumed in setting up the addresses on data transfer operations. In the preferred embodiment, however, the circuit has ACCB 31 be a parallel register of the same bit width as the accumulator ACC 23. When the minimum or maximum function is executed, the processor compares the latest values in the accumulator with the value in the parallel register ACCB and if less than the minimum or greater than the maximum, depending on the instruction, it writes the accumulator value into the parallel register or vice versa. This all executes with a single instruction word in a single machine cycle, thus saving both code space and program execution time. It also requires no memory addressing operations and it does not affect other registers in the ALU. While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description.

Claims: A data processing system comprising: an electronic processor (11) having an instruction set and having an interrupt signal input and being arranged to execute a predetermined series of instructions in response to said interrupt signal; and an electronic processor being responsive to a context signal (SEL) and operable in alternative processing contexts identified by the context signal; a main (851, 861, 881, 891) and a counterpart (855, 863, 883, 893) register connected to said electronic processor, said main register being arranged to participate in a first processing context and one of said main and counterpart registers ( 851, 863, 883, 893) being arranged to participate in a second processing context while the other of said main and counterpart registers (855, 861, 881, 891) retains information from the first processing context until a return thereto; and a context switching circuit (853) connected to said main and counterpart registers operative selectively to control input and output operations of said registers to and from said electronic processor depending on the processing context; characterised in that said context signal is derivable from said interrupt input signal and said instruction set includes an instruction (RETED) which inhibits interrupts during execution of a predetermined number of instructions following said return. A data processing system according to claim 1, wherein the main register (861, 881, 891) alternately acts as the participating register in the first context and then as the non-participating register in a second context while the counterpart register (863, 883, 893) correspondingly acts as the non-participating register in said first context and then acts as the participating register in said second context. A data processing system according to claim 1, wherein said main (851) and counterpart (855) registers are arranged as a stack. A data processing system as claimed in any preceding claim, wherein interrupts are inhibited for three instructions following said return. A data processing system as claimed in any preceding claim, having a plurality of main and counterpart registers.

Inventors: BOUTAUD FREDERIC, EHLIG PETER N, HOLLANDER JAMES F, BOUTAUD, FREDERIC, EHLIG, PETER N., HOLLANDER, JAMES F.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1990
Main classification: G06F9
IPC codes: G06F11, G06F9, G06F7, G01R31