Image processing apparatus

Abstract: An image processing apparatus is disclosed which inputs/outputs an image in which image data items having different information quantity for one pixel are mixed to one another. The information quantity for each of the image data items and information about the I/O positions are stored in a corresponding manner. When data is inputted, data is converted into each of the information quantities in accordance with the input position so as to be stored. When data is outputted, the stored image data is converted into output data in accordance with each of the information quantities. As a result, the memory capacity can be reduced, the flexibility can be improved at the time of use and the memory can be used efficiently.

Description: The present invention relates to an image processing apparatus, and, more particularly, to an image processing apparatus such as a work station for displaying, editing and outputting image data in which multivalued image, binary image and the like are mixed with one another. Hitherto, an apparatus of the type described above has been arranged in such a manner that the number of types of data which can be simultaneously processed is limited to one. When the memory capacity is small, the quantity of information for expressing one pixel is reduced to 1 bit/pixel or 8 bits/pixel or the output resolution deteriorates In the case where the memory capacity is large, the quantity of information for expressing one pixel is arranged to be 24 bits/pixel in which 8 bits are provided for each R, G and B. As a result, the memory for one pixel has been fixed. When data items of a plurality of types are simultaneously processed, a structure must be constituted in such a manner that a plurality of exclusive memories are provided for regions for binary images, regions for multivalued images and regions for color images and the plurality of the exclusive memories are then synthesized. However, the above described conventional structure arises the following problems: Since the memory capacity is insufficient, the quality of the output image may be deteriorated if the quantity of information for expressing one pixel is reduced to, for example, 1 bit/pixel or 8 bits/pixel or the resolution of the output is lowered. Furthermore, a color pallet, a lookup table or a resolution-conversion circuit must be provided. On the contrary, when the quantity of information for expressing one pixel is arranged to be 24 bits/pixel consisting of each 8 bits for R, G and B so as to prepare a memory for one frame, an excessively large capacity memory must be provided, causing the cost of the apparatus to be raised excessively. Furthermore, when multivalued white and black data or binary data the information quantity of which is small is written, the similarly long time is necessary to the case where data having a large information quantity is written. Furthermore, when a plurality of exclusive memories are prepared for the regions for the binary images and the regions for the color images and the plurality of the exclusive memories are synthesized, the memory capacity for each of the data items are undesirably fixed and the number of the types of the data items which can be processed is limited to two or three. As a result, the image data cannot be flexibly processed. As one example of a known apparatus, EP-A-0269746 describes a facsimile transmission system in which different types of image data (for example binary and halftone) contained in a source image are transmitted as separate blocks of image data. At the receiving apparatus, these different types are converted into an output format and written into a single image memory, prior to image output. Accordingly, an object of the present invention is to provide an image processing apparatus the necessary memory capacity of which can be reduced, the flexibility of which can be improved at the time of use and the memory of which can be used efficiently. One aspect of the present invention provides an image processing apparatus comprising: first storage means for storing image data having a plurality of areas at least two of the plurality of areas respectively storing pixel data with respective different quantities of information per pixel; second storage means for storing area information relating to the image data, including for each of the plurality of areas quantity-data specifying a quantity of information representing one pixel and area-data specifying an output position of the storage area; means for determining an outputting order of the stored pixel data in accordance with the specified output positions and a predetermined image data output sequence; memory controlling means for causing the readout of pixel data from said first storage means in accordance with the outputting order determined by said determining means and the quantity-data; and output means for converting the pixel data read out from said first storage means into a predetermined form of output data, in accordance with the quantity-data, and for outputting the output data. The output means may for example include a lookup table for converting the image data read by the reading means into data which corresponds to the output in accordance with information about the type of the image data. According to the thus arranged structure, a variety of image data items can be stored on the same memory with each of the information quantities maintained. Therefore, data having a large quantity of information can be stored with the information quantity maintained. Furthermore, data having small information quantity can be stored without taking an excessively lengthened time so that the data stored can be transmitted in a data format which adapts to the output apparatus. Therefore, the necessary memory capacity can be reduced, satisfactory flexibility can be realized and the memory can be efficiently used. The invention further provides an image processing method comprising the steps of: storing image data having a plurality of areas, at least two of the plurality of areas respectively storing pixel data with respectively different quantities of information per pixel; storing area information of the image data including for each of the plurality of areas quantity-data specifying a quantity of information representing one pixel, and area-data specifying an output position of the area; determining an outputting order to the stored pixel data in accordance with the specified output positions and a predetermined image data output sequence; reading pixel data stored in the image-data storing step in accordance with the outputting order determined in the determining step and the quantity-data; converting the pixel data being read in the reading step into a predetermined form of output data in accordance with the quantity-data; and outputting the output data. Embodiments of the invention store image data items of various bit/pixel in a compact manner so that an excellent quality image is reproduced at high speed at the time of the printing or the displaying. Moreover, image data can be stored in a compact manner in accordance with the characteristics of each of the images on the original image with the quality of the original image maintained. Other and further objects, features and advantages of the invention will be appear more fully from the following description. Fig. 1 is a block diagram which illustrates the structure of a first embodiment of an image processing apparatus according to the present invention; Fig. 2 is a block diagram which illustrates the structure of an output data conversion portion shown in Fig. 1; Fig. 3 specifically illustrates the output data conversion portion shown in Fig. 1; Figs. 4A and 4B illustrate an example of an output obtained according to the present invention; Figs. 5A to 5D illustrates data for each of the portions for obtaining the output shown in Fig. 4A; Fig. 6 is a flow chart which illustrates the procedure of the output processing performed by the image processing apparatus according to the present invention; Fig. 7 is a block diagram which illustrates a second embodiment of the image processing apparatus according to the present invention; Fig. 8 is a block diagram which illustrates the data conversion circuit 180 shown in Fig. 7; Fig. 9 specifically illustrates the data conversion circuit shown in Fig. 7; Fig. 10 is a flow chart which illustrates the procedure of processing performed by the image processing apparatus shown in Fig. 7; Fig. 11 is a flow chart which illustrates the processing of inputting image data; Fig. 12 illustrates the structure of a full color printer 200 connected to the image processing apparatus according to the second embodiment; and Figs. 13 and 14 are block diagrams which illustrate a conventional image processing apparatus. Preferred embodiments of the present invention will now be described with reference to the drawings. First, an example of a conventional image processing apparatus will be described with reference to Fig. 13. Referring to Fig. 13, reference numeral 1 represents a CPU for controlling the overall body of the apparatus. Reference numeral 2 represents a main memory for temporarily storing a program or serving as a working region and 3 represents a communication interface (to be abbreviated to "i/f" hereinafter) for establishing a communication with a LAN. Reference numeral 4 represents a key board through which a character code or the like is inputted and 5 represents a mouse for instructing the position on the display. Reference numeral 6 represents an input device interface (to be abbreviated to "input device i/f" hereinafter) for controlling an input device such as the key board 4, the mouse 5 or the like. Reference numeral 7 represents a system bus through which address data, a control signal and the like passes and 8 represents a CRT display serving as a display device. Reference numeral 9 represents a video RAM (to be abbreviated to "VRAM" hereinafter), 10 represents a floppy disk drive (to be abbreviated to "FD" hereinafter) and 11 represents a hard disk drive (to be abbreviated to "HD" hereinafter). Reference numeral 12 represents a disk interface (to be described to "DISK i/f) for establishing a communication with the FD 10 and that with the HD 11. Reference numeral 19 represents an output interface (to be abbreviated to "output device i/f) for establishing a connection with an output apparatus such as a printer. Reference numeral 20 represents the output apparatus such as a printer. Reference numeral 49 represents an image memory for storing image data, 50 represents a memory controller for controlling the image memory 49 and 51 represents an image controller board. Hitherto, as an output to a white and black multivalued printer, binary data "0" is simply converted into 00 H and "1" is also simply converted into FF H or the image memories 49 are held by the number which corresponds to the number of the multivalued planes so as to be stored as multivalued data. As an output to a color printer, 7-color expression of R, G, B, Y, M, C and Bk is realized with the memory for four planes held or the memory of the number of the planes for all of the frames is held. That is, the number of bits for one pixel of data developed in the image memory 49 is common to any place in a frame. Therefore, in the case where there is provided only a memory for binary data, the gradation expression of an image cannot be performed. As a result, the obtainable image quality has been insufficient. On the other hand, in the case where there are provided the memories for the number of the plane, data corresponding to the binary data must be processed as multivalued data. Therefore, an excessively long time takes to reload the memory or the like since one bit data is expressed by a plurality of bits. That is, in the case where there is provided only a memory for one plane, the cost can be reduced. However, the image quality is insufficient. On the contrary, in the case where there are provided memories for a plurality of planes, an excellent image quality can be obtained. However, the cost cannot be reduced. <First Structural Example> As shown in Fig. 1, according to this embodiment, a circuit (for example, an access address control circuit 17) for controlling data is provided in the vicinity of the memory. Furthermore, a selector 47 and a lookup table 48 (to be abbreviated to "LUT" hereinafter) as shown in Fig. 2 are provided. As a result, data of different type can be processed in an output frame depending upon the place. Referring to Fig. 1, the same elements as those shown in Fig. 13 are given the same reference numerals. This embodiment is characterized by an image controller board 1 comprising an extensible image memory 14 for storing image data, a memory controller 15, a type/position information register 16 for determining the type and the output position of the image data, an access address control circuit 17 for determining the type of data to be outputted, an output data conversion circuit 18 for converting data supplied from the image memory 14 into a data format which is able to correspond to the output apparatus depending upon the type of the data and the output apparatus i/f 19 which is the interface for establishing a connection with the output apparatus. Fig. 2 is a block diagram which illustrates the structure of the output data conversion circuit 18 shown in Fig. 1. Referring to the drawing, reference numeral 46 represents a latch circuit for temporarily storing data supplied from the image memory 14. Reference numeral 47 represents a selector for selecting necessary bits from the supplied 32 bits depending upon the type of the data. Reference numeral 48 represents an LUT serving as a color pallet for converting data supplied from the selector 47 into data adapted to the output apparatus i/f 19. Reference numeral 62 represents a control signal generating circuit. Fig. 3 further schematically illustrates the block shown in Fig. 2, where reference numerals 52 to 55 represent latch circuits for latching 32 bits data supplied from the image memory 14. Reference numerals 56 to 58 represent selectors for selecting 8 bits from the 32 bits data and 59 represents an LUT for outputting data corresponding to red. Reference numeral 60 represents an LUT for outputting data corresponding to green and 61 represents an LUT for outputting data corresponding to blue. The operation of this embodiment will be described with reference to Fig. 4A. Referring to Fig. 4A, reference numeral 21 represents 4 bits/pixel data capable of expressing 16 gradations in white and black. Reference numeral 22 represents white and black binary 1 bit/pixel data and 23 represents 24 bits/pixel color data capable of expressing 16,700,000 colors in 256 gradations in each R, G and B. Reference numeral 24 represents 8 bits/pixel pallet color data capable of simultaneously expressing 256 colors of 16,700,000 colors by using a color pallet. Fig. 4B illustrates the position and the size of each portion of the image shown in Fig. 4A. Referring to the drawing, a gray character portion 21 starts a pixel address (X0, Y0) on the display frame (that is, the original to be read or the print sheet), the gray character portion 21 having a size of W0 x H0. The other portions 22 to 24 are similarly arranged. A white and black portion 22 is sectioned into four rectangular blocks for the convenience in the processing. Fig. 5A illustrates the state where the each of the images shown in Fig. 4A is stored by the image memory 14. Referring to the drawing, an area 25 starting at address #a0 on the image memory 14 stores 4 bits/pixel gray image data a ○, an area 26 starting at address #b0 stores 1 bit/pixel white and black binary image data b ○, an area 27 starting at address #c0 stores 24 bits/pixel full color image data c ○, an area 28 starting at address #d0 stores 8 bits/pixel pallet color image data d ○. An area 29 starting at address #e0 is a vacant space area. The area 26 for the white and black binary image data b ○ is sectioned into four areas each of which starts at address #b0, #b1, #b2 and #b3. Thus, the image memory 14 according to this embodiment does not store image data corresponding to the marginal portion of Fig. 4A. Fig. 5B is a schematic view which illustrates the state in which the type and position information register 16 stores data. Referring to the drawing, reference numeral 30 represents the type of image data a ○, 31 represents the I/O output pixel position of image data a ○, 32 represents the type of image data b ○, 33 the I/O output pixel position of image data b ○, 34 represents the type of image data c ○, 35 represents the I/O output pixel position of image data c ○, 36 represents the type of image data d ○ and 37 represents the I/O output pixel position of image data d ○. Fig. 5B schematically illustrates the contents of the storage in the type and position information register 16. Referring to the drawing, the type of image data a ○ is 2, the I/O output pixel position for the read original or the printing sheet is an area starting from (X0, Y0) and having a size (W0, H0). The type of the image data b ○ is 0 and the I/O pixel position and size is an area (X1, Y1) and (W1, H1) and an area (X2, Y2) and (W2, H2), an area (X3, Y3) and (W3, H3) and an area(X4, Y4) and (W4, H4). The other image data items are similarly arranged. Fig. 5C illustrates the code table for the type of the image data. Referring to the drawing, type 0 corresponds to 1 bit/pixel and type 2 corresponds to 4 bits/pixel. The other types are similarly arranged. According to an example of the output shown in Fig. 4A, data for a character, a photograph, a graph and a figure is, as actual data, written in the image memory 14 as shown in Fig. 5A. Data concerned with the type of each of the actual data items and the output position is expressed by (X0, Y0) to (X6, Y6), W0 to W6, H0 to H6 and the like as shown in Fig. 4B so as to be written in the type/position information register 16 as shown in Fig. 5B. As described above, the type and the position has been specified by means of software. Therefore, data is read out from the corresponding address by hardware at the time of the output in accordance with the output position so as to be transmitted after each of the data format has been converted into the data format for the output apparatus. At this time, the address corresponding to the output position is generated by the access address control circuit 17. Fig. 5D illustrates, corresponding to Fig. 4A, the address and the type of data corresponding to the output position and transmitted from the access address control circuit 17. The memory controller 15 controls the action of reading data from the memory. The output data conversion circuit 18 converts each of the data formats into the data formats for the output apparatus. The output apparatus i/f sends/receives a signal to and from the output apparatus. <Processing procedure of the First Example> The operation will be described with reference to a flow chart shown in Fig. 6. Fig. 6 is a flow chart which illustrates the printing process according to this embodiment. Referring to the drawing, in step S38, an operator makes a layout or inputs data on the CRT frame for the purpose of obtaining a desired printing processing for each of the images. In accordance with the thus made layout, information for the type of each of the image data and position of the output pixel is inputted. As a result, CPU 1 develops the character data or the like in such a manner that that code information is made dot data and image data is made a format (a format packing in 1 bit/pixel, 4 bits/pixel or the like) depending upon the type. Furthermore, information for the type of each of image data, the position at which output to the output apparatus starts and size is written in the type and position information register 16. In step S39, it is determined whether or not the above-described setting has been ended. It it has been ended, the flow advances to step S40 in which a print command is issued to the output apparatus 20. Furthermore, a start flag for the access address control circuit 17 is stood or the like so that the output operation is started. In step S41, the access address control circuit 17 makes a reference to the contents of the type and position information register 16 relating to the output pixel position in the output apparatus 20. Furthermore, it determines the address of the image data to be read from the image memory 14. In step S42, it is determined whether or not there Is image data to be read from the image memory 14. Then, the relationship between the output pixel position and the read address of the image memory 14 in the access address control circuit 17 will be described with reference to Fig. 6. The scanning by the output apparatus 20 is performed from left to the right of the frame as the main scanning until the scanning reaches the right end portion. Then, the scanning is shift to the left end portion of the line which is lowered by one line so that the lines are mainly downwards scanned from the upper portion. Therefore, the first output pixel position in the output apparatus 20 is (0, 0). In the case of the image shown in Fig. 4A, the front portion of the paper sheet, that is, the area starting at the output pixel position (0,0) is a marginal portion. That is, the area starting at the output pixel position (0, 0) shown in Fig. 5D is arranged to have no read address. That is, there is no corresponding information in both the image memory 14 and the type and position information register 16. Furthermore, the type of the image data is 0 (1 bit/pixel). Therefore, the flow advances to step S45 in which a fact that output data is 0 (no data) is notified to the output apparatus i/f 19. In step S46, the output apparatus i/f 19 transmits a signal (for example, Nu11) which corresponds to the marginal space in synchronization with the output apparatus 20 with monitoring the image data output pixel position. In step S47, it is determined whether or not the output of image data for one frame has been ended. If it has not been ended, the flow advances to step S48 In which the output apparatus i/f 19 request the access address control circuit 17 for the next image data. Thus, when the output pixel position reaches in front of (X0, Y0), the access address control circuit makes a reference to the contents of the type and position information register 16 in step S4. As a result, a coincidence with the output pixel position information is obtained. Then, the read address #a0 of the image memory 14 is transmitted from the table shown in Fig. 5D. Furthermore, image data type 2 is transmitted. Since there is image data to be printed in the determination made in step S42, the flow advances to step S43 in which the memory controller 15 read image data from the address #a0 of the image memory 14 so as to supply it to the data conversion circuit 18. In step S44, the data conversion circuit 18 has been previously notified a fact that the type = 2 (4 bits/pixel) as the type of the image data from the access address control circuit 17. Therefore, it supplies image data for 32 bits latched by the latch circuit 46 to the selector 47. The selector 47 successively selects (unpack) each 4 bits of the image data for the 32 bits so as to make a reference to the lookup table 48 in a unit of 4 bits for one pixel clock. Thus, the lookup table 48 supplies 24 bits/pixel RGB image data corresponding to each 4 bits to the output apparatus i/f 19. In step S46, the output apparatus i/f 19 transmits the RGB image data supplied from the data conversion circuit 18 in synchronization with a timing signal of the output position 20. Thus the printing process is advanced until the output pixel position reaches (X0 + W0, Y0). At this time, the read address becomes zero from the relationship shown in Fig. 6, and the type also becomes zero. Furthermore, when the output pixel position becomes (X0, Y0 + 10, the read address of the image memory becomes # (a0 + W0/2) and the type becomes 2. That is, since the portion of the image memory 14 is 4 bits/pixel, the read address moves forward by W0/2 with respect to the increase WO of the output pixel position. The above-described operations from S41 to 46 are repeated until those for one frame is ended. <Specific Example of the Output Data Conversion Circuit> The output data conversion circuit 18 will be described more specifically with reference to Fig. 3. The 32-bit data read out from the image memory 14 is latched by the latch circuits 52 to 55 by 8 bits respectively. The outputs from the latch circuits 52 to 55 are supplied to the selectors 56 to 58 in which each 8 bits is selected. The way of the selection will be described with reference to the case where type = 6 shown in Fig. 5C. In response to a command for each 8 bits for R, G and b and supplied from the control signal generating circuit 62, the selector 56 selects the output from the latch circuit 52, the selector 57 selects the output from the latch 53 and the selector 58 selects the output from the latch 54. Each 8 bits thus selected is respectively supplied to the LUTs 59, 60 and 61. Then, the selector 56 selects the output from the latch 55, the selector 57 selects the output from the latch 52 and the selector 58 selects the output from the latch 53. The above-described operation is repeated. In the case where type = 2, all of the selectors 56, 57 and 58 respectively selects the output from the latch 52. That is, the outputs from the selectors 56, 57 and 58 comprise the same data. The LUTs 59, 60 and 61 first respectively make a reference with the upper 4 bit of the supplied 8 bits so that data for red corresponding to the above-described 4 bits is transmitted from the LUT 59, data for green is transmitted from the LUT 60 and data for blue is transmitted from the LUT 61. Then, a reference to the lower bits of the 8 bits is made so that the corresponding data for red, green and blue is transmitted from each of the LUTs 59, 60 and 61. As for other types of data, the similar operation is performed. That is, when the number of the bits necessary to express data for one pixel is 8 or less, the same data is supplied to the LUTs 59, 60 and 61 so as to the number of bits to be subjected to the reference is made correspond to the type of the data. When the number of the bits necessary to express data for one pixel is 8 or more, the selectors 56, 57 and 58 successively change the data to be selected. Although three LUTs are employed according to this embodiment, another structure may be employed in which one LUT which receives 24 bits and transmits 8 bits is provided. The present invention is not limited to the above-described number of the bits. Furthermore, the present invention is not limited to the above-described output apparatus arranged to act on the basis of red, green and blue for realizing a color image. It may be replaced by an output apparatus arranged to act on the basis of Y, M, C and Bk or an apparatus arranged to act on the basis of a white and black multivalued method. As described above, a variety of the image data can be stored on the same memory with the quantity of information maintained as it is. Therefore, data of a large quantity of information can be stored without a fear of lacking for the necessary information. Furthermore, a problem, taken place in that an excessively long time takes when data of a small quantity is written, can be overcome. Therefore, an output in a data format which adapts the output apparatus can be realized. As a result, an excellent quality output image can be obtained with a reduced memory capacity. According to this embodiment, an image processing apparatus the memory capacity of which can be reduced and which exhibits a structural flexibility and an excellent efficiency in use of the memory thereof. Fig. 14 is another block diagram which illustrates a conventional image processing apparatus. Referring to the drawing, reference numeral 1 represents a CPU for controlling the overall body of the apparatus and 2 represents a main memory for storing the program for the CPU 1 or serving as a work area used by the CPU 1. Reference numeral 3 represents a communication interface (a communication i/f) for establishing a communication with a local area network (LAN) such an either net. Reference numeral 4 represents a key board through which a character code or the like is inputted and 5 represents a pointing device (PD) for instructing the position on the display frame. Reference numeral 6 represents an input device interface for establishing the communication between the key board or the PD 5 with the CPU 1. Reference numeral 7 represents a system bus for the CPU 1 and 8 represents a CRT display device (CRT) for displaying image data. Reference numeral 9 represents a video RAM (VRAM) for storing video data to be displayed on the CRT display device 8. Reference numeral 10 represents a floppy disk drive (FD) for storing a user file and 11 represents a hard disk drive (HD) for storing the system file. Reference numeral 12 represents a disk interface (a disk i/f) for connecting the FD 10 or HD 11 to the CPU 1. Reference numeral 20 represents an output apparatus such as a printer, and 520 represents an input apparatus such as a scanner. Reference numeral 190 represents an I/O device interface (I/O device i/f) connects the input apparatus 520 and the output apparatus 20 to this system. Reference numeral 49 represents an image memory for storing image data, 50 represents a memory controller for controlling reading and writing to and from the image memory 49 and 51 represents an image controller board. According to the thus constituted conventional apparatus, in the case where the printer 20 is an 8 bits white, black and gray printer, bit 0 has been converted into multivalued image data 00 H and also bit 1 has been converted into multivalued image data FF H so as to be developed on the image memory 49 regardless of a fact that the data for the image is 1 bit/pixel character pattern data. In the case where a scanner 520 is an 8 bits white, black and gray scanner, multivalued image data 00 H to FF H , read by the scanner, are, as it is, stored in the image memory 49 regardless of a fact that the original image is constituted by white and black characters. As described above, according to the conventional apparatus, when once the number of the bits for one pixel is determined in the system, the number of the bits for the pixel data to be stored in the image memory 49 is not changed regardless of the fact that the data is binary image data, multivalued image data or color image data. Therefore, the image memory cannot be used efficiently and the accessing operation to the image memory cannot be performed efficiently. <Second Structural Example> Fig. 7 is a block diagram which illustrates the structure of the image processing apparatus according to another embodiment of the present invention. The same elements as those shown in Figs. 1, 13 and 14 are given the same reference numerals and their descriptions are omitted here. Referring to the drawing, reference numeral 2 represents a main memory for storing programs for overall body of the print processing shown in Fig.10, the print processing shown in Fig. 6 and the scanner reading processing shown in Fig. 11. Reference numeral 14 represents an image memory for storing a variety of image data such as 1 bit/pixel bit map data, 4 bits/pixel gray data, full color data of 8 bits for each of R, G and B in such a manner that the variety of the image data are efficiently mixed with one another. The memory capacity of the image memory 14 can be enlarged or reduced if necessary. Reference numeral 15 represents a memory controller for controlling the reading and writing data to and from the image memory 14. Reference numeral 16 represents a type/position information register for storing information for the type of the image data to be stored in each portion of the image memory 14 (that is, information corresponding to the number of bits for one pixel) with making it correspond to information for the start position on the original, printing paper or the display frame for the image data (that is, information for the output pixel position for the recording material or the frame) and for the size. Reference numeral 180 represents a data conversion circuit for converting image data read from the image memory 14 into image data (8 bits/pixel RGB data or the like) in the format which can adapt to the output apparatus 20 in accordance with information for the type (1 bit/pixel, 4 bits/pixel or the like). The data conversion circuit 180 converts, as an alternative, image data (8 bits/pixel RGB data or the like) supplied from the input apparatus 520 into image data the memory development format of which corresponds to information for the type (1 bit/pixel, 4 bits/pixel or the like). Reference numeral 190 represents an I/O apparatus interface (an I/O apparatus i/f) for sending and receiving image data in a suitable format to and from the I/O apparatuses 520 and 20. Furthermore, the I/O apparatus interface 190 receives a variety of operation timing signals (a VSYNC signal, an HSYNK signal, a pixel clock signal or the like) supplied from the I/O apparatuses 520 and 20 so as to transmit a variety of synchronizing signals for the purpose of detecting the present position of the pixel of the original image to be read or the present position of the pixel on the printing paper to be printed. Reference numeral 17 represents an access address control signal for controlling the determination of the type and the address of the image data to be read from the image memory 14 or determination of the type and the address of the image data to be written on the image memory 14. Reference numeral 13 represents an image interface board on which the above-described structures 14 to 17, 180 and 190. <Example of the Structure of the Output Apparatus> As the output apparatus 20 to be connected to the image processing apparatus according to this embodiment, the structure of a full color printer will be described with reference to Fig. 12. Referring to the drawing, reference numeral 701 represents a data conversion circuit (DCNV) for converting R, G and B data supplied from the I/O apparatus i/f 190 into analog image signals Y, M, C and Bk. Reference numeral 778 represents a pulse width modulation (PWM) circuit for forming a binary image signal the pulse width of which has been modulated by making a comparison between the analog image signal with a triangular signal with a predetermined period. The binary image signal is supplied to an ensuing laser output portion 711 so that a laser diode is ON/OFF modulated. As a result, a gradation image can be formed. Reference numeral 711 represents a beam scanner comprising a laser output portion for converting the binary image signal supplied from the PWM circuit 778, a polygonal mirror 712 of a polygonal body (for example, an octahedron), a motor (omitted from illustration) for rotating the polygonal mirror 712 at high speed and an f/ϑ lens (an imaging lens) 713. Reference numeral 714 represents a reflecting mirror for changing the optical passage through which the laser beam travels. Reference numeral 715 represents a photosensitive drum. As a result of the thus constituted structure, the laser beam emitted from the laser output portion is reflected by the polygonal mirror 712 before it passes through the f/ϑ lens 713 and the mirror 714 so as to linearly scan (raster scan) the surface of the photosensitive drum 715. As a result, a latent image which correspond to the image data is formed. Furthermore, reference numeral 717 represents a primary charger, 718 represents a full surface exposure lamp, 723 represents a cleaner portion for recovering residual toner which has not be transferred and 724 represents a pre-transference charger. The above-described elements are disposed around the photosensitive drum 715. Reference numeral 726 represents a developing machine unit for developing a static latent image formed on the surface of the photosensitive drum 715. Reference numerals 731Y, 731M, 731C and 731Bk respectively represent developing sleeves which come in contact with the photosensitive drum 715 so as to perform the direct development. Reference numerals 730Y, 730M, 730C and 730Bk respectively represent toner hoppers for accumulating spare toner for each of the colors. Reference numeral 732 represents a screw for conveying the developer for each of the colors. A developing machine unit 726 is constituted by the above-described sleeves 731Y to 731Bk, the toner hoppers 730Y to 703Bk and the screw 732. The above-described elements are disposed around the rotational axis P of the developing machine unit. As a result, when a yellow toner image is formed, the development operation with the yellow toner is performed at the position as shown in the drawing. When a magenta toner image is formed, the develoling sleeve 731M in the magenta developing machine is moved to a position at which it comes in contact with the photosensitive body 715 by rotating the developing machine unit 726 relative to the axis P. The development of the cyane toner image and that of the black toner image are similarly performed. Reference numeral 716 represents a transferring drum for transferring the toner image formed on the photosensitive drum 715 and 719 represents an actuator plate for detecting the position to which the transferring drum 716 has been moved. Reference numeral 720 represents a position sensor which approaches the actuator plate 719 so as to detect the movement of the transferring drum 716 to the home position. Reference numeral 725 represents a transferring drum cleaner, 727 represents a paper holding roller, 728 represents an electricity remover and 729 represents a transference charger. The above-described elements 719, 720, 725, 727 and 729 are disposed around the transferring roller 716. Reference numerals 735 and 736 represent paper feeding cassette for accommodating paper sheets 791. Reference numerals 737 and 738 represent paper supply rollers for feeding the paper sheets 791 from the cassettes 735 and 736. Reference numerals 739, 740 and 741 respectively represent timing rollers for arranging timing for the supply and the conveyance of the paper sheets 791. The paper sheet 791 which has passed through the above-described elements is guided by a paper guide 749, as a result of which it is wound around the transferring drum 716 with the front end portion thereof held by a gripper, to be described later. Then, the process is shifted to the image forming operation. Reference numeral 550 represents a motor which rotates the photosensitive drum 715 and the transferring drum 716 in a synchronization manner. Reference numeral 750 represents a removing claw for removing the paper sheet 791 from the transferring drum 716 after the image has been formed. Reference numeral 742 represents a conveyance belt for conveying the paper sheet 791 which has been removed from the transferring drum 716. Reference numeral 743 represents an image fixing portion for fixing the image on the paper sheet 791 which has been conveyed by the conveyance belt 742. The image fixing portion 743 comprises a pair of thermal pressure rollers 744 and 745. <Example of the Structure of the Data Conversion Circuit> Fig. 8 is a block diagram which illustrates the data conversion circuit 180 according to this embodiment. Referring to the drawing, the image memory 14 is able to access to data for 32 bits at a stretch. Reference numeral 46 represents the latch circuit for temporarily latching image data read out from the image memory 14 at the time of outputting the image, while the same latches image data to be written in the image memory 14 at the time of inputting the image. Reference numeral 47 represents the selector for selecting image data of the number of bits corresponding to the type (1 bit/pixel, 4 bits/pixel or the like) of the image data from supplied 32 bits for the purpose of successively transmitting the selected image data. Reference numeral 48 represents the lookup table (LUT) for converting each of the image data (1 bit/pixel, 4 bits/pixel or the like) supplied from the selector 47 into image data (8 bits/pixel RGB image data) in the form adaptable to the output apparatus 20. That is, the lookup table 48 serves as a color pallet similarly to the first embodiment. Reference numeral 530 represents a lookup table (LUT) for converting image data (8 bits/pixel RGB image data) supplied from the input apparatus 520 into image data (1 bit/pixel, 4 bits/pixel or the like) in the storage format which corresponds to the predetermined type. Reference numeral 540 represents a selector/shifter for collectively transmitting image data supplied from the lookup table 530 in a unit of 32 bits. Reference numeral 550 represents a control signal generating circuit for generating a variety of control signals such as a signal for converting data. Fig. 9 further specifically illustrates the block shown in Fig. 8. The latch circuits shown in Fig. 3 may be employed. In this case, a selector for selecting I/O must be provided. 8 bits data for R, G and B supplied from the input apparatus 520 are converted by the LUT 70, 71 and 72 corresponding to the type of the data shown in Fig. 5C. Then, the thus converted data is transmitted to 8 bits registers 73 and 76 each of which is constituted by two 4 bit register and to a shift register 75. According to this embodiment, since the lightness of white and black corresponds to the density of green (G), white and black data of types 0 to 3, 5 or the like store data for green. However, the data may be extracted from the total relationship among R, G and B although the circuit becomes considerably complicated. The way of the selection will be described. In the case where type = 6 shown in Fig. 5C, the output from the MUX 77 which is the same as the output from the LUT 70 is supplied to the input of the latch circuit 52, the output from the MUX 78 which is the same as the output from the LUT 71 is supplied to the input of the latch circuit 53 and the output from the MUX 79 which is the same as the output from the LUT 72 is supplied to the input of the latch circuit 53 in response to a command issued by the control signal generating circuit 62 for 8 bits for R, G and B. Then, the output from the MUX 77 is supplied to the latch 55 so that 32 bits data is written in the image memory. Then, the output from the MUX 78 is supplied to the input of the latch 52 and the output from the MUX 79 is supplied to the input of the latch 53 after respective selection have been performed. In the case where type = 2, only the output from the LUT 71 is latched in the shift register 75, and then 4 bits are shifted so as to shift the lower 4 bits to the shift register 74 so as to be coupled with the lower 4 bits of the output from the LUT 71. As a result, 8 bit data is formed so as to be written in the image memory with successively latched, by the MUX 78, in the sequential order: the latch 52, 53, 54, 55 and 52. In the case where type = 4, the coupling of the lower 4 bits is performed by the registers 73 and 76. Although no description is made about black (Bk) formed by removing the base color in Fig. 9. However, a known base color removal operation is performed in the case where type = 7 so that the forming of Bk is latched by the latch 55. As for data of other types, a similar operation is performed. When the number of bits necessary to express data for one pixel is 8 or less, the coupling is performed by the registers 73 and 75 or the shift registers 74 and 75 so as to make the number of bits correspond to the type of the data. In the case where the number of bits necessary to express data for one pixel is larger than 8, data selected by each of the MUXs 77, 78 and 79 is successively changed. <Processing procedure of the Second Example> Fig. 10 illustrates the overall processing procedure of the structure shown in Fig. 7. Referring to Fig. 10, an image input processing, to be described later, is performed in step S100 so as to input the image to the image memory 14. Then, the image is, in step S200, transmitted to the printer in accordance with the procedure shown in Fig. 6. Fig. 11 is a flow chart for the image data input processing. Referring to the drawing, step S21 is a step in which an operator determines a desired layout depending upon the configuration of the original sentence, figure and image to be read and set the position of the input pixel and the type of the image data for the block for each of the images to be inputted by the input apparatus 520 to the type/position information register 16. In step S22, it is determined whether or not the setting has been completed. It the determination has been completed, the flow advances to step S23 in which the input apparatus 520 and the I/O apparatus i/f 190 are started. In step S24, the I/O apparatus i/f 190 receives 24 bits/pixel RGB image data in synchronization with the input apparatus 520. In step S25, the data conversion circuit 180 converts data for image to be read into image data (1 bit/pixel, 4 bits/pixel or the like) in the corresponding format in accordance with information for the type of the image data. In step S26, the access address control circuit 17 makes a reference to the contents of the type/position information register 16 so as to determine the address for writing in the image memory 14 from the relationship shown in Fig. 5D. In step S27, the memory controller 15 writes the thus converted image data in the determined address in the image memory 14. In step S28, it is determined whether or not the writing for one frame has been completed. If it has not been completed, the flow advances to step S29 in which the I/O apparatus i/f 190 request the access address control circuit 17 to write the next image data. The processings from step S24 to step S27 is repeated until the processing for one frame is completed. The present invention is not limited to. the above-described various bits/pixel. Although the image data for R, G and B is employed, it may be Y, M, C and Bk. Alternatively, the half tone image may be formed by white and black multivalued data. As described above, according to the present invention, a variety of image data may be efficiently mixed with one another on the same memory without lacking for the respective information quantity. Therefore, the storage efficiency can be significantly improved. Furthermore, the necessity of forming the memory capacity by data having the largest quantity of information for one frame can be eliminated. The memory can be efficiently used by changing the type of data in accordance with the overall memory capacity. Furthermore, the restriction from the data format of the I/O apparatus can be eliminated. Although the invention has been described in its preferred form with a certain degree of particularly, it is understood that the present disclosure of the preferred form has been changed in the details of construction and the combination and arrangement of parts may be resorted to without departing from the scope of the invention as hereinafter claimed.

Claims: An image processing apparatus comprising: first storage means (14) for storing image data having a plurality of areas (25, 29) at least two of the plurality of areas (25, 26) storing pixel data with respective different quantities of information per pixel; second storage means (16) for storing area information relating to the image data, including for each of the plurality of areas quantity-data specifying a quantity of information representing one pixel and area-data specifying an output position of the storage area; means (17) for determining an outputting order of the stored pixel data in accordance with the specified output positions and a predetermined image data output sequence; memory controlling means (15) for causing the readout of pixel data from said first storage means in accordance with the outputting order determined by said determining means and the quantity-data; and output means (18, 19) for converting the pixel data read out from said first storage means into a predetermined form of output data, in accordance with the quantity-data, and for outputting the output data. An image processing apparatus according to claim 1, wherein said output means (18) includes a lookup table (48) for converting said pixel data read by said reading means into data which corresponds to the output in accordance with information about a type of image data in each storage area. An image processing apparatus to claim 1, wherein said image data includes binary data, and plural-bit gradation data or color data which expresses each color component by a plurality of bits per pixel. An image processing method comprising the steps of: storing (S27) image data having a plurality of areas, at least two of the plurality of areas storing pixel data with respective different quantities of information per pixel; storing (S26) area information of the image data including for each of the plurality of areas quantity-data specifying a quantity of information representing one pixel, and area-data specifying an output position of the area; determining (S41) an outputting order for the stored pixel data in accordance with the specified output positions and a predetermined image data output sequence; reading (S43) pixel data stored in the image-data storing step in accordance with the outputting order determined in the determining step and the quantity-data; converting (S44) the pixel data being read in the reading step into a predetermined form of output data in accordance with the quantity-data; and outputting (S46) the output data. An image processing method according to claim 4, wherein the image data includes binary data, and plural-bit gradation data or color data which expresses each color component by a plurality of bits per pixel.

Inventors: CHO KENJIRO, ISHIZAWA YASUHISA, NONOSHITA HIROSHI, YAMANASHI YOSHITSUGU, CHO, KENJIRO, ISHIZAWA, YASUHISA, NONOSHITA, HIROSHI, YAMANASHI, YOSHITSUGU
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H04N1
IPC codes: H04N1, G06T11