Potential detecting circuit

Abstract: A potential detecting circuit comprises a first MOS transistor (N6, P6) of a first conductivity type whose drain receives an input potential whose absolute which is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor (N11, P11) of the first conductivity type whose source is connected to the second MOS transistor (P5, N5), source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.

Description: The present invention relates to a potential detecting circuit comprising: a first MOS transistor of a first conductivity type whose drain receives an input potential which is equal to or lower, in absolute value, than a second potential whose absolute value is greater than that of a first potential; a second MOS transistor of a second conductivity type whose source is connected to the source of said first transistor and whose gate receives said first potential; a third MOS transistor of the first conductivity type whose drain is connected to the drains of said second MOS transistor, whose source receives a reference potential with an absolute value which is less than that of said first potential, and whose gate receives said first potential; and a potential detect output terminal for providing a detected potential, said potential detect output terminal being a junction point between the drains of said second and third MOS transistors. Such a circuit is described in US-A-4 626 704. The present invention is applicable for detecting a potential which is similar to the power source potential of a CMOS LSI, and a potential which is much higher than the reference potential or the power source potential of the CMOS LSI. Another circuit of interest is described in EP-A-0 090 116. In an LSI with a nonvolatile memory, for example an EPROM, it is required that a write mode be changed to a read mode, and vice versa. To operate the LSI in the write mode, an externally applied voltage V pp , which is much higher than the LSI power source V DD potential, is required. A protection transistor (Q19 in Fig. 4) is provided to prevent that the high voltage V pp appears at transistors not designed to be operated with such a high voltage. Fig. 1 shows another prior art potential detecting circuit. In this circuit, an input terminal IN for receiving an input potential VIN is grounded through PMOS transistors P1 and P2 and an MNOS transistor N1. A potential detection signal is derived from an output terminal Out1, through an inverter consisting of two pairs of MOS transistors P3 and N3, and P4 and N4. The high breakdown voltage transistor is different from the transistor of the VDD system in the following respects: 1) The high breakdown voltage transistor has an LDD (lightly doped drain) structure. 2) The high breakdown voltage transistor has a thick gate oxide film. In Fig. 1, the MOS transistors of the LDD structure are indicated by small circles attached to the drains. Let us consider two different operations of the prior art potential detecting circuit shown in Fig. 1, when the input potential of the circuit is equal to an LSI power source, high potential V pp , e.g., 20 V, which is much higher than an LSI power source, low potential V DD , e.g., 5 V, and when the input potential is equal to the power source potential V DD . a) When the high potential V pp (20 V) is applied to the input terminal IN, a potential at node 5 is lower than the potential V pp by the amount of the threshold voltage V THp1 of the PMOS transistor P1. If the potential at node 5 is higher than a sum of the threshold voltage V THp2 of the PMOS transistor P2 and the gate potential V DD , the PMOS transistor P2 is turned on. Under this condition, a current flows from the input terminal IN to the ground point G through the PMOS transistors P1 and P2 and the NMOS transistor N1. The potential at node 6 progressively rises by a ratio of the sum of the ON-resistance of the PMOS transistors P1 and P2 to the ON-resistance of the NMOS transistor N1. i) When the potential at node 6 is higher than the threshold voltage of the inverter including the MOS transistors P3 and N3, a potential at the V DD level is output from the output terminal Out1. ii) When the former is lower than the latter. A ground level potential is output from the output terminal Out1. b) When a potential V DD equal to or lower than the potential V pp is applied to the input terminal IN, the potential at node 5 is lower than a sum of the threshold voltage V TH2 of the PMOS transistor P2 and the gate potential V DD . Therefore, the transistor P2 remains off while the transistor N1 remains on. Accordingly, a ground level potential is output from the output terminal Out1. In this way, the potential detecting circuit can detect the input potential V IN , the high potential V pp , or the low potential V DD . The potential detecting circuit is characterized in that, even when a potential between the ground level and the V DD level is applied to the input terminal, the PMOS transistor P2 is turned off, and hence no DC path is formed. It is also characterized in that the drains of the transistors P3 and N3 are of the LDD structure type and can withstand a high potential applied to the gates of those transistors. To assemble the circuit, including the high breakdown voltage PMOS transistor P2 and the like as shown in Fig. 1, into an LSI chip which does not use high breakdown voltage PMOS transistors, another type of transistors must be used. This means that the number of manufacturing process steps must increase. In this regard, it should be noted that to manufacture an LSI containing elements such as E²PROM, polysilicon electrodes for the V DD system and those for the high breakdown voltage cells are separately formed. In this case, the following additional three steps are performed in the photo etching process: a) To implant ions into the channels of high breakdown voltage PMOS transistors, b) To form the LDD structure of high breakdown voltage NMOS transistors by using a mask, and c) To form the LDD structure of high breakdown voltage PMOS transistors by using a mask. It is evident that the increased number of process steps leads to an increase in the manufacturing cost and manufacturing time. Accordingly, an object of the present invention is to provide a potential detecting circuit capable of detecting a high potential (whose absolute value is great, in comparison with the negative potential) in an LSI of the type in which high breakdown voltage PMOS (or NMOS) transistors having a high breakdown structure such as the LDD structure are not required. According to the invention, the potential detecting circuit initially defined is characterized by: a detecting potential control block for applying a potential varying in accordance with said input potential to the gate of said first MOS transistor. A structure capable of withstanding the application of a high potential is not required for the second MOS transistor. Thus, in an LSI with different power sources, the potential detecting circuit can detect a potential higher, in absolute value, than the potential V DD , and can comprise the high breakdown voltage MOS transistors of the first conductivity type and the transistors of the second conductivity type used in the V DD (normal MOS LSI power source) system, rather than the high breakdown voltage MOS transistors of the second conductivity. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional potential detecting circuit; Fig. 2 is a circuit diagram showing a potential detecting circuit according to an embodiment of the present invention; Fig. 3 is a circuit diagram showing the details of the potential detecting circuit of Fig. 2; Fig. 4 is a block diagram of an EPROM-contained LSI into which a potential detecting circuit according to the present invention is assembled; Fig. 5 is a circuit diagram showing a potential detecting circuit according to another embodiment of the present invention; and Fig. 6 is a circuit diagram showing a potential detecting circuit according to another embodiment of the present invention. Some specific embodiments of the present invention will be described with reference to the accompanying drawings. Fig. 2, illustrates a high potential detecting circuit according to an embodiment of the present invention. In Fig. 2, the same components as those shown in Fig. 1 (prior art) are designated by the same symbols for simplicity. In Fig. 2, reference numeral 30 denotes a detecting potential control block. When the potential V pp , which is much higher than the LSI power source potential V DD , is applied to an input terminal IN, the detecting potential control block 30 produces at its output terminal 21 a potential higher than the potential V DD . When a potential lower than the potential V DD or higher, but not much higher, than the potential V DD is applied to the input terminal, the block 30 produces the potential V DD at its output termi nal 21. Reference numeral 31 indicates a level converting circuit. A level converting circuit 31 changes the potential appearing at an input terminal 23 to a potential of "V DD - ground potential". The input terminal IN is connected to the drain of a D-type (depletion-type) NMOS transistor N6. The transistors, which are NMOS and PMOS transistors, are of the E-type (enhancement-type). The source of the D-type NMOS transistor N6 is connected to the source and the back gate of a PMOS transistor P5. The gate of the transistor N6 is connected to the output terminal 21 of the detecting potential control circuit 30. The gates of the PMOS transistor P5 and the NMOS transistor N11 are connected to the potential V DD . The source of the transistor N11 is grounded. The potential applied to the input terminal IN passes through the level converting circuit 31, and is out-putted in the form of a detected potential, from the output terminal Out. The potential detecting circuit of Fig. 2 is illustrated in detail in Fig. 3. The detecting potential control block 30 shown in Fig. 2 is arranged as follows. The input terminal IN is connected to the drain and the gate of an NMOS transistor N8. The source of the transistor N8 is connected to the drain and the gate of an NMOS transistor N9. The source of the transistor N9 is connected to the drain and the gate of the NMOS transistor N10. The source of the transistor N10 is connected to the drain of the D-type NMOS transistor N14. The source and the gate of the transistor N14 is connected to the potential V DD . The level converting circuit 31 shown in Fig. 2 has the structure described as follows. The input terminal 23 is connected to the drain of a D-type transistor N7. The gate of the transistor N7 is connected to the potential V DD , and the source of the transistor N7 is connected to the input terminal of an inverter has a PMOS trnasistor P12 and an NMOS transistor N12. As output terminal of the inventer is connected to an output terminal out of an inverter having PMOS transistor P13 and NMOS trnasistor N13. In the circuit of Fig. 3, as is understood from mark o, the LDD structure is employed for the sources and the drains of the NMOS transistors N8, N9, and N10, and the D-type NMOS transistor N6, and the drains of the NMOS transistor N11 and the D-type NMOS transistors N14, and N7. It is noted here that the PMOS transistor P5 is a normal V DD system transistor and, unlike the PMOS transistor P2 in Fig. 1, does not employ the LDD structure for the drain. Operations of two modes of the potential detecting circuit thus arranged and shown in Fig. 3 will be described. a) A first operation mode of the potential detecting circuit starts when a potential lower than the potential V DD is applied to the input terminal IN. In this mode, the source and the gate of the NMOS transistor N14 are both at the V DD level. Accordingly, the potential V DD in applied at the node 21 between the drain of the transistor N14 and the source of the NMOS transistor 10. At this time, the potential lower than the potential V DD has been applied to the input terminal IN. Accordingly, no current flows through the current paths of the NMOS transistors N8 to N10, because those transistors are reversely biased. Since the potential at the node 21 is applied to the gate of the D-type NMOS transistors N6, the transistor N6 is turned on, and the potential lower than V DD at the input terminal IN is applied the source of the PMOS transistor P5 via the transistor N6. At this time, the potential V DD has been applied to the gate of the PMOS transistor P5, and hence the transistor P5 is turned off. The potential V DD has also been applied to the gate of the transistor N11, which has been turned on. Accordingly, the node 23 is pulled down to the ground potential. This potential goes through the D-type NMOS transistor N7, which has been in an on state because the potential V DD is applied to the gate thereof, and the two-stage inverter, and applied at the output terminal Out. Accordingly, when the potential below the V DD level is applied to the input terminal IN, the output terminal Out provides the potential of the ground level. b) A second operation mode of the potential detecting circuit starts when the potential V pp (which is much higher than the potential V DD . When the potential V pp is applied to the input terminal IN, a potential at the node 21 is determined by the back-gate effect of the NMOS transistors N8 to N10, and the ON-resistance of the D-type NMOS transistor N14. Since the potential at the node 21 is applied to the gate of the transistor N6, a potential at a node 22 is expressed as "(potential at node 21) + |(threshold voltage V TH of transistor N6 influenced by the back-gate effect)|". Thus, the detecting potential control block 30 is a circuit for determining a potential at the node 22 and controlling the potential so as not to degrade the PMOS transistor P5. Since the potential at the source and gate of the PMOS transistor P5 is higher than "V DD + |threshold voltage V TH of the PMOS transistor P5|" when the potential at the node 22 rises, the transistor P5 is turned on, and a potential at the input terminal 23 is determined by a ratio of the ON-resistance of the transistor P5 and that of the NMOS transistor N11 which has been already turned on. The potential at node 24 connected to the source of D-type NMOS transistor N7, which is turned on by applying potential V DD to the gate thereof, is substantially equal to a potential at input terminal 23. The potential at the node 24 is controlled to be below "V DD + |threshold voltage V TH of transistor N7 influenced by the back gate effect|", thereby protecting the PMOS transistor P12 and NMOS transistor N12 from its gate breakdown, e.g., breakage of the gate insulating film. This fact implies that there is no need for introducing the high breakdown voltage structure to the PMOS transistor P12 and NMOS N12, although the potential detecting circuit of Fig. 1 uses such a measure, or the LDD structure. The potential at the node 24 increases higher than the threshold voltage of the inverter consisting of the PMOS transistor P12 and the NMOS trnasistor N12, and goes through the two-stage inverter consisting of the paired transistors P12 and N12, and P13and N13, and appears as the potential of the V DD level at the output terminal Out. The potential of V DD level is output from the output terminal Out. It is thus detected that a high potential V pp is applied to the input terminal In. The circuit shown in Fig. 3 has the following feature. When the potential level is between the ground potential and the potential V DD , no current flows through the current path consisting of the NMOS transistors N8 to N10, as already stated. As seen from the foregoing description, the potential detecting circuit according to the embodiment shown in Fig. 3 is constructed by using E- and D-type NMOS transistors and the PMOS transistors (particularly, the transistor P5) of the V DD system, not the high breakdown voltage PMOS transistor like the PMOS transistor P2 in the prior art of Fig. 1. The potential detecting circuit thus constructed is capable of detecting a high potential. Accordingly, when the potential detecting circuit is assembled into the LSI not using the high breakdown voltage MOS transistors with the LDD structure, the manufacturing time is reduced, the production yield is improved, and the cost to manufacture is reduced. Further, when the input potential is between the ground potential and the potential V DD , no current path is formed between the high and low power sources. The input impedance of the circuit is extremely high. Therefore, the input terminal IN may be used for another terminal, for example, data input terminal. An LSI having an EPROM into which a potential detecting circuit according to the present invention is incorporated, will be described with reference to Fig. 4. In the figure, reference numeral 51 designates an LSI chip; 52, a potential detecting circuit according to the present invention; 53, an EPROM read out circuit; 54, an EPROM write circuit; 55, an EPROM cell array; 56, 57, random logics. The potential V DD at the output terminal Out of the potential detecting circuit 52 drives the write circuit 54, while the ground potential at the output terminal Out drives the read out circuit 53. The write circuit 54 is for writing data into the EPROM cell array 55. The read out circuit 53 reads data from the cell array 55. To separately operate the read and write circuits, it is necessary to change a read mode to a write mode and vice versa. To this end, a select signal V pp is used, and the potential detecting circuit 52 which operates in response to the select signal is provided. In this case, such an operation of the potential detecting circuit suffices that it produces the V DD potential for the potential of the V pp level, and produces ground potential for the input potential of the V DD level or less. Alternatively, the reversed case is also allowed. In the Fig. 4 circuit, the EPROM write circuit 54 goes into an active state when the output from the potential detecting circuit 52 is at level V DD . The read out circuit 53 goes into an active state when the output from the potential detecting circuit 52 is at the ground potential level. With such an arrangement, the write mode and the read mode may be selectively set up by applying the potential V pp or V DD to one of the input terminals IN of the LSI, which connects to the potential detecting circuit 52 contained therein. Thus, the input potential applied to the potential detecting circuit 52 is applied from the outside of the LSI chip, and the output potential of the circuit 52 is used for selecting the read mode or the write mode within the LSI. In this instance, when the input terminal is at a potential of the V DD level or less, it serves as an input terminal to the random logic 57. It should be understood that the present invention is not limited to the specific embodiments as mentioned above, but may be variously changed and modified within the scope of the present invention. While the embodiment as described with reference to Figs. 2 and 3 is the high potential detecting circuit, the present invention may also be embodied into a low potential detecting circuit as shown in Fig. 5. Here, the term "low potential" means a potential much lower than potential - V DD . An arrangement of the low potential detecting circuit of Fig. 5 is featured in that the PMOS transistors are replaced by the NMOS transistors, and the potential V DD is replaced by the potential - V DD . The arrangement of the Fig. 5 may readily be understood on the analogy of the arrangement of the high potential detecting circuit of Figs. 2 and 3. The reference symbols denoting the transistors in Fig. 4 are replaced characters, P by N, or vice versa followed by the same numerals as those in Figs. 2 and 3. The operation of the low potential detecting circuit of Fig. 5 will be understood with the reversed polarity. The detect voltage controller 30 is operable with only two transistors (specifically, the transistors P8 and P9 are omissible, if required). The detecting potential control block 30, which is designed to control a desired detecting potential, can be of any circuit which can control such a potential. Further, the block 30 can be dispensed with, as is shown in Fig. 6, depending upon the value of the detecting potential. Moreover, the gate input of the DMOS transistor N6 can be a fixed potential, for example, V DD (the first potential).

Claims: A potential detecting circuit comprising: a first MOS transistor (N6, P6) of a first conductivity type whose drain receives an input potential which is equal to or lower, in absolute value, than a second potential whose absolute value is greater than that of a first potential; a second MOS transistor (P5, N5) of a second conductivity type whose source is connected to the source of said first transistor and whose gate receives said first potential; a third MOS transistor (N11, P11) of the first conductivity type whose drain is connected to the drain of said second MOS transistor (P5, N5), whose source receives a reference potential with an absolute value which is less than that of said first potential, and whose gate receives said first potential; and a potential detect output terminal (23) for providing a detected potential, said potential detect output terminal being a junction point between the drains of said second and third MOS transistors (P5, N5, N11, P11), characterized by: a detecting potential control block (30; N5, N8 to N10, p5, P8 to P10) for applying a potential varying in accordance with said input potential to the gate of said first MOS transistor. The potential detecting circuit according to claim 1, characterized in that said first potential is a positive potential, said second potential is another positive potential higher than said first potential, said first conductivity type is an N type, and said second conductivity type is a P type. The potential detecting circuit according to claim 1, characterized in that said first potential is a negative potential, said second potential is another negative potential more negative than said first potential, said first conductivity type is a P type, and said second conductivity type is an N type. The potential detecting circuit according to claim 1, characterized in that the back-gate of said second MOS transistor (P5, N5) is connected to the source of said first MOS transistor (N6, P6). The potential detecting circuit according to claim 1, characterized in that said first MOS transistor (N6, P6) is of the depletion type. The potential detecting circuit according to claim 1, characterized in that said second MOS transistor (P5, N5) is structured not to have a high breakdown voltage. The potential detecting circuit according to claim 1, characterized in that when an absolute value of said input potential is much higher than said first potential, said detecting potential control block produces an output potential determined by said input potential, and when the absolute value of said input potential is higher than said first potential but much lower than said second potential, or when the absolute value of said input potential is lower than said first potential, said detecting potential control block produces said first potential, which is independent of said input potential. The potential detecting circuit according to claim 1, characterized in that said detecting potential control block (30), for producing a potential varying in accordance with said input potential, is arranged such that at least fourth and fifth MOS transistors (N10, N14) of the first conductivity type are connected in series, the source and gate of said fifth MOS transistor are connected to said first potential, a node (21) between said fourth and fifth MOS transistors is used as a potential output terminal connecting to the gate of said first MOS transistor (N6), the gate and drain of said fourth MOS transistor are interconnected, and the drain of said fourth MOS transistor is connected to said input terminal. The potential detecting circuit according to claim 1, characterized in that said potential detect output terminal (23) is connected to a level converting circuit (31) for changing the output potential at said output terminal to said reference potential or a potential of the same level as that of said first potential. The potential detecting circuit according to claim 9, characterized in that said level converting circuit (31) is designed such that said potential detect output terminal (23) is connected to the drain of a sixth MOS transistor (N7) of the first conductivity type, the gate of said sixth MOS transistor (N7) is connected to an input terminal receiving said first potential, and a detect output potential is derived from the source of said sixth MOS transistor (N7), through an inverter (P12, N12, P13, N13). The potential detecting circuit according to claim 3, characterized in that the back-gate of said second MOS transistor (P5, N5) is connected to the source of said first MOS transistor (N6, P6). The potential detecting circuit according to claim 3, characterized in that said first MOS transistor (N6, P6) is of the depletion type. The potential detecting circuit according to claim 3, characterized in that said second MOS transistor (P5, N5) is structured not to have a high breakdown voltage. The potential detecting circuit according to claim 3, characterized in that when an absolute value of said input potential is much higher than said first potential, said detecting potential control block produces an output potential determined by said input potential, and when the absolute value of said input potential is higher than said first potential but much lower than said second potential or, when the absolute value of said input potential is lower than said first potential, said detecting potential control block produces said first potential, which is independent of said input potential. The potential detecting circuit according to claim 3, characterized in that said detecting potential control block (30) for producing a potential varying in accordance with said input potential is designed such that at least fourth and fifth MOS transistors (N10, N14) of the first conductivity are connected in series, the source and gate of said fifth MOS transistor are connected to said first potential, a node between said fourth and fifth MOS transistors is used as a potential output terminal connecting to the gate of said first MOS transistor, the gate and drain of said fourth MOS transistor are interconnected, and the drain of said fourth MOS transistor is connected to said input terminal. The potential detecting circuit according to claim 3, characterized in that said potential detect output terminal (23) is connected to a level change circuit (31) for changing the output potential at said output terminal to said reference potential or a potential of the same level as that of said first potential. The potential detecting circuit according to claim 16, characterized in that said level converting circuit (31) is designed such that said potential detect output terminal (23) is connected to the drain of a sixth MOS transistor (N7) of the first conductivity type, the gate of said sixth MOS transistor (N7) is connected to an input terminal receiving said first potential, and a detect output potential for said input potential is derived from the source of said sixth MOS transistor (N7), through an inverter (P12, N12, P13, N13).

Inventors: MATSUMOTO OSAMU C O INTELLECTU, SAEKI YUKIHIRO C O INTELLECTUA, TAKIBA AKIRA C O INTELLECTUAL, MATSUMOTO, OSAMU, C/O INTELLECTUAL PROPERTY DIV., SAEKI, YUKIHIRO, C/O INTELLECTUAL PROPERTY DIV., TAKIBA, AKIRA, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G05F3
IPC codes: G01R19, G05F3, G11C16, G11C5