Sense amplifier

Abstract: A sense amplifier (38) uses a current source (40) to pull-up a product line (14) during as low-to-high transition. After a desired voltage is reached on the product line (14), the current source is turned off by a delay feedback circuit (44). A hold-up circuit (42) holds the product line at the desired voltage until a high-to-low transition occurs.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates in general to integrated circuits, and more particularly to a sense amplifier. BACKGROUND OF THE INVENTION Electrically programmable array logic (EPALs) use a plurality of FAMOS transistors having gates coupled to input signals and source/drain region coupled between a product line and ground to implement logic functions. Sense amplifiers, which detect logic levels on the product line, may pull the product line to a voltage which will result in preventing premature FAMOS data gain. Previously developed sense amplifiers use a stacked transistor design to achieve the required pull-up. The operating point of the two transistors moves along the edge of the linear and saturated region, thus operating like a resistive pull-up. The current supplied by the stacked transistor pull-up will therefore be dependent upon the voltage of the product line. The higher the product line voltage, the lower the current supplied. When the product line's voltage approaches the clamp voltage, the current diminishes greatly. This effect may be great enough to skew the output transitions, making the low-to-high transitions slower than the high-to-low transitions, even though the FAMOS cell will sink increasing current with the decreasing product line voltage when it is pulling the line low. The stacked transistor design must also be highly intolerant to process variations. If the N-channel transistors are weakened through any kind of parameters changes, such as VTO, BE (body effects), or KP, the performance of the sense amplifier will be greatly altered. The trip point of the CMOS inverter sense amplifier will also be skewed with process variations which can work against the slowest transition, and may even cause threshold problems. Other sense amplifiers utilize a resistor divider type of pull-up to achieve the low voltage "high" required to prevent premature FAMOS data gain. In this design, a reference voltage tracks with process variations to control N-channel and P-channel fluctuations. The low-to-high transition of such sense amplifiers is sacrificed by the pull-down resistor divider. The higher the product line voltage, the more the pull-up current is channeled from the product line capacitance to the pull-down transistor, which helps to slow down the low-to-high transition. The high-to-low transition creates a situation where the FAMOS cell pulling the line low must sink increasing current with decreasing product line voltage. This sense amplifier operation sacrifices the high-to-low transition speed. Therefore, a need has arisen to provide a high-speed process tolerate sense amplifier providing a low voltage cutoff to eliminate premature FAMOS data gain. In WO 86/01658 there is described a circuit for improving the rise time of an electronic signal in which the voltage of the electronic signal is compared with a reference voltage, and the output of the comparison is used to control the generation of a current pulse of predetermined duration that is added to the electronic signal to assist the voltage rise. The electronic signal may originate from any one of a plurality of VLSI chips connected to a common node. US-A- 4 827 728 and US-A- 4 899 070 both concern another circuit for improving the rise time of an electronic signal, the circuit having a feedback to the electric signal so that the circuit is disconnected when the electric signal has reached a predetermined level. It is an object of the present invention to provide a sense amplifier which at least partially eliminates the disadvantages and problems associated with prior sense amplifiers. According to one aspect of the present invention there is provided a sense circuitry operable to detect the logic state of a sense node coupled to a plurality of programmable switches selectively enabled by respective input signals, comprising: first voltage control circuitry for selectively coupling the sense node to a first voltage source in response to a first control signal; feedback circuitry for generating said first control signal which is such that said first voltage control circuitry decouples the sense node from said first voltage source in response to said sense node reaching a predetermin d voltage; and second voltage control circuitry to maintain said predetermined voltage on said sence node until one of said programmable switches is enabled, characterised in that said second voltage control circuitry comprises a first N-channel FET, having a source and a drain disposed in a P-well and a gate, and second N-channel FET, having a source and a drain disposed in a P-well and a gate, and the first and second N-channel FET's being diode coupled and connected in series between said first voltage source and said sense node zero power circuitry operable to disable said first and said second voltage control circuitry in response to a second control signal. According to a second aspect of the present invention there is provided a method of providing a rapid output transition responsive to an input transition, comprising the steps of: providing current to a product line during a low-to-high output transition to rapidly increase the voltage on said product line; disabling said current provision when said product line is at a high logic level to prevent excessive voltage on said product line; maintaining said product line voltage using a voltage generator; reenabling said current source when said product line is at a low logic level; and disabling said current provision and said product line voltage maintenance in response to a control signal. The sense circuitry of the present invention provides significant advantages over the prior art. Since the first voltage control circuitry is responsive to feedback circuitry, the sense node may be pulled high using a voltage source in excess of the predetermined clamping voltage, resulting in a fast transition. Further, since the first voltage control circuitry may decouple the voltage source from the sense node, a weaker second voltage control circuitry may maintain the predetermined voltage on the sense node, such that a fast high-to-low transition may occur. The present invention is compatible with programmable array logic (PALs) wherein a plurality of programmable switching devices selectively couple a plurality of product lines to a first voltage source under the control of a plurality of inputs. Sensing circuitry associated with each product line includes first voltage control circuitry for selectively coupling the product line to a second voltage source responsive to a control signal, feedback circuitry for generating the control signal responsive to the voltage on the associated product line and second voltage control circuitry to maintain a predetermined voltage on the product line when the product line is not coupled to the first voltage source. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGUREs 1a-c illustrate prior art sense amplifiers; FIGURE 2a-b illustrate the sense amplifier of the present invention; FIGURE 3 is a graph of a comparison between the present invention and a prior art sense amplifier; and FIGURE 4 illustrates a block diagram of the present invention used in an EPAL circuit. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention is best understood by referring to FIGUREs 1-4 of the drawings, like numerals being used for like and corresponding parts of the various drawings. FIGURE 1a illustrates a block diagram of a sense amplifier, as used in a CMOS programmable array logic (PAL) device. The circuit 10 comprises two FAMOS transistors 12a-b having drains connected to a product line 14, sources connected to ground and gates connected to respective input lines 16a-b of the PAL array. Pull-up circuitry 18 is connected to the product line. An inverter 20 inverts the logical signal on the product line to provide an output signal (OUT). The FAMOS (floating-gate avalanche MOS) transistor is the programmable element in an EPAL (erasable PAL). The FAMOS transistors 12 operates like normal N-channel MOS transistors when in an erased state. Thus, when the gate of the cell is addressed ( a logical "1" on the input line) the device is turned on and the drain of the cell is connected to ground, thereby producing a logical "0" on the product line 14. Similarly, if the gate of the cell is not addressed (a logical "0" on the input line), the transistor is not conducting and the drain of the cell remains at a logical "1", since the pull-up circuitry 18 forces the product line 14 to a logic high voltage. If the FAMOS transistor 12 was programmed, the threshold voltage of the transistor is shifted such that the transistor will not turn on under normal operation regardless of the logical signal at its input line. Hence, the drain of the programmed FAMOS cell will always be at a logical "1". Logically, the FAMOS cell 12 acts as an inverter of the input data on the input line 16. Because the drains of multiple transistors 12a-b are tied together on the product line, a logical "0" will predominate over any number of logical "1"s, producing an "AND" function on the inverted input data. The inverter 20 senses the logical value on the product line 14 and outputs the inverted value. In an actual implementation, the EPAL comprises many product lines 14 and many input lines 16 coupled by FAMOS transistor 12. By performing an OR operation on the outputs of each inverter 20, any SUM-OF-PRODUCTS logic function may be designed by appropriately programming or erasing the FAMOS transistors. The product line of an EPAL must be less than two volts to prevent accidental programming of the FAMOS transistor 12. Hence, it is important that the pull-up circuitry 18, which governs the voltage of the product line when the FAMOS transistors 12a-b are turned off, accurately maintain a voltage of two volts or less on the product line 14. FIGURE 1b illustrates a prior art sense amplifier 22. In this sense amplifier, the pull-up circuitry 18 comprises a stacked N-channel transistor pair. The pull-up circuitry 18 comprises N-channel transistors 24 and 26. N-channel transistor 24 has its gate and drain connected to V cc . The source of N-channel transistor 24 is connected to the gate and drain of N-channel transistor 26. The source of N-channel transistor 26 is connected to the product line 14. The P-wells of N-channel transistors 24 and 26 are connected to ground. The pull-up circuit 18 of FIGURE 1B will produce a voltage at the product line 14 of V cc - 2V t - BE, where BE are the body effects of the transistors 24 and 26. Since the V gs of the transistors 24 and 26 is close to the threshold voltage V t of the transistors, the operating point of the transistors moves along the edge of the linear and saturated region, operating like a resistive type of pull-up. Therefore, the current supplied by the pull-up will be dependent upon the voltage on the product line. As the voltage on the product line increases, the current supplied by the pull-up decreases. When the product line voltage approaches the clamp voltage (two volts), the current diminishes greatly. This effect may be great enough to skew the output transitions, making the low-to-high transitions slower than the high-to-low transition. The design shown in FIGURE 1b is highly intolerant to process variations. If the drive of the N-channel transistors 24 and 26 are weakened through any form of parameter changes during processing, the performance of the sense amplifier will be greatly altered. The trip-point of the inverter 20 may also be skewed with process variations, which can work against the slowest transition, and may even cause threshold problems. A second type of prior art sense amplifier is illustrated in connection with FIGURE 1c. The sense amplifier 28 includes a pull-up circuit 18 comprising three N-channel transistors 30, 32 and 34 and a P-channel transistor 36. N-channel transistor 30 has a drain connected to V cc , a gate connected to a first reference voltage source (REF1), and a source connected to the product line 14. N-channel transistor 32 has a gate and drain connected to the product line and a source connected to ground. N-channel transistor 34 has a gate connected to the product line, a source connected to ground and a drain connected to the drain of P-channel transistor 36 and to the input of inverter 20. The gate of P-channel transistor 36 is connected to a second reference voltage source (REF2) and the source of P-channel transistor 36 is connected to V cc . The P-well of N-channel transistor 30 and the N-well of P-channel transistor 36 are connected to V cc and the P-wells of N-channel transistors 32 and 34 are connected to ground. The sense amplifier 28 of FIGURE 1c uses a resistor divider type of pull-up to achieve the low voltage "high" required to prevent premature programming of the FAMOS transistors 12a-b. The reference voltage sources (REF1 and REF2) are designed such that their voltage compensates transistors 30 and 36 in accordance with process variations. In this design, the low-to-high transition is sacrificed by the pull-down resistor divider transistor 32. As the voltage on the product line increases, the current channeled from the product line to the pull-down transistor 32 is increased. The effect is to slow down the low-to-high transition. The high-to-low transition creates a situation where the FAMOS transistors 12a-b must sink increasing current with decreasing product line voltage, which slows the high-to-low transition. While the reference voltage sources achieve process tolerance, the cost of this feature is increased power dissipation, which is undesirable. FIGURE 2a illustrates a schematic representation of the sense amplifier of the present invention. The sense amplifier 38 includes a pull-up circuit 18 comprising a current source 40, a hold-up circuit 42 and a delay feedback circuit 44. The delay feedback circuit comprises two inverters 46 and 48 connected in serial, the input to inverter 46 connected to the product line 14 and the output of inverter 48 connected to the gate of P-channel transistor 50 which comprises the current source 40. P-channel transistor 50 has a source connected to V cc and the drain connected to the product line 14. Hold-up circuit 42 comprises two N-channel transistors 52 and 54. The gate and source N-channel transistor 52 are connected to V cc and the drain of N-channel transistor 52 is connected to the source and gate of N-channel transistor 54. The drain of N-channel transistor 54 is connected to the product line 14. The P-wells of N-channel transistors 52 and 54 are connected to ground. In operation, the current source 40 is used for low-to-high transitions, and is shut off by the delay feedback circuit 44 in order to keep the product line voltage from reaching the V cc rail. Additionally, the current source 40 is shut off to improve the high-to-low transition of the product line 14. The hold-up circuit 42 holds the product line voltage at a "high" after the current source 40 is shut off. Since the hold-up circuit 42 is not necessary to pull the product line 14 up during a low-to-high transition, it can be designed to be fairly weak so that the high-to-low transition is not affected. When the product line 14 is low, the inverters 46 and 48 turn on the P-channel transistor 40, resulting in a constant current into the FAMOS transistor. The P-channel transistor 50 is operating in the saturated region, and hence, not appreciably affected by process variations. When the gates of FAMOS transistors 12a-b are pulled low, the product line voltage will rise until the gate of P-channel transistor 50 rises to a voltage to power-down the P-channel transistor 50. Since the P-channel transistor 50 is heavily loaded due to the product line's capacitance and since the inverters 46 and 48 are lightly loaded, the gate of the P-channel transistor will have a faster rise time than the product line. The thresholds of the inverters 46 and 48 should be set to shut off the current source 40 at the desired product line voltage. This voltage is typically low enough to keep the P-channel transistor constantly saturated, so that maximum current is provided to the product line capacitive load during the low-to-high transition. The hold-up circuit 42 holds the product line at its desired level until the FAMOS cells are again enabled. Once the FAMOS transistors 12a-b are enabled (assuming one or more of the FAMOS transistors is erased), the FAMOS transistors 12a-b need only sink the weak hold-up circuit 42 and discharge the capacitance on the product line 14, since the current source remains off. Once the product line voltage is below the threshold of the feedback inverters 46 and 48, the P-channel 50 will turn on again. Thus, it is important to adjust the threshold of the feedback inverters against the threshold of the inverter 20 such that the P-channel transistor 50 will not turn on before the FAMOS transistors 12a-b pull the product line below the threshold of inverter 20. In doing so, the fall-time of the product line will be minimized since the FAMOS cells 12a-b remain unloaded by the P-channel throughout the transition. The following considerations should be taken into account when setting the threshold voltage of the inverter 20. The threshold of inverter 20 should be set between the voltage on the product line with one FAMOS cell turned on and the product line's maximum voltage limit determined by processing. Noise margins should also be taken into consideration and added to the lower voltage limit and subtracted from the upper voltage limit. The threshold of inverter 20 should be set according to the ratio of the size of the P-channel 50 to the size of a single FAMOS transistor. The P-channel transistor 50 always delivers constant saturated current during the low-to-high transition while a single FAMOS transistor will enter its linear region as the voltage of the product line drops. Therefore, the changing drive of a single FAMOS transistor versus the constant drive of a saturated P-channel transistor must be examined for rise and fall times of the product line. If the size of the P-channel transistor 50 and FAMOS transistor 12 are set such that the fall time of the product line is faster than its rise time, then the threshold of the inverter 20 should be set lower to compensate for the variation in transition time; however, the threshold must not be set so low that the P-channel transistor 50 turns on before the FAMOS transistor 12 can pull the product line below inverter 20's threshold. Process variations have very little affect on the sense amplifier of the present invention. Body effects should not affect the circuit, since all bulks are shorted to their respective rails. If process variations result in weak P-channels, the current source 40 will have little affect on the P-channel pull-up current, since the different between V gs and V t will not change significantly as V gs is much greater than V t . Furthermore, weaker P-channel transistors will result in a lower threshold of the inverter 20 to compensate for any slight rise time variation. The threshold of both inverters would be lowered, one offsetting the other. Since the P-channel driver is off during a high-to-low transition, weak P-channel transistors would have only a slight affect during such a transition. The process variations cause the P-channels to be strong, there will again be little affect on the pull-up current because of the wide differential between V gs and V t . Again, the inverters 46 and 48 will compensate for one another and the threshold of inverter 20 will rise, which will slightly improve the fall-time speed of the product line 14. If the N-channel transistors are weak, the consequential threshold rise in inverter 20 will make a very slight difference in speed during a low-to-high transition because of the saturated P-channel's current sourcing effect on the product line 14. The transition speed of the product line in a high-to-low transition will be only slightly improved due to the higher threshold of inverter 20 and a weaker hold-up circuit 42. Again, the inverters 46 and 48 will compensate for one another. If the processing variations cause strong N-channels, the threshold of inverter 20 will fall, slightly improving the low-to-high transition. The lower threshold of inverter 20 and the slightly increased strengthen of the hold-up circuit 42 will slow the fall-time of the product line during a high-to-low transition. Since the P-channel transistor 50 remains off during a high-to-low transition, the circuit will have a very steep fall-time. If processing variations cause a higher product line capacitance, the product line will rise more slowly. The feedback inverters 46 and 48 will be slowed somewhat, but not at the same rate of the product line slowdown. As a result, a lower maximum voltage for the product line will occur, but the difference should not be significant. The threshold of inverter 20 may be slightly adjusted for capacitance variations. Another important aspect of the present invention concerns the speed with which it comes out of a zero power state. In a zero power circuit, a control signal is generated in response to a change in one of the input signals. Zero power circuitry could be added to the sense amplifier 28 of FIGURE 1c in order to power-down the sense amplifier while no transitions are occuring. However, the two reference signals (REF₁ and REF₂) must also be powered down in a zero power mode. When a power-up pulse is generated in response to an input transition, the reference signals must power-up to allow the sense amplifier 28 to function. The delay associated with a reference signal power-up is much longer than would be necessary if the generated power-up pulse when straight to the sense amplifier. Typically, the zero power TPD of the type of sense amplifier illustrated in FIGURE 1c is at least 30% greater than the full power TPD. It should be noted that the sense amplifier 22 of FIGURE 1b does not require reference generators, and therefore allows the power-up pulse to go straight to the sense amplifier 22. However, the lack process compensation results in serious problems; such an application will likely result in the sense amplifier 22 using its slowest (low-to-high) transition when coming out of the zero power state. FIGURE 2b illustrates an embodiment of the present invention using zero power circuitry. The TN signal produces a pulse which goes low when the chip is powering up. The TN signal is connected to the gates of a P-channel transistor 55a and an N-channel transistor 55b. The source of the P-channel transistor 55a is connected to V cc and the drain of P-channel transistor 55a is connected to the source of P-channel transistor 50. The source of N-channel transistor 55b is connected to ground and the drain of N-channel transistor 55b is connected to the product line 14. The TN pulse goes low when the chip powers up. The sense amplifier 38 recovers quickly, since no reference signals are needed to achieve process tolerance. If the TN signal can be generated as quickly as data is generated for the inputs 12a-b, then the zero power mode may have the same TPD as the full power mode. FIGURE 3 illustrates a comparison of the rise and fall times of the sense amplifier of the present invention in comparison with the sense amplifier of the FIGURE 1b. As can be seen, the present invention provides very steep rise and fall times whereas the sense amplifier of FIGURE 1b has a very damped rise time. The present invention provides several technical advantages over the prior art. The rise time of the product line is minimized via a constant current source and the fall-time of the product line is minimized by removing the current source from the load. Since the transitions are optimized for speed, process variations will have little, if any, affect on the circuits total propagation delay. FIGURE 4 illustrates a simplified schematic representation of a programmable array logic (PAL) using the present invention. The PAL comprises a plurality of inputs connected to input buffers 56. Input buffers 56 have a TRUE output 58 and a FALSE output 60 (the inverted input). The outputs of the input buffers are connected to the input lines 16. Product lines 14 are connected to the input lines 16 via FAMOS transistors 12. Sense circuitry 38 is associated with each product line 14. The output of sense circuitry 38 is input to an OR gate 62 to provide an output signal (OUT). While the present invention has been described in conjunction with an EPAL, it may also be used with any design using FAMOS cells or other similar transistors to drive a node to a high or low logic level. Also, a powered CMOS gate may be able to improve its high-to-low transitions using this concept, since the N-channel pull-down transistors may pull the product line low with virtually no load. This would apply to any highly capacitive powered CMOS gate. Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by the appended claims.

Claims: A sense circuitry operable to detect the logic state of a sense node coupled to a plurality of programmable switches (12) selectively enabled by respective input signals, comprising: first voltage control circuitry (40) for selectively coupling the sense node to a first voltage source in response to a first control signal; feedback circuitry (44) for generating said first control signal which is such that said first voltage control circuitry (40) decouples the sense node from said first voltage source in response to said sense node reaching a predetermined voltage; and second voltage control circuitry (42) to maintain said predetermined voltage on said sense node until one of said programmable switches (12) is enabled, characterised in that said second voltage control circuitry (42) comprises a first N-channel FET (52), having a source and a drain disposed in a P-well and a gate, and second N-channel FET (54), having a source and a drain disposed in a P-well and a gate, the first and second N-Channel FET's being diode coupled and connected in series between said first voltage source and said sense node, and; zero power circuitry (55a,55b) operable to disable said first and said second voltage control circuitry in response to a second control signal (TN). A sense circuitry according to claim 1 wherein said first voltage control circuitry (40) comprises a P-channel transistor (50) having a gate connected to said feedback circuitry, a first source/drain connected to said voltage source and a second source/drain connected to said sense node. A sense circuitry according to claim 1 or claim 2 wherein said feedback circuitry comprises two inverters (46,48). A sense circuitry according to claim 3 wherein said feedback circuitry (44) comprises a first inverter (46) having an input coupled to the sense node and a second inverter (48) having an input connected to the output of said first inverter. A sense circuitry according to claim 4 wherein said first and second inverters have trip points such that said P-channel transistor (50) is disabled in response to said predetermined voltage. A sense circuitry according to any one of the preceding claims wherein the gate and a first source/drain terminal of said first N-channel transistor (52) is coupled to a voltage source, the second source/drain terminal of the first N-channel transistor is coupled to a first source/drain terminal of the second N-channel transistor (54) and the second source/drain terminal of the second N-channel transistor is coupled to the sense node. A sense circuitry according to any one of the preceding claims and further comprising an inverter (20) coupled to said sense node. A sense circuitry according to claim 1 wherein said programmable switches (12) comprise non-volatile memory cells. A sense circuitry according to claim 8 wherein said non-volatile memory cells comprise FAMOS transistors. A method of providing a rapid output transition responsive to an input transition, comprising the steps of: providing current to a product line (14) during a low-to-high output transition to rapidly increase the voltage on said product line; disabling said current provision when said product line is at a high logic level to prevent excessive voltage on said product line; maintaining said product line voltage using a voltage generator (42); reenabling said current source when said product line is at a low logic level; characterised by disabling said current provision and said product line voltage maintenance in response to a control signal. A method according to claim 10 wherein said step of providing current to said product line comprises the steps of enabling a P-channel FET current source coupled to said product line. A method according to claim 11 wherein said step of disabling said current source comprises the step of turning off said P-channel FET current source. A method according to any one of claims 10 to 12 wherein said step of maintaining the voltage on the product line comprises the step of generating a predetermined voltage across two N-channel FETs coupled between said product line and a voltage source.

Inventors: EDMONSON DANIEL D, WEBSTER WILLIAM STANLEY, EDMONSON, DANIEL D., WEBSTER, WILLIAM STANLEY
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1990
Main classification: G11C7
IPC codes: H03K19, G11C7, G11C16, G11C17