Data transfer system and method of transferring data

Abstract: This invention discloses a data transfer system comprising a data transfer apparatus (1) for transmitting clock signals (SCK₁) and binary serial data signals (SDT₁), a clock signal-tranfer line (2) connected to the data transfer apparatus (1), a data signal-transfer line (2a) connected to the data transfer apparatus (1), and at least one data receiving terminal unit (3) connected to the clock signal-transfer line (2) and data signal-transfer line (2a), the data receiving terminal unit (3) regarding the data signal (SDT₂) transmitted from data transfer apparatus (1) as a transfer start signal (START) when it detects that the data signal (SDT₂) transmitted at the time corresponding to the leading edge of the clock signal (SCK₂) transmitted from the apparatus (1) has the first logic level, and that the data signal (SDT₂) transmitted at the time corresponding to the trailing edge of the same has the second logic level, also regarding the data signal (SDT₂) as a transfer data signal when it detects that the data signal (SDT₂) transmitted at the time corresponding to the leading edge of the clock signal (SCK₂) has the same logic level as that transmitted at the time corresponding to the trailing edge of the same, and further regarding the data signal (SDT₂) as a transfer end signal (END) when it detects that the data signal (SDT₂) transmitted at the time corresponding to the leading edge of the clock signal (SCK₂) has the second logic level, and that the data signal (SDT₂) transmitted at the time corresponding to the trailing edge of the same has the first logic level.

Description: This invention relates to a data transfer system for use in, for example, a video tape recorder, which transfers data from a microcomputer incorporated in the recorder to an integrated circuit for controlling a servomotor incorporated therein. Published Unexamined Japanese Patent Application No. 57-106262 discloses two types of data transfer systems. The first type employs two transfer lines for transmitting a clock signal and a data signal, respectively. The second type is identical to the first type, except that it has one more line for controlling the start and finish of data transmission. More specifically, the first-type system comprises a data transfer apparatus for transmitting clock signals and binary serial-data signals, a bidirectional bus having two lines connected to the data transfer apparatus, and a plurality of data transfer/receiving terminal units connected to the bus. Each of the terminal units has two terminals, one for receiving a signal from the bidirectional bus, and the other for transmitting a signal in reply to the signal received. Since each of the data transfer/receiving terminal units requires transfer/receiving terminals connected to the bus, respectively, the system inevitably has a complex hardware structure. Further, the data transfer apparatus transmits a data signal which has identical logic levels at times corresponding to the leading and trailing edges of a clock signal, but does not transmit a sub-data signal which has logic levels temporarily inverted at any time between the leading and trailing edges of the clock signal. With this structure, it is impossible to transmit lots of data. On the other hand, the second-type system requires as many as three transfer lines. It is the object of the invention to provide a data transfer system which employs two transfer lines, and data receiving terminal units having only receiving terminals for the lines, resulting in a simple hardware structure, and to provide a data transfer method which enables the system of simple structure to accurately control the start and finish of data transmission. To attain the above object, the data transfer system of the invention comprises: a data transfer apparatus (1) for transmitting clock signals (SCK 1 ) and binary data signals (SDT 1 ), the data signals being transmitted in serial order, of which a signal transmitted at the start has a first logic level at a time corresponding to a leading edge of a clock signal (SCK 1 ) and a second logic level at a time corresponding to a trailing edge of the same, signals transmitted after the start have identical logic levels at times corresponding to the leading edge and trailing edge of the transfer clock signal, and a signal transmitted at the edge has the second level at the time corresponding to the leading edge of the clock signal and the first logic level at the time corresponding to the trailing edge of the same; a clock signal-tranfer line (2) connected to the data transfer apparatus (1); a data signal-transfer line (2a) connected to the data transfer apparatus (1); and at least one data receiving terminal unit (3) connected to the clock signal-transfer line (2) and data signal-transfer line (2a), the data receiving terminal unit (3) regarding the data signal (SDT 2 ) transmitted from data transfer apparatus (1) as a transfer start signal (START) when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) transmitted from the apparatus (1) has the first logic level, and that the data signal (SDT 2 ) transmitted at the time corresponding to the trailing edge of the same has the second logic level, also regarding the data signal (SDT 2 ) as a transfer data signal when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the same logic level as that transmitted at the time corresponding to the trailing edge of the same, and further regarding the data signal (SDT 2 ) as a transfer end signal (END) when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the second logic level, and that the data signal (SDT 2 ) transmitted at the time corresponding to the trailing edge of the same has the first logic level. According to another aspect of the invention, a method of transmitting data is provided which comprises the steps of: transmitting clock signals (SCK 1 ) from a data transfer apparatus (1) to at least one receiving terminal unit (3) connected to the apparatus (1) via a clock signal-transfer line (2); transmitting binary data signals (SDT 1 ) in serial order from the data transfer apparatus (1) to the receiving terminal unit (3) connected to the apparatus (1) via a data signal-transfer line (2a); making the data transfer apparatus (3) regard the data signal (SDT 2 ) transmitted from data transfer apparatus (1) as a transfer start signal (START) when the apparatus (3) detects that the data signal (SDT 2 ) transmitted at a time corresponding to a leading edge of a clock signal (SCK 2 ) transmitted from the apparatus (1) has a first logic level, and that the data signal (SDT 2 ) transmitted at a time corresponding to a trailing edge of the same has a second logic level; making the apparatus (3) regard the data signal (SDT 2 ) as a transfer data signal when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the same logic level as that transmitted at the time corresponding to the trailing edge of the same; and making the apparatus (3) regard the data signal (SDT 2 ) as a transfer end signal (END) when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the second logic level, and that the data signal (SDT 2 ) transmitted at the time corresponding to the trailing edge of the same has the first logic level. According to the invention constructed as above, the start time of data transmission, the end time thereof, and the time therebetween are determined by comparing logic levels of a data signal (SDT 2 ) assumed at times corresponding to the leading and trailing edges of a clock signal (SCK 2 ), so that the start and end of the data transmission can be controlled by using only two transfer lines (2, 2a). In addition, each data receiving terminal unit (3) has only receiving terminals connected to the transfer lines (2, 2a), resulting in a simple hardware structure. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram, showing a data transfer apparatus according to an embodiment of the present invention; A - D of Fig. 2 are waveform charts, showing the relationship between the logic levels of data signals transmitted from the data transfer apparatus shown in Fig. 1 and the leading/trailing edges of clock signals transmitted from the same; Fig. 3 is a circuit diagram of a data receiver shown in Fig. 1; Fig. 4 is a circuit diagram of another data receiver shown in Fig. 1; Fig. 5 is a waveform chart, showing the operation of data receiving terminal units shown in Figs. 3 and 4; Fig. 6 is a circuit diagram of a timing circuit shown in Figs. 3 and 4; and Fig. 7 is a waveform chart, showing the operation of the timing circuit shown in Fig. 6. The invention will now be explained in detail with reference to the accompanying drawings showing an embodiment thereof. Fig. 1 shows that data transfer system for use in, for example, a video tape recorder, which transmits data from a microcomputer incorporated in the recorder to an integrated circuit for controlling a servomotor incorporated therein. In the figure, reference numeral 1 denotes a data transfer apparatus for transmitting transfer clock signals SCK 1 and binary transfer data signals SDT 1 , reference numerals 2 and 2a a clock signal-transfer line and a data signal-transfer line, both connected to the data transfer apparatus 1, and reference numeral 3 a plurality of data-receiving terminal units for receiving the transfer clock signals SCK 1 and binary transfer data signals SDT 1 transmitted through the lines 2 and 2a. At the start of transmission of the transfer data signal SDT 1 , the data transfer apparatus 1 generates a transfer start signal START having logic levels which are different at times corresponding to the leading edge and trailing edge of a clock signal SCK 1 . During the transmission of the signal SDT 1 , the apparatus 1 generates, in serial order, signals SDT 1 having logic levels which are identical at times corresponding to the leading edge and trailing edge of each clock signal SCKP 1 . The logic level of the transfer data signal SDT 1 is usually inverted at a time between the trailing edge of a certain one of the transfer clock signals SCK 1 and the leading edge of the following one. At the end of transmission, the apparatus 1 generates a transfer end signal END having logic levels inverted at times corresponding to the leading edge and trailing edge of the clock signal SCK 1 . It should be noted that the logic level of the transfer end signal END changes in the opposite way to that of the transfer start signal START. The above-described structure of the data transfer apparatus 1 comprising a microcomputer or the like is known to those skilled in the art. A - D of Fig. 2 show four examples of the relationship between the logic level of the transfer data signal SDT 1 and the leading and trailing edges of the transfer clock signal SCK 1 . Specifically, A of Fig. 2 shows one example. In the figure, at the start of the transmission, the transfer data signal SDT 1 has a low level "L" at the rise of the transfer clock signal SCK 1 , and a high level "H" at the fall of the same. During the transmission, for example, a signal of low level "L" containing 2-bit data is transmitted, and then a signal of high level "H" containing 2-bit data is transmitted. At the end of the transfer, the level of the signal SDT 1 is high at the rise of the transfer clock signal SCK 1 , and becomes low at the fall of the same. B of Fig. 2 shows another example. At the start of the transmission, the level of the transfer data signal SDT 1 is high at the rise of the transfer clock signal SCK 1 , and becomes low at the fall of the same. During the transmission, for example, a signal of low level "L" containing 2-bit data is transmitted, and then a signal of high level "H" containing 2-bit data is transmitted. At the end of the transmission, the level of the signal SDT 1 is low at the rise of the transfer clock signal SCK 1 , and becomes high at the fall of the same. Further, as is shown in C of Fig. 2, at the start of the transfer, the level of the transfer data signal SDT 1 is low at the fall of the transfer clock signal SCK 1 , and becomes high at the rise of the same. During the transmission, for example, a signal of low level "L" containing 2-bit data is transmitted, and then a signal of high level "H" containing 2-bit data is transmitted. At the end of the transmission, the level of the signal SDT 1 is high at the fall of the transfer clock signal SCK 1 , and becomes low at the rise of the same. Finally, as is shown in D of Fig. 2, at the start of the transmission, the level of the transfer data signal SDT 1 is high at the fall of the transfer clock signal SCK 1 , and becomes low at the rise of the same. During the transmission, for example, a signal of low level "L" containing 2-bit data is transmitted, and then a signal of high level "H" containing 2-bit data is transmitted. At the end of the transmission, the level of the signal SDT 1 is low at the fall of the transfer clock signal SCK 1 , and becomes high at the rise of the same. In A - D of Fig. 2, if the logic level of the transfer data signal SDT 1 is temporarily inverted between the leading and trailing edges of the transfer clock signal SCK 1 , the data can be considered normal. The data-receiving terminal units 3 have signal-receiving terminals connected to the transfer lines 2 and 2a, and is constructed as follows: The transfer data signal SDT 1 and transfer clock signal SCK 1 transmitted from the data transfer apparatus 1 are hereinafter referred to as "received data signal SDT 2 " and "received clock signal SCK 2 ", respectively. When each data-receiving terminal unit 3 detects that the logic level of the received data signal SDT 2 has been changed from a first value to a second value between the leading edge and trailing edge of the received clock signal SCK 2 , the unit 3 regards the signal as the transfer start signal START, and starts to receive the following signals. Subsequently, when it detects that the logic level of the following received data signal SDT 2 is not changed between the leading edge and trailing edge of the received clock signal SCK 2 , it regards the signal as a received data signal D 0 . Further, when it detects that the logic level of the received data signal SDT 2 has been changed from the second value to the first value between the leading edge and trailing edge of the received clock signal SCK 2 , it regards the signal as the transfer end signal END. Fig. 3 shows an example of the data receiving terminal unit 3 comprising an integrated circuit. Reference numerals 30 and 30a denote a clock-receving terminal and a data-receiving terminal which are connected to the transfer lines 2 and 2a, respectively. A timing circuit 31 receives the clock signal SCK 2 and serial data signal SDT 2 through the receiving terminals 30 and 30a. Upon detection of the transfer start signal START, the circuit 31 starts to receive the following signals. Then, upon receipt of the following clock signal SCK 2 and serial data signal SDT 2 , it generates clock signals SCKA and a data signals SDTA. Further, upon detection of the transfer end signal END, it stops generating the signals SCKA and SDTA, and simultaneously activates a latch signal LATCH. A shift register 32 receives the data signals SDTA in serial order and in synchronism with the respective leading edges of the clock pulses SCKA. Upon activation of the latch signal LATCH, a latch circuit 33 latches the data transmitted from the shift register 32, also decodes the serial data to parallel data, and further transmits them to a circuit contained in the integrated circuit. As is shown in Fig. 4, the data receiving terminal unit 3 may be modified such that it detects the number of bits of data transmitted from the generation of the transfer start signal START to that of the transfer end signal END by counting the clock signals SCKA by means of a counter 34, and receives the transfer data only if the number of the bits counted meets a predetermined value. In this case, a plurality of data receiving terminal units 3 can select respective particular data, if each unit is set to receive that signal of a particular number of bits which indicates a corresponding data. Fig. 5 shows the operation of the data receiving terminal unit 3 performed when it receives those clock signals SCK 1 and serial data signals SDT 1 which are transmitted from the data transfer apparatus 1 at the timing shown in A of Fig. 2. The unit 3 regards the received data signal SDT 2 as the transfer start signal START when it detects that the level of the signal SDT 2 has changed from the "L" level to the "H" level between the leading edge and trailing edge of the received clock signal SCK 2 . Upon generation of the signal START, the latch signal LATCH is made inactive. Then, the received data signal SDT 2 is regarded as the transfer data signal D 0 while the unit 3 detects that the level of the signal SDT 2 is unchanged between the leading edge and trailing edge of the received clock signal SCK 2 . The transfer data signals D 0 - Dn are output after the transfer start signal START is inactivated. The signal SDT 2 is regarded as the transfer end signal END when the level of the signal SDT 2 is detected to change from the "H" level to the "L" level between the leading edge and trailing edge of the received clock signal SCK 2 , thereby activating the latch signal LATCH. The hatched portions shown in Fig. 5 indicates time periods in which the logic level is maintained as it is. Fig. 6 shows a specific structure of the timing circuit 31 shown in Fig. 3. Reference numerals 51 - 54 denote D-type flip-flop circuits, numerals 55 and 56 inventors, numeral 57 an AND gate having two input terminals, numeral 58 a NOR gate having two input terminals, numerals 59 and 60 NOR gates each having two input terminals and one output terminal, and numeral 61 a NOR gate having three input terminals. The output terminal of one of the NOR gates is connected to one of the input terminals of the other NOR gate, while the output terminal of the second-mentioned gate is connected to one of the input terminals of the first-mentioned gate. The first flip-flop circuit 51 has a data input terminal D for receiving the data signal SDT 2 , a clock input terminal CK for receiving an inverted clock signal SCK obtained by inverting the received clock signal SCK 2 by the invertor 55, and an output terminal Q for outputting the data signal SDTA. The second flip-flop circuit 52 has a data input terminal D for receiving the data signal SDT 2 , a clock input terminal CK for receiving the clock signal SCK 2 , and an output terminal Q. A signal A output from the terminal Q is inverted by the invertor 56, and then input into the AND gate 57, together with the received data signal SDT 2 . The output from the invertor 56 is input into the NOR gate, together with the received data signal SDT 2 . The third flip-flop circuit 53 has a data input terminal D for receiving the output of the AND gate 57, a clock input terminal CK for receiving the inverted clock signal SCK , and an output terminal Q for outputting a signal B (the transfer start signal START). The signal B is input into the NOR gate 61, together with the inverted clock signal SCK . The fourth flip-flop circuit 54 has a data input terminal D for receiving the output of the NOR gate, a clock input terminal CK for receiving the inverted clock signal SCK , and an output terminal Q for outputting the latch signal LATCH. One of the two input terminals of the NOR gate 59 receives the latch signal LATCH (transfer end signal END), and one of two input terminals of the NOR gate 60 receives the signal B (transfer start signal START). The output of the NOR gate 60 is input into the NOR gate 61, which in turn outputs the clock signal SCKA. Fig. 7 shows waveforms useful in explaining the operation of the timing circuit 31 shown in Fig. 6. The circuit 31 starts signal reception upon detection of the transfer start signal START. Subsequently, it generates, upon detection of the received clock signal SCK 2 and serial data signals SDT 2 , the clock signal SCKA (having the same phase as the clock signal SCK) and the data signal SDTA (this signal is 180°, out of phase with respect to the clock signal SCK, and varies at the time corresponding to the trailing edge of the clock signal SCK). Then, when the circuit 31 detects the transfer end signal END, it stops the generation of the clock signal SCKA and data signal SDTA, and simultaneously activates the latch signal LATCH. In the above-described embodiment, although the data signal SDT 1 is transmitted which has logic levels being identical between the leading edge and trailing edge of the transfer clock signal SCK 1 , the present invention can be modified, as shown in A - D of Fig. 2, such that the transfer apparatus 1 transmits a sub-data SBD whose logic level is inverted temporarily between the leading and trailing edges of the transfer clock signal SCK 1 , and the receiving terminal unit 3 detects whether or not the data signal is temporarily inverted therebetween, thereby enabling the transmission of the sub-data SBD, as well as the main data SDT. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A data transfer apparatus characterized by comprising: a data transfer means (1) for transmitting clock signals (SCK 1 ) and binary data signals (SDT 1 ), the data signals being transmitted in serial order, of which a signal transmitted at the start has a first logic level at a time corresponding to a leading edge of a clock signal (SCK 1 ) and a second logic level at a time corresponding to a trailing edge of the same, signals transmitted after the start have identical logic levels at times corresponding to the leading edge and trailing edge of the clock signal, and a signal transmitted at the end has the second level at the time corresponding to the leading edge of the clock signal and the first logic level at the time corresponding to the trailing edge of the same; a clock signal-tranfer line (2) connected to the data transfer means (1); a data signal-transfer line (2a) connected to the data transfer means (1); and at least one data receiving terminal unit (3) connected to the clock signal-transfer line (2) and data signal-transfer line (2a), the data receiving terminal unit (3) regarding the data signal (SDT 2 ) transmitted from data transfer means (1) as a transfer start signal (START) when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) transmitted from the data transfer means (1) has the first logic level, and that the data signal (SDT 2 ) transmitted at the time corresponding to the trailing edge of the same has the second logic level, also regarding the data signal (SDT 2 ) as a transfer data signal when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the same logic level as that transmitted at the time corresponding to the trailing edge of the same, and further regarding the data signal (SDT 2 ) as a transfer end signal (END) when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the second logic level, and that the data signal (SDT 2 ) transmitted at the time corresponding to the trailing edge of the same has the first logic level. The apparatus according to claim 1, characterized in that the receiving terminal unit (3) comprises a timing circuit (31) for receiving the clock signals (SCK 1 ) and the data signals (SDT 1 ) which are transmitted from the data transfer means (1) through the clock signal-transfer line (2) and the data signal-transfer line (2a), respectively, the timing circuit (31) starting data reception upon detection of the transfer start signal (START), also generating clock signals (SCKA) and data signals (SDTA) corresponding to the received clock signals (SCK 2 ) and the received data signals (SDT 2 ) upon detection thereof, and further stopping the generation of the clock signals (SCKA) and the data signals (SDTA) upon detection of the transfer end signal (END), and simultaneously activating a latch signal (LATCH), the system further comprising a shift register (32) for receiving the data signals (SDTA) in serial order at times corresponding to the leading edge of the clock signal (SCKA), and a latch circuit (33) for latching data transmitted from the shift register (32) upon activation of the latch signal (LATCH), and decoding the serial data into parallel data. The apparatus according to claim 2, characterized in that the receiving terminal unit (3) further comprises a counter (34) for counting the clock signals (SCKA) generated by the timing circuit (31), thereby detecting the number of bits of data transmitted from the time at which the transfer start signal (START) is detected to the time at which the transfer end signal (END) is detected, and the receiving terminal unit (3) receives the data signals (SDT 1 ) transmitted from the data transfer means (1) only if the bit number detected is a predetermined value. A method of transmitting data, comprising the steps of: transmitting clock signals (SCK 1 ) from a data transfer means (1) to at least one receiving terminal unit (3) connected to the data transfer means (1) via a clock signal-transfer line (2); transmitting binary data signals (SDT 1 ) in serial order from the data transfer means (1) to the receiving terminal unit (3) connected to the data transfer means (1) via a data signal-transfer line (2a); making the receiving terminal unit (3) regard the data signal (SDT 2 ) transmitted from data transfer means (1) as a transfer start signal (START) when the receiving terminal unit (3) detects that the data signal (SDT 2 ) transmitted at a time corresponding to a leading edge of a clock signal (SCK 2 ) transmitted from the data transfer means (1) has a first logic level, and that the data signal (SDT 2 ) transmitted at a time corresponding to a trailing edge of the same has a second logic level; making the receiving terminal unit (3) regard the data signal (SDT 2 ) as a transfer data signal when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the same logic level as that transmitted at the time corresponding to the trailing edge of the same; and making the receiving terminal unit (3) regard the data signal (SDT 2 ) as a transfer end signal (END) when it detects that the data signal (SDT 2 ) transmitted at the time corresponding to the leading edge of the clock signal (SCK 2 ) has the second logic level, and that the data signal (SDT 2 ) transmitted at the time corresponding to the trailing edge of the same has the first logic level. The method according to claim 4, characterized in that the receiving terminal unit (3) comprises a timing circuit (31) for receiving the clock signals (sCK 1 ) and the data signals (SDT 1 ) which are transmitted from the data transfer means (1) through the clock signal-transfer line (2) and the data signal-transfer line (2a), respectively, the timing circuit (31) starting data reception upon detection of the transfer start signal (START), also generating clock signals (SCKA) and data signals (SDTA) corresponding to the received clock signals (SCK 2 ) and the received data signals (SDT 2 ) upon detection thereof, and further stopping the generation of the clock signals (SCKA) and the data signals (SDTA) upon detection of the transfer end signal (END), and simultaneously activating a latch signal (LATCH), the system further comprising a shift register (32) for receiving the data signals (SDTA) in serial order at times corresponding to the leading edge of the clock signal (SCKA), and a latch circuit (33) for latching data transmitted from the shift register (32) upon activation of the latch signal (LATCH), and decoding the serial data into parallel data. The method according to claim 5, characterized in that the receiving terminal unit (3) further comprises a counter (34) for counting the clock signals (SCKA) generated by the timing circuit (31), thereby detecting the number of bits of data transmitted from the time at which the transfer start signal (START) is detected to the time at which the transfer end signal (END) is detected, and the receiving terminal unit (3) receives the data signals (SDT 1 ) transmitted from the data transfer means (1) only if the bit number detected is a predetermined value.

Inventors: ITO HIDEAKI, ITO, HIDEAKI, ITO, HIDEAKI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G06F13
IPC codes: G06F13, H04L7, H04L29