Methods of manufacturing MIS semiconductor devices

Abstract: A method of manufacturing a MIS semiconductor device having at least a portion of a drain region which contacts a channel and has a relatively low impurity concentration to obtain an LDD structure, wherein an insulating film (26) is formed on at least a surface of a semiconductor substrate (11) or double side walls (17,27) are formed on a gate electrode (13), the surface is oxidized, and in this state, an impurity region (25) having a relatively high impurity concentration is formed.

Description: This invention relates to methods of manufacturing MIS semiconductor devices. A method of manufacturing an MIS semiconductor device having an LDD structure is described in "Monthly Semiconductor World" (1987, February) pages 94 to 100. This method includes steps as shown in Figures 1A to 1C. As shown in Figure 1A, an SiO 2 film 12 serving as a gate insulating film is formed on an Si substrate 11, and a gate electrode 13 is formed on the SiO 2 film 12. The gate electrode 13 has a polycide structure formed by a polycrystalline Si film 14 and a WSi x film 15. Thereafter, phosphorus ions 16 for forming an n - type region for a source/drain region are implanted in the Si substrate 11 using the gate electrode 13 as a mask. As shown in Figure 1B, an SiO 2 film 17 is deposited by atmospheric-pressure, low-temperature (about 410 o C) CVD using monosilane or the like. The SiO 2 film 17 is etched by RIE to form side walls of the gate electrode 13 using the SiO 2 film 17. Thermal oxidation is performed for the resultant structure respectively to form SiO 2 films 21 and 22 on the surfaces of the Si substrate 11 and the WSi x film 15. The SiO 2 film 21 is used for preventing a decrease in gate breakdown voltage at the edge of the gate electrode 13. Thereafter, arsenic ions 23 for forming an n + type region for a source/drain region are implanted in the Si substrate 11 using the gate electrode 13 and the SiO 2 film 17 as masks. As shown in Figure 1C, annealing is performed to the resultant structure to form n - type regions 24 and n + type regions 25 serving as source/drain regions. The thermal oxidation for forming the SiO 2 films 21 and 22 is performed at a temperature within the range of 850°C to 900 o C. In an MIS transistor having a gate length of about 0.8 µm, however, when the high-temperature thermal oxidation is performed for a long time, the junction depth is undesirably increased. Therefore, since the thermal oxidation cannot be sufficiently performed, each of the SiO 2 films 21 and 22 has a thickness of about 10 nm. When the SiO 2 film 21 has such a small thickness, the Si substrate 11 is substantially damaged during ion implantation of the arsenic 23. Therefore, crystal defects easily occur in the Si substrate 11. For this reason, degradation in device characteristics such as an increase in leakage current through a junction occurs, and the production yield is decreased. In addition, since the RIE for forming the SiO 2 films 17 serving as the side walls of the gate electrode 13 causes damage to the surfaces of the Si substrate 11 and the WSi x film 15, the SiO 2 films 21 and 22 are difficult to grow. For this reason, the thickness of the SiO 2 film 21 is small, and the above problem of easy formation of crystal defects in the Si substrate 11 typically occurs. According to the present invention there is provided a method of manufacturing an MIS semiconductor device, the method comprising the steps of: forming a gate electrode on a gate insulating film on a silicon semiconductor substrate; forming a first impurity region having a relatively low impurity concentration in said substrate using said gate electrode as a mask; forming side walls on said gate electrode; forming a first SiO 2 film to cover exposed surfaces of said substrate, said side walls and said gate electrode; oxidizing at least the surface of said first SiO 2 film over said substrate to form a second SiO 2 film on the first SiO 2 film; and forming a second impurity region having a relatively high impurity concentration in said substrate using said gate electrode and side walls covered with said first SiO 2 film as a mask. In a method according to the present invention, after the first SiO 2 film (insulating film) has been formed on the side walls, the gate electrode and the surface of the semiconductor substrate, the surface is oxidized. Therefore, upon formation of the second impurity region having a relatively high impurity concentration in the semiconductor substrate, the semiconductor substrate is only slightly damaged even if the oxide layer is thin, and crystal defects tend not be formed in the semiconductor substrate. Since the oxide layer is formed in addition to the first SiO 2 film (insulating film), a decrease in gate breakdown voltage at the edge portion of a gate electrode can be prevented. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figures 1A to 1C are sectional side views showing the steps in manufacturing an MIS semiconductor device by a previously proposed method; Figures 2A to 2D are sectional side views showing the steps in manufacturing an MIS semiconductor device according to a first embodiment of the present invention; and Figure 3 is a graph showing step coverage in an MIS semiconductor device. In the first embodiment, as shown in Figure 2A, an SiO 2 film 12, a polycrystalline Si film 14 and a WSi x film 15 are formed on an Si substrate 11, and phosphorus ions 16 are implanted in the Si substrate 11. The same procedures as in Figures 1A to 1C are performed until an SiO 2 film 17 is formed on the Si substrate 11. In the first embodiment, as shown in Figure 2B, an SiO 2 film 26 having a thickness of 10 to 30 nm is deposited on the surfaces of the Si substrate 11 and the WSi x film 15 by low-pressure, high-temperature (about 700°C) CVD using TEOS (tetraethylorthosilicate) or the like. With this CVD, the deposition rate can be decreased. Therefore, the SiO 2 film 26 having a small thickness can be deposited with good controllability. The same procedures as in Figures 1A to 1C are performed. That is, as shown in Figure 2C, SiO 2 films 21 and 22 are formed, and arsenic ions 23 are implanted. As shown in Figure 2D, an n - type region 24 and an n + type region 25 are formed by annealing. In this first embodiment, since the SiO 2 film 26 is formed in addition to the SiO 2 film 21, even if the SiO 2 film 21 has a small thickness of about 10 nm as shown in Figures 1A to 1D, the Si substrate 11 is only slightly damaged during implantation of the arsenic ions 23. Therefore, crystal defects tend not to occur in the Si substrate 11. Thus an MIS semiconductor device having excellent characteristics can be manufactured at a high yield. The WSi x film 15 in an amorphous state is crystallized by heat generated during formation of the SiO 2 films 21 and 22, and the protection capability of the WSi x film 15 against ion implantation is degraded. Therefore, when only the SiO 2 film 22 having the thickness of about 10 nm is formed on the surface of the WSi x film 15 like in Figure 1B or 1C, the arsenic ions 23 easily reach a channel portion through the gate electrode 13 during implantation of the arsenic ions 23. However, in the first embodiment, in addition to the SiO 2 film 22, the SiO 2 film 26 is formed on the WSi x film 45. Therefore, the arsenic ions 23 cannot reach the channel portion through the gate electrode 13. Since the temperature of the low-pressure, high-temperature CVD for forming the SiO 2 film 26 is lower than that of thermal oxidation, junction depth is not increased even when the SiO 2 film 26 is formed. The second embodiment has substantially the same steps as in the first embodiment, except that SiO 2 films 17 serving as the side walls of a gate electrode 13 are formed by low-pressure, high-temperature CVD using TEOS or the like, and an SiO 2 film 26 is formed by atmospheric-pressure, low-temperature CVD. When the SiO 2 films 17 are formed by atmospheric-pressure, low-temperature CVD like the first embodiment, step coverage of the SiO 2 film 17 is good at a low-density pattern region such as a peripheral circuit portion, but is poor at a high-density pattern region such as a memory cell. Figure 3 shows the step coverage of the SiO 2 film 17. Therefore, when RIE is performed for the SiO 2 film 17, portions of the SiO 2 film 17 except for the side walls of the gate electrode 13 on the surface of the Si substrate 11 is removed from the memory cell due to poor step coverage. At this time, the SiO 2 film 17 is left on the peripheral circuit portion. If the RIE is stopped at this time, and then the arsenic ions 23 are implanted, the arsenic ions 23 do not reach deeply into the Si substrate 11 at the peripheral circuit portion. Therefore, an impurity diffusion layer has a high sheet resistance. In order to avoid this, the RIE must be performed until the SiO 2 film 17 is removed from the surface of the Si substrate 11 except for the side walls of the gate electrode 13, even in the peripheral circuit portion. However, in this case, the memory cell is excessively over-etched. When such over-etching occurs, the Si substrate 11 is frequently damaged. Therefore, crystal defects easily occur in the Si substrate 11 resulting in an inferior memory cell. In contrast to this, with the second embodiment, since the SiO 2 film 17 is formed by low-pressure, high-temperature CVD using TEOS or the like, the SiO 2 film 17 has good step coverage even in a high-density pattern region. With the second embodiment, an MIS semiconductor device having more excellent characteristics than those of the first embodiment can be manufactured at a higher yield than the first embodiment. Note that, when both the SiO 2 films 17 and 26 are formed by low-pressure, high temperature CVD, the WSi x film 15 is heated twice to a high temperature of 600 o C or more while the WSi x film 15 is exposed, thereby easily peeling the WSi x film 15 from a polycrystalline Si film 14. However, since the SiO 2 film 26 is formed by atmospheric-pressure, low-temperature CVD, the WSi x film 15 is not peeled from the polycrystalline Si film 14. In the third embodiment a semiconductor device is manufactured following substantially the same procedures as in the second embodiment except that, when an SiO 2 film 17 is not left on the surface of an Si substrate 11 in a high-density pattern region such as a memory cell except for the side walls of a gate electrode 13, RIE applied to the SiO 2 film 17 is stopped and the SiO 2 film 17 remaining in a low-density pattern region such as a peripheral circuit portion at this time is removed by post wet etching. A stop time of the RIE applied to the memory cell or the like can be detected using an end point detector for etching. When wet etching is performed as in the third embodiment, the Si substrate 11 is not damaged. In addition, since the etching amount is about several tens of nm, the shapes of the SiO 2 films 17 of the side walls of the gate electrode 13 are almost not affected. Therefore, with the third embodiment, an MIS semiconductor device having more excellent characteristics than those of the second embodiment can be manufactured at a yield higher that the second embodiment. When the SiO 2 film 17 is formed by atmospheric-pressure, low-temperature CVD instead of low-pressure, high-temperature CVD using TEOS or the like as in the third embodiment, cavities are undesirably formed in the shoulder portions of the SiO 2 film 17. In the fourth embodiment, a memory device having a memory cell in which each interval between gate electrodes 13 falls within the range of 1.4 to 3.6 µm and a peripheral circuit portion in which each interval between gate electrodes 13 is more than 3.6 µm is manufactured. In the fourth embodiment, an SiO 2 film 17 is deposited by atmospheric-pressure, low-temperature CVD using monosilane or the like, and RIE applied to the SiO 2 film 17 is absent in a 3.6µm interval between the gate electrodes 13 on the surface of an Si substrate 11, except for the side walls of the gate electrode 13. Thereafter, the memory cell is masked by a resist film. In order to remove a portion of the SiO 2 film 17 from the surface of the Si substrate 11, which corresponds to a peripheral circuit portion and excludes portions left on side walls of the gate electrode 13, the RIE is started again.

Claims: A method of manufacturing an MIS semiconductor device,the method comprising the steps of: forming a gate electrode (13) on a gate insulating film (12) on a silicon semiconductor substrate (11); forming a first impurity region (24) having a relatively low impurity concentration in said substrate (11) using said gate electrode (13) as a mask; forming side walls (17) on said gate electrode (13); forming a first SiO 2 film (26) to cover exposed surfaces of said substrate (11), said side walls (17) and said gate electrode (13); oxidizing at least the surface of said first SiO 2 film (26) over said substrate (11); to form a second SiO 2 film (21) on the first SiO 2 film (26); and forming a second impurity region (25) having a relatively high impurity concentration in said substrate (11) using said gate electrode (13) and side walls (17) covered with said first SiO 2 film (26) as a mask. A method according to claim 1, wherein the thickness of said first SiO 2 film (26) falls within a range of 10 to 30 nm and the thickness of said second SiO 2 film (21) is about 10 nm. A method according to claim 2, wherein said side walls (17) are formed from an SiO 2 film (17) deposited by atmospheric-pressure, low-temperature CVD using monosilane to cover the surfaces of said substrate (11) and said gate electrode (13), and the first SiO 2 film (26) is deposited by low-pressure, high-temperature CVD using tetraethylorthosilicate. A method according to claim 3, wherein to form said side walls (17) said deposited SiO 2 film (17) is partially removed by reactive ion etching to expose at least a portion of said substrate (11); a coating layer is formed on a region where said substrate (11) is exposed; and said deposited SiO 2 film (17) is further removed by reactive ion etching using said coating layer as a mask to form said side walls (17). A method according to claim 2, wherein said side walls are formed from an SiO 2 film (17) deposited by low-pressure, high-temperature CVD using tetraethylorthosilicate to cover the surfaces of said gate electrode (13) and said substrate (11), and the first SiO 2 film (26) is deposited by atmospheric-pressure, low-temperature CVD using monosilane. A method according to claim 5, wherein to form said side walls (17) said deposited SiO 2 film (17) is partially removed by reactive ion etching to expose at least a portion of said substrate (11) and said deposited SiO 2 film (17) is further removed by wet etching to form said side walls (17).

Inventors: HOSHI NAOYA, ITO SHINICHI, OKAMOTO YUTAKA, HOSHI, NAOYA, ITO, SHINICHI, OKAMOTO, YUTAKA, HOSHI, NAOYA, C/O PATENTS DIVISION, ITO, SHINICHI, C/O PATENTS DIVISION, OKAMOTO, YUTAKA, C/O PATENTS DIVISION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: H01L21
IPC codes: H01L21, H01L29