A dynamic type semiconductor memory

Abstract: A dynamic type semiconductor memory in which a bit line is made to be connected to an electric potential different from a precharge potential after a precharge of the bit line is effected and one of word lines is selected and before a sensing amplifier operates. Thereby, all data stored in memory cells of the same row address can be cleared or preset in a cycle. Further, data stored in all of memory cells of which the number is equal to that of row addresses multiplied by that of column addresses can be cleared or preset in cycles of which the number is equal to that of the row addresses. Consequently, a clearance of contents of or a presetting of all memory cells can be effected at a high speed.

Description: This invention generally relates to a dynamic type semiconductor memory. Recently, with high integration of semiconductor integrated circuits, development of a mass storage has been promoted. Especially, dynamic type semiconductor memories have been utilized in various fields because of the advantageousness of realization of a mass storage and the low cost per bit. Generally, a semiconductor memory is fabricated by arranging memory cells like a matrix. (This matrix-like arrangement of the memory cells will be referred to as a memory-cell matrix). Further, when a semiconductor memory is operated, a specific one of the memory cells is first selected according to an externally given address and thereafter data is read from or written to the selected memory cell. The selection of a specific memory cell is performed by first dividing the externally given address into an address for selecting one of rows of the memory-cell matrix (hereunder referred to simply as a row address) and an address for selecting one of columns of the matrix (hereunder referred to simply as a column address) and further selecting a row of the memory-cell matrix (hereunder referred to as a word line) in accordance with a row address. Thereby, data stored in each of the memory cells on the word line is transmitted on a column of the memory-cell matrix (hereunder referred to as a bit line) connected thereto. In case of the dynamic type semiconductor memory, since capacity of each memory cell is very small, change in electric potential of each bit line is also very small. Thus, a sense amplifier is connected to each of the bit lines. A read operation of reading data stored in a memory cell is effected by amplifying a very small change in electric potential of a corresponding bit line. Further, when data is written to a memory cell, a write operation is effected by forcedly applying data from an external circuit to a bit line, which is selected as above described, after the read operation is performed. Incidentally, operations of reading data from and writing data to memory cells of the same row address are succeedingly effected in a relatively short time by changing a column address of a memory cell which data is read from or written to, with a word line selected. However, in such a conventional dynamic type semiconductor memory, data can be written only to a memory cell of a specific address in a cycle (hereunder sometimes referred to as a write-operation cycle). It is therefore necessary for writing data to all of the memory cells to perform write operations in cycles of which the number is equal to that of all addresses (i.e., the number of row addresses multiplied by the number of column addresses). For example, in the case of a conventional dynamic type semiconductor memory of which the capacity is one mega byte, write operations corresponding to 1,048,576 cycles need to be performed. Similarly, in the case where data stored in all of the memory cells is cleared (reset or preset), since only a memory cell corresponding to one address can be cleared (reset or preset) in a write-operation cycle, it is necessary to perform write operations corresponding to write-operation cycles of which the number is that of all addresses. Moreover, in the case where data stored in the memory cells arranged on the same word line is cleared (reset or preset), it is similarly necessary to perform write operations corresponding to write-operation cycles of which the number is that of column addresses. This is a large obstacle to an increase in operating speed of an entire system employing the conventional dynamic type semiconductor memory. EP-A-0,321,847 discloses a semiconductor memory in which data stored in all the memory cells with the same row address can be cleared (rest or preset) simultaneously, but in which "sense amplifiers" must also work to complete this operation. Pat. Abstr. of Japan, vol.11, no.107, (p-563) 4 April 1987, and JP-A-61,253,695 which forms the basis for the preamble of claim 1 disclose a semiconductor memory in which many memory cells can be reset simultaneously, but the memory cells cannot be preset simultaneously. The present invention is created to obviate the above described defect of the conventional dynamic type semiconductor memory. It is therefore an object of the present invention to provide an improved dynamic type semiconductor memory. In accordance with the present invention, there is provided a dynamic type semiconductor memory comprising: a plurality of pairs of bit lines; a plurality of memory cells connected to the plurality of bit lines; first connecting means for connecting a first line of each pair of bit lines to a first electric potential and for charging up the first line to the first electric potential; second connecting means for connecting a second line of each pair of bit lines to a second electric potential and for charging up the second line to the second electric potential; third connecting means for connecting the first line to the second electric potential and for charging up the first line to the second electric potential; and fourth connecting means for connecting the second line to the first electric potential and for charging up the second line to the first electric potential. According to an embodiment, the present invention provides a dynamic type semiconductor memory wherein the first connecting means responds to a reset signal, the second connecting means responds to the reset signal, the third connecting means responds to a preset signal, and the fourth connecting means responds to the preset signal. According to another embodiment, the present invention provides a dynamic type semiconductor memory wherein the first connecting means responds to a first reset signal, and the second connecting means responds to a second reset signal, the third connecting means responds to a first preset signal and the fourth connecting means responds to a second preset signal. According to another embodiment, the present invention provides a dynamic type semiconductor memory wherein the phase of the first reset signal is opposite to that of the second reset signal, and the phase of the first preset signal is opposite to that of the second preset signal. It is an advantage that all data stored in memory cells of the same row address can be cleared (reset or preset) in a cycle. A further advantage of this invention is that a reset or a preset operation can be performed and it is not necessary to operate a sense amplifier to complete these operations. Consequently, a clearance of contents of (resetting or presetting of) all memory cells can be effected at a high speed. The features, objects and advantages of the present invention will become apparent from the following description of a preferred embodiment with reference to the drawings, which are given by way of example only, in which like reference characters designate like or corresponding parts throughout several views, and in which: Fig.1 is a circuit diagram of a dynamic type semiconductor memory not according to the present invention; Fig.2 is a timing chart for illustrating a resetting operation of the dynamic type semiconductor memory of Fig.1 in the case where a memory cell connected to a bit line BL is selected; Fig.3 is a timing chart for illustrating a resetting operation of the dynamic type semiconductor memory of Fig.1 in the case where a memory cell connected to a bit line NBL is selected; Fig.4 is a timing chart for illustrating a presetting operation of the dynamic type semiconductor memory of Fig.1 in the case where a memory cell connected to a bit line BL is selected; Fig.5 is a timing chart for illustrating a presetting operation of the dynamic type semiconductor memory of Fig.1 in the case where a memory cell connected to a bit line NBL is selected; Fig.6 is a circuit diagram of a dynamic type semiconductor memory not according to the present invention; Fig.7 is a circuit diagram of an embodiment of the present invention (i.e., a dynamic type semiconductor memory embodying the present invention); Fig.8 is a timing chart for illustrating a resetting operation of the embodiment of Fig.7 in the case where a memory cell connected to a bit line BL is selected; Fig.9 is a timing chart for illustrating a resetting operation of the embodiment of Fig.7 in the case where a memory cell connected to a bit line NBL is selected; Fig.10 is a timing chart for illustrating a presetting operation of the embodiment of Fig.7 in the case where a memory cell connected to a bit line BL is selected; and Fig.11 is a timing chart for illustrating a presetting operation of the embodiment of Fig.7 in the case where a memory cell connected to a bit line NBL is selected. Hereinafter, a preferred embodiment of the present invention will be described in detail by referring to the accompanying drawings. First, to assist in understanding the present invention, a circuit not according to the present invention will be described hereinbelow by referring to FIGS. 1 to 5. Referring first to FIG. 1, there is shown only a part of a dynamic type semiconductor memory, in which two bit lines BL and NBL and two word lines VL11 and WL12 intersect. As shown in this figure, a memory cell A11 consists of a capacitor C11 and a transistor Q11. An end of the capacitor C11 is connected to a cell plate voltage (VCP). Further, a drain and a gate of the transistor Q11 are connected to the bit line BL and the word line WL11, respectively. Moreover, a memory cell A12 consists of a capacitor C12 and a transistor Q12. An end of the capacitor C12 is connected to the cell plate voltage (VCP). Further, a drain and a gate of the transistor Q12 are connected to the bit line NBL and the word line WL12, respectively. An end of the bit line BL is connected to a bit-line precharge voltage line (VBP) by way of a transistor Q13. Moreover, an end of the bit line NBL is connected to the bit-line precharge voltage line VBP through a transistor Q14. The two bit lines BL and NBL are connected to each other through a transistor Q15. Furthermore, a bit-line precharge signal  BP is supplied to gates of the transistors Q13, Q14 and Q15. On the other hand, the other end of the bit line BL is connected to an input terminal of a data output amplifier DOA through a transistor Q16. Further, the other end of the bit line NBL is connected to the other input of the data output amplifier DOA through a transistor Q17. A bit-line selecting signal  B is supplied to gates of these transistors Q16 and Q17. A sense amplifier SA comprised of four transistors Q₂₂∼Q₂₅ is connected to both of the two bit lines BL and NBL. Further, a transistor Q₂₆ which is turned on and off by an enable pulse  SAP is connected to both of and is positioned between the sense amplifier SA and a power source having an electric potential Vcc. Moreover, a transistor Q₂₇ which is turned on and off by an enable pulse  SAN is connected to and is positioned between the sense amplifier SA and a ground having a reference potential Vss. Furthermore, input data DIN to be written to the memory cells A11 and A12 is amplified by a data input amplifier DIA and is then supplied to the two bit lines BL and NBL. On the other hand, data read out from the memory cells A11 and A12 is supplied to the data output amplifier DOA through the two bit lines BL and NBL and thereafter the read-out data is outputted from an output terminal DOUT. The data input amplifier DIA is activated when a voltage level of an enable pulse  IN becomes high (hereunder abbreviated as "H") in a write-operation cycle. Further, a voltage level of an enable pulse  OUT is low (hereunder abbreviated as "L") in a write-operation cycle, so that the data output amplifier DOA is inactive. Contrarily, in a cycle in which a read operation is effected (hereunder sometimes referred to as a read-operation cycle), a voltage level of an enable pulse  IN is "L" and a voltage level of an enable pulse  OUT is "H". Thus, in a read-operation cycle, the data input amplifier DIA is inactive and on the other hand the data output amplifier DOA is active. A characteristic feature of the circuit of FIG. 1 resides in that an N-channel transistor Q₁₈ is connected to both of and is positioned between the bit line BL and the ground having the reference potential Vss and moreover another N-channel transistor Q₁₉ is connected to both of and is provided between the other bit line NBL and the ground having the reference potential Vss. Incidentally, a reset signal  R is supplied to a gate of the transistor Q₁₈. and on the other hand a preset signal  P is supplied to a gate of the transistor Q₁₉. Next, an operation of the circuit of FIG. 1 will be described hereinafter by referring to FIGS. 2∼5. First, when a voltage level of a bit-line precharge signal  BP becomes "H", the bit lines BL and NBL are pre-charged up to a bit-line pre-charge potential VBP through the transistors Q₁₃ and Q₁₄ and further is equalized through the transistor Q₁₅. Thereafter, when the pre-charge of the bit lines BL and NBL is completed, a word line is selected in accordance with an externally given row address. Here, will be described an operation of the circuit of Fig.1 in the case where the word line WL11 is selected. When a voltage level of the word line WL11 becomes "H", electric charge accumulated in the capacitor C11 is transferred to the bit line BL through the transistor Q11. Further, if a voltage level of an enable pulse  SAN for the sense amplifier SA becomes "H" and on the other hand a voltage level of another enable pulse  SAP for the sense amplifier SA becomes "L", the sense amplifier SA operates and data transferred to the bit line BL is amplified. When a voltage level of the bit selecting signal  B is made to be "H" and moreover a voltage level of an enable pulse  IN for the data input amplifier DIA is made to be "H" in this state (incidentally, the data output amplifier DOA is inactive because it is in a write-operation cycle), the data representing "H" is written to the memory cell A11 in case where the input data DIN represents "H", and on the other hand the data representing "L" is written to the cell A11 in case where the input data represents "L". Next, will be described hereinbelow an operation of the circuit of Fig 1 in the case where the word line WL12 is selected. When a voltage level of the word line WL12 becomes "H", electric charge accumulated in the capacitor C12 is transferred to the bit line NBL through the transistor Q12. Further, if a voltage level of an enable pulse  SAN for the sense amplifier SA becomes "H" and on the other hand a voltage level of another enable pulse  SAP for the sense amplifier SA becomes "L", the sense amplifier SA operates and data transferred to the bit line NBL is amplified. When a voltage level of the bit selecting signal  B is made to be "H" and moreover a voltage level of an enable pulse  IN for the data input amplifier DIA is made to be "H" in this state (incidentally, the data output amplifier DOA is inactive because it is in a write-operation cycle), the data representing "L" is written to the memory cell A11 in case where the input data DIN represents "H", and on the other hand the data representing "H" is written to the cell A11 in case where the input data represents "L". That is, data which is in phase with input data is written to a memory cell connected to the bit line BL. In contrast, data of which the phase is opposite to that of input data is written to a memory cell connected to the bit line NBL. Incidentally, in the above described cycles in which an ordinary read and write operations are performed, voltage levels of a reset signal  R and a preset signal  P are "L" and the transistors Q₁₈ and Q₁₉ are off. Thus, the bit lines BL and NBL are not connected to the reference potential Vss. Next, will be described hereinbelow an operation of the circuit of Fig.1 in the case of resetting data stored in the memory. Upon completion of the precharge of the bit lines, a voltage level of a reset signal  R is made to be "H" after either of the word lines is selected and before the sense amplifier operates. Thereby, the transistor Q18 is turned on and further an electric potential of the bit line BL is forcedly made to be equal to the reference potential Vss. Generally, a capacity of a memory cell is far smaller than (i.e., approximately one-tenth to one-thirtieth of) a capacity of a bit line. Therefore, an electric potential of the bit line NBL is higher than the reference potential Vss whichever memory cell is selected. Thus, after the sense amplifier SA operates, a voltage level of the bit line BL becomes "L" and a voltage level of the bit line NBL becomes "H". In case where the memory cell A11 connected to the bit line BL is selected when the circuit is in this state, data representing "L" is written to the memory cell A11 (see FIG. 2). In contrast, in case where the memory cell A12 connected to the bit line NBL is selected, data representing "H" is written to the memory cell A12 (see FIG. 3). When data is read from either of the memory cells A11 and A12, in case where the data is read from the memory cell A11, data representing "L", which is in phase with the written data representing "L", is outputted therefrom. On the other hand, in case where the data is read from the memory cell A12, data representing "L", of which the phase is opposite to that of the written data representing "H", is outputted therefrom. That is, if a word line is selected when a voltage level of the reset signal  R is made to be "H", it has come that data stored in all of the memory cells arranged on the selected word line is cleared in one cycle. Thus, in order to clear data stored in all of the memory cells of a dynamic type semiconductor memory arranged according to Fig.1, the circuit has only to perform clearing operations in cycles of which the number is equal to that of the row addresses (i.e., that of the word lines). Next, will be described hereinbelow an operation of the circuit of Fig.1 in the case of performing preset of data in the memory. Upon completion of the precharge of the bit lines, a voltage level of a preset signal  P is made to be "H" after either of the word lines is selected and before the sense amplifier operates. Thereafter, when the sense amplifier SA is operated, a voltage level of the bit line BL becomes "H" and a voltage level of the bit line NBL becomes "L". In the case where the memory cell A11 connected to the bit line BL is selected when the circuit is in this state, data representing "H" is written to the memory cell A11 (see FIG. 4). In contrast with this, in case where the memory cell A12 connected to the bit line NBL is selected, data representing "L" is written to the memory cell A12 (see FIG. 5). When data is read from either of the memory cells A11 and A12, in case where the data is read from the memory cell A11, data representing "H", which is in phase with the written data representing "H", is outputted therefrom. On the other hand, in case where the data is read from the memory cell A12, data representing "H", of which the phase is opposite to that of the written data representing "L", is outputted therefrom. That is, if a word line is selected when a voltage level of the preset signal  P is made to be "H", it has come that data stored in all of the memory cells arranged on the selected word line is cleared in one cycle. Thus, in order to perform a preset of data in all of the memory cells of the dynamic type semiconductor memory according to Fig.1, the circuit has only to perform clearing operations in cycles of which the number is equal to that of the row addresses (i.e., that of the word lines). Incidentally, in the circuit of Fig.1, sources of the transistors Q₁₈ and Q₁₉ are connected to the reference potential Vss. However, even in the case where the sources of the transistors Q₁₈ and Q₁₉ are connected to the electric potential Vcc of the power source as in the second circuit, also not according to the present invention illustrated in Fig.6, a reset operation and a preset operation can be performed similarly as in the first embodiment of Fig.1. Voltage levels of the reset signal R and the preset signal P may be made to be "H" after the precharge of the bit lines are finished and before the sense amplifier operates. Further, the question does not arise concerning how the time should be regulated between when the reset signal R or the preset signal P is made "H" and the time at which a word line is selected. Next, an embodiment of the present invention will be described in detail with reference to Figs. 7-11. In Fig.7, circuits and elements having the same functions as corresponding circuits and elements of Fig.1 are designated by like reference characters. Thus, for simplicity of description, detailed description of such circuits and elements is omitted. Further, the embodiment of Fig.7 is different in the following respects from the circuit of Fig.1. That is, a p-channel transistor Q₂₀ is connected to both of and is provided between the bit line BL and the power source having the potential Vcc. Moreover, a preset signal NP is supplied to a gate of the transistor Q₂₀. A phase of the preset signal NP is opposite to a phase of the preset signal P. On the other hand, a p-channel transistor Q₂₁ is connected to both of and is provided between the bit line NBL and the power source having the potential Vcc. Moreover, a reset signal NR is supplied to a gate of the transistor Q₂₁. A phase of the reset signal NR is opposite to a phase of the reset signal R. Incidentally, among the four transistors Q₁₈-Q₂₁, the transistors Q₁₈ and Q₂₁ operate as transistors for clearing data and on the other hand the transistors Q₁₉ and Q₂₀ operate as transistors for performing preset of data. Next, an operation of this embodiment will be described in detail with reference to Figs. 8-11. In cycles in which ordinary read and write operations are performed, voltage levels of a reset signal R and a preset signal P are "L" and the transistors Q₁₈ and Q₁₉ are off. Thus, the bit lines BL and NBL are not connected to the reference potential Vss. On the other hand, voltage levels of a reset signal NR and a preset signal NP are "H" and thus the transistors Q₂₀ and Q₂₁ are off. Thus, the bit lines BL and NBL are not connected to the power source having the potential Vcc. As a result, in cycles in which ordinary read and write operations are performed, operations of reading and writing data are effected in the embodiment similarly as described with reference to Fig.1. Next, will be described hereinbelow an operation of the embodiment in the case of resetting data stored in the memory. Upon completion of the precharge of the bit lines, a voltage level of a reset signal R is made to be "H" after either of the word lines is selected and before the sense amplifier operates. Thereby, the transistor Q₁₈ is turned on and further an electric potential of the bit line BL is forcedly made to be equal to the reference potential Vss. Further, in the same period of time, i.e., after either of the word lines is selected and before the sense amplifier SA operates, a voltage level of the reset signal NR is made to be "L". Thereby, the transistor Q₂₁ is turned on and a voltage level of the bit line NBL is forcedly made to be equal to the potential Vcc of the power source. In the case where the memory cell A11 connected to the bit line BL is selected when the first embodiment is in this state, data representing "L" is written to the memory cell A11 (see FIG. 8). In contrast, in the case where the memory cell A12 connected to the bit line NBL is selected, data representing "H" is written to the memory cell A12 (see FIG. 9). When data is read from either of the memory cells A11 and A12, in the case where the data is read from the memory cell A11, data representing "L", which is in phase with the written data representing "L", is outputted therefrom. On the other hand, in the case where the data is read from the memory cell A12, data representing "H", of which the phase is opposite to that of the written data representing "H", is outputted therefrom. That is, if a word line is selected when a voltage level of the reset signal  R is made to be "H" and a voltage of the reset signal N  R is made to be "L", it has come that data stored in all of the memory cells arranged on the selected word line is cleared in one cycle. Thus, in order to clear data stored in all of the memory cells of this embodiment, the embodiment has only to perform clearing operations in cycles of which the number is equal to that of the row addresses (i.e., that of the word lines). Especially, in a cycle in which an operation of clearing data is performed in the embodiment of FIG. 7, it is not necessary to operate the sense amplifier. Thus, this embodiment can clear data from memory cells thereof in a cycle shorter than the cycle in which a clearing operation is effected in the circuit of FIGS. 1 and 2. Next, will be described hereinbelow an operation of the embodiment in the case of performing preset of data in the embodiment. Upon completion of the precharge of the bit lines, a voltage level of a preset signal  P is made to be "H" after either of the word lines is selected and before the sense amplifier operates. Thereby, the transistor Q₁₉ is turned on and an electric potential of the bit line NBL is forcedly made to be equal to the reference potential Vss. Further, in the same period of time, a voltage level of the reset signal N  P is made to be "L". Thereby, a voltage level of the bit line BL is forcedly made to be equal to the potential Vcc of the power source. In the case -where the memory cell A11 connected to the bit line BL is selected when the embodiment is in this state, data representing "H" is written to the memory cell A11 (see FIG. 10). In contrast with this, in the case where the memory cell A12 connected to the bit line NBL is selected, data representing "L" is written to the memory cell A12 (see FIG. 11). When data is read from either of the memory cells A11 and A12, in the case where the data is read from the memory cell A11, data representing "H", which is in phase with the written data thereto, is outputted therefrom. On the other hand, in the case where the data is read from the memory cell A12, data representing "H", of which the phase is opposite to that of the written data thereto, is outputted therefrom. That is, if a word line is selected when a voltage level of the preset signal  P is made to be "H" and a voltage level of the preset signal N  P is made to be "L", it has come that data stored in all of the memory cells arranged on the selected word line is cleared in one cycle. Thus, in order to effect preset of data in all of the memory cells of the embodiment, the embodiment has only to perform clearing operations in cycles of which the number is equal to that of the row addresses (i.e., that of the word lines). Especially, in a cycle in which an operation of performing preset of data is effected in the embodiment of FIG. 7, it is not necessary to operate the sense amplifier. Thus, the embodiment can preset data in memory cells thereof in a cycle shorter than the cycle in which a preset operation is effected in the circuit of Figs. 1 and 2. Incidentally, in the embodiment of Fig.7, voltage levels of the reset signal R or the preset signal P may be made to be "H", the corresponding signal NR or NP being made "L", after the precharge of the bit lines is finished and before the sense amplifier operates. Further, the question does not arise concerning how the time should be regulated between when the reset signal R or the preset signal P is made "H" and the time at which a word line is selected. Incidentally, in Fig.7, only a part of the corresponding embodiment is shown, in which the two bit lines BL and NBL and the two word lines WL11 and WL12 intersect. However, in a practical dynamic type semiconductor memory according to the present invention, many bit lines and many word lines are arranged like a matrix and a memory cell is connected to each of the intersections of bit lines and word lines. Accordingly, for all of the bit lines and the word lines, the transistors Q₁₈ - Q₂₁ are connected to the bit lines and the word lines as illustrated in Fig.7. While a preferred embodiment of the present invention has been described above, it is to be understood that the present invention is not limited thereto and that other modifications will be apparent to those skilled in the art without departing from the scope of the invention, which is to be determined solely by the appended claims.

Claims: A dynamic type semiconductor memory comprising: a plurality of pairs of bit lines (BL,NBL); a plurality of memory cells (A11,A12) connected to said plurality of bit lines; first connecting means (Q18) for connecting a first line (BL) of each pair of bit lines to a first electric potential and for charging up said first line to said first electric potential; second connecting means (Q21) for connecting a second line (NBL) of each pair of bit lines to a second electric potential and for charging up said second line to said second electric potential; characterized by third connecting means (Q20) for connecting said first line (BL) to said second electric potential and for charging up said first line to said second electric potential; and fourth connecting means (Q19) for connecting said second line (NBL) to said first electric potential and for charging up said second line to said first electric potential. A dynamic type semiconductor memory as set forth in Claim 1, wherein said first connecting means (Q18) responds to a reset signal, said second connecting means (Q21) responds to said reset signal, said third connecting means (Q20) responds to a preset signal, and said fourth connecting means (Q19) responds to said preset signal. A dynamic type semiconductor memory as set forth in Claim 1, wherein said first connecting means (Q18) responds to a first reset signal (R), and said second connecting means (Q21) responds to a second reset signal (NR), and said third connecting means (Q20) responds to a first preset signal (NP), and said fourth connecting means (Q19) responds to a second preset signal (P). A dynamic type semiconductor memory as set forth in Claim 3, wherein the phase of said first reset signal (R) is opposite to that of said second reset signal (NR), and the phase of said first preset signal (NP) is opposite to that of said second preset signal (P).

Inventors: SAKAGAMI MASAHIKO, SAKAGAMI, MASAHIKO
Applicants: MATSUSHITA ELECTRONICS CORP, MATSUSHITA ELECTRONICS CORPORATION
Application year: 1990
Main classification: G11C7
IPC codes: G11C7, G11C11