Method for forming semiconductor thin-film and resulting semiconductor thin-film

Abstract: Polycrystalline silicon thin-films having a large grain size are formed by preparing a substrate of amorphous surface comprising first regions containing tin atoms at a higher content and second regions containing tin atoms at a lower content or not substantially containing them, and then heat-treating the substrate to grow crystal grains from crystal nuclei formed only in the first regions.

Description: The present invention concerns a method of producing a semiconductor thin-film of polycrystalline silicon. Polycrystalline silicon thin film of a large grain size produced by the method makes feasible the production of semiconductor devices such as high performance thin-film transistors (TFT). Regarding the technique for forming a polycrystalline silicon semiconductor thin-film of a large grain size, a method has been reported in which an amorphous silicon thin-film is allowed to grow in a solid phase to form a polycrystalline silicon thin-film for use for a thin-film transistor [T. Noguchi, T. Ohshima, & T. Hayashi; Polysilicon Films and Interfaces, Boston, 1987, Mater. Res. Soc. Symp. Proc., Vol. 106, p. 293 (Elsevier Science Publishing, New York, 1988)]. The detail thereof is described below. In this method, firstly, an amorphous Si layer is formed on a substrate. The amorphous Si layer may be formed by a known method such as implantation of Si ions into a polycrystalline Si layer for amorphousness, thermal decomposition of SiH 4 by chemical vapour deposition, and deposition by electron-beam vapour deposition of Si on a substrate kept at room temperature. Subsequently, the amorphous Si layer is heat-treated at 600 °C in nitrogen atmosphere for several to several ten hours. Thereby, crystal nuclei are formed in the amorphous Si layer, and the nuclei grow larger with the lapse of treatment time to result finally in mutual collision of the crystal grains, forming crystal boundaries. For example, an amorphous Si layer of about 100 nm (1000Å) thick formed by Si ion implantation comes to have crystal grains of as large as 5-µm diameter by thermal treatment at 600 °C for 100 hours. A thin-film transistor formed on a polycrystalline Si layer having such a large grain diameter is observed to have a carrier mobility of more than 100 cm 2 /vsec. Accordingly, this treatment is a significantly useful method for grain growth. However, the inventors of the present invention have found disadvantages in the above-mentioned prior art as the result of practical experiment and detailed consideration as below. (1) An amorphous silicon layer will not crystallize at a temperature below 600 °C, so that the treating temperature cannot be lowered. For example, no crystal nucleus is formed by a heat treatment at 550 °C for 2000 hours in the silicon layer which is kept amorphous. The temperature 600 °C is generally higher than the heat resistance temperature of glass employed for amorphous Si thin-film transistors. Therefore, heat-resistant expensive quartz glass has to be used as the base material. (2) Generally, crystallization of amorphous thin film by solid-phase crystal growth requires time of as much as several ten hours from the start of heat treatment to achieve complete polycrystalline state independently of temperature. This is because the -induction period from the start of the heat treatment to formation of crystal nuclei is as much as several ten hours, and the growth of the crystal nuclei to crystal grain is extremely slow. For example, in amorphous Si formed by Si + ion implantation is observed to exhibit induction period of about 10 hours at-600 °C, and requires long time of 100 hours from the start of the heat treatment to the completion of crystallization of whole film. The above two problems are serious in industrial production from the standpoint of production efficiency and production cost, which have to be solved naturally. (3) In addition to the disadvantage (2) above, the nucleus formation in the amorphous Si occurs at random positions, so that the grain boundaries, which are formed by mutual collision of grown crystal grains, formed at random positions, which cannot be controlled. In fact, Si + implantation for amorphousness of the polycrystalline Si layer, and subsequent heat treatment at 600 °C will give a polycrystalline layer having a crystal diameter of 5 µm at the largest. However, the grain size distributes broadly from 1 µm to 5 µm, which gives rise to variation of characteristics of the elements, and may cause a great disadvantage practically. For example, a field-effect transistor, provided on the above-mentioned polycrystalline Si layer comprising large grains on a 4-inch substrate, exhibits variation of the electron mobility of ±10 cm 2 /v·sec relative to 110 cm 2 /v·sec and variation of the threshold value of ±0.5 v, which variations are significantly larger the those of transistors provided on a single crystal Si substrate, giving a large obstruction in constructing an integrated circuit. (4) Donor-acceptor impurities which modify electrical properties generally such as P, B, As, etc. are known to affect the growth of Si crystal. In particular, P is known to promote abnormal grain growth. (Y. Wada & S. Nishimatsu, J. Electrochem. Soc, Vol. 125, No. 9, p 1499) The inventor of the present invention, however, after long period of comprehensive study on every kind of impurity, has found that the aforementioned donor-acceptor impurities accelerate crystallization only when the impurity is introduced in a large amount near to the solid-solubility limit, and in that case an n + or p + layer comes to be formed which is unsuitable for an active semiconductor layer, making difficult the preparation of elements. The present invention, defined in the appended claims, is intended as a solution to the above-described problems in the prior art. The method defined enables control of the positions of nucleus formation and definition of the position of grain boundaries and results in a narrow grain size distribution. It is possible to grow polycrystalline film with a grain size of 10 µm or larger. This is an advantage over conventional solid phase growth where a maximum grain size of only about 5 µm is normally achieved. Recrystallisation can be conducted at a higher rate at a lower temperature than hitherto. In the method defined, localised regions, obtained by Sn-ion implantation, are used to initiate nucleation and solid phase growth. It is mentioned that it is known that solid phase epitaxy of amorphous silicon, in particular (111) silicon, can be improved by including Sn at a concentration of less than 1 at.%. This is detailed in Nuclear Instruments and Methods in Physics Research, vol.B37/38, 1989, pages 387-390. In the accompanying drawings: Fig. 1 is a graph showing the dependency of crystallisation-initiating temperature on the implantation level of Sn; Figs. 2A to 2C and Figs. 3A and 3B are schematic drawings to illustrate the process of forming semiconductor thin-film by the method of the present invention; and Figs. 4 and 5 are graphs to show the effect of Sn addition on maximum grain size. The inventor of the present invention has considered Group IV neutral impurities as a means of solving the above-mentioned problems of the prior art. For this purpose, the Group IV impurity, which does not impart polarity to a silicon semiconductor when added, is required not only to be a neutral impurity but also to have a low melting point and a high solid-solution limit, not to form a dopant level in the band gap of Si, not to form a deep recombination level, and to give a sufficiently long life to carriers. The inventor of the present invention comprehensively investigated the impurities that satisfy the above requirements, and conducted many experiments repeatedly regarding Sn. Consequently he has succeeded in lowering the crystallisation initiation temperature and in forming polycrystalline film having a large grain size in a short time. Because of the lowered crystallisation initiation temperature in the present invention, the substrate need not be highly heat-resistant. Glass which is inexpensive may be used as the substrate material. Amorphous Si semiconductor film containing Sn may be formed, for example, by depositing on a substrate a polycrystalline thin film having fine grain size (less than 50 nm (500Å)) at 600°C by a thermochemical vapour deposition (CVD) of SiH4, and implanting Sn ions by ion implantation, or otherwise by electron-beam vapour deposition, glow discharge, or sputtering. An amorphous silicon thin-film may be formed directly by chemical vapour deposition, and Sn-containing material may be used as a gas component in the chemical vapour deposition. The amount of the addition of Sn is not more than 1 x 10 22 atom/cm 3 , since an amount of the addition exceeding 1 x 10 22 atom/cm 3 may cause precipitation of β-Sn after the heat treatment. The lower limit of addition of Sn is 1 x 10 15 atom/cm 3 since the effect of the present invention cannot be achieved generally in a lower amount of addition of Sn. The thickness of the semiconductor thin-film depends on the device to be formed. For TFT, for example, the thickness is in the range from 50 to 200 nm (500 to 2000Å). Generally a thickness of about 100 nm (1000Å) is preferable for use in the production of a semiconductor device. Fig. 1 illustrates the dependency of crystallisation temperature (crystallisation initiation temperature) on the amount of the implantation in the case where Sn ion was implanted into a polycrystalline Si layer to make it amorphous. The Si layer had a thickness of 100 nm (1000Å), and Sn was implanted with an implantation energy of 110 keV with the implanting depth reaching the middle portion of the Si layer or thereabouts. An increase of the amount of Sn implantation from 1 × 10 15 cm -2 to 1 × 10 16 cm -2 lowered the temperature of formation of crystal nuclei in the Si layer made amorphous by Sn implantation by 100 °C, namely from 600 °C to 500 °C, which was confirmed by transmission electron microscopy after the heat treatment. As described above, the inventor of the present invention found the dependency of crystallization initiation temperature on the added amount of Sn, and succeeded to control the nucleation site by changing locally the Sn concentration in the Si layer by utilizing the above phenomenon. The grain size and the position of the grain boundaries are controlled by controlling the nucleation site. The invention is described more specifically below. In order to control the grain size and the grain boundary position of polycrystalline silicon thin-film, the Sn-added region containing locally a high concentration of tin (Sn) should be minute enough for crystal growth to be caused from a single nucleus. The size of the Sn-added region is not more than 2 µm, and preferably is not more than 1 µm, in maximum diameter. Outside the above-mentioned Sn-added region containing locally a high concentration of tin (Sn), Sn need not be contained, but may be contained, provided that it is in a lower concentration than in the Sn-added region, in order to accelerate crystal growth in the solid phase. In the latter case, the concentration of Sn should be not more than 10 -2 times that in the Sn-added region from the standpoint of positional control of nucleus formation and acceleration of the crystal growth. The heat treatment, to form the crystalline silicon semiconductor thin film, is carried out at a temperature lower than 600°C and which therefore is below the melting point of the amorphous silicon, to ensure that crystal growth is in the solid phase. In the heat treatment, the initiation site of the crystal growth in the solid phase is controlled by providing the Sn-added region containing tin (Sn) locally in a high concentration in the amorphous silicon thin-film. This positional control of nucleus formation in the solid phase is conducted on the basis of the finding that the crystallisation initiates at a lower temperature in the Sn-added region than in a Sn-non-added region. In order to control the position of the grain boundary, the heating temperature is such that the crystal grows from the nucleus formed in the Sn-added region but a nucleus cannot be formed in an Sn-non-added region. In the case of amorphous Si and Sn employed, as shown in Fig. 2, Sn is added locally to the predetermined sites inside the amorphous Si 2 formed on a SiO 2 substrate 1 (Fig. 2A), and subsequently heat treatment is conducted at such a temperature that Sn-containing amorphous Si (Sn-added regions 3 only will crystallize to form nuclei. In the other amorphous Si region (Sn-non-added region), no nucleus is formed because the crystallization temperature thereof is sufficiently higher than that of the impurity-added region. Continuation of the heat treatment causes the growth of the positionally controlled nuclei into amorphous Si region (Fig. 2B). This is because the phase transition of amorphous Si phase to a crystalline phase having a nucleus formed will occur with lower energy than the activation energy required for nucleus formation in an amorphous phase. Further continuation of the heat treatment gives rise to collision of the positionally controlled crystal grains 4, forming a grain boundary 6 between the nucleus-forming positions (Fig. 2C). Fig. 3 shows control of the position of the nucleus formation by forming the regions locally containing a higher concentration of Sn. An amorphous Si layer with Sn added is formed on a substrate material. In the layer, regions having locally a higher concentration of Sn are formed at a predetermined spacing (Fig. 3A). The substrate is treated thermally to cause solid phase recrystallization at a temperature such that only the regions of a higher Sn concentration crystallize,i.e. lower than the temperature of crystallization of the regions of a lower Sn concentration, thus forming Si nuclei only in the region of a higher Sn concentration. Further continuation of the heat treatment leads to growth of the crystal in the solid phase into the region of a lower Sn concentration forming no nucleus, causing collision with the grain generated at the adjacent region of higher Sn concentration around the midpoint, thereby the amorphous Si region disappearing and a positionally controlled grain boundary being formed at the position of the collision (Fig. 2B). The Si nucleus is formed at a portion of a high Sn density, the crystal growing in solid phase keeping a single domain to a low density portion, since the activation energy for growth of crystal from a nucleus having once formed is lower than the activation energy for nucleus formation to surmount the barrier of the surface energy. An experiment will now be described before detailed examples of the present invention are given. Experiment On a glass plate as a substrate, a polycrystal layer constituted of fine grains (less than 50nm (500Å) in diameter) was deposited by thermochemical vapour deposition of SiH 4 at 600 °C to a thickness of 100 nm (1000Å). Ions were implanted into the polycrystal layer under the conditions shown in Table 1. Sample No. Implanted ion Accelerating voltage (kV) Dose (cm -2 ) 0 Si 70 5 × 10 15 1 Sn 110 1 × 10 15 2 Sn 110 1 × 10 16 3 Sn 110 1 × 10 17 The accelerating voltage of 110 kV was selected so that the projection range (implantation depth) reaches the middle of the Si layer, resulting in the range of 49.8 nm (498 Å) from the surface. As shown in Table 1, into Sample of No. 0, Si ions were implanted at a dose of 5 x 10 15 ion/cm 2 at 70 kV, and into Samples of No. 1 to 3, Sn ions were implanted at 110 kV at doses of 1 x 10 15 , 1 x 10 16 , and 1 x 10 17 ion/cm 2 , respectively. Samples of No. 0, No. 1, and No. 2 as implanted, or before the heat treatment had an amorphous Si structure according to observation by transmission electron microscopy, and exhibited in electron beam diffraction a halo pattern which was characteristic of amorphous Si. On the other hand, Sample No. 3 into which Sn was implanted at a higher concentration of 1 x 10 17 ion/cm 2 (corresponding to Sn concentration of 1 x 10 22 ion/cm 3 in the 100 nm (1000 Å)-thick Si layer) had crystallised already at the time of implantation. After heat treatment at about 500°C, it was found, by scanning type transmission electron microscopy, to have β-Sn inclusions. Accordingly the tests below were omitted for this sample. Samples of No. 0, No. 1, and No. 2 were subjected to constant-temperature heat treatment at a temperature of 600 °C, in a nitrogen atmosphere as shown in Fig. 4. Consequently, in the Si layer made amorphous by implantation of Si + ions without any Sn addition, nuclei were formed in the amorphous Si only after an induction period of 10 or more hours, and thereafter the crystal extended in a dendrite form to cause collision with the adjacent crystal grain, resulting in disappearence of amorphous region and crystallization of the whole layer, thus giving a thin-film polycrystal. In approximately 100 hours, the maximum grain size became saturated with a grain size exceeding 5 µm. In Sample of No.1, into which Sn was implanted with a dose of 1 x 10 15 ion/cm 2 , the induction period was approximately 6 hours, and the formed crystal became saturated in 20 hours with a maximum grain size of about 4.8 µm. In Sample of No.2, into which Sn was implanted at a higher concentration with a dose of 1 × 10 16 ion/cm 2 , the induction period was 3 hours or less, and the maximum grain size became saturated at about 4.5 µm in 6 hours. The maximum saturated grain size decreased with the increase of the Sn dose. This is considered to be due to the increase of nucleus forming rate with the increase of the amount of Sn added. The increase of the Sn addition is considered to give rise to an increase of the nucleation density at the time of grain collision in the amorphous Si, resulting in some decrease of the grain size. Fig. 5 illustrates the dependency of the grain size on heat-treatment temperature at the treatment for 100 hours constantly under a nitrogen atmosphere. In Sample of No. 0 not containing Sn, no crystallization occurred below 600 °C even with 100 hours or more of heat treatment, while at 600 °C or a higher temperature the nucleation density increased, with tendency of a smaller grain size at a higher heat-treatment temperature because of the higher nucleation density at a higher temperature. In Sample No. 1, into which Sn was implanted with a dose of 1 × 10 15 ion/cm 2 , the crystallization initiated at 500 °C that is lower by 100°C than the samples without addition, and the nucleation density could be kept lower than that at 600 °C, so that the maximum grain size approached to approximately 10 pm by heat treatment for 100 hours. In Sample of No. 2, into which Sn is added with a dose of 1 × 10 16 ion/cm 2 , the crystallization initiated at a temperature as low as 450 °C, giving the maximum grain size exceeding 10 µm. As described above, the induction period could be shortened and the crystallization temperature could be lowered by addition of Sn, and the crystal grain was made possible to grow to a larger size. An FET (Field-effect transistor) was prepared by use of the Sn-doped polycrystal thin-film of a large grain size obtained by the present invention according to a usual IC process. The FET exhibited normal static characteristics of a transistor as one formed on a film containing no Sn, with the carrier mobility increasing with increase of the grain size, resulting in improvement by 20 to 40 % (120 to 140 cm 2 /vsec in electron mobility). Additionally, crystallization occurred at 500 °C or lower, which permits the use of inexpensive glass, giving economical effects. Example 1 On an amorphous SiO 2 substrate (thermally oxidised Si or glass), polycrystalline Si was deposited at 620°C to a thickness of 100 nm (1000 Å) by vacuum chemical vapour deposition. Further, Si ions were implanted into the entire surface thereof with an accelerating energy of 70 keV with a dose of 5 x 10 15 ion/cm 2 , to change the polycrystalline Si film into an amorphous Si film. Sn impurity was added locally by focused ion beam implantation in a maskless process under the conditions of an Sn ++ beam diameter of 0.1 µm, a dose of 1 x 10 15 ion/cm 2 , an accelerating energy of 50 keV, spacings of 10 µm, 20 µm, and 30 µm in a lattice arrangement, in a size of 2 µm square, to form implanted portions (Sn-added region) 3 (Fig. 2A). Subsequently, heat treatment was conducted therewith at 550°C for 100 hours in a nitrogen atmosphere to grow Si crystal 4. No nucleus was formed in Sn-non-added amorphous Si during the heat treatment. Crystal regions 5 were formed extending from the Sn-implanted region to approximately 10 µm, with grain boundaries 6 formed at the midpoints between the implanted sites (Fig. 2B and Fig. 2C). The grain sizes were found, by transmission electron microscopy, to have distributions in the range of 10 µm, respectively. Example 2 On an SiO 2 substrate, amorphous Si was deposited to a thickness of 100 nm (1000Å) at 550°C by vacuum chemical vapour deposition. Thereafter, Sn-added regions of 1 µm square were formed in the amorphous Si in a lattice arrangement by implanting Sn at a dose of 1 x 10 15 /cm 2 by employing a resist as a mask having apertures of 1 µm square at a spacing of 10 µm, 20 µm, or 30 µm with an accelerating energy of 50 keV. After removal of the resist, the amorphous Si was heat-treated at 550°C for 100 hours in a nitrogen atmosphere. The observation of crystal structure by transmission electron microscopy showed that the grain boundaries were formed in a lattice arrangement, the boundaries being between the Sn-implanted regions with grain sizes respectively of 10 µm ± 1 µm, 20 µm ± 2 µm, and 30 µm ± 3 µm. Example 3 On a 4-inch (1 inch = 25.4 mm) glass substrate, an Sn-added Si thin film was formed according to the present invention and having a grain size distribution of 5 ± 1 µm, from which 100 field-effect transistors with a channel length of 3 µm were prepared according to a conventional IC process. The electron mobility thereof was 200 ± 10 cm 2 /vsec, and the threshold value was 1.5 ± 0.2 V. The channel portion of each transistor could be arranged so as not to include any grain boundary since the location of the grain boundaries was known. The characteristics of the elements were improved and distributed within a narrow range.

Claims: A method of producing a polycrystalline silicon semiconductor thin film for use in the production of thin film transistors having said thin film as active layer, this method comprising:- providing an amorphous SiO 2 substrate having thereon a thin film of amorphous silicon of thickness 50 to 200 nm, in which thin film are defined localised regions obtained by Sn-ion implantation, not more than 2µm in maximum diameter, at predetermined positions, each localised region containing Sn in an amount of from 1x10 15 atom/cm 3 to 1x10 22 atom/cm 3 , the remainder of said amorphous silicon containing either no Sn or, if containing Sn, Sn in an amount not more than 10 -2 times that in each localised region, wherein the temperature at which crystallisation will initiate by nucleation of said localised regions is dependant on said amount of Sn therein and is lower than the temperature at which crystallisation will initiate by nucleation of said remainder of amorphous silicon; and carrying out a heat treatment at a temperature which is lower than 600°C, which is below the crystallisation initiation temperature of said remainder of amorphous silicon, and which is not lower than the crystallisation initiation temperature of said localised regions thereby to nucleate only said localised regions, grow crystal from a single nucleus of each nucleated localised region, and thus produce said polycrystalline silicon semiconductor thin film. A method as claimed in claim 1 wherein said substrate is of glass. A method as claimed in claim 1 wherein the step of providing the substrate having thereon a thin film of amorphous silicon includes depositing amorphous silicon thin film by chemical vapour deposition. A method as claimed in claim 4 wherein a Sn-containing material is used as a gas component in said chemical vapour deposition. A method as claimed in claim 1 wherein in providing the substrate having thereon a thin film of amorphous silicon, a polycrystalline thin film of silicon of grain size less than 50 nm is deposited at 600°C by thermochemical vapour deposition of SiH 4 and Sn ions are implanted by ion implantation, or otherwise introduced by electron beam vapour deposition, glow discharge or sputtering.

Inventors: YONEHARA TAKAO, YONEHARA, TAKAO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1990
Main classification: H01L21
IPC codes: H01L21