Semiconductor memory device

Abstract: When data read out from a memory cell array (11) is output to an external device through an output buffer (15), a first read control pulse signal (P1) and a second read control pulse signal (P2a) are generated in response to a change in address signal (Add). An operation for reading out data is controlled using the first and second read control pulse signals (P1, P2a). By such control, when an address signal (Add) seems to be changed by noise generated by a change in power source potential or the like due to a change in output, the noise can be removed, and thus the output (15) buffer is not erroneously operated.

Description: The present invention relates to a semiconductor memory device according to the preamble of claim 1, which is known from US-A- 4 701 889. In a static semiconductor memory device or a dynamic semiconductor memory device having a static column mode, an address transition detector which is called an ATD is arranged. This ATD detects a change in address signal to generate a pulse signal, and transmission of data read out from a memory cell array is controlled by this pulse signal. Fig. 1 is a block circuit diagram showing a schematic arrangement of a readout portion in a conventional semiconductor memory device having the ATD 86, and Fig. 2 is a timing chart showing an operation of the memory device. Data read out from a memory cell array 81 is supplied to an I/O buffer 83 through a core portion I/O bus 82. The output data from the I/O buffer 83 is supplied to an output buffer 85 through an I/O bus 84, and readout data Dout is output from the output buffer 85 to an external device. At this time, as shown in the timing chart of Fig. 2, the ATD 86 detects a change in input address Add to generate a pulse signal Pa having a predetermined pulse width and supplies it to the I/O buffer 83 and the output buffer 85. The I/O buffer 83 transmits data read out on the core portion I/O bus 82 to the I/O bus 84 on the basis of the pulse signal Pa. The output buffer 85 externally transmits the data output from the I/O bus 84 as a Dout on the basis of the pulse signal Pa. In order to enable the semiconductor memory device with the above arrangement to perform a high-speed operation, the ATD must detect a change in address as sensitive as possible. In the semiconductor memory device, a read operation speed and the number of bits of a multibit output have been increased. Therefore, the ATD 86 must be sensitive in order to achieve a high-speed operation. A buffer having a large current supply capacity is required as the output buffer 85. In addition, in multibit output data, a ratio di/dt of a change in output current to a change in time upon a change in output from the output buffer 85 is largely increased. Fig. 3 is a circuit diagram showing a wiring state around a chip when the above memory device is constituted by a one-chip memory. A plurality of input/output pins are arranged on a memory chip 91. However, in order to simplify the following description, only a Vcc pin for supplying a high source potential Vcc and a Vss pin for supplying a ground potential Vss are shown in Fig. 3. The Vcc and Vss pins are connected to a power source through the wiring on the circuit board. An inductance component L is parasitically present in the wiring. Symbol C in Fig. 3 denotes a capacitor for connecting the Vcc to the Vss. In the circuit shown in Fig. 3, when the di/dt is increased, an electromotive force ( = L di/dt) is also increased, thereby largely changing the ground potential Vss of the chip. Using the ATD 86 having high sensitivity, the change in the ground potential Vss due to the change in output is directly detected. As a result, as shown in the timing chart of Fig. 4, the ATD 86 is operated again to generate a pulse signal Pa. The output buffer 85 is operated again by this pulse signal Pa to reset the output or to change the output data into a reverse level within a short time, thereby largely changing the ground potential Vss again. As a result, as shown in Fig. 4, the output is set in an oscillating state, and a normal operation cannot be assured. Conventionally, as a countermeasure to these problems, a size of transistor elements constituting the output buffer 85 is decreased, or the sensibility of the ATD 86 is degraded. However, both methods are in conflict with a high-speed read operation. As described above, according to a conventional semiconductor memory device, when a sensitive ATD is used to increase a read operation speed, a normal operation cannot be assured because of a change in power source potential according to the change in output. The present invention has been made in consideration of the above drawbacks, and has as its object to provide a semiconductor memory device capable of designing a high-speed operation and assuring a normal operation. This object is achieved by a semiconductor memory device of the initially defined type having the characterizing features of claim 1. Preferred embodiments are listed in the dependent claims. When the address signal seems to be changed due to noise generated by a change in power source potential according to a change in output, this noise is removed by the low-pass filter means. Therefor, the pulse signal is not generated from the second pulse generating means. At this time, since the output buffer is not operated, the output buffer is not erroneously operated. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing a schematic arrangement of a date read portion of a conventional semiconductor memory device; Fig. 2 is a timing chart showing an operation of the semiconductor memory device in Fig. 1; Fig. 3 is a circuit diagram showing a wiring around a chip when the semiconductor memory device in Fig. 1 is constituted by a one-chip memory; Fig. 4 is a timing chart showing an operation of the circuit shown in Fig. 3; Fig. 5 is a block diagram showing an arrangement according to an embodiment of the present invention; Fig. 6 is a timing chart showing an operation of the semiconductor memory device shown in Fig. 5; Figs. 7 to 10 are circuit diagrams showing arrangements of different circuit portions on the semiconductor memory device according to the embodiment shown in Fig. 5; and Fig. 11 is a timing chart showing an operation of the circuit shown in Fig. 10. According to the present invention, a static semiconductor memory device or a dynamic semiconductor memory device having a static column mode is basically arranged as follows. A change in address signal Add is detected by an address transition detector ATD to generate two read control pulse signals, and an operation for reading out data from a memory cell array and outputting the data through an output buffer is controlled using the two read control pulses. Usually, the two read control pulses are respectively generated from two address transition detectors ATDs. There are two readout control methods using the two read control pulse signals. In the first method, the first read control pulse signal controls an entire read path extended from the memory cell array to an external device through a core portion I/O bus, an I/O buffer, an I/O bus and an output buffer, and the second read control pulse signal serves as a gate for determining whether the data passes at the halfway of this read path or not. As the second method, the first read control pulse controls up to the halfway of the above read path, e.g., the first half, and the second read control pulse sequentially controls the rest of the read path, e.g., the second half of the above read path, thereby sharing all the control. An embodiment of the present invention will be described below with reference to the accompanying drawings. Fig. 5 is a block diagram showing a schematic arrangement of a data read portion of the semiconductor memory device according to an embodiment of the present invention. Data read out from a memory cell array 11 is supplied to an I/O buffer 13 through a core portion I/O bus 12. The output data from the I/O buffer 13 is supplied to an output buffer 15 through an I/O bus 14, and readout data Dout is output from the output buffer 15 to the external device. Thus, the readout pulse is obtained. An address Add is synchronously supplied to a first ATD (address transition detector) 16 and a low-pass filter 17. The first ATD 16 detects a change in input address Add to generate a pulse signal P1 having a predetermined pulse width. The pulse signal P1 generated from the first ATD 16 is supplied to the I/O buffer 13. An operation of the I/O buffer 13 is controlled on the basis of this pulse signal P1. The low-pass filter 17 removes noise of a high-frequency component from the input address Add. The signal passing through the low-pass filter 17 is supplied to a second ATD 18. The second ATD 18 detects a change in input signal to generate a pulse signal P2 having a predetermined width. The pulse signal P2 generated by the second ATD 18 is converted into a pulse signal P2a having a predetermined pulse width and is then supplied to the output buffer 15. An operation of the output buffer 15 is controlled on the basis of the pulse signal P2a. Note that, in order to increase an operation speed, a sensitive detector is used as the first ATD 16, and a buffer having a large current supply capacity is used as the output buffer 15. An operation of the circuit with the above arrangement is described below with reference to a timing chart in Fig. 6. The address Add is firstly changed, thereby reading out data from the memory cell array 11 to the core portion I/O bus 12 in response to the address. After a lapse of a predetermined period of time from when the address Add was changed, a first pulse signal P1 is generated from the first ATD 16. The pulse signal P1 is input to operate the I/O buffer 13, and data of the core portion I/O bus 12 is transmitted to the I/O bus 14. In addition, after the lapse of the predetermined period of time from when the address Add is changed, the pulse signal P2 is generated by the second ATD 18. Thereafter, a pulse signal P2 is converted into a pulse signal P2a by a pulse width setting circuit 19. By receiving the pulse signal P2a, the output buffer 15 is operated. The data on the I/O bus 14 is output to an external device as output data Dout. As described above, since a buffer having a large current supply capacity is used as the output buffer 15, when the output buffer 15 is operated to output the output data Dout to the external device, noise may be generated from a ground potential Vss as shown in Fig. 6. Due to generation of the noise at the ground potential Vss, the address Add seems to be changed as shown in Fig. 6. The change is detected by the first ATD 16, and the first pulse signal P1 is generated again. Therefore, since the I/O buffer 13 is operated, the data of the I/O bus 14 is instantaneously changed, as shown in Fig. 6. However, since the above noise included in the address Add is removed by the low-pass filter 17, no pulse signal is generated by the second ATD 18. Therefore, no pulse signal P2a is generated either, and an oscillation state does not occur unlike in the conventional device. According to the above described embodiment, the device is protected from noise without delaying access time. In order to increase the operation speed, a sensitive detector is used as the first ATD 16. The second ATD 18 need not be highly sensible. However, when sensitivity of the second ATD 18 is poor, an output operation of data from the output buffer 15 is delayed, thereby delaying access time. About 10 nanoseconds of time are required to read out data onto the I/O bus 14 by the I/O buffer 13 controlled by the first pulse signal P1. Noise to be cut by the low-pass filter 17 is noise having a pulse width of several nanoseconds or less. For this reason, even if a change in address passing through the low-pass filter 17 is detected by the second ATD 18 and a pulse signal P2 is generated, data having a sufficient margin can be output from the output buffer 15 to the external device. Fig. 7 is a circuit diagram showing an arrangement of the low-pass filter 17 in the semiconductor memory device according to the above embodiment. This circuit comprises two p-channel MOS transistors 22 and 23 inserted between a power source potential Vcc and an output node 21 in series, two n-channel MOS transistors 24 and 25 inserted between the output node 21 and the ground potential Vss in series, and a signal delay circuit 26 for delaying a 1-bit address signal Add by a predetermined time. The 1-bit address signal Add is directly supplied to each of the gates of the transistors 22 and 24, and the 1-bit address signal Add is supplied to each of the gates of the transistors 23 and 25 through the signal delay circuit 26. In the low-pass filter 17 with the above arrangement, when the input address signal Add is converted from "0" to "1", the transistor 24 is immediately turned on. The transistor 25 is turned on after the output signal from the signal delay circuit 26 is converted to "1". As a result, when the input address signal Add is converted from "0" to "1", the signal from the output node 21 is converted from "1" to "0" with a delay time of the signal delay circuit 26. Fig. 8 is a circuit diagram showing a detailed arrangement of the first ATD 16 in the semiconductor memory device according to the above embodiment. The second ATD 18 has the same arrangement as the first ATD 16, and only an input stage of the ATD 18 is different from that of the ATD 16. This circuit comprises p-channel MOS transistor 32 inserted between a power source potential Vcc and a node 31 in series, two n-channel MOS transistors 33 and 34 inserted between the node 31 and a ground potential Vss in series, two n-channel MOS transistors 35 and 36 inserted between the node 31 and the ground potential Vss in series, a signal delay circuit 37 for delaying a 1-bit address signal Add by a predetermined time, an inverter 38 for inverting an output signal from the signal delay circuit 37, an inverter 39 for inverting the 1-bit address signal Add, a signal delay circuit 40 for delaying an output signal from the inverter 39 by a predetermined time, an inverter 41 for inverting an output signal from the signal delay circuit 40, and an inverter 42 for receiving a signal of the node 31. The p-channel MOS transistor 32 serves as a load MOS transistor, and the gate thereof is connected to the ground potential Vss and normally set in an ON state. The address signal Add is directly supplied to the gate of the n-channel MOS transistor 33, and an output signal from the inverter 38 is supplied to the gate of the n-channel MOS transistor 34. An output signal from the inverter 39 is supplied to the gate of the n-channel MOS transistor 35, and an output signal from the inverter 41 is supplied to the gate of the n-channel MOS transistor 36. A pulse signal P1 is output from the inverter 42. In the above arrangement, when the input address signal Add is stable to be "0", the transistor 33 is set in an OFF state; the transistor 34, an ON state; the transistor 35, an ON state; and the transistor 36, an OFF state. For this reason, there is no current path for discharging the node 31 to a ground potential, and the node 31 is set to be "1" by the transistor 32. Therefore, a pulse signal serving as the output from the inverter 42 is set to be "0". When the Add rises to "1", the transistor 33 set in an OFF state is immediately turned on. However, since the transistor 34 is still set in an ON state, a current path is formed due to both the transistors 33 and 34 for discharging the node 31 to the ground potential, thereby inverting the signal from the node 31 to "0". Thereafter, the pulse signal P1 serving as the output from the inverter 42 rises to "1". When the output signal is changed from "0" to "1" with a delay time of the signal delay circuit 37, the transistor 34 set in an ON state is turned off. Therefore, the node 31 is set to be "1" by the transistor 32 again, and the pulse signal P1 returns to "0" again. Thus, the change in input address signal Add from "0" to "1" is detected, thereby generating the pulse signal P1. When the input address signal Add is stable to be "1", the transistor 33 is set in an ON state, the transistor 34, an OFF state; the transistor 35, an OFF state; and the transistor 36, an ON state. In this case, there is no current path for discharging the node 31 to the ground potential, and the node 31 is set to be "1" by the transistor 32. When the Add goes to "0", the transistor 35 set in an OFF state is immediately turned on. However, since the transistor 36 is still set in an ON state, a current path is formed due to both the transistor 35 and 36 for discharging the node 31 to the ground potential, thereby inverting the signal from the node 31 to "0". When an output signal from the signal delay circuit 40 is changed from "0" to "1" with its delay time, the transistor 34 set in an ON state is turned off. Therefore, the node 31 is set to be "1" by the transistor 32 again. Thus, the change in input address signal Add from "1" to "0" is detected, thereby generating the pulse signal P1. Note that the width of the pulse signal P1 is determined according to each delay time of the signal delay circuits 37 and 40. Fig. 9 is a circuit diagram showing an arrangement of the I/O buffer 13 in the semiconductor memory device according to the above embodiment. This circuit comprises two p-channel MOS transistors 53 and 54 respectively inserted between a power source potential Vcc and a pair of nodes 51 and 52 connected to an arbitrary pair of buses I/Oc and I/Oc in the core portion I/O bus 12, a p-channel MOS transistor 55 inserted between a pair of nodes 51 and 52, a p-channel MOS transistor 56 inserted between the power source potential Vcc and the node 51 of the pair of nodes, a p-channel MOS transistor 57 inserted between the power source potential Vcc and the node 52, an n-channel MOS transistor 59 inserted between the node 51 of the pair of nodes and a node 58, an n-channel MOS transistor 60 inserted between the node 52 of the pair of nodes and the node 58, an n-channel MOS transistor 61 inserted between the node 58 and a ground potential Vss, an inverter 62 for inverting a pulse signal P1 generated by the first ATD 16, a buffer circuit 63, having a decoding function, for receiving the signal from the node 51 of the pair of nodes, and a buffer circuit 64, having a decoding function, for receiving a signal from the node 52. Each of the gates of transistors 56 and 59 is connected to the node 52, and each of the gates of the transistors 57 and 60 is connected to the node 51. An equalizing signal EQ serving as an output signal from the inverter 62 is supplied to each of the gates of the transistors 53, 54, 55 and 61. In the above arrangement, when a first pulse signal P1 generated by the first ATD 16 rises from "0" to "1", the equalizing signal EQ serving as an output signal from the inverter 62 falls from "1" to "0" and each of the transistors 53, 54 and 55 is turned on. By turning the transistors 53 and 54 on, the pair of nodes 51 and 52, i.e., the pair of buses I/Oc and I/Oc , are precharged by the power source potential Vcc. By turning the transistor 55 on, the pair of buses I/Oc and I/Oc are equalized to the same potential. When the pulse signal P1 falls to "0", each of the transistors 53, 54 and 55 is turned off and the transistor 61 is turned on. By tuning the transistor 61 on, a CMOS inverter constituted by the p-channel n-channel MOS transistor 56 and 57 and the MOS transistors 59 and 60 is operated to start amplification of a potential difference of data read out onto the pair of buses I/Oc and I/Oc . Therefore, complementary data of the pair of nodes 51 and 52 is generated. Thereafter, the data is read out onto the pair of buses I/O and I/O by the buffer circuits 63 and 64 having a decoding function. Fig. 10 is a circuit diagram showing an arrangement of the pulse width setting circuit 19 in the semiconductor memory device according to the above embodiment. Fig. 11 is a timing chart illustrating an operation of the pulse width setting circuit 19. This circuit comprises an inverter 71 for obtaining a signal P2 by inverting the second pulse signal P2 generated bV the second ATD 18, a signal delay circuit 72 for obtaining a delay signal P3 by delaying the output signal from the inverter 71 by a predetermined time, an inverter 73 for obtaining a signal P3 by inverting the output signal from the signal delay circuit 72, a NAND gate 74 for receiving an output signal from the inverter 73 and the output signal from the inverter 71, and an inverter 75 for inverting an output signal P4 from the NAND gate 74. An pulse signal P2a can be obtained as an output signal from the inverter 75. In the pulse width setting circuit with the above arrangement, regardless the pulse width of the input pulse signal P2, the pulse width is determined by a signal delay time of the signal delay circuit 72. As described above, according to the present invention, there is provided to a semiconductor memory device capable of designing a high-speed operation and assuring a normal operation. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory device for controlling transmission of data over an output signal path, said data being read from a memory cell array and output to an external device, comprising: an output signal path (12,13,14,15), provided between said memory cell array (11) and an output buffer (15), for outputting said data from said memory cell array (11) to said external device; and first pulse generating means (16) for receiving an address signal for addressing memory cells in said memory cell array (11) and for generating a first pulse signal (P1) in response to a change in said address signal (Add); characterized by low-pass filter means (17) for receiving said address signal (Add) and for outputting a filtered address signal; second pulse generating means (18,19) coupled to said low-pass filter means (17), for generating a second pulse signal (P2a) in response to a change in said filtered address signal; and control means, coupled to said first and second pulse generating means (16,18,19), for controlling said transmission of said data over said output signal path from a memory cell to a part of said signal output path (12,13,14,15) in response to said first pulse signal (P1) and controlling said transmission of data from said part of said output signal path (12,13,14,15) to said external device in response to said second pulse signal (P2a). A memory device according to claim 1, characterized in that said low-pass filter means (17) is included in said second pulse generating means (18,19). A memory device according to claim 1, characterized in that said output signal path (12,13,14,15) is constituted by connecting a core portion I/O bus (12), an I/O buffer (13), an I/O bus (14) and an output buffer (15) in order. A memory device according to claim 3, characterized in that said control means controls said transmission of said data over said output signal path (12,13,14,15) from said memory cell array (11) to said output buffer (15) in response to said first signal pulse (P1), and controls said output of said data from said output buffer (15) to said external device in response to said second signal pulse (P2a). A memory device according to claim 3, characterized in that said output signal path (12,13,14,15) comprises a first portion and a second portion, said first portion of said output signal path (12,13,14,15) being between said memory cell array (11) and said I/O buffer (13), and said second portion of said output signal path (12,13,14,15) being between said I/O buffer (13) and said output buffer (15), and said control means controls said I/O buffer (13) to transmit said data from said memory cell array (11) to said output buffer (15) in response to said first signal pulse (P1), and controls said output buffer (15) to transmit said data to said external device in response to said second signal pulse (P2a). A memory device according to claim 1, characterized in that said first pulse generating means (16) comprises a first address transition detector (16) which has a sensitive detecting characteristic and said second pulse generating means (18,19) comprises a second address transition detector (18). A memory device according to claim 1, characterized in that said second pulse generating means (18,19) includes a pulse width setting circuit (19) for generating a pulse signal having a predetermined pulse width in response to said filtered address signal supplied from said second address transition detector (18). A memory device according to claim 1, characterized in that said low-pass filter means (17) eliminates noise of high-frequency component from said address signal (Add).

Inventors: OKADA YOSHIO C O INTELLECTUAL, OKADA, YOSHIO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1990
Main classification: G11C7
IPC codes: G11C11, G11C7, G11C8