Semiconductor integrated circuit

Abstract: Inductive structures having low parasitic ca­ pacitances for direct integration in semiconductor integrated circuits. In one embodiment, a generally planar spiral winding (2) is disposed on the surface of a substrate (1). An electrical connection to the inter­ nal end (4) of the spiral (2) is made through electrically conducting vias (21,23) passing through the substrate (1). The spiral (2) may be spaced from a substrate surface by a plurality of spaced apart electrically conductive posts (25) having a staggered arrangement between adja­ cent windings of the spiral (2). A transformer includes two windings disposed on top of each other on a semiconductor substrate (1) and separated by an electri­ cally insulating film (33). The windings have a common central opening in which a magnetic material (36) is disposed to improve the inductive coupling between the windings. The transformer may include two heli­ cal windings (47,48), one surrounding another, each formed with vias (51,56) and electrical conductors (52,53;57,58) the inner wind­ ing (47) being formed in and on a semiconductor substrate (1) and the outer winding (48) being formed on insulating films (41,42) disposed on the substrate (1) and extending through the films (41,42) and substrate (1). A variable induc­ tor includes inductively coupled spiral windings (62,2) separated by an insulating film (61) and a current con­ trol (68) for controlling the current through one of the spirals and, thereby, the effective inductance of the other spiral.

Description: The present invention relates to a semiconductor integrated circuit as stated in the preamble of claim 1. Such kind of semiconductor integrated circuit is already known from GB-A-2 173 956. This known semiconductor integrated circuit comprising: an electrically semi-insulating semiconductor substrate having opposed first and second surfaces: active or passive elements on or within said semiconductor substrate; an electrical conductor disposed in a first spiral on the first surface of the semiconductor substrate, the spiral including an external end disposed outside the spiral as a first lead and an internal end disposed within the spiral; a second lead disposed on the first surface of the semiconductor substrate outside the first spiral, whereby electrical connections to the spiral can be made on the first surface of the semiconductor substrate; and an electrically conducting connector disposed below said first spiral for connecting the second lead to the internal end of the spiral. From US-A-3 504 276 a search coil is already known suitable for detecting variations in flux. Basically, coils of simple and complex coil-loop configurations are made by printed circuit techniques, and a specific coil structure can consist of different coil-loop configurations on different sides of a board which are connected by a wire running through the board. Further, from US-A-3 881 244 a solid state inductor is already known which is formed in a monocrystalline semiconductor body. An electrically isolated helix comprised of conductive studs selectively interconnected by electrical contacts circumscribes an electrically isolated core material. Typically the studs are comprised of the semiconductor slice material, or are deposited conductor. Such solid state inductor can also be part of an integrated circuit. The present invention relates to a semiconductor integrated circuit having an inductive structure, particularly for use at high frequencies. Of all passive electrical elements (resistors, capacitors, and inductors), inductors are the most difficult to form in integrated circuits. Inductors present difficulties because they require relatively large areas and/or volumes to achieve useful values of inductance. In addition, the traditional three-dimension character of inductors is difficult to realize within integrated circuits that are essentially two-dimensional in character. The difficulties of making satisfactory inductors of useful values that at integrable with integrated circuits are aggravated at higher frequencies. Because of the limited volumes available for components, i.e., active and passive elements in essentially two-dimensional integrated circuits, the conventional inductive structures suffer from increasing parasitic capacitances at increasing frequencies. These undesirable capacitances are produced by conductor cross overs, closely spaced wiring paths, and the like. The parasitic capacitances adversely affect and limit the frequency at which the circuits perform properly. At high enough frequencies, the effects of the parasitic capacitances can be so strong that they overwhelm the inductive characteristic of an inductance element. In more complex structures, such as transformers, employing several windings, the difficulties associated with controlling the area and volume of an element while achieving desired performance and limiting parasitic capacitances are even greater. It is an object of the present invention to provide a semiconductor integrated circuit comprising inductive structures that have reduced parasitic capacitances, especially and high frequencies. According to the invention, this object is achieved with a semiconductor integrated circuit, according to claim 1. According to the invention, an electrically conducting spiral is disposed on a surface of a semiconductor substrate. The spiral includes an external end disposed outside the spiral and an internal end disposed within the spiral. An electrical lead on the first surface of the semiconductor substrate reaches the internal end of the spiral through two vias and an electrical conductor on the second surface of the semiconductor substrate. Another electrical lead on the first surface of the semiconductor substrate reaches the external lead. The semiconductor substrate is interposed between the cross over of the lead from the internal end and the spiral, thereby significantly reducing the parasitic capacitance. Figure 1 is a perspective view of a prior art spiral inductor. Figures 2(a) and 2(b) are plan and sectional views, respectively, of a prior art spiral inductor. Figures 3(a), 3(b), and 3(c) are perspective, plan, and sectional views, respectively, of a prior art inductor employing two electrically interconnected spirals. Figure 4 is a perspective view of a spiral inductor in an embodiment of the invention. Figures 5(a), 5(b), and 5(c) are a perspective and two sectional views, respectively, of a spiral inductor in another embodiment of the invention. The embodiments of the invention are discussed below in conjunction with representative prior art to illustrate the improvements achieved in the invention. In all figures, like elements are given the same reference numbers. Figure 1 is a perspective view of a prior art inductor disposed on a semiconductor substrate 1 that may be gallium arsenide. In this inductor, an electrical conductor 2 arranged in a spiral pattern is disposed on a first surface of the substrate 1. As used here, the term "spiral" means a winding that increases in diameter with reference to a central point as the conductor becomes longer. The spiral may be smooth, gradually increasing in diameter like the shell of a nautilus, or have corners with angular turns like the ninety degree turns shown in Figure 1. The spiral is formed of a metal that is deposited by evaporation or by plating and includes an external end 3 lying outside the spiral and an internal end 4 disposed at the inside of the spiral. In Figure 1, external end 3 is connected to a terminal 5 for ease of connection by wire bonding or other techniques to other circuit components. Internal end 4 is connected through a lead 6 to a terminal 7 for making external connections. Lead 6 must cross over and, therefore, be electrically insulated from windings of the conductor 2. An electrically conducting ground plane 8 is disposed on the opposite side of substrate 1 from the conductor 2. In Figures 2(a) and 2(b), a plan view and a sectional view of a prior art inductor similar in structure to the inductor of Figure 1 is shown. An electrically insulating air bridge 9 including an air space 10 is part of lead 6, providing the electrical insulation from the turns of the conductor 2. The air bridge is formed by conventional technology employing a temporary support, such as a polyimide or photoresist film, covering the windings 2 while the metal comprising air bridge 9 is deposited. After that metal is deposited, the temporary support is removed, for example, with a solvent, leaving a free standing air bridge. In conventional technology, the spacing between the metal of the air bridge and the conductors 2 is, at most, a few microns. Because of this close spacing, even though the dielectric constant of the air between lead 6 and windings 2 is relatively low, a significant parasitic capacitance exists between the windings 2 and the lead 6 at air bridge 9. In Figures 3(a), 3(b), and 3(c), an inductive structure disclosed in Japanese Published Utility Model Application 60-136156 is shown in perspective, plan, and sectional views, respectively. A substrate 1, that may be a semiconductor material, employed with the structure is not shown in Figure 3(a) for clarity. The inductive structure of Figures 3(a)-3(c) includes two spiral electrical conductors 2 and 12 that are disposed opposite each other. The internal end 4 of spiral 2 is electrically connected to an external end 13 of spiral 12 through an electrical conductor 15. The inductive structure has a first terminal 5 electrically connected to the external end 3 of spiral 2 and a second terminal 7 connected to the internal end 14 of spiral 12. Realization of the inductive structure shown schematically in Figure 3(a) is indicated in the cross-sectional view of Figure 3(c). The structure is produced by depositing patterns of metal in conjunction with insulating layers 20, 30, 40, and 50 successively disposed on substrate 1. Initially, after the deposition of insulating layer 20, a window is opened for establishing contact with a highly conductive region 1a in substrate 1. Then, spiral 2 is formed by depositing and patterning a metal. Thereafter, insulating layer 30 is deposited and a window is opened for making a connection to the internal end 4 of spiral 2. After a subsequent metal deposition and patterning to form an interconnection with conductor 15, insulating layer 40 is deposited and a window opened. After still another metal deposition and patterning to form spiral 12, making an electrical connection in the window at the external end 13 of spiral 12, a final, electrically insulating layer 50 is deposited. The inductance of the structure shown in Figures 3(a)-3(c) is the inductance of the individual spirals plus a mutual inductance between the two spirals. Since the mutual inductance between the two spirals is greater than if they were side-by-side, the total inductance is increased over that of two side-by-side spirals and a smaller volume is occupied. However, the fabrication process for the structure of Figures 3(a)-3(c) is extremely complex and, as in the prior art device described with respect to Figures 2(a) and 2(b), the spacing between the two spirals is limited by the thickness of the insulating layers 20, 30, 40, and 50. Therefore, a significantly increased parasitic capacitance is produced by the structure of Figures 3(a)-3(c), limiting its useful frequency range. Embodiments of the invention are shown in Figures 4 and 5(a)-5(c). In Figure 4, a perspective, schematic view of an embodiment of the invention is shown in which an intervening semiconductor substrate 1, illustrated in Figures 5(b) and 5(c), is omitted for clarity. Turning to Figure 4, the inductive structure includes a spiral conductor 2 having an external end 3 and an internal end 4 disposed on a first surface of an electrically insulating semiconductor substrate (not shown). Internal end 4 is electrically connected to a lead 6 not by an air bridge structure but by a via and lead arrangement. A via 21 includes a via hole penetrating the semiconductor substrate 1 from the surface of the substrate on which spiral 2 is disposed to the opposite surface of the semiconductor substrate and an electrically conductive material filling the via hole. An electrical conductor 22 is disposed on the opposite surface of the semiconductor substrate from the spiral 2 and is in electrical contact with via 21. A second electrically conducting via 23 outside spiral 2 also penetrates the semiconductor substrate. That via 23 is in electrical contact with conductor 22 and with lead 6 so that an external electrical connection can be made to internal end 4 of spiral 2 from the side of the semiconductor substrate on which spiral 2 is disposed. The embodiment of the invention shown in Figures 4 and 5(a)-5(c) is produced by conventional techniques including preparing the via holes, filling them with metal to complete the vias, and subsequently depositing and patterning electrical conductors on both sides of the semiconductor substrate to complete the electrical connections. These processing steps can be carried out in various orders. For example, the spiral conductor 2 can be deposited and patterned first, the via holes then produced and filled with metal, and the structure completed by depositing and patterning conductor 22 at the rear surface of the semiconductor substrate 1. The semiconductor substrate 1 may consist gallium arsenide or indium phosphide. Gallium arsenide is preferred for high frequency applications. The invention has the advantage that the inductive structure is directly integrated into a semiconductor integrated circuit. The semi-insulating semiconductor substrate on which the spiral is disposed and in which the vias are formed have formed on and in it active components, such as transistors and diodes, and other passive elements, together forming an integrated circuit. In the embodiment of the invention shown in Figures 5(a)-5(c), a second electrically conducting spiral 12 is disposed on the surface of the semiconductor substrate opposite the surface bearing spiral 2. As in the embodiment of the invention shown in Figure 4, the internal end of spiral 2 disposed on the first surface of the semiconductor substrate 1 is electrically connected by means of a via 21. In the embodiment of Figures 5(a)-5(c), via 21 extends through the semiconductor substrate 1 and is electrically connected to the second spiral 12. Spiral 12 is connected to a lead 6 through a second via 23. An important feature of the structure of Figures 5(a)-5(c) is the sense, i.e., the direction of turning of the spirals 2 and 12. Spirals 2 and 12 in the embodiment of Figures 5(a)-5(c) have different senses, i.e., one is wound in a left-hand sense and the other is wound in a right-hand sense. In addition, spiral 12 is disposed, where possible, so that it does not directly underlie spiral 2. Obviously, the internal end 14 of spiral 12 directly underlies the internal end 4 of spiral 2, and a portion of spiral 12 or conductor 22 passes beneath part of spiral 2 to reach via 23. Otherwise, in the embodiment of Figures 5(a)-5(c), if spiral 12 is projected onto the surface of the semiconductor substrate bearing spiral 2, there is no overlapping of spirals 2 and 12 except at the via 23 and the cross over. In other words, the spirals 2 and 12 are interleaved. This arrangement minimizes the parasitic capacitance between the two spirals. The embodiment of Figures 5(a)-5(c) is produced in the same manner that the embodiment of Figure 4 is produced. The embodiment of the invention shown in Figures 5(a)-5(c) provides increased inductance over that of Figure 4 by the inclusion of second spiral 12. However, there is no significant increase in parasitic capacitance because spiral 12 does not directly underlie spiral 2 any more than conductor 22 of Figure 4 does. Moreover, the fabrication process is no more complex than that of the structure of Figure 4 and far less complex than that of the prior art structure of Figures 3(a)-3(c). In the embodiments of the invention shown in Figures 4 and 5(a)-5(c), the semiconductor substrate 1 is disposed between the spiral 2 and conductor 22 and, as indicated in Figures 5(a)-5(c), the second spiral 12. The relatively large thickness of the semiconductor substrate, particularly when compared to the relatively thin insulating layers of the prior art inductive structure of Figure 3(c), significantly reduces the parasitic capacitance of the novel structure. The dielectric constant of air employed in the air bridge 9 of the prior art structure shown in Figure 2(b) is one whereas for a semiconductor substrate 1, such as gallium arsenide, the dielectric constant is about twelve. However, the increase in the spacing between the conductors in the invention, hundreds of microns versus a few microns in the air bridge structure of Figures 2(a)-2(b), results in a substantial reduction in the parasitic capacitance in the invention.

Claims: A semiconductor integrated circuit, comprising: an electrically semi-insulating semiconductor substrate (1) having opposed first and second surfaces; active or passive elements on or within said semiconductor substrate (1); an electrical conductor disposed in a first spiral (2) on the first surface of the semiconductor substrate (1), the first spiral (2) including an external end (3) disposed outside the first spiral (2) as a first lead and an internal end (4) disposed within the first spiral (2); a second lead (6) disposed on the first surface of the semiconductor substrate (1) outside the first spiral (2), whereby electrical connections to the first spiral (2) can be made on the first surface of the semiconductor substrate (1) and an electrically conducting connector (22) disposed below said first spiral (2) for connecting the second lead (6) to the internal end (4) of the first spiral (2); characterized in that first and second electrically conducting vias (21, 23) pass through the semiconductor substrate (1) from the first to the second surface; the electrically conducting connector (22) is disposed on the second surface of the semiconductor substrate (1); the first via (21) connects the internal end (4) of the first spiral (2) with said connector (22); and the second via (23) connects said connector (22) with the second lead (6). The semiconductor integrated circuit of claim 1, characterized in that the electrically conducting connector (22) disposed on the second surface of the substrate (1) is a second spiral (12). The semiconductor integrated circuit of claim 2, characterized in that the second spiral (12), when projected onto the first surface of the substrate (1), is interleaved with the first spiral (2). The semiconductor integrated circuit of claim 3, characterized in that the substrate (1) is chosen from the group consisting of gallium arsenide and indium phosphide.

Inventors: ANDOH NAOTO, INOUE AKIRA, NAKAHARA KAZUHITO, NAKAJIMA YASUHARU, ANDOH, NAOTO, INOUE, AKIRA, NAKAHARA, KAZUHITO, NAKAJIMA, YASUHARU, ANDOH, NAOTO, C/O MITSUBISHI DENKI K.K., INOUE, AKIRA, C/O MITSUBISHI DENKI K.K., NAKAHARA, KAZUHITO, C/O MITSUBISHI DENKI K.K., NAKAJIMA, YASUHARU, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1990
Main classification: H01F17
IPC codes: H01F27, H01F17, H01L21, H01L27, H01L23, H01F21