REDUCING DARK CURRENT IN CHARGE COUPLED DEVICES

Abstract: In a CCD in which a pixel is defined by at least two adjacent gate electrodes, voltages are applied to both gate electrodes to simultaneously place both gates of each pixel in the accumulation mode of operation. Preferably one of these voltages is at a higher potential level than the other.

Description: REDUCING DARK CURRENT IN CHARGE COUPLED DEVICES Technical Field This invention relates to a method and apparatus for reducing dark current in charge coupled devices (CCDs). Background Art A true two phase CCD refers to a device in which there are two physical gates per pixel, with each gate having both a transfer and a storage region formed in the silicon under it. There are two voltage phase lines Φ, and Φ~. The charge coupling concept is used in frame transfer and interline transfer CCD image sensing devices. An example of a frame transfer area image sensor 10 is shown in FIG. 1. A schematic cross-section for a true two phase CCD is shown in FIG. la. A true two phase CCD is described in detail in commonly assigned U.S. Patent 4,613,402 to Losee and Lavine. A true two phase CCD has storage and transfer regions beneath each phase gate. In FIG. la the phase gates are labeled by either first or second polycrystalline silicon (poly-Si), and the transfer and storage regions by regions (1) and (2) for Φ, and (3) and (4) for y • In this disclosure only n-channel devices will be considered. In such devices the majority carriers are holes and the minority or signal carriers are electrons. This invention applies equally to p-buried channel devices. For an n—channel CCD, which is illustrated, the buried channel is formed by an n-type doping in a p-type substrate or in a p— ell in an n—type substrate. The transfer and storage buried channel regions are differentiated by less or more of the n-buried channel doping, respectively. U.S. Patent 4,613,402 discloses a detailed procedure for making true two phase CCD devices. The electrostatic potential band diagram through one of the phase gate electrodes, the buried channel and the substrate of an image pixel is shown in FIG. 2. The buried channel is shown reverse biased and with a positive gate voltage, Vg, to create a depleted surface. In this situation, the Fermi level (E F ), although not shown, will be near the middle of the band gap at the oxide-Si interface. In a buried channel CCD, dark current arises from three main sources: (1) generation from a mid— ap state resulting from either the disrupted lattice or an impurity at a depleted Si-Si0 2 interface, (2) generation in the depletion region as a result of an impurity or defect with a mid-gap state and (3) diffusion of minority carriers to the buried channel from the substrate. All three sources result in spurious charges being collected as signal in the buried channel. The mechanism for dark current generation both at the surface and in the depletion region is illustrated in FIG. 2 and is as follows: A generation site (defect) emits an electron (negative charge) into the conduction band in the buried channel and a hole (positive charge) into the valence band. In both cases, the electron is captured by the buried channel as dark signal, and if the spatial region where the hole is emitted to the valence band is depleted of majority carriers then the holes will migrate away from their point of generation thus leaving the region depleted of majority carriers. A hole generated in the depletion region is driven to the substrate. A hole generated at the surface goes laterally to a channel stop region, again leaving the surface depleted of majority carriers. Since the state of the generation regions is now exactly the same as before the electron and hole emission events, the surface and depletion region defects continue to generate electron and hole pairs, thus acting as sources of dark current. This generation process ceases only if an excess of either electrons or holes develop in the region where the defect exists. Modern fabrication technology has reduced the concentrations of both defects in the depletion region and also defects leading to bulk current to such an extent that the surface state generation mechanism is the dominant source of dark current in buried channel CCDs . Accordingly, it is an object of this invention to reduce this surface state component of dark current. Disclosure of the Invention To accomplish the above object there is provided a method of reducing dark current in a buried channel CCD in which a pixel is defined by at least two adjacent electrodes, comprising the step of: during the operation of such CCD simultaneously placing all electrodes in the accumulation mode of operation. In accordance with this invention, dark current generation is very effectively suppressed by holding all phase gates in the accumulation mode of operation for all but the time needed for the actual transfer of charge from one CCD stage to the next. In order to operate in the accumulation mode of operation, a voltage must be applied that attracts majority carriers to the silicon-Si0 2 interface. For n—channel devices the majority carriers are holes and for p-channel devices the majority carriers are electrons, therefore the appropriate voltages for the accumulation mode are negative and positive for n— and p-buried channel devices, respectively. The true two phase architecture is ideally suited to this mode of operation. In accordance with this invention, the channel potentials beneath the barrier and storage regions must be chosen properly to avoid mixing of adjacent pixel signals when operating in the accumulation mode. This invention is suitable for use in frame transfer CCD imagers during both integration and readout. It can also be applied to interline transfer CCD imagers during readout of the optically generated signal. An advantage of the accumulation mode of operating a frame transfer CCD is to dramatically reduce the dark current during both integration and readout and the dark fixed pattern noise that accrues during integration. The dark current reduction translates into both increased dynamic range and reduced dark signal shot noise. Another advantage of this invention is the capability to accommodate interlaced operation during both integration and readout in a frame transfer image sensor without loss of performance by performing a one half stage normal transfer following one of the fields to assure proper pixel alignment to avoid pixel mixing during subsequent accumulation periods. Brief Description of the Drawings FIG. 1 is a schematic plan view of a true two phase area image sensor; FIG. la is a fragmentary, partially schematic vertical sectional view taken along the lines a-a of the two phase CCD device of FIG. 1 showing an image pixel; FIG. 2 is an electrostatic potential band diagram for the image pixel of FIG. la illustrating the mechanisms for the generations of dark current; FIGS. 3a and 3b illustrate electrostatic potential band diagrams similar to FIG. 2 showing surface depletion and accumulation modes of operation; FIGS. 4a and 4b are graphs which respectively illustrate gate voltage vs . channel potential and gate voltage vs. dark current for a gate of FIG. la; FIG. 5 schematically illustrates three gate electrodes of a true two phase CCD and potential wells under these gates when changing from the end of a transfer period through an accumulation mode of operating these gates; and FIG. 6 illustrates the electrostatic potential maximum, in volts, vs gate voltage for a vertical cross-section through regions (a), (c) and (d) of FIG. 5, as well as the charge capacity in 2 electrons/μm vs gate voltage for region (d) of FIG. 5. Mode of Carrying Out the Invention For illustrative purposes, the present invention is described with reference to a frame transfer CCD image sensor 10 as shown in FIG. 1. In this arrangement, charge transfer channels 12 run in vertical directions. Separating each transfer channel is a channel stop 14 which confines charge collected to the transfer channels and prevents charge leakage into adjacent channels. Each transfer channel 12 has a plurality of sensing elements or image pixels (or, for an interline transfer CCD, stages of the vertical shift register). Each pixel is defined by two closely spaced gates per pixel since this is a two phase device. The gate electrodes can be made from a transparent conductive material such as polysilicon. A potential is applied to each of the electrodes of each sensing element and a potential well or depletion region is formed under it. Charge, which is a function of scene brightness, is collected in the potential well. In a buried channel CCD, the electrodes are disposed on an insulator such as Si0 2 - The insulator overlies the substrate. The substrate is doped and can be of a given polarity, for example, p—type for an n—channel device. For an n-channel device, the surface region near the insulator in the substrate is n—polarity opposite to that of the bulk substrate and of such a concentration that when a predetermined potential is applied to the electrode, a potential well is formed within the substrate spaced from the insulator. The image sensor 10 comprises a frame transfer true two phase CCD having voltage phase lines Φ, and Φ and a buried channel. The pixels define a two dimensional array, which for illustrative purposes only, is shown to have 740 columns and 485 rows of pixels . Each transparent electrode is connected to one line or phase of a two phase voltage clock signal source. After exposure to incident light, the voltage signals on the phase lines are sequentially applied in the well known manner to the image sensing array to move the imagewise charge pattern formed in the pixels one row at a time to an output register shown as block H. High frequency clock pulses drive the polysilicon gate electrodes to read out each of the rows of the image sensor at a rate determined by the particular application. The output register H is shown schematically as a block since it can be provided by a conventional two phase CCD shift register positioned between an optional transfer gate 16 and a horizontal channel stop 18. The transfer gate 16 may be one of the phase clocks of the vertical register. Each cell of the output register H has two gate electrodes aligned with a transfer channel. These electrodes are actuated by signals on voltage lines Φ, through Φ 2 in the conventional manner. The transfer gate electrode 16 is actuated by a first transfer signal T, and transfers a row of photocharges to the output register H. After a row of photocharges has been transferred to the output register H, the transfer gate 30 is closed. By being closed is meant that a potential barrier is formed under this transfer electrode. At this time, the output register is operated in a two phase manner, clocking the photocharge out to an output diode 32, one pixel at a time. The output diode 32 converts the photocharges into a voltage. Before proceeding further, the mechanism for operating in the accumulation mode will now be discussed. The generation of dark current due to surface generation sites can be significantly reduced if a voltage is applied to a gate electrode to accumulate majority carriers under that electrode. This will be referred to as an accumulation mode of operation. The terms accumulation, depletion and inversion are accepted technical terms in the description of the physics of metal-oxide-semiconductor (M0S) devices, and they mean presence of majority carriers, absence of carriers and presence of minority carriers, respectively. The mechanism underlying this effect will now be discussed. The accumulation of holes or majority carriers at the Si-Si0 2 interface suppresses further generation of dark current and can be understood as driving the reaction of producing electron hole pairs (previously discussed) in the reverse direction, i.e., hole capture by the defect rather than hole emission from the defect. The state of accumulation of holes at the Si-Si0 2 interface beneath any CCD phase gate can be controlled by the voltage, Vg, applied to the gate. As is well known in the physics of M0S devices, the hole density in the valence band is determined by the separation of the Fermi level, E„, from the valence band, Ev. The density of holes increases dramatically when that separation becomes less than approximately 1/4 the band gap, i.e., the separation between Ev and Ec. The separation is controlled by the gate voltage, V In FIG. 3a, this separation is practically the entire band gap so the semiconductor surface just beneath the gate insulator is depleted of holes (majority carriers). FIG. 3b illustrates the condition of sufficiently more negative gate voltage than for FIG. 3a such that holes are attracted to the Si-Si0 2 interface beneath the gate electrode. At even more negative gate voltages, V-, the layer of holes shields the buried channel from the effects of the gate voltage. The gate is now accumulated with holes and the dark current drops to a low value. The channel potential, Vc, is the difference between the Fermi level for the substrate, E F , and the Quasi Fermi level for the empty buried channel. The value of Vc is controlled by the gate voltage, V until the gate voltage becomes sufficiently negative to accumulate the silicon surface beneath the gate insulator with holes, at which point G no longer controls Vc This is illustrated on FIGS. 4a and 4b. This transition occurs over a small gate voltage range. FIG. 4a shows the dark current reduction, and FIG. 4b shows the channel potential saturation when the surface is accumulated with holes. Turning now to FIG. 5 where the operation of the CCD of FIG. 1 in the accumulation mode is illustrated. At the top of this FIG. is a schematic representation of 1 and 1/2 pixels of the true two phase CCD shift register. One pixel is comprised of two gates. For each gate, the regions labeled (a), (c), and (b) and (d) are the transfer and storage regions of the gate's buried channel. See also FIG. la. It is important to note as shown in FIG. la the transfer regions (a) and (c) are more lightly doped (n ) than the storage regions (b) and (d) (n~) . It should be noted that other means than doping differences could be employed to form the storage and transfer regions beneath a phase gate. One suitable method is a gate insulator thickness difference. The storage region could be fabricated with a thicker gate insulator than the transfer region, for example. Lines 1-7 show the channel potential (solid line) and the location of the signal charge (shaded) in a sequence of times as the phase one gates are clocked into accumulation between stage-to—stage transfer down the CCD shift register. A discussion of the accumulation mode of operation during charge integration follows the discussion of accumulation during stage—to—stage transfer. (A) Pixel-to-Pixel Transfer Line 1: This is the voltage and signal charge configuration at the end of a normal stage-to-stage transfer down the CCD shift register. The voltage applied to phase line Φ 2 is low and that applied to Φ, is high. The signal charge resides in the storage well beneath the gates connected to Φ, . The surface component of the dark current is suppressed beneath the gate connected to Φ 2 . The dark current beneath the gate connected to Φ-, can also be suppressed by driving it into accumulation. Lines 2-4: Begin to take phase line Φ-, low, i.e. toward accumulation. All the signal charge still resides beneath the gate connected to Φ, . At some voltage on phase line, Φ-^, the transfer region becomes accumulated and this is the condition at line 4. At this point the channel potential in the transfer region saturates so that a further reduction in the Φ, voltage results in no further reduction in the channel potential beneath the gate transfer region connected to Φ, . Line 5: Because this transfer region is now accumulated, a further reduction of the Φ-i gate voltage results in a reduction in the channel potential of the storage region. As a consequence, the storage well begins to collapse, resulting in a decrease in the charge handling capacity of the Φ, gate. The excess signal spills either backward or forward, depending on the relative channel potentials of phases 1 and 2. In this example, the channel potential is greater beneath Φ,, so the excess charge spills backward and is shown shaded beneath Φ 2 . Line 6: The gate connected to Φ-, is now completely accumulated and the signal is now shared between the pixel gates connected to Φ, and Φ 2> Both gates of each pixel are now simultaneously in the accumulation mode of operation. This is illustrated by the shaded areas. The surface contribution to the dark current is now suppressed. The channel potentials should be chosen so that the charge capacity is not dramatically reduced, i.e., the accumulated charge capacity beneath one phase should be no less than approximately 1/2 the charge capacity in the normal unaccumulated bias condition, as is shown in line 2, since in the accumulated condition the signal is shared between both pixel gates. Line 7: At the time that a stage-to-stage charge transfer is to be made, the Φ, voltage is increased and all the signal is held beneath the gate connected to Φ-, again. The normal clocking sequence is applied to transfer the charge from one stage to the next, leaving the signal beneath the Φ, gate as shown in line 1, but transferred one full CCD stage along the shift register. The cycle of lines 1—6 can now be repeated to simultaneously accumulate both gates again to suppress the dark current between stage-to-stage transfer. The preceding procedure can be applied during the readout of either a frame transfer or an interline transfer CCD. Such a procedure is applied to the phase gates of the vertical CCD during readout of the horizontal output register. The minimum dark current reduction depends on the fraction of the total frame readout time the phase gates are accumulated. Furthermore, the dark current reduction may be larger if the majority carriers are not emitted from the mid-gap states during the time the gates are not accumulated during the stage-to-stage transfer along the CCD shift register. (B) Integration For the frame transfer architecture, the dark current can also be suppressed during integration, i.e., during the time that the sensor pixels are optically exposed. This is accomplished by biasing the gates as in line 6 of FIG. 5. The pixel must be defined just as in FIG. 5 to eliminate mixing of information between pixels. In FIG. 5 an image pixel is defined by the left gate connected to Φ 2 and the middle gate connected to Φ, since excess charge beneath one will spill into the other and therefore remain in the same pixel. The definition of a pixel is important if, for example, a color filter pattern is applied such that different colors occur in the same column. As in the case of accumulation during readout, for accumulation during integration the accumulation channel potential in the transfer region for Φ, gate must be more positive than the accumulation channel potential for the Φ 2 gate. Dark current reduction of 50 times have been noted for the full accumulation mode operation at room temperature for true two phase, frame transfer CCD imagers. FIG. 6 shows the electrostatic potential for the transfer and storage region for the Φ^ gate, along with its charge capacity. These curves are calculated from a one dimensional electrostatics model. The charge capacity is determined to be the quantity of charge required to fill the storage region so that its electrostatic potential reaches to within 1/2 volt of the transfer region channel potential. The doping distribution in the storage region (d) is selected to yield an electrostatic potential of 7.75 volts at Vg=0 and an accumulation electrostatic potential (large negative Vg) of 2.3 volts. The transfer region (c) has an electrostatic potential of 3.75 volts at Vg=0 and an accumulation channel potential of 1.75 volts. The charge capacity is also shown on the same scale and is at Vg=0 is approximately 10000 e/μ (electrons per square micrometer). As the gate is reduced and the potential well collapses the charge capacity diminishes and at accumulation of both storage and transfer gates the charge capacity becomes 2 approximately 5700 electrons/μm . In this state the excess charge is shared with the Φ, gate, so the 10000 electrons/μm 2 can easily be accommodated by the two regions of 5700 2 electrons/μm each when both phases are accumulated to reduce the dark current. Therefore the saturation or maximum charge capacity of the CCD is not reduced by the accumulation mode operation. The electrostatic potential of the Φ 2 transfer region is also included on FIG. 6. It is designed to be approximately 1/2 volt less positive than Φ, as required for a pixel definition as was discussed for FIG. 5. The experimentally measured channel potentials match the channel potential curves of FIG. 6, and the experimentally measured charge capacity is not diminished in the accumulation mode, which is consistent with the calculated charge capacity shown in FIG. 6. The invention has been described in detail with particular reference to a true two phase CCD preferred embodiment thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, it is also applicable to a pseudo two phase device. In such a device each pixel has four electrodes but there are only two phase lines Φ, and Φ 2 - The first two pixel electrodes are connected to Φ, and the second two electrodes are connected to Φ 2 . One member of each pair becomes the storage region and the other member of each pair becomes the transfer region. The values of the channel potentials of the storage and transfer regions of each pair must be chosen as described above for the true two phase in order to properly define a pixel.

Claims: CLAIMS : 1. A method of reducing dark current in a buried channel CCD in which a pixel is defined by at least two adjacent electrodes, comprising the step of: during the operation of such CCD simultaneously placing all electrodes in the accumulation mode of operation. 2. A method of reducing dark current according to claim 1 wherein said buried channel is a two phase buried channel having a repeating series of two gate pixels with the first pixel gate being connected to a phase line Φ., and the second pixel gate to a phase line Φ 2 , appropriate voltage being simultaneously applied to both phase lines Φ.. and Φ 2 so that the gates of each pixel are in the accumulation mode of operation. 3. A method according to claim 2 wherein each buried channel gate has transfer and storage regions sequentially formed under each gate, the difference in channel potentials of the transfer regions being chosen so that a given pixel signal is not mixed with signals contained in adjacent pixels. 4. A method according to claim 3 wherein said buried channel CCD has a p-type substrate and an n-buried channel. 5. The method of claim 4 wherein the CCD is an image sensor and its gate electrodes are transparent and charge intergates in potential wells under each gate electrode of a pixel when they are held in the accumulation mode of operation. 6. The method of claim 4 wherein charge is transferred from one pixel to another. 7. A method according to any of claims 3 to 6, wherein the transfer regions are the transfer regions to be more lightly doped (n ) than the storage regions (n-) so that a given pixel signal is not mixed with signals contained in adjacent pixels. 8. The method of claim 7 wherein the CCD is an image sensor and its gate electrodes are transparent and charge intergates in potential wells under each gate electrode of a pixel when they are held in the accumulation mode of operation. 9. The method of claim 7 wherein charge is transferred from one pixel to another. 10. A true two phase CCD having a repeating series of two gate pixels, comprising an n-buried channel under such repeating series of gates and provided with transfer and storage doping regions under each gate, the transfer regions being more lightly doped (n ) than the storage regions (n — ) under the gates of each pixel such that a given pixel signal is not mixed with signals contained in adjacent pixels.

Inventors: BURKEY BRUCE, CHANG WING-CHYI, LEE TEH-HSUANG, BURKEY, BRUCE, CHANG, WING-CHYI, LEE, TEH-HSUANG
Applicants: EASTMAN KODAK CO, EASTMAN KODAK COMPANY
Application year: 1990
Main classification: H01L27
IPC codes: H01L27