Image processing system

Abstract: An image processing system, comprising: a camera for taking a picture image of an object and producing a corresponding picture image signal; a binary discrimination circuit for converting the picture image signal into a binary signal; a memory unit for storing the binary signal; and feature extracting circuit for extracting a geometric feature of the picture image by processing the binary signal. Preferably, the feature extracting circuit comprises: an edge detection circuit having a hardware structure; and an arithmetic processing unit for computing, through a software process, geometric features from a graphic image included in the picture image of the object according to data on edge addresses. Thus, the processing speed is increased and the size and cost of the system is reduced by carrying out edge detection and address data collection requiring a large amount of processing work by means of a dedicated hardware circuit and carrying out arithmetic and other processes by means of software. Further, since the software of its arithmetic unit can be easily modified, the versatility of the processing work can be improved, and the range of application of the system can be broadened.

Description: TECHNICAL FIELD The present invention relates to an image processing system having a function to detect an edge of a graphic image included in an inputted picture image and to extract features, such as an area, a gravitational center, an inclination and so on, of the graphic image. BACKGROUND OF THE INVENTION The present invention is intended to increase the processing speed and to reduce the size and cost of an image processing system for detecting an edge of a graphic image included in an inputted picture image by carrying out edge detection and address data collection requiring a large amount of processing work by means of a dedicated hardware circuit and carrying out arithmetic and other processes by means of software. Conventionally, with regard to such an image processing system, there have been known two methods for extracting features of a graphic image: (1) Computing representative values of a graphic image after writing image data into a memory and carrying out a software process thereon; and (2) Computing representative values of a graphic image as a hardware process either while writing image data into a memory or after writing image data into a memory. However, in the case of (1) the software process, because of a limited processing speed, a considerable time is required for the computing process. In the case of (2) the hardware process, the computing speed is high but the system tends to be bulky and expensive, and limited in versatility. In some applications of industrial image processing systems, it is highly desired to compute the locations of the centers of gravity of objects to be inspected or monitored. When there are a plurality of objects in a single frame, it is necessary to compute the center of gravity for each of the objects. Conventionally, each frame was divided into a plurality of windows each containing one of the objects to be monitored, and the arithmetic operation for finding the center of gravity was carried out on each of the objects or, in other words, each of the windows defined in the single frame. However, according to this conventional process, the time required for carrying out the necessary arithmetic operation increased in proportion to the number of objects in each frame, and this process was found to be impractical when there are a substantially large number of objects in each frame. Conventionally, in an image processing system for measuring such geometrical features as areas, gravitational centers, inclinations and so on, it has been customary to provide a memory having the same capacity as the size of the frame, and measure each part of the picture image transferred onto one of a plurality of windows after transferring the picture image onto the same coordinates in the memory so as to permit to read out and process the memory contents during the measurement process. However, such a conventional process has the following problem. Suppose that the frame size is given by 512 by 512 pixels as shown in Figure 11, and windows are defined around the coordinates of three objects A, B and C in a picture image. According to this conventional method, when three objects A, B and C are included in a frame D, it was necessary either to prepare a window memory for three frames or to rewrite the contents of the memory for the measurement process of each of the windows. Therefore, no matter how small the windows may be, it was necessary to prepare a memory having a capacity for the same number of frames as there are windows, and the necessary capacity of the memory increased in proportion to the number of the windows. If the capacity of the memory is not increased, it becomes necessary to rewrite memory each time a measurement for a new window is to be carried out, and the processing speed is significantly reduced. In some applications, it is desired to detect differences in gradation levels. When a monochromatic CCD camera or the like is used, differences in color may be detected as differences in gradation levels. An image processing system which is capable of detecting fine differences in gradation levels can offer an improved inspection capability through mechanization of the visual inspection of industrial products which has conventionally been performed by naked human eyes. However, according to conventional image processing systems, because of the use of a gradation recognition system based on the conversion of the gradation levels of the products to be inspected into binary data by defining a certain threshold level, the following problems existed. Specifically, when the difference in gradation is small between an industrial product or an object and its background, for instance when the product is yellow while the background is white, extraction of the external view of the product tends to be difficult, extraction of an arbitrary extraction level may be impossible, and the circuit structure tends to be complex when a plurality of windows are defined in a single frame and a threshold level is to be defined individually for each of the windows. Also, according to the conventional technology, it has been impossible to inspect the gradation of industrial products when a plurality of windows are superimposed one over the other. An image processing system according to the preamble of claim 1 is known from DE-A-3 718 620. WO-A-87/07057 discloses determining the length of a contour for feature extraction by determining contour pixels as pixels in whose neighbourhood at least one background pixel exists. BRIEF SUMMARY OF THE INVENTION In view of such problems of the prior art, an object of the present invention is to provide an image processing system which can compute representative values of a graphic image in a short time and which is compact and economical. Another object of the present invention is to provide an image processing system which can significantly reduce the necessary capacity of memory and increase the processing speed of an image processing system having a plurality of windows in a single frame by dividing the frame into a plurality of windows in such a manner that the picture images of the objects are recorded in the window memory for each of the windows, and drawing the picture images of the objects onto a plurality of divided regions depending on the sizes of the windows. Another object of the present invention is to provide an image processing system which can find the peripheral length of a picture image on a real time basis so as to be used in automated manufacdturing process or the like. The image processing system according to the invention is as defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an embodiment of an image processing system; Figure 2 is illustrating the process of computing representative values of geometric features of a graphic image; Figure 3 is a diagram illustrating an example of a data pattern on a horizontal line; Figure 4 is a view illustrating a window defined in a frame; Figure 5 is a view illustrating a window defined in a frame to illustrate the operation in another embodiment; Figure 6 is a diagram illustrating the relationship between the window table and the cumulative arithmetic values table defined in the memory; Figure 7 is a time chart showing the outline of the operation of that embodiment during a single field period; Figure 8 is a block diagram of the hardware for that embodiment; Figure 9 is a more detailed block diagram of the arithmetic operation circuit in Figure 8; Figure 10 is a time-chart showing the operation of that embodiment given in Figure 8; Figure 11 is a front view showing how picture images of objects can be drawn on a frame without modifying their relative positions; Figure 12 is a block diagram showing the electric structure of an image processing system constructed as an embodiment of the present invention; Figure 13 is a front view showing an example of display of an object in a frame; Figure 14 is a time chart showing the outline of the operation of a first embodiment of the invention; Figure 15 is an example of the peripheral length measuring circuit according to the present invention; Figure 16 is a time chart describing the relationship between the horizontal synchronization signal and the vertical synchronization signal according to the present invention; Figure 17 is a front view showing a plurality of windows defined in a single display frame to illustrate another embodiment of the present invention; Figures 18(A), 18(B) and 18(C) showing the relationship between the contents of the vertical table and the window table, and the peripheral lengths areas; Figure 19 is a time chart showing the outline of the operation of the sixth embodiment during a single field period; Figure 20 is a block diagram of the hardware for the sixth embodiment; and Figure 21 is a time chart for describing the operation of said another embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) Now among others preferred embodiments of the present invention are described in the following with reference to the appended drawings. Figure 1 is a block diagram of the electric structure of an image processing system. In the drawing, an A/D converter 2 converts an image signal supplied from a camera 1 into a digital signal and supplies it to an image memory 3. The image memory 3 stores the inputted digital signal and supplies the contents of the stored image signal to a binary discrimination circuit 5 at a predetermined timing. The binary discrimination circuit 4 discriminates the digitalized image signal supplied thereto by a predetermined level and converts it into binary data consisting of either "0" or "1", and sends it to an edge measurement circuit 5. The edge measurement circuit 5 detects a reversion of data, or transition from "1" to "0" or from"0" to "1", on each of the horizontal lines defining a picture image to determine it as an edge of the picture image, and extracts an address (X coordinate) of a point on the line corresponding to the detected edge to send this address to the edge information memory 6. The edge detection memory 6 stores data on the inputted addresses, and send it to a data/address bus 7 as required. A microcomputer unit is formed by a CPU 8, ROM 9, RAM 10 and so on connected to this data/address bus 7. This microcomputer unit reads out edge address data stored in the edge information memory 6 via the data/address bus 7 so as to recognize a graphic image included in a window defined within the picture image and to compute the area, gravitational center, inclination and so on of the graphic image. In other words, according to this system, the processes of detecting an edge of a graphic image contained in an inputted picture image and writing down edge address data thereof are assigned to a dedicated hardware circuit while the process of computing an area, a gravitational center, an inclination and so on is assigned to a microcomputer. Since edge detection by a dedicated hardware circuit can be carried out in a continual fashion as opposed to a software detection process which needs to be carried out pixel by pixel, a significant improvement can be accomplished in the processing speed of detecting an edge which requires a most significant amount of processing work. Further, by having a microprocessor carry out the process of writing edge address data and the subsequent processes, the size and cost of the system can be reduced, and the parameters of process execution can be readily modified simply by changing the program. Now is described the procedure for computing representative values from a graphic image by using edge address data. Generally speaking, the area (AREA), the gravitational center (XG, YG), and the major axis angle () defined in a two-dimensional coordinate system by dots are determined by the following equations: where To simplify the expression of these equations, the following definitions are made. Thus, equations (2), (3), (5), (6) and (7) can be expressed as given in the following: XG = SUMX AREA YG = SUMY AREA M 1,1 = SUMXY - SUMX SUMY AREA M 2,0 = SUMX2 - SUMX 2 AREA M 0,2 = SUMY2 - SUMY 2 AREA In the above equations, f(i,j) is either "0" or "1" as the graphic image is expressed by binary data. How AREA, SUMX, SUMY, SUMXY, SUMX2 and SUMY can be determined is illustrated in Figure 2 in regards to a specific example of binary picture image. In the case of the illustrated picture image, AREA, SUMX, SUMY, SUMXY, SUMX2 and SUMY2 can be determined by obtaining (1) the number of computed pixels (2) a weighted sum of the data at each X-coordinate taken along the X-direction, and (3) a weighted sum of a square of the data at each X-coordinate taken along the X-direction for each line, while using the Y-coordinates as a counter, and adding them up. When these values are substituted into equations (1) through (12), an area, a gravitational center and a major axis angle can be obtained. Now is described how (1) the number of pixels to be computed, (2) the weighted sum of the data at each X-coordinate along the X-direction, and (3) the weighted sum of a square the data at each X-coordinate along the X-direction can be computed for each line from the edge address data. When the edge coordinates in the pattern for each horizontal line are obtained as illustrated in Figure 3, the weighted sum of the data values (S n ) and the weighted sum of the squared data values (D n ) can be determined as given in the following: Since the following relations generally hold, once the edge coordinates (X a and X b ) of the pattern are known, the weighted sum and the weighted sum of the squared values can be determined as given by the following: According to this embodiment, the contents of the image memory 3 are converted into binary data by a binary discrimination circuit 4, and this information is supplied to the edge measurement circuit 5 for each horizontal line. The edge measurement circuit 5 detects each transition point (pixel) from 0 to 1 or from 1 to 0 for each horizontal line from left to right, and stores the detected X-coordinates in the edge information memory 6. The contents of the edge information memory 6 are read by the CPU 10 from right to left. Further, according to the present embodiment, an arbitrary rectangular region is assigned as a window on the screen as shown in Figure 4, and edge information within this arbitrary region is taken out in order to achieve a high versatility. The drawing shows it with respect to only one line. This window is defined by the coordinate of the upper left corner (X b , Y b ) and its size (X s , Y s ). In this case also, AREA, SUMX, SUMY, SUMXY, SUMX2 and SUMY2 are computed as given in the following: where E' n = E n + X b By substituting equations (17) through (22) into equations (8) through (12), an area, a gravitational center and a major axis angle can be obtained. In regards to equations (18), (20) and (21), if they are stored as tables containing results of computation, an even more significant reduction in computation time can be achieved. According to this embodiment, by obtaining the edge addresses of a graphic image by hardware, and by carrying out the above listed computations based upon this information by software, graphic features such as areas, gravitational centers, and major axis angles can be obtained both simply and quickly. Moreover, by modifying the software, it is possible to additionally obtain other graphic features such as the circumferential lengths, the numbers of holes and the numbers of graphic images. Figures 5 through 10 show another embodiment. Referring to Figure 1, three windows (processing regions) W1, W2 and W3 are defined in a single frame which consists of 256 by 242 pixels. Each horizontal line consists of 256 pixels. The number of windows may be selected as desired. However, each window must contain at least two by two pixels, and must be spaced from a horizontally adjacent window at least by one pixel. The lateral spacing of the windows is determined according to the operation speed of high speed memory as described hereinafter. On the other hand, the windows may closely adjoin each other in the vertical direction as long as they do not overlap each other. Therefore, it is possible to define more than 10,000 windows in a single frame. Further, each of the windows of the illustrated embodiment is rectangular but may have different shapes if desired. Each of the windows includes a picture image which is, in the illustrated embodiment, given as a shaded area represented by a set of binary data. The present embodiment is capable of detecting the center of gravity of each of such picture images. Suppose that the center of gravity of one of the picture images is given by a coordinate (X G , Y G ). It is known that the center of gravity is given by the following formulae: where f(i,j) is a weighting function which, in the present embodiment, is either "0" or "1" as the picture image is given as a set of binary data. In other words, for those pixels included in the picture image f(i,j) = 0 and for those pixels not included in the picture image f(i,j) = 1 Nj denotes the number of pixels in the j-th horizontal scanning line. The process of executing the arithmetic operation given by equations (23) and (24) may be carried out in the following manner: (1) Measure the values of N j , and N j j for each of the windows; (2) Add up the respective values for each of the horizontal scanning lines, to thereby obtain the numerators and denominators of equations (23) and (24); and (3) Carry out the arithmetic process given by equations (23) and (24) according to the values obtained in step (2) after completion of the scanning of each horizontal scanning line, to thereby obtain the coordinate of the gravitational center (X G , Y G ). Reading of data by picture taking means such as a CCD camera takes place along each horizontal scanning line j, and the horizontal scanning lines are scanned downwards from the upper most line to the lower most line in a sequential manner. In the present embodiment, since a plurality of windows are defined in each frame, it is necessary to distinguish the windows located along common horizontal scanning lines in step (2). To this end, a window table as shown in Figure 6(a) is defined in a system memory which stores the windows (in the form of addresses of the cumulative arithmetic operation values table as described hereinafter) which are encountered during the scanning process in the order of their first encounters. To execute the cumulative additions of the arithmetic operation values N j , and N j j in step (2), there is defined a cumulative operation values table to store the cumulative operation values for each of the windows as illustrated in Figure 6(b). In this table, the cumulative operation values for the window W1 (m 100 are stored at address WA1. Likewise, the cumulative operation values for the windows W2 and W3 are stored at addresses WA1 and WA2, respectively, or (m 200 , m 210 , and m 201 ) at address WA1 and (m 300 , m 310 , and m 301 ) at address WA3. Referring again to Figure 6(a), the addresses WA1 through WA3 of the cumulative arithmetic values table are stored in the window table in the order of the appearance of the corresponding windows W1 through W3. Now the overall processing of a single field of data or a single frame is described in the following. Figure 7 shows a vertical synchronization signal VD, a horizontal synchronization signal HD, and a window signal WD. The window signal WD is produced from the window memory in synchronism with the operation of the picture taking means as described hereinafter, and represents the positions of the windows in the frame. During the scanning of the first horizontal scanning line (j=1), the three arithmetic operation values are computed in regards to the picture image included in each of the windows located along the horizontal scanning line. In the present embodiment, as there is no window which is located on the first horizontal scanning line, no arithmetic computation takes place. During the scanning of the second horizontal scanning line (j=2), an address WT1 of the window table is looked up upon rising of the window signal WD, and, as result, it is found that this window corresponds to the window (or the window W1) which is to be stored at the address WA1. Therefore, during the time the window signal WD is high, the arithmetic operation values are computed. When this window signal WD has dropped to a low level, the arithmetic operation values are added to the cumulative operation values stored at the address WA1 of the cumulative operation values table. When the window signal WD has risen back to the high level again, the address WT1+1 of the window table is looked up, and it is found that this window correspond to the window W3.. In a similar fashion as described above, during the time the window signal WD is high the arithmetic operation values are computed, and every time the window signal has dropped to the low level, the arithmetic operation values are added to the cumulative operation values stored at the address WA3 of the cumulative operation values table. During the scanning of the third horizontal scanning line (j=3), the window table is looked up upon rising of the window signal WD, and, as result, it is found that this window corresponds to the window W1. And, again, during the time the window signal WD is high, the arithmetic operation values are computed, and every time the window signal WD has dropped to the low level, the arithmetic operation values are added to the cumulative operation values stored at the address WA1 of the cumulative operation values table. In this way, the windows W2 and W3 are identified by looking up the window table following the detection of the rises in the window signal WD. This process is repeated until the 242nd horizontal scanning line is covered, and the arithmetic operation values are stored in the corresponding addresses of the cumulative operation values table for each of the windows. When the scanning of the 242nd horizontal scanning line is completed, the cumulative operation values in the cumulative operation values table are read out, and the coordinate of the center of gravity of the picture image in each of the windows is obtained by carrying out the arithmetic operation in step (3) for each of the windows. Figure 8 shows an example of the image processing system according to the present embodiment. A camera 11 comprises a image tube or a solid state image sensor such as CCD, and produces an image signal. The produced image signal is processed by a synchronization signal separation circuit 12, and a sampling clock for each of the pixels, a horizontal synchronization signal HD, and a vertical synchronization signal VD are obtained. The image signal is then supplied to a binary discrimination circuit 13, and is converted into a binary signal which is either "o" or "1" by comparing the analog image signal with a certain threshold level. A window memory 14 stores such binary data, and has a capacity to store the data for a single frame according to the present embodiment. Further, the windows W1, W2 and W3 as illustrated in Figure 5 are also stored in the window memory, for instance by writing bit "1" into areas belonging to any of the windows and bit "0" into areas not belonging to any of the windows. Such a definition of windows is executed by a CPU 15. The reading of data from the window memory is executed according to sampling clock CK, and the obtained data is converted into a window signal WD which is supplied to a gate 16. The gate 16 is controlled by a measurement timing signal which is high (H) during each field of data is covered and is otherwise low (L). The gate 16 permits transmission of the window signal WD only during each measurement field. The window signal WD is in exact synchronism with the image signal from the camera 11. In other words, when the image signal is indicating the q-th bit of the p-th horizontal scanning line, the window signal WD also is indicating the q-th bit of the p-th horizontal scanning line. Another gate 17 permits transmission of the binary image signal to an arithmetic operation circuit 18 only when any one of the windows is present. A timing control circuit 19 generates control signals for a high speed memory 19 for the window table, and a high speed memory 20 for the cumulative arithmetic operation values table according to the window signal WD and the sampling clock CK. The window table and the cumulative arithmetic operation values table are created by the CPU 15 prior to the start of the measurement. A window counter 22 counts pulses in the window signal WD and accordingly defines the addresses of the high speed memory 20 (WT1 through WT1+n as given in Figure 6(a). The image processing system of the present embodiment further includes an arithmetic operation circuit 18 which computes the three arithmetic operation values N j , and N j j, and an adder 23 which adds the outputs from the arithmetic operation circuit 18 to the cumulative arithmetic operation values read out from the high speed memory 21, and the obtained sums are again stored into the same addresses of the high speed memory 21. A specific example of the arithmetic operation circuit 18 is given in Figure 9. A pixel counter 31 counts the number of pixels N j from the binary image signal for each horizontal scanning line of each frame, and supplies its output to the adder 23 shown in Figure 8 via a latch circuit 32. The pixel counter 31 is cleared by each falling edge of the window signal WD. The vertical counter 33 counts pulses from the horizontal synchronization signal HD, and determines the vertical coordinate j. The vertical coordinate j is multiplied by the number of pixels N j at a multiplier 34, and its output is supplied to the adder 23 of Figure 8 via a latch circuit 35. The vertical counter 33 is cleared by the vertical synchronization signal VD. The horizontal counter 36 counts pulses from the sampling clock CK, and determines the horizontal coordinate i. An adder 37 and a latch circuit 38 connected to the output end of the horizontal counter 36 produces a cumulative sum for the regions occupied by picture images on each horizontal scanning line, and likewise supply an output to the adder 23 shown in Figure 8. The horizontal counter 36 is cleared by the horizontal synchronization signal HD. Referring to Figure 8 again, the CPU 15 comprises PROM 24 storing the operation program for the CPU 15 and RAM 25 storing the finally obtained coordinates of the centers of gravity as well as data produced during the course of the arithmetic operations. The CPU 15 carries out, as mentioned above, writing of data into the window memory 14, writing of the window table into the high speed memory 20, initialization (clearing) of the cumulative arithmetic operation values table, reading out of the cumulative arithmetic operation values for each of the windows, and computation of the coordinate of the center of gravity of the picture image in each of the windows according to the obtained cumulative arithmetic operation values. Before measurement is started, writing of data into the window memory 14, creation of a window table in the high speed memory 20, clearing of the cumulative arithmetic operation values table, and presetting of the window counter 22 to WT1-1 are carried out. Once the measurement signal has risen to the high level, the cumulative arithmetic operation is started. Now the process of this arithmetic operation is described in the following taking the example of the window W3 in the third horizontal scanning line with reference to Figure 10. When the window signal WD has risen to the high level, the count of the window counter is incremented from WT1+1 to WT1+2. During the time the window signal WD is high, arithmetic operations for derivation of the arithmetic operation values N j , and N j j are carried out by the arithmetic operation circuit 18, and this process is terminated when the window signal WD has fallen to the low level. When the count of the window counter 22 is incremented to WT1+2, data WA1 at address WT1+2 is read out from the high speed memory 20. The read out data WA1 gives the address of the high speed memory 21 from which the cumulative arithmetic operation values (m 101 , m 110 , and m 100 ) for the window W1 up to the current moment are read out. The adder 23 is activated when the window signal WD falls to the low level to add up the computation results of the arithmetic operation circuit 28 with the cumulative arithmetic operation values read out from the high speed memory 21. Meanwhile, the high speed memory 21 is switched over from a read mode to a write mode, and the results of summing by the adder 23 are written into the address WA1. The cumulative arithmetic operation for the window W1 is completed in this fashion. When the cumulative arithmetic operation for the entire frame is completed, the CPU 15 reads out the cumulative arithmetic operation values from the high speed memory 21 for each of the windows, and carries out the arithmetic operation given by equations (23) and (24) to obtain the center of gravity of the picture image included in each of the windows. Referring to Figure 12 illustrating the hardware structure according to an embodiment of the present invention in a highly simplified fashion, numeral 81 denotes a camera which can take the pictures of stationary or moving objects and produces a video signal representing the distribution of different gradation levels in an analog form. Numerals 82 and 83 denote a synchronization signal separation circuit and a binary discrimination circuit for converting the analog video signal into a set of digital data accompanied by synchronization signals required for reproducing the original picture image by electronic means. Numerals 84 and 85 denote single horizontal scanning line delay circuits, and numerals 86 through 88 denote shift registers. Numeral 89 denotes a peripheral length detection circuit, and numerals 90 through 93 denote counters. Numerals 94 through 97 denote tri-state buffers, and numerals 98 and 99 denote a decoder and a CPU, respectively. Now the operation of this system is described in the following with reference to Figures 12 through 16. The output from the vide camera 81 is supplied to the synchronization signal separation circuit 82 and the binary discrimination circuit 83. The synchronization signal separation circuit 82 separates a horizontal synchronization signal HD and a vertical synchronization signal VD from the video signal, and generates a clock signal CK. The video signal representing the gradation distribution of the picture image is converted into a set of binary data by the binary discrimination circuit 83 according to a predetermined threshold level. The thus obtained binary signal is then supplied to the three shift registers 81, 82 and 83, directly, via one of the single horizontal scanning line delay circuit 84 and via both the single horizontal scanning line delay circuits 84 and 85, respectively. Thus, the first shift register 81 stores the binary video signal B1 which is delayed by two horizontal scanning lines, the second shift register 82 stores the binary video signal B2 which is delayed by one horizontal scanning line, and the third shift register 83 stores the current binary video signal B3. Since each of the shift registers 81 through 83 is provided with three storage locations, a three by three bit pattern consisting of a current bit and eight adjoining bits covering three horizontal scanning line can be obtained. This bit pattern is then supplied to the peripheral length detection circuit 89 which is shown in greater detail in Figure 27. In the peripheral length detection circuit given in Figure 15, output E1 is brought to high level when a horizontal component of the peripheral length is detected. Output E2 is brought to high level when a vertical component of the peripheral length is detected. Output E3 is brought to high level when a rightwardly rising component of the peripheral length is detected. Output E4 is brought to high level when a leftwardly rising component of the peripheral length is detected. Referring to Figure 12, the output signals E1 through E4 are supplied to enable terminals of counters 90 through 93. These counters 90 through 93 are reset by the inverted signal of the vertical synchronization signal, and receive the inverted sampling clock CK as their count clock. Thus, the outputs of the counters L1 through L4 give the total number of the components of the peripheral length within a single field or over an entire frame. Specifically, the output L1 gives the total number of the horizontal components of the peripheral length, the output L2 gives the total number of the vertical components of the peripheral length, the output L3 gives the total number of the rightwardly rising components of the peripheral length, and the output L4 gives the total number of the leftwardly rising components of the peripheral length. Figure 13 illustrates the binary data image during the process of incrementing the number of the components of the peripheral length, and Figure 14 is a time chart describing this process. Referring to Figure 13, the shaded parts corresponding to the pixels which are occupied by a picture image of interest. Suppose that a first peripheral length component is detected at X=n-1 and Y=m. As a horizontal component and a rightwardly rising component of the peripheral length exit in the eight adjacent bit pattern, the enable terminal El of the counter 90 and the enable terminal E3 of the counter 92 are brought to high level. The outputs of the counters 90 and 92 are both "1" at the subsequent falling edge of the sampling clock CK. When the center bit of the eight adjacent bit pattern is at X=n and Y=m, as there exists only a leftwardly rising component of the peripheral length, the enable terminal E4 of the counter 93 is brought to "1". The output of the counter 93 is "1" at the subsequent rising edge of the sampling clock CK. In this way, the counters 90 through 93 add up the total numbers of the different components of the peripheral length over a single field of video data or while an entire single frame is scanned. During the period of suppressing the vertical return line, the CPU 99 reads out the values of L1, L2, L3 and L4. Thereafter, the leftwardly and rightwardly increasing components are multiplied by the square root of 2, or the peripheral length of the picture image is obtained according to the following formula: L1 + L2 + 2 (L3 + L4) The peripheral length detection circuit given in Figure 15 is only an example, and does not limit the present invention in any way. Thus, depending on the kind of the specific peripheral length detection circuit, the arrangement and number of the counters may change. Figures 17 through 21 show another embodiment of the present invention. Figure 17 illustrates three windows W1, W2 and W3 defined in a single frame which consists of 256 by 242 pixels according to the present embodiment. The numbers and locations of the windows can be freely selected. Each window satisfies the following five conditions: (1) Each window includes at least two by two pixels; (2) Each horizontally adjacent pair of windows must be spaced from each other by at least one or two pixels; (3) Each vertically adjacent pair of windows may directly adjoin each other as long as they do not overlap each other; (4) Each object must be separated from each other by at least one or two pixels along the horizontal direction, and by at least one pixel along the vertical direction; and (5) Each object is completely encompassed by the associated window (An outer most pixel of an window may coincide with the outer periphery of the associated object. The present embodiment can measure the peripheral length of the object in each of the windows. The peripheral length is here defined as the total length of the lines connecting the centers of the pixels located along the periphery of each object. In this embodiment also, the different peripheral components are detected by using three by three pixels (eight adjacent bits pattern) and grouped into horizontal components (H), vertical components (V), rightwardly rising components (R), and leftwardly rising components (L). When the window W1 is considered, H11 = V11 = L11 = 1 and R11 = 0 for a horizontal scanning line y2, H12 = L12 = 0 and V12 = R12 = 1 for a horizontal scanning line y3, H13 = V13 = 0 and R13 = L13 = 1 for a horizontal scanning line y4, and H14 = 1 and V11 = L11 = R11 = 0 for a horizontal scanning line y5. Therefore, the peripheral length of the picture image in the window W1 is given as follows: ΣN1j = ΣH1j + ΣV1j + 2 (ΣR1j + ΣL1j) = (1 + 0 + 0 + 1) + (1 + 1 + 0 + 0) + 2 {(0 + 1 + 1 + 0) + (1 + 1 + 0 + 0)} = 4 + 4 2 . The peripheral lengths of the picture images in the other windows W2 and W3 can be computed in similar fashions. The above described process can be summarized as given in the following: (1) The different peripheral length components are detected and grouped into horizontal components (H), vertical components (V), rightwardly rising components (R), and leftwardly rising components (L) by evaluating picture image data over two adjacent horizontal scanning lines, and are individually added up for each of the windows; (2) The numbers of the data in the different component groups are individually added up for each of the windows; and (3) The peripheral length of the picture image in each of the window is obtained according to the following formula: ΣNki = ΣHki + ΣVki + 2 (ΣRki + ΣLki) where k denotes each window and i denotes each horizontal scanning line. Reading of data from the camera is carried out along the horizontal scanning line, and the current scanning line moves sequentially downwards. Since each horizontal scanning line may pass through a plurality of windows (for instance W1 and W3 along the horizontal scanning line y2), detection of horizontal components (H) must be carried out for each of the windows, and different windows located along a same horizontal scanning line must be distinguished one from the other. To this end, a vertical address table as shown in Figure 18(A) and a window table as shown in Figure 18(B) are provided. The window table stores the pattern of the crossing of the windows by the horizontal scanning line in the order of each occurrence, and if a plurality of horizontal scanning lines have a same pattern they may share this same pattern. In the window table, the two storage areas in the starting addresses WT1 and WT1+1 store the pattern of the appearance of the windows on the horizontal scanning line from the beginning. This pattern data specifically consists of the peripheral length area addresses (WA1, WA3, etc.) as will be described hereinafter. In the window table, a plurality of storage areas for storing at least on sequential pattern are assigned with consecutive addresses. The vertical address table is provided with the same number of storage areas as the number of the horizontal scanning lines, and these storage areas are assigned with consecutive addresses. According to the present embodiment, address 1 through 242 are assigned to the storage areas for the first through 242nd horizontal scanning lines. Each storage area stores the start address (such as WT1, WT2, etc. shown in Figure 18 (A)) of the storage areas of the window table containing the pattern of the sequential appearance of windows along the associated horizontal scanning line. The addresses of the vertical address table is incremented by the count of a vertical counter counting the pulses in the horizontal synchronization signal. In order to execute step (2) or the process of counting the four different peripheral length components for each of the windows, peripheral length storage areas are defined as illustrated in Figure 30(C) for storing the numbers of the four different peripheral length components for each of the windows. In these storage areas, the first address WA1 corresponds to the first window W1, and includes four storage areas for storing the four different peripheral length components. The second and the third addresses WA2 and WA3 likewise correspond to the second and third windows W2 and W3, respectively, and each of them includes four storage areas for storing the four different peripheral length components. Referring to Figure 18(B), the window table preferably stores data indicating whether the picture image in each particular window is given by a black level or a white level. In other words, the output signal of the camera consists of two levels, a white level and a black level, and the pixels of either a black or a white level are used as a basis for defining the peripheral length. This data may be used to control a white and black reversion circuit which will be described hereinafter. Before describing the specific structure of the image processing system of the sixth embodiment, the overall operation during each field of data is summarized in the following. Figure 19 shows a vertical synchronization signal VD, a measurement period signal, a horizontal synchronization signal HD, and a window signal WD. The window signal WD is synchronized with the scanning in the camera, and is produced from a window memory after the delay of a single horizontal scanning to indicate the positions of the windows for each of the horizontal scanning lines. In the first horizontal scanning period or along the first horizontal scanning line, the peripheral lengths components of the picture image located on the first and second horizontal scanning lines are detected. According to the present embodiment, there is no window on the first horizontal scanning line y1. In other words, when the vertical counter is incremented to the value 1 by counting the horizontal synchronization signal (horizontal scanning line y2 which is one scanning line behind the current horizontal scanning line in the camera), since the storage area of the vertical address table defined by this address contains no data, no window is detected and the above mentioned computation is not carried out. In the second scanning period (horizontal scanning line y2), the vertical counter is incremented to the value 2. The storage area of the vertical address table addressed by this value stores address data WT1. Therefore, the storage area of the window table at the address WT1 is looked up and the addresses WA1 and WA2 are stored in that order. When the window signal rose to the high level for the first time, it can be known that its corresponds to the window W1 at the address WA1 from the above mentioned sequential pattern, and it can be also known from black and white level data not shown in the drawing that pixels of either the black or the white level are to be evaluated. Therefore, as long as the window signal for the window W1 remains at high level, the pixels of black level are computed. When the window signal has dropped to low level, the computed values are added up to the cumulative values of the peripheral length components at the address WA1. When the window signal has risen again to high level, it can be seen from the sequential pattern that it corresponds to the window W3. Likewise, as long as the window signal for the window W3 remains at high level, the pixels of black level are computed. When the window signal has dropped to low level, the computed values are added up to the cumulative values of the peripheral length components at the address WA3. This process is repeated for the third through the 242nd horizontal scanning lines, and the cumulative values of the peripheral length components are computed for each of the windows appearing along the horizontal scanning lines. When this process is carried out on the last or the 242nd horizontal scanning line, the cumulative values contained in their respective peripheral length storage areas amount to their final cumulative sums. The measurement period signal remain at high level throughout the time of measurement and computation, and drops to low level from the time of completion of the process related to the last scanning line and until the occurrence of a pulse in the vertical synchronization signal. During the period of low level of the measurement period signal, the peripheral length is computed from the number of the four peripheral length components according to the aforementioned formula. In this way, the peripheral length of the picture image included in each of a plurality of windows can be promptly computed on a real time basis for each field Figure 20 illustrates the hardware structure of the image processing system according to an embodiment of the present invention, and Figure 21 shows the mode of its operation in regards to the measurements on the parts of the windows W1 and W2 located on the third horizontal scanning line y3. In Figure, the period of low level between the two windows W1 and W2 is exaggerate for the convenience of illustration. In Figure 20, a TV camera 104 obtains a picture image signal which is then supplied to a synchronization signal separation circuit 101. The synchronization signal separation circuit 101 separates a horizontal synchronization signal HD and a vertical synchronization signal from the picture image signal and, additionally, generates clock pulses CK. The picture image signal is then converted into a binary signal by a binary discrimination circuit 102 according to a certain threshold level. The binary picture image signal is then supplied to a shift register 106 and a single horizontal scanning line delay circuit 105 via a black and white reversion circuit 103 and a gate circuit 124. The output from the single horizontal scanning line delay circuit 105 is supplied to another shift register 107 and another single horizontal scanning line delay circuit 104. The output from the single horizontal scanning line delay circuit 104 is supplied to yet another shift register 108. The shift registers 106 through 108 are synchronized by the clock pulses CK, and produce a three by three mask pattern (signals a through i). These signals a through i are supplied to the peripheral length detection circuit 109. The black and white reversion circuit 103 consists of an EX-OR circuit, and is controlled by a CPU 110 according to the above mentioned black and white level data. The peripheral detection circuit 109 is identical to the peripheral detection circuit 89 of the previous embodiment. output E1 is brought to high level when a horizontal component of the peripheral length is detected; output E2 is brought to high level when a vertical component of the peripheral length is detected, output E3 is brought to high level when a rightwardly rising component of the peripheral length is detected, and output E4 is brought to high level when a leftwardly rising component of the peripheral length is detected. These signals El through E4 are supplied to the enable terminals EN2 of counters 160 through 164. The counters 160 through 164 individually counts the associated peripheral length components. The enable terminals EN1 of the counters 160 through 164 receive the window signal WD. The clock inputs of the counters 160 through 164 receive the inverted closes signal, and their resets inputs receive timing signal T2. The window memory 120 is consists of an image memory, and has the capacity to store a set of binary data corresponding to an entire single frame. This memory is partitioned into a plurality of windows as illustrated in Figure 17. The bit of the window memory corresponding to each pixels may be addressed by an address signal supplied via a multiplexer 125. The multiplexer 125 selects either the addresses given by the CPU 110 or the addresses given by an address counter 126. When windows are defined in the window memory 120, their addresses as well as the data which is to be written into the data IO terminals of the memory 120 are given by the CPU 110. The window memory 120 is turned into a read mode during the measurement period, and the address counter 126 designates addresses thereof. The address counter 126 is cleared by the vertical synchronization signal VD,and is incremented by the clock pulses CK. When it is indicated by its count that the 242nd horizontal scanning is completed, a measurement completion signal TE is produced. This measurement completion signal TE is supplied to the CPU 110 via an IO control circuit 113. The CPU 110 receives the vertical synchronization signal VD in addition to the measurement completion signal TE, and generates a measurement period signal TM as shown in Figure 31, and produces it from the IO control circuit 113. When the window memory 120 is in the read mode as mentioned above, the obtained window data therefrom is converted into a serial signal by a P/S conversion circuit 121,a nd is then supplied to a gate circuit 122 as a window signal WD. The gate circuit 122 is controlled by the measurement period signal TM, and permits transmission of the window signal WD during the measurement period. This window signal WD is in synchronism with the image signal from the camera 104 with a delay of one horizontal scanning line. The window signal WD is high in the window regions, and is otherwise low. The window signal WD is supplied to the counters 160 through 163 as well as to the timing control circuit 123. The timing control circuit 123 generates various timing signals D0, T1 and T2, a read signal RD and a write signal WR according to the input signal, the window signal WD, the horizontal synchronization signal HD, and the measurement period signal TM. The timing signal TO rises to high level for a certain short time interval following the rise in the horizontal synchronization signal HD with a certain time delay (a few clock cycles), and controls a window counter 133. The timing signal T1 rises to high level for a certain short time interval following the rise in the window signal WD either with or without a certain time delay (a few clock cycles), and controls latch circuits 144 through 147. The timing signal T2 falls to low level for a certain short time interval (until the next window is encountered) following the rise of either of the timing signals T0 or T1, and serves as a clear signal for the counters 160 through 163. The read signal RD is kept in low level for a certain time interval following the fall in the timing signal T1, and sets a third high speed memory 132 to a read mode while its level is high. The write signal WR remains at low level for a certain time interval (which is sufficient to write data into the memory) while the read signal RD is at low level, and sets the third high speed memory 132 to a write mode on the one hand and enables the gate circuits 150 through 153 while its level is low. A first high speed memory 130 stores the vertical address table, a second high speed memory 131 stores the window table, and the third high speed memory 132 stores the peripheral length storage areas. The CPU 110 carries out the address designation for the high speed memories 130, 131 and 132 as well as the writing of the address data (such as WT1 and WT2) into the vertical address table before the start of a measurement process, the writing of the sequential pattern consisting of the address data (such as WA1 and WA2) into the window table, the clearing of the cumulative values of the peripheral length components into the peripheral length component storage areas, and the reading of the final cumulative sums of the peripheral length components upon completion of the measurement process. During each measurement process, the high-speed memories 130 and 131 are always in a read mode. The vertical counter 134 is cleared by the vertical synchronization signal at the beginning of each measurement period, and thereafter counts pulses of the horizontal synchronization signal HD and produces an address signal YCT which is then supplied to the first high speed memory 130. The window counter 133 presets the address data (such as WT1 and WT2) read out from the first high speed memory 130 by the address signal YCT, and is thereafter incremented by each rising edge of the write signal WR. The high speed memory 131 produces storage area addresses (such was WA1 and WA3) according to the address designation (such as WT1 and WT1+1 by the output of the window counter 133. The high speed memory 132 carries out the read and write of the cumulative data of the peripheral length components according to the address designation by the output from the high speed memory 131. Adders 140 through 143 add up the counts of the counters 160 through 163 to the cumulative values read out from the third high speed memory 132, and the results of the additions are given to latch circuits 150 through 153 before they are routed back to the peripheral length storage areas of the third high speed memory 132. The CPU 110 comprises PROM 11 for storing its operation program, RAM 112 for storing the cumulative values of the peripheral length components and other data obtained during the course of the computation processes, and the aforementioned IO control circuit 113. The CPU 110 carries out the writing of window data into the window memory 120, the creation of the various tables in the high speed memories 130 and 131, the clearing of the cumulative values of the peripheral length components stored in the third high speed memory 132, and the reading of the final cumulative sums of the peripheral length components upon completion of the measurement process, to the end of obtaining the circumferential or peripheral length of the object included in each of the windows. Prior to the start of a new measurement cycle, window data is written into the window memory 120, and the vertical address table and the window table are created and the peripheral length storage areas are cleared in the high speed memories 130 through 132. When a new measurement cycle is started, the counting of the peripheral length components and the cumulative additions are carried out. This process can be describe as given following taking an example in the window W3 on the third yorizontal scanning line y3 as illustrated in Figure 19. Prior to the starting of the third horizontal scanning line, the count of the counter 134 is 2. And the cumulative sums of the peripheral length components are given by ΣH1i = H11, ΣV1i = V11, ΣR1i = R11, and ΣL1i = L11. The count of the vertical counter 34 is WA1+2 which is greater than the address designating the last window on the second horizontal scanning line. When the horizontal synchronization signal HD rises to high level, it is counted by the vertical counter, and its count is increased to 3. This value is given to the first high speed memory 130, and the data WT2 stored at address 3 of the vertical address table stored in the first high speed memory 130 is read out, and is preset on the window counter 138 when the timing signal T0 has dropped to low level. The count of the window counter 138 is now WT2. The output WT2 of the window counter 138 designates the associated address of the second high speed memory 131, and the third high speed memory 132 produces the data WA1 (area address) stored at the address WT2. Further, the third high speed memory 132 is accessed at the address WA1, and produces the cumulative peripheral length components data ZH1i = H11, ΣV1i = V11, ΣR1i - R11, and ΣL1i = L11. When the window signal WD has risen to high level, the counters 160 through 163 are enabled by their enable terminals EN2, and the counts of the peripheral length components E1 through E4 are counted. The counters 160 through 163 are cleared by the timing signal T2. In other words, only the peripheral length components in the window W1 are counted. The counts are given to the adders 144 through 147 for different peripheral length components, and are respectively added to the outputs ΣH1i, ΣV1i, ΣR1i, and ΣL1i from the third high speed memory 132. These results are latched onto latch circuits 144 through 147. Then, the read signal RD goes low level, the write signal risen to high level, the memory 132 is brought to its write mode, and the tri-state gates 150 through 153 are opened. The address WA1 is still assigned to the memory 132. Therefore, the results of addition latched onto the latch circuits 144 through 147 or ΣH1i + H12, ΣV1i + V12, ΣR1i + R12, and ΣL1i + L12 are stored in the peripheral length storage areas at WA1 to thereby carry out the process of addition for the window W1. The low level state of the timing signal T2 clears the counters 160 through 163, and each falling edge of the write signal WR increments the window counter by one, and sets it ready for the measurement process for the next window. The peripheral length components data obtained by carrying out such processes until the completion of the measurement period are sequentially read out of the memory 132 by the CPU 110, and the peripheral length data can be obtained carrying out the computation given in equation (27) for each of the windows. Thus, according to the present embodiment, since a plurality of images can be analyzed at high speed and without requiring a large memory or any other complex structures, a significant improvement in operation efficiency, reducing in manufacturing cost can be achieved.

Claims: An image processing system, comprising: camera means (1, 11, 71, 81) for taking a picture of an image of an object and producing a corresponding picture image signal, a binary discrimation means (4, 13, 64, 83, 102) for converting said picture image signal into a binary signal, feature extracting means (86-89, 106-109), characterized by said feature extracting means (86 - 89, 106 - 109) being arranged for extracting a geometric feature of said picture image by processing said binary signal to detect edge components of said picture image and the respective edge directions of said edge components, and processing means (99, 110) for determining the edge length from said directtional edge components. An image processing system according to claim 1, said processing means (110) comprising means for adding up the number of said directional edge components to obtain the peripheral length of the picture image. An image processing system according to claim 1 or 2, comprising first storage means (120), for defining a plurality of windows in a single frame, window generating means for reading out the windows in synchronism with a scanning operation of picture taking means and generating a window signal indicating the location and the size of each of said windows, second storage means for storing a sequential pattern of appearance of said windows on each of horizontal scanning lines, and third storage means for storing data for designating the sequential pattern of appearance of said windows for each horizontal scanning of said picture taking means on each of horizontal scanning lines, and a fourth storage means for storing data for obtaining a geometric feature of said picture image for each of said windows; said feature extracting means (106 - 109) comprising means for extracting representative pixels which are required for determination of said geometric feature of a picture image included in each of said windows along each horizontal scanning line, and means for allocating pixels detected on each horizontal scanning line to memory areas designated for different ones of said windows to allow extraction of a geometric feature of image signals for each of said windows.

Inventors: ISHIHARA HIDESHI, KURIOKA HIDENORI, NAITOH HITOSI, NAKAMOTO HIROSHI, YONEDA SATOSHI, ISHIHARA, HIDESHI, KURIOKA, HIDENORI, NAITOH, HITOSI, NAKAMOTO, HIROSHI, YONEDA, SATOSHI, ISHIHARA, HIDESHI,C/O INTELLECTUAL PROPERTY CENTER, KURIOKA, HIDENORI,C/O INTELLECTUAL PROPERTY CENTER, NAITOH, HITOSI,C/O INTELLECTUAL PROPERTY CENTER, NAKAMOTO, HIROSHI,C/O INTELLECTUAL PROPERTY CENTER, YONEDA, SATOSHI,C/O INTELLECTUAL PROPERTY CENTER
Applicants: OMRON TATEISI ELECTRONICS CO, OMRON CORPORATION
Application year: 1990
Main classification: G06T7
IPC codes: G06T5, G06T7, G06K9