Digital-signal processing apparatus

Abstract: A digital signal processing apparatus includes two or more address registers (8a, 8b; 11a, 11b; 14a, 14b) associated with at least one of an instruction memory (3), a data memory (4), or a coefficient memory (5) and two or more data registers (17a, 17b) associated with a computing block (6), and these two or more registers are duty cycled switched between different jobs being simultaneously processed by the computing block (6) to enable efficient processing on a single chip of jobs that can be processed with different processing speeds, such as jobs suited for high speed processing or low speed processing.

Description: This invention relates to a digital signal processing apparatus for processing digital signals, such as digital audio signals. Description of the Prior Art Recently, it has become customary to perform various digital signal processing operations, including numerical computations, such as computations for digital filters, fast Fourier transform (FFT) or correlative functions, for digital signals such as digitized audio or video signals, on a real-time basis, and a variety of digital signal processing apparatus, known as DSP, have been evolved to perform such real time operations. In general, a DSP includes a computing block to perform arithmetic operations, such as multiplication or addition, an instruction RAM for writing a microprogram stating the signal processing sequence, a data RAM for transient data storage, and a coefficient RAM for storing coefficients employed in the arithmetic operation in the computing block. Thus, under the control of the microprogram, written in the instruction RAM, data are read out from the data RAM and the coefficient RAM, and an arithmetic operation is performed by the computing block for processing digital signals. However, since a conventional DSP is mainly designed for high-speed signal processing, it is customary to perform a single job on the DSP. When plural jobs are executed in parallel, especially at different speeds, the program contents become complicated in order to realize such parallel processing in one program on a one-chip DSP, otherwise wasteful execute cycles may be generated at the transition point from one job to another. On the other hand, when plural jobs are executed using plural DSPs, data exchange between the DSPs becomes complicated. When the DSPs are connected in series objectionable time delays may be produced. Moreover, the use of plural DSPs results in an increased mounting space and elevated costs. Document D1 = US-A-4 197 579 is considered to be the closest state of the art document. Document D1 discloses computing means with the possibility of time divisional parallel executing two different jobs. Therefore the program memory is divided in two sections 18, 26 and a program address register is divided in a first section 11 and a second section 12. As described in column 3, line 7, each processing cycle is divided in two half-cycles. Address registers 11 and 12 are loaded alternately. As described in column 3, starting in line 46 with reference to fig. 2 of document D1, instruction selection and data processing are alternately executed for program P 0 and P 1 in the sense that when the next instruction is selected for program P 1 the data of program P 0 are processed and when the next instruction is selected for program P 0 the data of program P 1 are processed. This is achieved by providing a pair of program memories 18, 26 and a pair of program address registers 11, 12. As can be seen from fig. 2 and as is clearly outlined in column 3, lines 46 to 49, each program makes use of a half-cycle for data processing and instruction selection as well. This means that each of the programs P 0 and P 1 have the same processing time available and that it is not possible with the apparatus disclosed in document D1 to use two or more joint half-cycles for a single program P 0 or P 1 . This is the case because the next instruction select logic 16 immediately selects the next instruction of the respective other program and this respective other program has to be executed in the next half period. Thus, the apparatus disclosed in document D1 is quite unflexibel when different programs which need different programming times or which have different priorities are to be executed. In this case the program which needs less computing time will be executed first and the possibility of parallel processing becomes ineffective when the first program is finished. Furthermore, the apparatus of document D1 cannot handle different programs with different priorities as each program is executed with the same processing time (a half-cycle each) and thus the computing priorities of programs P 1 and P 0 are 1 : 1. OBJECTS AND SUMMARY OF THE INVENTION It is a principal object of the present invention to provide a digital signal processing apparatus whereby plural jobs can be executed on one chip. According to the present invention as set forth in the appended claim, there is provided a digital signal processing apparatus comprising at least an instruction memory, a data memory and a computing block, wherein two or more address registers are associated with at least one of the instruction memory or the data memory and two or more data registers are associated with the computing block and wherein the two or more address registers or data registers are duty cycle switched between one or more instruction cycles during multiple job processing to allow multiple jobs to be simultaneously processed. In the preferred embodiment of the present invention, there is also provided a cofficient memory, and two or more address registers are associated with the coefficient memory and the two or more address registers are also duty cycle switched in response to job switching. With the above described digital signal processing apparatus, two or more address registers are provided in association with at least one of the instruction memory, the data memory or a coefficient memory, if the apparatus is provided additionally with such coefficient memory, and two or more data registers are provided in association with the computing block, and these two or more registers are simultaneously switched by switching control means in response to job switching to enable efficient execution on one chip of plural jobs suited to processing at different processing speeds. In this manner, it becomes possible to avoid an increase in the required mounting space or costs otherwise caused when plural jobs are allotted to plural chips, as well as to avoid time delay otherwise caused when plural jobs are perfomed on plural DSPs connected in tandem. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing an embodiment of a digital signal processing apparatus according to the present invention. Fig. 2 shows an example of a multiple job program written in an instruction RAM of the apparatus shown in Fig. 1. DETAILED DESCRIPTION OF PREFERRED EMBODIMENT By referring to the drawings, an embodiment of a digital signal processing apparatus according to the present invention will be explained in detail. With the present illustrative embodiment, two address registers are associated with each of an instruction RAM 3, a data RAM 4 and a coefficient RAM 5, while two data registers are also associated with the computing block 6 to enable parallel execution of two different jobs. However, three or more registers can also be provided to enable parallel execution of three or more different jobs. Fig. 1 is a schematic block diagram showing an embodiment of a digital signal processing apparatus according to the presnet invention. The digital signal processing apparatus (DSP) is comprised of the instruction RAM 3, the data RAM 4, the coefficient RAM 5 and the computing block 6. Address registers 8a, 8b ,an increment circuit 7, and a decoder 10 are connected to instruction RAM 3 and these address registers 8a, 8b are connected to fixed terminals a , b of a changeover switch 9, respectively. One of addresses from these address registers 8a, 8b is transmitted to the instructioin RAM 3 after switching by the changeover switch 9. Instruction data stored in the instruction RAM 3 are decoded by the decoder 10, and are supplied as various kind of control signals to, for example, an address generator 13 for the data RAM, an address generator 16 for the coefficient RAM, and the computing block 6. The output address from the changeover switch 9 is supplied to the increment circuit 7 which increment the input address by e. g. one and is supplied to the address registers 8a, 8b again. The increment circuit 7 and the address registers 8a, 8b thus make up a so-called program counter. Address registers 11a, 11b and the address generator 13 are connected to the data RAM 4 and the address registers 11a, 11b are connected to fixed terminals a , b of a changeover switch 12, respectivery. According to the instruction read out from the instruction RAM 3, the address generator 13 generates a new address for the data RAM 4 independently or based on the current address transmitted from one of the address registers 11a, 11b selected by the changeover switch 12 to the address generator 13, and the generated new address is transmitted to the data RAM 4 to effect data accessing. The new address for the data RAM 4 generated by the address generatgor 13 is transmitted to the address registers 11a, 11b, and is used as a reference address of the relative address to effect next data accessing of data RAM 4. Address registers 14a, 14b and the address generator 16 are connected to the coefficient RAM 5 and the address registers 14a, 14b are connected to fixed terminals a , b of a changeover switch 15, respectivery. According to the coefficient read out from the coefficient RAM 5, the address generator 16 generates a new address for the coefficient RAM 5 independently or based on the current address transmitted from one of the address registers 14a, 14b selected by the changeover switch 15 to the address generator 16, and the generated new address is transmitted to the coefficient RAM 5 to effect data accessing. The new address for the coefficient RAM 5 generated by the address generatgor 16 is transmitted to the address registers 14a, 14b, and is used as a reference address of the relative address to effect next data accessing of coefficient RAM 5. Data from the data RAM 4 and the coefficient RAM 5 are supplied to a computing block 6 by way of a data bus 19, and subjected to an arithmetic operation, such as addition or multiplication according to the instruction read out from instruction RAM 3 before being transmitted to data registers 17a, 17b. The outputs from the data registers 17a, 17b are selected by a changeover switch 18 so as to be transmitted back to the computing block 6 or to the data bus 19. The changeover switches 9, 12, 15 and 18 are controlled simultaneously by a changeover control circuit 2 as will later be explained in further detail. The so-called microprogram, written in the instruction RAM 3, is classed into different jobs Ja, Jb, as shown in Figs. 2, wherein the instruction codes for these jobs Ja and Jb are written in the instruction memory 3 in a memory area bearing memory addresses n, n+1, n+2, ... and a memory area bearing memory addresses m, m+1, m+2, ... , respectively. With the above described digital signal processing apparatus or DSP, the changeover circuit 2 operates in response to instruction cycle clocks for transmitting to the changeover switches 9, 12, 15 and 18 changeover control signals which will switch two of three instruction cycle periods to the job Ja and the remaining instruction cycle to the job Jb so that the movable contacts of the changeover switches are biased to the fixed contact a during two sequential instruction cycles and to the fixed contact b during the following instruction cycle. It will be understood that although changeover switches 9, 12, 15, and 18 are represented in a mechanical form in the figure, they are actually high speed electronic switches. At this time, the program having the job Ja and the job Jb written in the instruction RAM 3 as shown in Fig. 2 is operated with the three instruction periods as shown in Table 1, so that the two sequential instruction cycles are allotted to the job Ja and the remaining instruction cycle is allotted to the job Jb, as shown in Table 1, to enable parallel separate execution of jobs with different processing speeds. processing sequence memory addresses jobs 1 n Ja 2 n + 1 Ja 3 m Jb 4 n + 2 Ja 5 n + 3 Ja 6 m + 1 Jb 7 n + 4 Ja . . . . . . . . . That is, when the address changeover switch 9, associated with the instruction RAM 3, is switched to the side of the fixed contact a during two of the three instruction cycles, the instruction codes of the job Ja written in the memory addresses n, n+1, n+2, ... of the instruction RAM 3, are sequentially read. On the other hand, when the switch 9 is switched to the side of the movable contact b during the remaining one instruction cycle, the instruction codes for the job Jb written in the memory addresses m, m+1, m+2, ... of the instruction RAM 3 are read out sequentially. The above described operational sequence is repeated at every three instruction cycles so that the jobs Ja and Jb are executed in parallel time-divisionally. The processing speed for the job Ja is twice that for the job Jb so that plural jobs with different processing speeds can be executed efficiently. When it is desired to execute the jobs Ja and Jb with different coefficients or data, it suffices to provide each two address registers 11a, 11b, 14a and 14b or data registers 17a, 17b, as shown in Fig. 1, these being switched by the changeover switches 12, 15 or in 18 response to job switching. Although the DSP having the coefficient RAM 5 has been explained in the above embodiment, the present invention can also be applied to the DSP in which coefficient data are included in the operand portions of the instruction codes and hence the coefficient RAM is not in use. Two or more address registers or data registers can be provided for one of the instruction RAM 3, the data RAM 4 or the coefficient RAM 5, or the computing block 6, while only one register can be provided for the remaining RAMs or the computing block. The number of the jobs processed in parallel, the job switching periods or the number of cycles allotted to the jobs can also the selected freely. The instruction RAM 3, the data RAM 4 or the coefficient RAM 5 can be replaced by corresponding ROMs or other memories.

Claims: A digital signal processing apparatus for simultaneously processing two or more jobs and comprising at least an instruction memory (3), a data memory (4) and a computing block (6), operatively connected to each other and wherein two or more registers (8a, 8b) are associated with the instruction memory (3), and switching means (9) are provided for cyclically switching between the two or more registers (8a, 8b) to connect them to the instruction memory (3) depending upon which job is being processed in part at that instant, characterized by two or more registers (11a, 11b; 17a, 17b) associated with at least one of the data memory (4) or the computing block (6), and switching means (12, 18) for cyclically switching between the two or more registers (11a, 11b; 17a, 17b) to connect them to the associated one of the data memory (4) or the computing block (6) depending upon which job is being processed in part at that instant and switching control means (2) operating according to instruction cycle clocks for synchronously controlling all switching means (9, 12, 18) so that the switching means (9, 12, 18) cyclically operate to connect a first group (8a, 11a, 17a) of said registers (8a, 8b; 11a, 11b; 17a, 17b) for a first number of instruction cycles to the instruction memory (3), the data memory (4) and the computing block (6), respectively, and to connect a second group (8b, 11b, 17b) of said registers (8a, 8b; 11a, 11b ; 17a, 17b) for a second number of instruction cycles to the instruction memory (3), the data memory (4) and the computing block (6), respectively, whereby the second number of instruction cycles is a fixed multiple of the first number of instruction cycles. The digital signal processing apparatus according to claim 2 characterized by a coefficient memory (5), whereby the two or more registers include address registers (14a, 14b) which are associated with the coefficient memory (5). The digital signal processing apparatus according to any one of claims 1 or 2 chacterized in that the computing block (6) operates according to the instruction cycles and the switching means (9, 12, 15, 18) comprises a plurality of separate switches for sequentially and simulaneously switching the outputs of the registers (8a, 8b; 11a, 11b; 14a, 14b; 17a, 17b) in correspondence with one or more of the instruction cycles to thereby allocate the registers (8a, 8b; 11a, 11b; 14a, 14b; 17a, 17b) to the processing of each job during one or more instruction cycle periods.

Inventors: NAKAGAWA TARO, SAKAMOTO AKIRA, NAKAGAWA, TARO, SAKAMOTO, AKIRA, NAKAGAWA, TARO, C/O SONY CORPORATION, SAKAMOTO, AKIRA, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1990
Main classification: G06F9
IPC codes: G06F7, G06F17, G06F9