Table cloth matrix of EPROM memory cells with an asymmetrical fin

Abstract: The table cloth matrix of EPROM memory cells (16) comprises a semiconductor substrate (1), parallel source lines (2) and drain lines (3), floating gate areas (6) interposed in a checkerboard pattern between the source lines (2) and the drain lines (3) and control gate lines (15), parallel to one another and perpendicular to the source lines (2) and to the drain lines (3). There are obtained in the semiconductor substrate (1) extensive oxide areas (4), with which the floating gates (6) are in contact by means of their asymmetrical lateral fin (7).

Description: The present invention relates to a table cloth matrix of EPROM memory cells with an asymmetrical fin. In the field of memories with EPROM cells one of the fundamental problems is the density of the cells; it is important to succeed in compacting the memory cells as much as possible the better to exploit the available space and to improve performance. For this reason research is oriented towards the study of new structures which overcome these problems. One of these new structures is the so-called "table cloth" matrix, wherein two groups of source lines and one group of drain lines parallel and alternated to one another are intersected perpendicularly by control gate lines parallel to one another, while floating gate areas are interposed between said source and drain lines beneath said control gate lines. This configuration is described in US-A-4792925 and allows the attainment of good levels of miniaturization and of cell density. One of the main defects of this structure is the low capacitive coupling between the control gate and the floating gate of each cell. In fact the coupling area between the gates is practically identical to that between the floating gate and the substrate so that the capacitive ratio is lower than that of standard EPROM cells, and the cell's writing characteristics are thus worsened. The memory is thus highly sensitive to the so-called "drain turn-on", a parasitic effect which can lead to soft-erasing effects in non-selected cells. An improvement on this structure is illustrated in EP-A-0352830. In this structure islands of field oxide are provided in the matrix zone, which, while allowing an improvement in the capacitive coupling between the gates, involve a greater complexity of manufacture and a lower degree of obtainable integration. In EP-A-0372614 a variant of the table cloth matrix structure is described. In this Application there are provided field oxide areas formed by the control gate lines, and the floating and control gates are provided with symmetrical lateral fins which are superimposed over the field oxide areas. In this structure the control gate is effectively coupled to the underlying layer only at narrow lateral fins, while in the central zone coupling is reduced by an oxide layer residue from a planarization stage included in the manufacturing process of the matrix. Thus the coupling area between the gates is extremely small, and this worsens coupling, if it does not altogether prevent it. US-A-4258466 discloses a structure according to the preamble of claim 1. The object of the present invention is to accomplish a matrix of EPROM memory cells of the table cloth type which offers an improved capacitive ratio without requiring particular manufacturing techniques, and which allows considerable compacting possibilities. According to the invention such object is attained with a matrix of EPROM memory cells as defined in claim 1. In this way each control gate is effectively coupled to the underlying floating gate area at the extensive surface of the latter's lateral fin. This improves electrical coupling between the two gates, increasing the capacitive ratio and thus the performance of the cell. The part of the control gate which is superimposed, with interposed planarization oxide, on the part of the floating gate close to the substrate is much reduced, and thus its effect is negligible. The characteristics and the advantages of the present invention shall be made more evident by the following detailed description of some possible embodiments illustrated as non-limiting examples in the following drawings wherein: Fig. 1 is a perspective cross-section of a portion of a checkerboard matrix according to the invention; Fig. 2 is a plan view from above of a portion of the checkerboard matrix of Fig. 1; Fig. 3 shows said portion of the checkerboard matrix in a cross-sectional view taken along the line III-III of Fig. 2; Fig.s 4, 5, 6 and 7 show enlarged details of the above table cloth matrix, along the lines IV-IV, V-V, VI-VI and VII-VII, respectively, of Fig.s 2 and 3; Fig. 8 shows a plan view from above of a portion of a further embodiment of the checkerboard matrix according to the invention. The memory matrix consists of a substrate 1 (Fig. 1) in which there are obtained parallel source lines 2 and drain lines 3 (Fig.s 1 and 2). An insulating system 5 is diffused in the substrate by means of a doping agent. As shall be made clearer later, this insulating system 5 is diffused only in the areas wherein there is an oxide in contact with said substrate 1 so as to avoid residual diffusion currents. Extensive areas of field oxide 4 are grown on substrate 1, interposed between the source lines 2 and the drain lines 3. Areas of floating gate 6 with underlying oxide layers 18 are arranged in a checkerboard pattern between said source lines 2 and drain lines 3. As shown in Fig.s 1 and 3, the areas of floating gate 6 have an asymmetrical fin 7 which is superimposed on the field oxide 4. Areas of dielectric 8 and areas of barrier polysilicon 9 are arranged on the areas of floating gate 7. Both the areas of dielectric 8 and the areas of polysilicon 9 have a fin, 10 and 11 respectively, which is superimposed and aligned over the corresponding fin 7 of the underlying floating gate 6. Areas of planarized oxide 12 are deposited between each group formed by floating gate 6, areas of dielectric 8 and of polysilicon 9. These oxide areas constitute the residue of the thick planarization oxide after its removal until the upper surface 13 of the oxide itself coincides with the upper surface 14 of fin 11 of polysilicon 9. Lastly control gate lines 15, say of polysilicon, are arranged perpendicularly to the source lines 2 and to the drain lines 3, in a condition superimposed and self-aligned with each group formed by floating gate 6, by dielectric area 8 and polysilicon area 9. There is thus obtained in this way a matrix of EPROM memory cells, such as that indicated with 16 in Fig.s 2, 3 and 6. As already mentioned, the insulation system 5 exists only in the areas of contact between field oxide 4 or planarized oxide 12 and substrate 1. The checkerboard matrix according to the invention is also applicable to the memory matrix structure illustrated in EP-A-0352830, as shown in Fig. 8. In this structure two drain lines 3 are alternated with each source line 2 and strips of oxide 17 are also present, parallel to the source lines and to the drain lines, which divide the matrix of memory cells into a plurality of groups of cells insulated from one another. In this way a checkerboard memory matrix is obtained, whose individual cells are accessible by traditional decoding.

Claims: Matrix of EPROM memory cells, comprising a semiconductor substrate (1), source lines (2) and drain lines (3) parallel and alternated to one another on said substrate (1), floating gate areas (6) interposed in a table cloth pattern between said source lines (2) and drain lines (3), control gate lines (15) parallel to one another and perpendicular to said source lines (2) and drain lines (3) in a condition superimposed over an intermediate dielectric (8) and aligned with respect to said floating gate areas (6), and extensive areas of field oxide (4) formed on said substrate (1), wherein areas of dielectric (8) and areas of polysilicon (9) connected to the control gate lines (15) are superimposed over and self-aligned with said floating gate areas (6), said areas of dielectric (8) and polysilicon (9) being provided with respective fins (10, 11) superimposed over the corresponding fins (7) of the underlying floating gate areas (6), characterized in that each of said floating gate areas (6) is provided with a single lateral fin (7) and in that the single lateral fins (7) of pairs of adjacent floating gate areas (6) which are interposed between the same source (2) and drain (3) lines are superimposed with an extensive coupling surface over opposite ends of corresponding ones of said field oxide areas (4) so that substantially all of said field oxide areas (4) have corresponding pairs of floating gate areas (6). Cell matrix (16) according to claim 1, characterized in that each source line (2) is alternated with a pair of drain lines (3) and that oxide strips (17) are interposed between said drain lines (3).

Inventors: MAZZALI STEFANO, MAZZALI, STEFANO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1990
Main classification: G11C16
IPC codes: H01L29, H01L21, H01L27, G11C16