Test mode switching system for LSI

Abstract: A said test mode switching system comprises a register (1) for storing test signal data and for outputting the test signal data to a self testing circuit (3) for checking whether or not the LSI (7) ope­ rates correctly, a memory (4) for storing a test inhibiting signal (CD) and a test allowing signal (Rs) received from a CPU through the control signal terminal (9) of the LSI (7); and means (5) for enabling the register (1) to output test signals depending on the condition of the output of the memory (4) whereby the LSI (7) can operate either under the normal operation mode or under the test mode.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a test mode switching system of a large scale integration circuit or LSI to be connected to a central processing unit or CPU, which is incorporated in the LSI to check whether or not the LSI can operate normally before flowing from the factory. Description of the Prior Art In the prior arts, LSI can be switched to a test mode through an external terminal of the LSI serving as a test mode switching pin of LSI as mentioned below. A LSI of this type is known from Patent Abstracts of Japan, JP-A-59160 778 vol. 9, no. 13, (P-328) (1736) January 19, 1985 (Nippon D.K.K.). If the test mode pin is '1' condition which represents the test mode, the test signal data register incorporated in the LSI operates, storing test signal data inputted from the CPU through the data input pin of LSI, whereby the register outputs it to each testing circuit in the LSI to set each testing circuit to the testing condition for checking whether or not the LSI can operate correctly. Each testing circuit is controlled by the CPU through each pin of the LSI, a control bus, and the address bus, and transmits the data resulted from the test to the CPU through the data bus, so that the CPU can judge the functions of the LSI based on the data. Before LSIs are shipped from the factory, '0' the test mode switching pin of each LSI which has passed the above mentioned device test is made '0' which represents the normal operation mode, whereby the test signal data register is disabled, so that the LSI can work in the normal operation mode under the control of CPU. The conventional LSIs of the above type necessitate an external pin serving as a test mode switching pin, to enable the LSIs in the test mode. LSIs are, however, limited in the number of external pins. Sometimes it is not allowed to provide even only one test mode switching pin. In the conventional LSI test mode switching device, there must be used a relatively large size package of LSI provide the test mode switching pin. The conventional LSI test mode switching device prevents to decrease the package size. SUMMARY OF THE INVENTION An essential object of the present invention is, therefore, to provide a test mode switching system for LSIs in which the test mode can be enabled without any specific test mode switching pin, whereby the number of the external pin of LSI can be reduced, resulting in reducing the LSI size. To accomplish the above mentioned object, in the present invention, a test mode switching system for a LSI comprises the features of appended claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for showing one example of configuration of the substantial portion of a LSI employing the test mode switching system of the present invention; Fig. 2 is a timing chart for illustrating the test mode of the LSI; and Fig. 3 is a timing chart for illustrating the normal operation mode of the LSI. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Hereinafter, the present invention will be described more in detail, taken in conjunction with embodiments shown in the accompanying drawings. Fig. 1 is a schematic diagram for showing a configuration of the substantial portion of LSI which employs the test mode switching system of the present invention. Referring to Fig. 1, a numeral 1 is a register which stores test signal data Di of 8-bit inputted from a CPU (not shown) through the data input terminal 2 of LSI 7, in synchronization with the rise of a signal inputted to a clock terminal CK. The register 1 outputs the test signal data Do of 8-bit to a self-testing circuit 3 for checking the functions of LSI 7, thereby switching the LSI 7 to the test mode operation; a numeral 4 is a D flip-flop which receives the falling of a reset signal RS at the reset terminal R, as a test allowing signal and outputs '1' signal Qo, from the output terminal Q by a '1' signal applied at an input terminal D, in synchronization with the rise of the test inhibiting signal CD inputted to the clock terminal CK. The output signal Qo from the D flip-flop 4 is applied, to the clock terminal CK of the register 1 through an OR gate 5 as a selection signal for enabling the register 1. The OR gate 5 also receives a selection signal CS inputted from the CPU through an address signal terminal 6 of LSI for enabling the register 1 when the signal CS rises. The above mentioned elements 1, 3, 4, and 5 are all incorporated in the LSI 7, and the reset signal RS and the test inhibiting signal CD are inputted from the CPU to the LSI 7 through respective control signal terminals 8 and 9, and the reset signal RS is also fed to the reset terminal R of the register 1. It is noted that the LSI 7 shown in Fig. 1 is not provided with any test mode switching terminal in the form of an external connection pin which the conventional LSI has. Since input terminal D of the D flip-flop 4 is normally maintained in '1' condition, and outputs '1' output signal Qo to the output terminal Q with the rise of the test inhibiting signal CD inputted to the clock terminal CK. The input terminal D continues to output '1' normally without changing into '0' even if the test inhibiting signal CD rises again and again, as long as the reset signal RS is not inputted to the reset terminal R. In addition, the OR gate 5 outputs '1' output signal to the clock terminal CK of the register 1 irrespective of condition of the selection signal CS, if the output signal Qo from the D flip-flop 4 becomes '1', while the OR gate 5 outputs the selection signal CS to the clock terminal CK of register 1, if the output signal Qo is '0'. Accordingly, when the output signal Qo is '1', the test signal data Di from the data input terminal 2 is not written to the register 1, which therefore does not output the test signal data Do, so that the self-testing circuit 3 does not operate, and that the LSI 7 does not operate under the test mode. When the output signal Qo is '0', the test signal data Di is written in the register 1 in synchronization with the rise of the selection signal CS, and simultaneously outputs the test signal data Do to operate the self-testing circuit 3, so that the LSI 7 can operate under the test mode. Referring to Figs. 2 and 3, the test mode switching system of the LSI 7 is described. The switching to the test mode is performed in such a manner as shown in Fig. 2. When a reset signal RS as shown in Fig. 2 (a) is inputted to the LSI 7 from the CPU through the control signal terminal 8, the D flip-flop 4 and the register 1 are reset through the respective reset terminals R , so that the output signal Qo and the test signal data Do become '0' respectively, as shown in Figs. 2 (b) and 2 (c). Next, when the selection signal CS as shown in Fig. 2 (e) is applied to the LSI 7 from CPU through the address signal terminal 6, so that the OR gate 5 outputs a signal corresponding to the logical sum of the selection signal CS and the '0' signal Qo, namely, the selection signal CS is applied to the clock terminal CK of the register 1. The register 1, then, stores the test signal data Di (Di=D1) inputted from the CPU through the data input terminal 2 with the rise of the selection signal CS as shown in Fig. 2 (d), and simultaneously outputs the data D1 as test signal data Do (Do=D1) to the self-testing circuit 3 as shown in Fig. 2 (c). When the next selection signal CS is inputted as shown in Fig. 2 (e), the register 1 stores the next test signal data Di (Di=D2) in the same manner as mentioned above with synchronization with the rise of the selection signal CS, and simultaneously outputs it as test signal data Do (Do=D2) to the self-testing circuit 3 as shown in Fig. 2 (c). Thus, the self-testing circuit 3 is switched to the test mode operation, and set to the predetermined testing conditions by the test signal data Do (Do=D1, D2), thereby checking whether or not each part of LSI 7 operates normally. One example of the test mode is shown where a 10-bit counter in the LSI 7 is tested. In one preferred example of test of the 10-bit counter the test is conducted as the 10-bit counter is composed by two 5-bit counters, the testing circuit 3 can rapidly complete the test of the counters by 2⁵ clock pulses, while according to a conventional test, 10-bit counter requires 2¹⁰ clock pulses to complete the test. Thus, until the test inhibiting signal CD is inputted to the clock terminal CK of the D flip-flop 4, the LSI 7 is controlled under the test mode by the CPU in accordance with the timing chart as shown in Fig. 2 and the CPU judges the operation of LSI 7 based on the data resulted from the test which is transmitted by the LSI 7 through the data bus. The switching process to the normal operation mode is performed according to the timing chart as shown in Fig. 3. A reset signal RS as shown in Fig. 3(a) is inputted to the reset terminal R, thereby resetting the D flip-flop 4 and the register 1, so that the output signal Qo and the test signal data Do enter '0' conditions as shown in Figs. 3 (b) and 3 (d). Next, when the CPU inputs a test inhibiting signal CD as shown in Fig. 3(c) to the LSI 7 through the control signal terminal 9, the D flip-flop 4 outputs '1' signal present at the input terminal D, as an output signal Qo, to the output terminal Q in synchronization with the rise of the test inhibiting signal CD as shown in Fig. 3(b). The '1' output signal Qo is not changed into '0' signal even if the test inhibiting signal CD rises repeatedly after that, because the input terminal D of the D flip-flop 4 maintains '1' condition. The output signal Qo does not enter in '0' condition until the reset signal RS is inputted to the reset terminal R of the D flip-flop 4. Since '1' output signal Qo is inputted to one of the input terminals of the OR gate 5, the OR gate 5 outputs a '1' output signal to the clock terminal of the register 1 even if the CPU inputs a selection signal CS to the other input terminal of the OR gate 5 through the address signal terminal 6 as shown in Fig. 3(f). Accordingly, even if test signal data Di (Di=D1) as shown in Fig. 3(e) is inputted to the register 1 through the data input terminal 2 with the rise of the selection signal CS, it is not written to the register 1. Furthermore, the register 1 does not output the test signal data Do as shown in Fig. 3(d). For these reasons, the self-testing circuit 3 does not operate, and hence, the LSI 7 can operate under the normal operation mode. As described above, once the clock terminal CK of the register 1 is made '1' condition by the input of test inhibiting signal CD, the register 1 does not store the test signal data Di even if the CPU erroneously inputs the selection signal CS to the register 1 repeatedly to perform the test mode operation, so that the self-testing circuit 3 is kept in the nonoperative or disabled state, thereby assuring the normal operation mode of LSI 7. To sum up, in programming the CPU, by initially setting the test inhibiting signal CD to be outputted to the LSI 7, the LSI 7 is never changed erroneously from the normal operation mode to the test mode until the reset signal RS is outputted, even if the CPU performs an erroneous operation, and also, the systems of the CPU and the LSI 7 are not broken by the erroneous switching operation to the test mode. Since the LSI 7 is switched to the test mode operation by utilizing the address signal terminal 6 and control signal terminals 9 and 8 which are generally usually provided in LSI chips, and does not require a specific test mode switching terminal, it is an advantage that the LSI to be reduced in the size and hence compacted, because the LSI has limitation in the number of pins in terms of its size as mentioned before. It is needless to say that the present invention is not limited to this embodiment as described above and shown in the accompanying drawings, and the modifications and variations thereof are possible in light of the above teachings.

Claims: A test mode switching system for an LSI (7) comprising a data input terminal (2) for applying a plurality of data signals used in said LSI, control signal terminals (8,9) for receiving signals by which said LSI can be operated, an address signal input terminal (6) for applying address data to be used in said LSI; said test mode switching system comprising a register means (1) for storing test signal data inputted from a CPU through the data input terminal (2) of the LSI (7) and having an input terminal (CK) for enabling and disabling the storage of said test signal data in said register (1), and for outputting the test signal data to a self testing circuit (3) for checking whether or not the LSI (7) operates correctly; a memory means consisting of a D type flip flop (4) whose clock input is connected to said control signal terminal (9) a resetting input (R) connected to control signal input (8) and having an output (Q), for storing a test inhibiting signal (CD) and a test allowing signal (RS) received from the CPU through said control signal terminals (9) and (8) respectively; and enabling means constituted by an OR gate (5) one input of which is connected to said output (Q) of the D flip flop (4) and another input is connected to said address input terminal (6) with the output connected to said input terminal (CK) of said register means (1), for enabling said register means (1) to output test signals depending on the condition of the output of said memory means (4) and the signal applied to the address signal input terminal (6), whereby the LSI can operate either under the normal operation mode or under the test mode.

Inventors: HORIE NOBUYUKI, SAKAMOTO NORIAKI, YAMANAKA TOSHIHIRO, YAMANE DAIJI, HORIE, NOBUYUKI, SAKAMOTO, NORIAKI, YAMANAKA, TOSHIHIRO, YAMANE, DAIJI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1990
Main classification: G06F11
IPC codes: G06F11, G01R31