Microprocessor having internal cache memory

Abstract: A microprocessor is coupled to an external memory so as to receive therefrom an instruction or data for data processing and a parity bit associated to the instruction or data for data processing. The microprocessor internally comprises a data latch for receiving and holding the instruction or data from the external memory, a parity bit latch for receiving and holding the parity bit associated to the instruction or data, a cache memory for receiving and storing the received instruction or data held in the data latch. The cache memory includes a valid bit prepared for each of the received instruction or data in order to indicate validity of the stored instruction or data. The microprocessor also internally comprises a parity control circuit receiving the received instruction or data held in the data latch and the received parity bit held in the parity bit latch for checking validity of the received instruction or data. The parity control circuit operates to activate a valid bit of the cache memory corresponding to the received instruction or data when the result of the checking indicates that the received instruction or data is valid.

Description: Background of the Invention Field of the invention The present invention relates to a microprocessor, and more specifically to a control of the microprocessor including an internal cache memory after the microprocessor has received an instruction or data including redundant information from an external device and has transferred the received instruction or data to the internal cache memory. Description of related art In the prior art, no microprocessor including an internal cache memory has a redundant information circuit. Therefore, in a system requiring a reliability, a redundant information control circuit has be externally added to a microprocessor in order to ensure a high degree of reliability. Here, consider one typical conventional system having a microprocessor and an external circuit for treating a parity bit which is one kind of redundant information. For example, when the microprocessor reads an instruction or data from an external memory, the microprocessor outputs an address to the external memory and a parity bit memory provided externally to the microprocessor. In response to the given address, the external memory supplies instruction or data selected by the given address, to the microprocessor and also to a parity control circuit provided externally to the microprocessor, and the parity bit memory outputs a parity bit selected by the given address, to the parity control circuit. On the basis of the received instruction or data and the received parity bit, the parity control circuit discriminates whether or not the instruction or data supplied to the microprocessor is valid. The result of this discrimination is sent to the microprocessor, and if the result of the discrimination indicates that the instruction or data supplied to the microprocessor is valid, the instruction or data supplied to the microprocessor is actually utilized or stored in the microprocessor. In the above mentioned instruction or data transfer procedure, it is possible to discriminate whether or not the instruction or data supplied to the microprocessor is valid, only after the instruction or data is read out from the external memory and a syndrome has been calculated in the parity control circuit provided externally to the microprocessor. This means that an access time looked from a viewpoint of the microprocessor is a sum of an access time to the external memory and a syndrome calculation time. As a result, the system added with the parity bit becomes lower in performance than a system added with no parity bit, by an increased amount of the access time. In order to overcome this problem, it has been proposed to early send data and lately send a data valid indication signal so that an access time becomes equal to a memory access time. In this case, a means for notifying the validity of the data to the microprocessor is limited only to the type such as interrupt in which an notification is acknowledged at a gap between instructions. However, this is disadvantageous in that when an erroneous instruction or data has been sent, the microprocessor knows the error at a delayed timing. Therefore, when the microprocessor has become aware of the error, the microprocessor can do no other than to execute an instruction or data processing on the basis of the erroneous data, or to clear all the data and/or instructions including valid data already stored in the cache memory. This means a large drop of performance. Summary of the Invention Accordingly, it is an object of the present invention to provide a microprocessor internally having a cache memory and having a reduced access time to an external device having redundant information, without decrease of performance of the microprocessor. The above object of the present invention is achieved in accordance with the present invention by a microprocessor as claimed in Claim 1. The above object, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram of a system including the microprocessor in accordance with the present invention; Figure 2 is a block diagram of one embodiment of the microprocessor in accordance with the present invention; and Figure 3 is a timing chart illustrating an operation of the system shown in Figure 1 including the microprocessor shown in Figure 2. Description of the Preferred embodiments Referring to Figure 1, there is shown a block diagram of a system including the microprocessor in accordance with the present invention. The shown system includes a microprocessor 101 embodying the present invention, a memory 102 storing instructions or data, and a parity bit memory 103 storing parity bits, a data bus 110 coupled to the microprocessor 101 and the data memory 102 for transferring an instruction or data between the microprocessor 101 and the data memory 102, and an address bus 111 for supplying from the microprocessor 101 to the data memory 102 and the parity bit memory 103 an address designating a location of each of the data memory 102 and the parity bit memory 103. In addition, the system includes a parity bit bus 112 for transferring parity bit information between the microprocessor 101 and the parity bit memory 103, and a group of control signal lines 113 for supplying control signals including a read/write signal and a timing signal, from the microprocessor 101 to the data memory 102 and the parity bit memory 103. Referring to Figure 2, there is shown a block diagram of one embodiment of the microprocessor in accordance with the present invention. The microprocessor 101 includes an execution unit 210 for executing a data processing and for calculating an address of an operand and others, a cache memory 211 for storing instruction codes and a part of data, and a parity control circuit 212 for generating a parity bit for data on an internal data bus 231 and for executing a parity check for data on the internal data bus 231. The microprocessor 101 also includes a parity latch 213 coupled between the external parity bit bus 112 and an internal parity bit bus 232 for holding a parity bit, a data latch 214 coupled between the external data bus 110 and the internal data bus 231 for holding data, and an address latch 215 coupled between the external address bus 111 and an internal address bus 230 connected to the execution unit 210 for the purpose of holding an address outputted onto on the internal address bus 230 from the execution unit 210 so as to output the held address to the external address bus 111. The cache memory 211 includes an address decoder 220 coupled to the internal address bus 230 so as to select one item of data (or an instruction) stored in the cache memory, a data memory section 221 for storing a number items of data, and a valid bit section 222 for storing one item of information indicating whether or not an item of data stored in the data memory section 221 and selected by the address decoder 220 is valid. The cache memory 221 also includes a valid bit control circuit 223 for determining whether or not each bit of the valid bit section 222 should be validated. The above mentioned internal data bus 231 is connected so as to mutually couple the data latch 214, the cache memory 211 and the parity control circuit 212, and the internal parity bit bus 232 is connected so as to couple mutually the parity latch 213 and the parity control circuit 212. A parity calculation result signal line 233 is connected so as to supply to the valid bit control circuit 223 a signal indicative of the result of a parity calculation executed in the parity control circuit 212. A group of internal control signal lines 234 are connected to the execution unit 210, the cache memory 211, the parity control circuit 212 and the latches 213, 214 and 215 for transferring various control signals between the execution unit 210, the cache memory 211, the parity control circuit 212 and the latches 213, 214 and 215. In addition, an execution data bus 235 is coupled between the execution unit 210 and the cache memory 211. The execution unit 210 outputs various control signals through the external control signal lines 113. Now, an operation of the system shown in Figure 1 including the microprocessor shown in Figure 2 will be described with reference to Figures 1 and 2. When the execution unit 210 reads out an instruction, the execution unit 210 outputs an address to the internal address bus 230. At this time, the address on the internal address bus 230 is checked so as to ascertain whether or not an instruction corresponding to the given address exists within the cache memory 211. If the instruction corresponding to the given address exists within the cache memory 211, the address on the internal address bus 230 is decoded by the address decoder 220 so that one location is selected within the data memory section 221 and one valid bit is selected in the valid bit section 222. If the selected valid bit is active, this is informed to execution unit 210 through a line 237, and the data stored in the selected location of the data memory section 221 is read out and supplied to the execution unit 210 through the execution data bus 235. To the contrary, if the selected valid bit is inactive, reference is made to an instruction stored in the external memory 102. In the following, an operation performed when if the selected valid bit is inactive will be described. The address on the internal address bus 230 is latched in the address latch 215 and outputted onto the external address bus 111. At this time, the execution unit 210 outputs, through the external control signal lines 113, a signal indicative of a memory read and a signal indicative of a memory read timing. In response to these signals, the data memory 102 outputs an instruction or data selected by the given address, to the external data bus 110, and the parity bit memory outputs to the external parity bit bus 112 a parity bit selected by the given address and corresponding to the selected instruction or data. The microprocessor 101 controls to the effect that the instruction or data outputted to the external data bus 110 is latched in the data latch 214, and the parity bit outputted to the external parity bit bus 112 is latched in the parity bit latch 213. The data latched in the data latch 214 is supplied to the data memory section 221 and the parity control circuit 212. In the data memory section 221, the received data is held. On the other hand, the parity bit latched in the parity bit latch 213 is supplied through the internal parity bit bus 232 to the parity control circuit 212, where a syndrome is calculated on the basis of the received data and the received parity bit in order to discriminate whether or not the received data latched in the data latch 214 is correct. The result of this discrimination is sent through the parity result signal line 233 to the valid bit control circuit 223. When the received data latched in the data latch 214 is correct, the valid bit control circuit 223 activates a corresponding valid bit of the valid bit section 222 through a line 238. As a result, the data sent from the external memory 102 is stored in the cache memory as a valid data. On the other hand, if it is discriminated in the parity control circuit 212 that the data sent from the external memory 102 and latched in the data latch 214 is in error, the valid bit control circuit 223 does not activate a corresponding valid bit of the valid bit section 222. This is also notified to the execution unit 210 through the internal control signal lines 234, so that the execution unit 210 triggers a bus cycle, again, for the purpose of fetching the data, again, or executes a necessary processing such as stop of the instruction processing. The above mentioned operation is illustrated in Figure 3 in the form of a timing chart. As seen from Figure 3, the syndrome calculation is executed in parallel to the writing of the data or instruction to the cache memory. From a viewpoint of the microprocessor, the time for syndrome calculation apparently disappears, and therefore, the memory access in the system added with the parity bit can be realized with the access time realized in a system added with no parity bit. In other words, the performance of the system added with the parity bit can be improved. The above mentioned embodiment has been directed to an example in which one bit of parity information is added to data which is transferred through the data bus. However, it would be apparent to persons skilled in the art that it is possible to perform a similar control in the case that the data bus is divided into a plurality of data buses and a parity bit or a redundant control bit string other than the parity is added to each of the plurality of data buses. As seen from the above, when an erroneous data has been transferred or supplied because of noises or other causes in the way of transferring an instruction or data, or when a content of a memory has been broken by a soft error or other causes, the microprocessor in accordance with the present invention internally having a cache memory can avoid storing the erroneous data as a valid data. Therefore, the microprocessor is prevented from malfunctioning. In addition, when the erroneous data has been supplied, it is possible to invalidate only the erroneous data without clearing or invalidating a whole content of the cache memory. Therefore, it is possible to avoid drop of performance in the system.

Claims: A microprocessor to be coupled to an external means so as to receive therefrom an instruction or data for data processing and redundant information associated to the instruction or data for data processing, said microprocessor internally comprising data holding means for receiving said instruction or data for data processing from said external means and for holding the received instruction or data, redundant information holding means for receiving from said external means said redundant information associated to said instruction or data for data processing and for holding the received redundant information, a cache memory for receiving and storing the received instruction or data held in said data holding means, and checking means receiving the received instruction or data held in said data holding means and the received redundant information held in said redundant information holding means at substantially the same time that said cache memory receives the received instruction or data held in said data holding means, said checking means operating to check validity of the received instruction or data, in parallel with a writing of the received instruction or data into said cache memory. A microprocessor claimed in Claim 1 wherein said cache memory includes a valid bit prepared for each of the received instruction or data in order to indicate validity of the stored instruction or data, said checking means operating, when the result of the checking indicates that the received instruction or data is valid, to activate a valid bit of said cache memory corresponding to the received instruction or data which had been written into said cache memory when said checking means had been checking validity of the same received instruction or data. A microprocessor claimed in Claim 2 wherein said redundant information is a parity bit, and wherein said external means includes an data memory storing said instruction or data for data processing and coupled to said microprocessor through an external address bus and an external data bus, and a parity bit memory storing parity bits each associated to a corresponding one of instructions or data stored in said data memory, each of said parity bits being stored at the same address as that of the corresponding instruction or data stored in said data memory, said parity bit memory being coupled to said microprocessor through said external data bus and an external parity bit bus. A microprocessor claimed in Claim 3 wherein said data holding means includes a data latch coupled to said external data bus and also coupled through an internal data bus to said cache memory and said checking means, and said redundant information holding means includes a parity bit latch coupled to said external parity bit bus and also coupled through an internal parity bit bus to said checking means, and further including an execution unit coupled to an internal address bus and to said cache memory through an execution data bus, and an address latch coupled to said external address bus and also coupled through said internal address bus to said execution unit and said cache memory. A microprocessor claimed in Claim 4 wherein wherein said checking means includes a parity control circuit receiving the received instruction or data held in said data latch and the received parity bit held in said parity bit latch for calculating a syndrome on the basis of the received instruction or data and the received parity bit, said parity control circuit operating to output an active signal when the result of the calculated syndrome indicates that the received instruction or data is valid, and wherein said cache memory includes a valid bit control circuit responding to said active signal outputted from said parity control circuit so as to activate the valid bit of said cache memory corresponding to the received instruction or data.

Inventors: MAEMURA KOUJI, SATO YOSHIKUNI, MAEMURA, KOUJI,, SATO, YOSHIKUNI,, MAEMURA, KOUJI, C/O NEC IC MICROCOMPUTER SYSTEM, SATO, YOSHIKUNI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1990
Main classification: G06F12
IPC codes: G06F11, G06F12, G06F15