Zero standby power, radiation hardened, memory redundancy circuit

Abstract: A fused, redundancy selection circuit (20) is disclosed which is disabled by the absence of a chip select signal (CS). The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristics. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit (20) is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal (CS) is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off. In this manner, a zero standby power, radiation hardened memory redundancy circuit has been provided.

Description: The invention disclosed broadly relates to semiconductor memory circuits and more particularly relates to improvements in radiation hardened, redundant circuits for memories. On semiconductor memory chips, spare memory locations are included to replace nonfunctioning regular locations. Reprogrammable redundant word and bit lines are designed into the chip to replace bad word or bit lines. This programming can be done at the time of manufacturing testing by blowing fuses included in the circuit, to deselect a bad word or bad bit line and to replace it with one of the redundant lines. The typical prior art redundancy selection circuit is selectively enabled by blowing a fuse contained in the redundancy circuit. One problem with such prior art circuits is that whether or not the circuit has been enabled, it still dissipates power during ordinary operation of the memory chip. The additional contribution of power dissipation is a disadvantage for such prior art designs. Other prior art redundancy selection circuits which are selected by blowing a fuse, include the feature that the redundancy circuit, after having been enabled by blowing a fuse, will be effectively enabled or disabled by the chip select signal applied to the memory chip. This provides for eliminating power dissipation contributed by the redundancy circuit when the memory chip is not selected. However this prior art redundancy circuit still suffers from additional power dissipation when the chip select signal is on regardless of whether the fuses have been blown or not. Once again, the minimization of power dissipation is a sought-after advantage which has been difficult to achieve in the prior art where redundancy circuits are used on memory chips. Still further, when a static memory chip is exposed to a high radiation environment, significant problems occur in maintaining the binary states of the storage cells. Prior art redundancy circuits have failed to provide for enhanced radiation hardness, because they typically include nodes having a floating potential. A redundancy circuit is disclosed in EP-A-148 722 that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses. A circuit for providing an identification signal indicative of whether or not an semiconductor device has a repaired or replaced portion therein is disclosed in EP-A-195 412. The circuit is enabled by a control signal which is used for control the semiconductor device and causes a change in power supply current flowing into the semiconductor device according to presence or absence of the repaired or replaced portion. Both documents exhibit circuits for identifying a redundant portion in a semiconductor memory, comprising an enabling fuse connected in series with a FET transistor device. The invention as claimed is intended to remedy these drawbacks. It is therefore an object of the invention to provide an improved memory redundancy circuit. It is another object of the invention to provide an improved memory redundancy circuit which minimizes power dissipation. It is still a further object of the invention to provide an improved memory redundancy circuit which has enhanced radiation hardness characteristics. These and other objects, features and advantages of the invention are accomplished by the zero standby radiation hardened memory redundancy circuit disclosed herein. A fused, redundancy selection circuit is disclosed which is disabled by the absence of a chip select signal. The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristic. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off. In this manner, a zero standby power, radiation hardened memory redundancy circuit has been provided. These and other objects, features and advantages of the invention will be more fully appreciated with reference to the figures which illustrate only specific embodiments. Fig. 1 is an overall architectural diagram of a memory chip showing the relationship of the redundancy circuit to the balance of the memory chip circuitry. Fig. 2 is a circuit diagram of the redundancy circuit invention, where the enablement fuses have not been blown. Fig. 3 is another view of the circuit of Fig. 2, where the enablement fuses have been blown. Fig. 4 shows an alternate embodiment of the invention. Fig. 1 is an overall architectural block diagram of the relationship of the redundancy selection circuit to the balance of a static memory array. The static memory array 10 consists of rows and columns of static flip-flop memory cell devices which are addressed by means of an eight bit or 16 bit wide address, for example. The 16 bit address for this example, is applied to the address buffer 12 for staging purposes and the 16 bits are then applied to both the normal decoder 14 and the redundancy decoder 16. The chip select signal 18 is applied to both the redundancy selection circuit 20 and to the address buffer 12 and it serves to enable the memory chip. When the chip select signal on line 18 is in its enabling state, the address buffer 12 will gate any address bits applied to its input, to the normal decoder 14. The normal decoder 14 is normally enabled and will decode the address value applied to it by the address buffer 12 and will address the appropriate column and row of the array 10 to access the desired memory cell. At the time of manufacture of the memory chip, if testing determines that a column or a row of storage cells in the array 10 contains a defective cell, then at the time of manufacture, appropriate selection fuses are blown in the redundancy selection circuit 20 and appropriate decoding circuits are blown in the redundancy decoder 16 so that when the column or the row containing the defective cell is addressed, the redundancy decoder 16 will disable the normal decoder 14 and will enable the redundant spare column or row 22. In this manner, the use of the defective storage cell is avoided. The redundancy selection circuit 20 is shown in more detail in the circuit schematic diagram of Fig. 2. The circuit shown in Fig. 2 is a CMOS circuit having a first enabling fuse 1 and a second enabling fuse 2 connected as shown in Fig. 2. The circuit of Fig. 2 is connected between a positive potential VDD and ground potential GND. The circuit consists of a pullup resistor R which is connected between VDD and a first node A. The first enable fuse 1 is connected between the node A and the drain of the N channel FET device 5, whose source is connected to ground potential and whose gate is connected by line 18 to the chip select signal CS. The circuit further includes the second enabling fuse 2 which is connected between VDD and a second mode B. A second N channel FET device 4 has its drain connected to node B and its source connected to the drain of the N channel FET device 5. The gate of FET device 4 is connected to node A. The circuit of Fig. 2 further includes the P channel FET device 24 whose source is connected to VDD and whose drain is connected to the source of the P channel FET device 26. The P channel FET device 26 has its drain connected to a node C. An N channel FET device 6 has its drain connected to node C and its source connected to the drain of the N channel FET device 7. The N channel FET device 7 has its source connected to ground potential. The gate of the P channel FET device 24 is connected to the complement CS* of the chip select signal CS. The gate of the P channel FET device 26 and the gate of the N channel FET device 6 are connected in common to the node B. The gate of the N channel FET device 7 is connected to the true value of the chip select signal CS. The circuit of Fig. 2 further includes an N channel FET device 8 whose drain is connected at node C. The source of the N channel FET device 8 is connected to ground potential and the gate is connected to CS*, the complement of the chip select signal CS. The portion of the circuit consisting of devices 24, 26, 6, 7 and 8 functions as a multiplexer. Node C is connected to line 28 which is the enable output to the redundancy decoder 16. This constitutes the basic circuit invention. The circuit in Fig. 2 can optionally further include an output inverter circuit at node C. The circuit of Fig. 2 shows the enabling fuses 1 and 2 remaining intact. The operation of the circuit in Fig. 2 is as follows. If the two fuses are not blown, then enable output 28 remains low at all times for the following reasons. If CS is low (indicating that the chip is not selected), then CS* is high which turns N channel FET device 8 on thus forcing node C low, making enable 28 low. There is no DC power consumption (standby power) in the circuit since N device 5 is off and, therefore, no direct path occurs to ground. If CS is high (chip selected), then N channel FET device 5 turns on which pulls node A low. This occurs because the resistance of enable fuse 1 (on the order of 100 ohms) will be much smaller than the pullup resistance R (on the order of a few hundred kilohms) implying that there in only a small voltage drop across fuse 1, thereby making node A approximately ground potential. N channel FET device 4 is then off, isolating node B from ground, thus node B is held high via fuse 2 to VDD. Node C potential is low since N channel FET devices 6 and 7 are now on which makes enable 28 low again. The only DC power consumption (active) which occurs through the path through the pullup resistor R and enable fuse 1 to ground via N channel FET device 5. This power will be small since Power=((VDD)**2)/(RESISTANCE). For a pullup resistor R of 500 kilohms and VDD of 5 volts, this power will only be 50 microwatts. Therefore, the active power is negligible. Fig. 3 shows the circuit of Fig. 2 with the two fuses 1 and 2 blown. In such a state the appropriate decoding fuses in the redundancy decoder 16 will also be blown to indicate the particular column or row in the array 10 which is to be deleted so that the redundant column or row for redundant element 22 can be substituted. The circuit of Fig. 3 operates as follows. If the enabling fuses 1 and 2 are blown, then redundancy is selected and the circuit is as in Fig. 3. Note that node A will be high to potential VDD at all times via the pullup resistor R. This will cause the enable output 28 to be high when CS is high and to be low when CS is low. Thus the circuit of Fig. 3 does not dissipate power when the chip is not selected. The resulting circuit provides a fuse redundancy selection circuit which has superior radiation hardness characteristics and dissipates minimal power in all nonselected states. The radiation hardness is accomplished by avoiding floating nodes. Fig. 4 shows an alternate embodiment of the invention in which the multiplexer consisting of devices 24, 26, 6, 7 and 8 of Figs. 2 and 3 are replaced by devices 30, 31, 32, 33 and 34 of Fig. 4. Devices 30 and 31 of Fig. 4 represent a pass gate consisting of an N channel FET device 30 whose gate is connected to the chip select signal CS and the P channel FET device 31 whose gate is connected to the complement chip select signal CS*. Also included in Fig. 4 is a P channel FET device 32 whose gate is connected to the chip select signal CS and device 32 has its source-drain path connected between the node D and the positive potential VDD. P channel FET device 33 and N channel FET device 34 functions as an inverter circuit between node D and the enable output 28. In this manner, the multiplexer operation of devices 24, 26, 6, 7 and 8 in Figs. 2 and 3 is accomplished by the pass gate configuration of devices 30-34 of Fig. 4. The circuit of Figs. 2, 3 and 4 is designed to avoid floating potential nodes; that is the circuit does not rely on the storage of charge at any node. Thus, if any portion of the circuit encounters ionizing radiation, there will be no resulting inadvertent change of logic state. This radiation hardness feature combined with the low power dissipation characteristic of the circuit, makes the circuit ideal for use in space-borne applications.

Claims: A redundancy select circuit (20) for a memory, comprising: a first N channel FET device (5) having its drain connected to a first enabling fuse and its source connected to ground potential (GND) and its gate connected to a chip select signal (CS); said first enabling fuse connected between a first node (A) and the drain of said first N channel FET device (5); a pullup impedance device (R) connected between said first node (A) and a positive potential (VDD); a second N channel FET device (4) having its source connected to a second node (B), its drain connected to said drain of said first N channel FET device (5) and its gate connected to said first node (A); a second enabling fuse connected between said second node (B) and said positive potential (VDD); a multiplexer circuit having a data input connected to said second node (B), a control input (18) related with said data input and being connected to said chip select signal (CS) and having an output line (28) coupled for selectively substituting a redundant storage element (22) for a failing storage element in a memory array (10). The circuit of claim 1, wherein said multiplexer circuit includes a P channel FET device (24) whose source is connected to positive potential (VDD) and whose drain is connected to the source of a P channel FET device (26), said P channel FET device (26) having its drain connected to a node (C); an N channel FET device (6) whose drain is connected to said node (C) and its source connected to the drain of an N channel FET device (7), said N channel FET device (7) having its source connected to ground potential (GND); the gate of said P channel FET device (24) being connected to the complement (CS*) of the chip select signal (CS); the gate of said P channel FET device (26) and the gate of said N channel FET device (6) being connected in common to said second node (B); the gate of said N channel FET device (7) being connected to the true value of the chip select signal (CS); an N channel FET device (8) whose drain is connected at said node (C), the source of said N channel FET device (8) being connected to ground potential (GND) and the gate being connected to the complement of the chip select signal (CS*). The circuit of claim 1 wherein said multiplexer circuit includes a pass gate, consisting of an N channel FET device (30) whose gate is connected to the chip select signal (CS), and a P channel FET device (31) whose gate is connected to the complement chip select signal (CS*), the source of said N channel FET device (30) and the drain of said P channel FET device (31) being connected in common with said second node (B), the drain of said N channel FET device (30) and the source of said P channel FET device being connected in common with a node (D); a P channel FET device (32) whose gate is connected to the chip select signal (CS), the source of said P channel device (32) being connected to positive potential (VDD) and the drain of said P channel FET device (32) being connected to said node (D); an inverter circuit consisting of a P channel FET device (33) whose source is connected to positive potential (VDD), and an N channel FET device (34) whose source is connected to ground potential (GND), the gates of said P and N channel FET devices (33, 34) being connected in common to said node (D) and the drains of said P and N channel FET devices (33, 34) being connected in common to said output line (28). A redundancy circuit for selectively substituting a redundant storage element (22) for a failing storage element in a memory array (10), comprising: a redundancy select circuit (20) according to any one of the above claims whereby the output line (28) of the redundancy select circuit (20) is coupled to a redundancy decoder circuit (16) for enabling the redundant storage element (22) and disabling the failing storage element in the memory array (10). The circuit of claim 4, wherein said redundancy decoder circuit (16) has an output (DISABLE) connected to a normal decoder circuit (14) which addresses the normal working storage elements in the memory array (10).

Inventors: CIRAULA MICHAEL KEVIN, DURHAM CHRISTOPHER MCCALL, JALLICE DERWIN L, CIRAULA, MICHAEL KEVIN, DURHAM, CHRISTOPHER MCCALL, JALLICE, DERWIN L.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1990
Main classification: G06F11
IPC codes: G11C29, G11C17, G11C5