Information recording and reproducing device

Abstract: The device which records, erases and reproduces information on and from a memory device having pre-format sections, includes a pre-recorded area detection circuit for detecting a pre-recorded area having information predeterminately recorded and located on the memory device, and timing control circuits for providing timing control of an information recording, erasing or reproducing operation according to a pre-recorded area detecting signal released from the pre-recorded area detection circuit. Therefore, each timing of recording, reproducing, or erasing operation is accurately determined. Additionally, the timing control may be performed according to both of the pre-recorded area detecting signal of the present invention and the conventional synchronization detection signal. In that case, if an error should occur in the synchronization detection signals, since the pre-recorded area detecting signal is released every time pre-recorded information for a sector mark or the like is reproduced, an accurate timing control without time lag is achieved according to the pre-recorded area detecting signals.

Description: FIELD OF THE INVENTION The present invention relates to an information recording and reproducing device for recording and reproducing information on and from a memory device of various kinds such as a magneto-optical disk wherein pieces of information such as address information are predeterminately recorded, and more specifically to timing control of information recording and reproduction. BACKGROUND OF THE INVENTION On a magneto-optical disk, a thin magnetic film having vertical magnetic anisotoropy is usually used as a recording medium, and a laser beam which is gathered to a spot of substantial 1µm is applied thereto in order to perform recording, reproducing and erasing operations. More concretely, the recording and erasing operations are achieved by effecting magnetization reversal by an external magnetic field by utilizing the fact that coercive force becomes lowered because of a temperature rise in the spot where the laser beam is focused. On the other hand, the reproducing operation is achieved by utilizing the fact that a plane of polarization of the laser beam rotates by magneto-optical effect and by detecting a rotation of the polarizing plane by an analyzer. In the meantime, an arrangement is suggested wherein each track of the magneto-optical disk is divided into a plurality of sectors in the circumferential direction, and in the leading area of each sector, a pre-format part is disposed, wherein a sector mark, address information and other data are predeterminately formed in pits, while recording, reproducing and erasing operations of magneto-optical signals are performed in the other area of each sector as a recording area for magneto-optical signals by every sector unit. In that case, it is necessary to provide timing control so that recording, reproducing and erasing operations can be performed in the recording area for magneto-optical signals except the pre-format part. In Fig. 21, is shown a conventional information recording and reproducing device (e.g. as disclosed in Japanese unexamined patent publication No. 58169337) for performing recording and reproducing operations on and from a magneto-optical disk by the use of the above-mentioned method. A reproduced signal A is released from an information reproducing circuit 1, and the reproduced signal A is entered to a synchronization detection circuit 2. In the synchronization detection circuit 2, synchronization detection for each sector is performed from, for example, a signal of a sector mark which is a part of the reproduced signal A. A synchronization detection signal B released from the synchronization detection circuit 2 is entered to a timing control circuit 3, where timing control is provided according to the synchronization detection signal B, and consequently, a reproducing timing signal C is sent to the information reproducing circuit 1 during a reproducing operation, while a recording/erasing timing signal E is sent to an information recording/erasing circuit 4 during a recording or erasing operation. With the above arrangement, recording, reproducing and erasing operations are performed in the recording area for magneto-optical signals of each sector. Additionally, the synchronization detection by the synchronization detection circuit 2 is performed separately from the reproducing operation of information so as not to disturb the synchronization detection due to the reproducing timing signal C. However, in the device shown in Fig. 21, since the timing control is provided only by the use of the synchronization detection, there sometimes arise such cases wherein an error occurs in synchronization detection or time lag in detection occurs in the synchronization detection circuit 2, and consequently an accurate timing control cannot be executed. More specifically, errors in the timing control arise because reed gate signals of a PLL (Phase Locked Loop) included in the information reproducing circuit 1 become inaccurate, pulling-in operation cannot be performed, or the runout of the locked loop is apt to occur. Accordingly the conventional method has a problem in that reliability of recording, reproducing and erasing operations cannot be fully achieved. Further, when an error occurs in synchronization detection, timing control of AGC (Automatic Gain Control) is adversely affected. EP-A-0 189 187 discloses a magneto-optical disk memory system which has (a) means for detecting a header portion in which header information is prerecorded in a pit form, and (b) means for detecting a data portion. Switching means selects one of the outputs of the (a) and (b) means. The switching means is controlled in response to a timing based on a sector mark signal which is detected by the header portion detecting means. DE-A-3 809 223 discloses an information recording/ reproducing apparatus in which a clock signal is generated in accordance with a signal which is reproduced from prerecorded pits. Then, information is recorded in accordance with the clock signal in an area other than the pre-recorded area of pits, and the information is reproduced in accordance with the delayed clock signal. SUMMARY OF THE INVENTION It is an object of the present invention to provide timing control for accurate recording and reproducing operations without time lag if an error should occur in synchronization detection signals. In order to achieve the above object, the present invention provides an information recording and/or reproducing device for recording and/or reproducing information to and/or from a memory device having pre-recorded areas including a sector mark section, comprising: sector timing detection means for generating a sector timing detection signal upon detecting a sector mark section; and timing control means for controlling the timing of an information recording or reproducing operation according to said sector timing detection signal, characterised by pre-recorded area detection means for generating a prerecorded area detection signal upon detecting a said prerecorded area, in that said timing control means is arranged to output a timing signal for the control of the timing of the information recording or reproducing operation according to said pre-recorded area detection signal, and in that said timing control means comprises: (a) a counter circuit for generating a further timing signal in accordance with said pre-recorded area detection signal; and (b) a switching circuit, to which the sector timing detection signal and the further timing signal are inputted, for outputing said timing signal on the basis of the further timing signal when the sector timing detection signal has an error, while outputting the timing signal based on the sector timing detection signal when the sector timing detection signal has no error. Thus, if an error should occur in the generation of the sector timing detection signals, since the prerecorded area detecting signal from which the further timing signal is derived is released every time a prerecorded area including a sector mark is detected, an accurate timing control without time lag can then be achieved on the basis of the pre-recorded area detecting signal. For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 to 20 show one embodiment of the present invention. Fig. 1(a) to (d) are time charts showing a generating sequence of pre-recorded area detecting signals. Fig. 2 is a schematic plan view showing a magneto-optical disk. Fig. 3 is an enlarged partial view of Fig. 2. Fig. 4 is a block diagram showing an information recording and reproducing device. Fig. 5 is a block diagram showing an information reproducing circuit. Figs. 6 to 8 are explanatory diagrams respectively showing examples of a re-triggerable pulse generation circuit. Fig. 9 is a block diagram showing a detailed arrangement of an information reproducing circuit. Fig. 10 is a block diagram showing a detailed arrangement of a synchronization detection circuit. Fig. 11 is a block diagram showing a detailed arrangement of a sector mark detection circuit. Fig. 12(a) to (e) are explanatory diagrams showing the operation of a counter circuit. Fig. 13 is a time chart showing the progress of each signal in the synchronization detection circuit. Fig. 14 is a block diagram showing a detailed arrangement of a timing control circuit. Fig. 15 is a time chart showing the progress of each signal in the timing control circuit. Fig. 16 is a circuit diagram showing a detailed configuration of a switching circuit. Fig. 17 is a time chart showing the progress of each signal in the switching circuit. Figs. 18 to 20 show another embodiment of the present invention. Fig. 18 is a block diagram showing an information reproducing circuit. Figs. 19 and 20 are explanatory diagrams showing examples of a pre-recorded area detection circuit. Fig. 21 is a block diagram showing a conventional information recording and reproducing device. DESCRIPTION OF THE EMBODIMENTS The following description will discuss one embodiment of the present invention referring to Figs. 1 to 17. In Fig. 2, there is shown a magneto-optical disk 10 as an example of an optical memory device on/from which recording, reproducing or erasing operations are executed by an information recording and reproducing device according to the present invention. On the magneto-optical disk 10, there are provided tracks 11 in a spiral shape, or in a concentric shape, and each track 11 is divided into a plurality of sectors 12 in the circumferential direction. A pre-format section 13 is disposed in a leading area of each sector 12, and the remaining area thereof forms a magneto-optical signal section 14. As shown in Fig. 3, in the pre-format section 13, there are predeterminately recorded a plurality of marks 15 (shown in hatching for convenience) formed in pits and non-marks which are space sections between those marks 15, and in the magneto-optical signal section 14, there are recorded a plurality of marks 16 (shown in hatching for convenience) formed by magneto-optical signals and non-marks which are space sections between those marks 16. The marks 15 are predeterminately formed physically, and therefore are not erasable; however, the marks 16 are recordable as well as erasable. Additionally, either each mark 15, 16 or each non-mark located in between corresponds to a signal "1", and the remaining corresponds to a signal "0". Fig. 13 (a) shows a sector format which is a format of each sector 12. The pre-format section 13 includes a sector mark section 13a for synchronizing each of the sectors 12 and an ID section 13b having address information of the sectors 12. On the other hand, the magneto-optical signal section 14 includes a data section 14a for recording magneto-optical signals therein and gap sections 14b, 14c. Basically, data is recorded in the data section 14a by using marks 16 and non-marks given by magneto-optical signals. The gap sections 14b, 14c are margin sections for allowing a recording start position and a recording end position to be dislocated forward or backward by phase errors which occur when synchronizing each of the sectors 12 to the rotation of a spindle motor for rotating the magneto-optical disk 10. As shown in Fig. 4, the information recording and reproducing device of the present invention comprises an information reproducing circuit 17 (information reproducing means), and from the information reproducing circuit 17, reproducing signals including a sector mark signal F are sent to a sector timing detection circuit 18, as will be described later. Furthermore, from the information reproducing circuit 17, a pre-recorded area detecting signal G (which will be described in detail later) is sent to a timing control circuit 20 as a timing control means, while a synchronization detection signal H, which will be described in detail later, generated in the sector timing detection circuit 18 according to the sector mark signal F is also sent to the timing control circuit 20. According to those signals, from the timing control circuit 20, a reproduction timing signal I is released to the information reproducing circuit 17, and a recording/erasing timing signal J is also released to an information recording/erasing circuit 21. As shown in Fig. 5, the information reproducing circuit 17 comprises a pre-recorded area detection circuit 24 including a waveform shaping circuit 22 and a re-triggerable pulse generation circuit 23, and is designed to detect the pre-format sections 13 as a pre-recorded area having a sector mark and the like recorded therein. More specifically, a reproduced analog signal K (see Fig. 1(a)) reproduced from the pre-format section 13 of the magneto-optical disk 10 is entered to the waveform shaping circuit 22, where it is converted to a reproduced digital signal L (see Fig. 1(b)) as a binary coded digital signal of "High" or "Low". The reproduced digital signal L is entered to the pre-recorded area detection circuit 24. When a pulse exists in the reproduced digital signal L, the pre-recorded area detection circuit 24 turns the pre-recorded area detecting signal G (see (c) in Fig. 1) to "High" and keeps it for τ seconds. Since the pre-recorded area detection circuit 24 includes the re-triggerable pulse generation circuit 23, when the next pulse is entered within the τ seconds after the preceding pulse was entered in the reproduced digital signal L, the pre-recorded area detecting signal G is kept "High" for the succeeding τ seconds. One example of an arrangement of the re-triggerable pulse generation circuit 23 is shown in Fig. 6. Here, the re-triggerable pulse generation circuit 23 includes a re-triggerable monostable multivibrator 25. The period of time τ for keeping the pre-recorded area detecting signal G high is predeterminately set by a resistor R and a capacitor C. Concretely, τ is directly proportional to the product R·C. Fig. 7 shows another example of an arrangement of the re-triggerable pulse generation circuit 23 wherein a shift register 26 is employed. Serial input to an input terminal IN is given as "High", and clock pulses having a frequency f c are entered to a clock terminal CK, and then a N-th output of a shift output terminal QN is released as a pre-recorded area detecting signal G. Further, a reproduced digital signal L is entered to a clear terminal CL. In that case, the equation is expressed as: τ = N x (1 / f c ) Fig. 8 shows the other example of an arrangement of the re-triggerable pulse generation circuit 23 wherein a modulo-N divider 27 is employed. The reproduced digital signal L is entered to a clear terminal CL, and an output of an output terminal OUT is released as a pre-recorded area detecting signal G. The pre-recorded area detecting signal G is also entered to one of the input terminals of an AND circuit 28. Further, clock pulses having a frequency f c are entered to the other of the input terminals of the AND circuit 28, and an output signal of the AND circuit 28 is entered to a clock terminal CK of the modulo-N divider 27. In that case, the equation is also expressed as: τ = N x (1 / f c ) As shown in Fig. 1(a) to (c), there exist a group of pulses derived from the marks 15 formed in pits in a reproduced analog signal K from the pre-format section 13 on the magneto-optical disk 10. The group of pulses are converted to binary coded signals in the waveform shaping circuit 22, which form a reproduced digital signal L. As a method for converting them to binary coded signals, amplitude detection, peak detection or other method is used. In the pre-recorded area detection circuit 24, when a pulse is entered in the reproduced digital signal L, the period of time τ for which the pre-recorded area detecting signal G is kept "High" is predeterminately set so as to be more than a maximum pulse period T max in the group of pulses in the reproduced digital signal L. As a result, the pre-recorded area detecting signal G as an output signal of the pre-recorded area detection circuit 24 has a form shown in Fig. 1(c), forming a signal having a portion thereof substantially equal to the pre-format section 13 having a group of pulses in the reproduced analog signal K. The following description will discuss a detailed example of an arrangement of the information reproducing circuit 17 referring to Fig. 9. The reproduced analog signal K reproduced from the magneto-optical disk 10 is entered to a buffer amplifier 30 in the information reproducing circuit 17. A reproduced analog signal K′ amplified by the buffer amplifier 30 is entered to both a magneto-optical signal waveform processing section 31 and a pre-format waveform processing section 32. The magneto-optical signal waveform processing section 31 and the pre-format waveform processing section 32 are respectively designed by the use of the aforementioned waveform shaping circuit 22 (see Fig. 5). From the magneto-optical signal waveform processing section 31 and the pre-format waveform processing section 32, are respectively released reproduced digital signals L1 and L2 as binary coded signals, which correspond to marks 16, 15 and non-marks in between in the respective magneto-optical signal section 14 and pre-format section 13. The reproduced digital signals L1, L2 are entered to a data synchronization section 33, where according to a PLL (Phase Locked Loop) therein, synchronous data M synchronizing to clock pulses is released and sent to a demodulation circuit, which is not shown in figures. Moreover, a sector mark signal F is generated according to the sector mark section 13a in the pre-format waveform processing section 32, and is sent to the sector timing detection circuit 18 (see Fig. 4). A signal processing control section 34 is designed to release various control and timing signals N, O, P, Q to the buffer amplifier 30, magneto-optical signal waveform processing section 31, pre-format waveform processing section 32, data synchronization section 33, or other section. Moreover, the signal processing control section 34 includes therein the aforementioned pre-recorded area detection circuit 24 (see Fig. 5), and is designed to release the pre-recorded area detecting signal G according to the reproduced digital signals L from the data synchronization section 33. Further, a reproduction timing signal I is entered to the signal processing control section 34. Next, the following description will discuss a detailed example of an arrangement of the sector timing detection circuit 18 referring to Figs. 10 to 17. In Fig. 10, the sector mark signal F released from the information reproducing circuit 17 is entered to a sector mark detection circuit 35 in the sector timing detection circuit 18. Detection of the sector mark section 13a is performed in the sector mark detection circuit 35. More specifically, as shown in Fig. 11, the sector mark detection circuit 35 comprises a counter circuit 36 having counters No. 1 to No. 9 and a judgement circuit 37, and the sector mark signal F released from the information reproducing circuit 17 is entered to counters No. 1 to No. 9. Output signals V1 to V9 of those counters No. 1 to No. 9 are respectively entered to the judgement circuit 37, and according to those signals, a sector mark detecting signal R is released from the judgement circuit 37. Fig. 12 is a diagram describing the operation of the counters No. 1 to No. 9. As shown in Fig. 12(b), there are recorded marks 15 (shown in hatching for convenience) and non-marks located in between in the sector mark section 13a, as aforementioned. In this example, as shown in Fig. 12(a), the marks 15 are physically provided so that a ratio of the mark lengths to the non-mark lengths can be expressed as 5:3:3:7:3:3:3:3:5. The sector mark signal F (Fig. 12(c)) obtained by the pattern of those marks and non-marks corresponds to, for example, "0" in the mark 15, and "1" in the non-mark. When the reproduced signal of these marks 15 and non-marks is entered to the counters No. 1 to No. 9, firstly a mark length of the leading mark 15 is counted by the counter No. 1 as shown in Fig. 12(e). When the counted number (Fig. 12(d)) is within a predetermined range corresponding to a mark length "5", the detection of the leading mark 15 is confirmed. Secondly, in the counter No. 2, the succeeding non-mark having a non-mark length "3" is detected in the same procedure. Then, the marks 15 and non-marks in the sector mark section 13a are successively detected by the counters No. 3 to No. 8, and lastly the last mark 15 having a mark length "5" is detected by the counter No. 9. Detecting signals V1 to V9 for those nine marks 15 and non-marks are entered to the judgement circuit 37. Then, it is judged whether those nine results of the detection conform to the pattern of the sector mark section 13a, and whether an order of each of those marks 15 and non-marks is properly followed. Consequently, only in the case where the length of each of those marks 15 and non-marks as well as the order thereof is appropriate, the sector mark detecting signal R becomes "Low", thereby showing that a sector mark has been detected. As shown in Fig. 10, the sector mark detecting signal R is entered to a counter 38, a timer circuit 40 and a judgement circuit 41 respectively. Output signals S and T of the counter 38 and the timer circuit 40 are respectively entered to a switching circuit 42, where either of the signals is selected according to a timing judgement signal H2 from the judgement circuit 41, which will be described later, and is released as a reference timing signal U. Further, the reference timing signal U is entered to a magneto-optical signal section judgement circuit 43 (recording signal section judgement circuit), a first magneto-optical signal section judgement signal H1 (recording signal section judgement signal) is released, as will be described in detail hereinafter. From the timer circuit 40, an output signal W is also entered to a window generation circuit 44 (which will be described in detail later). An output signal X from the window generation circuit 44 is entered to the judgement circuit 41. In the judgement circuit 41, according to the output signal X and the sector mark detecting signal R from the sector mark detection circuit 35, the timing judgement signal H2 is released, as will be described hereinafter, and the timing judgement signal H2 is sent to the switching circuit 42 and the timing control circuit 20. According to the reference timing signal U, the first magneto-optical signal section judgement signal H1 and the timing judgement signal H2, a recording/erasing timing signal J and a reproduction timing signal I, which are shown in Fig. 4, are released from the timing control circuit 20. Fig. 13 shows a waveform of each of those signals shown in Fig. 10. The sector mark detecting signal R (Fig. 13(b)) becomes "Low" when a sector mark section 13a of the pre-format section 13 is detected. A falling edge of the sector mark detecting signal R provides timing for synchronizing the sector 12. The counter 38 shown in Fig. 10 changes its output signal 5 (Fig. 13(c)) to "Low" upon reaching the predetermined count after the receipt of the rising edge. On the other hand, the timer circuit 40 is predeterminately set so as to have more count number for one sector in addition to the count number by the counter 38. Accordingly, a falling edge of an output signal T (Fig. 13(d)) of the timer circuit 40 is substantially synchronized with the falling edge of the output signal S of the counter 38 in the next sector 12. Moreover, based on the falling edge of the sector mark detecting signal R, an output signal X (Fig. 13(e)) of the window generation circuit 44 is predeterminately set to become "Low" with a predetermined window width at a vicinity of a falling edge of the sector mark detecting signal R in the next sector 12. The timing judgement signal H2 (Fig. 13(f)) released from the judgement circuit 41 is predeterminately set so that it may become "High" in the presence of a falling edge of the sector mark detecting signal R when the output signal X of the window generation circuit 44 is "Low", and on the other hand, may become "Low" in the absence of a falling edge of the sector mark detecting signal R when the output signal X of the window generation circuit 44 is "Low". Accordingly, the timing judgement signal H2 functions as a signal for judging whether the detection of a sector mark section 13a is executed within a predetermined range. In the switching circuit 42 shown in Fig. 10, the output signal S of the counter 38 is selected when a sector mark section 13a is detected, and on the other hand, the output signals T of the timer circuit 40 is selected if a sector mark section 13a is not detected. Accordingly, the reference timing signal U (Fig. 13 (g)) properly provides timing control for detecting a sector mark section 13a according to the output signal T from the timer circuit 40, even if an error occurs in detecting a sector mark section 13a. The magneto-optical signal section judgement circuit 43 to which the reference timing signal in is entered, is a sort of counters, and the first magneto-optical signal section judgement signal H1 thereof (Fig. 13(h)) becomes "Low" during the magneto-optical signal section 14. In other words, the first magneto-optical signal section judgement signal H1 is a signal for judging whether it is the magneto-optical signal section 14 or the pre-format section 13. The aforementioned reference timing signal U, timing judgement signal H2 and first magneto-optical signal section judgement signal H1 are sent to the timing control circuit 20. Next, the following description will discuss a detailed example of an arrangement of the timing control circuit 20. In Fig. 14, the pre-recorded area detecting signal G is entered to a first counter 45 in the timing control circuit 20. An output signal Y of the first counter 45 is entered to a second counter 46. An output signal of the second counter 46 becomes "Low" during the magneto-optical signal section 14, as will be described later, and the signal forms a second magneto-optical signal section judgement signal AA (a second recording signal section judgement signal). The second magneto-optical signal section judgement signal AA is entered to a switching circuit 47. To the switching circuit 47, the first magneto-optical signal section judgement signal H1 and the timing judgement signal H2 as the synchronization detection signals H are also entered, and according to the timing judgement signal H2, the first magneto-optical signal section judgement signal H1 and the second magneto-optical signal section judgement signal AA are interchangeably switched to form the reproduction timing signal I, which is released therefrom to be entered to the information reproducing circuit 17. As shown in Fig. 15(b), the pre-recorded area detecting signal G to be entered to the first counter 45 becomes "High" during the pre-format section 13, as aforementioned according to Fig. 1, and the rising edge is substantially synchronized with the start position of the pre-format section 13. It is predeterminately designed that when the pre-recorded area detecting signal G has been successively "High" for not less than a predetermined byte length (for example, seventeen bytes), the output signal Y of the first counter 45 changes from "Low" to "High", as shown in Fig. 15(c). In other words, in the first counter 45, judgement of whether it is a pre-format section 13 or not is made according to a byte length of the pre-recorded area detecting signal G. Based on a rising edge of the output signal Y of the first counter 45, the second counter 46 is operated as shown in Fig. 15(d). Further, it is predeterminately set that the second magneto-optical signal section judgement signal AA as an output signal from the second counter 46 changes from "High" to "Low" in the vicinity of a border between a pre-format section 13 and a magneto-optical signal section 14 (for example, at the gap section 14b in Fig. 15(a)). It is also predeterminately set that the second magneto-optical signal section judgement signal AA returns from "Low" to "High" again in the vicinity of the next border between the magneto-optical signal section 14 and a pre-format section 13 (for example, at the gap section 14c in the Fig. 15(a)). Therefore, the second magneto-optical signal section judgement signal AA functions as a timing signal which is formed according to the pre-recorded area detecting signal G. Additionally, in the timing control circuit 20, monostable multivibrators may be respectively used instead of the first and second counters 45, 46. A detailed example of an arrangement of the switching circuit 47 is shown in Fig. 16. The first magneto-optical signal section judgement signal (first recording signal section judgement signal) H1 as the synchronization detection signal H is entered to a clock input terminal CK of a flip-flop 50 (which is, for example, 74LS74 of U.S. Texas Instrument Co., Ltd.) through an inverter 48 (first inverter) in the switching circuit 47. On the other hand, the timing judgement signal H2, as it is, is entered to a data input terminal D of the flip-flop 50. An output signal BB from an output terminal Q (positive phase output terminal) is entered to both of terminals of a NAND circuit 51 (second inverter), while an output signal CC of an output terminal Q (negative phase output terminal) is entered to one of input terminals of a NAND circuit 52 (first NAND circuit). Furthermore, the second magneto-optical signal section judgement signal (second recording signal section judgement signal) AA is entered to the other of the input terminals of the NAND circuit 52. Output signals DD, EE from the respective NAND circuits 51, 52 are entered to a NAND circuit 53 (second NAND circuit), and an output signal of the NAND circuit 53 forms the reproduction timing signal I. Fig. 17 shows waveforms of the respective signals in Fig. 16. The first magneto-optical signal section judgement signal H1 (Fig. 17(c)) and the second magneto-optical signal section judgement signal AA (Fig. 17(e)) become "Low" during a magneto-optical section 14 (see Fig. 17(a)). Upon receiving the timing judgement signal H2 (Fig. 17(b)) at a falling edge of the first magneto-optical signal section judgement signal H1, the output signal BB (Fig. 17(d)) from the output terminal Q of the flip-flop 50 is obtained. When the output signal BB is "High" as shown in a solid line, detection of a sector mark section 13a is executed normally; however, when it is "Low" as shown in a dotted line, occurrence of an error is confirmed. Further, a circuit shown in Fig. 16 is designed so that as the reproduction timing signal I, the first magneto-optical signal section judgement signal H1 is released when the output signal BB from the output terminal Q of the flip-flop 50 is "High", while the second magneto-optical signal section judgement signal AA is released when the output signal BB is "Low". Accordingly, even if an error occurs in detecting sector mark sections 13a, timing control may be compensated based on the pre-recorded area detecting signal G. The reproduction timing signal I provides, for example, the following control operations. First, the reproduction timing signal I can be used for switching an input signal to the PLL of the data synchronization section 33 shown in Fig. 9. More specifically, in the case of using the magneto-optical disk 10, as shown in Fig. 9, it is necessary to properly switch between the reproduced signals L1 and L2 before being entered to the PLL in the data synchronization section 33, since the marks 15 and marks 16 in the reproduced analog signals K′ are separately processed in their waveforms in the respective pre-format waveform processing section 32 and magneto-optical signal waveform processing section 31. Secondly, the reproduction timing signal I can be used for judging whether signals of the magneto-optical signal section 14 are demodulated or those of address information of the pre-format section 13 are demodulated in a demodulating operation of a demodulation circuit, which is not shown in the figures, installed in a step after the data synchronization section 33. Lastly, in the case of occurrence of an error in reproduction, it is necessary to detect it and release the information about it, and therefore, the reproduction timing signal I is used for judging whether the error in reproduction has occurred in the magneto-optical signal section 14 or it has occurred in the pre-format section 13. In all those three examples, the reproduction timing signal I is used for judging whether the signals are from the magneto-optical signal section 14 or from the pre-format section 13. The pre-recorded area detecting signal G not only compensates the timing control which is operated by detecting the sector mark section 13a within the pre-format section 13 but also is utilized in the following cases. More specifically, the signal can be used as a reed gate signal for the PLL in the data synchronization section 33. Further, in order to provide timing control for AGC (Automatic Gain Control), the signal is used for turning on the AGC only in the areas having data recorded and for holding it in the other areas. Furthermore, the signal is used for detecting burst errors of recording signals. In all the above three examples, the pre-recorded area detecting signal G is used for judging whether an area has information recorded therein or not, in the magneto-optical signal section 14 or in the pre-format section 13. Accordingly, the pre-recorded area detecting signal G, which is used in the above cases, is applicable not only to the pre-format section 13 which is the pre-recorded section but also to the magneto-optical signal section 14 wherein information recording, reproducing and erasing operations are performed. The following description will discuss the second embodiment of the present invention referring to Figs. 18 to 20. The second embodiment deals with the case where a defect pulse such as shown by a dotted line s or t in Fig. 1(a) occurs at a section other than the pre-format section 13 in the magneto-optical disk 10, and gives proper measures to prevent occurrence of an error in information reproduction due to malfunction that the pre-recorded area detecting signal G becomes "High" erroneously, as shown by a dotted line u or v in Fig. 1(c), according to the defect pulse. More specifically, the pre-recorded area detection circuit 24 included in the information reproducing circuit 17 comprises a re-triggerable pulse generation circuit 54 and a leading pulse removing circuit 55, as shown in Fig. 18. The leading pulse removing circuit 55 functions as a circuit for nullifying the output of the re-triggerable pulse generation circuit 54 for one or more leading pulses the number of which is given by integer M in the reproduced digital signal L. A concrete example of an arrangement of the leading pulse removing circuit 55 is shown in Fig. 19. Here, a modulo-M counter 56 is disposed as the leading pulse removing circuit 55 in a step before the re-triggerable pulse generation circuit 54, and the modulo-M counter 56 removes the leading pulses the number of which is given by integer M from the reproduced digital signal L. Additionally, instead of the modulo-M counter 56, M-shift register may be used. Fig. 20 shows another example of the arrangement of the leading pulse removing circuit 55, where a shift register 57 is disposed as the leading pulse removing circuit 55 at a step after the re-triggerable pulse generation circuit 54, and an output of the pulse generation circuit 54 is entered to a clear terminal CL of the shift register 57, while the reproduced digital signal L is entered to a clock terminal CK of the sift register 57, thereby releasing an M-th shifted output QM as a pre-recorded area detecting signal G′. The following description will discuss, for example, timing control of a case where M = 1, that is to say, the output of the re-triggerable pulse generation circuit 55 is nullified only for one leading pulse of the reproduced digital signal L. As shown in Fig. 1(a), if there is only one defect pulse within an un-recorded area of information, the defect pulse is nullified by the leading pulse removing circuit 55, and therefore there occurs no such case wherein the pre-recorded area detecting signal G′ becomes "High" due to the defect pulse, as shown in Fig. 1(d). Moreover, in the pre-format section 13, the timing of the pre-recorded area detecting signal G′ to be "High" delays only by one pulse; however, for example, reed gate timing for the PLL is not affected by the delay of such a few pulses. Thus, reliability for the action of the PLL is not adversely affected. In addition, in the above embodiment, a device is taken as an example, wherein information recording, reproducing and erasing operations are performed on and from the magneto-optical disk 10; however, the present invention is applicable to other devices for only reproducing from various optical memory devices or to those of DRAW (Direct Read After Write) type. Further, the present invention is applicable to information recording and reproducing devices wherein magnetic memory devices having a group of information pulses for indicating recorded areas are used as well as those devices wherein optical memory devices are used. As aforementioned, the information recording and reproducing device of the present invention, which records and reproduces information on and from an optical memory device, comprises a pre-recorded area detection circuit for detecting a pre-recorded area having information predeterminately recorded and located on the memory device, and timing control means for providing timing control of an information recording or reproducing operation according to a pre-recorded area detecting signal released from the pre-recorded area detection circuit. With the arrangement, since the timing control of information recording, reproducing and erasing operations is provided according to the pre-recorded area detecting signal, timing of recording, reproducing, or erasing operation is accurately determined. Additionally, the timing control may be performed according to both of the pre-recorded area detecting signal of the present invention and the conventional synchronization detection signal. In that case, if an error should occur in the synchronization detection signal, since the pre-recorded area detecting signal is released every time pre-recorded information for a sector mark or the like is reproduced, an accurate timing control without time lag is achieved according to the pre-recorded area detecting signals.

Claims: An information and/or reproducing device for recording and/or reproducing information to and/or from a memory device (10) having pre-recorded areas (13) including a sector mark section (13a), comprising: sector timing detection means (18) for generating a sector timing detection signal (H) upon detecting a sector mark section (13a); and timing control means (20) for-controlling the timing of an information recording or reproducing operation according to said sector timing detection signal (H), characterised by pre-recorded area detection means (24) for generating a pre-recorded area detection signal (G) upon detecting a said pre-recorded area (13), in that said timing control means (20) is arranged to output a timing signal (I) for the control of the timing of the information recording or reproducing operation according to said pre-recorded area detection signal (G), and in that said timing control means comprises: (a) a counter circuit (45,46) for generating a further timing signal (AA) in accordance with said prerecorded area detection signal (G); and (b) a switching circuit (47), to which the sector timing detection signal (H) and the further timing signal (AA) are inputted, for outputing said timing signal (I) on the basis of the further timing signal (AA) when the sector timing detection signal (H) has an error, while outputting the timing signal (I) based on the sector timing detection signal (H) when the sector timing detection signal (H) has no error. A device as claimed in claim 1 further comprising: information reproducing means (17), information recording/erasing means (21) and sector timing detection means (18); the information reproducing means (17) being arranged to reproduce recorded information (14) and sector mark sections (13) according to said timing signal (I) released from the timing control means (20) to obtain a reproduced analog signal (K), and to generate and release therefrom said pre-recorded area detecting signal (G;G′) and a sector mark signal (F) according to the reproduced analog signal (K); the information/recording means (21) being arranged to perform an information recording or erasing operation according to a recording/erasing timing signal (J) from the timing control means (20); the sector timing detection means (18) being arranged to generate said sector timing detection signal (H) according to the sector mark signal (F); and the timing control means (20) being arranged to release, as said timing signal (I), a reproduction timing signal (I) and a recording/erasing signal (J) according to the sector timing detection signal (H) and pre-recorded area detecting signal (G;G′). An information recording and reproducing device as set forth in claim 2, wherein the information reproducing means (17) comprises: a waveform shaping circuit (22) for shaping a waveform of the reproduced analog signal (K) to convert to a binary coded reproduced digital signal (L); and a pre-recorded area detection circuit (23) for releasing the pre-recorded area detecting signal (G;G′) for a predetermined period of time in the case where pulses exist in an output (L) from the waveform shaping circuit (22). An information recording and reproducing device as set forth in claim 3, wherein the pre-recorded information area detection circuit (24) comprises a re-triggerable pulse generation circuit (23;54). An information recording and reproducing device as set forth in claim 4, wherein the re-triggerable pulse generation circuit (23;54) comprises a re-triggerable monostable multivibrator (25) provided with resistors (R) and capacitors (C) for determining a time constant thereof so as to detect whether a detected area is a pre-recorded area (13) or not according to the output thereof. An information recording and reproducing device as set forth in claim 4, wherein the re-triggerable pulse generation circuit (23;54) is a shift register (26). An information recording and reproducing device as set forth in claim 4, wherein the re-triggerable pulse generation circuit (23;54) comprises: a divider (27) having a clear input terminal (CL), a clock input terminal (CK) and an output terminal (OUT) which has the reproduced digital signal (L) entered thereto through the clear input terminal (CL) thereof; and an AND circuit (28) having one of its input terminals connected to the output terminal of the divider (27), the other of its input terminals connected to a reference clock signal (fc) for dividing operation and its output connected to the clock input terminal (CK). An information recording and reproducing device as set forth in any one of claims 2 to 7, wherein the information reproducing means (17) comprises: a pre-recorded area waveform processing section (32) for releasing a first reproduced digital signal (L2) corresponding to the pre-recorded areas (13) section and generating the sector mark signal (F); a recording signal waveform processing section (31) for releasing a second reproduced digital signal (L₁) corresponding to a recorded signal; a data synchronization section (33) having a PLL circuit whereby the section is arranged to release synchronous data synchronized to a reference clock, according to the first and second reproduced digital signals (L₁,L₂) from the respective waveform processing sections (31,32); and a signal processing control section (34) having a pre-recorded area detection circuit, for permitting the pre-recorded area detection circuit to release said prerecorded area detecting signal (G) and for releasing timing signals for each of the sections (N;O,P,Q); thereby releasing either the first reproduced digital signal (L₁) or the second reproduced digital (L₂) to the data synchronization section (33) according to the timing signals (N;O,P,Q). An information recording and reproducing device as set forth in any one of the preceding claims, wherein the sector timing detection means (17,18) comprises: a sector mark detection circuit (35) for releasing a sector mark detection signal (R) according to the sector mark signal (F); a counter (38) for releasing a negative pulse signal (S) after having reached a predetermined count number from a falling edge of the sector mark detection signal (R); a timer circuit (40) for releasing a negative pulse signal (T) after having reached a count number corresponding to one sector portion in addition to the count number by the counter (38); a window generation circuit (44) for releasing a negative pulse signal (X) having a predetermined window width in the vicinity of a falling edge of the next sector mark detection signal (R) based on a falling edge of a preceding sector mark detecting signal (R); a judgement circuit (41) for releasing a binary timing judgement signal (H₂) of a "High" level when a falling edge of the sector mark detection signal (R) is detected during a negative-pulse period of the output (X) of the window generation circuit (44) and for releasing the signal of a "Low" level when a falling edge of the sector mark detection signal (R) is not detected during the same condition; a switching circuit (42) for selecting an output (S) of the counter (38) as a reference timing signal (U) when the timing judgement signal (H₂) is in the "High" level and for selecting an output (T) of the timer circuit (40) as the same when the timing judgement signal (H₂) is the "Low" level; and a recording signal section judgement circuit (43) for releasing a first recording signal section judgement signal (H₁) as a negative pulse signal during a period corresponding to a recorded section (13) within one sector according to the reference timing signal (U); thereby permitting the reference timing signal (U), timing judgement signal (H₂), and recording signal section judgement signal (H₁) to be sent to the timing control means (20). An information recording and reproducing device as set forth in claim 9, wherein the sector mark detection circuit (35) comprises: a plurality of counters (36) for successively counting count numbers, each directly proportional to each length of marks and non-marks according to the sector mark signal (F) and releasing the results as a detecting signal (V₁-V₉); and a judgement circuit (37) for judging whether the detecting signal coincides with each predetermined length of marks and non-marks in the sector mark section (13a), and whether the order thereof is properly followed. An information recording and reproducing device as set forth in claim 9, wherein the counter circuit (45,46) comprises: a first counter (45) for releasing a positive pulse (Y) by counting a period during which the pre-recorded area detecting signal (G;G′) is in the "High" level and by regarding it as reproducing a pre-format section if the period continues for not less than a predetermined period; and a second counter (46) for starting a counting operation synchronizing to a rising edge of the positive pulse (Y) of the first counter (45) and for releasing, as said further timing signal (AA), a second recording signal section judgement signal (AA) which falls to a "Low" level in the vicinity of a border between a pre-format section (13) and a recording signal section (14), and rises to a "High" level in the vicinity of the next border between a recording signal section (14) and a pre-format section (13); and wherein said switching circuit (47) is operable for interchangeably switching between the second recording signal section judgement signal (AA) from the second counter (46) and the first recording signal section judgement signal (H₁) from the recording signal section judgement circuit (43) and releasing it as a reproduction timing signal (I). An information recording and reproducing device as set forth in claim 11, wherein the switching circuit (47) comprises: a D-type flip-flop (50) including a data input terminal (D), a clock input terminal (CK) a positive phase output terminal (Q) and a negative phase output terminal ( Q ) having the timing judgement signal (H₂) entered to the data input terminal (D) thereof; a first inverter (48) for reversing a polarity of the first recording signal section judgement signal (H₁), and for releasing it to the clock input terminal (CK) of the D-type flip-flop (50); a second inverter (51) for reversing a polarity of a signal released from the positive phase output terminal (Q) of the D-type flip-flop (50); a first NAND circuit (52) whereto a signal from the negative phase output terminal (Q) of the D-type flip-flop (50) and the second recording signal section judgement signal (AA) from the second counter (46) are entered; and a second NAND circuit (53) whereto the outputs of the second inverter (51) and the first NAND circuit (52) are entered to execute NAND operations and for releasing the reproduction timing signal (I); thereby permitting the first recording signal section judgement signal (H₁) to be released as the reproduction timing signal (I) when the signal from the positive phase output terminal (Q) of the D-type flip-flop is in a "High" level; and on the other hand, permitting the second recording signal section judgement signal (AA) to be released as the reproduction timing signal (I) when the signal from the positive phase output (Q) terminal of the D-type flip-flop (50) is in a "Low" level. An information recording and reproducing device as set forth in any one of claims 4 to 6, wherein the prerecorded area detection circuit (24) further comprises: a leading pulse removing circuit (55) for nullifying an output of the re-triggerable pulse generation circuit (54) with respect to a predetermined number of leading pulses in the reproduced digital signal (L); thereby permitting the pre-recorded area detection signal (G′) to be detected accurately even if there is contained at least one defect pulse in the reproduced digital signal. An information recording and reproducing device as set forth in claim 13, wherein the leading pulse removing circuit (55) comprises a modulo-N counter (56) for nullifying the output of the re-triggerable pulse generation circuit (54) with respect to leading pulses the number of which is given by N in the reproduced digital signal (L). An information recording and reproducing device as set forth in claim 13, wherein the leading pulse removing circuit (55) is a shift register (57). An information recording and reproducing device as set forth in any one of claims 4 to 6, wherein the prerecorded area detection circuit (24) further comprises: a shift register (57) having a clear input terminal (CL), a clock input terminal (CK), a data input terminal (IN) and an output terminal (QM), and having an output of the re-triggerable pulse generation circuit (54) entered to the clear input terminal ( CL ) thereof, the reproduced digital signal (L) entered to the clock input terminal (CK) thereof, and high levels of the reproduced signal constantly entered to the data input terminal (IN) thereof; thereby permitting the pre-recorded area detecting signal (G′) to be released from the output terminal (QM).

Inventors: DEGUCHI TOSHIHISA, FUJI HIROSHI, YAMAGUCHI TAKESHI, DEGUCHI, TOSHIHISA, FUJI, HIROSHI, YAMAGUCHI, TAKESHI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1990
Main classification: G11B27
IPC codes: G11B11, G11B20, G11B27, G11B7